[mirror_ubuntu-jammy-kernel.git] / include / linux / lightnvm.h

/* SPDX-License-Identifier: GPL-2.0 */
#ifndef NVM_H
#define NVM_H

#include <linux/blkdev.h>
#include <linux/types.h>
#include <uapi/linux/lightnvm.h>

enum {
	NVM_IO_OK = 0,
	NVM_IO_REQUEUE = 1,
	NVM_IO_DONE = 2,
	NVM_IO_ERR = 3,

	NVM_IOTYPE_NONE = 0,
	NVM_IOTYPE_GC = 1,
};

#define NVM_BLK_BITS (16)
#define NVM_PG_BITS  (16)
#define NVM_SEC_BITS (8)
#define NVM_PL_BITS  (8)
#define NVM_LUN_BITS (8)
#define NVM_CH_BITS  (7)

enum {
	NVM_OCSSD_SPEC_12 = 12,
	NVM_OCSSD_SPEC_20 = 20,
};

struct ppa_addr {
	/* Generic structure for all addresses */
	union {
		struct {
			u64 blk		: NVM_BLK_BITS;
			u64 pg		: NVM_PG_BITS;
			u64 sec		: NVM_SEC_BITS;
			u64 pl		: NVM_PL_BITS;
			u64 lun		: NVM_LUN_BITS;
			u64 ch		: NVM_CH_BITS;
			u64 reserved	: 1;
		} g;

		struct {
			u64 line	: 63;
			u64 is_cached	: 1;
		} c;

		u64 ppa;
	};
};

struct nvm_rq;
struct nvm_id;
struct nvm_dev;
struct nvm_tgt_dev;

typedef int (nvm_id_fn)(struct nvm_dev *);
typedef int (nvm_op_bb_tbl_fn)(struct nvm_dev *, struct ppa_addr, u8 *);
typedef int (nvm_op_set_bb_fn)(struct nvm_dev *, struct ppa_addr *, int, int);
typedef int (nvm_submit_io_fn)(struct nvm_dev *, struct nvm_rq *);
typedef int (nvm_submit_io_sync_fn)(struct nvm_dev *, struct nvm_rq *);
typedef void *(nvm_create_dma_pool_fn)(struct nvm_dev *, char *);
typedef void (nvm_destroy_dma_pool_fn)(void *);
typedef void *(nvm_dev_dma_alloc_fn)(struct nvm_dev *, void *, gfp_t,
								dma_addr_t *);
typedef void (nvm_dev_dma_free_fn)(void *, void*, dma_addr_t);

struct nvm_dev_ops {
	nvm_id_fn		*identity;
	nvm_op_bb_tbl_fn	*get_bb_tbl;
	nvm_op_set_bb_fn	*set_bb_tbl;

	nvm_submit_io_fn	*submit_io;
	nvm_submit_io_sync_fn	*submit_io_sync;

	nvm_create_dma_pool_fn	*create_dma_pool;
	nvm_destroy_dma_pool_fn	*destroy_dma_pool;
	nvm_dev_dma_alloc_fn	*dev_dma_alloc;
	nvm_dev_dma_free_fn	*dev_dma_free;
};

#ifdef CONFIG_NVM

#include <linux/blkdev.h>
#include <linux/file.h>
#include <linux/dmapool.h>
#include <uapi/linux/lightnvm.h>

enum {
	/* HW Responsibilities */
	NVM_RSP_L2P	= 1 << 0,
	NVM_RSP_ECC	= 1 << 1,

	/* Physical Adressing Mode */
	NVM_ADDRMODE_LINEAR	= 0,
	NVM_ADDRMODE_CHANNEL	= 1,

	/* Plane programming mode for LUN */
	NVM_PLANE_SINGLE	= 1,
	NVM_PLANE_DOUBLE	= 2,
	NVM_PLANE_QUAD		= 4,

	/* Status codes */
	NVM_RSP_SUCCESS		= 0x0,
	NVM_RSP_NOT_CHANGEABLE	= 0x1,
	NVM_RSP_ERR_FAILWRITE	= 0x40ff,
	NVM_RSP_ERR_EMPTYPAGE	= 0x42ff,
	NVM_RSP_ERR_FAILECC	= 0x4281,
	NVM_RSP_ERR_FAILCRC	= 0x4004,
	NVM_RSP_WARN_HIGHECC	= 0x4700,

	/* Device opcodes */
	NVM_OP_PWRITE		= 0x91,
	NVM_OP_PREAD		= 0x92,
	NVM_OP_ERASE		= 0x90,

	/* PPA Command Flags */
	NVM_IO_SNGL_ACCESS	= 0x0,
	NVM_IO_DUAL_ACCESS	= 0x1,
	NVM_IO_QUAD_ACCESS	= 0x2,

	/* NAND Access Modes */
	NVM_IO_SUSPEND		= 0x80,
	NVM_IO_SLC_MODE		= 0x100,
	NVM_IO_SCRAMBLE_ENABLE	= 0x200,

	/* Block Types */
	NVM_BLK_T_FREE		= 0x0,
	NVM_BLK_T_BAD		= 0x1,
	NVM_BLK_T_GRWN_BAD	= 0x2,
	NVM_BLK_T_DEV		= 0x4,
	NVM_BLK_T_HOST		= 0x8,

	/* Memory capabilities */
	NVM_ID_CAP_SLC		= 0x1,
	NVM_ID_CAP_CMD_SUSPEND	= 0x2,
	NVM_ID_CAP_SCRAMBLE	= 0x4,
	NVM_ID_CAP_ENCRYPT	= 0x8,

	/* Memory types */
	NVM_ID_FMTYPE_SLC	= 0,
	NVM_ID_FMTYPE_MLC	= 1,

	/* Device capabilities */
	NVM_ID_DCAP_BBLKMGMT	= 0x1,
	NVM_UD_DCAP_ECC		= 0x2,
};

struct nvm_id_lp_mlc {
	u16	num_pairs;
	u8	pairs[886];
};

struct nvm_id_lp_tbl {
	__u8	id[8];
	struct nvm_id_lp_mlc mlc;
};

struct nvm_addrf_12 {
	u8	ch_len;
	u8	lun_len;
	u8	blk_len;
	u8	pg_len;
	u8	pln_len;
	u8	sect_len;

	u8	ch_offset;
	u8	lun_offset;
	u8	blk_offset;
	u8	pg_offset;
	u8	pln_offset;
	u8	sect_offset;

	u64	ch_mask;
	u64	lun_mask;
	u64	blk_mask;
	u64	pg_mask;
	u64	pln_mask;
	u64	sec_mask;
};

struct nvm_addrf {
	u8	ch_len;
	u8	lun_len;
	u8	chk_len;
	u8	sec_len;
	u8	rsv_len[2];

	u8	ch_offset;
	u8	lun_offset;
	u8	chk_offset;
	u8	sec_offset;
	u8	rsv_off[2];

	u64	ch_mask;
	u64	lun_mask;
	u64	chk_mask;
	u64	sec_mask;
	u64	rsv_mask[2];
};

struct nvm_target {
	struct list_head list;
	struct nvm_tgt_dev *dev;
	struct nvm_tgt_type *type;
	struct gendisk *disk;
};

#define ADDR_EMPTY (~0ULL)

#define NVM_TARGET_DEFAULT_OP (101)
#define NVM_TARGET_MIN_OP (3)
#define NVM_TARGET_MAX_OP (80)

#define NVM_VERSION_MAJOR 1
#define NVM_VERSION_MINOR 0
#define NVM_VERSION_PATCH 0

#define NVM_MAX_VLBA (64) /* max logical blocks in a vector command */

struct nvm_rq;
typedef void (nvm_end_io_fn)(struct nvm_rq *);

struct nvm_rq {
	struct nvm_tgt_dev *dev;

	struct bio *bio;

	union {
		struct ppa_addr ppa_addr;
		dma_addr_t dma_ppa_list;
	};

	struct ppa_addr *ppa_list;

	void *meta_list;
	dma_addr_t dma_meta_list;

	nvm_end_io_fn *end_io;

	uint8_t opcode;
	uint16_t nr_ppas;
	uint16_t flags;

	u64 ppa_status; /* ppa media status */
	int error;

	void *private;
};

static inline struct nvm_rq *nvm_rq_from_pdu(void *pdu)
{
	return pdu - sizeof(struct nvm_rq);
}

static inline void *nvm_rq_to_pdu(struct nvm_rq *rqdata)
{
	return rqdata + 1;
}

enum {
	NVM_BLK_ST_FREE =	0x1,	/* Free block */
	NVM_BLK_ST_TGT =	0x2,	/* Block in use by target */
	NVM_BLK_ST_BAD =	0x8,	/* Bad block */
};

/* Instance geometry */
struct nvm_geo {
	/* device reported version */
	u8	major_ver_id;
	u8	minor_ver_id;

	/* kernel short version */
	u8	version;

	/* instance specific geometry */
	int nr_chnls;
	int nr_luns;		/* per channel */

	/* calculated values */
	int all_luns;		/* across channels */
	int all_chunks;		/* across channels */

	int op;			/* over-provision in instance */

	sector_t total_secs;	/* across channels */

	/* chunk geometry */
	u32	nr_chks;	/* chunks per lun */
	u32	clba;		/* sectors per chunk */
	u16	csecs;		/* sector size */
	u16	sos;		/* out-of-band area size */

	/* device write constrains */
	u32	ws_min;		/* minimum write size */
	u32	ws_opt;		/* optimal write size */
	u32	mw_cunits;	/* distance required for successful read */

	/* device capabilities */
	u32	mccap;

	/* device timings */
	u32	trdt;		/* Avg. Tread (ns) */
	u32	trdm;		/* Max Tread (ns) */
	u32	tprt;		/* Avg. Tprog (ns) */
	u32	tprm;		/* Max Tprog (ns) */
	u32	tbet;		/* Avg. Terase (ns) */
	u32	tbem;		/* Max Terase (ns) */

	/* generic address format */
	struct nvm_addrf addrf;

	/* 1.2 compatibility */
	u8	vmnt;
	u32	cap;
	u32	dom;

	u8	mtype;
	u8	fmtype;

	u16	cpar;
	u32	mpos;

	u8	num_pln;
	u8	plane_mode;
	u16	num_pg;
	u16	fpg_sz;
};

/* sub-device structure */
struct nvm_tgt_dev {
	/* Device information */
	struct nvm_geo geo;

	/* Base ppas for target LUNs */
	struct ppa_addr *luns;

	struct request_queue *q;

	struct nvm_dev *parent;
	void *map;
};

struct nvm_dev {
	struct nvm_dev_ops *ops;

	struct list_head devices;

	/* Device information */
	struct nvm_geo geo;

	unsigned long *lun_map;
	void *dma_pool;

	/* Backend device */
	struct request_queue *q;
	char name[DISK_NAME_LEN];
	void *private_data;

	void *rmap;

	struct mutex mlock;
	spinlock_t lock;

	/* target management */
	struct list_head area_list;
	struct list_head targets;
};

static inline struct ppa_addr generic_to_dev_addr(struct nvm_tgt_dev *tgt_dev,
						  struct ppa_addr r)
{
	struct nvm_geo *geo = &tgt_dev->geo;
	struct nvm_addrf_12 *ppaf = (struct nvm_addrf_12 *)&geo->addrf;
	struct ppa_addr l;

	l.ppa = ((u64)r.g.ch) << ppaf->ch_offset;
	l.ppa |= ((u64)r.g.lun) << ppaf->lun_offset;
	l.ppa |= ((u64)r.g.blk) << ppaf->blk_offset;
	l.ppa |= ((u64)r.g.pg) << ppaf->pg_offset;
	l.ppa |= ((u64)r.g.pl) << ppaf->pln_offset;
	l.ppa |= ((u64)r.g.sec) << ppaf->sect_offset;

	return l;
}

static inline struct ppa_addr dev_to_generic_addr(struct nvm_tgt_dev *tgt_dev,
						  struct ppa_addr r)
{
	struct nvm_geo *geo = &tgt_dev->geo;
	struct nvm_addrf_12 *ppaf = (struct nvm_addrf_12 *)&geo->addrf;
	struct ppa_addr l;

	l.ppa = 0;

	l.g.ch = (r.ppa & ppaf->ch_mask) >> ppaf->ch_offset;
	l.g.lun = (r.ppa & ppaf->lun_mask) >> ppaf->lun_offset;
	l.g.blk = (r.ppa & ppaf->blk_mask) >> ppaf->blk_offset;
	l.g.pg = (r.ppa & ppaf->pg_mask) >> ppaf->pg_offset;
	l.g.pl = (r.ppa & ppaf->pln_mask) >> ppaf->pln_offset;
	l.g.sec = (r.ppa & ppaf->sec_mask) >> ppaf->sect_offset;

	return l;
}

typedef blk_qc_t (nvm_tgt_make_rq_fn)(struct request_queue *, struct bio *);
typedef sector_t (nvm_tgt_capacity_fn)(void *);
typedef void *(nvm_tgt_init_fn)(struct nvm_tgt_dev *, struct gendisk *,
				int flags);
typedef void (nvm_tgt_exit_fn)(void *);
typedef int (nvm_tgt_sysfs_init_fn)(struct gendisk *);
typedef void (nvm_tgt_sysfs_exit_fn)(struct gendisk *);

struct nvm_tgt_type {
	const char *name;
	unsigned int version[3];

	/* target entry points */
	nvm_tgt_make_rq_fn *make_rq;
	nvm_tgt_capacity_fn *capacity;

	/* module-specific init/teardown */
	nvm_tgt_init_fn *init;
	nvm_tgt_exit_fn *exit;

	/* sysfs */
	nvm_tgt_sysfs_init_fn *sysfs_init;
	nvm_tgt_sysfs_exit_fn *sysfs_exit;

	/* For internal use */
	struct list_head list;
	struct module *owner;
};

extern int nvm_register_tgt_type(struct nvm_tgt_type *);
extern void nvm_unregister_tgt_type(struct nvm_tgt_type *);

extern void *nvm_dev_dma_alloc(struct nvm_dev *, gfp_t, dma_addr_t *);
extern void nvm_dev_dma_free(struct nvm_dev *, void *, dma_addr_t);

extern struct nvm_dev *nvm_alloc_dev(int);
extern int nvm_register(struct nvm_dev *);
extern void nvm_unregister(struct nvm_dev *);

extern int nvm_set_tgt_bb_tbl(struct nvm_tgt_dev *, struct ppa_addr *,
			      int, int);
extern int nvm_submit_io(struct nvm_tgt_dev *, struct nvm_rq *);
extern int nvm_submit_io_sync(struct nvm_tgt_dev *, struct nvm_rq *);
extern void nvm_end_io(struct nvm_rq *);
extern int nvm_bb_tbl_fold(struct nvm_dev *, u8 *, int);
extern int nvm_get_tgt_bb_tbl(struct nvm_tgt_dev *, struct ppa_addr, u8 *);

#else /* CONFIG_NVM */
struct nvm_dev_ops;

static inline struct nvm_dev *nvm_alloc_dev(int node)
{
	return ERR_PTR(-EINVAL);
}
static inline int nvm_register(struct nvm_dev *dev)
{
	return -EINVAL;
}
static inline void nvm_unregister(struct nvm_dev *dev) {}
#endif /* CONFIG_NVM */
#endif /* LIGHTNVM.H */
Commit	Line	Data
b2441318	1	/* SPDX-License-Identifier: GPL-2.0 */
cd9e9808 MB	2	#ifndef NVM_H
	3	#define NVM_H
	4
b76eb20b	5	#include <linux/blkdev.h>
a7fd9a4f	6	#include <linux/types.h>
b76eb20b	7	#include <uapi/linux/lightnvm.h>
a7fd9a4f	8
cd9e9808 MB	9	enum {
	10	NVM_IO_OK = 0,
	11	NVM_IO_REQUEUE = 1,
	12	NVM_IO_DONE = 2,
	13	NVM_IO_ERR = 3,
	14
	15	NVM_IOTYPE_NONE = 0,
	16	NVM_IOTYPE_GC = 1,
	17	};
	18
a7fd9a4f JA	19	#define NVM_BLK_BITS (16)
	20	#define NVM_PG_BITS (16)
	21	#define NVM_SEC_BITS (8)
	22	#define NVM_PL_BITS (8)
	23	#define NVM_LUN_BITS (8)
df414b33	24	#define NVM_CH_BITS (7)
a7fd9a4f	25
f1d4e812 JG	26	enum {
	27	NVM_OCSSD_SPEC_12 = 12,
	28	NVM_OCSSD_SPEC_20 = 20,
	29	};
	30
a7fd9a4f JA	31	struct ppa_addr {
	32	/* Generic structure for all addresses */
	33	union {
	34	struct {
	35	u64 blk : NVM_BLK_BITS;
	36	u64 pg : NVM_PG_BITS;
	37	u64 sec : NVM_SEC_BITS;
	38	u64 pl : NVM_PL_BITS;
	39	u64 lun : NVM_LUN_BITS;
	40	u64 ch : NVM_CH_BITS;
df414b33	41	u64 reserved : 1;
a7fd9a4f JA	42	} g;
a7fd9a4f JA	43
df414b33 MB	44	struct {
	45	u64 line : 63;
	46	u64 is_cached : 1;
	47	} c;
	48
a7fd9a4f JA	49	u64 ppa;
	50	};
	51	};
	52
	53	struct nvm_rq;
	54	struct nvm_id;
	55	struct nvm_dev;
8e53624d	56	struct nvm_tgt_dev;
a7fd9a4f	57
e46f4e48	58	typedef int (nvm_id_fn)(struct nvm_dev *);
e11903f5	59	typedef int (nvm_op_bb_tbl_fn)(struct nvm_dev , struct ppa_addr, u8 );
00ee6cc3	60	typedef int (nvm_op_set_bb_fn)(struct nvm_dev , struct ppa_addr , int, int);
a7fd9a4f	61	typedef int (nvm_submit_io_fn)(struct nvm_dev , struct nvm_rq );
1a94b2d4	62	typedef int (nvm_submit_io_sync_fn)(struct nvm_dev , struct nvm_rq );
a7fd9a4f JA	63	typedef void (nvm_create_dma_pool_fn)(struct nvm_dev , char *);
	64	typedef void (nvm_destroy_dma_pool_fn)(void *);
	65	typedef void (nvm_dev_dma_alloc_fn)(struct nvm_dev , void *, gfp_t,
	66	dma_addr_t *);
	67	typedef void (nvm_dev_dma_free_fn)(void , void, dma_addr_t);
	68
	69	struct nvm_dev_ops {
	70	nvm_id_fn *identity;
a7fd9a4f JA	71	nvm_op_bb_tbl_fn *get_bb_tbl;
	72	nvm_op_set_bb_fn *set_bb_tbl;
	73
	74	nvm_submit_io_fn *submit_io;
1a94b2d4	75	nvm_submit_io_sync_fn *submit_io_sync;
a7fd9a4f JA	76
	77	nvm_create_dma_pool_fn *create_dma_pool;
	78	nvm_destroy_dma_pool_fn *destroy_dma_pool;
	79	nvm_dev_dma_alloc_fn *dev_dma_alloc;
	80	nvm_dev_dma_free_fn *dev_dma_free;
a7fd9a4f JA	81	};
a7fd9a4f JA	82
cd9e9808 MB	83	#ifdef CONFIG_NVM
	84
	85	#include <linux/blkdev.h>
cd9e9808 MB	86	#include <linux/file.h>
cd9e9808 MB	87	#include <linux/dmapool.h>
e3eb3799	88	#include <uapi/linux/lightnvm.h>
cd9e9808 MB	89
	90	enum {
	91	/* HW Responsibilities */
	92	NVM_RSP_L2P = 1 << 0,
	93	NVM_RSP_ECC = 1 << 1,
	94
	95	/* Physical Adressing Mode */
	96	NVM_ADDRMODE_LINEAR = 0,
	97	NVM_ADDRMODE_CHANNEL = 1,
	98
	99	/* Plane programming mode for LUN */
d5bdec8d MB	100	NVM_PLANE_SINGLE = 1,
	101	NVM_PLANE_DOUBLE = 2,
	102	NVM_PLANE_QUAD = 4,
cd9e9808 MB	103
	104	/* Status codes */
	105	NVM_RSP_SUCCESS = 0x0,
	106	NVM_RSP_NOT_CHANGEABLE = 0x1,
	107	NVM_RSP_ERR_FAILWRITE = 0x40ff,
	108	NVM_RSP_ERR_EMPTYPAGE = 0x42ff,
402ab9a8	109	NVM_RSP_ERR_FAILECC = 0x4281,
38ea2f76	110	NVM_RSP_ERR_FAILCRC = 0x4004,
402ab9a8	111	NVM_RSP_WARN_HIGHECC = 0x4700,
cd9e9808 MB	112
cd9e9808 MB	113	/* Device opcodes */
cd9e9808 MB	114	NVM_OP_PWRITE = 0x91,
	115	NVM_OP_PREAD = 0x92,
	116	NVM_OP_ERASE = 0x90,
	117
	118	/* PPA Command Flags */
	119	NVM_IO_SNGL_ACCESS = 0x0,
	120	NVM_IO_DUAL_ACCESS = 0x1,
	121	NVM_IO_QUAD_ACCESS = 0x2,
	122
57b4bd06	123	/* NAND Access Modes */
cd9e9808 MB	124	NVM_IO_SUSPEND = 0x80,
cd9e9808 MB	125	NVM_IO_SLC_MODE = 0x100,
a7737f39	126	NVM_IO_SCRAMBLE_ENABLE = 0x200,
57b4bd06 MB	127
	128	/* Block Types */
	129	NVM_BLK_T_FREE = 0x0,
	130	NVM_BLK_T_BAD = 0x1,
b5d4acd4 MB	131	NVM_BLK_T_GRWN_BAD = 0x2,
	132	NVM_BLK_T_DEV = 0x4,
	133	NVM_BLK_T_HOST = 0x8,
f9a99950 MB	134
	135	/* Memory capabilities */
	136	NVM_ID_CAP_SLC = 0x1,
	137	NVM_ID_CAP_CMD_SUSPEND = 0x2,
	138	NVM_ID_CAP_SCRAMBLE = 0x4,
	139	NVM_ID_CAP_ENCRYPT = 0x8,
ca5927e7 MB	140
	141	/* Memory types */
	142	NVM_ID_FMTYPE_SLC = 0,
	143	NVM_ID_FMTYPE_MLC = 1,
bf643185 MB	144
	145	/* Device capabilities */
	146	NVM_ID_DCAP_BBLKMGMT = 0x1,
	147	NVM_UD_DCAP_ECC = 0x2,
ca5927e7 MB	148	};
	149
	150	struct nvm_id_lp_mlc {
	151	u16 num_pairs;
	152	u8 pairs[886];
	153	};
	154
	155	struct nvm_id_lp_tbl {
	156	__u8 id[8];
	157	struct nvm_id_lp_mlc mlc;
cd9e9808 MB	158	};
cd9e9808 MB	159
e46f4e48	160	struct nvm_addrf_12 {
c6ac3f35	161	u8 ch_len;
c6ac3f35	162	u8 lun_len;
c6ac3f35	163	u8 blk_len;
c6ac3f35	164	u8 pg_len;
e46f4e48	165	u8 pln_len;
c6ac3f35	166	u8 sect_len;
c6ac3f35	167
e46f4e48 JG	168	u8 ch_offset;
	169	u8 lun_offset;
	170	u8 blk_offset;
	171	u8 pg_offset;
	172	u8 pln_offset;
	173	u8 sect_offset;
fae7fae4	174
e46f4e48 JG	175	u64 ch_mask;
	176	u64 lun_mask;
	177	u64 blk_mask;
	178	u64 pg_mask;
	179	u64 pln_mask;
	180	u64 sec_mask;
	181	};
62771fe0	182
e46f4e48 JG	183	struct nvm_addrf {
	184	u8 ch_len;
	185	u8 lun_len;
	186	u8 chk_len;
	187	u8 sec_len;
	188	u8 rsv_len[2];
c6ac3f35	189
e46f4e48 JG	190	u8 ch_offset;
	191	u8 lun_offset;
	192	u8 chk_offset;
	193	u8 sec_offset;
	194	u8 rsv_off[2];
	195
	196	u64 ch_mask;
	197	u64 lun_mask;
	198	u64 chk_mask;
	199	u64 sec_mask;
	200	u64 rsv_mask[2];
	201	};
cd9e9808 MB	202
	203	struct nvm_target {
	204	struct list_head list;
8e79b5cb	205	struct nvm_tgt_dev *dev;
cd9e9808 MB	206	struct nvm_tgt_type *type;
	207	struct gendisk *disk;
	208	};
	209
cd9e9808 MB	210	#define ADDR_EMPTY (~0ULL)
cd9e9808 MB	211
e5392739 JG	212	#define NVM_TARGET_DEFAULT_OP (101)
	213	#define NVM_TARGET_MIN_OP (3)
	214	#define NVM_TARGET_MAX_OP (80)
	215
cd9e9808 MB	216	#define NVM_VERSION_MAJOR 1
	217	#define NVM_VERSION_MINOR 0
	218	#define NVM_VERSION_PATCH 0
	219
89a09c56 MB	220	#define NVM_MAX_VLBA (64) /* max logical blocks in a vector command */
89a09c56 MB	221
91276162	222	struct nvm_rq;
72d256ec	223	typedef void (nvm_end_io_fn)(struct nvm_rq *);
91276162	224
cd9e9808	225	struct nvm_rq {
8e53624d	226	struct nvm_tgt_dev *dev;
cd9e9808 MB	227
	228	struct bio *bio;
	229
	230	union {
	231	struct ppa_addr ppa_addr;
	232	dma_addr_t dma_ppa_list;
	233	};
	234
	235	struct ppa_addr *ppa_list;
	236
003fad37 JG	237	void *meta_list;
003fad37 JG	238	dma_addr_t dma_meta_list;
cd9e9808	239
91276162 MB	240	nvm_end_io_fn *end_io;
91276162 MB	241
cd9e9808	242	uint8_t opcode;
6d5be959	243	uint16_t nr_ppas;
cd9e9808	244	uint16_t flags;
72d256ec	245
9f867268	246	u64 ppa_status; /* ppa media status */
72d256ec	247	int error;
06894efe MB	248
06894efe MB	249	void *private;
cd9e9808 MB	250	};
	251
	252	static inline struct nvm_rq nvm_rq_from_pdu(void pdu)
	253	{
	254	return pdu - sizeof(struct nvm_rq);
	255	}
	256
	257	static inline void nvm_rq_to_pdu(struct nvm_rq rqdata)
	258	{
	259	return rqdata + 1;
	260	}
	261
ff0e498b JG	262	enum {
ff0e498b JG	263	NVM_BLK_ST_FREE = 0x1, /* Free block */
077d2389	264	NVM_BLK_ST_TGT = 0x2, /* Block in use by target */
ff0e498b	265	NVM_BLK_ST_BAD = 0x8, /* Bad block */
cd9e9808 MB	266	};
cd9e9808 MB	267
e46f4e48	268	/* Instance geometry */
8e79b5cb	269	struct nvm_geo {
e46f4e48	270	/* device reported version */
3cb98f84 JG	271	u8 major_ver_id;
3cb98f84 JG	272	u8 minor_ver_id;
e46f4e48	273
f1d4e812 JG	274	/* kernel short version */
	275	u8 version;
	276
e46f4e48	277	/* instance specific geometry */
cd9e9808	278	int nr_chnls;
e46f4e48	279	int nr_luns; /* per channel */
fae7fae4	280
e46f4e48 JG	281	/* calculated values */
	282	int all_luns; /* across channels */
	283	int all_chunks; /* across channels */
	284
	285	int op; /* over-provision in instance */
	286
	287	sector_t total_secs; /* across channels */
	288
	289	/* chunk geometry */
	290	u32 nr_chks; /* chunks per lun */
	291	u32 clba; /* sectors per chunk */
	292	u16 csecs; /* sector size */
	293	u16 sos; /* out-of-band area size */
cd9e9808	294
e46f4e48 JG	295	/* device write constrains */
	296	u32 ws_min; /* minimum write size */
	297	u32 ws_opt; /* optimal write size */
	298	u32 mw_cunits; /* distance required for successful read */
fae7fae4	299
e46f4e48 JG	300	/* device capabilities */
e46f4e48 JG	301	u32 mccap;
fae7fae4	302
e46f4e48 JG	303	/* device timings */
	304	u32 trdt; /* Avg. Tread (ns) */
	305	u32 trdm; /* Max Tread (ns) */
	306	u32 tprt; /* Avg. Tprog (ns) */
	307	u32 tprm; /* Max Tprog (ns) */
	308	u32 tbet; /* Avg. Terase (ns) */
	309	u32 tbem; /* Max Terase (ns) */
e5392739	310
e46f4e48 JG	311	/* generic address format */
e46f4e48 JG	312	struct nvm_addrf addrf;
fae7fae4	313
e46f4e48 JG	314	/* 1.2 compatibility */
	315	u8 vmnt;
	316	u32 cap;
	317	u32 dom;
	318
	319	u8 mtype;
	320	u8 fmtype;
	321
	322	u16 cpar;
	323	u32 mpos;
	324
	325	u8 num_pln;
	326	u8 plane_mode;
	327	u16 num_pg;
	328	u16 fpg_sz;
8e79b5cb JG	329	};
8e79b5cb JG	330
ade69e24	331	/* sub-device structure */
8e79b5cb JG	332	struct nvm_tgt_dev {
	333	/* Device information */
	334	struct nvm_geo geo;
	335
8e53624d JG	336	/* Base ppas for target LUNs */
	337	struct ppa_addr *luns;
	338
8e79b5cb JG	339	struct request_queue *q;
8e79b5cb JG	340
959e911b	341	struct nvm_dev *parent;
8e53624d	342	void *map;
8e79b5cb JG	343	};
	344
	345	struct nvm_dev {
	346	struct nvm_dev_ops *ops;
	347
	348	struct list_head devices;
	349
8e79b5cb JG	350	/* Device information */
8e79b5cb JG	351	struct nvm_geo geo;
cd9e9808	352
da1e2849	353	unsigned long *lun_map;
75b85649	354	void *dma_pool;
cd9e9808	355
cd9e9808 MB	356	/* Backend device */
	357	struct request_queue *q;
	358	char name[DISK_NAME_LEN];
40267efd	359	void *private_data;
e3eb3799	360
8e53624d JG	361	void *rmap;
8e53624d JG	362
e3eb3799	363	struct mutex mlock;
4c9dacb8	364	spinlock_t lock;
ade69e24 MB	365
	366	/* target management */
	367	struct list_head area_list;
	368	struct list_head targets;
cd9e9808 MB	369	};
cd9e9808 MB	370
dab8ee9e MB	371	static inline struct ppa_addr generic_to_dev_addr(struct nvm_tgt_dev *tgt_dev,
dab8ee9e MB	372	struct ppa_addr r)
cd9e9808	373	{
dab8ee9e	374	struct nvm_geo *geo = &tgt_dev->geo;
e46f4e48	375	struct nvm_addrf_12 ppaf = (struct nvm_addrf_12 )&geo->addrf;
cd9e9808 MB	376	struct ppa_addr l;
cd9e9808 MB	377
e46f4e48 JG	378	l.ppa = ((u64)r.g.ch) << ppaf->ch_offset;
	379	l.ppa \|= ((u64)r.g.lun) << ppaf->lun_offset;
	380	l.ppa \|= ((u64)r.g.blk) << ppaf->blk_offset;
	381	l.ppa \|= ((u64)r.g.pg) << ppaf->pg_offset;
	382	l.ppa \|= ((u64)r.g.pl) << ppaf->pln_offset;
	383	l.ppa \|= ((u64)r.g.sec) << ppaf->sect_offset;
cd9e9808 MB	384
	385	return l;
	386	}
	387
dab8ee9e MB	388	static inline struct ppa_addr dev_to_generic_addr(struct nvm_tgt_dev *tgt_dev,
dab8ee9e MB	389	struct ppa_addr r)
cd9e9808	390	{
dab8ee9e	391	struct nvm_geo *geo = &tgt_dev->geo;
e46f4e48	392	struct nvm_addrf_12 ppaf = (struct nvm_addrf_12 )&geo->addrf;
cd9e9808 MB	393	struct ppa_addr l;
cd9e9808 MB	394
5389a1df	395	l.ppa = 0;
e46f4e48 JG	396
	397	l.g.ch = (r.ppa & ppaf->ch_mask) >> ppaf->ch_offset;
	398	l.g.lun = (r.ppa & ppaf->lun_mask) >> ppaf->lun_offset;
	399	l.g.blk = (r.ppa & ppaf->blk_mask) >> ppaf->blk_offset;
	400	l.g.pg = (r.ppa & ppaf->pg_mask) >> ppaf->pg_offset;
	401	l.g.pl = (r.ppa & ppaf->pln_mask) >> ppaf->pln_offset;
	402	l.g.sec = (r.ppa & ppaf->sec_mask) >> ppaf->sect_offset;
cd9e9808 MB	403
	404	return l;
	405	}
	406
dece1635	407	typedef blk_qc_t (nvm_tgt_make_rq_fn)(struct request_queue , struct bio );
cd9e9808	408	typedef sector_t (nvm_tgt_capacity_fn)(void *);
4af3f75d JG	409	typedef void (nvm_tgt_init_fn)(struct nvm_tgt_dev , struct gendisk *,
4af3f75d JG	410	int flags);
cd9e9808	411	typedef void (nvm_tgt_exit_fn)(void *);
9a69b0ed JG	412	typedef int (nvm_tgt_sysfs_init_fn)(struct gendisk *);
9a69b0ed JG	413	typedef void (nvm_tgt_sysfs_exit_fn)(struct gendisk *);
cd9e9808 MB	414
	415	struct nvm_tgt_type {
	416	const char *name;
	417	unsigned int version[3];
	418
	419	/* target entry points */
	420	nvm_tgt_make_rq_fn *make_rq;
	421	nvm_tgt_capacity_fn *capacity;
cd9e9808 MB	422
	423	/* module-specific init/teardown */
	424	nvm_tgt_init_fn *init;
	425	nvm_tgt_exit_fn *exit;
	426
9a69b0ed JG	427	/* sysfs */
	428	nvm_tgt_sysfs_init_fn *sysfs_init;
	429	nvm_tgt_sysfs_exit_fn *sysfs_exit;
	430
cd9e9808 MB	431	/* For internal use */
cd9e9808 MB	432	struct list_head list;
90014829	433	struct module *owner;
cd9e9808 MB	434	};
cd9e9808 MB	435
6063fe39 SL	436	extern int nvm_register_tgt_type(struct nvm_tgt_type *);
6063fe39 SL	437	extern void nvm_unregister_tgt_type(struct nvm_tgt_type *);
cd9e9808 MB	438
	439	extern void nvm_dev_dma_alloc(struct nvm_dev , gfp_t, dma_addr_t *);
	440	extern void nvm_dev_dma_free(struct nvm_dev , void , dma_addr_t);
	441
b0b4e09c MB	442	extern struct nvm_dev *nvm_alloc_dev(int);
	443	extern int nvm_register(struct nvm_dev *);
	444	extern void nvm_unregister(struct nvm_dev *);
cd9e9808	445
333ba053 JG	446	extern int nvm_set_tgt_bb_tbl(struct nvm_tgt_dev , struct ppa_addr ,
333ba053 JG	447	int, int);
8e53624d	448	extern int nvm_submit_io(struct nvm_tgt_dev , struct nvm_rq );
1a94b2d4	449	extern int nvm_submit_io_sync(struct nvm_tgt_dev , struct nvm_rq );
06894efe	450	extern void nvm_end_io(struct nvm_rq *);
22e8c976	451	extern int nvm_bb_tbl_fold(struct nvm_dev , u8 , int);
333ba053	452	extern int nvm_get_tgt_bb_tbl(struct nvm_tgt_dev , struct ppa_addr, u8 );
e3eb3799	453
cd9e9808 MB	454	#else /* CONFIG_NVM */
	455	struct nvm_dev_ops;
	456
b0b4e09c MB	457	static inline struct nvm_dev *nvm_alloc_dev(int node)
	458	{
	459	return ERR_PTR(-EINVAL);
	460	}
	461	static inline int nvm_register(struct nvm_dev *dev)
cd9e9808 MB	462	{
	463	return -EINVAL;
	464	}
b0b4e09c	465	static inline void nvm_unregister(struct nvm_dev *dev) {}
cd9e9808 MB	466	#endif /* CONFIG_NVM */
cd9e9808 MB	467	#endif /* LIGHTNVM.H */