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4107da2a HZ |
1 | /* |
2 | * Marvell 88PM8607 Interface | |
3 | * | |
4 | * Copyright (C) 2009 Marvell International Ltd. | |
5 | * Haojian Zhuang <haojian.zhuang@marvell.com> | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
12 | #ifndef __LINUX_MFD_88PM8607_H | |
13 | #define __LINUX_MFD_88PM8607_H | |
14 | ||
15 | enum { | |
16 | PM8607_ID_BUCK1 = 0, | |
17 | PM8607_ID_BUCK2, | |
18 | PM8607_ID_BUCK3, | |
19 | ||
20 | PM8607_ID_LDO1, | |
21 | PM8607_ID_LDO2, | |
22 | PM8607_ID_LDO3, | |
23 | PM8607_ID_LDO4, | |
24 | PM8607_ID_LDO5, | |
25 | PM8607_ID_LDO6, | |
26 | PM8607_ID_LDO7, | |
27 | PM8607_ID_LDO8, | |
28 | PM8607_ID_LDO9, | |
29 | PM8607_ID_LDO10, | |
30 | PM8607_ID_LDO12, | |
31 | PM8607_ID_LDO14, | |
32 | ||
33 | PM8607_ID_RG_MAX, | |
34 | }; | |
35 | ||
36 | #define CHIP_ID (0x40) | |
37 | #define CHIP_ID_MASK (0xF8) | |
38 | ||
39 | /* Interrupt Registers */ | |
40 | #define PM8607_STATUS_1 (0x01) | |
41 | #define PM8607_STATUS_2 (0x02) | |
42 | #define PM8607_INT_STATUS1 (0x03) | |
43 | #define PM8607_INT_STATUS2 (0x04) | |
44 | #define PM8607_INT_STATUS3 (0x05) | |
45 | #define PM8607_INT_MASK_1 (0x06) | |
46 | #define PM8607_INT_MASK_2 (0x07) | |
47 | #define PM8607_INT_MASK_3 (0x08) | |
48 | ||
49 | /* Regulator Control Registers */ | |
50 | #define PM8607_LDO1 (0x10) | |
51 | #define PM8607_LDO2 (0x11) | |
52 | #define PM8607_LDO3 (0x12) | |
53 | #define PM8607_LDO4 (0x13) | |
54 | #define PM8607_LDO5 (0x14) | |
55 | #define PM8607_LDO6 (0x15) | |
56 | #define PM8607_LDO7 (0x16) | |
57 | #define PM8607_LDO8 (0x17) | |
58 | #define PM8607_LDO9 (0x18) | |
59 | #define PM8607_LDO10 (0x19) | |
60 | #define PM8607_LDO12 (0x1A) | |
61 | #define PM8607_LDO14 (0x1B) | |
62 | #define PM8607_SLEEP_MODE1 (0x1C) | |
63 | #define PM8607_SLEEP_MODE2 (0x1D) | |
64 | #define PM8607_SLEEP_MODE3 (0x1E) | |
65 | #define PM8607_SLEEP_MODE4 (0x1F) | |
66 | #define PM8607_GO (0x20) | |
67 | #define PM8607_SLEEP_BUCK1 (0x21) | |
68 | #define PM8607_SLEEP_BUCK2 (0x22) | |
69 | #define PM8607_SLEEP_BUCK3 (0x23) | |
70 | #define PM8607_BUCK1 (0x24) | |
71 | #define PM8607_BUCK2 (0x25) | |
72 | #define PM8607_BUCK3 (0x26) | |
73 | #define PM8607_BUCK_CONTROLS (0x27) | |
74 | #define PM8607_SUPPLIES_EN11 (0x2B) | |
75 | #define PM8607_SUPPLIES_EN12 (0x2C) | |
76 | #define PM8607_GROUP1 (0x2D) | |
77 | #define PM8607_GROUP2 (0x2E) | |
78 | #define PM8607_GROUP3 (0x2F) | |
79 | #define PM8607_GROUP4 (0x30) | |
80 | #define PM8607_GROUP5 (0x31) | |
81 | #define PM8607_GROUP6 (0x32) | |
82 | #define PM8607_SUPPLIES_EN21 (0x33) | |
83 | #define PM8607_SUPPLIES_EN22 (0x34) | |
84 | ||
85 | /* RTC Control Registers */ | |
86 | #define PM8607_RTC1 (0xA0) | |
87 | #define PM8607_RTC_COUNTER1 (0xA1) | |
88 | #define PM8607_RTC_COUNTER2 (0xA2) | |
89 | #define PM8607_RTC_COUNTER3 (0xA3) | |
90 | #define PM8607_RTC_COUNTER4 (0xA4) | |
91 | #define PM8607_RTC_EXPIRE1 (0xA5) | |
92 | #define PM8607_RTC_EXPIRE2 (0xA6) | |
93 | #define PM8607_RTC_EXPIRE3 (0xA7) | |
94 | #define PM8607_RTC_EXPIRE4 (0xA8) | |
95 | #define PM8607_RTC_TRIM1 (0xA9) | |
96 | #define PM8607_RTC_TRIM2 (0xAA) | |
97 | #define PM8607_RTC_TRIM3 (0xAB) | |
98 | #define PM8607_RTC_TRIM4 (0xAC) | |
99 | #define PM8607_RTC_MISC1 (0xAD) | |
100 | #define PM8607_RTC_MISC2 (0xAE) | |
101 | #define PM8607_RTC_MISC3 (0xAF) | |
102 | ||
103 | /* Misc Registers */ | |
104 | #define PM8607_CHIP_ID (0x00) | |
105 | #define PM8607_LDO1 (0x10) | |
106 | #define PM8607_DVC3 (0x26) | |
107 | #define PM8607_MISC1 (0x40) | |
108 | ||
109 | /* bit definitions for PM8607 events */ | |
110 | #define PM8607_EVENT_ONKEY (1 << 0) | |
111 | #define PM8607_EVENT_EXTON (1 << 1) | |
112 | #define PM8607_EVENT_CHG (1 << 2) | |
113 | #define PM8607_EVENT_BAT (1 << 3) | |
114 | #define PM8607_EVENT_RTC (1 << 4) | |
115 | #define PM8607_EVENT_CC (1 << 5) | |
116 | #define PM8607_EVENT_VBAT (1 << 8) | |
117 | #define PM8607_EVENT_VCHG (1 << 9) | |
118 | #define PM8607_EVENT_VSYS (1 << 10) | |
119 | #define PM8607_EVENT_TINT (1 << 11) | |
120 | #define PM8607_EVENT_GPADC0 (1 << 12) | |
121 | #define PM8607_EVENT_GPADC1 (1 << 13) | |
122 | #define PM8607_EVENT_GPADC2 (1 << 14) | |
123 | #define PM8607_EVENT_GPADC3 (1 << 15) | |
124 | #define PM8607_EVENT_AUDIO_SHORT (1 << 16) | |
125 | #define PM8607_EVENT_PEN (1 << 17) | |
126 | #define PM8607_EVENT_HEADSET (1 << 18) | |
127 | #define PM8607_EVENT_HOOK (1 << 19) | |
128 | #define PM8607_EVENT_MICIN (1 << 20) | |
129 | #define PM8607_EVENT_CHG_TIMEOUT (1 << 21) | |
130 | #define PM8607_EVENT_CHG_DONE (1 << 22) | |
131 | #define PM8607_EVENT_CHG_FAULT (1 << 23) | |
132 | ||
133 | /* bit definitions of Status Query Interface */ | |
134 | #define PM8607_STATUS_CC (1 << 3) | |
135 | #define PM8607_STATUS_PEN (1 << 4) | |
136 | #define PM8607_STATUS_HEADSET (1 << 5) | |
137 | #define PM8607_STATUS_HOOK (1 << 6) | |
138 | #define PM8607_STATUS_MICIN (1 << 7) | |
139 | #define PM8607_STATUS_ONKEY (1 << 8) | |
140 | #define PM8607_STATUS_EXTON (1 << 9) | |
141 | #define PM8607_STATUS_CHG (1 << 10) | |
142 | #define PM8607_STATUS_BAT (1 << 11) | |
143 | #define PM8607_STATUS_VBUS (1 << 12) | |
144 | #define PM8607_STATUS_OV (1 << 13) | |
145 | ||
146 | /* bit definitions of BUCK3 */ | |
147 | #define PM8607_BUCK3_DOUBLE (1 << 6) | |
148 | ||
149 | /* bit definitions of Misc1 */ | |
150 | #define PM8607_MISC1_PI2C (1 << 0) | |
151 | ||
152 | /* Interrupt Number in 88PM8607 */ | |
153 | enum { | |
154 | PM8607_IRQ_ONKEY = 0, | |
155 | PM8607_IRQ_EXTON, | |
156 | PM8607_IRQ_CHG, | |
157 | PM8607_IRQ_BAT, | |
158 | PM8607_IRQ_RTC, | |
159 | PM8607_IRQ_VBAT = 8, | |
160 | PM8607_IRQ_VCHG, | |
161 | PM8607_IRQ_VSYS, | |
162 | PM8607_IRQ_TINT, | |
163 | PM8607_IRQ_GPADC0, | |
164 | PM8607_IRQ_GPADC1, | |
165 | PM8607_IRQ_GPADC2, | |
166 | PM8607_IRQ_GPADC3, | |
167 | PM8607_IRQ_AUDIO_SHORT = 16, | |
168 | PM8607_IRQ_PEN, | |
169 | PM8607_IRQ_HEADSET, | |
170 | PM8607_IRQ_HOOK, | |
171 | PM8607_IRQ_MICIN, | |
172 | PM8607_IRQ_CHG_FAIL, | |
173 | PM8607_IRQ_CHG_DONE, | |
174 | PM8607_IRQ_CHG_FAULT, | |
175 | }; | |
176 | ||
177 | enum { | |
178 | PM8607_CHIP_A0 = 0x40, | |
179 | PM8607_CHIP_A1 = 0x41, | |
180 | PM8607_CHIP_B0 = 0x48, | |
181 | }; | |
182 | ||
183 | ||
184 | struct pm8607_chip { | |
185 | struct device *dev; | |
186 | struct mutex io_lock; | |
187 | struct i2c_client *client; | |
188 | ||
189 | int (*read)(struct pm8607_chip *chip, int reg, int bytes, void *dest); | |
190 | int (*write)(struct pm8607_chip *chip, int reg, int bytes, void *src); | |
191 | ||
192 | int buck3_double; /* DVC ramp slope double */ | |
193 | unsigned char chip_id; | |
194 | ||
195 | }; | |
196 | ||
197 | #define PM8607_MAX_REGULATOR 15 /* 3 Bucks, 12 LDOs */ | |
198 | ||
199 | enum { | |
200 | GI2C_PORT = 0, | |
201 | PI2C_PORT, | |
202 | }; | |
203 | ||
204 | struct pm8607_platform_data { | |
205 | int i2c_port; /* Controlled by GI2C or PI2C */ | |
206 | struct regulator_init_data *regulator[PM8607_MAX_REGULATOR]; | |
207 | }; | |
208 | ||
209 | extern int pm8607_reg_read(struct pm8607_chip *, int); | |
210 | extern int pm8607_reg_write(struct pm8607_chip *, int, unsigned char); | |
211 | extern int pm8607_bulk_read(struct pm8607_chip *, int, int, | |
212 | unsigned char *); | |
213 | extern int pm8607_bulk_write(struct pm8607_chip *, int, int, | |
214 | unsigned char *); | |
215 | extern int pm8607_set_bits(struct pm8607_chip *, int, unsigned char, | |
216 | unsigned char); | |
217 | #endif /* __LINUX_MFD_88PM8607_H */ |