projects / mirror_ubuntu-bionic-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| fa9ff4b1 SO |
1 | /* |
| 2 | * include/linux/mfd/asic3.h | |
| 3 | * | |
| 4 | * Compaq ASIC3 headers. | |
| 5 | * | |
| 6 | * This program is free software; you can redistribute it and/or modify | |
| 7 | * it under the terms of the GNU General Public License version 2 as | |
| 8 | * published by the Free Software Foundation. | |
| 9 | * | |
| 10 | * Copyright 2001 Compaq Computer Corporation. | |
| 3b26bf17 | 11 | * Copyright 2007-2008 OpenedHand Ltd. |
| fa9ff4b1 SO |
12 | */ |
| 13 | ||
| 14 | #ifndef __ASIC3_H__ | |
| 15 | #define __ASIC3_H__ | |
| 16 | ||
| 17 | #include <linux/types.h> | |
| 18 | ||
| fa9ff4b1 | 19 | struct asic3_platform_data { |
| 3b26bf17 SO |
20 | u16 *gpio_config; |
| 21 | unsigned int gpio_config_num; | |
| fa9ff4b1 | 22 | |
| fa9ff4b1 SO |
23 | unsigned int irq_base; |
| 24 | ||
| 6f2384c4 | 25 | unsigned int gpio_base; |
| fa9ff4b1 SO |
26 | }; |
| 27 | ||
| fa9ff4b1 SO |
28 | #define ASIC3_NUM_GPIO_BANKS 4 |
| 29 | #define ASIC3_GPIOS_PER_BANK 16 | |
| 30 | #define ASIC3_NUM_GPIOS 64 | |
| 31 | #define ASIC3_NR_IRQS ASIC3_NUM_GPIOS + 6 | |
| 32 | ||
| 01906d6d PZ |
33 | #define ASIC3_IRQ_LED0 64 |
| 34 | #define ASIC3_IRQ_LED1 65 | |
| 35 | #define ASIC3_IRQ_LED2 66 | |
| 36 | #define ASIC3_IRQ_SPI 67 | |
| 37 | #define ASIC3_IRQ_SMBUS 68 | |
| 38 | #define ASIC3_IRQ_OWM 69 | |
| 39 | ||
| 6f2384c4 SO |
40 | #define ASIC3_TO_GPIO(gpio) (NR_BUILTIN_GPIO + (gpio)) |
| 41 | ||
| fa9ff4b1 SO |
42 | #define ASIC3_GPIO_BANK_A 0 |
| 43 | #define ASIC3_GPIO_BANK_B 1 | |
| 44 | #define ASIC3_GPIO_BANK_C 2 | |
| 45 | #define ASIC3_GPIO_BANK_D 3 | |
| 46 | ||
| 47 | #define ASIC3_GPIO(bank, gpio) \ | |
| 48 | ((ASIC3_GPIOS_PER_BANK * ASIC3_GPIO_BANK_##bank) + (gpio)) | |
| 49 | #define ASIC3_GPIO_bit(gpio) (1 << (gpio & 0xf)) | |
| 50 | /* All offsets below are specified with this address bus shift */ | |
| 51 | #define ASIC3_DEFAULT_ADDR_SHIFT 2 | |
| 52 | ||
| 3b8139f8 | 53 | #define ASIC3_OFFSET(base, reg) (ASIC3_##base##_BASE + ASIC3_##base##_##reg) |
| fa9ff4b1 | 54 | #define ASIC3_GPIO_OFFSET(base, reg) \ |
| 3b8139f8 | 55 | (ASIC3_GPIO_##base##_BASE + ASIC3_GPIO_##reg) |
| fa9ff4b1 | 56 | |
| 3b8139f8 SO |
57 | #define ASIC3_GPIO_A_BASE 0x0000 |
| 58 | #define ASIC3_GPIO_B_BASE 0x0100 | |
| 59 | #define ASIC3_GPIO_C_BASE 0x0200 | |
| 60 | #define ASIC3_GPIO_D_BASE 0x0300 | |
| fa9ff4b1 | 61 | |
| 6f2384c4 SO |
62 | #define ASIC3_GPIO_TO_BANK(gpio) ((gpio) >> 4) |
| 63 | #define ASIC3_GPIO_TO_BIT(gpio) ((gpio) - \ | |
| 64 | (ASIC3_GPIOS_PER_BANK * ((gpio) >> 4))) | |
| 65 | #define ASIC3_GPIO_TO_MASK(gpio) (1 << ASIC3_GPIO_TO_BIT(gpio)) | |
| 3b8139f8 SO |
66 | #define ASIC3_GPIO_TO_BASE(gpio) (ASIC3_GPIO_A_BASE + (((gpio) >> 4) * 0x0100)) |
| 67 | #define ASIC3_BANK_TO_BASE(bank) (ASIC3_GPIO_A_BASE + ((bank) * 0x100)) | |
| 68 | ||
| 69 | #define ASIC3_GPIO_MASK 0x00 /* R/W 0:don't mask */ | |
| 70 | #define ASIC3_GPIO_DIRECTION 0x04 /* R/W 0:input */ | |
| 71 | #define ASIC3_GPIO_OUT 0x08 /* R/W 0:output low */ | |
| 72 | #define ASIC3_GPIO_TRIGGER_TYPE 0x0c /* R/W 0:level */ | |
| 73 | #define ASIC3_GPIO_EDGE_TRIGGER 0x10 /* R/W 0:falling */ | |
| 74 | #define ASIC3_GPIO_LEVEL_TRIGGER 0x14 /* R/W 0:low level detect */ | |
| 75 | #define ASIC3_GPIO_SLEEP_MASK 0x18 /* R/W 0:don't mask in sleep mode */ | |
| 76 | #define ASIC3_GPIO_SLEEP_OUT 0x1c /* R/W level 0:low in sleep mode */ | |
| 77 | #define ASIC3_GPIO_BAT_FAULT_OUT 0x20 /* R/W level 0:low in batt_fault */ | |
| 78 | #define ASIC3_GPIO_INT_STATUS 0x24 /* R/W 0:none, 1:detect */ | |
| 79 | #define ASIC3_GPIO_ALT_FUNCTION 0x28 /* R/W 1:LED register control */ | |
| 80 | #define ASIC3_GPIO_SLEEP_CONF 0x2c /* | |
| fa9ff4b1 SO |
81 | * R/W bit 1: autosleep |
| 82 | * 0: disable gposlpout in normal mode, | |
| 83 | * enable gposlpout in sleep mode. | |
| 84 | */ | |
| 3b8139f8 | 85 | #define ASIC3_GPIO_STATUS 0x30 /* R Pin status */ |
| fa9ff4b1 | 86 | |
| 3b26bf17 SO |
87 | /* |
| 88 | * ASIC3 GPIO config | |
| 89 | * | |
| 90 | * Bits 0..6 gpio number | |
| 91 | * Bits 7..13 Alternate function | |
| 92 | * Bit 14 Direction | |
| 93 | * Bit 15 Initial value | |
| 94 | * | |
| 95 | */ | |
| 96 | #define ASIC3_CONFIG_GPIO_PIN(config) ((config) & 0x7f) | |
| 97 | #define ASIC3_CONFIG_GPIO_ALT(config) (((config) & (0x7f << 7)) >> 7) | |
| 98 | #define ASIC3_CONFIG_GPIO_DIR(config) ((config & (1 << 14)) >> 14) | |
| 99 | #define ASIC3_CONFIG_GPIO_INIT(config) ((config & (1 << 15)) >> 15) | |
| 100 | #define ASIC3_CONFIG_GPIO(gpio, alt, dir, init) (((gpio) & 0x7f) \ | |
| 101 | | (((alt) & 0x7f) << 7) | (((dir) & 0x1) << 14) \ | |
| 102 | | (((init) & 0x1) << 15)) | |
| 103 | #define ASIC3_CONFIG_GPIO_DEFAULT(gpio, dir, init) \ | |
| 104 | ASIC3_CONFIG_GPIO((gpio), 0, (dir), (init)) | |
| 105 | #define ASIC3_CONFIG_GPIO_DEFAULT_OUT(gpio, init) \ | |
| 106 | ASIC3_CONFIG_GPIO((gpio), 0, 1, (init)) | |
| 107 | ||
| 4a67b528 PZ |
108 | /* |
| 109 | * Alternate functions | |
| 110 | */ | |
| 111 | #define ASIC3_GPIOA11_PWM0 ASIC3_CONFIG_GPIO(11, 1, 1, 0) | |
| 112 | #define ASIC3_GPIOA12_PWM1 ASIC3_CONFIG_GPIO(12, 1, 1, 0) | |
| 113 | #define ASIC3_GPIOA15_CONTROL_CX ASIC3_CONFIG_GPIO(15, 1, 1, 0) | |
| 114 | #define ASIC3_GPIOC0_LED0 ASIC3_CONFIG_GPIO(32, 1, 1, 0) | |
| 115 | #define ASIC3_GPIOC1_LED1 ASIC3_CONFIG_GPIO(33, 1, 1, 0) | |
| 116 | #define ASIC3_GPIOC2_LED2 ASIC3_CONFIG_GPIO(34, 1, 1, 0) | |
| 117 | #define ASIC3_GPIOC3_SPI_RXD ASIC3_CONFIG_GPIO(35, 1, 0, 0) | |
| 118 | #define ASIC3_GPIOC4_CF_nCD ASIC3_CONFIG_GPIO(36, 1, 0, 0) | |
| 119 | #define ASIC3_GPIOC4_SPI_TXD ASIC3_CONFIG_GPIO(36, 1, 1, 0) | |
| 120 | #define ASIC3_GPIOC5_SPI_CLK ASIC3_CONFIG_GPIO(37, 1, 1, 0) | |
| 121 | #define ASIC3_GPIOC5_nCIOW ASIC3_CONFIG_GPIO(37, 1, 1, 0) | |
| 122 | #define ASIC3_GPIOC6_nCIOR ASIC3_CONFIG_GPIO(38, 1, 1, 0) | |
| 123 | #define ASIC3_GPIOC7_nPCE_1 ASIC3_CONFIG_GPIO(39, 1, 0, 0) | |
| 124 | #define ASIC3_GPIOC8_nPCE_2 ASIC3_CONFIG_GPIO(40, 1, 0, 0) | |
| 125 | #define ASIC3_GPIOC9_nPOE ASIC3_CONFIG_GPIO(41, 1, 0, 0) | |
| 126 | #define ASIC3_GPIOC10_nPWE ASIC3_CONFIG_GPIO(42, 1, 0, 0) | |
| 127 | #define ASIC3_GPIOC11_PSKTSEL ASIC3_CONFIG_GPIO(43, 1, 0, 0) | |
| 128 | #define ASIC3_GPIOC12_nPREG ASIC3_CONFIG_GPIO(44, 1, 0, 0) | |
| 129 | #define ASIC3_GPIOC13_nPWAIT ASIC3_CONFIG_GPIO(45, 1, 1, 0) | |
| 130 | #define ASIC3_GPIOC14_nPIOIS16 ASIC3_CONFIG_GPIO(46, 1, 1, 0) | |
| 131 | #define ASIC3_GPIOC15_nPIOR ASIC3_CONFIG_GPIO(47, 1, 0, 0) | |
| 132 | #define ASIC3_GPIOD11_nCIOIS16 ASIC3_CONFIG_GPIO(59, 1, 0, 0) | |
| 133 | #define ASIC3_GPIOD12_nCWAIT ASIC3_CONFIG_GPIO(60, 1, 0, 0) | |
| 134 | #define ASIC3_GPIOD15_nPIOW ASIC3_CONFIG_GPIO(63, 1, 0, 0) | |
| 135 | ||
| 136 | ||
| fa9ff4b1 SO |
137 | #define ASIC3_SPI_Base 0x0400 |
| 138 | #define ASIC3_SPI_Control 0x0000 | |
| 139 | #define ASIC3_SPI_TxData 0x0004 | |
| 140 | #define ASIC3_SPI_RxData 0x0008 | |
| 141 | #define ASIC3_SPI_Int 0x000c | |
| 142 | #define ASIC3_SPI_Status 0x0010 | |
| 143 | ||
| 144 | #define SPI_CONTROL_SPR(clk) ((clk) & 0x0f) /* Clock rate */ | |
| 145 | ||
| 146 | #define ASIC3_PWM_0_Base 0x0500 | |
| 147 | #define ASIC3_PWM_1_Base 0x0600 | |
| 148 | #define ASIC3_PWM_TimeBase 0x0000 | |
| 149 | #define ASIC3_PWM_PeriodTime 0x0004 | |
| 150 | #define ASIC3_PWM_DutyTime 0x0008 | |
| 151 | ||
| 152 | #define PWM_TIMEBASE_VALUE(x) ((x)&0xf) /* Low 4 bits sets time base */ | |
| 153 | #define PWM_TIMEBASE_ENABLE (1 << 4) /* Enable clock */ | |
| 154 | ||
| 155 | #define ASIC3_LED_0_Base 0x0700 | |
| 156 | #define ASIC3_LED_1_Base 0x0800 | |
| 157 | #define ASIC3_LED_2_Base 0x0900 | |
| 158 | #define ASIC3_LED_TimeBase 0x0000 /* R/W 7 bits */ | |
| 159 | #define ASIC3_LED_PeriodTime 0x0004 /* R/W 12 bits */ | |
| 160 | #define ASIC3_LED_DutyTime 0x0008 /* R/W 12 bits */ | |
| 161 | #define ASIC3_LED_AutoStopCount 0x000c /* R/W 16 bits */ | |
| 162 | ||
| 163 | /* LED TimeBase bits - match ASIC2 */ | |
| 164 | #define LED_TBS 0x0f /* Low 4 bits sets time base, max = 13 */ | |
| 165 | /* Note: max = 5 on hx4700 */ | |
| 166 | /* 0: maximum time base */ | |
| 167 | /* 1: maximum time base / 2 */ | |
| 168 | /* n: maximum time base / 2^n */ | |
| 169 | ||
| 170 | #define LED_EN (1 << 4) /* LED ON/OFF 0:off, 1:on */ | |
| 171 | #define LED_AUTOSTOP (1 << 5) /* LED ON/OFF auto stop 0:disable, 1:enable */ | |
| 172 | #define LED_ALWAYS (1 << 6) /* LED Interrupt Mask 0:No mask, 1:mask */ | |
| 173 | ||
| 3b8139f8 | 174 | #define ASIC3_CLOCK_BASE 0x0A00 |
| fa9ff4b1 SO |
175 | #define ASIC3_CLOCK_CDEX 0x00 |
| 176 | #define ASIC3_CLOCK_SEL 0x04 | |
| 177 | ||
| 178 | #define CLOCK_CDEX_SOURCE (1 << 0) /* 2 bits */ | |
| 179 | #define CLOCK_CDEX_SOURCE0 (1 << 0) | |
| 180 | #define CLOCK_CDEX_SOURCE1 (1 << 1) | |
| 181 | #define CLOCK_CDEX_SPI (1 << 2) | |
| 182 | #define CLOCK_CDEX_OWM (1 << 3) | |
| 183 | #define CLOCK_CDEX_PWM0 (1 << 4) | |
| 184 | #define CLOCK_CDEX_PWM1 (1 << 5) | |
| 185 | #define CLOCK_CDEX_LED0 (1 << 6) | |
| 186 | #define CLOCK_CDEX_LED1 (1 << 7) | |
| 187 | #define CLOCK_CDEX_LED2 (1 << 8) | |
| 188 | ||
| 189 | /* Clocks settings: 1 for 24.576 MHz, 0 for 12.288Mhz */ | |
| 190 | #define CLOCK_CDEX_SD_HOST (1 << 9) /* R/W: SD host clock source */ | |
| 191 | #define CLOCK_CDEX_SD_BUS (1 << 10) /* R/W: SD bus clock source ctrl */ | |
| 192 | #define CLOCK_CDEX_SMBUS (1 << 11) | |
| 193 | #define CLOCK_CDEX_CONTROL_CX (1 << 12) | |
| 194 | ||
| 195 | #define CLOCK_CDEX_EX0 (1 << 13) /* R/W: 32.768 kHz crystal */ | |
| 196 | #define CLOCK_CDEX_EX1 (1 << 14) /* R/W: 24.576 MHz crystal */ | |
| 197 | ||
| 198 | #define CLOCK_SEL_SD_HCLK_SEL (1 << 0) /* R/W: SDIO host clock select */ | |
| 199 | #define CLOCK_SEL_SD_BCLK_SEL (1 << 1) /* R/W: SDIO bus clock select */ | |
| 200 | ||
| 201 | /* R/W: INT clock source control (32.768 kHz) */ | |
| 202 | #define CLOCK_SEL_CX (1 << 2) | |
| 203 | ||
| 204 | ||
| 3b8139f8 | 205 | #define ASIC3_INTR_BASE 0x0B00 |
| fa9ff4b1 | 206 | |
| 3b8139f8 SO |
207 | #define ASIC3_INTR_INT_MASK 0x00 /* Interrupt mask control */ |
| 208 | #define ASIC3_INTR_P_INT_STAT 0x04 /* Peripheral interrupt status */ | |
| 209 | #define ASIC3_INTR_INT_CPS 0x08 /* Interrupt timer clock pre-scale */ | |
| 210 | #define ASIC3_INTR_INT_TBS 0x0c /* Interrupt timer set */ | |
| fa9ff4b1 SO |
211 | |
| 212 | #define ASIC3_INTMASK_GINTMASK (1 << 0) /* Global INTs mask 1:enable */ | |
| 213 | #define ASIC3_INTMASK_GINTEL (1 << 1) /* 1: rising edge, 0: hi level */ | |
| 214 | #define ASIC3_INTMASK_MASK0 (1 << 2) | |
| 215 | #define ASIC3_INTMASK_MASK1 (1 << 3) | |
| 216 | #define ASIC3_INTMASK_MASK2 (1 << 4) | |
| 217 | #define ASIC3_INTMASK_MASK3 (1 << 5) | |
| 218 | #define ASIC3_INTMASK_MASK4 (1 << 6) | |
| 219 | #define ASIC3_INTMASK_MASK5 (1 << 7) | |
| 220 | ||
| 221 | #define ASIC3_INTR_PERIPHERAL_A (1 << 0) | |
| 222 | #define ASIC3_INTR_PERIPHERAL_B (1 << 1) | |
| 223 | #define ASIC3_INTR_PERIPHERAL_C (1 << 2) | |
| 224 | #define ASIC3_INTR_PERIPHERAL_D (1 << 3) | |
| 225 | #define ASIC3_INTR_LED0 (1 << 4) | |
| 226 | #define ASIC3_INTR_LED1 (1 << 5) | |
| 227 | #define ASIC3_INTR_LED2 (1 << 6) | |
| 228 | #define ASIC3_INTR_SPI (1 << 7) | |
| 229 | #define ASIC3_INTR_SMBUS (1 << 8) | |
| 230 | #define ASIC3_INTR_OWM (1 << 9) | |
| 231 | ||
| 232 | #define ASIC3_INTR_CPS(x) ((x)&0x0f) /* 4 bits, max 14 */ | |
| 233 | #define ASIC3_INTR_CPS_SET (1 << 4) /* Time base enable */ | |
| 234 | ||
| 235 | ||
| 236 | /* Basic control of the SD ASIC */ | |
| 6483c1b5 PZ |
237 | #define ASIC3_SDHWCTRL_BASE 0x0E00 |
| 238 | #define ASIC3_SDHWCTRL_SDCONF 0x00 | |
| fa9ff4b1 SO |
239 | |
| 240 | #define ASIC3_SDHWCTRL_SUSPEND (1 << 0) /* 1=suspend all SD operations */ | |
| 241 | #define ASIC3_SDHWCTRL_CLKSEL (1 << 1) /* 1=SDICK, 0=HCLK */ | |
| 242 | #define ASIC3_SDHWCTRL_PCLR (1 << 2) /* All registers of SDIO cleared */ | |
| 243 | #define ASIC3_SDHWCTRL_LEVCD (1 << 3) /* SD card detection: 0:low */ | |
| 244 | ||
| 245 | /* SD card write protection: 0=high */ | |
| 246 | #define ASIC3_SDHWCTRL_LEVWP (1 << 4) | |
| 247 | #define ASIC3_SDHWCTRL_SDLED (1 << 5) /* SD card LED signal 0=disable */ | |
| 248 | ||
| 249 | /* SD card power supply ctrl 1=enable */ | |
| 250 | #define ASIC3_SDHWCTRL_SDPWR (1 << 6) | |
| 251 | ||
| 6483c1b5 | 252 | #define ASIC3_EXTCF_BASE 0x1100 |
| fa9ff4b1 | 253 | |
| 6483c1b5 PZ |
254 | #define ASIC3_EXTCF_SELECT 0x00 |
| 255 | #define ASIC3_EXTCF_RESET 0x04 | |
| fa9ff4b1 SO |
256 | |
| 257 | #define ASIC3_EXTCF_SMOD0 (1 << 0) /* slot number of mode 0 */ | |
| 258 | #define ASIC3_EXTCF_SMOD1 (1 << 1) /* slot number of mode 1 */ | |
| 259 | #define ASIC3_EXTCF_SMOD2 (1 << 2) /* slot number of mode 2 */ | |
| 260 | #define ASIC3_EXTCF_OWM_EN (1 << 4) /* enable onewire module */ | |
| 261 | #define ASIC3_EXTCF_OWM_SMB (1 << 5) /* OWM bus selection */ | |
| 262 | #define ASIC3_EXTCF_OWM_RESET (1 << 6) /* ?? used by OWM and CF */ | |
| 263 | #define ASIC3_EXTCF_CF0_SLEEP_MODE (1 << 7) /* CF0 sleep state */ | |
| 264 | #define ASIC3_EXTCF_CF1_SLEEP_MODE (1 << 8) /* CF1 sleep state */ | |
| 265 | #define ASIC3_EXTCF_CF0_PWAIT_EN (1 << 10) /* CF0 PWAIT_n control */ | |
| 266 | #define ASIC3_EXTCF_CF1_PWAIT_EN (1 << 11) /* CF1 PWAIT_n control */ | |
| 267 | #define ASIC3_EXTCF_CF0_BUF_EN (1 << 12) /* CF0 buffer control */ | |
| 268 | #define ASIC3_EXTCF_CF1_BUF_EN (1 << 13) /* CF1 buffer control */ | |
| 269 | #define ASIC3_EXTCF_SD_MEM_ENABLE (1 << 14) | |
| 270 | #define ASIC3_EXTCF_CF_SLEEP (1 << 15) /* CF sleep mode control */ | |
| 271 | ||
| 272 | /********************************************* | |
| 279cac48 PZ |
273 | * The Onewire interface (DS1WM) is handled |
| 274 | * by the ds1wm driver. | |
| fa9ff4b1 SO |
275 | * |
| 276 | *********************************************/ | |
| 277 | ||
| 279cac48 | 278 | #define ASIC3_OWM_BASE 0xC00 |
| fa9ff4b1 SO |
279 | |
| 280 | /***************************************************************************** | |
| 281 | * The SD configuration registers are at a completely different location | |
| 282 | * in memory. They are divided into three sets of registers: | |
| 283 | * | |
| 284 | * SD_CONFIG Core configuration register | |
| 285 | * SD_CTRL Control registers for SD operations | |
| 286 | * SDIO_CTRL Control registers for SDIO operations | |
| 287 | * | |
| 288 | *****************************************************************************/ | |
| 289 | #define ASIC3_SD_CONFIG_Base 0x0400 /* Assumes 32 bit addressing */ | |
| 290 | ||
| 291 | #define ASIC3_SD_CONFIG_Command 0x08 /* R/W: Command */ | |
| 292 | ||
| 293 | /* [0:8] SD Control Register Base Address */ | |
| 294 | #define ASIC3_SD_CONFIG_Addr0 0x20 | |
| 295 | ||
| 296 | /* [9:31] SD Control Register Base Address */ | |
| 297 | #define ASIC3_SD_CONFIG_Addr1 0x24 | |
| 298 | ||
| 299 | /* R/O: interrupt assigned to pin */ | |
| 300 | #define ASIC3_SD_CONFIG_IntPin 0x78 | |
| 301 | ||
| 302 | /* | |
| 303 | * Set to 0x1f to clock SD controller, 0 otherwise. | |
| 304 | * At 0x82 - Gated Clock Ctrl | |
| 305 | */ | |
| 306 | #define ASIC3_SD_CONFIG_ClkStop 0x80 | |
| 307 | ||
| 308 | /* Control clock of SD controller */ | |
| 309 | #define ASIC3_SD_CONFIG_ClockMode 0x84 | |
| 310 | #define ASIC3_SD_CONFIG_SDHC_PinStatus 0x88 /* R/0: SD pins status */ | |
| 311 | #define ASIC3_SD_CONFIG_SDHC_Power1 0x90 /* Power1 - manual pwr ctrl */ | |
| 312 | ||
| 313 | /* auto power up after card inserted */ | |
| 314 | #define ASIC3_SD_CONFIG_SDHC_Power2 0x92 | |
| 315 | ||
| 316 | /* auto power down when card removed */ | |
| 317 | #define ASIC3_SD_CONFIG_SDHC_Power3 0x94 | |
| 318 | #define ASIC3_SD_CONFIG_SDHC_CardDetect 0x98 | |
| 319 | #define ASIC3_SD_CONFIG_SDHC_Slot 0xA0 /* R/O: support slot number */ | |
| 320 | #define ASIC3_SD_CONFIG_SDHC_ExtGateClk1 0x1E0 /* Not used */ | |
| 321 | #define ASIC3_SD_CONFIG_SDHC_ExtGateClk2 0x1E2 /* Not used*/ | |
| 322 | ||
| 323 | /* GPIO Output Reg. , at 0x1EA - GPIO Output Enable Reg. */ | |
| 324 | #define ASIC3_SD_CONFIG_SDHC_GPIO_OutAndEnable 0x1E8 | |
| 325 | #define ASIC3_SD_CONFIG_SDHC_GPIO_Status 0x1EC /* GPIO Status Reg. */ | |
| 326 | ||
| 327 | /* Bit 1: double buffer/single buffer */ | |
| 328 | #define ASIC3_SD_CONFIG_SDHC_ExtGateClk3 0x1F0 | |
| 329 | ||
| 330 | /* Memory access enable (set to 1 to access SD Controller) */ | |
| 331 | #define SD_CONFIG_COMMAND_MAE (1<<1) | |
| 332 | ||
| 333 | #define SD_CONFIG_CLK_ENABLE_ALL 0x1f | |
| 334 | ||
| 335 | #define SD_CONFIG_POWER1_PC_33V 0x0200 /* Set for 3.3 volts */ | |
| 336 | #define SD_CONFIG_POWER1_PC_OFF 0x0000 /* Turn off power */ | |
| 337 | ||
| 338 | /* two bits - number of cycles for card detection */ | |
| 339 | #define SD_CONFIG_CARDDETECTMODE_CLK ((x) & 0x3) | |
| 340 | ||
| 341 | ||
| 342 | #define ASIC3_SD_CTRL_Base 0x1000 | |
| 343 | ||
| 344 | #define ASIC3_SD_CTRL_Cmd 0x00 | |
| 345 | #define ASIC3_SD_CTRL_Arg0 0x08 | |
| 346 | #define ASIC3_SD_CTRL_Arg1 0x0C | |
| 347 | #define ASIC3_SD_CTRL_StopInternal 0x10 | |
| 348 | #define ASIC3_SD_CTRL_TransferSectorCount 0x14 | |
| 349 | #define ASIC3_SD_CTRL_Response0 0x18 | |
| 350 | #define ASIC3_SD_CTRL_Response1 0x1C | |
| 351 | #define ASIC3_SD_CTRL_Response2 0x20 | |
| 352 | #define ASIC3_SD_CTRL_Response3 0x24 | |
| 353 | #define ASIC3_SD_CTRL_Response4 0x28 | |
| 354 | #define ASIC3_SD_CTRL_Response5 0x2C | |
| 355 | #define ASIC3_SD_CTRL_Response6 0x30 | |
| 356 | #define ASIC3_SD_CTRL_Response7 0x34 | |
| 357 | #define ASIC3_SD_CTRL_CardStatus 0x38 | |
| 358 | #define ASIC3_SD_CTRL_BufferCtrl 0x3C | |
| 359 | #define ASIC3_SD_CTRL_IntMaskCard 0x40 | |
| 360 | #define ASIC3_SD_CTRL_IntMaskBuffer 0x44 | |
| 361 | #define ASIC3_SD_CTRL_CardClockCtrl 0x48 | |
| 362 | #define ASIC3_SD_CTRL_MemCardXferDataLen 0x4C | |
| 363 | #define ASIC3_SD_CTRL_MemCardOptionSetup 0x50 | |
| 364 | #define ASIC3_SD_CTRL_ErrorStatus0 0x58 | |
| 365 | #define ASIC3_SD_CTRL_ErrorStatus1 0x5C | |
| 366 | #define ASIC3_SD_CTRL_DataPort 0x60 | |
| 367 | #define ASIC3_SD_CTRL_TransactionCtrl 0x68 | |
| 368 | #define ASIC3_SD_CTRL_SoftwareReset 0x1C0 | |
| 369 | ||
| 370 | #define SD_CTRL_SOFTWARE_RESET_CLEAR (1<<0) | |
| 371 | ||
| 372 | #define SD_CTRL_TRANSACTIONCONTROL_SET (1<<8) | |
| 373 | ||
| 374 | #define SD_CTRL_CARDCLOCKCONTROL_FOR_SD_CARD (1<<15) | |
| 375 | #define SD_CTRL_CARDCLOCKCONTROL_ENABLE_CLOCK (1<<8) | |
| 376 | #define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_512 (1<<7) | |
| 377 | #define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_256 (1<<6) | |
| 378 | #define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_128 (1<<5) | |
| 379 | #define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_64 (1<<4) | |
| 380 | #define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_32 (1<<3) | |
| 381 | #define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_16 (1<<2) | |
| 382 | #define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_8 (1<<1) | |
| 383 | #define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_4 (1<<0) | |
| 384 | #define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_2 (0<<0) | |
| 385 | ||
| 386 | #define MEM_CARD_OPTION_REQUIRED 0x000e | |
| 387 | #define MEM_CARD_OPTION_DATA_RESPONSE_TIMEOUT(x) (((x) & 0x0f) << 4) | |
| 388 | #define MEM_CARD_OPTION_C2_MODULE_NOT_PRESENT (1<<14) | |
| 389 | #define MEM_CARD_OPTION_DATA_XFR_WIDTH_1 (1<<15) | |
| 390 | #define MEM_CARD_OPTION_DATA_XFR_WIDTH_4 0 | |
| 391 | ||
| 392 | #define SD_CTRL_COMMAND_INDEX(x) ((x) & 0x3f) | |
| 393 | #define SD_CTRL_COMMAND_TYPE_CMD (0 << 6) | |
| 394 | #define SD_CTRL_COMMAND_TYPE_ACMD (1 << 6) | |
| 395 | #define SD_CTRL_COMMAND_TYPE_AUTHENTICATION (2 << 6) | |
| 396 | #define SD_CTRL_COMMAND_RESPONSE_TYPE_NORMAL (0 << 8) | |
| 397 | #define SD_CTRL_COMMAND_RESPONSE_TYPE_EXT_R1 (4 << 8) | |
| 398 | #define SD_CTRL_COMMAND_RESPONSE_TYPE_EXT_R1B (5 << 8) | |
| 399 | #define SD_CTRL_COMMAND_RESPONSE_TYPE_EXT_R2 (6 << 8) | |
| 400 | #define SD_CTRL_COMMAND_RESPONSE_TYPE_EXT_R3 (7 << 8) | |
| 401 | #define SD_CTRL_COMMAND_DATA_PRESENT (1 << 11) | |
| 402 | #define SD_CTRL_COMMAND_TRANSFER_READ (1 << 12) | |
| 403 | #define SD_CTRL_COMMAND_TRANSFER_WRITE (0 << 12) | |
| 404 | #define SD_CTRL_COMMAND_MULTI_BLOCK (1 << 13) | |
| 405 | #define SD_CTRL_COMMAND_SECURITY_CMD (1 << 14) | |
| 406 | ||
| 407 | #define SD_CTRL_STOP_INTERNAL_ISSSUE_CMD12 (1 << 0) | |
| 408 | #define SD_CTRL_STOP_INTERNAL_AUTO_ISSUE_CMD12 (1 << 8) | |
| 409 | ||
| 410 | #define SD_CTRL_CARDSTATUS_RESPONSE_END (1 << 0) | |
| 411 | #define SD_CTRL_CARDSTATUS_RW_END (1 << 2) | |
| 412 | #define SD_CTRL_CARDSTATUS_CARD_REMOVED_0 (1 << 3) | |
| 413 | #define SD_CTRL_CARDSTATUS_CARD_INSERTED_0 (1 << 4) | |
| 414 | #define SD_CTRL_CARDSTATUS_SIGNAL_STATE_PRESENT_0 (1 << 5) | |
| 415 | #define SD_CTRL_CARDSTATUS_WRITE_PROTECT (1 << 7) | |
| 416 | #define SD_CTRL_CARDSTATUS_CARD_REMOVED_3 (1 << 8) | |
| 417 | #define SD_CTRL_CARDSTATUS_CARD_INSERTED_3 (1 << 9) | |
| 418 | #define SD_CTRL_CARDSTATUS_SIGNAL_STATE_PRESENT_3 (1 << 10) | |
| 419 | ||
| 420 | #define SD_CTRL_BUFFERSTATUS_CMD_INDEX_ERROR (1 << 0) | |
| 421 | #define SD_CTRL_BUFFERSTATUS_CRC_ERROR (1 << 1) | |
| 422 | #define SD_CTRL_BUFFERSTATUS_STOP_BIT_END_ERROR (1 << 2) | |
| 423 | #define SD_CTRL_BUFFERSTATUS_DATA_TIMEOUT (1 << 3) | |
| 424 | #define SD_CTRL_BUFFERSTATUS_BUFFER_OVERFLOW (1 << 4) | |
| 425 | #define SD_CTRL_BUFFERSTATUS_BUFFER_UNDERFLOW (1 << 5) | |
| 426 | #define SD_CTRL_BUFFERSTATUS_CMD_TIMEOUT (1 << 6) | |
| 427 | #define SD_CTRL_BUFFERSTATUS_UNK7 (1 << 7) | |
| 428 | #define SD_CTRL_BUFFERSTATUS_BUFFER_READ_ENABLE (1 << 8) | |
| 429 | #define SD_CTRL_BUFFERSTATUS_BUFFER_WRITE_ENABLE (1 << 9) | |
| 430 | #define SD_CTRL_BUFFERSTATUS_ILLEGAL_FUNCTION (1 << 13) | |
| 431 | #define SD_CTRL_BUFFERSTATUS_CMD_BUSY (1 << 14) | |
| 432 | #define SD_CTRL_BUFFERSTATUS_ILLEGAL_ACCESS (1 << 15) | |
| 433 | ||
| 434 | #define SD_CTRL_INTMASKCARD_RESPONSE_END (1 << 0) | |
| 435 | #define SD_CTRL_INTMASKCARD_RW_END (1 << 2) | |
| 436 | #define SD_CTRL_INTMASKCARD_CARD_REMOVED_0 (1 << 3) | |
| 437 | #define SD_CTRL_INTMASKCARD_CARD_INSERTED_0 (1 << 4) | |
| 438 | #define SD_CTRL_INTMASKCARD_SIGNAL_STATE_PRESENT_0 (1 << 5) | |
| 439 | #define SD_CTRL_INTMASKCARD_UNK6 (1 << 6) | |
| 440 | #define SD_CTRL_INTMASKCARD_WRITE_PROTECT (1 << 7) | |
| 441 | #define SD_CTRL_INTMASKCARD_CARD_REMOVED_3 (1 << 8) | |
| 442 | #define SD_CTRL_INTMASKCARD_CARD_INSERTED_3 (1 << 9) | |
| 443 | #define SD_CTRL_INTMASKCARD_SIGNAL_STATE_PRESENT_3 (1 << 10) | |
| 444 | ||
| 445 | #define SD_CTRL_INTMASKBUFFER_CMD_INDEX_ERROR (1 << 0) | |
| 446 | #define SD_CTRL_INTMASKBUFFER_CRC_ERROR (1 << 1) | |
| 447 | #define SD_CTRL_INTMASKBUFFER_STOP_BIT_END_ERROR (1 << 2) | |
| 448 | #define SD_CTRL_INTMASKBUFFER_DATA_TIMEOUT (1 << 3) | |
| 449 | #define SD_CTRL_INTMASKBUFFER_BUFFER_OVERFLOW (1 << 4) | |
| 450 | #define SD_CTRL_INTMASKBUFFER_BUFFER_UNDERFLOW (1 << 5) | |
| 451 | #define SD_CTRL_INTMASKBUFFER_CMD_TIMEOUT (1 << 6) | |
| 452 | #define SD_CTRL_INTMASKBUFFER_UNK7 (1 << 7) | |
| 453 | #define SD_CTRL_INTMASKBUFFER_BUFFER_READ_ENABLE (1 << 8) | |
| 454 | #define SD_CTRL_INTMASKBUFFER_BUFFER_WRITE_ENABLE (1 << 9) | |
| 455 | #define SD_CTRL_INTMASKBUFFER_ILLEGAL_FUNCTION (1 << 13) | |
| 456 | #define SD_CTRL_INTMASKBUFFER_CMD_BUSY (1 << 14) | |
| 457 | #define SD_CTRL_INTMASKBUFFER_ILLEGAL_ACCESS (1 << 15) | |
| 458 | ||
| 459 | #define SD_CTRL_DETAIL0_RESPONSE_CMD_ERROR (1 << 0) | |
| 460 | #define SD_CTRL_DETAIL0_END_BIT_ERROR_FOR_RESPONSE_NON_CMD12 (1 << 2) | |
| 461 | #define SD_CTRL_DETAIL0_END_BIT_ERROR_FOR_RESPONSE_CMD12 (1 << 3) | |
| 462 | #define SD_CTRL_DETAIL0_END_BIT_ERROR_FOR_READ_DATA (1 << 4) | |
| 463 | #define SD_CTRL_DETAIL0_END_BIT_ERROR_FOR_WRITE_CRC_STATUS (1 << 5) | |
| 464 | #define SD_CTRL_DETAIL0_CRC_ERROR_FOR_RESPONSE_NON_CMD12 (1 << 8) | |
| 465 | #define SD_CTRL_DETAIL0_CRC_ERROR_FOR_RESPONSE_CMD12 (1 << 9) | |
| 466 | #define SD_CTRL_DETAIL0_CRC_ERROR_FOR_READ_DATA (1 << 10) | |
| 467 | #define SD_CTRL_DETAIL0_CRC_ERROR_FOR_WRITE_CMD (1 << 11) | |
| 468 | ||
| 469 | #define SD_CTRL_DETAIL1_NO_CMD_RESPONSE (1 << 0) | |
| 470 | #define SD_CTRL_DETAIL1_TIMEOUT_READ_DATA (1 << 4) | |
| 471 | #define SD_CTRL_DETAIL1_TIMEOUT_CRS_STATUS (1 << 5) | |
| 472 | #define SD_CTRL_DETAIL1_TIMEOUT_CRC_BUSY (1 << 6) | |
| 473 | ||
| 474 | #define ASIC3_SDIO_CTRL_Base 0x1200 | |
| 475 | ||
| 476 | #define ASIC3_SDIO_CTRL_Cmd 0x00 | |
| 477 | #define ASIC3_SDIO_CTRL_CardPortSel 0x04 | |
| 478 | #define ASIC3_SDIO_CTRL_Arg0 0x08 | |
| 479 | #define ASIC3_SDIO_CTRL_Arg1 0x0C | |
| 480 | #define ASIC3_SDIO_CTRL_TransferBlockCount 0x14 | |
| 481 | #define ASIC3_SDIO_CTRL_Response0 0x18 | |
| 482 | #define ASIC3_SDIO_CTRL_Response1 0x1C | |
| 483 | #define ASIC3_SDIO_CTRL_Response2 0x20 | |
| 484 | #define ASIC3_SDIO_CTRL_Response3 0x24 | |
| 485 | #define ASIC3_SDIO_CTRL_Response4 0x28 | |
| 486 | #define ASIC3_SDIO_CTRL_Response5 0x2C | |
| 487 | #define ASIC3_SDIO_CTRL_Response6 0x30 | |
| 488 | #define ASIC3_SDIO_CTRL_Response7 0x34 | |
| 489 | #define ASIC3_SDIO_CTRL_CardStatus 0x38 | |
| 490 | #define ASIC3_SDIO_CTRL_BufferCtrl 0x3C | |
| 491 | #define ASIC3_SDIO_CTRL_IntMaskCard 0x40 | |
| 492 | #define ASIC3_SDIO_CTRL_IntMaskBuffer 0x44 | |
| 493 | #define ASIC3_SDIO_CTRL_CardXferDataLen 0x4C | |
| 494 | #define ASIC3_SDIO_CTRL_CardOptionSetup 0x50 | |
| 495 | #define ASIC3_SDIO_CTRL_ErrorStatus0 0x54 | |
| 496 | #define ASIC3_SDIO_CTRL_ErrorStatus1 0x58 | |
| 497 | #define ASIC3_SDIO_CTRL_DataPort 0x60 | |
| 498 | #define ASIC3_SDIO_CTRL_TransactionCtrl 0x68 | |
| 499 | #define ASIC3_SDIO_CTRL_CardIntCtrl 0x6C | |
| 500 | #define ASIC3_SDIO_CTRL_ClocknWaitCtrl 0x70 | |
| 501 | #define ASIC3_SDIO_CTRL_HostInformation 0x74 | |
| 502 | #define ASIC3_SDIO_CTRL_ErrorCtrl 0x78 | |
| 503 | #define ASIC3_SDIO_CTRL_LEDCtrl 0x7C | |
| 504 | #define ASIC3_SDIO_CTRL_SoftwareReset 0x1C0 | |
| 505 | ||
| 99cdb0c8 PZ |
506 | #define ASIC3_MAP_SIZE_32BIT 0x2000 |
| 507 | #define ASIC3_MAP_SIZE_16BIT 0x1000 | |
| fa9ff4b1 SO |
508 | |
| 509 | #endif /* __ASIC3_H__ */ |