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1766e7b3 DL |
1 | /* |
2 | * TI DaVinci DA8xx CHIPCFGx registers for syscon consumers. | |
3 | * | |
4 | * Copyright (C) 2016 David Lechner <david@lechnology.com> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | */ | |
16 | ||
17 | #ifndef __LINUX_MFD_DA8XX_CFGCHIP_H | |
18 | #define __LINUX_MFD_DA8XX_CFGCHIP_H | |
19 | ||
20 | #include <linux/bitops.h> | |
21 | ||
22 | /* register offset (32-bit registers) */ | |
23 | #define CFGCHIP(n) ((n) * 4) | |
24 | ||
25 | /* CFGCHIP0 (PLL0/EDMA3_0) register bits */ | |
26 | #define CFGCHIP0_PLL_MASTER_LOCK BIT(4) | |
27 | #define CFGCHIP0_EDMA30TC1DBS(n) ((n) << 2) | |
28 | #define CFGCHIP0_EDMA30TC1DBS_MASK CFGCHIP0_EDMA30TC1DBS(0x3) | |
29 | #define CFGCHIP0_EDMA30TC1DBS_16 CFGCHIP0_EDMA30TC1DBS(0x0) | |
30 | #define CFGCHIP0_EDMA30TC1DBS_32 CFGCHIP0_EDMA30TC1DBS(0x1) | |
31 | #define CFGCHIP0_EDMA30TC1DBS_64 CFGCHIP0_EDMA30TC1DBS(0x2) | |
32 | #define CFGCHIP0_EDMA30TC0DBS(n) ((n) << 0) | |
33 | #define CFGCHIP0_EDMA30TC0DBS_MASK CFGCHIP0_EDMA30TC0DBS(0x3) | |
34 | #define CFGCHIP0_EDMA30TC0DBS_16 CFGCHIP0_EDMA30TC0DBS(0x0) | |
35 | #define CFGCHIP0_EDMA30TC0DBS_32 CFGCHIP0_EDMA30TC0DBS(0x1) | |
36 | #define CFGCHIP0_EDMA30TC0DBS_64 CFGCHIP0_EDMA30TC0DBS(0x2) | |
37 | ||
38 | /* CFGCHIP1 (eCAP/HPI/EDMA3_1/eHRPWM TBCLK/McASP0 AMUTEIN) register bits */ | |
39 | #define CFGCHIP1_CAP2SRC(n) ((n) << 27) | |
40 | #define CFGCHIP1_CAP2SRC_MASK CFGCHIP1_CAP2SRC(0x1f) | |
41 | #define CFGCHIP1_CAP2SRC_ECAP_PIN CFGCHIP1_CAP2SRC(0x0) | |
42 | #define CFGCHIP1_CAP2SRC_MCASP0_TX CFGCHIP1_CAP2SRC(0x1) | |
43 | #define CFGCHIP1_CAP2SRC_MCASP0_RX CFGCHIP1_CAP2SRC(0x2) | |
44 | #define CFGCHIP1_CAP2SRC_EMAC_C0_RX_THRESHOLD CFGCHIP1_CAP2SRC(0x7) | |
45 | #define CFGCHIP1_CAP2SRC_EMAC_C0_RX CFGCHIP1_CAP2SRC(0x8) | |
46 | #define CFGCHIP1_CAP2SRC_EMAC_C0_TX CFGCHIP1_CAP2SRC(0x9) | |
47 | #define CFGCHIP1_CAP2SRC_EMAC_C0_MISC CFGCHIP1_CAP2SRC(0xa) | |
48 | #define CFGCHIP1_CAP2SRC_EMAC_C1_RX_THRESHOLD CFGCHIP1_CAP2SRC(0xb) | |
49 | #define CFGCHIP1_CAP2SRC_EMAC_C1_RX CFGCHIP1_CAP2SRC(0xc) | |
50 | #define CFGCHIP1_CAP2SRC_EMAC_C1_TX CFGCHIP1_CAP2SRC(0xd) | |
51 | #define CFGCHIP1_CAP2SRC_EMAC_C1_MISC CFGCHIP1_CAP2SRC(0xe) | |
52 | #define CFGCHIP1_CAP2SRC_EMAC_C2_RX_THRESHOLD CFGCHIP1_CAP2SRC(0xf) | |
53 | #define CFGCHIP1_CAP2SRC_EMAC_C2_RX CFGCHIP1_CAP2SRC(0x10) | |
54 | #define CFGCHIP1_CAP2SRC_EMAC_C2_TX CFGCHIP1_CAP2SRC(0x11) | |
55 | #define CFGCHIP1_CAP2SRC_EMAC_C2_MISC CFGCHIP1_CAP2SRC(0x12) | |
56 | #define CFGCHIP1_CAP1SRC(n) ((n) << 22) | |
57 | #define CFGCHIP1_CAP1SRC_MASK CFGCHIP1_CAP1SRC(0x1f) | |
58 | #define CFGCHIP1_CAP1SRC_ECAP_PIN CFGCHIP1_CAP1SRC(0x0) | |
59 | #define CFGCHIP1_CAP1SRC_MCASP0_TX CFGCHIP1_CAP1SRC(0x1) | |
60 | #define CFGCHIP1_CAP1SRC_MCASP0_RX CFGCHIP1_CAP1SRC(0x2) | |
61 | #define CFGCHIP1_CAP1SRC_EMAC_C0_RX_THRESHOLD CFGCHIP1_CAP1SRC(0x7) | |
62 | #define CFGCHIP1_CAP1SRC_EMAC_C0_RX CFGCHIP1_CAP1SRC(0x8) | |
63 | #define CFGCHIP1_CAP1SRC_EMAC_C0_TX CFGCHIP1_CAP1SRC(0x9) | |
64 | #define CFGCHIP1_CAP1SRC_EMAC_C0_MISC CFGCHIP1_CAP1SRC(0xa) | |
65 | #define CFGCHIP1_CAP1SRC_EMAC_C1_RX_THRESHOLD CFGCHIP1_CAP1SRC(0xb) | |
66 | #define CFGCHIP1_CAP1SRC_EMAC_C1_RX CFGCHIP1_CAP1SRC(0xc) | |
67 | #define CFGCHIP1_CAP1SRC_EMAC_C1_TX CFGCHIP1_CAP1SRC(0xd) | |
68 | #define CFGCHIP1_CAP1SRC_EMAC_C1_MISC CFGCHIP1_CAP1SRC(0xe) | |
69 | #define CFGCHIP1_CAP1SRC_EMAC_C2_RX_THRESHOLD CFGCHIP1_CAP1SRC(0xf) | |
70 | #define CFGCHIP1_CAP1SRC_EMAC_C2_RX CFGCHIP1_CAP1SRC(0x10) | |
71 | #define CFGCHIP1_CAP1SRC_EMAC_C2_TX CFGCHIP1_CAP1SRC(0x11) | |
72 | #define CFGCHIP1_CAP1SRC_EMAC_C2_MISC CFGCHIP1_CAP1SRC(0x12) | |
73 | #define CFGCHIP1_CAP0SRC(n) ((n) << 17) | |
74 | #define CFGCHIP1_CAP0SRC_MASK CFGCHIP1_CAP0SRC(0x1f) | |
75 | #define CFGCHIP1_CAP0SRC_ECAP_PIN CFGCHIP1_CAP0SRC(0x0) | |
76 | #define CFGCHIP1_CAP0SRC_MCASP0_TX CFGCHIP1_CAP0SRC(0x1) | |
77 | #define CFGCHIP1_CAP0SRC_MCASP0_RX CFGCHIP1_CAP0SRC(0x2) | |
78 | #define CFGCHIP1_CAP0SRC_EMAC_C0_RX_THRESHOLD CFGCHIP1_CAP0SRC(0x7) | |
79 | #define CFGCHIP1_CAP0SRC_EMAC_C0_RX CFGCHIP1_CAP0SRC(0x8) | |
80 | #define CFGCHIP1_CAP0SRC_EMAC_C0_TX CFGCHIP1_CAP0SRC(0x9) | |
81 | #define CFGCHIP1_CAP0SRC_EMAC_C0_MISC CFGCHIP1_CAP0SRC(0xa) | |
82 | #define CFGCHIP1_CAP0SRC_EMAC_C1_RX_THRESHOLD CFGCHIP1_CAP0SRC(0xb) | |
83 | #define CFGCHIP1_CAP0SRC_EMAC_C1_RX CFGCHIP1_CAP0SRC(0xc) | |
84 | #define CFGCHIP1_CAP0SRC_EMAC_C1_TX CFGCHIP1_CAP0SRC(0xd) | |
85 | #define CFGCHIP1_CAP0SRC_EMAC_C1_MISC CFGCHIP1_CAP0SRC(0xe) | |
86 | #define CFGCHIP1_CAP0SRC_EMAC_C2_RX_THRESHOLD CFGCHIP1_CAP0SRC(0xf) | |
87 | #define CFGCHIP1_CAP0SRC_EMAC_C2_RX CFGCHIP1_CAP0SRC(0x10) | |
88 | #define CFGCHIP1_CAP0SRC_EMAC_C2_TX CFGCHIP1_CAP0SRC(0x11) | |
89 | #define CFGCHIP1_CAP0SRC_EMAC_C2_MISC CFGCHIP1_CAP0SRC(0x12) | |
90 | #define CFGCHIP1_HPIBYTEAD BIT(16) | |
91 | #define CFGCHIP1_HPIENA BIT(15) | |
92 | #define CFGCHIP0_EDMA31TC0DBS(n) ((n) << 13) | |
93 | #define CFGCHIP0_EDMA31TC0DBS_MASK CFGCHIP0_EDMA31TC0DBS(0x3) | |
94 | #define CFGCHIP0_EDMA31TC0DBS_16 CFGCHIP0_EDMA31TC0DBS(0x0) | |
95 | #define CFGCHIP0_EDMA31TC0DBS_32 CFGCHIP0_EDMA31TC0DBS(0x1) | |
96 | #define CFGCHIP0_EDMA31TC0DBS_64 CFGCHIP0_EDMA31TC0DBS(0x2) | |
97 | #define CFGCHIP1_TBCLKSYNC BIT(12) | |
98 | #define CFGCHIP1_AMUTESEL0(n) ((n) << 0) | |
99 | #define CFGCHIP1_AMUTESEL0_MASK CFGCHIP1_AMUTESEL0(0xf) | |
100 | #define CFGCHIP1_AMUTESEL0_LOW CFGCHIP1_AMUTESEL0(0x0) | |
101 | #define CFGCHIP1_AMUTESEL0_BANK_0 CFGCHIP1_AMUTESEL0(0x1) | |
102 | #define CFGCHIP1_AMUTESEL0_BANK_1 CFGCHIP1_AMUTESEL0(0x2) | |
103 | #define CFGCHIP1_AMUTESEL0_BANK_2 CFGCHIP1_AMUTESEL0(0x3) | |
104 | #define CFGCHIP1_AMUTESEL0_BANK_3 CFGCHIP1_AMUTESEL0(0x4) | |
105 | #define CFGCHIP1_AMUTESEL0_BANK_4 CFGCHIP1_AMUTESEL0(0x5) | |
106 | #define CFGCHIP1_AMUTESEL0_BANK_5 CFGCHIP1_AMUTESEL0(0x6) | |
107 | #define CFGCHIP1_AMUTESEL0_BANK_6 CFGCHIP1_AMUTESEL0(0x7) | |
108 | #define CFGCHIP1_AMUTESEL0_BANK_7 CFGCHIP1_AMUTESEL0(0x8) | |
109 | ||
110 | /* CFGCHIP2 (USB PHY) register bits */ | |
111 | #define CFGCHIP2_PHYCLKGD BIT(17) | |
112 | #define CFGCHIP2_VBUSSENSE BIT(16) | |
113 | #define CFGCHIP2_RESET BIT(15) | |
114 | #define CFGCHIP2_OTGMODE(n) ((n) << 13) | |
115 | #define CFGCHIP2_OTGMODE_MASK CFGCHIP2_OTGMODE(0x3) | |
116 | #define CFGCHIP2_OTGMODE_NO_OVERRIDE CFGCHIP2_OTGMODE(0x0) | |
117 | #define CFGCHIP2_OTGMODE_FORCE_HOST CFGCHIP2_OTGMODE(0x1) | |
118 | #define CFGCHIP2_OTGMODE_FORCE_DEVICE CFGCHIP2_OTGMODE(0x2) | |
119 | #define CFGCHIP2_OTGMODE_FORCE_HOST_VBUS_LOW CFGCHIP2_OTGMODE(0x3) | |
120 | #define CFGCHIP2_USB1PHYCLKMUX BIT(12) | |
121 | #define CFGCHIP2_USB2PHYCLKMUX BIT(11) | |
122 | #define CFGCHIP2_PHYPWRDN BIT(10) | |
123 | #define CFGCHIP2_OTGPWRDN BIT(9) | |
124 | #define CFGCHIP2_DATPOL BIT(8) | |
125 | #define CFGCHIP2_USB1SUSPENDM BIT(7) | |
126 | #define CFGCHIP2_PHY_PLLON BIT(6) | |
127 | #define CFGCHIP2_SESENDEN BIT(5) | |
128 | #define CFGCHIP2_VBDTCTEN BIT(4) | |
129 | #define CFGCHIP2_REFFREQ(n) ((n) << 0) | |
130 | #define CFGCHIP2_REFFREQ_MASK CFGCHIP2_REFFREQ(0xf) | |
131 | #define CFGCHIP2_REFFREQ_12MHZ CFGCHIP2_REFFREQ(0x1) | |
132 | #define CFGCHIP2_REFFREQ_24MHZ CFGCHIP2_REFFREQ(0x2) | |
133 | #define CFGCHIP2_REFFREQ_48MHZ CFGCHIP2_REFFREQ(0x3) | |
134 | #define CFGCHIP2_REFFREQ_19_2MHZ CFGCHIP2_REFFREQ(0x4) | |
135 | #define CFGCHIP2_REFFREQ_38_4MHZ CFGCHIP2_REFFREQ(0x5) | |
136 | #define CFGCHIP2_REFFREQ_13MHZ CFGCHIP2_REFFREQ(0x6) | |
137 | #define CFGCHIP2_REFFREQ_26MHZ CFGCHIP2_REFFREQ(0x7) | |
138 | #define CFGCHIP2_REFFREQ_20MHZ CFGCHIP2_REFFREQ(0x8) | |
139 | #define CFGCHIP2_REFFREQ_40MHZ CFGCHIP2_REFFREQ(0x9) | |
140 | ||
141 | /* CFGCHIP3 (EMAC/uPP/PLL1/ASYNC3/PRU/DIV4.5/EMIFA) register bits */ | |
142 | #define CFGCHIP3_RMII_SEL BIT(8) | |
143 | #define CFGCHIP3_UPP_TX_CLKSRC BIT(6) | |
144 | #define CFGCHIP3_PLL1_MASTER_LOCK BIT(5) | |
145 | #define CFGCHIP3_ASYNC3_CLKSRC BIT(4) | |
146 | #define CFGCHIP3_PRUEVTSEL BIT(3) | |
147 | #define CFGCHIP3_DIV45PENA BIT(2) | |
148 | #define CFGCHIP3_EMA_CLKSRC BIT(1) | |
149 | ||
150 | /* CFGCHIP4 (McASP0 AMUNTEIN) register bits */ | |
151 | #define CFGCHIP4_AMUTECLR0 BIT(0) | |
152 | ||
153 | #endif /* __LINUX_MFD_DA8XX_CFGCHIP_H */ |