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fea799e3 MN |
1 | /* |
2 | * Copyright (C) ST Ericsson SA 2011 | |
3 | * | |
4 | * License Terms: GNU General Public License v2 | |
5 | * | |
6 | * STE Ux500 PRCMU API | |
7 | */ | |
8 | #ifndef __MACH_PRCMU_H | |
9 | #define __MACH_PRCMU_H | |
10 | ||
11 | #include <linux/interrupt.h> | |
12 | #include <linux/notifier.h> | |
0508901c | 13 | #include <linux/err.h> |
fea799e3 MN |
14 | |
15 | /* PRCMU Wakeup defines */ | |
16 | enum prcmu_wakeup_index { | |
17 | PRCMU_WAKEUP_INDEX_RTC, | |
18 | PRCMU_WAKEUP_INDEX_RTT0, | |
19 | PRCMU_WAKEUP_INDEX_RTT1, | |
20 | PRCMU_WAKEUP_INDEX_HSI0, | |
21 | PRCMU_WAKEUP_INDEX_HSI1, | |
22 | PRCMU_WAKEUP_INDEX_USB, | |
23 | PRCMU_WAKEUP_INDEX_ABB, | |
24 | PRCMU_WAKEUP_INDEX_ABB_FIFO, | |
25 | PRCMU_WAKEUP_INDEX_ARM, | |
26 | PRCMU_WAKEUP_INDEX_CD_IRQ, | |
27 | NUM_PRCMU_WAKEUP_INDICES | |
28 | }; | |
29 | #define PRCMU_WAKEUP(_name) (BIT(PRCMU_WAKEUP_INDEX_##_name)) | |
30 | ||
31 | /* EPOD (power domain) IDs */ | |
32 | ||
33 | /* | |
34 | * DB8500 EPODs | |
35 | * - EPOD_ID_SVAMMDSP: power domain for SVA MMDSP | |
36 | * - EPOD_ID_SVAPIPE: power domain for SVA pipe | |
37 | * - EPOD_ID_SIAMMDSP: power domain for SIA MMDSP | |
38 | * - EPOD_ID_SIAPIPE: power domain for SIA pipe | |
39 | * - EPOD_ID_SGA: power domain for SGA | |
40 | * - EPOD_ID_B2R2_MCDE: power domain for B2R2 and MCDE | |
41 | * - EPOD_ID_ESRAM12: power domain for ESRAM 1 and 2 | |
42 | * - EPOD_ID_ESRAM34: power domain for ESRAM 3 and 4 | |
43 | * - NUM_EPOD_ID: number of power domains | |
44 | * | |
45 | * TODO: These should be prefixed. | |
46 | */ | |
47 | #define EPOD_ID_SVAMMDSP 0 | |
48 | #define EPOD_ID_SVAPIPE 1 | |
49 | #define EPOD_ID_SIAMMDSP 2 | |
50 | #define EPOD_ID_SIAPIPE 3 | |
51 | #define EPOD_ID_SGA 4 | |
52 | #define EPOD_ID_B2R2_MCDE 5 | |
53 | #define EPOD_ID_ESRAM12 6 | |
54 | #define EPOD_ID_ESRAM34 7 | |
55 | #define NUM_EPOD_ID 8 | |
56 | ||
57 | /* | |
58 | * DB5500 EPODs | |
59 | */ | |
60 | #define DB5500_EPOD_ID_BASE 0x0100 | |
61 | #define DB5500_EPOD_ID_SGA (DB5500_EPOD_ID_BASE + 0) | |
62 | #define DB5500_EPOD_ID_HVA (DB5500_EPOD_ID_BASE + 1) | |
63 | #define DB5500_EPOD_ID_SIA (DB5500_EPOD_ID_BASE + 2) | |
64 | #define DB5500_EPOD_ID_DISP (DB5500_EPOD_ID_BASE + 3) | |
65 | #define DB5500_EPOD_ID_ESRAM12 (DB5500_EPOD_ID_BASE + 6) | |
66 | #define DB5500_NUM_EPOD_ID 7 | |
67 | ||
68 | /* | |
69 | * state definition for EPOD (power domain) | |
70 | * - EPOD_STATE_NO_CHANGE: The EPOD should remain unchanged | |
71 | * - EPOD_STATE_OFF: The EPOD is switched off | |
72 | * - EPOD_STATE_RAMRET: The EPOD is switched off with its internal RAM in | |
73 | * retention | |
74 | * - EPOD_STATE_ON_CLK_OFF: The EPOD is switched on, clock is still off | |
75 | * - EPOD_STATE_ON: Same as above, but with clock enabled | |
76 | */ | |
77 | #define EPOD_STATE_NO_CHANGE 0x00 | |
78 | #define EPOD_STATE_OFF 0x01 | |
79 | #define EPOD_STATE_RAMRET 0x02 | |
80 | #define EPOD_STATE_ON_CLK_OFF 0x03 | |
81 | #define EPOD_STATE_ON 0x04 | |
82 | ||
6b6fae2b MN |
83 | /* DB5500 CLKOUT IDs */ |
84 | enum { | |
85 | DB5500_CLKOUT0 = 0, | |
86 | DB5500_CLKOUT1, | |
87 | }; | |
88 | ||
89 | /* DB5500 CLKOUTx sources */ | |
90 | enum { | |
91 | DB5500_CLKOUT_REF_CLK_SEL0, | |
92 | DB5500_CLKOUT_RTC_CLK0_SEL0, | |
93 | DB5500_CLKOUT_ULP_CLK_SEL0, | |
94 | DB5500_CLKOUT_STATIC0, | |
95 | DB5500_CLKOUT_REFCLK, | |
96 | DB5500_CLKOUT_ULPCLK, | |
97 | DB5500_CLKOUT_ARMCLK, | |
98 | DB5500_CLKOUT_SYSACC0CLK, | |
99 | DB5500_CLKOUT_SOC0PLLCLK, | |
100 | DB5500_CLKOUT_SOC1PLLCLK, | |
101 | DB5500_CLKOUT_DDRPLLCLK, | |
102 | DB5500_CLKOUT_TVCLK, | |
103 | DB5500_CLKOUT_IRDACLK, | |
104 | }; | |
105 | ||
fea799e3 MN |
106 | /* |
107 | * CLKOUT sources | |
108 | */ | |
109 | #define PRCMU_CLKSRC_CLK38M 0x00 | |
110 | #define PRCMU_CLKSRC_ACLK 0x01 | |
111 | #define PRCMU_CLKSRC_SYSCLK 0x02 | |
112 | #define PRCMU_CLKSRC_LCDCLK 0x03 | |
113 | #define PRCMU_CLKSRC_SDMMCCLK 0x04 | |
114 | #define PRCMU_CLKSRC_TVCLK 0x05 | |
115 | #define PRCMU_CLKSRC_TIMCLK 0x06 | |
116 | #define PRCMU_CLKSRC_CLK009 0x07 | |
117 | /* These are only valid for CLKOUT1: */ | |
118 | #define PRCMU_CLKSRC_SIAMMDSPCLK 0x40 | |
119 | #define PRCMU_CLKSRC_I2CCLK 0x41 | |
120 | #define PRCMU_CLKSRC_MSP02CLK 0x42 | |
121 | #define PRCMU_CLKSRC_ARMPLL_OBSCLK 0x43 | |
122 | #define PRCMU_CLKSRC_HSIRXCLK 0x44 | |
123 | #define PRCMU_CLKSRC_HSITXCLK 0x45 | |
124 | #define PRCMU_CLKSRC_ARMCLKFIX 0x46 | |
125 | #define PRCMU_CLKSRC_HDMICLK 0x47 | |
126 | ||
127 | /* | |
128 | * Clock identifiers. | |
129 | */ | |
130 | enum prcmu_clock { | |
131 | PRCMU_SGACLK, | |
132 | PRCMU_UARTCLK, | |
133 | PRCMU_MSP02CLK, | |
134 | PRCMU_MSP1CLK, | |
135 | PRCMU_I2CCLK, | |
136 | PRCMU_SDMMCCLK, | |
6b6fae2b | 137 | PRCMU_SPARE1CLK, |
fea799e3 MN |
138 | PRCMU_SLIMCLK, |
139 | PRCMU_PER1CLK, | |
140 | PRCMU_PER2CLK, | |
141 | PRCMU_PER3CLK, | |
142 | PRCMU_PER5CLK, | |
143 | PRCMU_PER6CLK, | |
144 | PRCMU_PER7CLK, | |
145 | PRCMU_LCDCLK, | |
146 | PRCMU_BMLCLK, | |
147 | PRCMU_HSITXCLK, | |
148 | PRCMU_HSIRXCLK, | |
149 | PRCMU_HDMICLK, | |
150 | PRCMU_APEATCLK, | |
151 | PRCMU_APETRACECLK, | |
152 | PRCMU_MCDECLK, | |
153 | PRCMU_IPI2CCLK, | |
154 | PRCMU_DSIALTCLK, | |
155 | PRCMU_DMACLK, | |
156 | PRCMU_B2R2CLK, | |
157 | PRCMU_TVCLK, | |
158 | PRCMU_SSPCLK, | |
159 | PRCMU_RNGCLK, | |
160 | PRCMU_UICCCLK, | |
161 | PRCMU_PWMCLK, | |
162 | PRCMU_IRDACLK, | |
163 | PRCMU_IRRCCLK, | |
164 | PRCMU_SIACLK, | |
165 | PRCMU_SVACLK, | |
6b6fae2b | 166 | PRCMU_ACLK, |
fea799e3 MN |
167 | PRCMU_NUM_REG_CLOCKS, |
168 | PRCMU_SYSCLK = PRCMU_NUM_REG_CLOCKS, | |
6b6fae2b | 169 | PRCMU_CDCLK, |
fea799e3 MN |
170 | PRCMU_TIMCLK, |
171 | PRCMU_PLLSOC0, | |
172 | PRCMU_PLLSOC1, | |
173 | PRCMU_PLLDDR, | |
6b6fae2b MN |
174 | PRCMU_PLLDSI, |
175 | PRCMU_DSI0CLK, | |
176 | PRCMU_DSI1CLK, | |
177 | PRCMU_DSI0ESCCLK, | |
178 | PRCMU_DSI1ESCCLK, | |
179 | PRCMU_DSI2ESCCLK, | |
fea799e3 MN |
180 | }; |
181 | ||
182 | /** | |
183 | * enum ape_opp - APE OPP states definition | |
184 | * @APE_OPP_INIT: | |
185 | * @APE_NO_CHANGE: The APE operating point is unchanged | |
186 | * @APE_100_OPP: The new APE operating point is ape100opp | |
187 | * @APE_50_OPP: 50% | |
4d64d2e3 | 188 | * @APE_50_PARTLY_25_OPP: 50%, except some clocks at 25%. |
fea799e3 MN |
189 | */ |
190 | enum ape_opp { | |
191 | APE_OPP_INIT = 0x00, | |
192 | APE_NO_CHANGE = 0x01, | |
193 | APE_100_OPP = 0x02, | |
4d64d2e3 MN |
194 | APE_50_OPP = 0x03, |
195 | APE_50_PARTLY_25_OPP = 0xFF, | |
fea799e3 MN |
196 | }; |
197 | ||
198 | /** | |
199 | * enum arm_opp - ARM OPP states definition | |
200 | * @ARM_OPP_INIT: | |
201 | * @ARM_NO_CHANGE: The ARM operating point is unchanged | |
202 | * @ARM_100_OPP: The new ARM operating point is arm100opp | |
203 | * @ARM_50_OPP: The new ARM operating point is arm50opp | |
204 | * @ARM_MAX_OPP: Operating point is "max" (more than 100) | |
205 | * @ARM_MAX_FREQ100OPP: Set max opp if available, else 100 | |
206 | * @ARM_EXTCLK: The new ARM operating point is armExtClk | |
207 | */ | |
208 | enum arm_opp { | |
209 | ARM_OPP_INIT = 0x00, | |
210 | ARM_NO_CHANGE = 0x01, | |
211 | ARM_100_OPP = 0x02, | |
212 | ARM_50_OPP = 0x03, | |
213 | ARM_MAX_OPP = 0x04, | |
214 | ARM_MAX_FREQ100OPP = 0x05, | |
215 | ARM_EXTCLK = 0x07 | |
216 | }; | |
217 | ||
218 | /** | |
219 | * enum ddr_opp - DDR OPP states definition | |
220 | * @DDR_100_OPP: The new DDR operating point is ddr100opp | |
221 | * @DDR_50_OPP: The new DDR operating point is ddr50opp | |
222 | * @DDR_25_OPP: The new DDR operating point is ddr25opp | |
223 | */ | |
224 | enum ddr_opp { | |
225 | DDR_100_OPP = 0x00, | |
226 | DDR_50_OPP = 0x01, | |
227 | DDR_25_OPP = 0x02, | |
228 | }; | |
229 | ||
230 | /* | |
231 | * Definitions for controlling ESRAM0 in deep sleep. | |
232 | */ | |
233 | #define ESRAM0_DEEP_SLEEP_STATE_OFF 1 | |
234 | #define ESRAM0_DEEP_SLEEP_STATE_RET 2 | |
235 | ||
236 | /** | |
237 | * enum ddr_pwrst - DDR power states definition | |
238 | * @DDR_PWR_STATE_UNCHANGED: SDRAM and DDR controller state is unchanged | |
239 | * @DDR_PWR_STATE_ON: | |
240 | * @DDR_PWR_STATE_OFFLOWLAT: | |
241 | * @DDR_PWR_STATE_OFFHIGHLAT: | |
242 | */ | |
243 | enum ddr_pwrst { | |
244 | DDR_PWR_STATE_UNCHANGED = 0x00, | |
245 | DDR_PWR_STATE_ON = 0x01, | |
246 | DDR_PWR_STATE_OFFLOWLAT = 0x02, | |
247 | DDR_PWR_STATE_OFFHIGHLAT = 0x03 | |
248 | }; | |
249 | ||
250 | #include <linux/mfd/db8500-prcmu.h> | |
251 | #include <linux/mfd/db5500-prcmu.h> | |
252 | ||
253 | #if defined(CONFIG_UX500_SOC_DB8500) || defined(CONFIG_UX500_SOC_DB5500) | |
254 | ||
0508901c MN |
255 | #include <mach/id.h> |
256 | ||
fea799e3 MN |
257 | static inline void __init prcmu_early_init(void) |
258 | { | |
0508901c | 259 | if (cpu_is_u5500()) |
fea799e3 MN |
260 | return db5500_prcmu_early_init(); |
261 | else | |
262 | return db8500_prcmu_early_init(); | |
263 | } | |
264 | ||
265 | static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk, | |
266 | bool keep_ap_pll) | |
267 | { | |
0508901c | 268 | if (cpu_is_u5500()) |
fea799e3 MN |
269 | return db5500_prcmu_set_power_state(state, keep_ulp_clk, |
270 | keep_ap_pll); | |
271 | else | |
272 | return db8500_prcmu_set_power_state(state, keep_ulp_clk, | |
273 | keep_ap_pll); | |
274 | } | |
275 | ||
4d64d2e3 MN |
276 | static inline u8 prcmu_get_power_state_result(void) |
277 | { | |
278 | if (cpu_is_u5500()) | |
279 | return -EINVAL; | |
280 | else | |
281 | return db8500_prcmu_get_power_state_result(); | |
282 | } | |
283 | ||
485540dc DL |
284 | static inline int prcmu_gic_decouple(void) |
285 | { | |
286 | if (cpu_is_u5500()) | |
287 | return -EINVAL; | |
288 | else | |
289 | return db8500_prcmu_gic_decouple(); | |
290 | } | |
291 | ||
292 | static inline int prcmu_gic_recouple(void) | |
293 | { | |
294 | if (cpu_is_u5500()) | |
295 | return -EINVAL; | |
296 | else | |
297 | return db8500_prcmu_gic_recouple(); | |
298 | } | |
299 | ||
cc9a0f68 DL |
300 | static inline bool prcmu_gic_pending_irq(void) |
301 | { | |
302 | if (cpu_is_u5500()) | |
303 | return -EINVAL; | |
304 | else | |
305 | return db8500_prcmu_gic_pending_irq(); | |
306 | } | |
307 | ||
34fe6f10 DL |
308 | static inline bool prcmu_is_cpu_in_wfi(int cpu) |
309 | { | |
310 | if (cpu_is_u5500()) | |
311 | return -EINVAL; | |
312 | else | |
313 | return db8500_prcmu_is_cpu_in_wfi(cpu); | |
314 | } | |
315 | ||
9f60d33e DL |
316 | static inline int prcmu_copy_gic_settings(void) |
317 | { | |
318 | if (cpu_is_u5500()) | |
319 | return -EINVAL; | |
320 | else | |
321 | return db8500_prcmu_copy_gic_settings(); | |
322 | } | |
323 | ||
9ab492e1 DL |
324 | static inline bool prcmu_pending_irq(void) |
325 | { | |
326 | if (cpu_is_u5500()) | |
327 | return -EINVAL; | |
328 | else | |
329 | return db8500_prcmu_pending_irq(); | |
330 | } | |
331 | ||
fea799e3 MN |
332 | static inline int prcmu_set_epod(u16 epod_id, u8 epod_state) |
333 | { | |
0508901c | 334 | if (cpu_is_u5500()) |
73180f85 | 335 | return -EINVAL; |
fea799e3 MN |
336 | else |
337 | return db8500_prcmu_set_epod(epod_id, epod_state); | |
338 | } | |
339 | ||
340 | static inline void prcmu_enable_wakeups(u32 wakeups) | |
341 | { | |
0508901c | 342 | if (cpu_is_u5500()) |
fea799e3 MN |
343 | db5500_prcmu_enable_wakeups(wakeups); |
344 | else | |
345 | db8500_prcmu_enable_wakeups(wakeups); | |
346 | } | |
347 | ||
348 | static inline void prcmu_disable_wakeups(void) | |
349 | { | |
350 | prcmu_enable_wakeups(0); | |
351 | } | |
352 | ||
353 | static inline void prcmu_config_abb_event_readout(u32 abb_events) | |
354 | { | |
0508901c | 355 | if (cpu_is_u5500()) |
fea799e3 MN |
356 | db5500_prcmu_config_abb_event_readout(abb_events); |
357 | else | |
358 | db8500_prcmu_config_abb_event_readout(abb_events); | |
359 | } | |
360 | ||
361 | static inline void prcmu_get_abb_event_buffer(void __iomem **buf) | |
362 | { | |
0508901c | 363 | if (cpu_is_u5500()) |
fea799e3 MN |
364 | db5500_prcmu_get_abb_event_buffer(buf); |
365 | else | |
366 | db8500_prcmu_get_abb_event_buffer(buf); | |
367 | } | |
368 | ||
369 | int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size); | |
370 | int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size); | |
371 | ||
372 | int prcmu_config_clkout(u8 clkout, u8 source, u8 div); | |
373 | ||
374 | static inline int prcmu_request_clock(u8 clock, bool enable) | |
375 | { | |
0508901c | 376 | if (cpu_is_u5500()) |
fea799e3 MN |
377 | return db5500_prcmu_request_clock(clock, enable); |
378 | else | |
379 | return db8500_prcmu_request_clock(clock, enable); | |
380 | } | |
381 | ||
0508901c MN |
382 | unsigned long prcmu_clock_rate(u8 clock); |
383 | long prcmu_round_clock_rate(u8 clock, unsigned long rate); | |
384 | int prcmu_set_clock_rate(u8 clock, unsigned long rate); | |
385 | ||
386 | static inline int prcmu_set_ddr_opp(u8 opp) | |
387 | { | |
388 | if (cpu_is_u5500()) | |
389 | return -EINVAL; | |
390 | else | |
391 | return db8500_prcmu_set_ddr_opp(opp); | |
392 | } | |
393 | static inline int prcmu_get_ddr_opp(void) | |
394 | { | |
395 | if (cpu_is_u5500()) | |
396 | return -EINVAL; | |
397 | else | |
398 | return db8500_prcmu_get_ddr_opp(); | |
399 | } | |
fea799e3 MN |
400 | |
401 | static inline int prcmu_set_arm_opp(u8 opp) | |
402 | { | |
0508901c | 403 | if (cpu_is_u5500()) |
73180f85 | 404 | return -EINVAL; |
fea799e3 MN |
405 | else |
406 | return db8500_prcmu_set_arm_opp(opp); | |
407 | } | |
408 | ||
409 | static inline int prcmu_get_arm_opp(void) | |
410 | { | |
0508901c | 411 | if (cpu_is_u5500()) |
73180f85 | 412 | return -EINVAL; |
fea799e3 MN |
413 | else |
414 | return db8500_prcmu_get_arm_opp(); | |
415 | } | |
416 | ||
0508901c MN |
417 | static inline int prcmu_set_ape_opp(u8 opp) |
418 | { | |
419 | if (cpu_is_u5500()) | |
420 | return -EINVAL; | |
421 | else | |
422 | return db8500_prcmu_set_ape_opp(opp); | |
423 | } | |
424 | ||
425 | static inline int prcmu_get_ape_opp(void) | |
426 | { | |
427 | if (cpu_is_u5500()) | |
428 | return -EINVAL; | |
429 | else | |
430 | return db8500_prcmu_get_ape_opp(); | |
431 | } | |
432 | ||
fea799e3 MN |
433 | static inline void prcmu_system_reset(u16 reset_code) |
434 | { | |
0508901c | 435 | if (cpu_is_u5500()) |
fea799e3 MN |
436 | return db5500_prcmu_system_reset(reset_code); |
437 | else | |
438 | return db8500_prcmu_system_reset(reset_code); | |
439 | } | |
440 | ||
441 | static inline u16 prcmu_get_reset_code(void) | |
442 | { | |
0508901c | 443 | if (cpu_is_u5500()) |
fea799e3 MN |
444 | return db5500_prcmu_get_reset_code(); |
445 | else | |
446 | return db8500_prcmu_get_reset_code(); | |
447 | } | |
448 | ||
449 | void prcmu_ac_wake_req(void); | |
450 | void prcmu_ac_sleep_req(void); | |
0508901c MN |
451 | static inline void prcmu_modem_reset(void) |
452 | { | |
453 | if (cpu_is_u5500()) | |
454 | return; | |
455 | else | |
456 | return db8500_prcmu_modem_reset(); | |
457 | } | |
458 | ||
fea799e3 MN |
459 | static inline bool prcmu_is_ac_wake_requested(void) |
460 | { | |
0508901c | 461 | if (cpu_is_u5500()) |
fea799e3 MN |
462 | return db5500_prcmu_is_ac_wake_requested(); |
463 | else | |
464 | return db8500_prcmu_is_ac_wake_requested(); | |
465 | } | |
466 | ||
467 | static inline int prcmu_set_display_clocks(void) | |
468 | { | |
0508901c | 469 | if (cpu_is_u5500()) |
fea799e3 MN |
470 | return db5500_prcmu_set_display_clocks(); |
471 | else | |
472 | return db8500_prcmu_set_display_clocks(); | |
473 | } | |
474 | ||
475 | static inline int prcmu_disable_dsipll(void) | |
476 | { | |
0508901c | 477 | if (cpu_is_u5500()) |
fea799e3 MN |
478 | return db5500_prcmu_disable_dsipll(); |
479 | else | |
480 | return db8500_prcmu_disable_dsipll(); | |
481 | } | |
482 | ||
483 | static inline int prcmu_enable_dsipll(void) | |
484 | { | |
0508901c | 485 | if (cpu_is_u5500()) |
fea799e3 MN |
486 | return db5500_prcmu_enable_dsipll(); |
487 | else | |
488 | return db8500_prcmu_enable_dsipll(); | |
489 | } | |
490 | ||
491 | static inline int prcmu_config_esram0_deep_sleep(u8 state) | |
492 | { | |
0508901c | 493 | if (cpu_is_u5500()) |
73180f85 | 494 | return -EINVAL; |
fea799e3 MN |
495 | else |
496 | return db8500_prcmu_config_esram0_deep_sleep(state); | |
497 | } | |
0508901c MN |
498 | |
499 | static inline int prcmu_config_hotdog(u8 threshold) | |
500 | { | |
501 | if (cpu_is_u5500()) | |
502 | return -EINVAL; | |
503 | else | |
504 | return db8500_prcmu_config_hotdog(threshold); | |
505 | } | |
506 | ||
507 | static inline int prcmu_config_hotmon(u8 low, u8 high) | |
508 | { | |
509 | if (cpu_is_u5500()) | |
510 | return -EINVAL; | |
511 | else | |
512 | return db8500_prcmu_config_hotmon(low, high); | |
513 | } | |
514 | ||
515 | static inline int prcmu_start_temp_sense(u16 cycles32k) | |
516 | { | |
517 | if (cpu_is_u5500()) | |
518 | return -EINVAL; | |
519 | else | |
520 | return db8500_prcmu_start_temp_sense(cycles32k); | |
521 | } | |
522 | ||
523 | static inline int prcmu_stop_temp_sense(void) | |
524 | { | |
525 | if (cpu_is_u5500()) | |
526 | return -EINVAL; | |
527 | else | |
528 | return db8500_prcmu_stop_temp_sense(); | |
529 | } | |
530 | ||
b4a6dbd5 MN |
531 | static inline u32 prcmu_read(unsigned int reg) |
532 | { | |
533 | if (cpu_is_u5500()) | |
534 | return -EINVAL; | |
535 | else | |
536 | return db8500_prcmu_read(reg); | |
537 | } | |
538 | ||
539 | static inline void prcmu_write(unsigned int reg, u32 value) | |
540 | { | |
541 | if (cpu_is_u5500()) | |
542 | return; | |
543 | else | |
544 | db8500_prcmu_write(reg, value); | |
545 | } | |
546 | ||
547 | static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value) | |
548 | { | |
549 | if (cpu_is_u5500()) | |
550 | return; | |
551 | else | |
552 | db8500_prcmu_write_masked(reg, mask, value); | |
553 | } | |
554 | ||
0508901c MN |
555 | static inline int prcmu_enable_a9wdog(u8 id) |
556 | { | |
557 | if (cpu_is_u5500()) | |
558 | return -EINVAL; | |
559 | else | |
560 | return db8500_prcmu_enable_a9wdog(id); | |
561 | } | |
562 | ||
563 | static inline int prcmu_disable_a9wdog(u8 id) | |
564 | { | |
565 | if (cpu_is_u5500()) | |
566 | return -EINVAL; | |
567 | else | |
568 | return db8500_prcmu_disable_a9wdog(id); | |
569 | } | |
570 | ||
571 | static inline int prcmu_kick_a9wdog(u8 id) | |
572 | { | |
573 | if (cpu_is_u5500()) | |
574 | return -EINVAL; | |
575 | else | |
576 | return db8500_prcmu_kick_a9wdog(id); | |
577 | } | |
578 | ||
579 | static inline int prcmu_load_a9wdog(u8 id, u32 timeout) | |
580 | { | |
581 | if (cpu_is_u5500()) | |
582 | return -EINVAL; | |
583 | else | |
584 | return db8500_prcmu_load_a9wdog(id, timeout); | |
585 | } | |
586 | ||
587 | static inline int prcmu_config_a9wdog(u8 num, bool sleep_auto_off) | |
588 | { | |
589 | if (cpu_is_u5500()) | |
590 | return -EINVAL; | |
591 | else | |
592 | return db8500_prcmu_config_a9wdog(num, sleep_auto_off); | |
593 | } | |
fea799e3 MN |
594 | #else |
595 | ||
596 | static inline void __init prcmu_early_init(void) {} | |
597 | ||
598 | static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk, | |
599 | bool keep_ap_pll) | |
600 | { | |
601 | return 0; | |
602 | } | |
603 | ||
604 | static inline int prcmu_set_epod(u16 epod_id, u8 epod_state) | |
605 | { | |
606 | return 0; | |
607 | } | |
608 | ||
609 | static inline void prcmu_enable_wakeups(u32 wakeups) {} | |
610 | ||
611 | static inline void prcmu_disable_wakeups(void) {} | |
612 | ||
613 | static inline int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size) | |
614 | { | |
615 | return -ENOSYS; | |
616 | } | |
617 | ||
618 | static inline int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size) | |
619 | { | |
620 | return -ENOSYS; | |
621 | } | |
622 | ||
623 | static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div) | |
624 | { | |
625 | return 0; | |
626 | } | |
627 | ||
628 | static inline int prcmu_request_clock(u8 clock, bool enable) | |
629 | { | |
630 | return 0; | |
6b6fae2b MN |
631 | } |
632 | ||
633 | static inline long prcmu_round_clock_rate(u8 clock, unsigned long rate) | |
634 | { | |
635 | return 0; | |
636 | } | |
637 | ||
638 | static inline int prcmu_set_clock_rate(u8 clock, unsigned long rate) | |
639 | { | |
640 | return 0; | |
641 | } | |
642 | ||
643 | static inline unsigned long prcmu_clock_rate(u8 clock) | |
644 | { | |
645 | return 0; | |
fea799e3 MN |
646 | } |
647 | ||
648 | static inline int prcmu_set_ape_opp(u8 opp) | |
649 | { | |
650 | return 0; | |
651 | } | |
652 | ||
653 | static inline int prcmu_get_ape_opp(void) | |
654 | { | |
655 | return APE_100_OPP; | |
656 | } | |
657 | ||
658 | static inline int prcmu_set_arm_opp(u8 opp) | |
659 | { | |
660 | return 0; | |
661 | } | |
662 | ||
663 | static inline int prcmu_get_arm_opp(void) | |
664 | { | |
665 | return ARM_100_OPP; | |
666 | } | |
667 | ||
668 | static inline int prcmu_set_ddr_opp(u8 opp) | |
669 | { | |
670 | return 0; | |
671 | } | |
672 | ||
673 | static inline int prcmu_get_ddr_opp(void) | |
674 | { | |
675 | return DDR_100_OPP; | |
676 | } | |
677 | ||
678 | static inline void prcmu_system_reset(u16 reset_code) {} | |
679 | ||
680 | static inline u16 prcmu_get_reset_code(void) | |
681 | { | |
682 | return 0; | |
683 | } | |
684 | ||
685 | static inline void prcmu_ac_wake_req(void) {} | |
686 | ||
687 | static inline void prcmu_ac_sleep_req(void) {} | |
688 | ||
689 | static inline void prcmu_modem_reset(void) {} | |
690 | ||
691 | static inline bool prcmu_is_ac_wake_requested(void) | |
692 | { | |
693 | return false; | |
694 | } | |
695 | ||
696 | static inline int prcmu_set_display_clocks(void) | |
697 | { | |
698 | return 0; | |
699 | } | |
700 | ||
701 | static inline int prcmu_disable_dsipll(void) | |
702 | { | |
703 | return 0; | |
704 | } | |
705 | ||
706 | static inline int prcmu_enable_dsipll(void) | |
707 | { | |
708 | return 0; | |
709 | } | |
710 | ||
711 | static inline int prcmu_config_esram0_deep_sleep(u8 state) | |
712 | { | |
713 | return 0; | |
714 | } | |
715 | ||
716 | static inline void prcmu_config_abb_event_readout(u32 abb_events) {} | |
717 | ||
718 | static inline void prcmu_get_abb_event_buffer(void __iomem **buf) | |
719 | { | |
720 | *buf = NULL; | |
721 | } | |
722 | ||
0508901c MN |
723 | static inline int prcmu_config_hotdog(u8 threshold) |
724 | { | |
725 | return 0; | |
726 | } | |
727 | ||
728 | static inline int prcmu_config_hotmon(u8 low, u8 high) | |
729 | { | |
730 | return 0; | |
731 | } | |
732 | ||
733 | static inline int prcmu_start_temp_sense(u16 cycles32k) | |
734 | { | |
735 | return 0; | |
736 | } | |
737 | ||
738 | static inline int prcmu_stop_temp_sense(void) | |
739 | { | |
740 | return 0; | |
741 | } | |
742 | ||
b4a6dbd5 MN |
743 | static inline u32 prcmu_read(unsigned int reg) |
744 | { | |
745 | return 0; | |
746 | } | |
747 | ||
748 | static inline void prcmu_write(unsigned int reg, u32 value) {} | |
749 | ||
750 | static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value) {} | |
751 | ||
752 | #endif | |
753 | ||
754 | static inline void prcmu_set(unsigned int reg, u32 bits) | |
755 | { | |
756 | prcmu_write_masked(reg, bits, bits); | |
757 | } | |
758 | ||
759 | static inline void prcmu_clear(unsigned int reg, u32 bits) | |
760 | { | |
761 | prcmu_write_masked(reg, bits, 0); | |
762 | } | |
763 | ||
764 | #if defined(CONFIG_UX500_SOC_DB8500) || defined(CONFIG_UX500_SOC_DB5500) | |
765 | ||
766 | /** | |
767 | * prcmu_enable_spi2 - Enables pin muxing for SPI2 on OtherAlternateC1. | |
768 | */ | |
769 | static inline void prcmu_enable_spi2(void) | |
770 | { | |
771 | if (cpu_is_u8500()) | |
772 | prcmu_set(DB8500_PRCM_GPIOCR, DB8500_PRCM_GPIOCR_SPI2_SELECT); | |
773 | } | |
774 | ||
775 | /** | |
776 | * prcmu_disable_spi2 - Disables pin muxing for SPI2 on OtherAlternateC1. | |
777 | */ | |
778 | static inline void prcmu_disable_spi2(void) | |
779 | { | |
780 | if (cpu_is_u8500()) | |
781 | prcmu_clear(DB8500_PRCM_GPIOCR, DB8500_PRCM_GPIOCR_SPI2_SELECT); | |
782 | } | |
783 | ||
784 | /** | |
785 | * prcmu_enable_stm_mod_uart - Enables pin muxing for STMMOD | |
786 | * and UARTMOD on OtherAlternateC3. | |
787 | */ | |
788 | static inline void prcmu_enable_stm_mod_uart(void) | |
789 | { | |
790 | if (cpu_is_u8500()) { | |
791 | prcmu_set(DB8500_PRCM_GPIOCR, | |
792 | (DB8500_PRCM_GPIOCR_DBG_STM_MOD_CMD1 | | |
793 | DB8500_PRCM_GPIOCR_DBG_UARTMOD_CMD0)); | |
794 | } | |
795 | } | |
796 | ||
797 | /** | |
798 | * prcmu_disable_stm_mod_uart - Disables pin muxing for STMMOD | |
799 | * and UARTMOD on OtherAlternateC3. | |
800 | */ | |
801 | static inline void prcmu_disable_stm_mod_uart(void) | |
802 | { | |
803 | if (cpu_is_u8500()) { | |
804 | prcmu_clear(DB8500_PRCM_GPIOCR, | |
805 | (DB8500_PRCM_GPIOCR_DBG_STM_MOD_CMD1 | | |
806 | DB8500_PRCM_GPIOCR_DBG_UARTMOD_CMD0)); | |
807 | } | |
808 | } | |
809 | ||
810 | /** | |
811 | * prcmu_enable_stm_ape - Enables pin muxing for STM APE on OtherAlternateC1. | |
812 | */ | |
813 | static inline void prcmu_enable_stm_ape(void) | |
814 | { | |
815 | if (cpu_is_u8500()) { | |
816 | prcmu_set(DB8500_PRCM_GPIOCR, | |
817 | DB8500_PRCM_GPIOCR_DBG_STM_APE_CMD); | |
818 | } | |
819 | } | |
820 | ||
821 | /** | |
822 | * prcmu_disable_stm_ape - Disables pin muxing for STM APE on OtherAlternateC1. | |
823 | */ | |
824 | static inline void prcmu_disable_stm_ape(void) | |
825 | { | |
826 | if (cpu_is_u8500()) { | |
827 | prcmu_clear(DB8500_PRCM_GPIOCR, | |
828 | DB8500_PRCM_GPIOCR_DBG_STM_APE_CMD); | |
829 | } | |
830 | } | |
831 | ||
832 | #else | |
833 | ||
834 | static inline void prcmu_enable_spi2(void) {} | |
835 | static inline void prcmu_disable_spi2(void) {} | |
836 | static inline void prcmu_enable_stm_mod_uart(void) {} | |
837 | static inline void prcmu_disable_stm_mod_uart(void) {} | |
838 | static inline void prcmu_enable_stm_ape(void) {} | |
839 | static inline void prcmu_disable_stm_ape(void) {} | |
840 | ||
fea799e3 MN |
841 | #endif |
842 | ||
843 | /* PRCMU QoS APE OPP class */ | |
844 | #define PRCMU_QOS_APE_OPP 1 | |
845 | #define PRCMU_QOS_DDR_OPP 2 | |
4d64d2e3 | 846 | #define PRCMU_QOS_ARM_OPP 3 |
fea799e3 MN |
847 | #define PRCMU_QOS_DEFAULT_VALUE -1 |
848 | ||
4d64d2e3 | 849 | #ifdef CONFIG_DBX500_PRCMU_QOS_POWER |
fea799e3 MN |
850 | |
851 | unsigned long prcmu_qos_get_cpufreq_opp_delay(void); | |
852 | void prcmu_qos_set_cpufreq_opp_delay(unsigned long); | |
853 | void prcmu_qos_force_opp(int, s32); | |
854 | int prcmu_qos_requirement(int pm_qos_class); | |
855 | int prcmu_qos_add_requirement(int pm_qos_class, char *name, s32 value); | |
856 | int prcmu_qos_update_requirement(int pm_qos_class, char *name, s32 new_value); | |
857 | void prcmu_qos_remove_requirement(int pm_qos_class, char *name); | |
858 | int prcmu_qos_add_notifier(int prcmu_qos_class, | |
859 | struct notifier_block *notifier); | |
860 | int prcmu_qos_remove_notifier(int prcmu_qos_class, | |
861 | struct notifier_block *notifier); | |
862 | ||
863 | #else | |
864 | ||
865 | static inline unsigned long prcmu_qos_get_cpufreq_opp_delay(void) | |
866 | { | |
867 | return 0; | |
868 | } | |
869 | ||
870 | static inline void prcmu_qos_set_cpufreq_opp_delay(unsigned long n) {} | |
871 | ||
872 | static inline void prcmu_qos_force_opp(int prcmu_qos_class, s32 i) {} | |
873 | ||
874 | static inline int prcmu_qos_requirement(int prcmu_qos_class) | |
875 | { | |
876 | return 0; | |
877 | } | |
878 | ||
879 | static inline int prcmu_qos_add_requirement(int prcmu_qos_class, | |
880 | char *name, s32 value) | |
881 | { | |
882 | return 0; | |
883 | } | |
884 | ||
885 | static inline int prcmu_qos_update_requirement(int prcmu_qos_class, | |
886 | char *name, s32 new_value) | |
887 | { | |
888 | return 0; | |
889 | } | |
890 | ||
891 | static inline void prcmu_qos_remove_requirement(int prcmu_qos_class, char *name) | |
892 | { | |
893 | } | |
894 | ||
895 | static inline int prcmu_qos_add_notifier(int prcmu_qos_class, | |
896 | struct notifier_block *notifier) | |
897 | { | |
898 | return 0; | |
899 | } | |
900 | static inline int prcmu_qos_remove_notifier(int prcmu_qos_class, | |
901 | struct notifier_block *notifier) | |
902 | { | |
903 | return 0; | |
904 | } | |
905 | ||
906 | #endif | |
907 | ||
908 | #endif /* __MACH_PRCMU_H */ |