projects / mirror_ubuntu-eoan-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 26c7e05a | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 1f5a371c | 2 | /* |
| 26c7e05a | 3 | * Core interface for Intel MSIC |
| 1f5a371c MW |
4 | * |
| 5 | * Copyright (C) 2011, Intel Corporation | |
| 6 | * Author: Mika Westerberg <mika.westerberg@linux.intel.com> | |
| 1f5a371c MW |
7 | */ |
| 8 | ||
| 9 | #ifndef __LINUX_MFD_INTEL_MSIC_H__ | |
| 10 | #define __LINUX_MFD_INTEL_MSIC_H__ | |
| 11 | ||
| 12 | /* ID */ | |
| 13 | #define INTEL_MSIC_ID0 0x000 /* RO */ | |
| 14 | #define INTEL_MSIC_ID1 0x001 /* RO */ | |
| 15 | ||
| 16 | /* IRQ */ | |
| 17 | #define INTEL_MSIC_IRQLVL1 0x002 | |
| 18 | #define INTEL_MSIC_ADC1INT 0x003 | |
| 19 | #define INTEL_MSIC_CCINT 0x004 | |
| 20 | #define INTEL_MSIC_PWRSRCINT 0x005 | |
| 21 | #define INTEL_MSIC_PWRSRCINT1 0x006 | |
| 22 | #define INTEL_MSIC_CHRINT 0x007 | |
| 23 | #define INTEL_MSIC_CHRINT1 0x008 | |
| 24 | #define INTEL_MSIC_RTCIRQ 0x009 | |
| 25 | #define INTEL_MSIC_GPIO0LVIRQ 0x00a | |
| 26 | #define INTEL_MSIC_GPIO1LVIRQ 0x00b | |
| 27 | #define INTEL_MSIC_GPIOHVIRQ 0x00c | |
| 28 | #define INTEL_MSIC_VRINT 0x00d | |
| 29 | #define INTEL_MSIC_OCAUDIO 0x00e | |
| 30 | #define INTEL_MSIC_ACCDET 0x00f | |
| 31 | #define INTEL_MSIC_RESETIRQ1 0x010 | |
| 32 | #define INTEL_MSIC_RESETIRQ2 0x011 | |
| 33 | #define INTEL_MSIC_MADC1INT 0x012 | |
| 34 | #define INTEL_MSIC_MCCINT 0x013 | |
| 35 | #define INTEL_MSIC_MPWRSRCINT 0x014 | |
| 36 | #define INTEL_MSIC_MPWRSRCINT1 0x015 | |
| 37 | #define INTEL_MSIC_MCHRINT 0x016 | |
| 38 | #define INTEL_MSIC_MCHRINT1 0x017 | |
| 39 | #define INTEL_MSIC_RTCIRQMASK 0x018 | |
| 40 | #define INTEL_MSIC_GPIO0LVIRQMASK 0x019 | |
| 41 | #define INTEL_MSIC_GPIO1LVIRQMASK 0x01a | |
| 42 | #define INTEL_MSIC_GPIOHVIRQMASK 0x01b | |
| 43 | #define INTEL_MSIC_VRINTMASK 0x01c | |
| 44 | #define INTEL_MSIC_OCAUDIOMASK 0x01d | |
| 45 | #define INTEL_MSIC_ACCDETMASK 0x01e | |
| 46 | #define INTEL_MSIC_RESETIRQ1MASK 0x01f | |
| 47 | #define INTEL_MSIC_RESETIRQ2MASK 0x020 | |
| 48 | #define INTEL_MSIC_IRQLVL1MSK 0x021 | |
| 49 | #define INTEL_MSIC_PBCONFIG 0x03e | |
| 50 | #define INTEL_MSIC_PBSTATUS 0x03f /* RO */ | |
| 51 | ||
| 52 | /* GPIO */ | |
| 53 | #define INTEL_MSIC_GPIO0LV7CTLO 0x040 | |
| 54 | #define INTEL_MSIC_GPIO0LV6CTLO 0x041 | |
| 55 | #define INTEL_MSIC_GPIO0LV5CTLO 0x042 | |
| 56 | #define INTEL_MSIC_GPIO0LV4CTLO 0x043 | |
| 57 | #define INTEL_MSIC_GPIO0LV3CTLO 0x044 | |
| 58 | #define INTEL_MSIC_GPIO0LV2CTLO 0x045 | |
| 59 | #define INTEL_MSIC_GPIO0LV1CTLO 0x046 | |
| 60 | #define INTEL_MSIC_GPIO0LV0CTLO 0x047 | |
| 61 | #define INTEL_MSIC_GPIO1LV7CTLOS 0x048 | |
| 62 | #define INTEL_MSIC_GPIO1LV6CTLO 0x049 | |
| 63 | #define INTEL_MSIC_GPIO1LV5CTLO 0x04a | |
| 64 | #define INTEL_MSIC_GPIO1LV4CTLO 0x04b | |
| 65 | #define INTEL_MSIC_GPIO1LV3CTLO 0x04c | |
| 66 | #define INTEL_MSIC_GPIO1LV2CTLO 0x04d | |
| 67 | #define INTEL_MSIC_GPIO1LV1CTLO 0x04e | |
| 68 | #define INTEL_MSIC_GPIO1LV0CTLO 0x04f | |
| 69 | #define INTEL_MSIC_GPIO0LV7CTLI 0x050 | |
| 70 | #define INTEL_MSIC_GPIO0LV6CTLI 0x051 | |
| 71 | #define INTEL_MSIC_GPIO0LV5CTLI 0x052 | |
| 72 | #define INTEL_MSIC_GPIO0LV4CTLI 0x053 | |
| 73 | #define INTEL_MSIC_GPIO0LV3CTLI 0x054 | |
| 74 | #define INTEL_MSIC_GPIO0LV2CTLI 0x055 | |
| 75 | #define INTEL_MSIC_GPIO0LV1CTLI 0x056 | |
| 76 | #define INTEL_MSIC_GPIO0LV0CTLI 0x057 | |
| 77 | #define INTEL_MSIC_GPIO1LV7CTLIS 0x058 | |
| 78 | #define INTEL_MSIC_GPIO1LV6CTLI 0x059 | |
| 79 | #define INTEL_MSIC_GPIO1LV5CTLI 0x05a | |
| 80 | #define INTEL_MSIC_GPIO1LV4CTLI 0x05b | |
| 81 | #define INTEL_MSIC_GPIO1LV3CTLI 0x05c | |
| 82 | #define INTEL_MSIC_GPIO1LV2CTLI 0x05d | |
| 83 | #define INTEL_MSIC_GPIO1LV1CTLI 0x05e | |
| 84 | #define INTEL_MSIC_GPIO1LV0CTLI 0x05f | |
| 85 | #define INTEL_MSIC_PWM0CLKDIV1 0x061 | |
| 86 | #define INTEL_MSIC_PWM0CLKDIV0 0x062 | |
| 87 | #define INTEL_MSIC_PWM1CLKDIV1 0x063 | |
| 88 | #define INTEL_MSIC_PWM1CLKDIV0 0x064 | |
| 89 | #define INTEL_MSIC_PWM2CLKDIV1 0x065 | |
| 90 | #define INTEL_MSIC_PWM2CLKDIV0 0x066 | |
| 91 | #define INTEL_MSIC_PWM0DUTYCYCLE 0x067 | |
| 92 | #define INTEL_MSIC_PWM1DUTYCYCLE 0x068 | |
| 93 | #define INTEL_MSIC_PWM2DUTYCYCLE 0x069 | |
| 94 | #define INTEL_MSIC_GPIO0HV3CTLO 0x06d | |
| 95 | #define INTEL_MSIC_GPIO0HV2CTLO 0x06e | |
| 96 | #define INTEL_MSIC_GPIO0HV1CTLO 0x06f | |
| 97 | #define INTEL_MSIC_GPIO0HV0CTLO 0x070 | |
| 98 | #define INTEL_MSIC_GPIO1HV3CTLO 0x071 | |
| 99 | #define INTEL_MSIC_GPIO1HV2CTLO 0x072 | |
| 100 | #define INTEL_MSIC_GPIO1HV1CTLO 0x073 | |
| 101 | #define INTEL_MSIC_GPIO1HV0CTLO 0x074 | |
| 102 | #define INTEL_MSIC_GPIO0HV3CTLI 0x075 | |
| 103 | #define INTEL_MSIC_GPIO0HV2CTLI 0x076 | |
| 104 | #define INTEL_MSIC_GPIO0HV1CTLI 0x077 | |
| 105 | #define INTEL_MSIC_GPIO0HV0CTLI 0x078 | |
| 106 | #define INTEL_MSIC_GPIO1HV3CTLI 0x079 | |
| 107 | #define INTEL_MSIC_GPIO1HV2CTLI 0x07a | |
| 108 | #define INTEL_MSIC_GPIO1HV1CTLI 0x07b | |
| 109 | #define INTEL_MSIC_GPIO1HV0CTLI 0x07c | |
| 110 | ||
| 111 | /* SVID */ | |
| 112 | #define INTEL_MSIC_SVIDCTRL0 0x080 | |
| 113 | #define INTEL_MSIC_SVIDCTRL1 0x081 | |
| 114 | #define INTEL_MSIC_SVIDCTRL2 0x082 | |
| 115 | #define INTEL_MSIC_SVIDTXLASTPKT3 0x083 /* RO */ | |
| 116 | #define INTEL_MSIC_SVIDTXLASTPKT2 0x084 /* RO */ | |
| 117 | #define INTEL_MSIC_SVIDTXLASTPKT1 0x085 /* RO */ | |
| 118 | #define INTEL_MSIC_SVIDTXLASTPKT0 0x086 /* RO */ | |
| 119 | #define INTEL_MSIC_SVIDPKTOUTBYTE3 0x087 | |
| 120 | #define INTEL_MSIC_SVIDPKTOUTBYTE2 0x088 | |
| 121 | #define INTEL_MSIC_SVIDPKTOUTBYTE1 0x089 | |
| 122 | #define INTEL_MSIC_SVIDPKTOUTBYTE0 0x08a | |
| 123 | #define INTEL_MSIC_SVIDRXVPDEBUG1 0x08b | |
| 124 | #define INTEL_MSIC_SVIDRXVPDEBUG0 0x08c | |
| 125 | #define INTEL_MSIC_SVIDRXLASTPKT3 0x08d /* RO */ | |
| 126 | #define INTEL_MSIC_SVIDRXLASTPKT2 0x08e /* RO */ | |
| 127 | #define INTEL_MSIC_SVIDRXLASTPKT1 0x08f /* RO */ | |
| 128 | #define INTEL_MSIC_SVIDRXLASTPKT0 0x090 /* RO */ | |
| 129 | #define INTEL_MSIC_SVIDRXCHKSTATUS3 0x091 /* RO */ | |
| 130 | #define INTEL_MSIC_SVIDRXCHKSTATUS2 0x092 /* RO */ | |
| 131 | #define INTEL_MSIC_SVIDRXCHKSTATUS1 0x093 /* RO */ | |
| 132 | #define INTEL_MSIC_SVIDRXCHKSTATUS0 0x094 /* RO */ | |
| 133 | ||
| 134 | /* VREG */ | |
| 135 | #define INTEL_MSIC_VCCLATCH 0x0c0 | |
| 136 | #define INTEL_MSIC_VNNLATCH 0x0c1 | |
| 137 | #define INTEL_MSIC_VCCCNT 0x0c2 | |
| 138 | #define INTEL_MSIC_SMPSRAMP 0x0c3 | |
| 139 | #define INTEL_MSIC_VNNCNT 0x0c4 | |
| 140 | #define INTEL_MSIC_VNNAONCNT 0x0c5 | |
| 141 | #define INTEL_MSIC_VCC122AONCNT 0x0c6 | |
| 142 | #define INTEL_MSIC_V180AONCNT 0x0c7 | |
| 143 | #define INTEL_MSIC_V500CNT 0x0c8 | |
| 144 | #define INTEL_MSIC_VIHFCNT 0x0c9 | |
| 145 | #define INTEL_MSIC_LDORAMP1 0x0ca | |
| 146 | #define INTEL_MSIC_LDORAMP2 0x0cb | |
| 147 | #define INTEL_MSIC_VCC108AONCNT 0x0cc | |
| 148 | #define INTEL_MSIC_VCC108ASCNT 0x0cd | |
| 149 | #define INTEL_MSIC_VCC108CNT 0x0ce | |
| 150 | #define INTEL_MSIC_VCCA100ASCNT 0x0cf | |
| 151 | #define INTEL_MSIC_VCCA100CNT 0x0d0 | |
| 152 | #define INTEL_MSIC_VCC180AONCNT 0x0d1 | |
| 153 | #define INTEL_MSIC_VCC180CNT 0x0d2 | |
| 154 | #define INTEL_MSIC_VCC330CNT 0x0d3 | |
| 155 | #define INTEL_MSIC_VUSB330CNT 0x0d4 | |
| 156 | #define INTEL_MSIC_VCCSDIOCNT 0x0d5 | |
| 157 | #define INTEL_MSIC_VPROG1CNT 0x0d6 | |
| 158 | #define INTEL_MSIC_VPROG2CNT 0x0d7 | |
| 159 | #define INTEL_MSIC_VEMMCSCNT 0x0d8 | |
| 160 | #define INTEL_MSIC_VEMMC1CNT 0x0d9 | |
| 161 | #define INTEL_MSIC_VEMMC2CNT 0x0da | |
| 162 | #define INTEL_MSIC_VAUDACNT 0x0db | |
| 163 | #define INTEL_MSIC_VHSPCNT 0x0dc | |
| 164 | #define INTEL_MSIC_VHSNCNT 0x0dd | |
| 165 | #define INTEL_MSIC_VHDMICNT 0x0de | |
| 166 | #define INTEL_MSIC_VOTGCNT 0x0df | |
| 167 | #define INTEL_MSIC_V1P35CNT 0x0e0 | |
| 168 | #define INTEL_MSIC_V330AONCNT 0x0e1 | |
| 169 | ||
| 170 | /* RESET */ | |
| 171 | #define INTEL_MSIC_CHIPCNTRL 0x100 /* WO */ | |
| 172 | #define INTEL_MSIC_ERCONFIG 0x101 | |
| 173 | ||
| 174 | /* BURST */ | |
| 175 | #define INTEL_MSIC_BATCURRENTLIMIT12 0x102 | |
| 176 | #define INTEL_MSIC_BATTIMELIMIT12 0x103 | |
| 177 | #define INTEL_MSIC_BATTIMELIMIT3 0x104 | |
| 178 | #define INTEL_MSIC_BATTIMEDB 0x105 | |
| 179 | #define INTEL_MSIC_BRSTCONFIGOUTPUTS 0x106 | |
| 180 | #define INTEL_MSIC_BRSTCONFIGACTIONS 0x107 | |
| 181 | #define INTEL_MSIC_BURSTCONTROLSTATUS 0x108 | |
| 182 | ||
| 183 | /* RTC */ | |
| 184 | #define INTEL_MSIC_RTCB1 0x140 /* RO */ | |
| 185 | #define INTEL_MSIC_RTCB2 0x141 /* RO */ | |
| 186 | #define INTEL_MSIC_RTCB3 0x142 /* RO */ | |
| 187 | #define INTEL_MSIC_RTCB4 0x143 /* RO */ | |
| 188 | #define INTEL_MSIC_RTCOB1 0x144 | |
| 189 | #define INTEL_MSIC_RTCOB2 0x145 | |
| 190 | #define INTEL_MSIC_RTCOB3 0x146 | |
| 191 | #define INTEL_MSIC_RTCOB4 0x147 | |
| 192 | #define INTEL_MSIC_RTCAB1 0x148 | |
| 193 | #define INTEL_MSIC_RTCAB2 0x149 | |
| 194 | #define INTEL_MSIC_RTCAB3 0x14a | |
| 195 | #define INTEL_MSIC_RTCAB4 0x14b | |
| 196 | #define INTEL_MSIC_RTCWAB1 0x14c | |
| 197 | #define INTEL_MSIC_RTCWAB2 0x14d | |
| 198 | #define INTEL_MSIC_RTCWAB3 0x14e | |
| 199 | #define INTEL_MSIC_RTCWAB4 0x14f | |
| 200 | #define INTEL_MSIC_RTCSC1 0x150 | |
| 201 | #define INTEL_MSIC_RTCSC2 0x151 | |
| 202 | #define INTEL_MSIC_RTCSC3 0x152 | |
| 203 | #define INTEL_MSIC_RTCSC4 0x153 | |
| 204 | #define INTEL_MSIC_RTCSTATUS 0x154 /* RO */ | |
| 205 | #define INTEL_MSIC_RTCCONFIG1 0x155 | |
| 206 | #define INTEL_MSIC_RTCCONFIG2 0x156 | |
| 207 | ||
| 208 | /* CHARGER */ | |
| 209 | #define INTEL_MSIC_BDTIMER 0x180 | |
| 210 | #define INTEL_MSIC_BATTRMV 0x181 | |
| 211 | #define INTEL_MSIC_VBUSDET 0x182 | |
| 212 | #define INTEL_MSIC_VBUSDET1 0x183 | |
| 213 | #define INTEL_MSIC_ADPHVDET 0x184 | |
| 214 | #define INTEL_MSIC_ADPLVDET 0x185 | |
| 215 | #define INTEL_MSIC_ADPDETDBDM 0x186 | |
| 216 | #define INTEL_MSIC_LOWBATTDET 0x187 | |
| 217 | #define INTEL_MSIC_CHRCTRL 0x188 | |
| 218 | #define INTEL_MSIC_CHRCVOLTAGE 0x189 | |
| 219 | #define INTEL_MSIC_CHRCCURRENT 0x18a | |
| 220 | #define INTEL_MSIC_SPCHARGER 0x18b | |
| 221 | #define INTEL_MSIC_CHRTTIME 0x18c | |
| 222 | #define INTEL_MSIC_CHRCTRL1 0x18d | |
| 223 | #define INTEL_MSIC_PWRSRCLMT 0x18e | |
| 224 | #define INTEL_MSIC_CHRSTWDT 0x18f | |
| 225 | #define INTEL_MSIC_WDTWRITE 0x190 /* WO */ | |
| 226 | #define INTEL_MSIC_CHRSAFELMT 0x191 | |
| 227 | #define INTEL_MSIC_SPWRSRCINT 0x192 /* RO */ | |
| 228 | #define INTEL_MSIC_SPWRSRCINT1 0x193 /* RO */ | |
| 229 | #define INTEL_MSIC_CHRLEDPWM 0x194 | |
| 230 | #define INTEL_MSIC_CHRLEDCTRL 0x195 | |
| 231 | ||
| 232 | /* ADC */ | |
| 233 | #define INTEL_MSIC_ADC1CNTL1 0x1c0 | |
| 234 | #define INTEL_MSIC_ADC1CNTL2 0x1c1 | |
| 235 | #define INTEL_MSIC_ADC1CNTL3 0x1c2 | |
| 236 | #define INTEL_MSIC_ADC1OFFSETH 0x1c3 /* RO */ | |
| 237 | #define INTEL_MSIC_ADC1OFFSETL 0x1c4 /* RO */ | |
| 238 | #define INTEL_MSIC_ADC1ADDR0 0x1c5 | |
| 239 | #define INTEL_MSIC_ADC1ADDR1 0x1c6 | |
| 240 | #define INTEL_MSIC_ADC1ADDR2 0x1c7 | |
| 241 | #define INTEL_MSIC_ADC1ADDR3 0x1c8 | |
| 242 | #define INTEL_MSIC_ADC1ADDR4 0x1c9 | |
| 243 | #define INTEL_MSIC_ADC1ADDR5 0x1ca | |
| 244 | #define INTEL_MSIC_ADC1ADDR6 0x1cb | |
| 245 | #define INTEL_MSIC_ADC1ADDR7 0x1cc | |
| 246 | #define INTEL_MSIC_ADC1ADDR8 0x1cd | |
| 247 | #define INTEL_MSIC_ADC1ADDR9 0x1ce | |
| 248 | #define INTEL_MSIC_ADC1ADDR10 0x1cf | |
| 249 | #define INTEL_MSIC_ADC1ADDR11 0x1d0 | |
| 250 | #define INTEL_MSIC_ADC1ADDR12 0x1d1 | |
| 251 | #define INTEL_MSIC_ADC1ADDR13 0x1d2 | |
| 252 | #define INTEL_MSIC_ADC1ADDR14 0x1d3 | |
| 253 | #define INTEL_MSIC_ADC1SNS0H 0x1d4 /* RO */ | |
| 254 | #define INTEL_MSIC_ADC1SNS0L 0x1d5 /* RO */ | |
| 255 | #define INTEL_MSIC_ADC1SNS1H 0x1d6 /* RO */ | |
| 256 | #define INTEL_MSIC_ADC1SNS1L 0x1d7 /* RO */ | |
| 257 | #define INTEL_MSIC_ADC1SNS2H 0x1d8 /* RO */ | |
| 258 | #define INTEL_MSIC_ADC1SNS2L 0x1d9 /* RO */ | |
| 259 | #define INTEL_MSIC_ADC1SNS3H 0x1da /* RO */ | |
| 260 | #define INTEL_MSIC_ADC1SNS3L 0x1db /* RO */ | |
| 261 | #define INTEL_MSIC_ADC1SNS4H 0x1dc /* RO */ | |
| 262 | #define INTEL_MSIC_ADC1SNS4L 0x1dd /* RO */ | |
| 263 | #define INTEL_MSIC_ADC1SNS5H 0x1de /* RO */ | |
| 264 | #define INTEL_MSIC_ADC1SNS5L 0x1df /* RO */ | |
| 265 | #define INTEL_MSIC_ADC1SNS6H 0x1e0 /* RO */ | |
| 266 | #define INTEL_MSIC_ADC1SNS6L 0x1e1 /* RO */ | |
| 267 | #define INTEL_MSIC_ADC1SNS7H 0x1e2 /* RO */ | |
| 268 | #define INTEL_MSIC_ADC1SNS7L 0x1e3 /* RO */ | |
| 269 | #define INTEL_MSIC_ADC1SNS8H 0x1e4 /* RO */ | |
| 270 | #define INTEL_MSIC_ADC1SNS8L 0x1e5 /* RO */ | |
| 271 | #define INTEL_MSIC_ADC1SNS9H 0x1e6 /* RO */ | |
| 272 | #define INTEL_MSIC_ADC1SNS9L 0x1e7 /* RO */ | |
| 273 | #define INTEL_MSIC_ADC1SNS10H 0x1e8 /* RO */ | |
| 274 | #define INTEL_MSIC_ADC1SNS10L 0x1e9 /* RO */ | |
| 275 | #define INTEL_MSIC_ADC1SNS11H 0x1ea /* RO */ | |
| 276 | #define INTEL_MSIC_ADC1SNS11L 0x1eb /* RO */ | |
| 277 | #define INTEL_MSIC_ADC1SNS12H 0x1ec /* RO */ | |
| 278 | #define INTEL_MSIC_ADC1SNS12L 0x1ed /* RO */ | |
| 279 | #define INTEL_MSIC_ADC1SNS13H 0x1ee /* RO */ | |
| 280 | #define INTEL_MSIC_ADC1SNS13L 0x1ef /* RO */ | |
| 281 | #define INTEL_MSIC_ADC1SNS14H 0x1f0 /* RO */ | |
| 282 | #define INTEL_MSIC_ADC1SNS14L 0x1f1 /* RO */ | |
| 283 | #define INTEL_MSIC_ADC1BV0H 0x1f2 /* RO */ | |
| 284 | #define INTEL_MSIC_ADC1BV0L 0x1f3 /* RO */ | |
| 285 | #define INTEL_MSIC_ADC1BV1H 0x1f4 /* RO */ | |
| 286 | #define INTEL_MSIC_ADC1BV1L 0x1f5 /* RO */ | |
| 287 | #define INTEL_MSIC_ADC1BV2H 0x1f6 /* RO */ | |
| 288 | #define INTEL_MSIC_ADC1BV2L 0x1f7 /* RO */ | |
| 289 | #define INTEL_MSIC_ADC1BV3H 0x1f8 /* RO */ | |
| 290 | #define INTEL_MSIC_ADC1BV3L 0x1f9 /* RO */ | |
| 291 | #define INTEL_MSIC_ADC1BI0H 0x1fa /* RO */ | |
| 292 | #define INTEL_MSIC_ADC1BI0L 0x1fb /* RO */ | |
| 293 | #define INTEL_MSIC_ADC1BI1H 0x1fc /* RO */ | |
| 294 | #define INTEL_MSIC_ADC1BI1L 0x1fd /* RO */ | |
| 295 | #define INTEL_MSIC_ADC1BI2H 0x1fe /* RO */ | |
| 296 | #define INTEL_MSIC_ADC1BI2L 0x1ff /* RO */ | |
| 297 | #define INTEL_MSIC_ADC1BI3H 0x200 /* RO */ | |
| 298 | #define INTEL_MSIC_ADC1BI3L 0x201 /* RO */ | |
| 299 | #define INTEL_MSIC_CCCNTL 0x202 | |
| 300 | #define INTEL_MSIC_CCOFFSETH 0x203 /* RO */ | |
| 301 | #define INTEL_MSIC_CCOFFSETL 0x204 /* RO */ | |
| 302 | #define INTEL_MSIC_CCADCHA 0x205 /* RO */ | |
| 303 | #define INTEL_MSIC_CCADCLA 0x206 /* RO */ | |
| 304 | ||
| 305 | /* AUDIO */ | |
| 306 | #define INTEL_MSIC_AUDPLLCTRL 0x240 | |
| 307 | #define INTEL_MSIC_DMICBUF0123 0x241 | |
| 308 | #define INTEL_MSIC_DMICBUF45 0x242 | |
| 309 | #define INTEL_MSIC_DMICGPO 0x244 | |
| 310 | #define INTEL_MSIC_DMICMUX 0x245 | |
| 311 | #define INTEL_MSIC_DMICCLK 0x246 | |
| 312 | #define INTEL_MSIC_MICBIAS 0x247 | |
| 313 | #define INTEL_MSIC_ADCCONFIG 0x248 | |
| 314 | #define INTEL_MSIC_MICAMP1 0x249 | |
| 315 | #define INTEL_MSIC_MICAMP2 0x24a | |
| 316 | #define INTEL_MSIC_NOISEMUX 0x24b | |
| 317 | #define INTEL_MSIC_AUDIOMUX12 0x24c | |
| 318 | #define INTEL_MSIC_AUDIOMUX34 0x24d | |
| 319 | #define INTEL_MSIC_AUDIOSINC 0x24e | |
| 320 | #define INTEL_MSIC_AUDIOTXEN 0x24f | |
| 321 | #define INTEL_MSIC_HSEPRXCTRL 0x250 | |
| 322 | #define INTEL_MSIC_IHFRXCTRL 0x251 | |
| 323 | #define INTEL_MSIC_VOICETXVOL 0x252 | |
| 324 | #define INTEL_MSIC_SIDETONEVOL 0x253 | |
| 325 | #define INTEL_MSIC_MUSICSHARVOL 0x254 | |
| 326 | #define INTEL_MSIC_VOICETXCTRL 0x255 | |
| 327 | #define INTEL_MSIC_HSMIXER 0x256 | |
| 328 | #define INTEL_MSIC_DACCONFIG 0x257 | |
| 329 | #define INTEL_MSIC_SOFTMUTE 0x258 | |
| 330 | #define INTEL_MSIC_HSLVOLCTRL 0x259 | |
| 331 | #define INTEL_MSIC_HSRVOLCTRL 0x25a | |
| 332 | #define INTEL_MSIC_IHFLVOLCTRL 0x25b | |
| 333 | #define INTEL_MSIC_IHFRVOLCTRL 0x25c | |
| 334 | #define INTEL_MSIC_DRIVEREN 0x25d | |
| 335 | #define INTEL_MSIC_LINEOUTCTRL 0x25e | |
| 336 | #define INTEL_MSIC_VIB1CTRL1 0x25f | |
| 337 | #define INTEL_MSIC_VIB1CTRL2 0x260 | |
| 338 | #define INTEL_MSIC_VIB1CTRL3 0x261 | |
| 339 | #define INTEL_MSIC_VIB1SPIPCM_1 0x262 | |
| 340 | #define INTEL_MSIC_VIB1SPIPCM_2 0x263 | |
| 341 | #define INTEL_MSIC_VIB1CTRL5 0x264 | |
| 342 | #define INTEL_MSIC_VIB2CTRL1 0x265 | |
| 343 | #define INTEL_MSIC_VIB2CTRL2 0x266 | |
| 344 | #define INTEL_MSIC_VIB2CTRL3 0x267 | |
| 345 | #define INTEL_MSIC_VIB2SPIPCM_1 0x268 | |
| 346 | #define INTEL_MSIC_VIB2SPIPCM_2 0x269 | |
| 347 | #define INTEL_MSIC_VIB2CTRL5 0x26a | |
| 348 | #define INTEL_MSIC_BTNCTRL1 0x26b | |
| 349 | #define INTEL_MSIC_BTNCTRL2 0x26c | |
| 350 | #define INTEL_MSIC_PCM1TXSLOT01 0x26d | |
| 351 | #define INTEL_MSIC_PCM1TXSLOT23 0x26e | |
| 352 | #define INTEL_MSIC_PCM1TXSLOT45 0x26f | |
| 353 | #define INTEL_MSIC_PCM1RXSLOT0123 0x270 | |
| 354 | #define INTEL_MSIC_PCM1RXSLOT045 0x271 | |
| 355 | #define INTEL_MSIC_PCM2TXSLOT01 0x272 | |
| 356 | #define INTEL_MSIC_PCM2TXSLOT23 0x273 | |
| 357 | #define INTEL_MSIC_PCM2TXSLOT45 0x274 | |
| 358 | #define INTEL_MSIC_PCM2RXSLOT01 0x275 | |
| 359 | #define INTEL_MSIC_PCM2RXSLOT23 0x276 | |
| 360 | #define INTEL_MSIC_PCM2RXSLOT45 0x277 | |
| 361 | #define INTEL_MSIC_PCM1CTRL1 0x278 | |
| 362 | #define INTEL_MSIC_PCM1CTRL2 0x279 | |
| 363 | #define INTEL_MSIC_PCM1CTRL3 0x27a | |
| 364 | #define INTEL_MSIC_PCM2CTRL1 0x27b | |
| 365 | #define INTEL_MSIC_PCM2CTRL2 0x27c | |
| 366 | ||
| 367 | /* HDMI */ | |
| 368 | #define INTEL_MSIC_HDMIPUEN 0x280 | |
| 369 | #define INTEL_MSIC_HDMISTATUS 0x281 /* RO */ | |
| 370 | ||
| 371 | /* Physical address of the start of the MSIC interrupt tree in SRAM */ | |
| 372 | #define INTEL_MSIC_IRQ_PHYS_BASE 0xffff7fc0 | |
| 373 | ||
| 374 | /** | |
| 375 | * struct intel_msic_gpio_pdata - platform data for the MSIC GPIO driver | |
| 376 | * @gpio_base: base number for the GPIOs | |
| 377 | */ | |
| 378 | struct intel_msic_gpio_pdata { | |
| 379 | unsigned gpio_base; | |
| 380 | }; | |
| 381 | ||
| 382 | /** | |
| 383 | * struct intel_msic_ocd_pdata - platform data for the MSIC OCD driver | |
| 384 | * @gpio: GPIO number used for OCD interrupts | |
| 385 | * | |
| 386 | * The MSIC MFD driver converts @gpio into an IRQ number and passes it to | |
| 387 | * the OCD driver as %IORESOURCE_IRQ. | |
| 388 | */ | |
| 389 | struct intel_msic_ocd_pdata { | |
| 390 | unsigned gpio; | |
| 391 | }; | |
| 392 | ||
| 393 | /* MSIC embedded blocks (subdevices) */ | |
| 394 | enum intel_msic_block { | |
| 395 | INTEL_MSIC_BLOCK_TOUCH, | |
| 396 | INTEL_MSIC_BLOCK_ADC, | |
| 397 | INTEL_MSIC_BLOCK_BATTERY, | |
| 398 | INTEL_MSIC_BLOCK_GPIO, | |
| 399 | INTEL_MSIC_BLOCK_AUDIO, | |
| 400 | INTEL_MSIC_BLOCK_HDMI, | |
| 401 | INTEL_MSIC_BLOCK_THERMAL, | |
| 402 | INTEL_MSIC_BLOCK_POWER_BTN, | |
| 403 | INTEL_MSIC_BLOCK_OCD, | |
| 404 | ||
| 405 | INTEL_MSIC_BLOCK_LAST, | |
| 406 | }; | |
| 407 | ||
| 408 | /** | |
| 409 | * struct intel_msic_platform_data - platform data for the MSIC driver | |
| 410 | * @irq: array of interrupt numbers, one per device. If @irq is set to %0 | |
| 411 | * for a given block, the corresponding platform device is not | |
| 412 | * created. For devices which don't have an interrupt, use %0xff | |
| 413 | * (this is same as in SFI spec). | |
| 414 | * @gpio: platform data for the MSIC GPIO driver | |
| 415 | * @ocd: platform data for the MSIC OCD driver | |
| 416 | * | |
| 417 | * Once the MSIC driver is initialized, the register interface is ready to | |
| 418 | * use. All the platform devices for subdevices are created after the | |
| 419 | * register interface is ready so that we can guarantee its availability to | |
| 420 | * the subdevice drivers. | |
| 421 | * | |
| 422 | * Interrupt numbers are passed to the subdevices via %IORESOURCE_IRQ | |
| 423 | * resources of the created platform device. | |
| 424 | */ | |
| 425 | struct intel_msic_platform_data { | |
| 426 | int irq[INTEL_MSIC_BLOCK_LAST]; | |
| 427 | struct intel_msic_gpio_pdata *gpio; | |
| 428 | struct intel_msic_ocd_pdata *ocd; | |
| 429 | }; | |
| 430 | ||
| 431 | struct intel_msic; | |
| 432 | ||
| 433 | extern int intel_msic_reg_read(unsigned short reg, u8 *val); | |
| 434 | extern int intel_msic_reg_write(unsigned short reg, u8 val); | |
| 435 | extern int intel_msic_reg_update(unsigned short reg, u8 val, u8 mask); | |
| 436 | extern int intel_msic_bulk_read(unsigned short *reg, u8 *buf, size_t count); | |
| 437 | extern int intel_msic_bulk_write(unsigned short *reg, u8 *buf, size_t count); | |
| 438 | ||
| 439 | /* | |
| 440 | * pdev_to_intel_msic - gets an MSIC instance from the platform device | |
| 441 | * @pdev: platform device pointer | |
| 442 | * | |
| 443 | * The client drivers need to have pointer to the MSIC instance if they | |
| 444 | * want to call intel_msic_irq_read(). This macro can be used for | |
| 445 | * convenience to get the MSIC pointer from @pdev where needed. This is | |
| 446 | * _only_ valid for devices which are managed by the MSIC. | |
| 447 | */ | |
| 448 | #define pdev_to_intel_msic(pdev) (dev_get_drvdata(pdev->dev.parent)) | |
| 449 | ||
| 450 | extern int intel_msic_irq_read(struct intel_msic *msic, unsigned short reg, | |
| 451 | u8 *val); | |
| 452 | ||
| 453 | #endif /* __LINUX_MFD_INTEL_MSIC_H__ */ |