projects / mirror_ubuntu-eoan-kernel.git / blame
| Commit | Line | Data |
|---|---|---|
| 1e349600 K |
1 | /* |
| 2 | * Functions to access LP87565 power management chip. | |
| 3 | * | |
| 4 | * Copyright (C) 2017 Texas Instruments Incorporated - http://www.ti.com/ | |
| 5 | * | |
| 6 | * This program is free software; you can redistribute it and/or | |
| 7 | * modify it under the terms of the GNU General Public License as | |
| 8 | * published by the Free Software Foundation version 2. | |
| 9 | */ | |
| 10 | ||
| 11 | #ifndef __LINUX_MFD_LP87565_H | |
| 12 | #define __LINUX_MFD_LP87565_H | |
| 13 | ||
| 14 | #include <linux/i2c.h> | |
| 15 | #include <linux/regulator/driver.h> | |
| 16 | #include <linux/regulator/machine.h> | |
| 17 | ||
| 18 | enum lp87565_device_type { | |
| 19 | LP87565_DEVICE_TYPE_UNKNOWN = 0, | |
| 20 | LP87565_DEVICE_TYPE_LP87565_Q1, | |
| 21 | }; | |
| 22 | ||
| 23 | /* All register addresses */ | |
| 24 | #define LP87565_REG_DEV_REV 0X00 | |
| 25 | #define LP87565_REG_OTP_REV 0X01 | |
| 26 | #define LP87565_REG_BUCK0_CTRL_1 0X02 | |
| 27 | #define LP87565_REG_BUCK0_CTRL_2 0X03 | |
| 28 | ||
| 29 | #define LP87565_REG_BUCK1_CTRL_1 0X04 | |
| 30 | #define LP87565_REG_BUCK1_CTRL_2 0X05 | |
| 31 | ||
| 32 | #define LP87565_REG_BUCK2_CTRL_1 0X06 | |
| 33 | #define LP87565_REG_BUCK2_CTRL_2 0X07 | |
| 34 | ||
| 35 | #define LP87565_REG_BUCK3_CTRL_1 0X08 | |
| 36 | #define LP87565_REG_BUCK3_CTRL_2 0X09 | |
| 37 | ||
| 38 | #define LP87565_REG_BUCK0_VOUT 0X0A | |
| 39 | #define LP87565_REG_BUCK0_FLOOR_VOUT 0X0B | |
| 40 | ||
| 41 | #define LP87565_REG_BUCK1_VOUT 0X0C | |
| 42 | #define LP87565_REG_BUCK1_FLOOR_VOUT 0X0D | |
| 43 | ||
| 44 | #define LP87565_REG_BUCK2_VOUT 0X0E | |
| 45 | #define LP87565_REG_BUCK2_FLOOR_VOUT 0X0F | |
| 46 | ||
| 47 | #define LP87565_REG_BUCK3_VOUT 0X10 | |
| 48 | #define LP87565_REG_BUCK3_FLOOR_VOUT 0X11 | |
| 49 | ||
| 50 | #define LP87565_REG_BUCK0_DELAY 0X12 | |
| 51 | #define LP87565_REG_BUCK1_DELAY 0X13 | |
| 52 | ||
| 53 | #define LP87565_REG_BUCK2_DELAY 0X14 | |
| 54 | #define LP87565_REG_BUCK3_DELAY 0X15 | |
| 55 | ||
| 56 | #define LP87565_REG_GPO2_DELAY 0X16 | |
| 57 | #define LP87565_REG_GPO3_DELAY 0X17 | |
| 58 | #define LP87565_REG_RESET 0X18 | |
| 59 | #define LP87565_REG_CONFIG 0X19 | |
| 60 | ||
| 61 | #define LP87565_REG_INT_TOP_1 0X1A | |
| 62 | #define LP87565_REG_INT_TOP_2 0X1B | |
| 63 | ||
| 64 | #define LP87565_REG_INT_BUCK_0_1 0X1C | |
| 65 | #define LP87565_REG_INT_BUCK_2_3 0X1D | |
| 66 | #define LP87565_REG_TOP_STAT 0X1E | |
| 67 | #define LP87565_REG_BUCK_0_1_STAT 0X1F | |
| 68 | #define LP87565_REG_BUCK_2_3_STAT 0x20 | |
| 69 | ||
| 70 | #define LP87565_REG_TOP_MASK_1 0x21 | |
| 71 | #define LP87565_REG_TOP_MASK_2 0x22 | |
| 72 | ||
| 73 | #define LP87565_REG_BUCK_0_1_MASK 0x23 | |
| 74 | #define LP87565_REG_BUCK_2_3_MASK 0x24 | |
| 75 | #define LP87565_REG_SEL_I_LOAD 0x25 | |
| 76 | ||
| 77 | #define LP87565_REG_I_LOAD_2 0x26 | |
| 78 | #define LP87565_REG_I_LOAD_1 0x27 | |
| 79 | ||
| 80 | #define LP87565_REG_PGOOD_CTRL1 0x28 | |
| 81 | #define LP87565_REG_PGOOD_CTRL2 0x29 | |
| 82 | #define LP87565_REG_PGOOD_FLT 0x2A | |
| 83 | #define LP87565_REG_PLL_CTRL 0x2B | |
| 84 | #define LP87565_REG_PIN_FUNCTION 0x2C | |
| 85 | #define LP87565_REG_GPIO_CONFIG 0x2D | |
| 86 | #define LP87565_REG_GPIO_IN 0x2E | |
| 87 | #define LP87565_REG_GPIO_OUT 0x2F | |
| 88 | ||
| 89 | #define LP87565_REG_MAX LP87565_REG_GPIO_OUT | |
| 90 | ||
| 91 | /* Register field definitions */ | |
| 92 | #define LP87565_DEV_REV_DEV_ID 0xC0 | |
| 93 | #define LP87565_DEV_REV_ALL_LAYER 0x30 | |
| 94 | #define LP87565_DEV_REV_METAL_LAYER 0x0F | |
| 95 | ||
| 96 | #define LP87565_OTP_REV_OTP_ID 0xFF | |
| 97 | ||
| 98 | #define LP87565_BUCK_CTRL_1_EN BIT(7) | |
| 99 | #define LP87565_BUCK_CTRL_1_EN_PIN_CTRL BIT(6) | |
| 100 | #define LP87565_BUCK_CTRL_1_PIN_SELECT_EN 0x30 | |
| 101 | ||
| 102 | #define LP87565_BUCK_CTRL_1_ROOF_FLOOR_EN BIT(3) | |
| 103 | #define LP87565_BUCK_CTRL_1_RDIS_EN BIT(2) | |
| 104 | #define LP87565_BUCK_CTRL_1_FPWM BIT(1) | |
| 105 | /* Bit0 is reserved for BUCK1 and BUCK3 and valid only for BUCK0 and BUCK2 */ | |
| 106 | #define LP87565_BUCK_CTRL_1_FPWM_MP_0_2 BIT(0) | |
| 107 | ||
| 108 | #define LP87565_BUCK_CTRL_2_ILIM 0x38 | |
| 109 | #define LP87565_BUCK_CTRL_2_SLEW_RATE 0x07 | |
| 110 | ||
| 111 | #define LP87565_BUCK_VSET 0xFF | |
| 112 | #define LP87565_BUCK_FLOOR_VSET 0xFF | |
| 113 | ||
| 114 | #define LP87565_BUCK_SHUTDOWN_DELAY 0xF0 | |
| 115 | #define LP87565_BUCK_STARTUP_DELAY 0x0F | |
| 116 | ||
| 117 | #define LP87565_GPIO_SHUTDOWN_DELAY 0xF0 | |
| 118 | #define LP87565_GPIO_STARTUP_DELAY 0x0F | |
| 119 | ||
| 120 | #define LP87565_RESET_SW_RESET BIT(0) | |
| 121 | ||
| 122 | #define LP87565_CONFIG_DOUBLE_DELAY BIT(7) | |
| 123 | #define LP87565_CONFIG_CLKIN_PD BIT(6) | |
| 124 | #define LP87565_CONFIG_EN4_PD BIT(5) | |
| 125 | #define LP87565_CONFIG_EN3_PD BIT(4) | |
| 126 | #define LP87565_CONFIG_TDIE_WARN_LEVEL BIT(3) | |
| 127 | #define LP87565_CONFIG_EN2_PD BIT(2) | |
| 128 | #define LP87565_CONFIG_EN1_PD BIT(1) | |
| 129 | ||
| 130 | #define LP87565_INT_GPIO BIT(7) | |
| 131 | #define LP87565_INT_BUCK23 BIT(6) | |
| 132 | #define LP87565_INT_BUCK01 BIT(5) | |
| 133 | #define LP87565_NO_SYNC_CLK BIT(4) | |
| 134 | #define LP87565_TDIE_SD BIT(3) | |
| 135 | #define LP87565_TDIE_WARN BIT(2) | |
| 136 | #define LP87565_INT_OVP BIT(1) | |
| 137 | #define LP87565_I_LOAD_READY BIT(0) | |
| 138 | ||
| 139 | #define LP87565_INT_TOP2_RESET_REG BIT(0) | |
| 140 | ||
| 141 | #define LP87565_BUCK1_PG_INT BIT(6) | |
| 142 | #define LP87565_BUCK1_SC_INT BIT(5) | |
| 143 | #define LP87565_BUCK1_ILIM_INT BIT(4) | |
| 144 | #define LP87565_BUCK0_PG_INT BIT(2) | |
| 145 | #define LP87565_BUCK0_SC_INT BIT(1) | |
| 146 | #define LP87565_BUCK0_ILIM_INT BIT(0) | |
| 147 | ||
| 148 | #define LP87565_BUCK3_PG_INT BIT(6) | |
| 149 | #define LP87565_BUCK3_SC_INT BIT(5) | |
| 150 | #define LP87565_BUCK3_ILIM_INT BIT(4) | |
| 151 | #define LP87565_BUCK2_PG_INT BIT(2) | |
| 152 | #define LP87565_BUCK2_SC_INT BIT(1) | |
| 153 | #define LP87565_BUCK2_ILIM_INT BIT(0) | |
| 154 | ||
| 155 | #define LP87565_SYNC_CLK_STAT BIT(4) | |
| 156 | #define LP87565_TDIE_SD_STAT BIT(3) | |
| 157 | #define LP87565_TDIE_WARN_STAT BIT(2) | |
| 158 | #define LP87565_OVP_STAT BIT(1) | |
| 159 | ||
| 160 | #define LP87565_BUCK1_STAT BIT(7) | |
| 161 | #define LP87565_BUCK1_PG_STAT BIT(6) | |
| 162 | #define LP87565_BUCK1_ILIM_STAT BIT(4) | |
| 163 | #define LP87565_BUCK0_STAT BIT(3) | |
| 164 | #define LP87565_BUCK0_PG_STAT BIT(2) | |
| 165 | #define LP87565_BUCK0_ILIM_STAT BIT(0) | |
| 166 | ||
| 167 | #define LP87565_BUCK3_STAT BIT(7) | |
| 168 | #define LP87565_BUCK3_PG_STAT BIT(6) | |
| 169 | #define LP87565_BUCK3_ILIM_STAT BIT(4) | |
| 170 | #define LP87565_BUCK2_STAT BIT(3) | |
| 171 | #define LP87565_BUCK2_PG_STAT BIT(2) | |
| 172 | #define LP87565_BUCK2_ILIM_STAT BIT(0) | |
| 173 | ||
| 174 | #define LPL87565_GPIO_MASK BIT(7) | |
| 175 | #define LPL87565_SYNC_CLK_MASK BIT(4) | |
| 176 | #define LPL87565_TDIE_WARN_MASK BIT(2) | |
| 177 | #define LPL87565_I_LOAD_READY_MASK BIT(0) | |
| 178 | ||
| 179 | #define LPL87565_RESET_REG_MASK BIT(0) | |
| 180 | ||
| 181 | #define LPL87565_BUCK1_PG_MASK BIT(6) | |
| 182 | #define LPL87565_BUCK1_ILIM_MASK BIT(4) | |
| 183 | #define LPL87565_BUCK0_PG_MASK BIT(2) | |
| 184 | #define LPL87565_BUCK0_ILIM_MASK BIT(0) | |
| 185 | ||
| 186 | #define LPL87565_BUCK3_PG_MASK BIT(6) | |
| 187 | #define LPL87565_BUCK3_ILIM_MASK BIT(4) | |
| 188 | #define LPL87565_BUCK2_PG_MASK BIT(2) | |
| 189 | #define LPL87565_BUCK2_ILIM_MASK BIT(0) | |
| 190 | ||
| 191 | #define LP87565_LOAD_CURRENT_BUCK_SELECT 0x3 | |
| 192 | ||
| 193 | #define LP87565_I_LOAD2_BUCK_LOAD_CURRENT 0x3 | |
| 194 | #define LP87565_I_LOAD1_BUCK_LOAD_CURRENT 0xFF | |
| 195 | ||
| 196 | #define LP87565_PG3_SEL 0xC0 | |
| 197 | #define LP87565_PG2_SEL 0x30 | |
| 198 | #define LP87565_PG1_SEL 0x0C | |
| 199 | #define LP87565_PG0_SEL 0x03 | |
| 200 | ||
| 201 | #define LP87565_HALF_DAY BIT(7) | |
| 202 | #define LP87565_EN_PG0_NINT BIT(6) | |
| 203 | #define LP87565_PGOOD_SET_DELAY BIT(5) | |
| 204 | #define LP87565_EN_PGFLT_STAT BIT(4) | |
| 205 | #define LP87565_PGOOD_WINDOW BIT(2) | |
| 206 | #define LP87565_PGOOD_OD BIT(1) | |
| 207 | #define LP87565_PGOOD_POL BIT(0) | |
| 208 | ||
| 209 | #define LP87565_PG3_FLT BIT(3) | |
| 210 | #define LP87565_PG2_FLT BIT(2) | |
| 211 | #define LP87565_PG1_FLT BIT(1) | |
| 212 | #define LP87565_PG0_FLT BIT(0) | |
| 213 | ||
| 214 | #define LP87565_PLL_MODE 0xC0 | |
| 215 | #define LP87565_EXT_CLK_FREQ 0x1F | |
| 216 | ||
| 217 | #define LP87565_EN_SPREAD_SPEC BIT(7) | |
| 218 | #define LP87565_EN_PIN_CTRL_GPIO3 BIT(6) | |
| 219 | #define LP87565_EN_PIN_SELECT_GPIO3 BIT(5) | |
| 220 | #define LP87565_EN_PIN_CTRL_GPIO2 BIT(4) | |
| 221 | #define LP87565_EN_PIN_SELECT_GPIO2 BIT(3) | |
| 222 | #define LP87565_GPIO3_SEL BIT(2) | |
| 223 | #define LP87565_GPIO2_SEL BIT(1) | |
| 224 | #define LP87565_GPIO1_SEL BIT(0) | |
| 225 | ||
| 226 | #define LP87565_GOIO3_OD BIT(6) | |
| 227 | #define LP87565_GOIO2_OD BIT(5) | |
| 228 | #define LP87565_GOIO1_OD BIT(4) | |
| 229 | #define LP87565_GOIO3_DIR BIT(2) | |
| 230 | #define LP87565_GOIO2_DIR BIT(1) | |
| 231 | #define LP87565_GOIO1_DIR BIT(0) | |
| 232 | ||
| 233 | #define LP87565_GOIO3_IN BIT(2) | |
| 234 | #define LP87565_GOIO2_IN BIT(1) | |
| 235 | #define LP87565_GOIO1_IN BIT(0) | |
| 236 | ||
| 237 | #define LP87565_GOIO3_OUT BIT(2) | |
| 238 | #define LP87565_GOIO2_OUT BIT(1) | |
| 239 | #define LP87565_GOIO1_OUT BIT(0) | |
| 240 | ||
| 241 | /* Number of step-down converters available */ | |
| 242 | #define LP87565_NUM_BUCK 6 | |
| 243 | ||
| 244 | enum LP87565_regulator_id { | |
| 245 | /* BUCK's */ | |
| 246 | LP87565_BUCK_0, | |
| 247 | LP87565_BUCK_1, | |
| 248 | LP87565_BUCK_2, | |
| 249 | LP87565_BUCK_3, | |
| 250 | LP87565_BUCK_10, | |
| 251 | LP87565_BUCK_23, | |
| 252 | }; | |
| 253 | ||
| 254 | /** | |
| 255 | * struct LP87565 - state holder for the LP87565 driver | |
| 256 | * @dev: struct device pointer for MFD device | |
| 257 | * @rev: revision of the LP87565 | |
| 258 | * @dev_type: The device type for example lp87565-q1 | |
| 259 | * @lock: lock guarding the data structure | |
| 260 | * @regmap: register map of the LP87565 PMIC | |
| 261 | * | |
| 262 | * Device data may be used to access the LP87565 chip | |
| 263 | */ | |
| 264 | struct lp87565 { | |
| 265 | struct device *dev; | |
| 266 | u8 rev; | |
| 267 | u8 dev_type; | |
| 268 | struct regmap *regmap; | |
| 269 | }; | |
| 270 | #endif /* __LINUX_MFD_LP87565_H */ |