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mfd: palmas: Add tps65917 support
[mirror_ubuntu-bionic-kernel.git] / include / linux / mfd / palmas.h
CommitLineData
2945fbc2
GG		 1/*
2 * TI Palmas
3 *
654003e9 4 * Copyright 2011-2013 Texas Instruments Inc.
2945fbc2
GG		 5 *
6 * Author: Graeme Gregory <gg@slimlogic.co.uk>
654003e9 7 * Author: Ian Lartey <ian@slimlogic.co.uk>
2945fbc2
GG		 8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 */
15
16#ifndef __LINUX_MFD_PALMAS_H
17#define __LINUX_MFD_PALMAS_H
18
19#include <linux/usb/otg.h>
20#include <linux/leds.h>
21#include <linux/regmap.h>
22#include <linux/regulator/driver.h>
b1f254e3
GG		 23#include <linux/extcon.h>
24#include <linux/usb/phy_companion.h>
2945fbc2
GG		 25
26#define PALMAS_NUM_CLIENTS 3
27
654003e9
IL		 28/* The ID_REVISION NUMBERS */
29#define PALMAS_CHIP_OLD_ID 0x0000
30#define PALMAS_CHIP_ID 0xC035
31#define PALMAS_CHIP_CHARGER_ID 0xC036
32
027d7c2a
K		 33#define TPS65917_RESERVED -1
34
654003e9
IL		 35#define is_palmas(a) (((a) == PALMAS_CHIP_OLD_ID) || \
36 ((a) == PALMAS_CHIP_ID))
37#define is_palmas_charger(a) ((a) == PALMAS_CHIP_CHARGER_ID)
38
1ffb0be3
K		 39/**
40 * Palmas PMIC feature types
41 *
42 * PALMAS_PMIC_FEATURE_SMPS10_BOOST - used when the PMIC provides SMPS10_BOOST
43 * regulator.
44 *
45 * PALMAS_PMIC_HAS(b, f) - macro to check if a bandgap device is capable of a
46 * specific feature (above) or not. Return non-zero, if yes.
47 */
48#define PALMAS_PMIC_FEATURE_SMPS10_BOOST BIT(0)
49#define PALMAS_PMIC_HAS(b, f) \
50 ((b)->features & PALMAS_PMIC_FEATURE_ ## f)
51
2945fbc2 52struct palmas_pmic;
190ef1a6
GG		 53struct palmas_gpadc;
54struct palmas_resource;
55struct palmas_usb;
2945fbc2 56
b1f254e3
GG		 57enum palmas_usb_state {
58 PALMAS_USB_STATE_DISCONNECT,
59 PALMAS_USB_STATE_VBUS,
60 PALMAS_USB_STATE_ID,
61};
62
2945fbc2
GG		 63struct palmas {
64 struct device *dev;
65
66 struct i2c_client *i2c_clients[PALMAS_NUM_CLIENTS];
67 struct regmap *regmap[PALMAS_NUM_CLIENTS];
68
69 /* Stored chip id */
70 int id;
71
1ffb0be3 72 unsigned int features;
2945fbc2
GG		 73 /* IRQ Data */
74 int irq;
75 u32 irq_mask;
76 struct mutex irq_lock;
77 struct regmap_irq_chip_data *irq_data;
78
79 /* Child Devices */
80 struct palmas_pmic *pmic;
190ef1a6
GG		 81 struct palmas_gpadc *gpadc;
82 struct palmas_resource *resource;
83 struct palmas_usb *usb;
2945fbc2
GG		 84
85 /* GPIO MUXing */
86 u8 gpio_muxed;
87 u8 led_muxed;
88 u8 pwm_muxed;
89};
90
190ef1a6
GG		 91struct palmas_gpadc_platform_data {
92 /* Channel 3 current source is only enabled during conversion */
93 int ch3_current;
94
95 /* Channel 0 current source can be used for battery detection.
96 * If used for battery detection this will cause a permanent current
97 * consumption depending on current level set here.
98 */
99 int ch0_current;
100
101 /* default BAT_REMOVAL_DAT setting on device probe */
102 int bat_removal;
103
104 /* Sets the START_POLARITY bit in the RT_CTRL register */
105 int start_polarity;
106};
107
2945fbc2
GG		 108struct palmas_reg_init {
109 /* warm_rest controls the voltage levels after a warm reset
110 *
111 * 0: reload default values from OTP on warm reset
112 * 1: maintain voltage from VSEL on warm reset
113 */
114 int warm_reset;
115
116 /* roof_floor controls whether the regulator uses the i2c style
117 * of DVS or uses the method where a GPIO or other control method is
118 * attached to the NSLEEP/ENABLE1/ENABLE2 pins
119 *
120 * For SMPS
121 *
122 * 0: i2c selection of voltage
123 * 1: pin selection of voltage.
124 *
125 * For LDO unused
126 */
127 int roof_floor;
128
129 /* sleep_mode is the mode loaded to MODE_SLEEP bits as defined in
130 * the data sheet.
131 *
132 * For SMPS
133 *
134 * 0: Off
135 * 1: AUTO
136 * 2: ECO
137 * 3: Forced PWM
138 *
139 * For LDO
140 *
141 * 0: Off
142 * 1: On
143 */
144 int mode_sleep;
145
2945fbc2
GG		 146 /* voltage_sel is the bitfield loaded onto the SMPSX_VOLTAGE
147 * register. Set this is the default voltage set in OTP needs
148 * to be overridden.
149 */
150 u8 vsel;
151
152};
153
7cc4c92f
GG		 154enum palmas_regulators {
155 /* SMPS regulators */
156 PALMAS_REG_SMPS12,
157 PALMAS_REG_SMPS123,
158 PALMAS_REG_SMPS3,
159 PALMAS_REG_SMPS45,
160 PALMAS_REG_SMPS457,
161 PALMAS_REG_SMPS6,
162 PALMAS_REG_SMPS7,
163 PALMAS_REG_SMPS8,
164 PALMAS_REG_SMPS9,
77409d9b
KVA		 165 PALMAS_REG_SMPS10_OUT2,
166 PALMAS_REG_SMPS10_OUT1,
7cc4c92f
GG		 167 /* LDO regulators */
168 PALMAS_REG_LDO1,
169 PALMAS_REG_LDO2,
170 PALMAS_REG_LDO3,
171 PALMAS_REG_LDO4,
172 PALMAS_REG_LDO5,
173 PALMAS_REG_LDO6,
174 PALMAS_REG_LDO7,
175 PALMAS_REG_LDO8,
176 PALMAS_REG_LDO9,
177 PALMAS_REG_LDOLN,
178 PALMAS_REG_LDOUSB,
aa07f027
LD		 179 /* External regulators */
180 PALMAS_REG_REGEN1,
181 PALMAS_REG_REGEN2,
182 PALMAS_REG_REGEN3,
183 PALMAS_REG_SYSEN1,
184 PALMAS_REG_SYSEN2,
7cc4c92f
GG		 185 /* Total number of regulators */
186 PALMAS_NUM_REGS,
187};
188
027d7c2a
K		 189enum tps65917_regulators {
190 /* SMPS regulators */
191 TPS65917_REG_SMPS1,
192 TPS65917_REG_SMPS2,
193 TPS65917_REG_SMPS3,
194 TPS65917_REG_SMPS4,
195 TPS65917_REG_SMPS5,
196 /* LDO regulators */
197 TPS65917_REG_LDO1,
198 TPS65917_REG_LDO2,
199 TPS65917_REG_LDO3,
200 TPS65917_REG_LDO4,
201 TPS65917_REG_LDO5,
202 TPS65917_REG_REGEN1,
203 TPS65917_REG_REGEN2,
204 TPS65917_REG_REGEN3,
205
206 /* Total number of regulators */
207 TPS65917_NUM_REGS,
208};
209
cc01b463
LD		 210/* External controll signal name */
211enum {
212 PALMAS_EXT_CONTROL_ENABLE1 = 0x1,
213 PALMAS_EXT_CONTROL_ENABLE2 = 0x2,
214 PALMAS_EXT_CONTROL_NSLEEP = 0x4,
215};
216
217/*
218 * Palmas device resources can be controlled externally for
219 * enabling/disabling it rather than register write through i2c.
220 * Add the external controlled requestor ID for different resources.
221 */
222enum palmas_external_requestor_id {
223 PALMAS_EXTERNAL_REQSTR_ID_REGEN1,
224 PALMAS_EXTERNAL_REQSTR_ID_REGEN2,
225 PALMAS_EXTERNAL_REQSTR_ID_SYSEN1,
226 PALMAS_EXTERNAL_REQSTR_ID_SYSEN2,
227 PALMAS_EXTERNAL_REQSTR_ID_CLK32KG,
228 PALMAS_EXTERNAL_REQSTR_ID_CLK32KGAUDIO,
229 PALMAS_EXTERNAL_REQSTR_ID_REGEN3,
230 PALMAS_EXTERNAL_REQSTR_ID_SMPS12,
231 PALMAS_EXTERNAL_REQSTR_ID_SMPS3,
232 PALMAS_EXTERNAL_REQSTR_ID_SMPS45,
233 PALMAS_EXTERNAL_REQSTR_ID_SMPS6,
234 PALMAS_EXTERNAL_REQSTR_ID_SMPS7,
235 PALMAS_EXTERNAL_REQSTR_ID_SMPS8,
236 PALMAS_EXTERNAL_REQSTR_ID_SMPS9,
237 PALMAS_EXTERNAL_REQSTR_ID_SMPS10,
238 PALMAS_EXTERNAL_REQSTR_ID_LDO1,
239 PALMAS_EXTERNAL_REQSTR_ID_LDO2,
240 PALMAS_EXTERNAL_REQSTR_ID_LDO3,
241 PALMAS_EXTERNAL_REQSTR_ID_LDO4,
242 PALMAS_EXTERNAL_REQSTR_ID_LDO5,
243 PALMAS_EXTERNAL_REQSTR_ID_LDO6,
244 PALMAS_EXTERNAL_REQSTR_ID_LDO7,
245 PALMAS_EXTERNAL_REQSTR_ID_LDO8,
246 PALMAS_EXTERNAL_REQSTR_ID_LDO9,
247 PALMAS_EXTERNAL_REQSTR_ID_LDOLN,
248 PALMAS_EXTERNAL_REQSTR_ID_LDOUSB,
249
250 /* Last entry */
251 PALMAS_EXTERNAL_REQSTR_ID_MAX,
252};
253
027d7c2a
K		 254enum tps65917_external_requestor_id {
255 TPS65917_EXTERNAL_REQSTR_ID_REGEN1,
256 TPS65917_EXTERNAL_REQSTR_ID_REGEN2,
257 TPS65917_EXTERNAL_REQSTR_ID_REGEN3,
258 TPS65917_EXTERNAL_REQSTR_ID_SMPS1,
259 TPS65917_EXTERNAL_REQSTR_ID_SMPS2,
260 TPS65917_EXTERNAL_REQSTR_ID_SMPS3,
261 TPS65917_EXTERNAL_REQSTR_ID_SMPS4,
262 TPS65917_EXTERNAL_REQSTR_ID_SMPS5,
263 TPS65917_EXTERNAL_REQSTR_ID_LDO1,
264 TPS65917_EXTERNAL_REQSTR_ID_LDO2,
265 TPS65917_EXTERNAL_REQSTR_ID_LDO3,
266 TPS65917_EXTERNAL_REQSTR_ID_LDO4,
267 TPS65917_EXTERNAL_REQSTR_ID_LDO5,
268 /* Last entry */
269 TPS65917_EXTERNAL_REQSTR_ID_MAX,
270};
271
2945fbc2
GG		 272struct palmas_pmic_platform_data {
273 /* An array of pointers to regulator init data indexed by regulator
274 * ID
275 */
7cc4c92f 276 struct regulator_init_data *reg_data[PALMAS_NUM_REGS];
2945fbc2
GG		 277
278 /* An array of pointers to structures containing sleep mode and DVS
279 * configuration for regulators indexed by ID
280 */
7cc4c92f 281 struct palmas_reg_init *reg_init[PALMAS_NUM_REGS];
2945fbc2
GG		 282
283 /* use LDO6 for vibrator control */
284 int ldo6_vibrator;
17c11a76
LD		 285
286 /* Enable tracking mode of LDO8 */
287 bool enable_ldo8_tracking;
190ef1a6
GG		 288};
289
290struct palmas_usb_platform_data {
190ef1a6
GG		 291 /* Do we enable the wakeup comparator on probe */
292 int wakeup;
293};
294
295struct palmas_resource_platform_data {
296 int regen1_mode_sleep;
297 int regen2_mode_sleep;
298 int sysen1_mode_sleep;
299 int sysen2_mode_sleep;
300
301 /* bitfield to be loaded to NSLEEP_RES_ASSIGN */
302 u8 nsleep_res;
303 /* bitfield to be loaded to NSLEEP_SMPS_ASSIGN */
304 u8 nsleep_smps;
305 /* bitfield to be loaded to NSLEEP_LDO_ASSIGN1 */
306 u8 nsleep_ldo1;
307 /* bitfield to be loaded to NSLEEP_LDO_ASSIGN2 */
308 u8 nsleep_ldo2;
309
310 /* bitfield to be loaded to ENABLE1_RES_ASSIGN */
311 u8 enable1_res;
312 /* bitfield to be loaded to ENABLE1_SMPS_ASSIGN */
313 u8 enable1_smps;
314 /* bitfield to be loaded to ENABLE1_LDO_ASSIGN1 */
315 u8 enable1_ldo1;
316 /* bitfield to be loaded to ENABLE1_LDO_ASSIGN2 */
317 u8 enable1_ldo2;
318
319 /* bitfield to be loaded to ENABLE2_RES_ASSIGN */
320 u8 enable2_res;
321 /* bitfield to be loaded to ENABLE2_SMPS_ASSIGN */
322 u8 enable2_smps;
323 /* bitfield to be loaded to ENABLE2_LDO_ASSIGN1 */
324 u8 enable2_ldo1;
325 /* bitfield to be loaded to ENABLE2_LDO_ASSIGN2 */
326 u8 enable2_ldo2;
327};
2945fbc2 328
190ef1a6
GG		 329struct palmas_clk_platform_data {
330 int clk32kg_mode_sleep;
331 int clk32kgaudio_mode_sleep;
2945fbc2
GG		 332};
333
334struct palmas_platform_data {
df545d1c 335 int irq_flags;
2945fbc2
GG		 336 int gpio_base;
337
338 /* bit value to be loaded to the POWER_CTRL register */
339 u8 power_ctrl;
340
341 /*
342 * boolean to select if we want to configure muxing here
343 * then the two value to load into the registers if true
344 */
345 int mux_from_pdata;
346 u8 pad1, pad2;
b81eec09 347 bool pm_off;
2945fbc2
GG		 348
349 struct palmas_pmic_platform_data *pmic_pdata;
190ef1a6
GG		 350 struct palmas_gpadc_platform_data *gpadc_pdata;
351 struct palmas_usb_platform_data *usb_pdata;
352 struct palmas_resource_platform_data *resource_pdata;
353 struct palmas_clk_platform_data *clk_pdata;
2945fbc2
GG		 354};
355
190ef1a6
GG		 356struct palmas_gpadc_calibration {
357 s32 gain;
358 s32 gain_error;
359 s32 offset_error;
360};
361
362struct palmas_gpadc {
363 struct device *dev;
364 struct palmas *palmas;
365
366 int ch3_current;
367 int ch0_current;
368
369 int gpadc_force;
370
371 int bat_removal;
372
373 struct mutex reading_lock;
374 struct completion irq_complete;
375
376 int eoc_sw_irq;
377
378 struct palmas_gpadc_calibration *palmas_cal_tbl;
379
380 int conv0_channel;
381 int conv1_channel;
382 int rt_channel;
383};
384
385struct palmas_gpadc_result {
386 s32 raw_code;
387 s32 corrected_code;
388 s32 result;
389};
390
391#define PALMAS_MAX_CHANNELS 16
392
027d7c2a
K		 393/* Define the tps65917 IRQ numbers */
394enum tps65917_irqs {
395 /* INT1 registers */
396 TPS65917_RESERVED1,
397 TPS65917_PWRON_IRQ,
398 TPS65917_LONG_PRESS_KEY_IRQ,
399 TPS65917_RESERVED2,
400 TPS65917_PWRDOWN_IRQ,
401 TPS65917_HOTDIE_IRQ,
402 TPS65917_VSYS_MON_IRQ,
403 TPS65917_RESERVED3,
404 /* INT2 registers */
405 TPS65917_RESERVED4,
406 TPS65917_OTP_ERROR_IRQ,
407 TPS65917_WDT_IRQ,
408 TPS65917_RESERVED5,
409 TPS65917_RESET_IN_IRQ,
410 TPS65917_FSD_IRQ,
411 TPS65917_SHORT_IRQ,
412 TPS65917_RESERVED6,
413 /* INT3 registers */
414 TPS65917_GPADC_AUTO_0_IRQ,
415 TPS65917_GPADC_AUTO_1_IRQ,
416 TPS65917_GPADC_EOC_SW_IRQ,
417 TPS65917_RESREVED6,
418 TPS65917_RESERVED7,
419 TPS65917_RESERVED8,
420 TPS65917_RESERVED9,
421 TPS65917_VBUS_IRQ,
422 /* INT4 registers */
423 TPS65917_GPIO_0_IRQ,
424 TPS65917_GPIO_1_IRQ,
425 TPS65917_GPIO_2_IRQ,
426 TPS65917_GPIO_3_IRQ,
427 TPS65917_GPIO_4_IRQ,
428 TPS65917_GPIO_5_IRQ,
429 TPS65917_GPIO_6_IRQ,
430 TPS65917_RESERVED10,
431 /* Total Number IRQs */
432 TPS65917_NUM_IRQ,
433};
434
2945fbc2
GG		 435/* Define the palmas IRQ numbers */
436enum palmas_irqs {
437 /* INT1 registers */
438 PALMAS_CHARG_DET_N_VBUS_OVV_IRQ,
439 PALMAS_PWRON_IRQ,
440 PALMAS_LONG_PRESS_KEY_IRQ,
441 PALMAS_RPWRON_IRQ,
442 PALMAS_PWRDOWN_IRQ,
443 PALMAS_HOTDIE_IRQ,
444 PALMAS_VSYS_MON_IRQ,
445 PALMAS_VBAT_MON_IRQ,
446 /* INT2 registers */
447 PALMAS_RTC_ALARM_IRQ,
448 PALMAS_RTC_TIMER_IRQ,
449 PALMAS_WDT_IRQ,
450 PALMAS_BATREMOVAL_IRQ,
451 PALMAS_RESET_IN_IRQ,
452 PALMAS_FBI_BB_IRQ,
453 PALMAS_SHORT_IRQ,
454 PALMAS_VAC_ACOK_IRQ,
455 /* INT3 registers */
456 PALMAS_GPADC_AUTO_0_IRQ,
457 PALMAS_GPADC_AUTO_1_IRQ,
458 PALMAS_GPADC_EOC_SW_IRQ,
459 PALMAS_GPADC_EOC_RT_IRQ,
460 PALMAS_ID_OTG_IRQ,
461 PALMAS_ID_IRQ,
462 PALMAS_VBUS_OTG_IRQ,
463 PALMAS_VBUS_IRQ,
464 /* INT4 registers */
465 PALMAS_GPIO_0_IRQ,
466 PALMAS_GPIO_1_IRQ,
467 PALMAS_GPIO_2_IRQ,
468 PALMAS_GPIO_3_IRQ,
469 PALMAS_GPIO_4_IRQ,
470 PALMAS_GPIO_5_IRQ,
471 PALMAS_GPIO_6_IRQ,
472 PALMAS_GPIO_7_IRQ,
473 /* Total Number IRQs */
474 PALMAS_NUM_IRQ,
475};
476
2945fbc2
GG		 477struct palmas_pmic {
478 struct palmas *palmas;
479 struct device *dev;
480 struct regulator_desc desc[PALMAS_NUM_REGS];
481 struct regulator_dev *rdev[PALMAS_NUM_REGS];
482 struct mutex mutex;
483
484 int smps123;
485 int smps457;
027d7c2a 486 int smps12;
2945fbc2 487
77409d9b
KVA		 488 int range[PALMAS_REG_SMPS10_OUT1];
489 unsigned int ramp_delay[PALMAS_REG_SMPS10_OUT1];
490 unsigned int current_reg_mode[PALMAS_REG_SMPS10_OUT1];
2945fbc2
GG		 491};
492
190ef1a6
GG		 493struct palmas_resource {
494 struct palmas *palmas;
495 struct device *dev;
496};
497
498struct palmas_usb {
499 struct palmas *palmas;
500 struct device *dev;
501
3f79a3fb 502 struct extcon_dev *edev;
190ef1a6 503
b1f254e3
GG		 504 int id_otg_irq;
505 int id_irq;
506 int vbus_otg_irq;
507 int vbus_irq;
190ef1a6 508
b1f254e3 509 enum palmas_usb_state linkstat;
7281e05a
LD		 510 int wakeup;
511 bool enable_vbus_detection;
512 bool enable_id_detection;
190ef1a6
GG		 513};
514
515#define comparator_to_palmas(x) container_of((x), struct palmas_usb, comparator)
516
517enum usb_irq_events {
518 /* Wakeup events from INT3 */
519 PALMAS_USB_ID_WAKEPUP,
520 PALMAS_USB_VBUS_WAKEUP,
521
522 /* ID_OTG_EVENTS */
523 PALMAS_USB_ID_GND,
524 N_PALMAS_USB_ID_GND,
525 PALMAS_USB_ID_C,
526 N_PALMAS_USB_ID_C,
527 PALMAS_USB_ID_B,
528 N_PALMAS_USB_ID_B,
529 PALMAS_USB_ID_A,
530 N_PALMAS_USB_ID_A,
531 PALMAS_USB_ID_FLOAT,
532 N_PALMAS_USB_ID_FLOAT,
533
534 /* VBUS_OTG_EVENTS */
535 PALMAS_USB_VB_SESS_END,
536 N_PALMAS_USB_VB_SESS_END,
537 PALMAS_USB_VB_SESS_VLD,
538 N_PALMAS_USB_VB_SESS_VLD,
539 PALMAS_USB_VA_SESS_VLD,
540 N_PALMAS_USB_VA_SESS_VLD,
541 PALMAS_USB_VA_VBUS_VLD,
542 N_PALMAS_USB_VA_VBUS_VLD,
543 PALMAS_USB_VADP_SNS,
544 N_PALMAS_USB_VADP_SNS,
545 PALMAS_USB_VADP_PRB,
546 N_PALMAS_USB_VADP_PRB,
547 PALMAS_USB_VOTG_SESS_VLD,
548 N_PALMAS_USB_VOTG_SESS_VLD,
549};
550
2945fbc2
GG		 551/* defines so we can store the mux settings */
552#define PALMAS_GPIO_0_MUXED (1 << 0)
553#define PALMAS_GPIO_1_MUXED (1 << 1)
554#define PALMAS_GPIO_2_MUXED (1 << 2)
555#define PALMAS_GPIO_3_MUXED (1 << 3)
556#define PALMAS_GPIO_4_MUXED (1 << 4)
557#define PALMAS_GPIO_5_MUXED (1 << 5)
558#define PALMAS_GPIO_6_MUXED (1 << 6)
559#define PALMAS_GPIO_7_MUXED (1 << 7)
560
561#define PALMAS_LED1_MUXED (1 << 0)
562#define PALMAS_LED2_MUXED (1 << 1)
563
564#define PALMAS_PWM1_MUXED (1 << 0)
565#define PALMAS_PWM2_MUXED (1 << 1)
566
567/* helper macro to get correct slave number */
568#define PALMAS_BASE_TO_SLAVE(x) ((x >> 8) - 1)
45ac60c0 569#define PALMAS_BASE_TO_REG(x, y) ((x & 0xFF) + y)
2945fbc2
GG		 570
571/* Base addresses of IP blocks in Palmas */
45ac60c0 572#define PALMAS_SMPS_DVS_BASE 0x020
2945fbc2
GG		 573#define PALMAS_RTC_BASE 0x100
574#define PALMAS_VALIDITY_BASE 0x118
575#define PALMAS_SMPS_BASE 0x120
576#define PALMAS_LDO_BASE 0x150
577#define PALMAS_DVFS_BASE 0x180
578#define PALMAS_PMU_CONTROL_BASE 0x1A0
579#define PALMAS_RESOURCE_BASE 0x1D4
0a8d3e24 580#define PALMAS_PU_PD_OD_BASE 0x1F0
2945fbc2
GG		 581#define PALMAS_LED_BASE 0x200
582#define PALMAS_INTERRUPT_BASE 0x210
583#define PALMAS_USB_OTG_BASE 0x250
584#define PALMAS_VIBRATOR_BASE 0x270
585#define PALMAS_GPIO_BASE 0x280
586#define PALMAS_USB_BASE 0x290
587#define PALMAS_GPADC_BASE 0x2C0
588#define PALMAS_TRIM_GPADC_BASE 0x3CD
589
590/* Registers for function RTC */
45ac60c0
K		 591#define PALMAS_SECONDS_REG 0x00
592#define PALMAS_MINUTES_REG 0x01
593#define PALMAS_HOURS_REG 0x02
594#define PALMAS_DAYS_REG 0x03
595#define PALMAS_MONTHS_REG 0x04
596#define PALMAS_YEARS_REG 0x05
597#define PALMAS_WEEKS_REG 0x06
598#define PALMAS_ALARM_SECONDS_REG 0x08
599#define PALMAS_ALARM_MINUTES_REG 0x09
600#define PALMAS_ALARM_HOURS_REG 0x0A
601#define PALMAS_ALARM_DAYS_REG 0x0B
602#define PALMAS_ALARM_MONTHS_REG 0x0C
603#define PALMAS_ALARM_YEARS_REG 0x0D
2945fbc2
GG		 604#define PALMAS_RTC_CTRL_REG 0x10
605#define PALMAS_RTC_STATUS_REG 0x11
606#define PALMAS_RTC_INTERRUPTS_REG 0x12
607#define PALMAS_RTC_COMP_LSB_REG 0x13
608#define PALMAS_RTC_COMP_MSB_REG 0x14
609#define PALMAS_RTC_RES_PROG_REG 0x15
610#define PALMAS_RTC_RESET_STATUS_REG 0x16
611
612/* Bit definitions for SECONDS_REG */
613#define PALMAS_SECONDS_REG_SEC1_MASK 0x70
45ac60c0
K		 614#define PALMAS_SECONDS_REG_SEC1_SHIFT 0x04
615#define PALMAS_SECONDS_REG_SEC0_MASK 0x0F
616#define PALMAS_SECONDS_REG_SEC0_SHIFT 0x00
2945fbc2
GG		 617
618/* Bit definitions for MINUTES_REG */
619#define PALMAS_MINUTES_REG_MIN1_MASK 0x70
45ac60c0
K		 620#define PALMAS_MINUTES_REG_MIN1_SHIFT 0x04
621#define PALMAS_MINUTES_REG_MIN0_MASK 0x0F
622#define PALMAS_MINUTES_REG_MIN0_SHIFT 0x00
2945fbc2
GG		 623
624/* Bit definitions for HOURS_REG */
625#define PALMAS_HOURS_REG_PM_NAM 0x80
45ac60c0 626#define PALMAS_HOURS_REG_PM_NAM_SHIFT 0x07
2945fbc2 627#define PALMAS_HOURS_REG_HOUR1_MASK 0x30
45ac60c0
K		 628#define PALMAS_HOURS_REG_HOUR1_SHIFT 0x04
629#define PALMAS_HOURS_REG_HOUR0_MASK 0x0F
630#define PALMAS_HOURS_REG_HOUR0_SHIFT 0x00
2945fbc2
GG		 631
632/* Bit definitions for DAYS_REG */
633#define PALMAS_DAYS_REG_DAY1_MASK 0x30
45ac60c0
K		 634#define PALMAS_DAYS_REG_DAY1_SHIFT 0x04
635#define PALMAS_DAYS_REG_DAY0_MASK 0x0F
636#define PALMAS_DAYS_REG_DAY0_SHIFT 0x00
2945fbc2
GG		 637
638/* Bit definitions for MONTHS_REG */
639#define PALMAS_MONTHS_REG_MONTH1 0x10
45ac60c0
K		 640#define PALMAS_MONTHS_REG_MONTH1_SHIFT 0x04
641#define PALMAS_MONTHS_REG_MONTH0_MASK 0x0F
642#define PALMAS_MONTHS_REG_MONTH0_SHIFT 0x00
2945fbc2
GG		 643
644/* Bit definitions for YEARS_REG */
645#define PALMAS_YEARS_REG_YEAR1_MASK 0xf0
45ac60c0
K		 646#define PALMAS_YEARS_REG_YEAR1_SHIFT 0x04
647#define PALMAS_YEARS_REG_YEAR0_MASK 0x0F
648#define PALMAS_YEARS_REG_YEAR0_SHIFT 0x00
2945fbc2
GG		 649
650/* Bit definitions for WEEKS_REG */
651#define PALMAS_WEEKS_REG_WEEK_MASK 0x07
45ac60c0 652#define PALMAS_WEEKS_REG_WEEK_SHIFT 0x00
2945fbc2
GG		 653
654/* Bit definitions for ALARM_SECONDS_REG */
655#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_MASK 0x70
45ac60c0
K		 656#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_SHIFT 0x04
657#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_MASK 0x0F
658#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_SHIFT 0x00
2945fbc2
GG		 659
660/* Bit definitions for ALARM_MINUTES_REG */
661#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_MASK 0x70
45ac60c0
K		 662#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_SHIFT 0x04
663#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_MASK 0x0F
664#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_SHIFT 0x00
2945fbc2
GG		 665
666/* Bit definitions for ALARM_HOURS_REG */
667#define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM 0x80
45ac60c0 668#define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM_SHIFT 0x07
2945fbc2 669#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_MASK 0x30
45ac60c0
K		 670#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_SHIFT 0x04
671#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_MASK 0x0F
672#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_SHIFT 0x00
2945fbc2
GG		 673
674/* Bit definitions for ALARM_DAYS_REG */
675#define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_MASK 0x30
45ac60c0
K		 676#define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_SHIFT 0x04
677#define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_MASK 0x0F
678#define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_SHIFT 0x00
2945fbc2
GG		 679
680/* Bit definitions for ALARM_MONTHS_REG */
681#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1 0x10
45ac60c0
K		 682#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1_SHIFT 0x04
683#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_MASK 0x0F
684#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_SHIFT 0x00
2945fbc2
GG		 685
686/* Bit definitions for ALARM_YEARS_REG */
687#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_MASK 0xf0
45ac60c0
K		 688#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_SHIFT 0x04
689#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_MASK 0x0F
690#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_SHIFT 0x00
2945fbc2
GG		 691
692/* Bit definitions for RTC_CTRL_REG */
693#define PALMAS_RTC_CTRL_REG_RTC_V_OPT 0x80
45ac60c0 694#define PALMAS_RTC_CTRL_REG_RTC_V_OPT_SHIFT 0x07
2945fbc2 695#define PALMAS_RTC_CTRL_REG_GET_TIME 0x40
45ac60c0 696#define PALMAS_RTC_CTRL_REG_GET_TIME_SHIFT 0x06
2945fbc2 697#define PALMAS_RTC_CTRL_REG_SET_32_COUNTER 0x20
45ac60c0 698#define PALMAS_RTC_CTRL_REG_SET_32_COUNTER_SHIFT 0x05
2945fbc2 699#define PALMAS_RTC_CTRL_REG_TEST_MODE 0x10
45ac60c0 700#define PALMAS_RTC_CTRL_REG_TEST_MODE_SHIFT 0x04
2945fbc2 701#define PALMAS_RTC_CTRL_REG_MODE_12_24 0x08
45ac60c0 702#define PALMAS_RTC_CTRL_REG_MODE_12_24_SHIFT 0x03
2945fbc2 703#define PALMAS_RTC_CTRL_REG_AUTO_COMP 0x04
45ac60c0 704#define PALMAS_RTC_CTRL_REG_AUTO_COMP_SHIFT 0x02
2945fbc2 705#define PALMAS_RTC_CTRL_REG_ROUND_30S 0x02
45ac60c0 706#define PALMAS_RTC_CTRL_REG_ROUND_30S_SHIFT 0x01
2945fbc2 707#define PALMAS_RTC_CTRL_REG_STOP_RTC 0x01
45ac60c0 708#define PALMAS_RTC_CTRL_REG_STOP_RTC_SHIFT 0x00
2945fbc2
GG		 709
710/* Bit definitions for RTC_STATUS_REG */
711#define PALMAS_RTC_STATUS_REG_POWER_UP 0x80
45ac60c0 712#define PALMAS_RTC_STATUS_REG_POWER_UP_SHIFT 0x07
2945fbc2 713#define PALMAS_RTC_STATUS_REG_ALARM 0x40
45ac60c0 714#define PALMAS_RTC_STATUS_REG_ALARM_SHIFT 0x06
2945fbc2 715#define PALMAS_RTC_STATUS_REG_EVENT_1D 0x20
45ac60c0 716#define PALMAS_RTC_STATUS_REG_EVENT_1D_SHIFT 0x05
2945fbc2 717#define PALMAS_RTC_STATUS_REG_EVENT_1H 0x10
45ac60c0 718#define PALMAS_RTC_STATUS_REG_EVENT_1H_SHIFT 0x04
2945fbc2 719#define PALMAS_RTC_STATUS_REG_EVENT_1M 0x08
45ac60c0 720#define PALMAS_RTC_STATUS_REG_EVENT_1M_SHIFT 0x03
2945fbc2 721#define PALMAS_RTC_STATUS_REG_EVENT_1S 0x04
45ac60c0 722#define PALMAS_RTC_STATUS_REG_EVENT_1S_SHIFT 0x02
2945fbc2 723#define PALMAS_RTC_STATUS_REG_RUN 0x02
45ac60c0 724#define PALMAS_RTC_STATUS_REG_RUN_SHIFT 0x01
2945fbc2
GG		 725
726/* Bit definitions for RTC_INTERRUPTS_REG */
727#define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN 0x10
45ac60c0 728#define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN_SHIFT 0x04
2945fbc2 729#define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM 0x08
45ac60c0 730#define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM_SHIFT 0x03
2945fbc2 731#define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER 0x04
45ac60c0 732#define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER_SHIFT 0x02
2945fbc2 733#define PALMAS_RTC_INTERRUPTS_REG_EVERY_MASK 0x03
45ac60c0 734#define PALMAS_RTC_INTERRUPTS_REG_EVERY_SHIFT 0x00
2945fbc2
GG		 735
736/* Bit definitions for RTC_COMP_LSB_REG */
45ac60c0
K		 737#define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_MASK 0xFF
738#define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_SHIFT 0x00
2945fbc2
GG		 739
740/* Bit definitions for RTC_COMP_MSB_REG */
45ac60c0
K		 741#define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_MASK 0xFF
742#define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_SHIFT 0x00
2945fbc2
GG		 743
744/* Bit definitions for RTC_RES_PROG_REG */
45ac60c0
K		 745#define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_MASK 0x3F
746#define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_SHIFT 0x00
2945fbc2
GG		 747
748/* Bit definitions for RTC_RESET_STATUS_REG */
749#define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS 0x01
45ac60c0 750#define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS_SHIFT 0x00
2945fbc2
GG		 751
752/* Registers for function BACKUP */
45ac60c0
K		 753#define PALMAS_BACKUP0 0x00
754#define PALMAS_BACKUP1 0x01
755#define PALMAS_BACKUP2 0x02
756#define PALMAS_BACKUP3 0x03
757#define PALMAS_BACKUP4 0x04
758#define PALMAS_BACKUP5 0x05
759#define PALMAS_BACKUP6 0x06
760#define PALMAS_BACKUP7 0x07
2945fbc2
GG		 761
762/* Bit definitions for BACKUP0 */
45ac60c0
K		 763#define PALMAS_BACKUP0_BACKUP_MASK 0xFF
764#define PALMAS_BACKUP0_BACKUP_SHIFT 0x00
2945fbc2
GG		 765
766/* Bit definitions for BACKUP1 */
45ac60c0
K		 767#define PALMAS_BACKUP1_BACKUP_MASK 0xFF
768#define PALMAS_BACKUP1_BACKUP_SHIFT 0x00
2945fbc2
GG		 769
770/* Bit definitions for BACKUP2 */
45ac60c0
K		 771#define PALMAS_BACKUP2_BACKUP_MASK 0xFF
772#define PALMAS_BACKUP2_BACKUP_SHIFT 0x00
2945fbc2
GG		 773
774/* Bit definitions for BACKUP3 */
45ac60c0
K		 775#define PALMAS_BACKUP3_BACKUP_MASK 0xFF
776#define PALMAS_BACKUP3_BACKUP_SHIFT 0x00
2945fbc2
GG		 777
778/* Bit definitions for BACKUP4 */
45ac60c0
K		 779#define PALMAS_BACKUP4_BACKUP_MASK 0xFF
780#define PALMAS_BACKUP4_BACKUP_SHIFT 0x00
2945fbc2
GG		 781
782/* Bit definitions for BACKUP5 */
45ac60c0
K		 783#define PALMAS_BACKUP5_BACKUP_MASK 0xFF
784#define PALMAS_BACKUP5_BACKUP_SHIFT 0x00
2945fbc2
GG		 785
786/* Bit definitions for BACKUP6 */
45ac60c0
K		 787#define PALMAS_BACKUP6_BACKUP_MASK 0xFF
788#define PALMAS_BACKUP6_BACKUP_SHIFT 0x00
2945fbc2
GG		 789
790/* Bit definitions for BACKUP7 */
45ac60c0
K		 791#define PALMAS_BACKUP7_BACKUP_MASK 0xFF
792#define PALMAS_BACKUP7_BACKUP_SHIFT 0x00
2945fbc2
GG		 793
794/* Registers for function SMPS */
45ac60c0
K		 795#define PALMAS_SMPS12_CTRL 0x00
796#define PALMAS_SMPS12_TSTEP 0x01
797#define PALMAS_SMPS12_FORCE 0x02
798#define PALMAS_SMPS12_VOLTAGE 0x03
799#define PALMAS_SMPS3_CTRL 0x04
800#define PALMAS_SMPS3_VOLTAGE 0x07
801#define PALMAS_SMPS45_CTRL 0x08
802#define PALMAS_SMPS45_TSTEP 0x09
803#define PALMAS_SMPS45_FORCE 0x0A
804#define PALMAS_SMPS45_VOLTAGE 0x0B
805#define PALMAS_SMPS6_CTRL 0x0C
806#define PALMAS_SMPS6_TSTEP 0x0D
807#define PALMAS_SMPS6_FORCE 0x0E
808#define PALMAS_SMPS6_VOLTAGE 0x0F
2945fbc2
GG		 809#define PALMAS_SMPS7_CTRL 0x10
810#define PALMAS_SMPS7_VOLTAGE 0x13
811#define PALMAS_SMPS8_CTRL 0x14
812#define PALMAS_SMPS8_TSTEP 0x15
813#define PALMAS_SMPS8_FORCE 0x16
814#define PALMAS_SMPS8_VOLTAGE 0x17
815#define PALMAS_SMPS9_CTRL 0x18
816#define PALMAS_SMPS9_VOLTAGE 0x1B
817#define PALMAS_SMPS10_CTRL 0x1C
818#define PALMAS_SMPS10_STATUS 0x1F
819#define PALMAS_SMPS_CTRL 0x24
820#define PALMAS_SMPS_PD_CTRL 0x25
821#define PALMAS_SMPS_DITHER_EN 0x26
822#define PALMAS_SMPS_THERMAL_EN 0x27
823#define PALMAS_SMPS_THERMAL_STATUS 0x28
824#define PALMAS_SMPS_SHORT_STATUS 0x29
825#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN 0x2A
826#define PALMAS_SMPS_POWERGOOD_MASK1 0x2B
827#define PALMAS_SMPS_POWERGOOD_MASK2 0x2C
828
829/* Bit definitions for SMPS12_CTRL */
830#define PALMAS_SMPS12_CTRL_WR_S 0x80
45ac60c0 831#define PALMAS_SMPS12_CTRL_WR_S_SHIFT 0x07
2945fbc2 832#define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN 0x40
45ac60c0 833#define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
2945fbc2 834#define PALMAS_SMPS12_CTRL_STATUS_MASK 0x30
45ac60c0 835#define PALMAS_SMPS12_CTRL_STATUS_SHIFT 0x04
2945fbc2 836#define PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK 0x0c
45ac60c0 837#define PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT 0x02
2945fbc2 838#define PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK 0x03
45ac60c0 839#define PALMAS_SMPS12_CTRL_MODE_ACTIVE_SHIFT 0x00
2945fbc2
GG		 840
841/* Bit definitions for SMPS12_TSTEP */
842#define PALMAS_SMPS12_TSTEP_TSTEP_MASK 0x03
45ac60c0 843#define PALMAS_SMPS12_TSTEP_TSTEP_SHIFT 0x00
2945fbc2
GG		 844
845/* Bit definitions for SMPS12_FORCE */
846#define PALMAS_SMPS12_FORCE_CMD 0x80
45ac60c0
K		 847#define PALMAS_SMPS12_FORCE_CMD_SHIFT 0x07
848#define PALMAS_SMPS12_FORCE_VSEL_MASK 0x7F
849#define PALMAS_SMPS12_FORCE_VSEL_SHIFT 0x00
2945fbc2
GG		 850
851/* Bit definitions for SMPS12_VOLTAGE */
852#define PALMAS_SMPS12_VOLTAGE_RANGE 0x80
45ac60c0
K		 853#define PALMAS_SMPS12_VOLTAGE_RANGE_SHIFT 0x07
854#define PALMAS_SMPS12_VOLTAGE_VSEL_MASK 0x7F
855#define PALMAS_SMPS12_VOLTAGE_VSEL_SHIFT 0x00
2945fbc2
GG		 856
857/* Bit definitions for SMPS3_CTRL */
858#define PALMAS_SMPS3_CTRL_WR_S 0x80
45ac60c0 859#define PALMAS_SMPS3_CTRL_WR_S_SHIFT 0x07
2945fbc2 860#define PALMAS_SMPS3_CTRL_STATUS_MASK 0x30
45ac60c0 861#define PALMAS_SMPS3_CTRL_STATUS_SHIFT 0x04
2945fbc2 862#define PALMAS_SMPS3_CTRL_MODE_SLEEP_MASK 0x0c
45ac60c0 863#define PALMAS_SMPS3_CTRL_MODE_SLEEP_SHIFT 0x02
2945fbc2 864#define PALMAS_SMPS3_CTRL_MODE_ACTIVE_MASK 0x03
45ac60c0 865#define PALMAS_SMPS3_CTRL_MODE_ACTIVE_SHIFT 0x00
2945fbc2
GG		 866
867/* Bit definitions for SMPS3_VOLTAGE */
868#define PALMAS_SMPS3_VOLTAGE_RANGE 0x80
45ac60c0
K		 869#define PALMAS_SMPS3_VOLTAGE_RANGE_SHIFT 0x07
870#define PALMAS_SMPS3_VOLTAGE_VSEL_MASK 0x7F
871#define PALMAS_SMPS3_VOLTAGE_VSEL_SHIFT 0x00
2945fbc2
GG		 872
873/* Bit definitions for SMPS45_CTRL */
874#define PALMAS_SMPS45_CTRL_WR_S 0x80
45ac60c0 875#define PALMAS_SMPS45_CTRL_WR_S_SHIFT 0x07
2945fbc2 876#define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN 0x40
45ac60c0 877#define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
2945fbc2 878#define PALMAS_SMPS45_CTRL_STATUS_MASK 0x30
45ac60c0 879#define PALMAS_SMPS45_CTRL_STATUS_SHIFT 0x04
2945fbc2 880#define PALMAS_SMPS45_CTRL_MODE_SLEEP_MASK 0x0c
45ac60c0 881#define PALMAS_SMPS45_CTRL_MODE_SLEEP_SHIFT 0x02
2945fbc2 882#define PALMAS_SMPS45_CTRL_MODE_ACTIVE_MASK 0x03
45ac60c0 883#define PALMAS_SMPS45_CTRL_MODE_ACTIVE_SHIFT 0x00
2945fbc2
GG		 884
885/* Bit definitions for SMPS45_TSTEP */
886#define PALMAS_SMPS45_TSTEP_TSTEP_MASK 0x03
45ac60c0 887#define PALMAS_SMPS45_TSTEP_TSTEP_SHIFT 0x00
2945fbc2
GG		 888
889/* Bit definitions for SMPS45_FORCE */
890#define PALMAS_SMPS45_FORCE_CMD 0x80
45ac60c0
K		 891#define PALMAS_SMPS45_FORCE_CMD_SHIFT 0x07
892#define PALMAS_SMPS45_FORCE_VSEL_MASK 0x7F
893#define PALMAS_SMPS45_FORCE_VSEL_SHIFT 0x00
2945fbc2
GG		 894
895/* Bit definitions for SMPS45_VOLTAGE */
896#define PALMAS_SMPS45_VOLTAGE_RANGE 0x80
45ac60c0
K		 897#define PALMAS_SMPS45_VOLTAGE_RANGE_SHIFT 0x07
898#define PALMAS_SMPS45_VOLTAGE_VSEL_MASK 0x7F
899#define PALMAS_SMPS45_VOLTAGE_VSEL_SHIFT 0x00
2945fbc2
GG		 900
901/* Bit definitions for SMPS6_CTRL */
902#define PALMAS_SMPS6_CTRL_WR_S 0x80
45ac60c0 903#define PALMAS_SMPS6_CTRL_WR_S_SHIFT 0x07
2945fbc2 904#define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN 0x40
45ac60c0 905#define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
2945fbc2 906#define PALMAS_SMPS6_CTRL_STATUS_MASK 0x30
45ac60c0 907#define PALMAS_SMPS6_CTRL_STATUS_SHIFT 0x04
2945fbc2 908#define PALMAS_SMPS6_CTRL_MODE_SLEEP_MASK 0x0c
45ac60c0 909#define PALMAS_SMPS6_CTRL_MODE_SLEEP_SHIFT 0x02
2945fbc2 910#define PALMAS_SMPS6_CTRL_MODE_ACTIVE_MASK 0x03
45ac60c0 911#define PALMAS_SMPS6_CTRL_MODE_ACTIVE_SHIFT 0x00
2945fbc2
GG		 912
913/* Bit definitions for SMPS6_TSTEP */
914#define PALMAS_SMPS6_TSTEP_TSTEP_MASK 0x03
45ac60c0 915#define PALMAS_SMPS6_TSTEP_TSTEP_SHIFT 0x00
2945fbc2
GG		 916
917/* Bit definitions for SMPS6_FORCE */
918#define PALMAS_SMPS6_FORCE_CMD 0x80
45ac60c0
K		 919#define PALMAS_SMPS6_FORCE_CMD_SHIFT 0x07
920#define PALMAS_SMPS6_FORCE_VSEL_MASK 0x7F
921#define PALMAS_SMPS6_FORCE_VSEL_SHIFT 0x00
2945fbc2
GG		 922
923/* Bit definitions for SMPS6_VOLTAGE */
924#define PALMAS_SMPS6_VOLTAGE_RANGE 0x80
45ac60c0
K		 925#define PALMAS_SMPS6_VOLTAGE_RANGE_SHIFT 0x07
926#define PALMAS_SMPS6_VOLTAGE_VSEL_MASK 0x7F
927#define PALMAS_SMPS6_VOLTAGE_VSEL_SHIFT 0x00
2945fbc2
GG		 928
929/* Bit definitions for SMPS7_CTRL */
930#define PALMAS_SMPS7_CTRL_WR_S 0x80
45ac60c0 931#define PALMAS_SMPS7_CTRL_WR_S_SHIFT 0x07
2945fbc2 932#define PALMAS_SMPS7_CTRL_STATUS_MASK 0x30
45ac60c0 933#define PALMAS_SMPS7_CTRL_STATUS_SHIFT 0x04
2945fbc2 934#define PALMAS_SMPS7_CTRL_MODE_SLEEP_MASK 0x0c
45ac60c0 935#define PALMAS_SMPS7_CTRL_MODE_SLEEP_SHIFT 0x02
2945fbc2 936#define PALMAS_SMPS7_CTRL_MODE_ACTIVE_MASK 0x03
45ac60c0 937#define PALMAS_SMPS7_CTRL_MODE_ACTIVE_SHIFT 0x00
2945fbc2
GG		 938
939/* Bit definitions for SMPS7_VOLTAGE */
940#define PALMAS_SMPS7_VOLTAGE_RANGE 0x80
45ac60c0
K		 941#define PALMAS_SMPS7_VOLTAGE_RANGE_SHIFT 0x07
942#define PALMAS_SMPS7_VOLTAGE_VSEL_MASK 0x7F
943#define PALMAS_SMPS7_VOLTAGE_VSEL_SHIFT 0x00
2945fbc2
GG		 944
945/* Bit definitions for SMPS8_CTRL */
946#define PALMAS_SMPS8_CTRL_WR_S 0x80
45ac60c0 947#define PALMAS_SMPS8_CTRL_WR_S_SHIFT 0x07
2945fbc2 948#define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN 0x40
45ac60c0 949#define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
2945fbc2 950#define PALMAS_SMPS8_CTRL_STATUS_MASK 0x30
45ac60c0 951#define PALMAS_SMPS8_CTRL_STATUS_SHIFT 0x04
2945fbc2 952#define PALMAS_SMPS8_CTRL_MODE_SLEEP_MASK 0x0c
45ac60c0 953#define PALMAS_SMPS8_CTRL_MODE_SLEEP_SHIFT 0x02
2945fbc2 954#define PALMAS_SMPS8_CTRL_MODE_ACTIVE_MASK 0x03
45ac60c0 955#define PALMAS_SMPS8_CTRL_MODE_ACTIVE_SHIFT 0x00
2945fbc2
GG		 956
957/* Bit definitions for SMPS8_TSTEP */
958#define PALMAS_SMPS8_TSTEP_TSTEP_MASK 0x03
45ac60c0 959#define PALMAS_SMPS8_TSTEP_TSTEP_SHIFT 0x00
2945fbc2
GG		 960
961/* Bit definitions for SMPS8_FORCE */
962#define PALMAS_SMPS8_FORCE_CMD 0x80
45ac60c0
K		 963#define PALMAS_SMPS8_FORCE_CMD_SHIFT 0x07
964#define PALMAS_SMPS8_FORCE_VSEL_MASK 0x7F
965#define PALMAS_SMPS8_FORCE_VSEL_SHIFT 0x00
2945fbc2
GG		 966
967/* Bit definitions for SMPS8_VOLTAGE */
968#define PALMAS_SMPS8_VOLTAGE_RANGE 0x80
45ac60c0
K		 969#define PALMAS_SMPS8_VOLTAGE_RANGE_SHIFT 0x07
970#define PALMAS_SMPS8_VOLTAGE_VSEL_MASK 0x7F
971#define PALMAS_SMPS8_VOLTAGE_VSEL_SHIFT 0x00
2945fbc2
GG		 972
973/* Bit definitions for SMPS9_CTRL */
974#define PALMAS_SMPS9_CTRL_WR_S 0x80
45ac60c0 975#define PALMAS_SMPS9_CTRL_WR_S_SHIFT 0x07
2945fbc2 976#define PALMAS_SMPS9_CTRL_STATUS_MASK 0x30
45ac60c0 977#define PALMAS_SMPS9_CTRL_STATUS_SHIFT 0x04
2945fbc2 978#define PALMAS_SMPS9_CTRL_MODE_SLEEP_MASK 0x0c
45ac60c0 979#define PALMAS_SMPS9_CTRL_MODE_SLEEP_SHIFT 0x02
2945fbc2 980#define PALMAS_SMPS9_CTRL_MODE_ACTIVE_MASK 0x03
45ac60c0 981#define PALMAS_SMPS9_CTRL_MODE_ACTIVE_SHIFT 0x00
2945fbc2
GG		 982
983/* Bit definitions for SMPS9_VOLTAGE */
984#define PALMAS_SMPS9_VOLTAGE_RANGE 0x80
45ac60c0
K		 985#define PALMAS_SMPS9_VOLTAGE_RANGE_SHIFT 0x07
986#define PALMAS_SMPS9_VOLTAGE_VSEL_MASK 0x7F
987#define PALMAS_SMPS9_VOLTAGE_VSEL_SHIFT 0x00
2945fbc2
GG		 988
989/* Bit definitions for SMPS10_CTRL */
990#define PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK 0xf0
45ac60c0
K		 991#define PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT 0x04
992#define PALMAS_SMPS10_CTRL_MODE_ACTIVE_MASK 0x0F
993#define PALMAS_SMPS10_CTRL_MODE_ACTIVE_SHIFT 0x00
2945fbc2
GG		 994
995/* Bit definitions for SMPS10_STATUS */
45ac60c0
K		 996#define PALMAS_SMPS10_STATUS_STATUS_MASK 0x0F
997#define PALMAS_SMPS10_STATUS_STATUS_SHIFT 0x00
2945fbc2
GG		 998
999/* Bit definitions for SMPS_CTRL */
1000#define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN 0x20
45ac60c0 1001#define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN_SHIFT 0x05
2945fbc2 1002#define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN 0x10
45ac60c0 1003#define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN_SHIFT 0x04
2945fbc2 1004#define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_MASK 0x0c
45ac60c0 1005#define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_SHIFT 0x02
2945fbc2 1006#define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_MASK 0x03
45ac60c0 1007#define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_SHIFT 0x00
2945fbc2
GG		 1008
1009/* Bit definitions for SMPS_PD_CTRL */
1010#define PALMAS_SMPS_PD_CTRL_SMPS9 0x40
45ac60c0 1011#define PALMAS_SMPS_PD_CTRL_SMPS9_SHIFT 0x06
2945fbc2 1012#define PALMAS_SMPS_PD_CTRL_SMPS8 0x20
45ac60c0 1013#define PALMAS_SMPS_PD_CTRL_SMPS8_SHIFT 0x05
2945fbc2 1014#define PALMAS_SMPS_PD_CTRL_SMPS7 0x10
45ac60c0 1015#define PALMAS_SMPS_PD_CTRL_SMPS7_SHIFT 0x04
2945fbc2 1016#define PALMAS_SMPS_PD_CTRL_SMPS6 0x08
45ac60c0 1017#define PALMAS_SMPS_PD_CTRL_SMPS6_SHIFT 0x03
2945fbc2 1018#define PALMAS_SMPS_PD_CTRL_SMPS45 0x04
45ac60c0 1019#define PALMAS_SMPS_PD_CTRL_SMPS45_SHIFT 0x02
2945fbc2 1020#define PALMAS_SMPS_PD_CTRL_SMPS3 0x02
45ac60c0 1021#define PALMAS_SMPS_PD_CTRL_SMPS3_SHIFT 0x01
2945fbc2 1022#define PALMAS_SMPS_PD_CTRL_SMPS12 0x01
45ac60c0 1023#define PALMAS_SMPS_PD_CTRL_SMPS12_SHIFT 0x00
2945fbc2
GG		 1024
1025/* Bit definitions for SMPS_THERMAL_EN */
1026#define PALMAS_SMPS_THERMAL_EN_SMPS9 0x40
45ac60c0 1027#define PALMAS_SMPS_THERMAL_EN_SMPS9_SHIFT 0x06
2945fbc2 1028#define PALMAS_SMPS_THERMAL_EN_SMPS8 0x20
45ac60c0 1029#define PALMAS_SMPS_THERMAL_EN_SMPS8_SHIFT 0x05
2945fbc2 1030#define PALMAS_SMPS_THERMAL_EN_SMPS6 0x08
45ac60c0 1031#define PALMAS_SMPS_THERMAL_EN_SMPS6_SHIFT 0x03
2945fbc2 1032#define PALMAS_SMPS_THERMAL_EN_SMPS457 0x04
45ac60c0 1033#define PALMAS_SMPS_THERMAL_EN_SMPS457_SHIFT 0x02
2945fbc2 1034#define PALMAS_SMPS_THERMAL_EN_SMPS123 0x01
45ac60c0 1035#define PALMAS_SMPS_THERMAL_EN_SMPS123_SHIFT 0x00
2945fbc2
GG		 1036
1037/* Bit definitions for SMPS_THERMAL_STATUS */
1038#define PALMAS_SMPS_THERMAL_STATUS_SMPS9 0x40
45ac60c0 1039#define PALMAS_SMPS_THERMAL_STATUS_SMPS9_SHIFT 0x06
2945fbc2 1040#define PALMAS_SMPS_THERMAL_STATUS_SMPS8 0x20
45ac60c0 1041#define PALMAS_SMPS_THERMAL_STATUS_SMPS8_SHIFT 0x05
2945fbc2 1042#define PALMAS_SMPS_THERMAL_STATUS_SMPS6 0x08
45ac60c0 1043#define PALMAS_SMPS_THERMAL_STATUS_SMPS6_SHIFT 0x03
2945fbc2 1044#define PALMAS_SMPS_THERMAL_STATUS_SMPS457 0x04
45ac60c0 1045#define PALMAS_SMPS_THERMAL_STATUS_SMPS457_SHIFT 0x02
2945fbc2 1046#define PALMAS_SMPS_THERMAL_STATUS_SMPS123 0x01
45ac60c0 1047#define PALMAS_SMPS_THERMAL_STATUS_SMPS123_SHIFT 0x00
2945fbc2
GG		 1048
1049/* Bit definitions for SMPS_SHORT_STATUS */
1050#define PALMAS_SMPS_SHORT_STATUS_SMPS10 0x80
45ac60c0 1051#define PALMAS_SMPS_SHORT_STATUS_SMPS10_SHIFT 0x07
2945fbc2 1052#define PALMAS_SMPS_SHORT_STATUS_SMPS9 0x40
45ac60c0 1053#define PALMAS_SMPS_SHORT_STATUS_SMPS9_SHIFT 0x06
2945fbc2 1054#define PALMAS_SMPS_SHORT_STATUS_SMPS8 0x20
45ac60c0 1055#define PALMAS_SMPS_SHORT_STATUS_SMPS8_SHIFT 0x05
2945fbc2 1056#define PALMAS_SMPS_SHORT_STATUS_SMPS7 0x10
45ac60c0 1057#define PALMAS_SMPS_SHORT_STATUS_SMPS7_SHIFT 0x04
2945fbc2 1058#define PALMAS_SMPS_SHORT_STATUS_SMPS6 0x08
45ac60c0 1059#define PALMAS_SMPS_SHORT_STATUS_SMPS6_SHIFT 0x03
2945fbc2 1060#define PALMAS_SMPS_SHORT_STATUS_SMPS45 0x04
45ac60c0 1061#define PALMAS_SMPS_SHORT_STATUS_SMPS45_SHIFT 0x02
2945fbc2 1062#define PALMAS_SMPS_SHORT_STATUS_SMPS3 0x02
45ac60c0 1063#define PALMAS_SMPS_SHORT_STATUS_SMPS3_SHIFT 0x01
2945fbc2 1064#define PALMAS_SMPS_SHORT_STATUS_SMPS12 0x01
45ac60c0 1065#define PALMAS_SMPS_SHORT_STATUS_SMPS12_SHIFT 0x00
2945fbc2
GG		 1066
1067/* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */
1068#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9 0x40
45ac60c0 1069#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9_SHIFT 0x06
2945fbc2 1070#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8 0x20
45ac60c0 1071#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8_SHIFT 0x05
2945fbc2 1072#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7 0x10
45ac60c0 1073#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7_SHIFT 0x04
2945fbc2 1074#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6 0x08
45ac60c0 1075#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6_SHIFT 0x03
2945fbc2 1076#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45 0x04
45ac60c0 1077#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45_SHIFT 0x02
2945fbc2 1078#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3 0x02
45ac60c0 1079#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT 0x01
2945fbc2 1080#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12 0x01
45ac60c0 1081#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12_SHIFT 0x00
2945fbc2
GG		 1082
1083/* Bit definitions for SMPS_POWERGOOD_MASK1 */
1084#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10 0x80
45ac60c0 1085#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10_SHIFT 0x07
2945fbc2 1086#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9 0x40
45ac60c0 1087#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9_SHIFT 0x06
2945fbc2 1088#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8 0x20
45ac60c0 1089#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8_SHIFT 0x05
2945fbc2 1090#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7 0x10
45ac60c0 1091#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7_SHIFT 0x04
2945fbc2 1092#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6 0x08
45ac60c0 1093#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6_SHIFT 0x03
2945fbc2 1094#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45 0x04
45ac60c0 1095#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45_SHIFT 0x02
2945fbc2 1096#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3 0x02
45ac60c0 1097#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT 0x01
2945fbc2 1098#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12 0x01
45ac60c0 1099#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12_SHIFT 0x00
2945fbc2
GG		 1100
1101/* Bit definitions for SMPS_POWERGOOD_MASK2 */
1102#define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT 0x80
45ac60c0 1103#define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 0x07
2945fbc2 1104#define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7 0x04
45ac60c0 1105#define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7_SHIFT 0x02
2945fbc2 1106#define PALMAS_SMPS_POWERGOOD_MASK2_VBUS 0x02
45ac60c0 1107#define PALMAS_SMPS_POWERGOOD_MASK2_VBUS_SHIFT 0x01
2945fbc2 1108#define PALMAS_SMPS_POWERGOOD_MASK2_ACOK 0x01
45ac60c0 1109#define PALMAS_SMPS_POWERGOOD_MASK2_ACOK_SHIFT 0x00
2945fbc2
GG		 1110
1111/* Registers for function LDO */
45ac60c0
K		 1112#define PALMAS_LDO1_CTRL 0x00
1113#define PALMAS_LDO1_VOLTAGE 0x01
1114#define PALMAS_LDO2_CTRL 0x02
1115#define PALMAS_LDO2_VOLTAGE 0x03
1116#define PALMAS_LDO3_CTRL 0x04
1117#define PALMAS_LDO3_VOLTAGE 0x05
1118#define PALMAS_LDO4_CTRL 0x06
1119#define PALMAS_LDO4_VOLTAGE 0x07
1120#define PALMAS_LDO5_CTRL 0x08
1121#define PALMAS_LDO5_VOLTAGE 0x09
1122#define PALMAS_LDO6_CTRL 0x0A
1123#define PALMAS_LDO6_VOLTAGE 0x0B
1124#define PALMAS_LDO7_CTRL 0x0C
1125#define PALMAS_LDO7_VOLTAGE 0x0D
1126#define PALMAS_LDO8_CTRL 0x0E
1127#define PALMAS_LDO8_VOLTAGE 0x0F
2945fbc2
GG		 1128#define PALMAS_LDO9_CTRL 0x10
1129#define PALMAS_LDO9_VOLTAGE 0x11
1130#define PALMAS_LDOLN_CTRL 0x12
1131#define PALMAS_LDOLN_VOLTAGE 0x13
1132#define PALMAS_LDOUSB_CTRL 0x14
1133#define PALMAS_LDOUSB_VOLTAGE 0x15
1134#define PALMAS_LDO_CTRL 0x1A
1135#define PALMAS_LDO_PD_CTRL1 0x1B
1136#define PALMAS_LDO_PD_CTRL2 0x1C
1137#define PALMAS_LDO_SHORT_STATUS1 0x1D
1138#define PALMAS_LDO_SHORT_STATUS2 0x1E
1139
1140/* Bit definitions for LDO1_CTRL */
1141#define PALMAS_LDO1_CTRL_WR_S 0x80
45ac60c0 1142#define PALMAS_LDO1_CTRL_WR_S_SHIFT 0x07
2945fbc2 1143#define PALMAS_LDO1_CTRL_STATUS 0x10
45ac60c0 1144#define PALMAS_LDO1_CTRL_STATUS_SHIFT 0x04
2945fbc2 1145#define PALMAS_LDO1_CTRL_MODE_SLEEP 0x04
45ac60c0 1146#define PALMAS_LDO1_CTRL_MODE_SLEEP_SHIFT 0x02
2945fbc2 1147#define PALMAS_LDO1_CTRL_MODE_ACTIVE 0x01
45ac60c0 1148#define PALMAS_LDO1_CTRL_MODE_ACTIVE_SHIFT 0x00
2945fbc2
GG		 1149
1150/* Bit definitions for LDO1_VOLTAGE */
45ac60c0
K		 1151#define PALMAS_LDO1_VOLTAGE_VSEL_MASK 0x3F
1152#define PALMAS_LDO1_VOLTAGE_VSEL_SHIFT 0x00
2945fbc2
GG		 1153
1154/* Bit definitions for LDO2_CTRL */
1155#define PALMAS_LDO2_CTRL_WR_S 0x80
45ac60c0 1156#define PALMAS_LDO2_CTRL_WR_S_SHIFT 0x07
2945fbc2 1157#define PALMAS_LDO2_CTRL_STATUS 0x10
45ac60c0 1158#define PALMAS_LDO2_CTRL_STATUS_SHIFT 0x04
2945fbc2 1159#define PALMAS_LDO2_CTRL_MODE_SLEEP 0x04
45ac60c0 1160#define PALMAS_LDO2_CTRL_MODE_SLEEP_SHIFT 0x02
2945fbc2 1161#define PALMAS_LDO2_CTRL_MODE_ACTIVE 0x01
45ac60c0 1162#define PALMAS_LDO2_CTRL_MODE_ACTIVE_SHIFT 0x00
2945fbc2
GG		 1163
1164/* Bit definitions for LDO2_VOLTAGE */
45ac60c0
K		 1165#define PALMAS_LDO2_VOLTAGE_VSEL_MASK 0x3F
1166#define PALMAS_LDO2_VOLTAGE_VSEL_SHIFT 0x00
2945fbc2
GG		 1167
1168/* Bit definitions for LDO3_CTRL */
1169#define PALMAS_LDO3_CTRL_WR_S 0x80
45ac60c0 1170#define PALMAS_LDO3_CTRL_WR_S_SHIFT 0x07
2945fbc2 1171#define PALMAS_LDO3_CTRL_STATUS 0x10
45ac60c0 1172#define PALMAS_LDO3_CTRL_STATUS_SHIFT 0x04
2945fbc2 1173#define PALMAS_LDO3_CTRL_MODE_SLEEP 0x04
45ac60c0 1174#define PALMAS_LDO3_CTRL_MODE_SLEEP_SHIFT 0x02
2945fbc2 1175#define PALMAS_LDO3_CTRL_MODE_ACTIVE 0x01
45ac60c0 1176#define PALMAS_LDO3_CTRL_MODE_ACTIVE_SHIFT 0x00
2945fbc2
GG		 1177
1178/* Bit definitions for LDO3_VOLTAGE */
45ac60c0
K		 1179#define PALMAS_LDO3_VOLTAGE_VSEL_MASK 0x3F
1180#define PALMAS_LDO3_VOLTAGE_VSEL_SHIFT 0x00
2945fbc2
GG		 1181
1182/* Bit definitions for LDO4_CTRL */
1183#define PALMAS_LDO4_CTRL_WR_S 0x80
45ac60c0 1184#define PALMAS_LDO4_CTRL_WR_S_SHIFT 0x07
2945fbc2 1185#define PALMAS_LDO4_CTRL_STATUS 0x10
45ac60c0 1186#define PALMAS_LDO4_CTRL_STATUS_SHIFT 0x04
2945fbc2 1187#define PALMAS_LDO4_CTRL_MODE_SLEEP 0x04
45ac60c0 1188#define PALMAS_LDO4_CTRL_MODE_SLEEP_SHIFT 0x02
2945fbc2 1189#define PALMAS_LDO4_CTRL_MODE_ACTIVE 0x01
45ac60c0 1190#define PALMAS_LDO4_CTRL_MODE_ACTIVE_SHIFT 0x00
2945fbc2
GG		 1191
1192/* Bit definitions for LDO4_VOLTAGE */
45ac60c0
K		 1193#define PALMAS_LDO4_VOLTAGE_VSEL_MASK 0x3F
1194#define PALMAS_LDO4_VOLTAGE_VSEL_SHIFT 0x00
2945fbc2
GG		 1195
1196/* Bit definitions for LDO5_CTRL */
1197#define PALMAS_LDO5_CTRL_WR_S 0x80
45ac60c0 1198#define PALMAS_LDO5_CTRL_WR_S_SHIFT 0x07
2945fbc2 1199#define PALMAS_LDO5_CTRL_STATUS 0x10
45ac60c0 1200#define PALMAS_LDO5_CTRL_STATUS_SHIFT 0x04
2945fbc2 1201#define PALMAS_LDO5_CTRL_MODE_SLEEP 0x04
45ac60c0 1202#define PALMAS_LDO5_CTRL_MODE_SLEEP_SHIFT 0x02
2945fbc2 1203#define PALMAS_LDO5_CTRL_MODE_ACTIVE 0x01
45ac60c0 1204#define PALMAS_LDO5_CTRL_MODE_ACTIVE_SHIFT 0x00
2945fbc2
GG		 1205
1206/* Bit definitions for LDO5_VOLTAGE */
45ac60c0
K		 1207#define PALMAS_LDO5_VOLTAGE_VSEL_MASK 0x3F
1208#define PALMAS_LDO5_VOLTAGE_VSEL_SHIFT 0x00
2945fbc2
GG		 1209
1210/* Bit definitions for LDO6_CTRL */
1211#define PALMAS_LDO6_CTRL_WR_S 0x80
45ac60c0 1212#define PALMAS_LDO6_CTRL_WR_S_SHIFT 0x07
2945fbc2 1213#define PALMAS_LDO6_CTRL_LDO_VIB_EN 0x40
45ac60c0 1214#define PALMAS_LDO6_CTRL_LDO_VIB_EN_SHIFT 0x06
2945fbc2 1215#define PALMAS_LDO6_CTRL_STATUS 0x10
45ac60c0 1216#define PALMAS_LDO6_CTRL_STATUS_SHIFT 0x04
2945fbc2 1217#define PALMAS_LDO6_CTRL_MODE_SLEEP 0x04
45ac60c0 1218#define PALMAS_LDO6_CTRL_MODE_SLEEP_SHIFT 0x02
2945fbc2 1219#define PALMAS_LDO6_CTRL_MODE_ACTIVE 0x01
45ac60c0 1220#define PALMAS_LDO6_CTRL_MODE_ACTIVE_SHIFT 0x00
2945fbc2
GG		 1221
1222/* Bit definitions for LDO6_VOLTAGE */
45ac60c0
K		 1223#define PALMAS_LDO6_VOLTAGE_VSEL_MASK 0x3F
1224#define PALMAS_LDO6_VOLTAGE_VSEL_SHIFT 0x00
2945fbc2
GG		 1225
1226/* Bit definitions for LDO7_CTRL */
1227#define PALMAS_LDO7_CTRL_WR_S 0x80
45ac60c0 1228#define PALMAS_LDO7_CTRL_WR_S_SHIFT 0x07
2945fbc2 1229#define PALMAS_LDO7_CTRL_STATUS 0x10
45ac60c0 1230#define PALMAS_LDO7_CTRL_STATUS_SHIFT 0x04
2945fbc2 1231#define PALMAS_LDO7_CTRL_MODE_SLEEP 0x04
45ac60c0 1232#define PALMAS_LDO7_CTRL_MODE_SLEEP_SHIFT 0x02
2945fbc2 1233#define PALMAS_LDO7_CTRL_MODE_ACTIVE 0x01
45ac60c0 1234#define PALMAS_LDO7_CTRL_MODE_ACTIVE_SHIFT 0x00
2945fbc2
GG		 1235
1236/* Bit definitions for LDO7_VOLTAGE */
45ac60c0
K		 1237#define PALMAS_LDO7_VOLTAGE_VSEL_MASK 0x3F
1238#define PALMAS_LDO7_VOLTAGE_VSEL_SHIFT 0x00
2945fbc2
GG		 1239
1240/* Bit definitions for LDO8_CTRL */
1241#define PALMAS_LDO8_CTRL_WR_S 0x80
45ac60c0 1242#define PALMAS_LDO8_CTRL_WR_S_SHIFT 0x07
2945fbc2 1243#define PALMAS_LDO8_CTRL_LDO_TRACKING_EN 0x40
45ac60c0 1244#define PALMAS_LDO8_CTRL_LDO_TRACKING_EN_SHIFT 0x06
2945fbc2 1245#define PALMAS_LDO8_CTRL_STATUS 0x10
45ac60c0 1246#define PALMAS_LDO8_CTRL_STATUS_SHIFT 0x04
2945fbc2 1247#define PALMAS_LDO8_CTRL_MODE_SLEEP 0x04
45ac60c0 1248#define PALMAS_LDO8_CTRL_MODE_SLEEP_SHIFT 0x02
2945fbc2 1249#define PALMAS_LDO8_CTRL_MODE_ACTIVE 0x01
45ac60c0 1250#define PALMAS_LDO8_CTRL_MODE_ACTIVE_SHIFT 0x00
2945fbc2
GG		 1251
1252/* Bit definitions for LDO8_VOLTAGE */
45ac60c0
K		 1253#define PALMAS_LDO8_VOLTAGE_VSEL_MASK 0x3F
1254#define PALMAS_LDO8_VOLTAGE_VSEL_SHIFT 0x00
2945fbc2
GG		 1255
1256/* Bit definitions for LDO9_CTRL */
1257#define PALMAS_LDO9_CTRL_WR_S 0x80
45ac60c0 1258#define PALMAS_LDO9_CTRL_WR_S_SHIFT 0x07
2945fbc2 1259#define PALMAS_LDO9_CTRL_LDO_BYPASS_EN 0x40
45ac60c0 1260#define PALMAS_LDO9_CTRL_LDO_BYPASS_EN_SHIFT 0x06
2945fbc2 1261#define PALMAS_LDO9_CTRL_STATUS 0x10
45ac60c0 1262#define PALMAS_LDO9_CTRL_STATUS_SHIFT 0x04
2945fbc2 1263#define PALMAS_LDO9_CTRL_MODE_SLEEP 0x04
45ac60c0 1264#define PALMAS_LDO9_CTRL_MODE_SLEEP_SHIFT 0x02
2945fbc2 1265#define PALMAS_LDO9_CTRL_MODE_ACTIVE 0x01
45ac60c0 1266#define PALMAS_LDO9_CTRL_MODE_ACTIVE_SHIFT 0x00
2945fbc2
GG		 1267
1268/* Bit definitions for LDO9_VOLTAGE */
45ac60c0
K		 1269#define PALMAS_LDO9_VOLTAGE_VSEL_MASK 0x3F
1270#define PALMAS_LDO9_VOLTAGE_VSEL_SHIFT 0x00
2945fbc2
GG		 1271
1272/* Bit definitions for LDOLN_CTRL */
1273#define PALMAS_LDOLN_CTRL_WR_S 0x80
45ac60c0 1274#define PALMAS_LDOLN_CTRL_WR_S_SHIFT 0x07
2945fbc2 1275#define PALMAS_LDOLN_CTRL_STATUS 0x10
45ac60c0 1276#define PALMAS_LDOLN_CTRL_STATUS_SHIFT 0x04
2945fbc2 1277#define PALMAS_LDOLN_CTRL_MODE_SLEEP 0x04
45ac60c0 1278#define PALMAS_LDOLN_CTRL_MODE_SLEEP_SHIFT 0x02
2945fbc2 1279#define PALMAS_LDOLN_CTRL_MODE_ACTIVE 0x01
45ac60c0 1280#define PALMAS_LDOLN_CTRL_MODE_ACTIVE_SHIFT 0x00
2945fbc2
GG		 1281
1282/* Bit definitions for LDOLN_VOLTAGE */
45ac60c0
K		 1283#define PALMAS_LDOLN_VOLTAGE_VSEL_MASK 0x3F
1284#define PALMAS_LDOLN_VOLTAGE_VSEL_SHIFT 0x00
2945fbc2
GG		 1285
1286/* Bit definitions for LDOUSB_CTRL */
1287#define PALMAS_LDOUSB_CTRL_WR_S 0x80
45ac60c0 1288#define PALMAS_LDOUSB_CTRL_WR_S_SHIFT 0x07
2945fbc2 1289#define PALMAS_LDOUSB_CTRL_STATUS 0x10
45ac60c0 1290#define PALMAS_LDOUSB_CTRL_STATUS_SHIFT 0x04
2945fbc2 1291#define PALMAS_LDOUSB_CTRL_MODE_SLEEP 0x04
45ac60c0 1292#define PALMAS_LDOUSB_CTRL_MODE_SLEEP_SHIFT 0x02
2945fbc2 1293#define PALMAS_LDOUSB_CTRL_MODE_ACTIVE 0x01
45ac60c0 1294#define PALMAS_LDOUSB_CTRL_MODE_ACTIVE_SHIFT 0x00
2945fbc2
GG		 1295
1296/* Bit definitions for LDOUSB_VOLTAGE */
45ac60c0
K		 1297#define PALMAS_LDOUSB_VOLTAGE_VSEL_MASK 0x3F
1298#define PALMAS_LDOUSB_VOLTAGE_VSEL_SHIFT 0x00
2945fbc2
GG		 1299
1300/* Bit definitions for LDO_CTRL */
1301#define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS 0x01
45ac60c0 1302#define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS_SHIFT 0x00
2945fbc2
GG		 1303
1304/* Bit definitions for LDO_PD_CTRL1 */
1305#define PALMAS_LDO_PD_CTRL1_LDO8 0x80
45ac60c0 1306#define PALMAS_LDO_PD_CTRL1_LDO8_SHIFT 0x07
2945fbc2 1307#define PALMAS_LDO_PD_CTRL1_LDO7 0x40
45ac60c0 1308#define PALMAS_LDO_PD_CTRL1_LDO7_SHIFT 0x06
2945fbc2 1309#define PALMAS_LDO_PD_CTRL1_LDO6 0x20
45ac60c0 1310#define PALMAS_LDO_PD_CTRL1_LDO6_SHIFT 0x05
2945fbc2 1311#define PALMAS_LDO_PD_CTRL1_LDO5 0x10
45ac60c0 1312#define PALMAS_LDO_PD_CTRL1_LDO5_SHIFT 0x04
2945fbc2 1313#define PALMAS_LDO_PD_CTRL1_LDO4 0x08
45ac60c0 1314#define PALMAS_LDO_PD_CTRL1_LDO4_SHIFT 0x03
2945fbc2 1315#define PALMAS_LDO_PD_CTRL1_LDO3 0x04
45ac60c0 1316#define PALMAS_LDO_PD_CTRL1_LDO3_SHIFT 0x02
2945fbc2 1317#define PALMAS_LDO_PD_CTRL1_LDO2 0x02
45ac60c0 1318#define PALMAS_LDO_PD_CTRL1_LDO2_SHIFT 0x01
2945fbc2 1319#define PALMAS_LDO_PD_CTRL1_LDO1 0x01
45ac60c0 1320#define PALMAS_LDO_PD_CTRL1_LDO1_SHIFT 0x00
2945fbc2
GG		 1321
1322/* Bit definitions for LDO_PD_CTRL2 */
1323#define PALMAS_LDO_PD_CTRL2_LDOUSB 0x04
45ac60c0 1324#define PALMAS_LDO_PD_CTRL2_LDOUSB_SHIFT 0x02
2945fbc2 1325#define PALMAS_LDO_PD_CTRL2_LDOLN 0x02
45ac60c0 1326#define PALMAS_LDO_PD_CTRL2_LDOLN_SHIFT 0x01
2945fbc2 1327#define PALMAS_LDO_PD_CTRL2_LDO9 0x01
45ac60c0 1328#define PALMAS_LDO_PD_CTRL2_LDO9_SHIFT 0x00
2945fbc2
GG		 1329
1330/* Bit definitions for LDO_SHORT_STATUS1 */
1331#define PALMAS_LDO_SHORT_STATUS1_LDO8 0x80
45ac60c0 1332#define PALMAS_LDO_SHORT_STATUS1_LDO8_SHIFT 0x07
2945fbc2 1333#define PALMAS_LDO_SHORT_STATUS1_LDO7 0x40
45ac60c0 1334#define PALMAS_LDO_SHORT_STATUS1_LDO7_SHIFT 0x06
2945fbc2 1335#define PALMAS_LDO_SHORT_STATUS1_LDO6 0x20
45ac60c0 1336#define PALMAS_LDO_SHORT_STATUS1_LDO6_SHIFT 0x05
2945fbc2 1337#define PALMAS_LDO_SHORT_STATUS1_LDO5 0x10
45ac60c0 1338#define PALMAS_LDO_SHORT_STATUS1_LDO5_SHIFT 0x04
2945fbc2 1339#define PALMAS_LDO_SHORT_STATUS1_LDO4 0x08
45ac60c0 1340#define PALMAS_LDO_SHORT_STATUS1_LDO4_SHIFT 0x03
2945fbc2 1341#define PALMAS_LDO_SHORT_STATUS1_LDO3 0x04
45ac60c0 1342#define PALMAS_LDO_SHORT_STATUS1_LDO3_SHIFT 0x02
2945fbc2 1343#define PALMAS_LDO_SHORT_STATUS1_LDO2 0x02
45ac60c0 1344#define PALMAS_LDO_SHORT_STATUS1_LDO2_SHIFT 0x01
2945fbc2 1345#define PALMAS_LDO_SHORT_STATUS1_LDO1 0x01
45ac60c0 1346#define PALMAS_LDO_SHORT_STATUS1_LDO1_SHIFT 0x00
2945fbc2
GG		 1347
1348/* Bit definitions for LDO_SHORT_STATUS2 */
1349#define PALMAS_LDO_SHORT_STATUS2_LDOVANA 0x08
45ac60c0 1350#define PALMAS_LDO_SHORT_STATUS2_LDOVANA_SHIFT 0x03
2945fbc2 1351#define PALMAS_LDO_SHORT_STATUS2_LDOUSB 0x04
45ac60c0 1352#define PALMAS_LDO_SHORT_STATUS2_LDOUSB_SHIFT 0x02
2945fbc2 1353#define PALMAS_LDO_SHORT_STATUS2_LDOLN 0x02
45ac60c0 1354#define PALMAS_LDO_SHORT_STATUS2_LDOLN_SHIFT 0x01
2945fbc2 1355#define PALMAS_LDO_SHORT_STATUS2_LDO9 0x01
45ac60c0 1356#define PALMAS_LDO_SHORT_STATUS2_LDO9_SHIFT 0x00
2945fbc2
GG		 1357
1358/* Registers for function PMU_CONTROL */
45ac60c0
K		 1359#define PALMAS_DEV_CTRL 0x00
1360#define PALMAS_POWER_CTRL 0x01
1361#define PALMAS_VSYS_LO 0x02
1362#define PALMAS_VSYS_MON 0x03
1363#define PALMAS_VBAT_MON 0x04
1364#define PALMAS_WATCHDOG 0x05
1365#define PALMAS_BOOT_STATUS 0x06
1366#define PALMAS_BATTERY_BOUNCE 0x07
1367#define PALMAS_BACKUP_BATTERY_CTRL 0x08
1368#define PALMAS_LONG_PRESS_KEY 0x09
1369#define PALMAS_OSC_THERM_CTRL 0x0A
1370#define PALMAS_BATDEBOUNCING 0x0B
1371#define PALMAS_SWOFF_HWRST 0x0F
2945fbc2
GG		 1372#define PALMAS_SWOFF_COLDRST 0x10
1373#define PALMAS_SWOFF_STATUS 0x11
1374#define PALMAS_PMU_CONFIG 0x12
1375#define PALMAS_SPARE 0x14
1376#define PALMAS_PMU_SECONDARY_INT 0x15
1377#define PALMAS_SW_REVISION 0x17
1378#define PALMAS_EXT_CHRG_CTRL 0x18
1379#define PALMAS_PMU_SECONDARY_INT2 0x19
1380
1381/* Bit definitions for DEV_CTRL */
1382#define PALMAS_DEV_CTRL_DEV_STATUS_MASK 0x0c
45ac60c0 1383#define PALMAS_DEV_CTRL_DEV_STATUS_SHIFT 0x02
2945fbc2 1384#define PALMAS_DEV_CTRL_SW_RST 0x02
45ac60c0 1385#define PALMAS_DEV_CTRL_SW_RST_SHIFT 0x01
2945fbc2 1386#define PALMAS_DEV_CTRL_DEV_ON 0x01
45ac60c0 1387#define PALMAS_DEV_CTRL_DEV_ON_SHIFT 0x00
2945fbc2
GG		 1388
1389/* Bit definitions for POWER_CTRL */
1390#define PALMAS_POWER_CTRL_ENABLE2_MASK 0x04
45ac60c0 1391#define PALMAS_POWER_CTRL_ENABLE2_MASK_SHIFT 0x02
2945fbc2 1392#define PALMAS_POWER_CTRL_ENABLE1_MASK 0x02
45ac60c0 1393#define PALMAS_POWER_CTRL_ENABLE1_MASK_SHIFT 0x01
2945fbc2 1394#define PALMAS_POWER_CTRL_NSLEEP_MASK 0x01
45ac60c0 1395#define PALMAS_POWER_CTRL_NSLEEP_MASK_SHIFT 0x00
2945fbc2
GG		 1396
1397/* Bit definitions for VSYS_LO */
45ac60c0
K		 1398#define PALMAS_VSYS_LO_THRESHOLD_MASK 0x1F
1399#define PALMAS_VSYS_LO_THRESHOLD_SHIFT 0x00
2945fbc2
GG		 1400
1401/* Bit definitions for VSYS_MON */
1402#define PALMAS_VSYS_MON_ENABLE 0x80
45ac60c0
K		 1403#define PALMAS_VSYS_MON_ENABLE_SHIFT 0x07
1404#define PALMAS_VSYS_MON_THRESHOLD_MASK 0x3F
1405#define PALMAS_VSYS_MON_THRESHOLD_SHIFT 0x00
2945fbc2
GG		 1406
1407/* Bit definitions for VBAT_MON */
1408#define PALMAS_VBAT_MON_ENABLE 0x80
45ac60c0
K		 1409#define PALMAS_VBAT_MON_ENABLE_SHIFT 0x07
1410#define PALMAS_VBAT_MON_THRESHOLD_MASK 0x3F
1411#define PALMAS_VBAT_MON_THRESHOLD_SHIFT 0x00
2945fbc2
GG		 1412
1413/* Bit definitions for WATCHDOG */
1414#define PALMAS_WATCHDOG_LOCK 0x20
45ac60c0 1415#define PALMAS_WATCHDOG_LOCK_SHIFT 0x05
2945fbc2 1416#define PALMAS_WATCHDOG_ENABLE 0x10
45ac60c0 1417#define PALMAS_WATCHDOG_ENABLE_SHIFT 0x04
2945fbc2 1418#define PALMAS_WATCHDOG_MODE 0x08
45ac60c0 1419#define PALMAS_WATCHDOG_MODE_SHIFT 0x03
2945fbc2 1420#define PALMAS_WATCHDOG_TIMER_MASK 0x07
45ac60c0 1421#define PALMAS_WATCHDOG_TIMER_SHIFT 0x00
2945fbc2
GG		 1422
1423/* Bit definitions for BOOT_STATUS */
1424#define PALMAS_BOOT_STATUS_BOOT1 0x02
45ac60c0 1425#define PALMAS_BOOT_STATUS_BOOT1_SHIFT 0x01
2945fbc2 1426#define PALMAS_BOOT_STATUS_BOOT0 0x01
45ac60c0 1427#define PALMAS_BOOT_STATUS_BOOT0_SHIFT 0x00
2945fbc2
GG		 1428
1429/* Bit definitions for BATTERY_BOUNCE */
45ac60c0
K		 1430#define PALMAS_BATTERY_BOUNCE_BB_DELAY_MASK 0x3F
1431#define PALMAS_BATTERY_BOUNCE_BB_DELAY_SHIFT 0x00
2945fbc2
GG		 1432
1433/* Bit definitions for BACKUP_BATTERY_CTRL */
1434#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15 0x80
45ac60c0 1435#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15_SHIFT 0x07
2945fbc2 1436#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP 0x40
45ac60c0 1437#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP_SHIFT 0x06
2945fbc2 1438#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF 0x20
45ac60c0 1439#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF_SHIFT 0x05
2945fbc2 1440#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN 0x10
45ac60c0 1441#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN_SHIFT 0x04
2945fbc2 1442#define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG 0x08
45ac60c0 1443#define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG_SHIFT 0x03
2945fbc2 1444#define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_MASK 0x06
45ac60c0 1445#define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_SHIFT 0x01
2945fbc2 1446#define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN 0x01
45ac60c0 1447#define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN_SHIFT 0x00
2945fbc2
GG		 1448
1449/* Bit definitions for LONG_PRESS_KEY */
1450#define PALMAS_LONG_PRESS_KEY_LPK_LOCK 0x80
45ac60c0 1451#define PALMAS_LONG_PRESS_KEY_LPK_LOCK_SHIFT 0x07
2945fbc2 1452#define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR 0x10
45ac60c0 1453#define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR_SHIFT 0x04
2945fbc2 1454#define PALMAS_LONG_PRESS_KEY_LPK_TIME_MASK 0x0c
45ac60c0 1455#define PALMAS_LONG_PRESS_KEY_LPK_TIME_SHIFT 0x02
2945fbc2 1456#define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_MASK 0x03
45ac60c0 1457#define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_SHIFT 0x00
2945fbc2
GG		 1458
1459/* Bit definitions for OSC_THERM_CTRL */
1460#define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP 0x80
45ac60c0 1461#define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP_SHIFT 0x07
2945fbc2 1462#define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP 0x40
45ac60c0 1463#define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP_SHIFT 0x06
2945fbc2 1464#define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP 0x20
45ac60c0 1465#define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP_SHIFT 0x05
2945fbc2 1466#define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP 0x10
45ac60c0 1467#define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP_SHIFT 0x04
2945fbc2 1468#define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_MASK 0x0c
45ac60c0 1469#define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_SHIFT 0x02
2945fbc2 1470#define PALMAS_OSC_THERM_CTRL_OSC_BYPASS 0x02
45ac60c0 1471#define PALMAS_OSC_THERM_CTRL_OSC_BYPASS_SHIFT 0x01
2945fbc2 1472#define PALMAS_OSC_THERM_CTRL_OSC_HPMODE 0x01
45ac60c0 1473#define PALMAS_OSC_THERM_CTRL_OSC_HPMODE_SHIFT 0x00
2945fbc2
GG		 1474
1475/* Bit definitions for BATDEBOUNCING */
1476#define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS 0x80
45ac60c0 1477#define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS_SHIFT 0x07
2945fbc2 1478#define PALMAS_BATDEBOUNCING_BINS_DEB_MASK 0x78
45ac60c0 1479#define PALMAS_BATDEBOUNCING_BINS_DEB_SHIFT 0x03
2945fbc2 1480#define PALMAS_BATDEBOUNCING_BEXT_DEB_MASK 0x07
45ac60c0 1481#define PALMAS_BATDEBOUNCING_BEXT_DEB_SHIFT 0x00
2945fbc2
GG		 1482
1483/* Bit definitions for SWOFF_HWRST */
1484#define PALMAS_SWOFF_HWRST_PWRON_LPK 0x80
45ac60c0 1485#define PALMAS_SWOFF_HWRST_PWRON_LPK_SHIFT 0x07
2945fbc2 1486#define PALMAS_SWOFF_HWRST_PWRDOWN 0x40
45ac60c0 1487#define PALMAS_SWOFF_HWRST_PWRDOWN_SHIFT 0x06
2945fbc2 1488#define PALMAS_SWOFF_HWRST_WTD 0x20
45ac60c0 1489#define PALMAS_SWOFF_HWRST_WTD_SHIFT 0x05
2945fbc2 1490#define PALMAS_SWOFF_HWRST_TSHUT 0x10
45ac60c0 1491#define PALMAS_SWOFF_HWRST_TSHUT_SHIFT 0x04
2945fbc2 1492#define PALMAS_SWOFF_HWRST_RESET_IN 0x08
45ac60c0 1493#define PALMAS_SWOFF_HWRST_RESET_IN_SHIFT 0x03
2945fbc2 1494#define PALMAS_SWOFF_HWRST_SW_RST 0x04
45ac60c0 1495#define PALMAS_SWOFF_HWRST_SW_RST_SHIFT 0x02
2945fbc2 1496#define PALMAS_SWOFF_HWRST_VSYS_LO 0x02
45ac60c0 1497#define PALMAS_SWOFF_HWRST_VSYS_LO_SHIFT 0x01
2945fbc2 1498#define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN 0x01
45ac60c0 1499#define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN_SHIFT 0x00
2945fbc2
GG		 1500
1501/* Bit definitions for SWOFF_COLDRST */
1502#define PALMAS_SWOFF_COLDRST_PWRON_LPK 0x80
45ac60c0 1503#define PALMAS_SWOFF_COLDRST_PWRON_LPK_SHIFT 0x07
2945fbc2 1504#define PALMAS_SWOFF_COLDRST_PWRDOWN 0x40
45ac60c0 1505#define PALMAS_SWOFF_COLDRST_PWRDOWN_SHIFT 0x06
2945fbc2 1506#define PALMAS_SWOFF_COLDRST_WTD 0x20
45ac60c0 1507#define PALMAS_SWOFF_COLDRST_WTD_SHIFT 0x05
2945fbc2 1508#define PALMAS_SWOFF_COLDRST_TSHUT 0x10
45ac60c0 1509#define PALMAS_SWOFF_COLDRST_TSHUT_SHIFT 0x04
2945fbc2 1510#define PALMAS_SWOFF_COLDRST_RESET_IN 0x08
45ac60c0 1511#define PALMAS_SWOFF_COLDRST_RESET_IN_SHIFT 0x03
2945fbc2 1512#define PALMAS_SWOFF_COLDRST_SW_RST 0x04
45ac60c0 1513#define PALMAS_SWOFF_COLDRST_SW_RST_SHIFT 0x02
2945fbc2 1514#define PALMAS_SWOFF_COLDRST_VSYS_LO 0x02
45ac60c0 1515#define PALMAS_SWOFF_COLDRST_VSYS_LO_SHIFT 0x01
2945fbc2 1516#define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN 0x01
45ac60c0 1517#define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN_SHIFT 0x00
2945fbc2
GG		 1518
1519/* Bit definitions for SWOFF_STATUS */
1520#define PALMAS_SWOFF_STATUS_PWRON_LPK 0x80
45ac60c0 1521#define PALMAS_SWOFF_STATUS_PWRON_LPK_SHIFT 0x07
2945fbc2 1522#define PALMAS_SWOFF_STATUS_PWRDOWN 0x40
45ac60c0 1523#define PALMAS_SWOFF_STATUS_PWRDOWN_SHIFT 0x06
2945fbc2 1524#define PALMAS_SWOFF_STATUS_WTD 0x20
45ac60c0 1525#define PALMAS_SWOFF_STATUS_WTD_SHIFT 0x05
2945fbc2 1526#define PALMAS_SWOFF_STATUS_TSHUT 0x10
45ac60c0 1527#define PALMAS_SWOFF_STATUS_TSHUT_SHIFT 0x04
2945fbc2 1528#define PALMAS_SWOFF_STATUS_RESET_IN 0x08
45ac60c0 1529#define PALMAS_SWOFF_STATUS_RESET_IN_SHIFT 0x03
2945fbc2 1530#define PALMAS_SWOFF_STATUS_SW_RST 0x04
45ac60c0 1531#define PALMAS_SWOFF_STATUS_SW_RST_SHIFT 0x02
2945fbc2 1532#define PALMAS_SWOFF_STATUS_VSYS_LO 0x02
45ac60c0 1533#define PALMAS_SWOFF_STATUS_VSYS_LO_SHIFT 0x01
2945fbc2 1534#define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN 0x01
45ac60c0 1535#define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN_SHIFT 0x00
2945fbc2
GG		 1536
1537/* Bit definitions for PMU_CONFIG */
1538#define PALMAS_PMU_CONFIG_MULTI_CELL_EN 0x40
45ac60c0 1539#define PALMAS_PMU_CONFIG_MULTI_CELL_EN_SHIFT 0x06
2945fbc2 1540#define PALMAS_PMU_CONFIG_SPARE_MASK 0x30
45ac60c0 1541#define PALMAS_PMU_CONFIG_SPARE_SHIFT 0x04
2945fbc2 1542#define PALMAS_PMU_CONFIG_SWOFF_DLY_MASK 0x0c
45ac60c0 1543#define PALMAS_PMU_CONFIG_SWOFF_DLY_SHIFT 0x02
2945fbc2 1544#define PALMAS_PMU_CONFIG_GATE_RESET_OUT 0x02
45ac60c0 1545#define PALMAS_PMU_CONFIG_GATE_RESET_OUT_SHIFT 0x01
2945fbc2 1546#define PALMAS_PMU_CONFIG_AUTODEVON 0x01
45ac60c0 1547#define PALMAS_PMU_CONFIG_AUTODEVON_SHIFT 0x00
2945fbc2
GG		 1548
1549/* Bit definitions for SPARE */
1550#define PALMAS_SPARE_SPARE_MASK 0xf8
45ac60c0 1551#define PALMAS_SPARE_SPARE_SHIFT 0x03
2945fbc2 1552#define PALMAS_SPARE_REGEN3_OD 0x04
45ac60c0 1553#define PALMAS_SPARE_REGEN3_OD_SHIFT 0x02
2945fbc2 1554#define PALMAS_SPARE_REGEN2_OD 0x02
45ac60c0 1555#define PALMAS_SPARE_REGEN2_OD_SHIFT 0x01
2945fbc2 1556#define PALMAS_SPARE_REGEN1_OD 0x01
45ac60c0 1557#define PALMAS_SPARE_REGEN1_OD_SHIFT 0x00
2945fbc2
GG		 1558
1559/* Bit definitions for PMU_SECONDARY_INT */
1560#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC 0x80
45ac60c0 1561#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC_SHIFT 0x07
2945fbc2 1562#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC 0x40
45ac60c0 1563#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC_SHIFT 0x06
2945fbc2 1564#define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC 0x20
45ac60c0 1565#define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC_SHIFT 0x05
2945fbc2 1566#define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC 0x10
45ac60c0 1567#define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC_SHIFT 0x04
2945fbc2 1568#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK 0x08
45ac60c0 1569#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK_SHIFT 0x03
2945fbc2 1570#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK 0x04
45ac60c0 1571#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK_SHIFT 0x02
2945fbc2 1572#define PALMAS_PMU_SECONDARY_INT_BB_MASK 0x02
45ac60c0 1573#define PALMAS_PMU_SECONDARY_INT_BB_MASK_SHIFT 0x01
2945fbc2 1574#define PALMAS_PMU_SECONDARY_INT_FBI_MASK 0x01
45ac60c0 1575#define PALMAS_PMU_SECONDARY_INT_FBI_MASK_SHIFT 0x00
2945fbc2
GG		 1576
1577/* Bit definitions for SW_REVISION */
45ac60c0
K		 1578#define PALMAS_SW_REVISION_SW_REVISION_MASK 0xFF
1579#define PALMAS_SW_REVISION_SW_REVISION_SHIFT 0x00
2945fbc2
GG		 1580
1581/* Bit definitions for EXT_CHRG_CTRL */
1582#define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS 0x80
45ac60c0 1583#define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS_SHIFT 0x07
2945fbc2 1584#define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS 0x40
45ac60c0 1585#define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS_SHIFT 0x06
2945fbc2 1586#define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY 0x08
45ac60c0 1587#define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY_SHIFT 0x03
2945fbc2 1588#define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N 0x04
45ac60c0 1589#define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N_SHIFT 0x02
2945fbc2 1590#define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN 0x02
45ac60c0 1591#define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN_SHIFT 0x01
2945fbc2 1592#define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN 0x01
45ac60c0 1593#define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN_SHIFT 0x00
2945fbc2
GG		 1594
1595/* Bit definitions for PMU_SECONDARY_INT2 */
1596#define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC 0x20
45ac60c0 1597#define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC_SHIFT 0x05
2945fbc2 1598#define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC 0x10
45ac60c0 1599#define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC_SHIFT 0x04
2945fbc2 1600#define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK 0x02
45ac60c0 1601#define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK_SHIFT 0x01
2945fbc2 1602#define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK 0x01
45ac60c0 1603#define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK_SHIFT 0x00
2945fbc2
GG		 1604
1605/* Registers for function RESOURCE */
45ac60c0
K		 1606#define PALMAS_CLK32KG_CTRL 0x00
1607#define PALMAS_CLK32KGAUDIO_CTRL 0x01
1608#define PALMAS_REGEN1_CTRL 0x02
1609#define PALMAS_REGEN2_CTRL 0x03
1610#define PALMAS_SYSEN1_CTRL 0x04
1611#define PALMAS_SYSEN2_CTRL 0x05
1612#define PALMAS_NSLEEP_RES_ASSIGN 0x06
1613#define PALMAS_NSLEEP_SMPS_ASSIGN 0x07
1614#define PALMAS_NSLEEP_LDO_ASSIGN1 0x08
1615#define PALMAS_NSLEEP_LDO_ASSIGN2 0x09
1616#define PALMAS_ENABLE1_RES_ASSIGN 0x0A
1617#define PALMAS_ENABLE1_SMPS_ASSIGN 0x0B
1618#define PALMAS_ENABLE1_LDO_ASSIGN1 0x0C
1619#define PALMAS_ENABLE1_LDO_ASSIGN2 0x0D
1620#define PALMAS_ENABLE2_RES_ASSIGN 0x0E
1621#define PALMAS_ENABLE2_SMPS_ASSIGN 0x0F
2945fbc2
GG		 1622#define PALMAS_ENABLE2_LDO_ASSIGN1 0x10
1623#define PALMAS_ENABLE2_LDO_ASSIGN2 0x11
1624#define PALMAS_REGEN3_CTRL 0x12
1625
1626/* Bit definitions for CLK32KG_CTRL */
1627#define PALMAS_CLK32KG_CTRL_STATUS 0x10
45ac60c0 1628#define PALMAS_CLK32KG_CTRL_STATUS_SHIFT 0x04
2945fbc2 1629#define PALMAS_CLK32KG_CTRL_MODE_SLEEP 0x04
45ac60c0 1630#define PALMAS_CLK32KG_CTRL_MODE_SLEEP_SHIFT 0x02
2945fbc2 1631#define PALMAS_CLK32KG_CTRL_MODE_ACTIVE 0x01
45ac60c0 1632#define PALMAS_CLK32KG_CTRL_MODE_ACTIVE_SHIFT 0x00
2945fbc2
GG		 1633
1634/* Bit definitions for CLK32KGAUDIO_CTRL */
1635#define PALMAS_CLK32KGAUDIO_CTRL_STATUS 0x10
45ac60c0 1636#define PALMAS_CLK32KGAUDIO_CTRL_STATUS_SHIFT 0x04
2945fbc2 1637#define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3 0x08
45ac60c0 1638#define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3_SHIFT 0x03
2945fbc2 1639#define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP 0x04
45ac60c0 1640#define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP_SHIFT 0x02
2945fbc2 1641#define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE 0x01
45ac60c0 1642#define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE_SHIFT 0x00
2945fbc2
GG		 1643
1644/* Bit definitions for REGEN1_CTRL */
1645#define PALMAS_REGEN1_CTRL_STATUS 0x10
45ac60c0 1646#define PALMAS_REGEN1_CTRL_STATUS_SHIFT 0x04
2945fbc2 1647#define PALMAS_REGEN1_CTRL_MODE_SLEEP 0x04
45ac60c0 1648#define PALMAS_REGEN1_CTRL_MODE_SLEEP_SHIFT 0x02
2945fbc2 1649#define PALMAS_REGEN1_CTRL_MODE_ACTIVE 0x01
45ac60c0 1650#define PALMAS_REGEN1_CTRL_MODE_ACTIVE_SHIFT 0x00
2945fbc2
GG		 1651
1652/* Bit definitions for REGEN2_CTRL */
1653#define PALMAS_REGEN2_CTRL_STATUS 0x10
45ac60c0 1654#define PALMAS_REGEN2_CTRL_STATUS_SHIFT 0x04
2945fbc2 1655#define PALMAS_REGEN2_CTRL_MODE_SLEEP 0x04
45ac60c0 1656#define PALMAS_REGEN2_CTRL_MODE_SLEEP_SHIFT 0x02
2945fbc2 1657#define PALMAS_REGEN2_CTRL_MODE_ACTIVE 0x01
45ac60c0 1658#define PALMAS_REGEN2_CTRL_MODE_ACTIVE_SHIFT 0x00
2945fbc2
GG		 1659
1660/* Bit definitions for SYSEN1_CTRL */
1661#define PALMAS_SYSEN1_CTRL_STATUS 0x10
45ac60c0 1662#define PALMAS_SYSEN1_CTRL_STATUS_SHIFT 0x04
2945fbc2 1663#define PALMAS_SYSEN1_CTRL_MODE_SLEEP 0x04
45ac60c0 1664#define PALMAS_SYSEN1_CTRL_MODE_SLEEP_SHIFT 0x02
2945fbc2 1665#define PALMAS_SYSEN1_CTRL_MODE_ACTIVE 0x01
45ac60c0 1666#define PALMAS_SYSEN1_CTRL_MODE_ACTIVE_SHIFT 0x00
2945fbc2
GG		 1667
1668/* Bit definitions for SYSEN2_CTRL */
1669#define PALMAS_SYSEN2_CTRL_STATUS 0x10
45ac60c0 1670#define PALMAS_SYSEN2_CTRL_STATUS_SHIFT 0x04
2945fbc2 1671#define PALMAS_SYSEN2_CTRL_MODE_SLEEP 0x04
45ac60c0 1672#define PALMAS_SYSEN2_CTRL_MODE_SLEEP_SHIFT 0x02
2945fbc2 1673#define PALMAS_SYSEN2_CTRL_MODE_ACTIVE 0x01
45ac60c0 1674#define PALMAS_SYSEN2_CTRL_MODE_ACTIVE_SHIFT 0x00
2945fbc2
GG		 1675
1676/* Bit definitions for NSLEEP_RES_ASSIGN */
1677#define PALMAS_NSLEEP_RES_ASSIGN_REGEN3 0x40
45ac60c0 1678#define PALMAS_NSLEEP_RES_ASSIGN_REGEN3_SHIFT 0x06
2945fbc2 1679#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO 0x20
45ac60c0 1680#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO_SHIFT 0x05
2945fbc2 1681#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG 0x10
45ac60c0 1682#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG_SHIFT 0x04
2945fbc2 1683#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2 0x08
45ac60c0 1684#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2_SHIFT 0x03
2945fbc2 1685#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1 0x04
45ac60c0 1686#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1_SHIFT 0x02
2945fbc2 1687#define PALMAS_NSLEEP_RES_ASSIGN_REGEN2 0x02
45ac60c0 1688#define PALMAS_NSLEEP_RES_ASSIGN_REGEN2_SHIFT 0x01
2945fbc2 1689#define PALMAS_NSLEEP_RES_ASSIGN_REGEN1 0x01
45ac60c0 1690#define PALMAS_NSLEEP_RES_ASSIGN_REGEN1_SHIFT 0x00
2945fbc2
GG		 1691
1692/* Bit definitions for NSLEEP_SMPS_ASSIGN */
1693#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10 0x80
45ac60c0 1694#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10_SHIFT 0x07
2945fbc2 1695#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9 0x40
45ac60c0 1696#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9_SHIFT 0x06
2945fbc2 1697#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8 0x20
45ac60c0 1698#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8_SHIFT 0x05
2945fbc2 1699#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7 0x10
45ac60c0 1700#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7_SHIFT 0x04
2945fbc2 1701#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6 0x08
45ac60c0 1702#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6_SHIFT 0x03
2945fbc2 1703#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45 0x04
45ac60c0 1704#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45_SHIFT 0x02
2945fbc2 1705#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3 0x02
45ac60c0 1706#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT 0x01
2945fbc2 1707#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12 0x01
45ac60c0 1708#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12_SHIFT 0x00
2945fbc2
GG		 1709
1710/* Bit definitions for NSLEEP_LDO_ASSIGN1 */
1711#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8 0x80
45ac60c0 1712#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8_SHIFT 0x07
2945fbc2 1713#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7 0x40
45ac60c0 1714#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7_SHIFT 0x06
2945fbc2 1715#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6 0x20
45ac60c0 1716#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6_SHIFT 0x05
2945fbc2 1717#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5 0x10
45ac60c0 1718#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5_SHIFT 0x04
2945fbc2 1719#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4 0x08
45ac60c0 1720#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT 0x03
2945fbc2 1721#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3 0x04
45ac60c0 1722#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3_SHIFT 0x02
2945fbc2 1723#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2 0x02
45ac60c0 1724#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT 0x01
2945fbc2 1725#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1 0x01
45ac60c0 1726#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT 0x00
2945fbc2
GG		 1727
1728/* Bit definitions for NSLEEP_LDO_ASSIGN2 */
1729#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB 0x04
45ac60c0 1730#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB_SHIFT 0x02
2945fbc2 1731#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN 0x02
45ac60c0 1732#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN_SHIFT 0x01
2945fbc2 1733#define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9 0x01
45ac60c0 1734#define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9_SHIFT 0x00
2945fbc2
GG		 1735
1736/* Bit definitions for ENABLE1_RES_ASSIGN */
1737#define PALMAS_ENABLE1_RES_ASSIGN_REGEN3 0x40
45ac60c0 1738#define PALMAS_ENABLE1_RES_ASSIGN_REGEN3_SHIFT 0x06
2945fbc2 1739#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO 0x20
45ac60c0 1740#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO_SHIFT 0x05
2945fbc2 1741#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG 0x10
45ac60c0 1742#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG_SHIFT 0x04
2945fbc2 1743#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2 0x08
45ac60c0 1744#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2_SHIFT 0x03
2945fbc2 1745#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1 0x04
45ac60c0 1746#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1_SHIFT 0x02
2945fbc2 1747#define PALMAS_ENABLE1_RES_ASSIGN_REGEN2 0x02
45ac60c0 1748#define PALMAS_ENABLE1_RES_ASSIGN_REGEN2_SHIFT 0x01
2945fbc2 1749#define PALMAS_ENABLE1_RES_ASSIGN_REGEN1 0x01
45ac60c0 1750#define PALMAS_ENABLE1_RES_ASSIGN_REGEN1_SHIFT 0x00
2945fbc2
GG		 1751
1752/* Bit definitions for ENABLE1_SMPS_ASSIGN */
1753#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10 0x80
45ac60c0 1754#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10_SHIFT 0x07
2945fbc2 1755#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9 0x40
45ac60c0 1756#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9_SHIFT 0x06
2945fbc2 1757#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8 0x20
45ac60c0 1758#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8_SHIFT 0x05
2945fbc2 1759#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7 0x10
45ac60c0 1760#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7_SHIFT 0x04
2945fbc2 1761#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6 0x08
45ac60c0 1762#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6_SHIFT 0x03
2945fbc2 1763#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45 0x04
45ac60c0 1764#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45_SHIFT 0x02
2945fbc2 1765#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3 0x02
45ac60c0 1766#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT 0x01
2945fbc2 1767#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12 0x01
45ac60c0 1768#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12_SHIFT 0x00
2945fbc2
GG		 1769
1770/* Bit definitions for ENABLE1_LDO_ASSIGN1 */
1771#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8 0x80
45ac60c0 1772#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8_SHIFT 0x07
2945fbc2 1773#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7 0x40
45ac60c0 1774#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7_SHIFT 0x06
2945fbc2 1775#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6 0x20
45ac60c0 1776#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6_SHIFT 0x05
2945fbc2 1777#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5 0x10
45ac60c0 1778#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5_SHIFT 0x04
2945fbc2 1779#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4 0x08
45ac60c0 1780#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT 0x03
2945fbc2 1781#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3 0x04
45ac60c0 1782#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3_SHIFT 0x02
2945fbc2 1783#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2 0x02
45ac60c0 1784#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT 0x01
2945fbc2 1785#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1 0x01
45ac60c0 1786#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT 0x00
2945fbc2
GG		 1787
1788/* Bit definitions for ENABLE1_LDO_ASSIGN2 */
1789#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB 0x04
45ac60c0 1790#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB_SHIFT 0x02
2945fbc2 1791#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN 0x02
45ac60c0 1792#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN_SHIFT 0x01
2945fbc2 1793#define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9 0x01
45ac60c0 1794#define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9_SHIFT 0x00
2945fbc2
GG		 1795
1796/* Bit definitions for ENABLE2_RES_ASSIGN */
1797#define PALMAS_ENABLE2_RES_ASSIGN_REGEN3 0x40
45ac60c0 1798#define PALMAS_ENABLE2_RES_ASSIGN_REGEN3_SHIFT 0x06
2945fbc2 1799#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO 0x20
45ac60c0 1800#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO_SHIFT 0x05
2945fbc2 1801#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG 0x10
45ac60c0 1802#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG_SHIFT 0x04
2945fbc2 1803#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2 0x08
45ac60c0 1804#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2_SHIFT 0x03
2945fbc2 1805#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1 0x04
45ac60c0 1806#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1_SHIFT 0x02
2945fbc2 1807#define PALMAS_ENABLE2_RES_ASSIGN_REGEN2 0x02
45ac60c0 1808#define PALMAS_ENABLE2_RES_ASSIGN_REGEN2_SHIFT 0x01
2945fbc2 1809#define PALMAS_ENABLE2_RES_ASSIGN_REGEN1 0x01
45ac60c0 1810#define PALMAS_ENABLE2_RES_ASSIGN_REGEN1_SHIFT 0x00
2945fbc2
GG		 1811
1812/* Bit definitions for ENABLE2_SMPS_ASSIGN */
1813#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10 0x80
45ac60c0 1814#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10_SHIFT 0x07
2945fbc2 1815#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9 0x40
45ac60c0 1816#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9_SHIFT 0x06
2945fbc2 1817#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8 0x20
45ac60c0 1818#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8_SHIFT 0x05
2945fbc2 1819#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7 0x10
45ac60c0 1820#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7_SHIFT 0x04
2945fbc2 1821#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6 0x08
45ac60c0 1822#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6_SHIFT 0x03
2945fbc2 1823#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45 0x04
45ac60c0 1824#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45_SHIFT 0x02
2945fbc2 1825#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3 0x02
45ac60c0 1826#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT 0x01
2945fbc2 1827#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12 0x01
45ac60c0 1828#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12_SHIFT 0x00
2945fbc2
GG		 1829
1830/* Bit definitions for ENABLE2_LDO_ASSIGN1 */
1831#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8 0x80
45ac60c0 1832#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8_SHIFT 0x07
2945fbc2 1833#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7 0x40
45ac60c0 1834#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7_SHIFT 0x06
2945fbc2 1835#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6 0x20
45ac60c0 1836#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6_SHIFT 0x05
2945fbc2 1837#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5 0x10
45ac60c0 1838#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5_SHIFT 0x04
2945fbc2 1839#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4 0x08
45ac60c0 1840#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT 0x03
2945fbc2 1841#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3 0x04
45ac60c0 1842#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3_SHIFT 0x02
2945fbc2 1843#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2 0x02
45ac60c0 1844#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT 0x01
2945fbc2 1845#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1 0x01
45ac60c0 1846#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT 0x00
2945fbc2
GG		 1847
1848/* Bit definitions for ENABLE2_LDO_ASSIGN2 */
1849#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB 0x04
45ac60c0 1850#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB_SHIFT 0x02
2945fbc2 1851#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN 0x02
45ac60c0 1852#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN_SHIFT 0x01
2945fbc2 1853#define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9 0x01
45ac60c0 1854#define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9_SHIFT 0x00
2945fbc2
GG		 1855
1856/* Bit definitions for REGEN3_CTRL */
1857#define PALMAS_REGEN3_CTRL_STATUS 0x10
45ac60c0 1858#define PALMAS_REGEN3_CTRL_STATUS_SHIFT 0x04
2945fbc2 1859#define PALMAS_REGEN3_CTRL_MODE_SLEEP 0x04
45ac60c0 1860#define PALMAS_REGEN3_CTRL_MODE_SLEEP_SHIFT 0x02
2945fbc2 1861#define PALMAS_REGEN3_CTRL_MODE_ACTIVE 0x01
45ac60c0 1862#define PALMAS_REGEN3_CTRL_MODE_ACTIVE_SHIFT 0x00
2945fbc2
GG		 1863
1864/* Registers for function PAD_CONTROL */
45ac60c0
K		 1865#define PALMAS_OD_OUTPUT_CTRL2 0x02
1866#define PALMAS_POLARITY_CTRL2 0x03
1867#define PALMAS_PU_PD_INPUT_CTRL1 0x04
1868#define PALMAS_PU_PD_INPUT_CTRL2 0x05
1869#define PALMAS_PU_PD_INPUT_CTRL3 0x06
1870#define PALMAS_PU_PD_INPUT_CTRL5 0x07
1871#define PALMAS_OD_OUTPUT_CTRL 0x08
1872#define PALMAS_POLARITY_CTRL 0x09
1873#define PALMAS_PRIMARY_SECONDARY_PAD1 0x0A
1874#define PALMAS_PRIMARY_SECONDARY_PAD2 0x0B
1875#define PALMAS_I2C_SPI 0x0C
1876#define PALMAS_PU_PD_INPUT_CTRL4 0x0D
1877#define PALMAS_PRIMARY_SECONDARY_PAD3 0x0E
1878#define PALMAS_PRIMARY_SECONDARY_PAD4 0x0F
2945fbc2
GG		 1879
1880/* Bit definitions for PU_PD_INPUT_CTRL1 */
1881#define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD 0x40
45ac60c0 1882#define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD_SHIFT 0x06
2945fbc2 1883#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU 0x20
45ac60c0 1884#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU_SHIFT 0x05
2945fbc2 1885#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD 0x10
45ac60c0 1886#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD_SHIFT 0x04
2945fbc2 1887#define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD 0x04
45ac60c0 1888#define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD_SHIFT 0x02
2945fbc2 1889#define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU 0x02
45ac60c0 1890#define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU_SHIFT 0x01
2945fbc2
GG		 1891
1892/* Bit definitions for PU_PD_INPUT_CTRL2 */
1893#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU 0x20
45ac60c0 1894#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU_SHIFT 0x05
2945fbc2 1895#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD 0x10
45ac60c0 1896#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD_SHIFT 0x04
2945fbc2 1897#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU 0x08
45ac60c0 1898#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU_SHIFT 0x03
2945fbc2 1899#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD 0x04
45ac60c0 1900#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD_SHIFT 0x02
2945fbc2 1901#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU 0x02
45ac60c0 1902#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU_SHIFT 0x01
2945fbc2 1903#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD 0x01
45ac60c0 1904#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD_SHIFT 0x00
2945fbc2
GG		 1905
1906/* Bit definitions for PU_PD_INPUT_CTRL3 */
1907#define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD 0x40
45ac60c0 1908#define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD_SHIFT 0x06
2945fbc2 1909#define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD 0x10
45ac60c0 1910#define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD_SHIFT 0x04
2945fbc2 1911#define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD 0x04
45ac60c0 1912#define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD_SHIFT 0x02
2945fbc2 1913#define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD 0x01
45ac60c0 1914#define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD_SHIFT 0x00
2945fbc2
GG		 1915
1916/* Bit definitions for OD_OUTPUT_CTRL */
1917#define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD 0x80
45ac60c0 1918#define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD_SHIFT 0x07
2945fbc2 1919#define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD 0x40
45ac60c0 1920#define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD_SHIFT 0x06
2945fbc2 1921#define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD 0x20
45ac60c0 1922#define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD_SHIFT 0x05
2945fbc2 1923#define PALMAS_OD_OUTPUT_CTRL_INT_OD 0x08
45ac60c0 1924#define PALMAS_OD_OUTPUT_CTRL_INT_OD_SHIFT 0x03
2945fbc2
GG		 1925
1926/* Bit definitions for POLARITY_CTRL */
1927#define PALMAS_POLARITY_CTRL_INT_POLARITY 0x80
45ac60c0 1928#define PALMAS_POLARITY_CTRL_INT_POLARITY_SHIFT 0x07
2945fbc2 1929#define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY 0x40
45ac60c0 1930#define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY_SHIFT 0x06
2945fbc2 1931#define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY 0x20
45ac60c0 1932#define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY_SHIFT 0x05
2945fbc2 1933#define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY 0x10
45ac60c0 1934#define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY_SHIFT 0x04
2945fbc2 1935#define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY 0x08
45ac60c0 1936#define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY_SHIFT 0x03
2945fbc2 1937#define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY 0x04
45ac60c0 1938#define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY_SHIFT 0x02
2945fbc2 1939#define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY 0x02
45ac60c0 1940#define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY_SHIFT 0x01
2945fbc2 1941#define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY 0x01
45ac60c0 1942#define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY_SHIFT 0x00
2945fbc2
GG		 1943
1944/* Bit definitions for PRIMARY_SECONDARY_PAD1 */
1945#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3 0x80
45ac60c0 1946#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3_SHIFT 0x07
2945fbc2 1947#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK 0x60
45ac60c0 1948#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT 0x05
2945fbc2 1949#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK 0x18
45ac60c0 1950#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT 0x03
2945fbc2 1951#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0 0x04
45ac60c0 1952#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0_SHIFT 0x02
2945fbc2 1953#define PALMAS_PRIMARY_SECONDARY_PAD1_VAC 0x02
45ac60c0 1954#define PALMAS_PRIMARY_SECONDARY_PAD1_VAC_SHIFT 0x01
2945fbc2 1955#define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD 0x01
45ac60c0 1956#define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD_SHIFT 0x00
2945fbc2
GG		 1957
1958/* Bit definitions for PRIMARY_SECONDARY_PAD2 */
1959#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK 0x30
45ac60c0 1960#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_SHIFT 0x04
2945fbc2 1961#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6 0x08
45ac60c0 1962#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6_SHIFT 0x03
2945fbc2 1963#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK 0x06
45ac60c0 1964#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_SHIFT 0x01
2945fbc2 1965#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4 0x01
45ac60c0 1966#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4_SHIFT 0x00
2945fbc2
GG		 1967
1968/* Bit definitions for I2C_SPI */
1969#define PALMAS_I2C_SPI_I2C2OTP_EN 0x80
45ac60c0 1970#define PALMAS_I2C_SPI_I2C2OTP_EN_SHIFT 0x07
2945fbc2 1971#define PALMAS_I2C_SPI_I2C2OTP_PAGESEL 0x40
45ac60c0 1972#define PALMAS_I2C_SPI_I2C2OTP_PAGESEL_SHIFT 0x06
2945fbc2 1973#define PALMAS_I2C_SPI_ID_I2C2 0x20
45ac60c0 1974#define PALMAS_I2C_SPI_ID_I2C2_SHIFT 0x05
2945fbc2 1975#define PALMAS_I2C_SPI_I2C_SPI 0x10
45ac60c0
K		 1976#define PALMAS_I2C_SPI_I2C_SPI_SHIFT 0x04
1977#define PALMAS_I2C_SPI_ID_I2C1_MASK 0x0F
1978#define PALMAS_I2C_SPI_ID_I2C1_SHIFT 0x00
2945fbc2
GG		 1979
1980/* Bit definitions for PU_PD_INPUT_CTRL4 */
1981#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD 0x40
45ac60c0 1982#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD_SHIFT 0x06
2945fbc2 1983#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD 0x10
45ac60c0 1984#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD_SHIFT 0x04
2945fbc2 1985#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD 0x04
45ac60c0 1986#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD_SHIFT 0x02
2945fbc2 1987#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD 0x01
45ac60c0 1988#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD_SHIFT 0x00
2945fbc2
GG		 1989
1990/* Bit definitions for PRIMARY_SECONDARY_PAD3 */
1991#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2 0x02
45ac60c0 1992#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2_SHIFT 0x01
2945fbc2 1993#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1 0x01
45ac60c0 1994#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1_SHIFT 0x00
2945fbc2
GG		 1995
1996/* Registers for function LED_PWM */
45ac60c0
K		 1997#define PALMAS_LED_PERIOD_CTRL 0x00
1998#define PALMAS_LED_CTRL 0x01
1999#define PALMAS_PWM_CTRL1 0x02
2000#define PALMAS_PWM_CTRL2 0x03
2945fbc2
GG		 2001
2002/* Bit definitions for LED_PERIOD_CTRL */
2003#define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_MASK 0x38
45ac60c0 2004#define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_SHIFT 0x03
2945fbc2 2005#define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_MASK 0x07
45ac60c0 2006#define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_SHIFT 0x00
2945fbc2
GG		 2007
2008/* Bit definitions for LED_CTRL */
2009#define PALMAS_LED_CTRL_LED_2_SEQ 0x20
45ac60c0 2010#define PALMAS_LED_CTRL_LED_2_SEQ_SHIFT 0x05
2945fbc2 2011#define PALMAS_LED_CTRL_LED_1_SEQ 0x10
45ac60c0 2012#define PALMAS_LED_CTRL_LED_1_SEQ_SHIFT 0x04
2945fbc2 2013#define PALMAS_LED_CTRL_LED_2_ON_TIME_MASK 0x0c
45ac60c0 2014#define PALMAS_LED_CTRL_LED_2_ON_TIME_SHIFT 0x02
2945fbc2 2015#define PALMAS_LED_CTRL_LED_1_ON_TIME_MASK 0x03
45ac60c0 2016#define PALMAS_LED_CTRL_LED_1_ON_TIME_SHIFT 0x00
2945fbc2
GG		 2017
2018/* Bit definitions for PWM_CTRL1 */
2019#define PALMAS_PWM_CTRL1_PWM_FREQ_EN 0x02
45ac60c0 2020#define PALMAS_PWM_CTRL1_PWM_FREQ_EN_SHIFT 0x01
2945fbc2 2021#define PALMAS_PWM_CTRL1_PWM_FREQ_SEL 0x01
45ac60c0 2022#define PALMAS_PWM_CTRL1_PWM_FREQ_SEL_SHIFT 0x00
2945fbc2
GG		 2023
2024/* Bit definitions for PWM_CTRL2 */
45ac60c0
K		 2025#define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_MASK 0xFF
2026#define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_SHIFT 0x00
2945fbc2
GG		 2027
2028/* Registers for function INTERRUPT */
45ac60c0
K		 2029#define PALMAS_INT1_STATUS 0x00
2030#define PALMAS_INT1_MASK 0x01
2031#define PALMAS_INT1_LINE_STATE 0x02
2032#define PALMAS_INT1_EDGE_DETECT1_RESERVED 0x03
2033#define PALMAS_INT1_EDGE_DETECT2_RESERVED 0x04
2034#define PALMAS_INT2_STATUS 0x05
2035#define PALMAS_INT2_MASK 0x06
2036#define PALMAS_INT2_LINE_STATE 0x07
2037#define PALMAS_INT2_EDGE_DETECT1_RESERVED 0x08
2038#define PALMAS_INT2_EDGE_DETECT2_RESERVED 0x09
2039#define PALMAS_INT3_STATUS 0x0A
2040#define PALMAS_INT3_MASK 0x0B
2041#define PALMAS_INT3_LINE_STATE 0x0C
2042#define PALMAS_INT3_EDGE_DETECT1_RESERVED 0x0D
2043#define PALMAS_INT3_EDGE_DETECT2_RESERVED 0x0E
2044#define PALMAS_INT4_STATUS 0x0F
2945fbc2
GG		 2045#define PALMAS_INT4_MASK 0x10
2046#define PALMAS_INT4_LINE_STATE 0x11
2047#define PALMAS_INT4_EDGE_DETECT1 0x12
2048#define PALMAS_INT4_EDGE_DETECT2 0x13
2049#define PALMAS_INT_CTRL 0x14
2050
2051/* Bit definitions for INT1_STATUS */
2052#define PALMAS_INT1_STATUS_VBAT_MON 0x80
45ac60c0 2053#define PALMAS_INT1_STATUS_VBAT_MON_SHIFT 0x07
2945fbc2 2054#define PALMAS_INT1_STATUS_VSYS_MON 0x40
45ac60c0 2055#define PALMAS_INT1_STATUS_VSYS_MON_SHIFT 0x06
2945fbc2 2056#define PALMAS_INT1_STATUS_HOTDIE 0x20
45ac60c0 2057#define PALMAS_INT1_STATUS_HOTDIE_SHIFT 0x05
2945fbc2 2058#define PALMAS_INT1_STATUS_PWRDOWN 0x10
45ac60c0 2059#define PALMAS_INT1_STATUS_PWRDOWN_SHIFT 0x04
2945fbc2 2060#define PALMAS_INT1_STATUS_RPWRON 0x08
45ac60c0 2061#define PALMAS_INT1_STATUS_RPWRON_SHIFT 0x03
2945fbc2 2062#define PALMAS_INT1_STATUS_LONG_PRESS_KEY 0x04
45ac60c0 2063#define PALMAS_INT1_STATUS_LONG_PRESS_KEY_SHIFT 0x02
2945fbc2 2064#define PALMAS_INT1_STATUS_PWRON 0x02
45ac60c0 2065#define PALMAS_INT1_STATUS_PWRON_SHIFT 0x01
2945fbc2 2066#define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV 0x01
45ac60c0 2067#define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV_SHIFT 0x00
2945fbc2
GG		 2068
2069/* Bit definitions for INT1_MASK */
2070#define PALMAS_INT1_MASK_VBAT_MON 0x80
45ac60c0 2071#define PALMAS_INT1_MASK_VBAT_MON_SHIFT 0x07
2945fbc2 2072#define PALMAS_INT1_MASK_VSYS_MON 0x40
45ac60c0 2073#define PALMAS_INT1_MASK_VSYS_MON_SHIFT 0x06
2945fbc2 2074#define PALMAS_INT1_MASK_HOTDIE 0x20
45ac60c0 2075#define PALMAS_INT1_MASK_HOTDIE_SHIFT 0x05
2945fbc2 2076#define PALMAS_INT1_MASK_PWRDOWN 0x10
45ac60c0 2077#define PALMAS_INT1_MASK_PWRDOWN_SHIFT 0x04
2945fbc2 2078#define PALMAS_INT1_MASK_RPWRON 0x08
45ac60c0 2079#define PALMAS_INT1_MASK_RPWRON_SHIFT 0x03
2945fbc2 2080#define PALMAS_INT1_MASK_LONG_PRESS_KEY 0x04
45ac60c0 2081#define PALMAS_INT1_MASK_LONG_PRESS_KEY_SHIFT 0x02
2945fbc2 2082#define PALMAS_INT1_MASK_PWRON 0x02
45ac60c0 2083#define PALMAS_INT1_MASK_PWRON_SHIFT 0x01
2945fbc2 2084#define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV 0x01
45ac60c0 2085#define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV_SHIFT 0x00
2945fbc2
GG		 2086
2087/* Bit definitions for INT1_LINE_STATE */
2088#define PALMAS_INT1_LINE_STATE_VBAT_MON 0x80
45ac60c0 2089#define PALMAS_INT1_LINE_STATE_VBAT_MON_SHIFT 0x07
2945fbc2 2090#define PALMAS_INT1_LINE_STATE_VSYS_MON 0x40
45ac60c0 2091#define PALMAS_INT1_LINE_STATE_VSYS_MON_SHIFT 0x06
2945fbc2 2092#define PALMAS_INT1_LINE_STATE_HOTDIE 0x20
45ac60c0 2093#define PALMAS_INT1_LINE_STATE_HOTDIE_SHIFT 0x05
2945fbc2 2094#define PALMAS_INT1_LINE_STATE_PWRDOWN 0x10
45ac60c0 2095#define PALMAS_INT1_LINE_STATE_PWRDOWN_SHIFT 0x04
2945fbc2 2096#define PALMAS_INT1_LINE_STATE_RPWRON 0x08
45ac60c0 2097#define PALMAS_INT1_LINE_STATE_RPWRON_SHIFT 0x03
2945fbc2 2098#define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY 0x04
45ac60c0 2099#define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT 0x02
2945fbc2 2100#define PALMAS_INT1_LINE_STATE_PWRON 0x02
45ac60c0 2101#define PALMAS_INT1_LINE_STATE_PWRON_SHIFT 0x01
2945fbc2 2102#define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV 0x01
45ac60c0 2103#define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV_SHIFT 0x00
2945fbc2
GG		 2104
2105/* Bit definitions for INT2_STATUS */
2106#define PALMAS_INT2_STATUS_VAC_ACOK 0x80
45ac60c0 2107#define PALMAS_INT2_STATUS_VAC_ACOK_SHIFT 0x07
2945fbc2 2108#define PALMAS_INT2_STATUS_SHORT 0x40
45ac60c0 2109#define PALMAS_INT2_STATUS_SHORT_SHIFT 0x06
2945fbc2 2110#define PALMAS_INT2_STATUS_FBI_BB 0x20
45ac60c0 2111#define PALMAS_INT2_STATUS_FBI_BB_SHIFT 0x05
2945fbc2 2112#define PALMAS_INT2_STATUS_RESET_IN 0x10
45ac60c0 2113#define PALMAS_INT2_STATUS_RESET_IN_SHIFT 0x04
2945fbc2 2114#define PALMAS_INT2_STATUS_BATREMOVAL 0x08
45ac60c0 2115#define PALMAS_INT2_STATUS_BATREMOVAL_SHIFT 0x03
2945fbc2 2116#define PALMAS_INT2_STATUS_WDT 0x04
45ac60c0 2117#define PALMAS_INT2_STATUS_WDT_SHIFT 0x02
2945fbc2 2118#define PALMAS_INT2_STATUS_RTC_TIMER 0x02
45ac60c0 2119#define PALMAS_INT2_STATUS_RTC_TIMER_SHIFT 0x01
2945fbc2 2120#define PALMAS_INT2_STATUS_RTC_ALARM 0x01
45ac60c0 2121#define PALMAS_INT2_STATUS_RTC_ALARM_SHIFT 0x00
2945fbc2
GG		 2122
2123/* Bit definitions for INT2_MASK */
2124#define PALMAS_INT2_MASK_VAC_ACOK 0x80
45ac60c0 2125#define PALMAS_INT2_MASK_VAC_ACOK_SHIFT 0x07
2945fbc2 2126#define PALMAS_INT2_MASK_SHORT 0x40
45ac60c0 2127#define PALMAS_INT2_MASK_SHORT_SHIFT 0x06
2945fbc2 2128#define PALMAS_INT2_MASK_FBI_BB 0x20
45ac60c0 2129#define PALMAS_INT2_MASK_FBI_BB_SHIFT 0x05
2945fbc2 2130#define PALMAS_INT2_MASK_RESET_IN 0x10
45ac60c0 2131#define PALMAS_INT2_MASK_RESET_IN_SHIFT 0x04
2945fbc2 2132#define PALMAS_INT2_MASK_BATREMOVAL 0x08
45ac60c0 2133#define PALMAS_INT2_MASK_BATREMOVAL_SHIFT 0x03
2945fbc2 2134#define PALMAS_INT2_MASK_WDT 0x04
45ac60c0 2135#define PALMAS_INT2_MASK_WDT_SHIFT 0x02
2945fbc2 2136#define PALMAS_INT2_MASK_RTC_TIMER 0x02
45ac60c0 2137#define PALMAS_INT2_MASK_RTC_TIMER_SHIFT 0x01
2945fbc2 2138#define PALMAS_INT2_MASK_RTC_ALARM 0x01
45ac60c0 2139#define PALMAS_INT2_MASK_RTC_ALARM_SHIFT 0x00
2945fbc2
GG		 2140
2141/* Bit definitions for INT2_LINE_STATE */
2142#define PALMAS_INT2_LINE_STATE_VAC_ACOK 0x80
45ac60c0 2143#define PALMAS_INT2_LINE_STATE_VAC_ACOK_SHIFT 0x07
2945fbc2 2144#define PALMAS_INT2_LINE_STATE_SHORT 0x40
45ac60c0 2145#define PALMAS_INT2_LINE_STATE_SHORT_SHIFT 0x06
2945fbc2 2146#define PALMAS_INT2_LINE_STATE_FBI_BB 0x20
45ac60c0 2147#define PALMAS_INT2_LINE_STATE_FBI_BB_SHIFT 0x05
2945fbc2 2148#define PALMAS_INT2_LINE_STATE_RESET_IN 0x10
45ac60c0 2149#define PALMAS_INT2_LINE_STATE_RESET_IN_SHIFT 0x04
2945fbc2 2150#define PALMAS_INT2_LINE_STATE_BATREMOVAL 0x08
45ac60c0 2151#define PALMAS_INT2_LINE_STATE_BATREMOVAL_SHIFT 0x03
2945fbc2 2152#define PALMAS_INT2_LINE_STATE_WDT 0x04
45ac60c0 2153#define PALMAS_INT2_LINE_STATE_WDT_SHIFT 0x02
2945fbc2 2154#define PALMAS_INT2_LINE_STATE_RTC_TIMER 0x02
45ac60c0 2155#define PALMAS_INT2_LINE_STATE_RTC_TIMER_SHIFT 0x01
2945fbc2 2156#define PALMAS_INT2_LINE_STATE_RTC_ALARM 0x01
45ac60c0 2157#define PALMAS_INT2_LINE_STATE_RTC_ALARM_SHIFT 0x00
2945fbc2
GG		 2158
2159/* Bit definitions for INT3_STATUS */
2160#define PALMAS_INT3_STATUS_VBUS 0x80
45ac60c0 2161#define PALMAS_INT3_STATUS_VBUS_SHIFT 0x07
2945fbc2 2162#define PALMAS_INT3_STATUS_VBUS_OTG 0x40
45ac60c0 2163#define PALMAS_INT3_STATUS_VBUS_OTG_SHIFT 0x06
2945fbc2 2164#define PALMAS_INT3_STATUS_ID 0x20
45ac60c0 2165#define PALMAS_INT3_STATUS_ID_SHIFT 0x05
2945fbc2 2166#define PALMAS_INT3_STATUS_ID_OTG 0x10
45ac60c0 2167#define PALMAS_INT3_STATUS_ID_OTG_SHIFT 0x04
2945fbc2 2168#define PALMAS_INT3_STATUS_GPADC_EOC_RT 0x08
45ac60c0 2169#define PALMAS_INT3_STATUS_GPADC_EOC_RT_SHIFT 0x03
2945fbc2 2170#define PALMAS_INT3_STATUS_GPADC_EOC_SW 0x04
45ac60c0 2171#define PALMAS_INT3_STATUS_GPADC_EOC_SW_SHIFT 0x02
2945fbc2 2172#define PALMAS_INT3_STATUS_GPADC_AUTO_1 0x02
45ac60c0 2173#define PALMAS_INT3_STATUS_GPADC_AUTO_1_SHIFT 0x01
2945fbc2 2174#define PALMAS_INT3_STATUS_GPADC_AUTO_0 0x01
45ac60c0 2175#define PALMAS_INT3_STATUS_GPADC_AUTO_0_SHIFT 0x00
2945fbc2
GG		 2176
2177/* Bit definitions for INT3_MASK */
2178#define PALMAS_INT3_MASK_VBUS 0x80
45ac60c0 2179#define PALMAS_INT3_MASK_VBUS_SHIFT 0x07
2945fbc2 2180#define PALMAS_INT3_MASK_VBUS_OTG 0x40
45ac60c0 2181#define PALMAS_INT3_MASK_VBUS_OTG_SHIFT 0x06
2945fbc2 2182#define PALMAS_INT3_MASK_ID 0x20
45ac60c0 2183#define PALMAS_INT3_MASK_ID_SHIFT 0x05
2945fbc2 2184#define PALMAS_INT3_MASK_ID_OTG 0x10
45ac60c0 2185#define PALMAS_INT3_MASK_ID_OTG_SHIFT 0x04
2945fbc2 2186#define PALMAS_INT3_MASK_GPADC_EOC_RT 0x08
45ac60c0 2187#define PALMAS_INT3_MASK_GPADC_EOC_RT_SHIFT 0x03
2945fbc2 2188#define PALMAS_INT3_MASK_GPADC_EOC_SW 0x04
45ac60c0 2189#define PALMAS_INT3_MASK_GPADC_EOC_SW_SHIFT 0x02
2945fbc2 2190#define PALMAS_INT3_MASK_GPADC_AUTO_1 0x02
45ac60c0 2191#define PALMAS_INT3_MASK_GPADC_AUTO_1_SHIFT 0x01
2945fbc2 2192#define PALMAS_INT3_MASK_GPADC_AUTO_0 0x01
45ac60c0 2193#define PALMAS_INT3_MASK_GPADC_AUTO_0_SHIFT 0x00
2945fbc2
GG		 2194
2195/* Bit definitions for INT3_LINE_STATE */
2196#define PALMAS_INT3_LINE_STATE_VBUS 0x80
45ac60c0 2197#define PALMAS_INT3_LINE_STATE_VBUS_SHIFT 0x07
2945fbc2 2198#define PALMAS_INT3_LINE_STATE_VBUS_OTG 0x40
45ac60c0 2199#define PALMAS_INT3_LINE_STATE_VBUS_OTG_SHIFT 0x06
2945fbc2 2200#define PALMAS_INT3_LINE_STATE_ID 0x20
45ac60c0 2201#define PALMAS_INT3_LINE_STATE_ID_SHIFT 0x05
2945fbc2 2202#define PALMAS_INT3_LINE_STATE_ID_OTG 0x10
45ac60c0 2203#define PALMAS_INT3_LINE_STATE_ID_OTG_SHIFT 0x04
2945fbc2 2204#define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT 0x08
45ac60c0 2205#define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT_SHIFT 0x03
2945fbc2 2206#define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW 0x04
45ac60c0 2207#define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT 0x02
2945fbc2 2208#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1 0x02
45ac60c0 2209#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT 0x01
2945fbc2 2210#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0 0x01
45ac60c0 2211#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT 0x00
2945fbc2
GG		 2212
2213/* Bit definitions for INT4_STATUS */
2214#define PALMAS_INT4_STATUS_GPIO_7 0x80
45ac60c0 2215#define PALMAS_INT4_STATUS_GPIO_7_SHIFT 0x07
2945fbc2 2216#define PALMAS_INT4_STATUS_GPIO_6 0x40
45ac60c0 2217#define PALMAS_INT4_STATUS_GPIO_6_SHIFT 0x06
2945fbc2 2218#define PALMAS_INT4_STATUS_GPIO_5 0x20
45ac60c0 2219#define PALMAS_INT4_STATUS_GPIO_5_SHIFT 0x05
2945fbc2 2220#define PALMAS_INT4_STATUS_GPIO_4 0x10
45ac60c0 2221#define PALMAS_INT4_STATUS_GPIO_4_SHIFT 0x04
2945fbc2 2222#define PALMAS_INT4_STATUS_GPIO_3 0x08
45ac60c0 2223#define PALMAS_INT4_STATUS_GPIO_3_SHIFT 0x03
2945fbc2 2224#define PALMAS_INT4_STATUS_GPIO_2 0x04
45ac60c0 2225#define PALMAS_INT4_STATUS_GPIO_2_SHIFT 0x02
2945fbc2 2226#define PALMAS_INT4_STATUS_GPIO_1 0x02
45ac60c0 2227#define PALMAS_INT4_STATUS_GPIO_1_SHIFT 0x01
2945fbc2 2228#define PALMAS_INT4_STATUS_GPIO_0 0x01
45ac60c0 2229#define PALMAS_INT4_STATUS_GPIO_0_SHIFT 0x00
2945fbc2
GG		 2230
2231/* Bit definitions for INT4_MASK */
2232#define PALMAS_INT4_MASK_GPIO_7 0x80
45ac60c0 2233#define PALMAS_INT4_MASK_GPIO_7_SHIFT 0x07
2945fbc2 2234#define PALMAS_INT4_MASK_GPIO_6 0x40
45ac60c0 2235#define PALMAS_INT4_MASK_GPIO_6_SHIFT 0x06
2945fbc2 2236#define PALMAS_INT4_MASK_GPIO_5 0x20
45ac60c0 2237#define PALMAS_INT4_MASK_GPIO_5_SHIFT 0x05
2945fbc2 2238#define PALMAS_INT4_MASK_GPIO_4 0x10
45ac60c0 2239#define PALMAS_INT4_MASK_GPIO_4_SHIFT 0x04
2945fbc2 2240#define PALMAS_INT4_MASK_GPIO_3 0x08
45ac60c0 2241#define PALMAS_INT4_MASK_GPIO_3_SHIFT 0x03
2945fbc2 2242#define PALMAS_INT4_MASK_GPIO_2 0x04
45ac60c0 2243#define PALMAS_INT4_MASK_GPIO_2_SHIFT 0x02
2945fbc2 2244#define PALMAS_INT4_MASK_GPIO_1 0x02
45ac60c0 2245#define PALMAS_INT4_MASK_GPIO_1_SHIFT 0x01
2945fbc2 2246#define PALMAS_INT4_MASK_GPIO_0 0x01
45ac60c0 2247#define PALMAS_INT4_MASK_GPIO_0_SHIFT 0x00
2945fbc2
GG		 2248
2249/* Bit definitions for INT4_LINE_STATE */
2250#define PALMAS_INT4_LINE_STATE_GPIO_7 0x80
45ac60c0 2251#define PALMAS_INT4_LINE_STATE_GPIO_7_SHIFT 0x07
2945fbc2 2252#define PALMAS_INT4_LINE_STATE_GPIO_6 0x40
45ac60c0 2253#define PALMAS_INT4_LINE_STATE_GPIO_6_SHIFT 0x06
2945fbc2 2254#define PALMAS_INT4_LINE_STATE_GPIO_5 0x20
45ac60c0 2255#define PALMAS_INT4_LINE_STATE_GPIO_5_SHIFT 0x05
2945fbc2 2256#define PALMAS_INT4_LINE_STATE_GPIO_4 0x10
45ac60c0 2257#define PALMAS_INT4_LINE_STATE_GPIO_4_SHIFT 0x04
2945fbc2 2258#define PALMAS_INT4_LINE_STATE_GPIO_3 0x08
45ac60c0 2259#define PALMAS_INT4_LINE_STATE_GPIO_3_SHIFT 0x03
2945fbc2 2260#define PALMAS_INT4_LINE_STATE_GPIO_2 0x04
45ac60c0 2261#define PALMAS_INT4_LINE_STATE_GPIO_2_SHIFT 0x02
2945fbc2 2262#define PALMAS_INT4_LINE_STATE_GPIO_1 0x02
45ac60c0 2263#define PALMAS_INT4_LINE_STATE_GPIO_1_SHIFT 0x01
2945fbc2 2264#define PALMAS_INT4_LINE_STATE_GPIO_0 0x01
45ac60c0 2265#define PALMAS_INT4_LINE_STATE_GPIO_0_SHIFT 0x00
2945fbc2
GG		 2266
2267/* Bit definitions for INT4_EDGE_DETECT1 */
2268#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING 0x80
45ac60c0 2269#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT 0x07
2945fbc2 2270#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING 0x40
45ac60c0 2271#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT 0x06
2945fbc2 2272#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING 0x20
45ac60c0 2273#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT 0x05
2945fbc2 2274#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING 0x10
45ac60c0 2275#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT 0x04
2945fbc2 2276#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING 0x08
45ac60c0 2277#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT 0x03
2945fbc2 2278#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING 0x04
45ac60c0 2279#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT 0x02
2945fbc2 2280#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING 0x02
45ac60c0 2281#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT 0x01
2945fbc2 2282#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING 0x01
45ac60c0 2283#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT 0x00
2945fbc2
GG		 2284
2285/* Bit definitions for INT4_EDGE_DETECT2 */
2286#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING 0x80
45ac60c0 2287#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING_SHIFT 0x07
2945fbc2 2288#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING 0x40
45ac60c0 2289#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING_SHIFT 0x06
2945fbc2 2290#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING 0x20
45ac60c0 2291#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT 0x05
2945fbc2 2292#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING 0x10
45ac60c0 2293#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT 0x04
2945fbc2 2294#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING 0x08
45ac60c0 2295#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT 0x03
2945fbc2 2296#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING 0x04
45ac60c0 2297#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT 0x02
2945fbc2 2298#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING 0x02
45ac60c0 2299#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT 0x01
2945fbc2 2300#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING 0x01
45ac60c0 2301#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT 0x00
2945fbc2
GG		 2302
2303/* Bit definitions for INT_CTRL */
2304#define PALMAS_INT_CTRL_INT_PENDING 0x04
45ac60c0 2305#define PALMAS_INT_CTRL_INT_PENDING_SHIFT 0x02
2945fbc2 2306#define PALMAS_INT_CTRL_INT_CLEAR 0x01
45ac60c0 2307#define PALMAS_INT_CTRL_INT_CLEAR_SHIFT 0x00
2945fbc2
GG		 2308
2309/* Registers for function USB_OTG */
45ac60c0
K		 2310#define PALMAS_USB_WAKEUP 0x03
2311#define PALMAS_USB_VBUS_CTRL_SET 0x04
2312#define PALMAS_USB_VBUS_CTRL_CLR 0x05
2313#define PALMAS_USB_ID_CTRL_SET 0x06
2314#define PALMAS_USB_ID_CTRL_CLEAR 0x07
2315#define PALMAS_USB_VBUS_INT_SRC 0x08
2316#define PALMAS_USB_VBUS_INT_LATCH_SET 0x09
2317#define PALMAS_USB_VBUS_INT_LATCH_CLR 0x0A
2318#define PALMAS_USB_VBUS_INT_EN_LO_SET 0x0B
2319#define PALMAS_USB_VBUS_INT_EN_LO_CLR 0x0C
2320#define PALMAS_USB_VBUS_INT_EN_HI_SET 0x0D
2321#define PALMAS_USB_VBUS_INT_EN_HI_CLR 0x0E
2322#define PALMAS_USB_ID_INT_SRC 0x0F
2945fbc2
GG		 2323#define PALMAS_USB_ID_INT_LATCH_SET 0x10
2324#define PALMAS_USB_ID_INT_LATCH_CLR 0x11
2325#define PALMAS_USB_ID_INT_EN_LO_SET 0x12
2326#define PALMAS_USB_ID_INT_EN_LO_CLR 0x13
2327#define PALMAS_USB_ID_INT_EN_HI_SET 0x14
2328#define PALMAS_USB_ID_INT_EN_HI_CLR 0x15
2329#define PALMAS_USB_OTG_ADP_CTRL 0x16
2330#define PALMAS_USB_OTG_ADP_HIGH 0x17
2331#define PALMAS_USB_OTG_ADP_LOW 0x18
2332#define PALMAS_USB_OTG_ADP_RISE 0x19
2333#define PALMAS_USB_OTG_REVISION 0x1A
2334
2335/* Bit definitions for USB_WAKEUP */
2336#define PALMAS_USB_WAKEUP_ID_WK_UP_COMP 0x01
45ac60c0 2337#define PALMAS_USB_WAKEUP_ID_WK_UP_COMP_SHIFT 0x00
2945fbc2
GG		 2338
2339/* Bit definitions for USB_VBUS_CTRL_SET */
2340#define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS 0x80
45ac60c0 2341#define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS_SHIFT 0x07
2945fbc2 2342#define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG 0x20
45ac60c0 2343#define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG_SHIFT 0x05
2945fbc2 2344#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC 0x10
45ac60c0 2345#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC_SHIFT 0x04
2945fbc2 2346#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK 0x08
45ac60c0 2347#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK_SHIFT 0x03
2945fbc2 2348#define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP 0x04
45ac60c0 2349#define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP_SHIFT 0x02
2945fbc2
GG		 2350
2351/* Bit definitions for USB_VBUS_CTRL_CLR */
2352#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS 0x80
45ac60c0 2353#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS_SHIFT 0x07
2945fbc2 2354#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG 0x20
45ac60c0 2355#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG_SHIFT 0x05
2945fbc2 2356#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC 0x10
45ac60c0 2357#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC_SHIFT 0x04
2945fbc2 2358#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK 0x08
45ac60c0 2359#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK_SHIFT 0x03
2945fbc2 2360#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP 0x04
45ac60c0 2361#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP_SHIFT 0x02
2945fbc2
GG		 2362
2363/* Bit definitions for USB_ID_CTRL_SET */
2364#define PALMAS_USB_ID_CTRL_SET_ID_PU_220K 0x80
45ac60c0 2365#define PALMAS_USB_ID_CTRL_SET_ID_PU_220K_SHIFT 0x07
2945fbc2 2366#define PALMAS_USB_ID_CTRL_SET_ID_PU_100K 0x40
45ac60c0 2367#define PALMAS_USB_ID_CTRL_SET_ID_PU_100K_SHIFT 0x06
2945fbc2 2368#define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV 0x20
45ac60c0 2369#define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV_SHIFT 0x05
2945fbc2 2370#define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U 0x10
45ac60c0 2371#define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U_SHIFT 0x04
2945fbc2 2372#define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U 0x08
45ac60c0 2373#define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U_SHIFT 0x03
2945fbc2 2374#define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP 0x04
45ac60c0 2375#define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP_SHIFT 0x02
2945fbc2
GG		 2376
2377/* Bit definitions for USB_ID_CTRL_CLEAR */
2378#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K 0x80
45ac60c0 2379#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K_SHIFT 0x07
2945fbc2 2380#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K 0x40
45ac60c0 2381#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K_SHIFT 0x06
2945fbc2 2382#define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV 0x20
45ac60c0 2383#define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV_SHIFT 0x05
2945fbc2 2384#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U 0x10
45ac60c0 2385#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U_SHIFT 0x04
2945fbc2 2386#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U 0x08
45ac60c0 2387#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U_SHIFT 0x03
2945fbc2 2388#define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP 0x04
45ac60c0 2389#define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP_SHIFT 0x02
2945fbc2
GG		 2390
2391/* Bit definitions for USB_VBUS_INT_SRC */
2392#define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD 0x80
45ac60c0 2393#define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD_SHIFT 0x07
2945fbc2 2394#define PALMAS_USB_VBUS_INT_SRC_VADP_PRB 0x40
45ac60c0 2395#define PALMAS_USB_VBUS_INT_SRC_VADP_PRB_SHIFT 0x06
2945fbc2 2396#define PALMAS_USB_VBUS_INT_SRC_VADP_SNS 0x20
45ac60c0 2397#define PALMAS_USB_VBUS_INT_SRC_VADP_SNS_SHIFT 0x05
2945fbc2 2398#define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD 0x08
45ac60c0 2399#define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD_SHIFT 0x03
2945fbc2 2400#define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD 0x04
45ac60c0 2401#define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD_SHIFT 0x02
2945fbc2 2402#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD 0x02
45ac60c0 2403#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD_SHIFT 0x01
2945fbc2 2404#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END 0x01
45ac60c0 2405#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END_SHIFT 0x00
2945fbc2
GG		 2406
2407/* Bit definitions for USB_VBUS_INT_LATCH_SET */
2408#define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD 0x80
45ac60c0 2409#define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD_SHIFT 0x07
2945fbc2 2410#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB 0x40
45ac60c0 2411#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB_SHIFT 0x06
2945fbc2 2412#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS 0x20
45ac60c0 2413#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS_SHIFT 0x05
2945fbc2 2414#define PALMAS_USB_VBUS_INT_LATCH_SET_ADP 0x10
45ac60c0 2415#define PALMAS_USB_VBUS_INT_LATCH_SET_ADP_SHIFT 0x04
2945fbc2 2416#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD 0x08
45ac60c0 2417#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD_SHIFT 0x03
2945fbc2 2418#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD 0x04
45ac60c0 2419#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD_SHIFT 0x02
2945fbc2 2420#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD 0x02
45ac60c0 2421#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD_SHIFT 0x01
2945fbc2 2422#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END 0x01
45ac60c0 2423#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END_SHIFT 0x00
2945fbc2
GG		 2424
2425/* Bit definitions for USB_VBUS_INT_LATCH_CLR */
2426#define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD 0x80
45ac60c0 2427#define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD_SHIFT 0x07
2945fbc2 2428#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB 0x40
45ac60c0 2429#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB_SHIFT 0x06
2945fbc2 2430#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS 0x20
45ac60c0 2431#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS_SHIFT 0x05
2945fbc2 2432#define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP 0x10
45ac60c0 2433#define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP_SHIFT 0x04
2945fbc2 2434#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD 0x08
45ac60c0 2435#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD_SHIFT 0x03
2945fbc2 2436#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD 0x04
45ac60c0 2437#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD_SHIFT 0x02
2945fbc2 2438#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD 0x02
45ac60c0 2439#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD_SHIFT 0x01
2945fbc2 2440#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END 0x01
45ac60c0 2441#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END_SHIFT 0x00
2945fbc2
GG		 2442
2443/* Bit definitions for USB_VBUS_INT_EN_LO_SET */
2444#define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD 0x80
45ac60c0 2445#define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD_SHIFT 0x07
2945fbc2 2446#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB 0x40
45ac60c0 2447#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB_SHIFT 0x06
2945fbc2 2448#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS 0x20
45ac60c0 2449#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS_SHIFT 0x05
2945fbc2 2450#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD 0x08
45ac60c0 2451#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD_SHIFT 0x03
2945fbc2 2452#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD 0x04
45ac60c0 2453#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD_SHIFT 0x02
2945fbc2 2454#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD 0x02
45ac60c0 2455#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD_SHIFT 0x01
2945fbc2 2456#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END 0x01
45ac60c0 2457#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END_SHIFT 0x00
2945fbc2
GG		 2458
2459/* Bit definitions for USB_VBUS_INT_EN_LO_CLR */
2460#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD 0x80
45ac60c0 2461#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD_SHIFT 0x07
2945fbc2 2462#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB 0x40
45ac60c0 2463#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB_SHIFT 0x06
2945fbc2 2464#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS 0x20
45ac60c0 2465#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS_SHIFT 0x05
2945fbc2 2466#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD 0x08
45ac60c0 2467#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD_SHIFT 0x03
2945fbc2 2468#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD 0x04
45ac60c0 2469#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD_SHIFT 0x02
2945fbc2 2470#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD 0x02
45ac60c0 2471#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD_SHIFT 0x01
2945fbc2 2472#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END 0x01
45ac60c0 2473#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END_SHIFT 0x00
2945fbc2
GG		 2474
2475/* Bit definitions for USB_VBUS_INT_EN_HI_SET */
2476#define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD 0x80
45ac60c0 2477#define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD_SHIFT 0x07
2945fbc2 2478#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB 0x40
45ac60c0 2479#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB_SHIFT 0x06
2945fbc2 2480#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS 0x20
45ac60c0 2481#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS_SHIFT 0x05
2945fbc2 2482#define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP 0x10
45ac60c0 2483#define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP_SHIFT 0x04
2945fbc2 2484#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD 0x08
45ac60c0 2485#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD_SHIFT 0x03
2945fbc2 2486#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD 0x04
45ac60c0 2487#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD_SHIFT 0x02
2945fbc2 2488#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD 0x02
45ac60c0 2489#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD_SHIFT 0x01
2945fbc2 2490#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END 0x01
45ac60c0 2491#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END_SHIFT 0x00
2945fbc2
GG		 2492
2493/* Bit definitions for USB_VBUS_INT_EN_HI_CLR */
2494#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD 0x80
45ac60c0 2495#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD_SHIFT 0x07
2945fbc2 2496#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB 0x40
45ac60c0 2497#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB_SHIFT 0x06
2945fbc2 2498#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS 0x20
45ac60c0 2499#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS_SHIFT 0x05
2945fbc2 2500#define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP 0x10
45ac60c0 2501#define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP_SHIFT 0x04
2945fbc2 2502#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD 0x08
45ac60c0 2503#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD_SHIFT 0x03
2945fbc2 2504#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD 0x04
45ac60c0 2505#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD_SHIFT 0x02
2945fbc2 2506#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD 0x02
45ac60c0 2507#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD_SHIFT 0x01
2945fbc2 2508#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END 0x01
45ac60c0 2509#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END_SHIFT 0x00
2945fbc2
GG		 2510
2511/* Bit definitions for USB_ID_INT_SRC */
2512#define PALMAS_USB_ID_INT_SRC_ID_FLOAT 0x10
45ac60c0 2513#define PALMAS_USB_ID_INT_SRC_ID_FLOAT_SHIFT 0x04
2945fbc2 2514#define PALMAS_USB_ID_INT_SRC_ID_A 0x08
45ac60c0 2515#define PALMAS_USB_ID_INT_SRC_ID_A_SHIFT 0x03
2945fbc2 2516#define PALMAS_USB_ID_INT_SRC_ID_B 0x04
45ac60c0 2517#define PALMAS_USB_ID_INT_SRC_ID_B_SHIFT 0x02
2945fbc2 2518#define PALMAS_USB_ID_INT_SRC_ID_C 0x02
45ac60c0 2519#define PALMAS_USB_ID_INT_SRC_ID_C_SHIFT 0x01
2945fbc2 2520#define PALMAS_USB_ID_INT_SRC_ID_GND 0x01
45ac60c0 2521#define PALMAS_USB_ID_INT_SRC_ID_GND_SHIFT 0x00
2945fbc2
GG		 2522
2523/* Bit definitions for USB_ID_INT_LATCH_SET */
2524#define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT 0x10
45ac60c0 2525#define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT_SHIFT 0x04
2945fbc2 2526#define PALMAS_USB_ID_INT_LATCH_SET_ID_A 0x08
45ac60c0 2527#define PALMAS_USB_ID_INT_LATCH_SET_ID_A_SHIFT 0x03
2945fbc2 2528#define PALMAS_USB_ID_INT_LATCH_SET_ID_B 0x04
45ac60c0 2529#define PALMAS_USB_ID_INT_LATCH_SET_ID_B_SHIFT 0x02
2945fbc2 2530#define PALMAS_USB_ID_INT_LATCH_SET_ID_C 0x02
45ac60c0 2531#define PALMAS_USB_ID_INT_LATCH_SET_ID_C_SHIFT 0x01
2945fbc2 2532#define PALMAS_USB_ID_INT_LATCH_SET_ID_GND 0x01
45ac60c0 2533#define PALMAS_USB_ID_INT_LATCH_SET_ID_GND_SHIFT 0x00
2945fbc2
GG		 2534
2535/* Bit definitions for USB_ID_INT_LATCH_CLR */
2536#define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT 0x10
45ac60c0 2537#define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT_SHIFT 0x04
2945fbc2 2538#define PALMAS_USB_ID_INT_LATCH_CLR_ID_A 0x08
45ac60c0 2539#define PALMAS_USB_ID_INT_LATCH_CLR_ID_A_SHIFT 0x03
2945fbc2 2540#define PALMAS_USB_ID_INT_LATCH_CLR_ID_B 0x04
45ac60c0 2541#define PALMAS_USB_ID_INT_LATCH_CLR_ID_B_SHIFT 0x02
2945fbc2 2542#define PALMAS_USB_ID_INT_LATCH_CLR_ID_C 0x02
45ac60c0 2543#define PALMAS_USB_ID_INT_LATCH_CLR_ID_C_SHIFT 0x01
2945fbc2 2544#define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND 0x01
45ac60c0 2545#define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND_SHIFT 0x00
2945fbc2
GG		 2546
2547/* Bit definitions for USB_ID_INT_EN_LO_SET */
2548#define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT 0x10
45ac60c0 2549#define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT_SHIFT 0x04
2945fbc2 2550#define PALMAS_USB_ID_INT_EN_LO_SET_ID_A 0x08
45ac60c0 2551#define PALMAS_USB_ID_INT_EN_LO_SET_ID_A_SHIFT 0x03
2945fbc2 2552#define PALMAS_USB_ID_INT_EN_LO_SET_ID_B 0x04
45ac60c0 2553#define PALMAS_USB_ID_INT_EN_LO_SET_ID_B_SHIFT 0x02
2945fbc2 2554#define PALMAS_USB_ID_INT_EN_LO_SET_ID_C 0x02
45ac60c0 2555#define PALMAS_USB_ID_INT_EN_LO_SET_ID_C_SHIFT 0x01
2945fbc2 2556#define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND 0x01
45ac60c0 2557#define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND_SHIFT 0x00
2945fbc2
GG		 2558
2559/* Bit definitions for USB_ID_INT_EN_LO_CLR */
2560#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT 0x10
45ac60c0 2561#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT_SHIFT 0x04
2945fbc2 2562#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A 0x08
45ac60c0 2563#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A_SHIFT 0x03
2945fbc2 2564#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B 0x04
45ac60c0 2565#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B_SHIFT 0x02
2945fbc2 2566#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C 0x02
45ac60c0 2567#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C_SHIFT 0x01
2945fbc2 2568#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND 0x01
45ac60c0 2569#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND_SHIFT 0x00
2945fbc2
GG		 2570
2571/* Bit definitions for USB_ID_INT_EN_HI_SET */
2572#define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT 0x10
45ac60c0 2573#define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT_SHIFT 0x04
2945fbc2 2574#define PALMAS_USB_ID_INT_EN_HI_SET_ID_A 0x08
45ac60c0 2575#define PALMAS_USB_ID_INT_EN_HI_SET_ID_A_SHIFT 0x03
2945fbc2 2576#define PALMAS_USB_ID_INT_EN_HI_SET_ID_B 0x04
45ac60c0 2577#define PALMAS_USB_ID_INT_EN_HI_SET_ID_B_SHIFT 0x02
2945fbc2 2578#define PALMAS_USB_ID_INT_EN_HI_SET_ID_C 0x02
45ac60c0 2579#define PALMAS_USB_ID_INT_EN_HI_SET_ID_C_SHIFT 0x01
2945fbc2 2580#define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND 0x01
45ac60c0 2581#define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND_SHIFT 0x00
2945fbc2
GG		 2582
2583/* Bit definitions for USB_ID_INT_EN_HI_CLR */
2584#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT 0x10
45ac60c0 2585#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT_SHIFT 0x04
2945fbc2 2586#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A 0x08
45ac60c0 2587#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A_SHIFT 0x03
2945fbc2 2588#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B 0x04
45ac60c0 2589#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B_SHIFT 0x02
2945fbc2 2590#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C 0x02
45ac60c0 2591#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C_SHIFT 0x01
2945fbc2 2592#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND 0x01
45ac60c0 2593#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND_SHIFT 0x00
2945fbc2
GG		 2594
2595/* Bit definitions for USB_OTG_ADP_CTRL */
2596#define PALMAS_USB_OTG_ADP_CTRL_ADP_EN 0x04
45ac60c0 2597#define PALMAS_USB_OTG_ADP_CTRL_ADP_EN_SHIFT 0x02
2945fbc2 2598#define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_MASK 0x03
45ac60c0 2599#define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_SHIFT 0x00
2945fbc2
GG		 2600
2601/* Bit definitions for USB_OTG_ADP_HIGH */
45ac60c0
K		 2602#define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_MASK 0xFF
2603#define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_SHIFT 0x00
2945fbc2
GG		 2604
2605/* Bit definitions for USB_OTG_ADP_LOW */
45ac60c0
K		 2606#define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_MASK 0xFF
2607#define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_SHIFT 0x00
2945fbc2
GG		 2608
2609/* Bit definitions for USB_OTG_ADP_RISE */
45ac60c0
K		 2610#define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_MASK 0xFF
2611#define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_SHIFT 0x00
2945fbc2
GG		 2612
2613/* Bit definitions for USB_OTG_REVISION */
2614#define PALMAS_USB_OTG_REVISION_OTG_REV 0x01
45ac60c0 2615#define PALMAS_USB_OTG_REVISION_OTG_REV_SHIFT 0x00
2945fbc2
GG		 2616
2617/* Registers for function VIBRATOR */
45ac60c0 2618#define PALMAS_VIBRA_CTRL 0x00
2945fbc2
GG		 2619
2620/* Bit definitions for VIBRA_CTRL */
2621#define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_MASK 0x06
45ac60c0 2622#define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_SHIFT 0x01
2945fbc2 2623#define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL 0x01
45ac60c0 2624#define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL_SHIFT 0x00
2945fbc2
GG		 2625
2626/* Registers for function GPIO */
45ac60c0
K		 2627#define PALMAS_GPIO_DATA_IN 0x00
2628#define PALMAS_GPIO_DATA_DIR 0x01
2629#define PALMAS_GPIO_DATA_OUT 0x02
2630#define PALMAS_GPIO_DEBOUNCE_EN 0x03
2631#define PALMAS_GPIO_CLEAR_DATA_OUT 0x04
2632#define PALMAS_GPIO_SET_DATA_OUT 0x05
2633#define PALMAS_PU_PD_GPIO_CTRL1 0x06
2634#define PALMAS_PU_PD_GPIO_CTRL2 0x07
2635#define PALMAS_OD_OUTPUT_GPIO_CTRL 0x08
2636#define PALMAS_GPIO_DATA_IN2 0x09
0a8d3e24
LD		 2637#define PALMAS_GPIO_DATA_DIR2 0x0A
2638#define PALMAS_GPIO_DATA_OUT2 0x0B
2639#define PALMAS_GPIO_DEBOUNCE_EN2 0x0C
2640#define PALMAS_GPIO_CLEAR_DATA_OUT2 0x0D
2641#define PALMAS_GPIO_SET_DATA_OUT2 0x0E
2642#define PALMAS_PU_PD_GPIO_CTRL3 0x0F
2643#define PALMAS_PU_PD_GPIO_CTRL4 0x10
2644#define PALMAS_OD_OUTPUT_GPIO_CTRL2 0x11
2945fbc2
GG		 2645
2646/* Bit definitions for GPIO_DATA_IN */
2647#define PALMAS_GPIO_DATA_IN_GPIO_7_IN 0x80
45ac60c0 2648#define PALMAS_GPIO_DATA_IN_GPIO_7_IN_SHIFT 0x07
2945fbc2 2649#define PALMAS_GPIO_DATA_IN_GPIO_6_IN 0x40
45ac60c0 2650#define PALMAS_GPIO_DATA_IN_GPIO_6_IN_SHIFT 0x06
2945fbc2 2651#define PALMAS_GPIO_DATA_IN_GPIO_5_IN 0x20
45ac60c0 2652#define PALMAS_GPIO_DATA_IN_GPIO_5_IN_SHIFT 0x05
2945fbc2 2653#define PALMAS_GPIO_DATA_IN_GPIO_4_IN 0x10
45ac60c0 2654#define PALMAS_GPIO_DATA_IN_GPIO_4_IN_SHIFT 0x04
2945fbc2 2655#define PALMAS_GPIO_DATA_IN_GPIO_3_IN 0x08
45ac60c0 2656#define PALMAS_GPIO_DATA_IN_GPIO_3_IN_SHIFT 0x03
2945fbc2 2657#define PALMAS_GPIO_DATA_IN_GPIO_2_IN 0x04
45ac60c0 2658#define PALMAS_GPIO_DATA_IN_GPIO_2_IN_SHIFT 0x02
2945fbc2 2659#define PALMAS_GPIO_DATA_IN_GPIO_1_IN 0x02
45ac60c0 2660#define PALMAS_GPIO_DATA_IN_GPIO_1_IN_SHIFT 0x01
2945fbc2 2661#define PALMAS_GPIO_DATA_IN_GPIO_0_IN 0x01
45ac60c0 2662#define PALMAS_GPIO_DATA_IN_GPIO_0_IN_SHIFT 0x00
2945fbc2
GG		 2663
2664/* Bit definitions for GPIO_DATA_DIR */
2665#define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR 0x80
45ac60c0 2666#define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR_SHIFT 0x07
2945fbc2 2667#define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR 0x40
45ac60c0 2668#define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR_SHIFT 0x06
2945fbc2 2669#define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR 0x20
45ac60c0 2670#define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR_SHIFT 0x05
2945fbc2 2671#define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR 0x10
45ac60c0 2672#define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR_SHIFT 0x04
2945fbc2 2673#define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR 0x08
45ac60c0 2674#define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR_SHIFT 0x03
2945fbc2 2675#define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR 0x04
45ac60c0 2676#define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR_SHIFT 0x02
2945fbc2 2677#define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR 0x02
45ac60c0 2678#define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR_SHIFT 0x01
2945fbc2 2679#define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR 0x01
45ac60c0 2680#define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR_SHIFT 0x00
2945fbc2
GG		 2681
2682/* Bit definitions for GPIO_DATA_OUT */
2683#define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT 0x80
45ac60c0 2684#define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT_SHIFT 0x07
2945fbc2 2685#define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT 0x40
45ac60c0 2686#define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT_SHIFT 0x06
2945fbc2 2687#define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT 0x20
45ac60c0 2688#define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT_SHIFT 0x05
2945fbc2 2689#define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT 0x10
45ac60c0 2690#define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT_SHIFT 0x04
2945fbc2 2691#define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT 0x08
45ac60c0 2692#define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT_SHIFT 0x03
2945fbc2 2693#define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT 0x04
45ac60c0 2694#define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT_SHIFT 0x02
2945fbc2 2695#define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT 0x02
45ac60c0 2696#define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT_SHIFT 0x01
2945fbc2 2697#define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT 0x01
45ac60c0 2698#define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT_SHIFT 0x00
2945fbc2
GG		 2699
2700/* Bit definitions for GPIO_DEBOUNCE_EN */
2701#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN 0x80
45ac60c0 2702#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN_SHIFT 0x07
2945fbc2 2703#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN 0x40
45ac60c0 2704#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN_SHIFT 0x06
2945fbc2 2705#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN 0x20
45ac60c0 2706#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN_SHIFT 0x05
2945fbc2 2707#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN 0x10
45ac60c0 2708#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN_SHIFT 0x04
2945fbc2 2709#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN 0x08
45ac60c0 2710#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN_SHIFT 0x03
2945fbc2 2711#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN 0x04
45ac60c0 2712#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN_SHIFT 0x02
2945fbc2 2713#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN 0x02
45ac60c0 2714#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN_SHIFT 0x01
2945fbc2 2715#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN 0x01
45ac60c0 2716#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN_SHIFT 0x00
2945fbc2
GG		 2717
2718/* Bit definitions for GPIO_CLEAR_DATA_OUT */
2719#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT 0x80
45ac60c0 2720#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT_SHIFT 0x07
2945fbc2 2721#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT 0x40
45ac60c0 2722#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT_SHIFT 0x06
2945fbc2 2723#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT 0x20
45ac60c0 2724#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT_SHIFT 0x05
2945fbc2 2725#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT 0x10
45ac60c0 2726#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT_SHIFT 0x04
2945fbc2 2727#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT 0x08
45ac60c0 2728#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT_SHIFT 0x03
2945fbc2 2729#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT 0x04
45ac60c0 2730#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT_SHIFT 0x02
2945fbc2 2731#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT 0x02
45ac60c0 2732#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT_SHIFT 0x01
2945fbc2 2733#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT 0x01
45ac60c0 2734#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT_SHIFT 0x00
2945fbc2
GG		 2735
2736/* Bit definitions for GPIO_SET_DATA_OUT */
2737#define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT 0x80
45ac60c0 2738#define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT_SHIFT 0x07
2945fbc2 2739#define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT 0x40
45ac60c0 2740#define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT_SHIFT 0x06
2945fbc2 2741#define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT 0x20
45ac60c0 2742#define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT_SHIFT 0x05
2945fbc2 2743#define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT 0x10
45ac60c0 2744#define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT_SHIFT 0x04
2945fbc2 2745#define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT 0x08
45ac60c0 2746#define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT_SHIFT 0x03
2945fbc2 2747#define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT 0x04
45ac60c0 2748#define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT_SHIFT 0x02
2945fbc2 2749#define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT 0x02
45ac60c0 2750#define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT_SHIFT 0x01
2945fbc2 2751#define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT 0x01
45ac60c0 2752#define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT_SHIFT 0x00
2945fbc2
GG		 2753
2754/* Bit definitions for PU_PD_GPIO_CTRL1 */
2755#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD 0x40
45ac60c0 2756#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD_SHIFT 0x06
2945fbc2 2757#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU 0x20
45ac60c0 2758#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU_SHIFT 0x05
2945fbc2 2759#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD 0x10
45ac60c0 2760#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD_SHIFT 0x04
2945fbc2 2761#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU 0x08
45ac60c0 2762#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU_SHIFT 0x03
2945fbc2 2763#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD 0x04
45ac60c0 2764#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD_SHIFT 0x02
2945fbc2 2765#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD 0x01
45ac60c0 2766#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD_SHIFT 0x00
2945fbc2
GG		 2767
2768/* Bit definitions for PU_PD_GPIO_CTRL2 */
2769#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD 0x40
45ac60c0 2770#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD_SHIFT 0x06
2945fbc2 2771#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU 0x20
45ac60c0 2772#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU_SHIFT 0x05
2945fbc2 2773#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD 0x10
45ac60c0 2774#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD_SHIFT 0x04
2945fbc2 2775#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU 0x08
45ac60c0 2776#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU_SHIFT 0x03
2945fbc2 2777#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD 0x04
45ac60c0 2778#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD_SHIFT 0x02
2945fbc2 2779#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU 0x02
45ac60c0 2780#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU_SHIFT 0x01
2945fbc2 2781#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD 0x01
45ac60c0 2782#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD_SHIFT 0x00
2945fbc2
GG		 2783
2784/* Bit definitions for OD_OUTPUT_GPIO_CTRL */
2785#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD 0x20
45ac60c0 2786#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD_SHIFT 0x05
2945fbc2 2787#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD 0x04
45ac60c0 2788#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD_SHIFT 0x02
2945fbc2 2789#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD 0x02
45ac60c0 2790#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD_SHIFT 0x01
2945fbc2
GG		 2791
2792/* Registers for function GPADC */
45ac60c0
K		 2793#define PALMAS_GPADC_CTRL1 0x00
2794#define PALMAS_GPADC_CTRL2 0x01
2795#define PALMAS_GPADC_RT_CTRL 0x02
2796#define PALMAS_GPADC_AUTO_CTRL 0x03
2797#define PALMAS_GPADC_STATUS 0x04
2798#define PALMAS_GPADC_RT_SELECT 0x05
2799#define PALMAS_GPADC_RT_CONV0_LSB 0x06
2800#define PALMAS_GPADC_RT_CONV0_MSB 0x07
2801#define PALMAS_GPADC_AUTO_SELECT 0x08
2802#define PALMAS_GPADC_AUTO_CONV0_LSB 0x09
2803#define PALMAS_GPADC_AUTO_CONV0_MSB 0x0A
2804#define PALMAS_GPADC_AUTO_CONV1_LSB 0x0B
2805#define PALMAS_GPADC_AUTO_CONV1_MSB 0x0C
2806#define PALMAS_GPADC_SW_SELECT 0x0D
2807#define PALMAS_GPADC_SW_CONV0_LSB 0x0E
2808#define PALMAS_GPADC_SW_CONV0_MSB 0x0F
2945fbc2
GG		 2809#define PALMAS_GPADC_THRES_CONV0_LSB 0x10
2810#define PALMAS_GPADC_THRES_CONV0_MSB 0x11
2811#define PALMAS_GPADC_THRES_CONV1_LSB 0x12
2812#define PALMAS_GPADC_THRES_CONV1_MSB 0x13
2813#define PALMAS_GPADC_SMPS_ILMONITOR_EN 0x14
2814#define PALMAS_GPADC_SMPS_VSEL_MONITORING 0x15
2815
2816/* Bit definitions for GPADC_CTRL1 */
2817#define PALMAS_GPADC_CTRL1_RESERVED_MASK 0xc0
45ac60c0 2818#define PALMAS_GPADC_CTRL1_RESERVED_SHIFT 0x06
2945fbc2 2819#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_MASK 0x30
45ac60c0 2820#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_SHIFT 0x04
2945fbc2 2821#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_MASK 0x0c
45ac60c0 2822#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_SHIFT 0x02
2945fbc2 2823#define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET 0x02
45ac60c0 2824#define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET_SHIFT 0x01
2945fbc2 2825#define PALMAS_GPADC_CTRL1_GPADC_FORCE 0x01
45ac60c0 2826#define PALMAS_GPADC_CTRL1_GPADC_FORCE_SHIFT 0x00
2945fbc2
GG		 2827
2828/* Bit definitions for GPADC_CTRL2 */
2829#define PALMAS_GPADC_CTRL2_RESERVED_MASK 0x06
45ac60c0 2830#define PALMAS_GPADC_CTRL2_RESERVED_SHIFT 0x01
2945fbc2
GG		 2831
2832/* Bit definitions for GPADC_RT_CTRL */
2833#define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY 0x02
45ac60c0 2834#define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY_SHIFT 0x01
2945fbc2 2835#define PALMAS_GPADC_RT_CTRL_START_POLARITY 0x01
45ac60c0 2836#define PALMAS_GPADC_RT_CTRL_START_POLARITY_SHIFT 0x00
2945fbc2
GG		 2837
2838/* Bit definitions for GPADC_AUTO_CTRL */
2839#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1 0x80
45ac60c0 2840#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1_SHIFT 0x07
2945fbc2 2841#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0 0x40
45ac60c0 2842#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0_SHIFT 0x06
2945fbc2 2843#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN 0x20
45ac60c0 2844#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN_SHIFT 0x05
2945fbc2 2845#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN 0x10
45ac60c0
K		 2846#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN_SHIFT 0x04
2847#define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_MASK 0x0F
2848#define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_SHIFT 0x00
2945fbc2
GG		 2849
2850/* Bit definitions for GPADC_STATUS */
2851#define PALMAS_GPADC_STATUS_GPADC_AVAILABLE 0x10
45ac60c0 2852#define PALMAS_GPADC_STATUS_GPADC_AVAILABLE_SHIFT 0x04
2945fbc2
GG		 2853
2854/* Bit definitions for GPADC_RT_SELECT */
2855#define PALMAS_GPADC_RT_SELECT_RT_CONV_EN 0x80
45ac60c0
K		 2856#define PALMAS_GPADC_RT_SELECT_RT_CONV_EN_SHIFT 0x07
2857#define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_MASK 0x0F
2858#define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_SHIFT 0x00
2945fbc2
GG		 2859
2860/* Bit definitions for GPADC_RT_CONV0_LSB */
45ac60c0
K		 2861#define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_MASK 0xFF
2862#define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_SHIFT 0x00
2945fbc2
GG		 2863
2864/* Bit definitions for GPADC_RT_CONV0_MSB */
45ac60c0
K		 2865#define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_MASK 0x0F
2866#define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_SHIFT 0x00
2945fbc2
GG		 2867
2868/* Bit definitions for GPADC_AUTO_SELECT */
45ac60c0
K		 2869#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_MASK 0xF0
2870#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_SHIFT 0x04
2871#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_MASK 0x0F
2872#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_SHIFT 0x00
2945fbc2
GG		 2873
2874/* Bit definitions for GPADC_AUTO_CONV0_LSB */
45ac60c0
K		 2875#define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_MASK 0xFF
2876#define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_SHIFT 0x00
2945fbc2
GG		 2877
2878/* Bit definitions for GPADC_AUTO_CONV0_MSB */
45ac60c0
K		 2879#define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_MASK 0x0F
2880#define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_SHIFT 0x00
2945fbc2
GG		 2881
2882/* Bit definitions for GPADC_AUTO_CONV1_LSB */
45ac60c0
K		 2883#define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_MASK 0xFF
2884#define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_SHIFT 0x00
2945fbc2
GG		 2885
2886/* Bit definitions for GPADC_AUTO_CONV1_MSB */
45ac60c0
K		 2887#define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_MASK 0x0F
2888#define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_SHIFT 0x00
2945fbc2
GG		 2889
2890/* Bit definitions for GPADC_SW_SELECT */
2891#define PALMAS_GPADC_SW_SELECT_SW_CONV_EN 0x80
45ac60c0 2892#define PALMAS_GPADC_SW_SELECT_SW_CONV_EN_SHIFT 0x07
2945fbc2 2893#define PALMAS_GPADC_SW_SELECT_SW_START_CONV0 0x10
45ac60c0
K		 2894#define PALMAS_GPADC_SW_SELECT_SW_START_CONV0_SHIFT 0x04
2895#define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_MASK 0x0F
2896#define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_SHIFT 0x00
2945fbc2
GG		 2897
2898/* Bit definitions for GPADC_SW_CONV0_LSB */
45ac60c0
K		 2899#define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_MASK 0xFF
2900#define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_SHIFT 0x00
2945fbc2
GG		 2901
2902/* Bit definitions for GPADC_SW_CONV0_MSB */
45ac60c0
K		 2903#define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_MASK 0x0F
2904#define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_SHIFT 0x00
2945fbc2
GG		 2905
2906/* Bit definitions for GPADC_THRES_CONV0_LSB */
45ac60c0
K		 2907#define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_MASK 0xFF
2908#define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_SHIFT 0x00
2945fbc2
GG		 2909
2910/* Bit definitions for GPADC_THRES_CONV0_MSB */
2911#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL 0x80
45ac60c0
K		 2912#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL_SHIFT 0x07
2913#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_MASK 0x0F
2914#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_SHIFT 0x00
2945fbc2
GG		 2915
2916/* Bit definitions for GPADC_THRES_CONV1_LSB */
45ac60c0
K		 2917#define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_MASK 0xFF
2918#define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_SHIFT 0x00
2945fbc2
GG		 2919
2920/* Bit definitions for GPADC_THRES_CONV1_MSB */
2921#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL 0x80
45ac60c0
K		 2922#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL_SHIFT 0x07
2923#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_MASK 0x0F
2924#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_SHIFT 0x00
2945fbc2
GG		 2925
2926/* Bit definitions for GPADC_SMPS_ILMONITOR_EN */
2927#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN 0x20
45ac60c0 2928#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN_SHIFT 0x05
2945fbc2 2929#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT 0x10
45ac60c0
K		 2930#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT_SHIFT 0x04
2931#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_MASK 0x0F
2932#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_SHIFT 0x00
2945fbc2
GG		 2933
2934/* Bit definitions for GPADC_SMPS_VSEL_MONITORING */
2935#define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE 0x80
45ac60c0
K		 2936#define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE_SHIFT 0x07
2937#define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_MASK 0x7F
2938#define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_SHIFT 0x00
2945fbc2
GG		 2939
2940/* Registers for function GPADC */
45ac60c0
K		 2941#define PALMAS_GPADC_TRIM1 0x00
2942#define PALMAS_GPADC_TRIM2 0x01
2943#define PALMAS_GPADC_TRIM3 0x02
2944#define PALMAS_GPADC_TRIM4 0x03
2945#define PALMAS_GPADC_TRIM5 0x04
2946#define PALMAS_GPADC_TRIM6 0x05
2947#define PALMAS_GPADC_TRIM7 0x06
2948#define PALMAS_GPADC_TRIM8 0x07
2949#define PALMAS_GPADC_TRIM9 0x08
2950#define PALMAS_GPADC_TRIM10 0x09
2951#define PALMAS_GPADC_TRIM11 0x0A
2952#define PALMAS_GPADC_TRIM12 0x0B
2953#define PALMAS_GPADC_TRIM13 0x0C
2954#define PALMAS_GPADC_TRIM14 0x0D
2955#define PALMAS_GPADC_TRIM15 0x0E
2956#define PALMAS_GPADC_TRIM16 0x0F
2945fbc2 2957
027d7c2a
K		 2958/* TPS65917 Interrupt registers */
2959
2960/* Registers for function INTERRUPT */
2961#define TPS65917_INT1_STATUS 0x00
2962#define TPS65917_INT1_MASK 0x01
2963#define TPS65917_INT1_LINE_STATE 0x02
2964#define TPS65917_INT2_STATUS 0x05
2965#define TPS65917_INT2_MASK 0x06
2966#define TPS65917_INT2_LINE_STATE 0x07
2967#define TPS65917_INT3_STATUS 0x0A
2968#define TPS65917_INT3_MASK 0x0B
2969#define TPS65917_INT3_LINE_STATE 0x0C
2970#define TPS65917_INT4_STATUS 0x0F
2971#define TPS65917_INT4_MASK 0x10
2972#define TPS65917_INT4_LINE_STATE 0x11
2973#define TPS65917_INT4_EDGE_DETECT1 0x12
2974#define TPS65917_INT4_EDGE_DETECT2 0x13
2975#define TPS65917_INT_CTRL 0x14
2976
2977/* Bit definitions for INT1_STATUS */
2978#define TPS65917_INT1_STATUS_VSYS_MON 0x40
2979#define TPS65917_INT1_STATUS_VSYS_MON_SHIFT 0x06
2980#define TPS65917_INT1_STATUS_HOTDIE 0x20
2981#define TPS65917_INT1_STATUS_HOTDIE_SHIFT 0x05
2982#define TPS65917_INT1_STATUS_PWRDOWN 0x10
2983#define TPS65917_INT1_STATUS_PWRDOWN_SHIFT 0x04
2984#define TPS65917_INT1_STATUS_LONG_PRESS_KEY 0x04
2985#define TPS65917_INT1_STATUS_LONG_PRESS_KEY_SHIFT 0x02
2986#define TPS65917_INT1_STATUS_PWRON 0x02
2987#define TPS65917_INT1_STATUS_PWRON_SHIFT 0x01
2988
2989/* Bit definitions for INT1_MASK */
2990#define TPS65917_INT1_MASK_VSYS_MON 0x40
2991#define TPS65917_INT1_MASK_VSYS_MON_SHIFT 0x06
2992#define TPS65917_INT1_MASK_HOTDIE 0x20
2993#define TPS65917_INT1_MASK_HOTDIE_SHIFT 0x05
2994#define TPS65917_INT1_MASK_PWRDOWN 0x10
2995#define TPS65917_INT1_MASK_PWRDOWN_SHIFT 0x04
2996#define TPS65917_INT1_MASK_LONG_PRESS_KEY 0x04
2997#define TPS65917_INT1_MASK_LONG_PRESS_KEY_SHIFT 0x02
2998#define TPS65917_INT1_MASK_PWRON 0x02
2999#define TPS65917_INT1_MASK_PWRON_SHIFT 0x01
3000
3001/* Bit definitions for INT1_LINE_STATE */
3002#define TPS65917_INT1_LINE_STATE_VSYS_MON 0x40
3003#define TPS65917_INT1_LINE_STATE_VSYS_MON_SHIFT 0x06
3004#define TPS65917_INT1_LINE_STATE_HOTDIE 0x20
3005#define TPS65917_INT1_LINE_STATE_HOTDIE_SHIFT 0x05
3006#define TPS65917_INT1_LINE_STATE_PWRDOWN 0x10
3007#define TPS65917_INT1_LINE_STATE_PWRDOWN_SHIFT 0x04
3008#define TPS65917_INT1_LINE_STATE_LONG_PRESS_KEY 0x04
3009#define TPS65917_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT 0x02
3010#define TPS65917_INT1_LINE_STATE_PWRON 0x02
3011#define TPS65917_INT1_LINE_STATE_PWRON_SHIFT 0x01
3012
3013/* Bit definitions for INT2_STATUS */
3014#define TPS65917_INT2_STATUS_SHORT 0x40
3015#define TPS65917_INT2_STATUS_SHORT_SHIFT 0x06
3016#define TPS65917_INT2_STATUS_FSD 0x20
3017#define TPS65917_INT2_STATUS_FSD_SHIFT 0x05
3018#define TPS65917_INT2_STATUS_RESET_IN 0x10
3019#define TPS65917_INT2_STATUS_RESET_IN_SHIFT 0x04
3020#define TPS65917_INT2_STATUS_WDT 0x04
3021#define TPS65917_INT2_STATUS_WDT_SHIFT 0x02
3022#define TPS65917_INT2_STATUS_OTP_ERROR 0x02
3023#define TPS65917_INT2_STATUS_OTP_ERROR_SHIFT 0x01
3024
3025/* Bit definitions for INT2_MASK */
3026#define TPS65917_INT2_MASK_SHORT 0x40
3027#define TPS65917_INT2_MASK_SHORT_SHIFT 0x06
3028#define TPS65917_INT2_MASK_FSD 0x20
3029#define TPS65917_INT2_MASK_FSD_SHIFT 0x05
3030#define TPS65917_INT2_MASK_RESET_IN 0x10
3031#define TPS65917_INT2_MASK_RESET_IN_SHIFT 0x04
3032#define TPS65917_INT2_MASK_WDT 0x04
3033#define TPS65917_INT2_MASK_WDT_SHIFT 0x02
3034#define TPS65917_INT2_MASK_OTP_ERROR_TIMER 0x02
3035#define TPS65917_INT2_MASK_OTP_ERROR_SHIFT 0x01
3036
3037/* Bit definitions for INT2_LINE_STATE */
3038#define TPS65917_INT2_LINE_STATE_SHORT 0x40
3039#define TPS65917_INT2_LINE_STATE_SHORT_SHIFT 0x06
3040#define TPS65917_INT2_LINE_STATE_FSD 0x20
3041#define TPS65917_INT2_LINE_STATE_FSD_SHIFT 0x05
3042#define TPS65917_INT2_LINE_STATE_RESET_IN 0x10
3043#define TPS65917_INT2_LINE_STATE_RESET_IN_SHIFT 0x04
3044#define TPS65917_INT2_LINE_STATE_WDT 0x04
3045#define TPS65917_INT2_LINE_STATE_WDT_SHIFT 0x02
3046#define TPS65917_INT2_LINE_STATE_OTP_ERROR 0x02
3047#define TPS65917_INT2_LINE_STATE_OTP_ERROR_SHIFT 0x01
3048
3049/* Bit definitions for INT3_STATUS */
3050#define TPS65917_INT3_STATUS_VBUS 0x80
3051#define TPS65917_INT3_STATUS_VBUS_SHIFT 0x07
3052#define TPS65917_INT3_STATUS_GPADC_EOC_SW 0x04
3053#define TPS65917_INT3_STATUS_GPADC_EOC_SW_SHIFT 0x02
3054#define TPS65917_INT3_STATUS_GPADC_AUTO_1 0x02
3055#define TPS65917_INT3_STATUS_GPADC_AUTO_1_SHIFT 0x01
3056#define TPS65917_INT3_STATUS_GPADC_AUTO_0 0x01
3057#define TPS65917_INT3_STATUS_GPADC_AUTO_0_SHIFT 0x00
3058
3059/* Bit definitions for INT3_MASK */
3060#define TPS65917_INT3_MASK_VBUS 0x80
3061#define TPS65917_INT3_MASK_VBUS_SHIFT 0x07
3062#define TPS65917_INT3_MASK_GPADC_EOC_SW 0x04
3063#define TPS65917_INT3_MASK_GPADC_EOC_SW_SHIFT 0x02
3064#define TPS65917_INT3_MASK_GPADC_AUTO_1 0x02
3065#define TPS65917_INT3_MASK_GPADC_AUTO_1_SHIFT 0x01
3066#define TPS65917_INT3_MASK_GPADC_AUTO_0 0x01
3067#define TPS65917_INT3_MASK_GPADC_AUTO_0_SHIFT 0x00
3068
3069/* Bit definitions for INT3_LINE_STATE */
3070#define TPS65917_INT3_LINE_STATE_VBUS 0x80
3071#define TPS65917_INT3_LINE_STATE_VBUS_SHIFT 0x07
3072#define TPS65917_INT3_LINE_STATE_GPADC_EOC_SW 0x04
3073#define TPS65917_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT 0x02
3074#define TPS65917_INT3_LINE_STATE_GPADC_AUTO_1 0x02
3075#define TPS65917_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT 0x01
3076#define TPS65917_INT3_LINE_STATE_GPADC_AUTO_0 0x01
3077#define TPS65917_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT 0x00
3078
3079/* Bit definitions for INT4_STATUS */
3080#define TPS65917_INT4_STATUS_GPIO_6 0x40
3081#define TPS65917_INT4_STATUS_GPIO_6_SHIFT 0x06
3082#define TPS65917_INT4_STATUS_GPIO_5 0x20
3083#define TPS65917_INT4_STATUS_GPIO_5_SHIFT 0x05
3084#define TPS65917_INT4_STATUS_GPIO_4 0x10
3085#define TPS65917_INT4_STATUS_GPIO_4_SHIFT 0x04
3086#define TPS65917_INT4_STATUS_GPIO_3 0x08
3087#define TPS65917_INT4_STATUS_GPIO_3_SHIFT 0x03
3088#define TPS65917_INT4_STATUS_GPIO_2 0x04
3089#define TPS65917_INT4_STATUS_GPIO_2_SHIFT 0x02
3090#define TPS65917_INT4_STATUS_GPIO_1 0x02
3091#define TPS65917_INT4_STATUS_GPIO_1_SHIFT 0x01
3092#define TPS65917_INT4_STATUS_GPIO_0 0x01
3093#define TPS65917_INT4_STATUS_GPIO_0_SHIFT 0x00
3094
3095/* Bit definitions for INT4_MASK */
3096#define TPS65917_INT4_MASK_GPIO_6 0x40
3097#define TPS65917_INT4_MASK_GPIO_6_SHIFT 0x06
3098#define TPS65917_INT4_MASK_GPIO_5 0x20
3099#define TPS65917_INT4_MASK_GPIO_5_SHIFT 0x05
3100#define TPS65917_INT4_MASK_GPIO_4 0x10
3101#define TPS65917_INT4_MASK_GPIO_4_SHIFT 0x04
3102#define TPS65917_INT4_MASK_GPIO_3 0x08
3103#define TPS65917_INT4_MASK_GPIO_3_SHIFT 0x03
3104#define TPS65917_INT4_MASK_GPIO_2 0x04
3105#define TPS65917_INT4_MASK_GPIO_2_SHIFT 0x02
3106#define TPS65917_INT4_MASK_GPIO_1 0x02
3107#define TPS65917_INT4_MASK_GPIO_1_SHIFT 0x01
3108#define TPS65917_INT4_MASK_GPIO_0 0x01
3109#define TPS65917_INT4_MASK_GPIO_0_SHIFT 0x00
3110
3111/* Bit definitions for INT4_LINE_STATE */
3112#define TPS65917_INT4_LINE_STATE_GPIO_6 0x40
3113#define TPS65917_INT4_LINE_STATE_GPIO_6_SHIFT 0x06
3114#define TPS65917_INT4_LINE_STATE_GPIO_5 0x20
3115#define TPS65917_INT4_LINE_STATE_GPIO_5_SHIFT 0x05
3116#define TPS65917_INT4_LINE_STATE_GPIO_4 0x10
3117#define TPS65917_INT4_LINE_STATE_GPIO_4_SHIFT 0x04
3118#define TPS65917_INT4_LINE_STATE_GPIO_3 0x08
3119#define TPS65917_INT4_LINE_STATE_GPIO_3_SHIFT 0x03
3120#define TPS65917_INT4_LINE_STATE_GPIO_2 0x04
3121#define TPS65917_INT4_LINE_STATE_GPIO_2_SHIFT 0x02
3122#define TPS65917_INT4_LINE_STATE_GPIO_1 0x02
3123#define TPS65917_INT4_LINE_STATE_GPIO_1_SHIFT 0x01
3124#define TPS65917_INT4_LINE_STATE_GPIO_0 0x01
3125#define TPS65917_INT4_LINE_STATE_GPIO_0_SHIFT 0x00
3126
3127/* Bit definitions for INT4_EDGE_DETECT1 */
3128#define TPS65917_INT4_EDGE_DETECT1_GPIO_3_RISING 0x80
3129#define TPS65917_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT 0x07
3130#define TPS65917_INT4_EDGE_DETECT1_GPIO_3_FALLING 0x40
3131#define TPS65917_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT 0x06
3132#define TPS65917_INT4_EDGE_DETECT1_GPIO_2_RISING 0x20
3133#define TPS65917_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT 0x05
3134#define TPS65917_INT4_EDGE_DETECT1_GPIO_2_FALLING 0x10
3135#define TPS65917_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT 0x04
3136#define TPS65917_INT4_EDGE_DETECT1_GPIO_1_RISING 0x08
3137#define TPS65917_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT 0x03
3138#define TPS65917_INT4_EDGE_DETECT1_GPIO_1_FALLING 0x04
3139#define TPS65917_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT 0x02
3140#define TPS65917_INT4_EDGE_DETECT1_GPIO_0_RISING 0x02
3141#define TPS65917_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT 0x01
3142#define TPS65917_INT4_EDGE_DETECT1_GPIO_0_FALLING 0x01
3143#define TPS65917_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT 0x00
3144
3145/* Bit definitions for INT4_EDGE_DETECT2 */
3146#define TPS65917_INT4_EDGE_DETECT2_GPIO_6_RISING 0x20
3147#define TPS65917_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT 0x05
3148#define TPS65917_INT4_EDGE_DETECT2_GPIO_6_FALLING 0x10
3149#define TPS65917_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT 0x04
3150#define TPS65917_INT4_EDGE_DETECT2_GPIO_5_RISING 0x08
3151#define TPS65917_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT 0x03
3152#define TPS65917_INT4_EDGE_DETECT2_GPIO_5_FALLING 0x04
3153#define TPS65917_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT 0x02
3154#define TPS65917_INT4_EDGE_DETECT2_GPIO_4_RISING 0x02
3155#define TPS65917_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT 0x01
3156#define TPS65917_INT4_EDGE_DETECT2_GPIO_4_FALLING 0x01
3157#define TPS65917_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT 0x00
3158
3159/* Bit definitions for INT_CTRL */
3160#define TPS65917_INT_CTRL_INT_PENDING 0x04
3161#define TPS65917_INT_CTRL_INT_PENDING_SHIFT 0x02
3162#define TPS65917_INT_CTRL_INT_CLEAR 0x01
3163#define TPS65917_INT_CTRL_INT_CLEAR_SHIFT 0x00
3164
3165/* TPS65917 SMPS Registers */
3166
3167/* Registers for function SMPS */
3168#define TPS65917_SMPS1_CTRL 0x00
3169#define TPS65917_SMPS1_FORCE 0x02
3170#define TPS65917_SMPS1_VOLTAGE 0x03
3171#define TPS65917_SMPS2_CTRL 0x04
3172#define TPS65917_SMPS2_FORCE 0x06
3173#define TPS65917_SMPS2_VOLTAGE 0x07
3174#define TPS65917_SMPS3_CTRL 0x0C
3175#define TPS65917_SMPS3_FORCE 0x0E
3176#define TPS65917_SMPS3_VOLTAGE 0x0F
3177#define TPS65917_SMPS4_CTRL 0x10
3178#define TPS65917_SMPS4_VOLTAGE 0x13
3179#define TPS65917_SMPS5_CTRL 0x18
3180#define TPS65917_SMPS5_VOLTAGE 0x1B
3181#define TPS65917_SMPS_CTRL 0x24
3182#define TPS65917_SMPS_PD_CTRL 0x25
3183#define TPS65917_SMPS_THERMAL_EN 0x27
3184#define TPS65917_SMPS_THERMAL_STATUS 0x28
3185#define TPS65917_SMPS_SHORT_STATUS 0x29
3186#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN 0x2A
3187#define TPS65917_SMPS_POWERGOOD_MASK1 0x2B
3188#define TPS65917_SMPS_POWERGOOD_MASK2 0x2C
3189
3190/* Bit definitions for SMPS1_CTRL */
3191#define TPS65917_SMPS1_CTRL_WR_S 0x80
3192#define TPS65917_SMPS1_CTRL_WR_S_SHIFT 0x07
3193#define TPS65917_SMPS1_CTRL_ROOF_FLOOR_EN 0x40
3194#define TPS65917_SMPS1_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
3195#define TPS65917_SMPS1_CTRL_STATUS_MASK 0x30
3196#define TPS65917_SMPS1_CTRL_STATUS_SHIFT 0x04
3197#define TPS65917_SMPS1_CTRL_MODE_SLEEP_MASK 0x0C
3198#define TPS65917_SMPS1_CTRL_MODE_SLEEP_SHIFT 0x02
3199#define TPS65917_SMPS1_CTRL_MODE_ACTIVE_MASK 0x03
3200#define TPS65917_SMPS1_CTRL_MODE_ACTIVE_SHIFT 0x00
3201
3202/* Bit definitions for SMPS1_FORCE */
3203#define TPS65917_SMPS1_FORCE_CMD 0x80
3204#define TPS65917_SMPS1_FORCE_CMD_SHIFT 0x07
3205#define TPS65917_SMPS1_FORCE_VSEL_MASK 0x7F
3206#define TPS65917_SMPS1_FORCE_VSEL_SHIFT 0x00
3207
3208/* Bit definitions for SMPS1_VOLTAGE */
3209#define TPS65917_SMPS1_VOLTAGE_RANGE 0x80
3210#define TPS65917_SMPS1_VOLTAGE_RANGE_SHIFT 0x07
3211#define TPS65917_SMPS1_VOLTAGE_VSEL_MASK 0x7F
3212#define TPS65917_SMPS1_VOLTAGE_VSEL_SHIFT 0x00
3213
3214/* Bit definitions for SMPS2_CTRL */
3215#define TPS65917_SMPS2_CTRL_WR_S 0x80
3216#define TPS65917_SMPS2_CTRL_WR_S_SHIFT 0x07
3217#define TPS65917_SMPS2_CTRL_ROOF_FLOOR_EN 0x40
3218#define TPS65917_SMPS2_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
3219#define TPS65917_SMPS2_CTRL_STATUS_MASK 0x30
3220#define TPS65917_SMPS2_CTRL_STATUS_SHIFT 0x04
3221#define TPS65917_SMPS2_CTRL_MODE_SLEEP_MASK 0x0C
3222#define TPS65917_SMPS2_CTRL_MODE_SLEEP_SHIFT 0x02
3223#define TPS65917_SMPS2_CTRL_MODE_ACTIVE_MASK 0x03
3224#define TPS65917_SMPS2_CTRL_MODE_ACTIVE_SHIFT 0x00
3225
3226/* Bit definitions for SMPS2_FORCE */
3227#define TPS65917_SMPS2_FORCE_CMD 0x80
3228#define TPS65917_SMPS2_FORCE_CMD_SHIFT 0x07
3229#define TPS65917_SMPS2_FORCE_VSEL_MASK 0x7F
3230#define TPS65917_SMPS2_FORCE_VSEL_SHIFT 0x00
3231
3232/* Bit definitions for SMPS2_VOLTAGE */
3233#define TPS65917_SMPS2_VOLTAGE_RANGE 0x80
3234#define TPS65917_SMPS2_VOLTAGE_RANGE_SHIFT 0x07
3235#define TPS65917_SMPS2_VOLTAGE_VSEL_MASK 0x7F
3236#define TPS65917_SMPS2_VOLTAGE_VSEL_SHIFT 0x00
3237
3238/* Bit definitions for SMPS3_CTRL */
3239#define TPS65917_SMPS3_CTRL_WR_S 0x80
3240#define TPS65917_SMPS3_CTRL_WR_S_SHIFT 0x07
3241#define TPS65917_SMPS3_CTRL_ROOF_FLOOR_EN 0x40
3242#define TPS65917_SMPS3_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
3243#define TPS65917_SMPS3_CTRL_STATUS_MASK 0x30
3244#define TPS65917_SMPS3_CTRL_STATUS_SHIFT 0x04
3245#define TPS65917_SMPS3_CTRL_MODE_SLEEP_MASK 0x0C
3246#define TPS65917_SMPS3_CTRL_MODE_SLEEP_SHIFT 0x02
3247#define TPS65917_SMPS3_CTRL_MODE_ACTIVE_MASK 0x03
3248#define TPS65917_SMPS3_CTRL_MODE_ACTIVE_SHIFT 0x00
3249
3250/* Bit definitions for SMPS3_FORCE */
3251#define TPS65917_SMPS3_FORCE_CMD 0x80
3252#define TPS65917_SMPS3_FORCE_CMD_SHIFT 0x07
3253#define TPS65917_SMPS3_FORCE_VSEL_MASK 0x7F
3254#define TPS65917_SMPS3_FORCE_VSEL_SHIFT 0x00
3255
3256/* Bit definitions for SMPS3_VOLTAGE */
3257#define TPS65917_SMPS3_VOLTAGE_RANGE 0x80
3258#define TPS65917_SMPS3_VOLTAGE_RANGE_SHIFT 0x07
3259#define TPS65917_SMPS3_VOLTAGE_VSEL_MASK 0x7F
3260#define TPS65917_SMPS3_VOLTAGE_VSEL_SHIFT 0x00
3261
3262/* Bit definitions for SMPS4_CTRL */
3263#define TPS65917_SMPS4_CTRL_WR_S 0x80
3264#define TPS65917_SMPS4_CTRL_WR_S_SHIFT 0x07
3265#define TPS65917_SMPS4_CTRL_ROOF_FLOOR_EN 0x40
3266#define TPS65917_SMPS4_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
3267#define TPS65917_SMPS4_CTRL_STATUS_MASK 0x30
3268#define TPS65917_SMPS4_CTRL_STATUS_SHIFT 0x04
3269#define TPS65917_SMPS4_CTRL_MODE_SLEEP_MASK 0x0C
3270#define TPS65917_SMPS4_CTRL_MODE_SLEEP_SHIFT 0x02
3271#define TPS65917_SMPS4_CTRL_MODE_ACTIVE_MASK 0x03
3272#define TPS65917_SMPS4_CTRL_MODE_ACTIVE_SHIFT 0x00
3273
3274/* Bit definitions for SMPS4_VOLTAGE */
3275#define TPS65917_SMPS4_VOLTAGE_RANGE 0x80
3276#define TPS65917_SMPS4_VOLTAGE_RANGE_SHIFT 0x07
3277#define TPS65917_SMPS4_VOLTAGE_VSEL_MASK 0x7F
3278#define TPS65917_SMPS4_VOLTAGE_VSEL_SHIFT 0x00
3279
3280/* Bit definitions for SMPS5_CTRL */
3281#define TPS65917_SMPS5_CTRL_WR_S 0x80
3282#define TPS65917_SMPS5_CTRL_WR_S_SHIFT 0x07
3283#define TPS65917_SMPS5_CTRL_ROOF_FLOOR_EN 0x40
3284#define TPS65917_SMPS5_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
3285#define TPS65917_SMPS5_CTRL_STATUS_MASK 0x30
3286#define TPS65917_SMPS5_CTRL_STATUS_SHIFT 0x04
3287#define TPS65917_SMPS5_CTRL_MODE_SLEEP_MASK 0x0C
3288#define TPS65917_SMPS5_CTRL_MODE_SLEEP_SHIFT 0x02
3289#define TPS65917_SMPS5_CTRL_MODE_ACTIVE_MASK 0x03
3290#define TPS65917_SMPS5_CTRL_MODE_ACTIVE_SHIFT 0x00
3291
3292/* Bit definitions for SMPS5_VOLTAGE */
3293#define TPS65917_SMPS5_VOLTAGE_RANGE 0x80
3294#define TPS65917_SMPS5_VOLTAGE_RANGE_SHIFT 0x07
3295#define TPS65917_SMPS5_VOLTAGE_VSEL_MASK 0x7F
3296#define TPS65917_SMPS5_VOLTAGE_VSEL_SHIFT 0x00
3297
3298/* Bit definitions for SMPS_CTRL */
3299#define TPS65917_SMPS_CTRL_SMPS1_SMPS12_EN 0x10
3300#define TPS65917_SMPS_CTRL_SMPS1_SMPS12_EN_SHIFT 0x04
3301#define TPS65917_SMPS_CTRL_SMPS12_PHASE_CTRL 0x03
3302#define TPS65917_SMPS_CTRL_SMPS12_PHASE_CTRL_SHIFT 0x00
3303
3304/* Bit definitions for SMPS_PD_CTRL */
3305#define TPS65917_SMPS_PD_CTRL_SMPS5 0x40
3306#define TPS65917_SMPS_PD_CTRL_SMPS5_SHIFT 0x06
3307#define TPS65917_SMPS_PD_CTRL_SMPS4 0x10
3308#define TPS65917_SMPS_PD_CTRL_SMPS4_SHIFT 0x04
3309#define TPS65917_SMPS_PD_CTRL_SMPS3 0x08
3310#define TPS65917_SMPS_PD_CTRL_SMPS3_SHIFT 0x03
3311#define TPS65917_SMPS_PD_CTRL_SMPS2 0x02
3312#define TPS65917_SMPS_PD_CTRL_SMPS2_SHIFT 0x01
3313#define TPS65917_SMPS_PD_CTRL_SMPS1 0x01
3314#define TPS65917_SMPS_PD_CTRL_SMPS1_SHIFT 0x00
3315
3316/* Bit definitions for SMPS_THERMAL_EN */
3317#define TPS65917_SMPS_THERMAL_EN_SMPS5 0x40
3318#define TPS65917_SMPS_THERMAL_EN_SMPS5_SHIFT 0x06
3319#define TPS65917_SMPS_THERMAL_EN_SMPS3 0x08
3320#define TPS65917_SMPS_THERMAL_EN_SMPS3_SHIFT 0x03
3321#define TPS65917_SMPS_THERMAL_EN_SMPS12 0x01
3322#define TPS65917_SMPS_THERMAL_EN_SMPS12_SHIFT 0x00
3323
3324/* Bit definitions for SMPS_THERMAL_STATUS */
3325#define TPS65917_SMPS_THERMAL_STATUS_SMPS5 0x40
3326#define TPS65917_SMPS_THERMAL_STATUS_SMPS5_SHIFT 0x06
3327#define TPS65917_SMPS_THERMAL_STATUS_SMPS3 0x08
3328#define TPS65917_SMPS_THERMAL_STATUS_SMPS3_SHIFT 0x03
3329#define TPS65917_SMPS_THERMAL_STATUS_SMPS12 0x01
3330#define TPS65917_SMPS_THERMAL_STATUS_SMPS12_SHIFT 0x00
3331
3332/* Bit definitions for SMPS_SHORT_STATUS */
3333#define TPS65917_SMPS_SHORT_STATUS_SMPS5 0x40
3334#define TPS65917_SMPS_SHORT_STATUS_SMPS5_SHIFT 0x06
3335#define TPS65917_SMPS_SHORT_STATUS_SMPS4 0x10
3336#define TPS65917_SMPS_SHORT_STATUS_SMPS4_SHIFT 0x04
3337#define TPS65917_SMPS_SHORT_STATUS_SMPS3 0x08
3338#define TPS65917_SMPS_SHORT_STATUS_SMPS3_SHIFT 0x03
3339#define TPS65917_SMPS_SHORT_STATUS_SMPS2 0x02
3340#define TPS65917_SMPS_SHORT_STATUS_SMPS2_SHIFT 0x01
3341#define TPS65917_SMPS_SHORT_STATUS_SMPS1 0x01
3342#define TPS65917_SMPS_SHORT_STATUS_SMPS1_SHIFT 0x00
3343
3344/* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */
3345#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS5 0x40
3346#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS5_SHIFT 0x06
3347#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS4 0x10
3348#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS4_SHIFT 0x04
3349#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3 0x08
3350#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT 0x03
3351#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS2 0x02
3352#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS2_SHIFT 0x01
3353#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS1 0x01
3354#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS1_SHIFT 0x00
3355
3356/* Bit definitions for SMPS_POWERGOOD_MASK1 */
3357#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS5 0x40
3358#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS5_SHIFT 0x06
3359#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS4 0x10
3360#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS4_SHIFT 0x04
3361#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS3 0x08
3362#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT 0x03
3363#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS2 0x02
3364#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS2_SHIFT 0x01
3365#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS1 0x01
3366#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS1_SHIFT 0x00
3367
3368/* Bit definitions for SMPS_POWERGOOD_MASK2 */
3369#define TPS65917_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT 0x80
3370#define TPS65917_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 0x07
3371#define TPS65917_SMPS_POWERGOOD_MASK2_OVC_ALARM_SHIFT 0x10
3372#define TPS65917_SMPS_POWERGOOD_MASK2_OVC_ALARM 0x04
3373
3374/* Bit definitions for SMPS_PLL_CTRL */
3375
3376#define TPS65917_SMPS_PLL_CTRL_PLL_EN_PLL_BYPASS_SHIFT 0x08
3377#define TPS65917_SMPS_PLL_CTRL_PLL_PLL_EN_BYPASS 0x03
3378#define TPS65917_SMPS_PLL_CTRL_PLL_PLL_BYPASS_CLK_SHIFT 0x04
3379#define TPS65917_SMPS_PLL_CTRL_PLL_PLL_BYPASS_CLK 0x02
3380
3381/* Registers for function LDO */
3382#define TPS65917_LDO1_CTRL 0x00
3383#define TPS65917_LDO1_VOLTAGE 0x01
3384#define TPS65917_LDO2_CTRL 0x02
3385#define TPS65917_LDO2_VOLTAGE 0x03
3386#define TPS65917_LDO3_CTRL 0x04
3387#define TPS65917_LDO3_VOLTAGE 0x05
3388#define TPS65917_LDO4_CTRL 0x0E
3389#define TPS65917_LDO4_VOLTAGE 0x0F
3390#define TPS65917_LDO5_CTRL 0x12
3391#define TPS65917_LDO5_VOLTAGE 0x13
3392#define TPS65917_LDO_PD_CTRL1 0x1B
3393#define TPS65917_LDO_PD_CTRL2 0x1C
3394#define TPS65917_LDO_SHORT_STATUS1 0x1D
3395#define TPS65917_LDO_SHORT_STATUS2 0x1E
3396#define TPS65917_LDO_PD_CTRL3 0x2D
3397#define TPS65917_LDO_SHORT_STATUS3 0x2E
3398
3399/* Bit definitions for LDO1_CTRL */
3400#define TPS65917_LDO1_CTRL_WR_S 0x80
3401#define TPS65917_LDO1_CTRL_WR_S_SHIFT 0x07
3402#define TPS65917_LDO1_CTRL_BYPASS_EN 0x40
3403#define TPS65917_LDO1_CTRL_BYPASS_EN_SHIFT 0x06
3404#define TPS65917_LDO1_CTRL_STATUS 0x10
3405#define TPS65917_LDO1_CTRL_STATUS_SHIFT 0x04
3406#define TPS65917_LDO1_CTRL_MODE_SLEEP 0x04
3407#define TPS65917_LDO1_CTRL_MODE_SLEEP_SHIFT 0x02
3408#define TPS65917_LDO1_CTRL_MODE_ACTIVE 0x01
3409#define TPS65917_LDO1_CTRL_MODE_ACTIVE_SHIFT 0x00
3410
3411/* Bit definitions for LDO1_VOLTAGE */
3412#define TPS65917_LDO1_VOLTAGE_VSEL_MASK 0x2F
3413#define TPS65917_LDO1_VOLTAGE_VSEL_SHIFT 0x00
3414
3415/* Bit definitions for LDO2_CTRL */
3416#define TPS65917_LDO2_CTRL_WR_S 0x80
3417#define TPS65917_LDO2_CTRL_WR_S_SHIFT 0x07
3418#define TPS65917_LDO2_CTRL_BYPASS_EN 0x40
3419#define TPS65917_LDO2_CTRL_BYPASS_EN_SHIFT 0x06
3420#define TPS65917_LDO2_CTRL_STATUS 0x10
3421#define TPS65917_LDO2_CTRL_STATUS_SHIFT 0x04
3422#define TPS65917_LDO2_CTRL_MODE_SLEEP 0x04
3423#define TPS65917_LDO2_CTRL_MODE_SLEEP_SHIFT 0x02
3424#define TPS65917_LDO2_CTRL_MODE_ACTIVE 0x01
3425#define TPS65917_LDO2_CTRL_MODE_ACTIVE_SHIFT 0x00
3426
3427/* Bit definitions for LDO2_VOLTAGE */
3428#define TPS65917_LDO2_VOLTAGE_VSEL_MASK 0x2F
3429#define TPS65917_LDO2_VOLTAGE_VSEL_SHIFT 0x00
3430
3431/* Bit definitions for LDO3_CTRL */
3432#define TPS65917_LDO3_CTRL_WR_S 0x80
3433#define TPS65917_LDO3_CTRL_WR_S_SHIFT 0x07
3434#define TPS65917_LDO3_CTRL_STATUS 0x10
3435#define TPS65917_LDO3_CTRL_STATUS_SHIFT 0x04
3436#define TPS65917_LDO3_CTRL_MODE_SLEEP 0x04
3437#define TPS65917_LDO3_CTRL_MODE_SLEEP_SHIFT 0x02
3438#define TPS65917_LDO3_CTRL_MODE_ACTIVE 0x01
3439#define TPS65917_LDO3_CTRL_MODE_ACTIVE_SHIFT 0x00
3440
3441/* Bit definitions for LDO3_VOLTAGE */
3442#define TPS65917_LDO3_VOLTAGE_VSEL_MASK 0x2F
3443#define TPS65917_LDO3_VOLTAGE_VSEL_SHIFT 0x00
3444
3445/* Bit definitions for LDO4_CTRL */
3446#define TPS65917_LDO4_CTRL_WR_S 0x80
3447#define TPS65917_LDO4_CTRL_WR_S_SHIFT 0x07
3448#define TPS65917_LDO4_CTRL_STATUS 0x10
3449#define TPS65917_LDO4_CTRL_STATUS_SHIFT 0x04
3450#define TPS65917_LDO4_CTRL_MODE_SLEEP 0x04
3451#define TPS65917_LDO4_CTRL_MODE_SLEEP_SHIFT 0x02
3452#define TPS65917_LDO4_CTRL_MODE_ACTIVE 0x01
3453#define TPS65917_LDO4_CTRL_MODE_ACTIVE_SHIFT 0x00
3454
3455/* Bit definitions for LDO4_VOLTAGE */
3456#define TPS65917_LDO4_VOLTAGE_VSEL_MASK 0x2F
3457#define TPS65917_LDO4_VOLTAGE_VSEL_SHIFT 0x00
3458
3459/* Bit definitions for LDO5_CTRL */
3460#define TPS65917_LDO5_CTRL_WR_S 0x80
3461#define TPS65917_LDO5_CTRL_WR_S_SHIFT 0x07
3462#define TPS65917_LDO5_CTRL_STATUS 0x10
3463#define TPS65917_LDO5_CTRL_STATUS_SHIFT 0x04
3464#define TPS65917_LDO5_CTRL_MODE_SLEEP 0x04
3465#define TPS65917_LDO5_CTRL_MODE_SLEEP_SHIFT 0x02
3466#define TPS65917_LDO5_CTRL_MODE_ACTIVE 0x01
3467#define TPS65917_LDO5_CTRL_MODE_ACTIVE_SHIFT 0x00
3468
3469/* Bit definitions for LDO5_VOLTAGE */
3470#define TPS65917_LDO5_VOLTAGE_VSEL_MASK 0x2F
3471#define TPS65917_LDO5_VOLTAGE_VSEL_SHIFT 0x00
3472
3473/* Bit definitions for LDO_PD_CTRL1 */
3474#define TPS65917_LDO_PD_CTRL1_LDO4 0x80
3475#define TPS65917_LDO_PD_CTRL1_LDO4_SHIFT 0x07
3476#define TPS65917_LDO_PD_CTRL1_LDO2 0x02
3477#define TPS65917_LDO_PD_CTRL1_LDO2_SHIFT 0x01
3478#define TPS65917_LDO_PD_CTRL1_LDO1 0x01
3479#define TPS65917_LDO_PD_CTRL1_LDO1_SHIFT 0x00
3480
3481/* Bit definitions for LDO_PD_CTRL2 */
3482#define TPS65917_LDO_PD_CTRL2_LDO3 0x04
3483#define TPS65917_LDO_PD_CTRL2_LDO3_SHIFT 0x02
3484#define TPS65917_LDO_PD_CTRL2_LDO5 0x02
3485#define TPS65917_LDO_PD_CTRL2_LDO5_SHIFT 0x01
3486
3487/* Bit definitions for LDO_PD_CTRL3 */
3488#define TPS65917_LDO_PD_CTRL2_LDOVANA 0x80
3489#define TPS65917_LDO_PD_CTRL2_LDOVANA_SHIFT 0x07
3490
3491/* Bit definitions for LDO_SHORT_STATUS1 */
3492#define TPS65917_LDO_SHORT_STATUS1_LDO4 0x80
3493#define TPS65917_LDO_SHORT_STATUS1_LDO4_SHIFT 0x07
3494#define TPS65917_LDO_SHORT_STATUS1_LDO2 0x02
3495#define TPS65917_LDO_SHORT_STATUS1_LDO2_SHIFT 0x01
3496#define TPS65917_LDO_SHORT_STATUS1_LDO1 0x01
3497#define TPS65917_LDO_SHORT_STATUS1_LDO1_SHIFT 0x00
3498
3499/* Bit definitions for LDO_SHORT_STATUS2 */
3500#define TPS65917_LDO_SHORT_STATUS2_LDO3 0x04
3501#define TPS65917_LDO_SHORT_STATUS2_LDO3_SHIFT 0x02
3502#define TPS65917_LDO_SHORT_STATUS2_LDO5 0x02
3503#define TPS65917_LDO_SHORT_STATUS2_LDO5_SHIFT 0x01
3504
3505/* Bit definitions for LDO_SHORT_STATUS2 */
3506#define TPS65917_LDO_SHORT_STATUS2_LDOVANA 0x80
3507#define TPS65917_LDO_SHORT_STATUS2_LDOVANA_SHIFT 0x07
3508
3509/* Bit definitions for REGEN1_CTRL */
3510#define TPS65917_REGEN1_CTRL_STATUS 0x10
3511#define TPS65917_REGEN1_CTRL_STATUS_SHIFT 0x04
3512#define TPS65917_REGEN1_CTRL_MODE_SLEEP 0x04
3513#define TPS65917_REGEN1_CTRL_MODE_SLEEP_SHIFT 0x02
3514#define TPS65917_REGEN1_CTRL_MODE_ACTIVE 0x01
3515#define TPS65917_REGEN1_CTRL_MODE_ACTIVE_SHIFT 0x00
3516
3517/* Bit definitions for PLLEN_CTRL */
3518#define TPS65917_PLLEN_CTRL_STATUS 0x10
3519#define TPS65917_PLLEN_CTRL_STATUS_SHIFT 0x04
3520#define TPS65917_PLLEN_CTRL_MODE_SLEEP 0x04
3521#define TPS65917_PLLEN_CTRL_MODE_SLEEP_SHIFT 0x02
3522#define TPS65917_PLLEN_CTRL_MODE_ACTIVE 0x01
3523#define TPS65917_PLLEN_CTRL_MODE_ACTIVE_SHIFT 0x00
3524
3525/* Bit definitions for REGEN2_CTRL */
3526#define TPS65917_REGEN2_CTRL_STATUS 0x10
3527#define TPS65917_REGEN2_CTRL_STATUS_SHIFT 0x04
3528#define TPS65917_REGEN2_CTRL_MODE_SLEEP 0x04
3529#define TPS65917_REGEN2_CTRL_MODE_SLEEP_SHIFT 0x02
3530#define TPS65917_REGEN2_CTRL_MODE_ACTIVE 0x01
3531#define TPS65917_REGEN2_CTRL_MODE_ACTIVE_SHIFT 0x00
3532
3533/* Bit definitions for NSLEEP_RES_ASSIGN */
3534#define TPS65917_NSLEEP_RES_ASSIGN_PLL_EN 0x08
3535#define TPS65917_NSLEEP_RES_ASSIGN_PLL_EN_SHIFT 0x03
3536#define TPS65917_NSLEEP_RES_ASSIGN_REGEN3 0x04
3537#define TPS65917_NSLEEP_RES_ASSIGN_REGEN3_SHIFT 0x02
3538#define TPS65917_NSLEEP_RES_ASSIGN_REGEN2 0x02
3539#define TPS65917_NSLEEP_RES_ASSIGN_REGEN2_SHIFT 0x01
3540#define TPS65917_NSLEEP_RES_ASSIGN_REGEN1 0x01
3541#define TPS65917_NSLEEP_RES_ASSIGN_REGEN1_SHIFT 0x00
3542
3543/* Bit definitions for NSLEEP_SMPS_ASSIGN */
3544#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS5 0x40
3545#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS5_SHIFT 0x06
3546#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS4 0x10
3547#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS4_SHIFT 0x04
3548#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS3 0x08
3549#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT 0x03
3550#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS2 0x02
3551#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS2_SHIFT 0x01
3552#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS1 0x01
3553#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS1_SHIFT 0x00
3554
3555/* Bit definitions for NSLEEP_LDO_ASSIGN1 */
3556#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO4 0x80
3557#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT 0x07
3558#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO2 0x02
3559#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT 0x01
3560#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO1 0x01
3561#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT 0x00
3562
3563/* Bit definitions for NSLEEP_LDO_ASSIGN2 */
3564#define TPS65917_NSLEEP_LDO_ASSIGN2_LDO3 0x04
3565#define TPS65917_NSLEEP_LDO_ASSIGN2_LDO3_SHIFT 0x02
3566#define TPS65917_NSLEEP_LDO_ASSIGN2_LDO5 0x02
3567#define TPS65917_NSLEEP_LDO_ASSIGN2_LDO5_SHIFT 0x01
3568
3569/* Bit definitions for ENABLE1_RES_ASSIGN */
3570#define TPS65917_ENABLE1_RES_ASSIGN_PLLEN 0x08
3571#define TPS65917_ENABLE1_RES_ASSIGN_PLLEN_SHIFT 0x03
3572#define TPS65917_ENABLE1_RES_ASSIGN_REGEN3 0x04
3573#define TPS65917_ENABLE1_RES_ASSIGN_REGEN3_SHIFT 0x02
3574#define TPS65917_ENABLE1_RES_ASSIGN_REGEN2 0x02
3575#define TPS65917_ENABLE1_RES_ASSIGN_REGEN2_SHIFT 0x01
3576#define TPS65917_ENABLE1_RES_ASSIGN_REGEN1 0x01
3577#define TPS65917_ENABLE1_RES_ASSIGN_REGEN1_SHIFT 0x00
3578
3579/* Bit definitions for ENABLE1_SMPS_ASSIGN */
3580#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS5 0x40
3581#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS5_SHIFT 0x06
3582#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS4 0x10
3583#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS4_SHIFT 0x04
3584#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS3 0x08
3585#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT 0x03
3586#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS2 0x02
3587#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS2_SHIFT 0x01
3588#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS1 0x01
3589#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS1_SHIFT 0x00
3590
3591/* Bit definitions for ENABLE1_LDO_ASSIGN1 */
3592#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO4 0x80
3593#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT 0x07
3594#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO2 0x02
3595#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT 0x01
3596#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO1 0x01
3597#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT 0x00
3598
3599/* Bit definitions for ENABLE1_LDO_ASSIGN2 */
3600#define TPS65917_ENABLE1_LDO_ASSIGN2_LDO3 0x04
3601#define TPS65917_ENABLE1_LDO_ASSIGN2_LDO3_SHIFT 0x02
3602#define TPS65917_ENABLE1_LDO_ASSIGN2_LDO5 0x02
3603#define TPS65917_ENABLE1_LDO_ASSIGN2_LDO5_SHIFT 0x01
3604
3605/* Bit definitions for ENABLE2_RES_ASSIGN */
3606#define TPS65917_ENABLE2_RES_ASSIGN_PLLEN 0x08
3607#define TPS65917_ENABLE2_RES_ASSIGN_PLLEN_SHIFT 0x03
3608#define TPS65917_ENABLE2_RES_ASSIGN_REGEN3 0x04
3609#define TPS65917_ENABLE2_RES_ASSIGN_REGEN3_SHIFT 0x02
3610#define TPS65917_ENABLE2_RES_ASSIGN_REGEN2 0x02
3611#define TPS65917_ENABLE2_RES_ASSIGN_REGEN2_SHIFT 0x01
3612#define TPS65917_ENABLE2_RES_ASSIGN_REGEN1 0x01
3613#define TPS65917_ENABLE2_RES_ASSIGN_REGEN1_SHIFT 0x00
3614
3615/* Bit definitions for ENABLE2_SMPS_ASSIGN */
3616#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS5 0x40
3617#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS5_SHIFT 0x06
3618#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS4 0x10
3619#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS4_SHIFT 0x04
3620#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS3 0x08
3621#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT 0x03
3622#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS2 0x02
3623#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS2_SHIFT 0x01
3624#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS1 0x01
3625#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS1_SHIFT 0x00
3626
3627/* Bit definitions for ENABLE2_LDO_ASSIGN1 */
3628#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO4 0x80
3629#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT 0x07
3630#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO2 0x02
3631#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT 0x01
3632#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO1 0x01
3633#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT 0x00
3634
3635/* Bit definitions for ENABLE2_LDO_ASSIGN2 */
3636#define TPS65917_ENABLE2_LDO_ASSIGN2_LDO3 0x04
3637#define TPS65917_ENABLE2_LDO_ASSIGN2_LDO3_SHIFT 0x02
3638#define TPS65917_ENABLE2_LDO_ASSIGN2_LDO5 0x02
3639#define TPS65917_ENABLE2_LDO_ASSIGN2_LDO5_SHIFT 0x01
3640
3641/* Bit definitions for REGEN3_CTRL */
3642#define TPS65917_REGEN3_CTRL_STATUS 0x10
3643#define TPS65917_REGEN3_CTRL_STATUS_SHIFT 0x04
3644#define TPS65917_REGEN3_CTRL_MODE_SLEEP 0x04
3645#define TPS65917_REGEN3_CTRL_MODE_SLEEP_SHIFT 0x02
3646#define TPS65917_REGEN3_CTRL_MODE_ACTIVE 0x01
3647#define TPS65917_REGEN3_CTRL_MODE_ACTIVE_SHIFT 0x00
3648
3649/* Registers for function RESOURCE */
3650#define TPS65917_REGEN1_CTRL 0x2
3651#define TPS65917_PLLEN_CTRL 0x3
3652#define TPS65917_NSLEEP_RES_ASSIGN 0x6
3653#define TPS65917_NSLEEP_SMPS_ASSIGN 0x7
3654#define TPS65917_NSLEEP_LDO_ASSIGN1 0x8
3655#define TPS65917_NSLEEP_LDO_ASSIGN2 0x9
3656#define TPS65917_ENABLE1_RES_ASSIGN 0xA
3657#define TPS65917_ENABLE1_SMPS_ASSIGN 0xB
3658#define TPS65917_ENABLE1_LDO_ASSIGN1 0xC
3659#define TPS65917_ENABLE1_LDO_ASSIGN2 0xD
3660#define TPS65917_ENABLE2_RES_ASSIGN 0xE
3661#define TPS65917_ENABLE2_SMPS_ASSIGN 0xF
3662#define TPS65917_ENABLE2_LDO_ASSIGN1 0x10
3663#define TPS65917_ENABLE2_LDO_ASSIGN2 0x11
3664#define TPS65917_REGEN2_CTRL 0x12
3665#define TPS65917_REGEN3_CTRL 0x13
3666
60c185f0
LD		 3667static inline int palmas_read(struct palmas *palmas, unsigned int base,
3668 unsigned int reg, unsigned int *val)
3669{
45ac60c0 3670 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
60c185f0
LD		 3671 int slave_id = PALMAS_BASE_TO_SLAVE(base);
3672
3673 return regmap_read(palmas->regmap[slave_id], addr, val);
3674}
3675
3676static inline int palmas_write(struct palmas *palmas, unsigned int base,
3677 unsigned int reg, unsigned int value)
3678{
3679 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
3680 int slave_id = PALMAS_BASE_TO_SLAVE(base);
3681
3682 return regmap_write(palmas->regmap[slave_id], addr, value);
3683}
3684
3685static inline int palmas_bulk_write(struct palmas *palmas, unsigned int base,
3686 unsigned int reg, const void *val, size_t val_count)
3687{
3688 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
3689 int slave_id = PALMAS_BASE_TO_SLAVE(base);
3690
3691 return regmap_bulk_write(palmas->regmap[slave_id], addr,
3692 val, val_count);
3693}
3694
3695static inline int palmas_bulk_read(struct palmas *palmas, unsigned int base,
3696 unsigned int reg, void *val, size_t val_count)
3697{
3698 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
3699 int slave_id = PALMAS_BASE_TO_SLAVE(base);
3700
3701 return regmap_bulk_read(palmas->regmap[slave_id], addr,
3702 val, val_count);
3703}
3704
3705static inline int palmas_update_bits(struct palmas *palmas, unsigned int base,
3706 unsigned int reg, unsigned int mask, unsigned int val)
3707{
3708 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
3709 int slave_id = PALMAS_BASE_TO_SLAVE(base);
3710
3711 return regmap_update_bits(palmas->regmap[slave_id], addr, mask, val);
3712}
3713
3714static inline int palmas_irq_get_virq(struct palmas *palmas, int irq)
3715{
3716 return regmap_irq_get_virq(palmas->irq_data, irq);
3717}
3718
cc01b463
LD		 3719
3720int palmas_ext_control_req_config(struct palmas *palmas,
3721 enum palmas_external_requestor_id ext_control_req_id,
3722 int ext_ctrl, bool enable);
3723
2945fbc2 3724#endif /* __LINUX_MFD_PALMAS_H */
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