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mfd: palmas: shift the palmas_sleep_requestor_info structure definition to the header...
[mirror_ubuntu-bionic-kernel.git] / include / linux / mfd / palmas.h
CommitLineData
2945fbc2
GG		 1/*
2 * TI Palmas
3 *
654003e9 4 * Copyright 2011-2013 Texas Instruments Inc.
2945fbc2
GG		 5 *
6 * Author: Graeme Gregory <gg@slimlogic.co.uk>
654003e9 7 * Author: Ian Lartey <ian@slimlogic.co.uk>
2945fbc2
GG		 8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
13 *
14 */
15
16#ifndef __LINUX_MFD_PALMAS_H
17#define __LINUX_MFD_PALMAS_H
18
19#include <linux/usb/otg.h>
20#include <linux/leds.h>
21#include <linux/regmap.h>
22#include <linux/regulator/driver.h>
b1f254e3
GG		 23#include <linux/extcon.h>
24#include <linux/usb/phy_companion.h>
2945fbc2
GG		 25
26#define PALMAS_NUM_CLIENTS 3
27
654003e9
IL		 28/* The ID_REVISION NUMBERS */
29#define PALMAS_CHIP_OLD_ID 0x0000
30#define PALMAS_CHIP_ID 0xC035
31#define PALMAS_CHIP_CHARGER_ID 0xC036
32
027d7c2a
K		 33#define TPS65917_RESERVED -1
34
654003e9
IL		 35#define is_palmas(a) (((a) == PALMAS_CHIP_OLD_ID) || \
36 ((a) == PALMAS_CHIP_ID))
37#define is_palmas_charger(a) ((a) == PALMAS_CHIP_CHARGER_ID)
38
1ffb0be3
K		 39/**
40 * Palmas PMIC feature types
41 *
42 * PALMAS_PMIC_FEATURE_SMPS10_BOOST - used when the PMIC provides SMPS10_BOOST
43 * regulator.
44 *
45 * PALMAS_PMIC_HAS(b, f) - macro to check if a bandgap device is capable of a
46 * specific feature (above) or not. Return non-zero, if yes.
47 */
48#define PALMAS_PMIC_FEATURE_SMPS10_BOOST BIT(0)
49#define PALMAS_PMIC_HAS(b, f) \
50 ((b)->features & PALMAS_PMIC_FEATURE_ ## f)
51
2945fbc2 52struct palmas_pmic;
190ef1a6
GG		 53struct palmas_gpadc;
54struct palmas_resource;
55struct palmas_usb;
2945fbc2 56
b1f254e3
GG		 57enum palmas_usb_state {
58 PALMAS_USB_STATE_DISCONNECT,
59 PALMAS_USB_STATE_VBUS,
60 PALMAS_USB_STATE_ID,
61};
62
2945fbc2
GG		 63struct palmas {
64 struct device *dev;
65
66 struct i2c_client *i2c_clients[PALMAS_NUM_CLIENTS];
67 struct regmap *regmap[PALMAS_NUM_CLIENTS];
68
69 /* Stored chip id */
70 int id;
71
1ffb0be3 72 unsigned int features;
2945fbc2
GG		 73 /* IRQ Data */
74 int irq;
75 u32 irq_mask;
76 struct mutex irq_lock;
77 struct regmap_irq_chip_data *irq_data;
78
79 /* Child Devices */
80 struct palmas_pmic *pmic;
190ef1a6
GG		 81 struct palmas_gpadc *gpadc;
82 struct palmas_resource *resource;
83 struct palmas_usb *usb;
2945fbc2
GG		 84
85 /* GPIO MUXing */
86 u8 gpio_muxed;
87 u8 led_muxed;
88 u8 pwm_muxed;
89};
90
7ec70c73
K		 91#define PALMAS_EXT_REQ (PALMAS_EXT_CONTROL_ENABLE1 | \
92 PALMAS_EXT_CONTROL_ENABLE2 | \
93 PALMAS_EXT_CONTROL_NSLEEP)
94
95struct palmas_sleep_requestor_info {
96 int id;
97 int reg_offset;
98 int bit_pos;
99};
100
9f057dc1
K		 101struct regs_info {
102 char *name;
103 char *sname;
104 u8 vsel_addr;
105 u8 ctrl_addr;
106 u8 tstep_addr;
107 int sleep_id;
108};
109
190ef1a6
GG		 110struct palmas_gpadc_platform_data {
111 /* Channel 3 current source is only enabled during conversion */
112 int ch3_current;
113
114 /* Channel 0 current source can be used for battery detection.
115 * If used for battery detection this will cause a permanent current
116 * consumption depending on current level set here.
117 */
118 int ch0_current;
119
120 /* default BAT_REMOVAL_DAT setting on device probe */
121 int bat_removal;
122
123 /* Sets the START_POLARITY bit in the RT_CTRL register */
124 int start_polarity;
125};
126
2945fbc2
GG		 127struct palmas_reg_init {
128 /* warm_rest controls the voltage levels after a warm reset
129 *
130 * 0: reload default values from OTP on warm reset
131 * 1: maintain voltage from VSEL on warm reset
132 */
133 int warm_reset;
134
135 /* roof_floor controls whether the regulator uses the i2c style
136 * of DVS or uses the method where a GPIO or other control method is
137 * attached to the NSLEEP/ENABLE1/ENABLE2 pins
138 *
139 * For SMPS
140 *
141 * 0: i2c selection of voltage
142 * 1: pin selection of voltage.
143 *
144 * For LDO unused
145 */
146 int roof_floor;
147
148 /* sleep_mode is the mode loaded to MODE_SLEEP bits as defined in
149 * the data sheet.
150 *
151 * For SMPS
152 *
153 * 0: Off
154 * 1: AUTO
155 * 2: ECO
156 * 3: Forced PWM
157 *
158 * For LDO
159 *
160 * 0: Off
161 * 1: On
162 */
163 int mode_sleep;
164
2945fbc2
GG		 165 /* voltage_sel is the bitfield loaded onto the SMPSX_VOLTAGE
166 * register. Set this is the default voltage set in OTP needs
167 * to be overridden.
168 */
169 u8 vsel;
170
171};
172
7cc4c92f
GG		 173enum palmas_regulators {
174 /* SMPS regulators */
175 PALMAS_REG_SMPS12,
176 PALMAS_REG_SMPS123,
177 PALMAS_REG_SMPS3,
178 PALMAS_REG_SMPS45,
179 PALMAS_REG_SMPS457,
180 PALMAS_REG_SMPS6,
181 PALMAS_REG_SMPS7,
182 PALMAS_REG_SMPS8,
183 PALMAS_REG_SMPS9,
77409d9b
KVA		 184 PALMAS_REG_SMPS10_OUT2,
185 PALMAS_REG_SMPS10_OUT1,
7cc4c92f
GG		 186 /* LDO regulators */
187 PALMAS_REG_LDO1,
188 PALMAS_REG_LDO2,
189 PALMAS_REG_LDO3,
190 PALMAS_REG_LDO4,
191 PALMAS_REG_LDO5,
192 PALMAS_REG_LDO6,
193 PALMAS_REG_LDO7,
194 PALMAS_REG_LDO8,
195 PALMAS_REG_LDO9,
196 PALMAS_REG_LDOLN,
197 PALMAS_REG_LDOUSB,
aa07f027
LD		 198 /* External regulators */
199 PALMAS_REG_REGEN1,
200 PALMAS_REG_REGEN2,
201 PALMAS_REG_REGEN3,
202 PALMAS_REG_SYSEN1,
203 PALMAS_REG_SYSEN2,
7cc4c92f
GG		 204 /* Total number of regulators */
205 PALMAS_NUM_REGS,
206};
207
027d7c2a
K		 208enum tps65917_regulators {
209 /* SMPS regulators */
210 TPS65917_REG_SMPS1,
211 TPS65917_REG_SMPS2,
212 TPS65917_REG_SMPS3,
213 TPS65917_REG_SMPS4,
214 TPS65917_REG_SMPS5,
215 /* LDO regulators */
216 TPS65917_REG_LDO1,
217 TPS65917_REG_LDO2,
218 TPS65917_REG_LDO3,
219 TPS65917_REG_LDO4,
220 TPS65917_REG_LDO5,
221 TPS65917_REG_REGEN1,
222 TPS65917_REG_REGEN2,
223 TPS65917_REG_REGEN3,
224
225 /* Total number of regulators */
226 TPS65917_NUM_REGS,
227};
228
cc01b463
LD		 229/* External controll signal name */
230enum {
231 PALMAS_EXT_CONTROL_ENABLE1 = 0x1,
232 PALMAS_EXT_CONTROL_ENABLE2 = 0x2,
233 PALMAS_EXT_CONTROL_NSLEEP = 0x4,
234};
235
236/*
237 * Palmas device resources can be controlled externally for
238 * enabling/disabling it rather than register write through i2c.
239 * Add the external controlled requestor ID for different resources.
240 */
241enum palmas_external_requestor_id {
242 PALMAS_EXTERNAL_REQSTR_ID_REGEN1,
243 PALMAS_EXTERNAL_REQSTR_ID_REGEN2,
244 PALMAS_EXTERNAL_REQSTR_ID_SYSEN1,
245 PALMAS_EXTERNAL_REQSTR_ID_SYSEN2,
246 PALMAS_EXTERNAL_REQSTR_ID_CLK32KG,
247 PALMAS_EXTERNAL_REQSTR_ID_CLK32KGAUDIO,
248 PALMAS_EXTERNAL_REQSTR_ID_REGEN3,
249 PALMAS_EXTERNAL_REQSTR_ID_SMPS12,
250 PALMAS_EXTERNAL_REQSTR_ID_SMPS3,
251 PALMAS_EXTERNAL_REQSTR_ID_SMPS45,
252 PALMAS_EXTERNAL_REQSTR_ID_SMPS6,
253 PALMAS_EXTERNAL_REQSTR_ID_SMPS7,
254 PALMAS_EXTERNAL_REQSTR_ID_SMPS8,
255 PALMAS_EXTERNAL_REQSTR_ID_SMPS9,
256 PALMAS_EXTERNAL_REQSTR_ID_SMPS10,
257 PALMAS_EXTERNAL_REQSTR_ID_LDO1,
258 PALMAS_EXTERNAL_REQSTR_ID_LDO2,
259 PALMAS_EXTERNAL_REQSTR_ID_LDO3,
260 PALMAS_EXTERNAL_REQSTR_ID_LDO4,
261 PALMAS_EXTERNAL_REQSTR_ID_LDO5,
262 PALMAS_EXTERNAL_REQSTR_ID_LDO6,
263 PALMAS_EXTERNAL_REQSTR_ID_LDO7,
264 PALMAS_EXTERNAL_REQSTR_ID_LDO8,
265 PALMAS_EXTERNAL_REQSTR_ID_LDO9,
266 PALMAS_EXTERNAL_REQSTR_ID_LDOLN,
267 PALMAS_EXTERNAL_REQSTR_ID_LDOUSB,
268
269 /* Last entry */
270 PALMAS_EXTERNAL_REQSTR_ID_MAX,
271};
272
027d7c2a
K		 273enum tps65917_external_requestor_id {
274 TPS65917_EXTERNAL_REQSTR_ID_REGEN1,
275 TPS65917_EXTERNAL_REQSTR_ID_REGEN2,
276 TPS65917_EXTERNAL_REQSTR_ID_REGEN3,
277 TPS65917_EXTERNAL_REQSTR_ID_SMPS1,
278 TPS65917_EXTERNAL_REQSTR_ID_SMPS2,
279 TPS65917_EXTERNAL_REQSTR_ID_SMPS3,
280 TPS65917_EXTERNAL_REQSTR_ID_SMPS4,
281 TPS65917_EXTERNAL_REQSTR_ID_SMPS5,
282 TPS65917_EXTERNAL_REQSTR_ID_LDO1,
283 TPS65917_EXTERNAL_REQSTR_ID_LDO2,
284 TPS65917_EXTERNAL_REQSTR_ID_LDO3,
285 TPS65917_EXTERNAL_REQSTR_ID_LDO4,
286 TPS65917_EXTERNAL_REQSTR_ID_LDO5,
287 /* Last entry */
288 TPS65917_EXTERNAL_REQSTR_ID_MAX,
289};
290
2945fbc2
GG		 291struct palmas_pmic_platform_data {
292 /* An array of pointers to regulator init data indexed by regulator
293 * ID
294 */
7cc4c92f 295 struct regulator_init_data *reg_data[PALMAS_NUM_REGS];
2945fbc2
GG		 296
297 /* An array of pointers to structures containing sleep mode and DVS
298 * configuration for regulators indexed by ID
299 */
7cc4c92f 300 struct palmas_reg_init *reg_init[PALMAS_NUM_REGS];
2945fbc2
GG		 301
302 /* use LDO6 for vibrator control */
303 int ldo6_vibrator;
17c11a76
LD		 304
305 /* Enable tracking mode of LDO8 */
306 bool enable_ldo8_tracking;
190ef1a6
GG		 307};
308
309struct palmas_usb_platform_data {
190ef1a6
GG		 310 /* Do we enable the wakeup comparator on probe */
311 int wakeup;
312};
313
314struct palmas_resource_platform_data {
315 int regen1_mode_sleep;
316 int regen2_mode_sleep;
317 int sysen1_mode_sleep;
318 int sysen2_mode_sleep;
319
320 /* bitfield to be loaded to NSLEEP_RES_ASSIGN */
321 u8 nsleep_res;
322 /* bitfield to be loaded to NSLEEP_SMPS_ASSIGN */
323 u8 nsleep_smps;
324 /* bitfield to be loaded to NSLEEP_LDO_ASSIGN1 */
325 u8 nsleep_ldo1;
326 /* bitfield to be loaded to NSLEEP_LDO_ASSIGN2 */
327 u8 nsleep_ldo2;
328
329 /* bitfield to be loaded to ENABLE1_RES_ASSIGN */
330 u8 enable1_res;
331 /* bitfield to be loaded to ENABLE1_SMPS_ASSIGN */
332 u8 enable1_smps;
333 /* bitfield to be loaded to ENABLE1_LDO_ASSIGN1 */
334 u8 enable1_ldo1;
335 /* bitfield to be loaded to ENABLE1_LDO_ASSIGN2 */
336 u8 enable1_ldo2;
337
338 /* bitfield to be loaded to ENABLE2_RES_ASSIGN */
339 u8 enable2_res;
340 /* bitfield to be loaded to ENABLE2_SMPS_ASSIGN */
341 u8 enable2_smps;
342 /* bitfield to be loaded to ENABLE2_LDO_ASSIGN1 */
343 u8 enable2_ldo1;
344 /* bitfield to be loaded to ENABLE2_LDO_ASSIGN2 */
345 u8 enable2_ldo2;
346};
2945fbc2 347
190ef1a6
GG		 348struct palmas_clk_platform_data {
349 int clk32kg_mode_sleep;
350 int clk32kgaudio_mode_sleep;
2945fbc2
GG		 351};
352
353struct palmas_platform_data {
df545d1c 354 int irq_flags;
2945fbc2
GG		 355 int gpio_base;
356
357 /* bit value to be loaded to the POWER_CTRL register */
358 u8 power_ctrl;
359
360 /*
361 * boolean to select if we want to configure muxing here
362 * then the two value to load into the registers if true
363 */
364 int mux_from_pdata;
365 u8 pad1, pad2;
b81eec09 366 bool pm_off;
2945fbc2
GG		 367
368 struct palmas_pmic_platform_data *pmic_pdata;
190ef1a6
GG		 369 struct palmas_gpadc_platform_data *gpadc_pdata;
370 struct palmas_usb_platform_data *usb_pdata;
371 struct palmas_resource_platform_data *resource_pdata;
372 struct palmas_clk_platform_data *clk_pdata;
2945fbc2
GG		 373};
374
190ef1a6
GG		 375struct palmas_gpadc_calibration {
376 s32 gain;
377 s32 gain_error;
378 s32 offset_error;
379};
380
381struct palmas_gpadc {
382 struct device *dev;
383 struct palmas *palmas;
384
385 int ch3_current;
386 int ch0_current;
387
388 int gpadc_force;
389
390 int bat_removal;
391
392 struct mutex reading_lock;
393 struct completion irq_complete;
394
395 int eoc_sw_irq;
396
397 struct palmas_gpadc_calibration *palmas_cal_tbl;
398
399 int conv0_channel;
400 int conv1_channel;
401 int rt_channel;
402};
403
404struct palmas_gpadc_result {
405 s32 raw_code;
406 s32 corrected_code;
407 s32 result;
408};
409
410#define PALMAS_MAX_CHANNELS 16
411
027d7c2a
K		 412/* Define the tps65917 IRQ numbers */
413enum tps65917_irqs {
414 /* INT1 registers */
415 TPS65917_RESERVED1,
416 TPS65917_PWRON_IRQ,
417 TPS65917_LONG_PRESS_KEY_IRQ,
418 TPS65917_RESERVED2,
419 TPS65917_PWRDOWN_IRQ,
420 TPS65917_HOTDIE_IRQ,
421 TPS65917_VSYS_MON_IRQ,
422 TPS65917_RESERVED3,
423 /* INT2 registers */
424 TPS65917_RESERVED4,
425 TPS65917_OTP_ERROR_IRQ,
426 TPS65917_WDT_IRQ,
427 TPS65917_RESERVED5,
428 TPS65917_RESET_IN_IRQ,
429 TPS65917_FSD_IRQ,
430 TPS65917_SHORT_IRQ,
431 TPS65917_RESERVED6,
432 /* INT3 registers */
433 TPS65917_GPADC_AUTO_0_IRQ,
434 TPS65917_GPADC_AUTO_1_IRQ,
435 TPS65917_GPADC_EOC_SW_IRQ,
436 TPS65917_RESREVED6,
437 TPS65917_RESERVED7,
438 TPS65917_RESERVED8,
439 TPS65917_RESERVED9,
440 TPS65917_VBUS_IRQ,
441 /* INT4 registers */
442 TPS65917_GPIO_0_IRQ,
443 TPS65917_GPIO_1_IRQ,
444 TPS65917_GPIO_2_IRQ,
445 TPS65917_GPIO_3_IRQ,
446 TPS65917_GPIO_4_IRQ,
447 TPS65917_GPIO_5_IRQ,
448 TPS65917_GPIO_6_IRQ,
449 TPS65917_RESERVED10,
450 /* Total Number IRQs */
451 TPS65917_NUM_IRQ,
452};
453
2945fbc2
GG		 454/* Define the palmas IRQ numbers */
455enum palmas_irqs {
456 /* INT1 registers */
457 PALMAS_CHARG_DET_N_VBUS_OVV_IRQ,
458 PALMAS_PWRON_IRQ,
459 PALMAS_LONG_PRESS_KEY_IRQ,
460 PALMAS_RPWRON_IRQ,
461 PALMAS_PWRDOWN_IRQ,
462 PALMAS_HOTDIE_IRQ,
463 PALMAS_VSYS_MON_IRQ,
464 PALMAS_VBAT_MON_IRQ,
465 /* INT2 registers */
466 PALMAS_RTC_ALARM_IRQ,
467 PALMAS_RTC_TIMER_IRQ,
468 PALMAS_WDT_IRQ,
469 PALMAS_BATREMOVAL_IRQ,
470 PALMAS_RESET_IN_IRQ,
471 PALMAS_FBI_BB_IRQ,
472 PALMAS_SHORT_IRQ,
473 PALMAS_VAC_ACOK_IRQ,
474 /* INT3 registers */
475 PALMAS_GPADC_AUTO_0_IRQ,
476 PALMAS_GPADC_AUTO_1_IRQ,
477 PALMAS_GPADC_EOC_SW_IRQ,
478 PALMAS_GPADC_EOC_RT_IRQ,
479 PALMAS_ID_OTG_IRQ,
480 PALMAS_ID_IRQ,
481 PALMAS_VBUS_OTG_IRQ,
482 PALMAS_VBUS_IRQ,
483 /* INT4 registers */
484 PALMAS_GPIO_0_IRQ,
485 PALMAS_GPIO_1_IRQ,
486 PALMAS_GPIO_2_IRQ,
487 PALMAS_GPIO_3_IRQ,
488 PALMAS_GPIO_4_IRQ,
489 PALMAS_GPIO_5_IRQ,
490 PALMAS_GPIO_6_IRQ,
491 PALMAS_GPIO_7_IRQ,
492 /* Total Number IRQs */
493 PALMAS_NUM_IRQ,
494};
495
2945fbc2
GG		 496struct palmas_pmic {
497 struct palmas *palmas;
498 struct device *dev;
499 struct regulator_desc desc[PALMAS_NUM_REGS];
500 struct regulator_dev *rdev[PALMAS_NUM_REGS];
501 struct mutex mutex;
502
503 int smps123;
504 int smps457;
027d7c2a 505 int smps12;
2945fbc2 506
77409d9b
KVA		 507 int range[PALMAS_REG_SMPS10_OUT1];
508 unsigned int ramp_delay[PALMAS_REG_SMPS10_OUT1];
509 unsigned int current_reg_mode[PALMAS_REG_SMPS10_OUT1];
2945fbc2
GG		 510};
511
190ef1a6
GG		 512struct palmas_resource {
513 struct palmas *palmas;
514 struct device *dev;
515};
516
517struct palmas_usb {
518 struct palmas *palmas;
519 struct device *dev;
520
3f79a3fb 521 struct extcon_dev *edev;
190ef1a6 522
b1f254e3
GG		 523 int id_otg_irq;
524 int id_irq;
525 int vbus_otg_irq;
526 int vbus_irq;
190ef1a6 527
b1f254e3 528 enum palmas_usb_state linkstat;
7281e05a
LD		 529 int wakeup;
530 bool enable_vbus_detection;
531 bool enable_id_detection;
190ef1a6
GG		 532};
533
534#define comparator_to_palmas(x) container_of((x), struct palmas_usb, comparator)
535
536enum usb_irq_events {
537 /* Wakeup events from INT3 */
538 PALMAS_USB_ID_WAKEPUP,
539 PALMAS_USB_VBUS_WAKEUP,
540
541 /* ID_OTG_EVENTS */
542 PALMAS_USB_ID_GND,
543 N_PALMAS_USB_ID_GND,
544 PALMAS_USB_ID_C,
545 N_PALMAS_USB_ID_C,
546 PALMAS_USB_ID_B,
547 N_PALMAS_USB_ID_B,
548 PALMAS_USB_ID_A,
549 N_PALMAS_USB_ID_A,
550 PALMAS_USB_ID_FLOAT,
551 N_PALMAS_USB_ID_FLOAT,
552
553 /* VBUS_OTG_EVENTS */
554 PALMAS_USB_VB_SESS_END,
555 N_PALMAS_USB_VB_SESS_END,
556 PALMAS_USB_VB_SESS_VLD,
557 N_PALMAS_USB_VB_SESS_VLD,
558 PALMAS_USB_VA_SESS_VLD,
559 N_PALMAS_USB_VA_SESS_VLD,
560 PALMAS_USB_VA_VBUS_VLD,
561 N_PALMAS_USB_VA_VBUS_VLD,
562 PALMAS_USB_VADP_SNS,
563 N_PALMAS_USB_VADP_SNS,
564 PALMAS_USB_VADP_PRB,
565 N_PALMAS_USB_VADP_PRB,
566 PALMAS_USB_VOTG_SESS_VLD,
567 N_PALMAS_USB_VOTG_SESS_VLD,
568};
569
2945fbc2
GG		 570/* defines so we can store the mux settings */
571#define PALMAS_GPIO_0_MUXED (1 << 0)
572#define PALMAS_GPIO_1_MUXED (1 << 1)
573#define PALMAS_GPIO_2_MUXED (1 << 2)
574#define PALMAS_GPIO_3_MUXED (1 << 3)
575#define PALMAS_GPIO_4_MUXED (1 << 4)
576#define PALMAS_GPIO_5_MUXED (1 << 5)
577#define PALMAS_GPIO_6_MUXED (1 << 6)
578#define PALMAS_GPIO_7_MUXED (1 << 7)
579
580#define PALMAS_LED1_MUXED (1 << 0)
581#define PALMAS_LED2_MUXED (1 << 1)
582
583#define PALMAS_PWM1_MUXED (1 << 0)
584#define PALMAS_PWM2_MUXED (1 << 1)
585
586/* helper macro to get correct slave number */
587#define PALMAS_BASE_TO_SLAVE(x) ((x >> 8) - 1)
45ac60c0 588#define PALMAS_BASE_TO_REG(x, y) ((x & 0xFF) + y)
2945fbc2
GG		 589
590/* Base addresses of IP blocks in Palmas */
45ac60c0 591#define PALMAS_SMPS_DVS_BASE 0x020
2945fbc2
GG		 592#define PALMAS_RTC_BASE 0x100
593#define PALMAS_VALIDITY_BASE 0x118
594#define PALMAS_SMPS_BASE 0x120
595#define PALMAS_LDO_BASE 0x150
596#define PALMAS_DVFS_BASE 0x180
597#define PALMAS_PMU_CONTROL_BASE 0x1A0
598#define PALMAS_RESOURCE_BASE 0x1D4
0a8d3e24 599#define PALMAS_PU_PD_OD_BASE 0x1F0
2945fbc2
GG		 600#define PALMAS_LED_BASE 0x200
601#define PALMAS_INTERRUPT_BASE 0x210
602#define PALMAS_USB_OTG_BASE 0x250
603#define PALMAS_VIBRATOR_BASE 0x270
604#define PALMAS_GPIO_BASE 0x280
605#define PALMAS_USB_BASE 0x290
606#define PALMAS_GPADC_BASE 0x2C0
607#define PALMAS_TRIM_GPADC_BASE 0x3CD
608
609/* Registers for function RTC */
45ac60c0
K		 610#define PALMAS_SECONDS_REG 0x00
611#define PALMAS_MINUTES_REG 0x01
612#define PALMAS_HOURS_REG 0x02
613#define PALMAS_DAYS_REG 0x03
614#define PALMAS_MONTHS_REG 0x04
615#define PALMAS_YEARS_REG 0x05
616#define PALMAS_WEEKS_REG 0x06
617#define PALMAS_ALARM_SECONDS_REG 0x08
618#define PALMAS_ALARM_MINUTES_REG 0x09
619#define PALMAS_ALARM_HOURS_REG 0x0A
620#define PALMAS_ALARM_DAYS_REG 0x0B
621#define PALMAS_ALARM_MONTHS_REG 0x0C
622#define PALMAS_ALARM_YEARS_REG 0x0D
2945fbc2
GG		 623#define PALMAS_RTC_CTRL_REG 0x10
624#define PALMAS_RTC_STATUS_REG 0x11
625#define PALMAS_RTC_INTERRUPTS_REG 0x12
626#define PALMAS_RTC_COMP_LSB_REG 0x13
627#define PALMAS_RTC_COMP_MSB_REG 0x14
628#define PALMAS_RTC_RES_PROG_REG 0x15
629#define PALMAS_RTC_RESET_STATUS_REG 0x16
630
631/* Bit definitions for SECONDS_REG */
632#define PALMAS_SECONDS_REG_SEC1_MASK 0x70
45ac60c0
K		 633#define PALMAS_SECONDS_REG_SEC1_SHIFT 0x04
634#define PALMAS_SECONDS_REG_SEC0_MASK 0x0F
635#define PALMAS_SECONDS_REG_SEC0_SHIFT 0x00
2945fbc2
GG		 636
637/* Bit definitions for MINUTES_REG */
638#define PALMAS_MINUTES_REG_MIN1_MASK 0x70
45ac60c0
K		 639#define PALMAS_MINUTES_REG_MIN1_SHIFT 0x04
640#define PALMAS_MINUTES_REG_MIN0_MASK 0x0F
641#define PALMAS_MINUTES_REG_MIN0_SHIFT 0x00
2945fbc2
GG		 642
643/* Bit definitions for HOURS_REG */
644#define PALMAS_HOURS_REG_PM_NAM 0x80
45ac60c0 645#define PALMAS_HOURS_REG_PM_NAM_SHIFT 0x07
2945fbc2 646#define PALMAS_HOURS_REG_HOUR1_MASK 0x30
45ac60c0
K		 647#define PALMAS_HOURS_REG_HOUR1_SHIFT 0x04
648#define PALMAS_HOURS_REG_HOUR0_MASK 0x0F
649#define PALMAS_HOURS_REG_HOUR0_SHIFT 0x00
2945fbc2
GG		 650
651/* Bit definitions for DAYS_REG */
652#define PALMAS_DAYS_REG_DAY1_MASK 0x30
45ac60c0
K		 653#define PALMAS_DAYS_REG_DAY1_SHIFT 0x04
654#define PALMAS_DAYS_REG_DAY0_MASK 0x0F
655#define PALMAS_DAYS_REG_DAY0_SHIFT 0x00
2945fbc2
GG		 656
657/* Bit definitions for MONTHS_REG */
658#define PALMAS_MONTHS_REG_MONTH1 0x10
45ac60c0
K		 659#define PALMAS_MONTHS_REG_MONTH1_SHIFT 0x04
660#define PALMAS_MONTHS_REG_MONTH0_MASK 0x0F
661#define PALMAS_MONTHS_REG_MONTH0_SHIFT 0x00
2945fbc2
GG		 662
663/* Bit definitions for YEARS_REG */
664#define PALMAS_YEARS_REG_YEAR1_MASK 0xf0
45ac60c0
K		 665#define PALMAS_YEARS_REG_YEAR1_SHIFT 0x04
666#define PALMAS_YEARS_REG_YEAR0_MASK 0x0F
667#define PALMAS_YEARS_REG_YEAR0_SHIFT 0x00
2945fbc2
GG		 668
669/* Bit definitions for WEEKS_REG */
670#define PALMAS_WEEKS_REG_WEEK_MASK 0x07
45ac60c0 671#define PALMAS_WEEKS_REG_WEEK_SHIFT 0x00
2945fbc2
GG		 672
673/* Bit definitions for ALARM_SECONDS_REG */
674#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_MASK 0x70
45ac60c0
K		 675#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC1_SHIFT 0x04
676#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_MASK 0x0F
677#define PALMAS_ALARM_SECONDS_REG_ALARM_SEC0_SHIFT 0x00
2945fbc2
GG		 678
679/* Bit definitions for ALARM_MINUTES_REG */
680#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_MASK 0x70
45ac60c0
K		 681#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN1_SHIFT 0x04
682#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_MASK 0x0F
683#define PALMAS_ALARM_MINUTES_REG_ALARM_MIN0_SHIFT 0x00
2945fbc2
GG		 684
685/* Bit definitions for ALARM_HOURS_REG */
686#define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM 0x80
45ac60c0 687#define PALMAS_ALARM_HOURS_REG_ALARM_PM_NAM_SHIFT 0x07
2945fbc2 688#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_MASK 0x30
45ac60c0
K		 689#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR1_SHIFT 0x04
690#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_MASK 0x0F
691#define PALMAS_ALARM_HOURS_REG_ALARM_HOUR0_SHIFT 0x00
2945fbc2
GG		 692
693/* Bit definitions for ALARM_DAYS_REG */
694#define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_MASK 0x30
45ac60c0
K		 695#define PALMAS_ALARM_DAYS_REG_ALARM_DAY1_SHIFT 0x04
696#define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_MASK 0x0F
697#define PALMAS_ALARM_DAYS_REG_ALARM_DAY0_SHIFT 0x00
2945fbc2
GG		 698
699/* Bit definitions for ALARM_MONTHS_REG */
700#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1 0x10
45ac60c0
K		 701#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH1_SHIFT 0x04
702#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_MASK 0x0F
703#define PALMAS_ALARM_MONTHS_REG_ALARM_MONTH0_SHIFT 0x00
2945fbc2
GG		 704
705/* Bit definitions for ALARM_YEARS_REG */
706#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_MASK 0xf0
45ac60c0
K		 707#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR1_SHIFT 0x04
708#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_MASK 0x0F
709#define PALMAS_ALARM_YEARS_REG_ALARM_YEAR0_SHIFT 0x00
2945fbc2
GG		 710
711/* Bit definitions for RTC_CTRL_REG */
712#define PALMAS_RTC_CTRL_REG_RTC_V_OPT 0x80
45ac60c0 713#define PALMAS_RTC_CTRL_REG_RTC_V_OPT_SHIFT 0x07
2945fbc2 714#define PALMAS_RTC_CTRL_REG_GET_TIME 0x40
45ac60c0 715#define PALMAS_RTC_CTRL_REG_GET_TIME_SHIFT 0x06
2945fbc2 716#define PALMAS_RTC_CTRL_REG_SET_32_COUNTER 0x20
45ac60c0 717#define PALMAS_RTC_CTRL_REG_SET_32_COUNTER_SHIFT 0x05
2945fbc2 718#define PALMAS_RTC_CTRL_REG_TEST_MODE 0x10
45ac60c0 719#define PALMAS_RTC_CTRL_REG_TEST_MODE_SHIFT 0x04
2945fbc2 720#define PALMAS_RTC_CTRL_REG_MODE_12_24 0x08
45ac60c0 721#define PALMAS_RTC_CTRL_REG_MODE_12_24_SHIFT 0x03
2945fbc2 722#define PALMAS_RTC_CTRL_REG_AUTO_COMP 0x04
45ac60c0 723#define PALMAS_RTC_CTRL_REG_AUTO_COMP_SHIFT 0x02
2945fbc2 724#define PALMAS_RTC_CTRL_REG_ROUND_30S 0x02
45ac60c0 725#define PALMAS_RTC_CTRL_REG_ROUND_30S_SHIFT 0x01
2945fbc2 726#define PALMAS_RTC_CTRL_REG_STOP_RTC 0x01
45ac60c0 727#define PALMAS_RTC_CTRL_REG_STOP_RTC_SHIFT 0x00
2945fbc2
GG		 728
729/* Bit definitions for RTC_STATUS_REG */
730#define PALMAS_RTC_STATUS_REG_POWER_UP 0x80
45ac60c0 731#define PALMAS_RTC_STATUS_REG_POWER_UP_SHIFT 0x07
2945fbc2 732#define PALMAS_RTC_STATUS_REG_ALARM 0x40
45ac60c0 733#define PALMAS_RTC_STATUS_REG_ALARM_SHIFT 0x06
2945fbc2 734#define PALMAS_RTC_STATUS_REG_EVENT_1D 0x20
45ac60c0 735#define PALMAS_RTC_STATUS_REG_EVENT_1D_SHIFT 0x05
2945fbc2 736#define PALMAS_RTC_STATUS_REG_EVENT_1H 0x10
45ac60c0 737#define PALMAS_RTC_STATUS_REG_EVENT_1H_SHIFT 0x04
2945fbc2 738#define PALMAS_RTC_STATUS_REG_EVENT_1M 0x08
45ac60c0 739#define PALMAS_RTC_STATUS_REG_EVENT_1M_SHIFT 0x03
2945fbc2 740#define PALMAS_RTC_STATUS_REG_EVENT_1S 0x04
45ac60c0 741#define PALMAS_RTC_STATUS_REG_EVENT_1S_SHIFT 0x02
2945fbc2 742#define PALMAS_RTC_STATUS_REG_RUN 0x02
45ac60c0 743#define PALMAS_RTC_STATUS_REG_RUN_SHIFT 0x01
2945fbc2
GG		 744
745/* Bit definitions for RTC_INTERRUPTS_REG */
746#define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN 0x10
45ac60c0 747#define PALMAS_RTC_INTERRUPTS_REG_IT_SLEEP_MASK_EN_SHIFT 0x04
2945fbc2 748#define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM 0x08
45ac60c0 749#define PALMAS_RTC_INTERRUPTS_REG_IT_ALARM_SHIFT 0x03
2945fbc2 750#define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER 0x04
45ac60c0 751#define PALMAS_RTC_INTERRUPTS_REG_IT_TIMER_SHIFT 0x02
2945fbc2 752#define PALMAS_RTC_INTERRUPTS_REG_EVERY_MASK 0x03
45ac60c0 753#define PALMAS_RTC_INTERRUPTS_REG_EVERY_SHIFT 0x00
2945fbc2
GG		 754
755/* Bit definitions for RTC_COMP_LSB_REG */
45ac60c0
K		 756#define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_MASK 0xFF
757#define PALMAS_RTC_COMP_LSB_REG_RTC_COMP_LSB_SHIFT 0x00
2945fbc2
GG		 758
759/* Bit definitions for RTC_COMP_MSB_REG */
45ac60c0
K		 760#define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_MASK 0xFF
761#define PALMAS_RTC_COMP_MSB_REG_RTC_COMP_MSB_SHIFT 0x00
2945fbc2
GG		 762
763/* Bit definitions for RTC_RES_PROG_REG */
45ac60c0
K		 764#define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_MASK 0x3F
765#define PALMAS_RTC_RES_PROG_REG_SW_RES_PROG_SHIFT 0x00
2945fbc2
GG		 766
767/* Bit definitions for RTC_RESET_STATUS_REG */
768#define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS 0x01
45ac60c0 769#define PALMAS_RTC_RESET_STATUS_REG_RESET_STATUS_SHIFT 0x00
2945fbc2
GG		 770
771/* Registers for function BACKUP */
45ac60c0
K		 772#define PALMAS_BACKUP0 0x00
773#define PALMAS_BACKUP1 0x01
774#define PALMAS_BACKUP2 0x02
775#define PALMAS_BACKUP3 0x03
776#define PALMAS_BACKUP4 0x04
777#define PALMAS_BACKUP5 0x05
778#define PALMAS_BACKUP6 0x06
779#define PALMAS_BACKUP7 0x07
2945fbc2
GG		 780
781/* Bit definitions for BACKUP0 */
45ac60c0
K		 782#define PALMAS_BACKUP0_BACKUP_MASK 0xFF
783#define PALMAS_BACKUP0_BACKUP_SHIFT 0x00
2945fbc2
GG		 784
785/* Bit definitions for BACKUP1 */
45ac60c0
K		 786#define PALMAS_BACKUP1_BACKUP_MASK 0xFF
787#define PALMAS_BACKUP1_BACKUP_SHIFT 0x00
2945fbc2
GG		 788
789/* Bit definitions for BACKUP2 */
45ac60c0
K		 790#define PALMAS_BACKUP2_BACKUP_MASK 0xFF
791#define PALMAS_BACKUP2_BACKUP_SHIFT 0x00
2945fbc2
GG		 792
793/* Bit definitions for BACKUP3 */
45ac60c0
K		 794#define PALMAS_BACKUP3_BACKUP_MASK 0xFF
795#define PALMAS_BACKUP3_BACKUP_SHIFT 0x00
2945fbc2
GG		 796
797/* Bit definitions for BACKUP4 */
45ac60c0
K		 798#define PALMAS_BACKUP4_BACKUP_MASK 0xFF
799#define PALMAS_BACKUP4_BACKUP_SHIFT 0x00
2945fbc2
GG		 800
801/* Bit definitions for BACKUP5 */
45ac60c0
K		 802#define PALMAS_BACKUP5_BACKUP_MASK 0xFF
803#define PALMAS_BACKUP5_BACKUP_SHIFT 0x00
2945fbc2
GG		 804
805/* Bit definitions for BACKUP6 */
45ac60c0
K		 806#define PALMAS_BACKUP6_BACKUP_MASK 0xFF
807#define PALMAS_BACKUP6_BACKUP_SHIFT 0x00
2945fbc2
GG		 808
809/* Bit definitions for BACKUP7 */
45ac60c0
K		 810#define PALMAS_BACKUP7_BACKUP_MASK 0xFF
811#define PALMAS_BACKUP7_BACKUP_SHIFT 0x00
2945fbc2
GG		 812
813/* Registers for function SMPS */
45ac60c0
K		 814#define PALMAS_SMPS12_CTRL 0x00
815#define PALMAS_SMPS12_TSTEP 0x01
816#define PALMAS_SMPS12_FORCE 0x02
817#define PALMAS_SMPS12_VOLTAGE 0x03
818#define PALMAS_SMPS3_CTRL 0x04
819#define PALMAS_SMPS3_VOLTAGE 0x07
820#define PALMAS_SMPS45_CTRL 0x08
821#define PALMAS_SMPS45_TSTEP 0x09
822#define PALMAS_SMPS45_FORCE 0x0A
823#define PALMAS_SMPS45_VOLTAGE 0x0B
824#define PALMAS_SMPS6_CTRL 0x0C
825#define PALMAS_SMPS6_TSTEP 0x0D
826#define PALMAS_SMPS6_FORCE 0x0E
827#define PALMAS_SMPS6_VOLTAGE 0x0F
2945fbc2
GG		 828#define PALMAS_SMPS7_CTRL 0x10
829#define PALMAS_SMPS7_VOLTAGE 0x13
830#define PALMAS_SMPS8_CTRL 0x14
831#define PALMAS_SMPS8_TSTEP 0x15
832#define PALMAS_SMPS8_FORCE 0x16
833#define PALMAS_SMPS8_VOLTAGE 0x17
834#define PALMAS_SMPS9_CTRL 0x18
835#define PALMAS_SMPS9_VOLTAGE 0x1B
836#define PALMAS_SMPS10_CTRL 0x1C
837#define PALMAS_SMPS10_STATUS 0x1F
838#define PALMAS_SMPS_CTRL 0x24
839#define PALMAS_SMPS_PD_CTRL 0x25
840#define PALMAS_SMPS_DITHER_EN 0x26
841#define PALMAS_SMPS_THERMAL_EN 0x27
842#define PALMAS_SMPS_THERMAL_STATUS 0x28
843#define PALMAS_SMPS_SHORT_STATUS 0x29
844#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN 0x2A
845#define PALMAS_SMPS_POWERGOOD_MASK1 0x2B
846#define PALMAS_SMPS_POWERGOOD_MASK2 0x2C
847
848/* Bit definitions for SMPS12_CTRL */
849#define PALMAS_SMPS12_CTRL_WR_S 0x80
45ac60c0 850#define PALMAS_SMPS12_CTRL_WR_S_SHIFT 0x07
2945fbc2 851#define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN 0x40
45ac60c0 852#define PALMAS_SMPS12_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
2945fbc2 853#define PALMAS_SMPS12_CTRL_STATUS_MASK 0x30
45ac60c0 854#define PALMAS_SMPS12_CTRL_STATUS_SHIFT 0x04
2945fbc2 855#define PALMAS_SMPS12_CTRL_MODE_SLEEP_MASK 0x0c
45ac60c0 856#define PALMAS_SMPS12_CTRL_MODE_SLEEP_SHIFT 0x02
2945fbc2 857#define PALMAS_SMPS12_CTRL_MODE_ACTIVE_MASK 0x03
45ac60c0 858#define PALMAS_SMPS12_CTRL_MODE_ACTIVE_SHIFT 0x00
2945fbc2
GG		 859
860/* Bit definitions for SMPS12_TSTEP */
861#define PALMAS_SMPS12_TSTEP_TSTEP_MASK 0x03
45ac60c0 862#define PALMAS_SMPS12_TSTEP_TSTEP_SHIFT 0x00
2945fbc2
GG		 863
864/* Bit definitions for SMPS12_FORCE */
865#define PALMAS_SMPS12_FORCE_CMD 0x80
45ac60c0
K		 866#define PALMAS_SMPS12_FORCE_CMD_SHIFT 0x07
867#define PALMAS_SMPS12_FORCE_VSEL_MASK 0x7F
868#define PALMAS_SMPS12_FORCE_VSEL_SHIFT 0x00
2945fbc2
GG		 869
870/* Bit definitions for SMPS12_VOLTAGE */
871#define PALMAS_SMPS12_VOLTAGE_RANGE 0x80
45ac60c0
K		 872#define PALMAS_SMPS12_VOLTAGE_RANGE_SHIFT 0x07
873#define PALMAS_SMPS12_VOLTAGE_VSEL_MASK 0x7F
874#define PALMAS_SMPS12_VOLTAGE_VSEL_SHIFT 0x00
2945fbc2
GG		 875
876/* Bit definitions for SMPS3_CTRL */
877#define PALMAS_SMPS3_CTRL_WR_S 0x80
45ac60c0 878#define PALMAS_SMPS3_CTRL_WR_S_SHIFT 0x07
2945fbc2 879#define PALMAS_SMPS3_CTRL_STATUS_MASK 0x30
45ac60c0 880#define PALMAS_SMPS3_CTRL_STATUS_SHIFT 0x04
2945fbc2 881#define PALMAS_SMPS3_CTRL_MODE_SLEEP_MASK 0x0c
45ac60c0 882#define PALMAS_SMPS3_CTRL_MODE_SLEEP_SHIFT 0x02
2945fbc2 883#define PALMAS_SMPS3_CTRL_MODE_ACTIVE_MASK 0x03
45ac60c0 884#define PALMAS_SMPS3_CTRL_MODE_ACTIVE_SHIFT 0x00
2945fbc2
GG		 885
886/* Bit definitions for SMPS3_VOLTAGE */
887#define PALMAS_SMPS3_VOLTAGE_RANGE 0x80
45ac60c0
K		 888#define PALMAS_SMPS3_VOLTAGE_RANGE_SHIFT 0x07
889#define PALMAS_SMPS3_VOLTAGE_VSEL_MASK 0x7F
890#define PALMAS_SMPS3_VOLTAGE_VSEL_SHIFT 0x00
2945fbc2
GG		 891
892/* Bit definitions for SMPS45_CTRL */
893#define PALMAS_SMPS45_CTRL_WR_S 0x80
45ac60c0 894#define PALMAS_SMPS45_CTRL_WR_S_SHIFT 0x07
2945fbc2 895#define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN 0x40
45ac60c0 896#define PALMAS_SMPS45_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
2945fbc2 897#define PALMAS_SMPS45_CTRL_STATUS_MASK 0x30
45ac60c0 898#define PALMAS_SMPS45_CTRL_STATUS_SHIFT 0x04
2945fbc2 899#define PALMAS_SMPS45_CTRL_MODE_SLEEP_MASK 0x0c
45ac60c0 900#define PALMAS_SMPS45_CTRL_MODE_SLEEP_SHIFT 0x02
2945fbc2 901#define PALMAS_SMPS45_CTRL_MODE_ACTIVE_MASK 0x03
45ac60c0 902#define PALMAS_SMPS45_CTRL_MODE_ACTIVE_SHIFT 0x00
2945fbc2
GG		 903
904/* Bit definitions for SMPS45_TSTEP */
905#define PALMAS_SMPS45_TSTEP_TSTEP_MASK 0x03
45ac60c0 906#define PALMAS_SMPS45_TSTEP_TSTEP_SHIFT 0x00
2945fbc2
GG		 907
908/* Bit definitions for SMPS45_FORCE */
909#define PALMAS_SMPS45_FORCE_CMD 0x80
45ac60c0
K		 910#define PALMAS_SMPS45_FORCE_CMD_SHIFT 0x07
911#define PALMAS_SMPS45_FORCE_VSEL_MASK 0x7F
912#define PALMAS_SMPS45_FORCE_VSEL_SHIFT 0x00
2945fbc2
GG		 913
914/* Bit definitions for SMPS45_VOLTAGE */
915#define PALMAS_SMPS45_VOLTAGE_RANGE 0x80
45ac60c0
K		 916#define PALMAS_SMPS45_VOLTAGE_RANGE_SHIFT 0x07
917#define PALMAS_SMPS45_VOLTAGE_VSEL_MASK 0x7F
918#define PALMAS_SMPS45_VOLTAGE_VSEL_SHIFT 0x00
2945fbc2
GG		 919
920/* Bit definitions for SMPS6_CTRL */
921#define PALMAS_SMPS6_CTRL_WR_S 0x80
45ac60c0 922#define PALMAS_SMPS6_CTRL_WR_S_SHIFT 0x07
2945fbc2 923#define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN 0x40
45ac60c0 924#define PALMAS_SMPS6_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
2945fbc2 925#define PALMAS_SMPS6_CTRL_STATUS_MASK 0x30
45ac60c0 926#define PALMAS_SMPS6_CTRL_STATUS_SHIFT 0x04
2945fbc2 927#define PALMAS_SMPS6_CTRL_MODE_SLEEP_MASK 0x0c
45ac60c0 928#define PALMAS_SMPS6_CTRL_MODE_SLEEP_SHIFT 0x02
2945fbc2 929#define PALMAS_SMPS6_CTRL_MODE_ACTIVE_MASK 0x03
45ac60c0 930#define PALMAS_SMPS6_CTRL_MODE_ACTIVE_SHIFT 0x00
2945fbc2
GG		 931
932/* Bit definitions for SMPS6_TSTEP */
933#define PALMAS_SMPS6_TSTEP_TSTEP_MASK 0x03
45ac60c0 934#define PALMAS_SMPS6_TSTEP_TSTEP_SHIFT 0x00
2945fbc2
GG		 935
936/* Bit definitions for SMPS6_FORCE */
937#define PALMAS_SMPS6_FORCE_CMD 0x80
45ac60c0
K		 938#define PALMAS_SMPS6_FORCE_CMD_SHIFT 0x07
939#define PALMAS_SMPS6_FORCE_VSEL_MASK 0x7F
940#define PALMAS_SMPS6_FORCE_VSEL_SHIFT 0x00
2945fbc2
GG		 941
942/* Bit definitions for SMPS6_VOLTAGE */
943#define PALMAS_SMPS6_VOLTAGE_RANGE 0x80
45ac60c0
K		 944#define PALMAS_SMPS6_VOLTAGE_RANGE_SHIFT 0x07
945#define PALMAS_SMPS6_VOLTAGE_VSEL_MASK 0x7F
946#define PALMAS_SMPS6_VOLTAGE_VSEL_SHIFT 0x00
2945fbc2
GG		 947
948/* Bit definitions for SMPS7_CTRL */
949#define PALMAS_SMPS7_CTRL_WR_S 0x80
45ac60c0 950#define PALMAS_SMPS7_CTRL_WR_S_SHIFT 0x07
2945fbc2 951#define PALMAS_SMPS7_CTRL_STATUS_MASK 0x30
45ac60c0 952#define PALMAS_SMPS7_CTRL_STATUS_SHIFT 0x04
2945fbc2 953#define PALMAS_SMPS7_CTRL_MODE_SLEEP_MASK 0x0c
45ac60c0 954#define PALMAS_SMPS7_CTRL_MODE_SLEEP_SHIFT 0x02
2945fbc2 955#define PALMAS_SMPS7_CTRL_MODE_ACTIVE_MASK 0x03
45ac60c0 956#define PALMAS_SMPS7_CTRL_MODE_ACTIVE_SHIFT 0x00
2945fbc2
GG		 957
958/* Bit definitions for SMPS7_VOLTAGE */
959#define PALMAS_SMPS7_VOLTAGE_RANGE 0x80
45ac60c0
K		 960#define PALMAS_SMPS7_VOLTAGE_RANGE_SHIFT 0x07
961#define PALMAS_SMPS7_VOLTAGE_VSEL_MASK 0x7F
962#define PALMAS_SMPS7_VOLTAGE_VSEL_SHIFT 0x00
2945fbc2
GG		 963
964/* Bit definitions for SMPS8_CTRL */
965#define PALMAS_SMPS8_CTRL_WR_S 0x80
45ac60c0 966#define PALMAS_SMPS8_CTRL_WR_S_SHIFT 0x07
2945fbc2 967#define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN 0x40
45ac60c0 968#define PALMAS_SMPS8_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
2945fbc2 969#define PALMAS_SMPS8_CTRL_STATUS_MASK 0x30
45ac60c0 970#define PALMAS_SMPS8_CTRL_STATUS_SHIFT 0x04
2945fbc2 971#define PALMAS_SMPS8_CTRL_MODE_SLEEP_MASK 0x0c
45ac60c0 972#define PALMAS_SMPS8_CTRL_MODE_SLEEP_SHIFT 0x02
2945fbc2 973#define PALMAS_SMPS8_CTRL_MODE_ACTIVE_MASK 0x03
45ac60c0 974#define PALMAS_SMPS8_CTRL_MODE_ACTIVE_SHIFT 0x00
2945fbc2
GG		 975
976/* Bit definitions for SMPS8_TSTEP */
977#define PALMAS_SMPS8_TSTEP_TSTEP_MASK 0x03
45ac60c0 978#define PALMAS_SMPS8_TSTEP_TSTEP_SHIFT 0x00
2945fbc2
GG		 979
980/* Bit definitions for SMPS8_FORCE */
981#define PALMAS_SMPS8_FORCE_CMD 0x80
45ac60c0
K		 982#define PALMAS_SMPS8_FORCE_CMD_SHIFT 0x07
983#define PALMAS_SMPS8_FORCE_VSEL_MASK 0x7F
984#define PALMAS_SMPS8_FORCE_VSEL_SHIFT 0x00
2945fbc2
GG		 985
986/* Bit definitions for SMPS8_VOLTAGE */
987#define PALMAS_SMPS8_VOLTAGE_RANGE 0x80
45ac60c0
K		 988#define PALMAS_SMPS8_VOLTAGE_RANGE_SHIFT 0x07
989#define PALMAS_SMPS8_VOLTAGE_VSEL_MASK 0x7F
990#define PALMAS_SMPS8_VOLTAGE_VSEL_SHIFT 0x00
2945fbc2
GG		 991
992/* Bit definitions for SMPS9_CTRL */
993#define PALMAS_SMPS9_CTRL_WR_S 0x80
45ac60c0 994#define PALMAS_SMPS9_CTRL_WR_S_SHIFT 0x07
2945fbc2 995#define PALMAS_SMPS9_CTRL_STATUS_MASK 0x30
45ac60c0 996#define PALMAS_SMPS9_CTRL_STATUS_SHIFT 0x04
2945fbc2 997#define PALMAS_SMPS9_CTRL_MODE_SLEEP_MASK 0x0c
45ac60c0 998#define PALMAS_SMPS9_CTRL_MODE_SLEEP_SHIFT 0x02
2945fbc2 999#define PALMAS_SMPS9_CTRL_MODE_ACTIVE_MASK 0x03
45ac60c0 1000#define PALMAS_SMPS9_CTRL_MODE_ACTIVE_SHIFT 0x00
2945fbc2
GG		 1001
1002/* Bit definitions for SMPS9_VOLTAGE */
1003#define PALMAS_SMPS9_VOLTAGE_RANGE 0x80
45ac60c0
K		 1004#define PALMAS_SMPS9_VOLTAGE_RANGE_SHIFT 0x07
1005#define PALMAS_SMPS9_VOLTAGE_VSEL_MASK 0x7F
1006#define PALMAS_SMPS9_VOLTAGE_VSEL_SHIFT 0x00
2945fbc2
GG		 1007
1008/* Bit definitions for SMPS10_CTRL */
1009#define PALMAS_SMPS10_CTRL_MODE_SLEEP_MASK 0xf0
45ac60c0
K		 1010#define PALMAS_SMPS10_CTRL_MODE_SLEEP_SHIFT 0x04
1011#define PALMAS_SMPS10_CTRL_MODE_ACTIVE_MASK 0x0F
1012#define PALMAS_SMPS10_CTRL_MODE_ACTIVE_SHIFT 0x00
2945fbc2
GG		 1013
1014/* Bit definitions for SMPS10_STATUS */
45ac60c0
K		 1015#define PALMAS_SMPS10_STATUS_STATUS_MASK 0x0F
1016#define PALMAS_SMPS10_STATUS_STATUS_SHIFT 0x00
2945fbc2
GG		 1017
1018/* Bit definitions for SMPS_CTRL */
1019#define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN 0x20
45ac60c0 1020#define PALMAS_SMPS_CTRL_SMPS45_SMPS457_EN_SHIFT 0x05
2945fbc2 1021#define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN 0x10
45ac60c0 1022#define PALMAS_SMPS_CTRL_SMPS12_SMPS123_EN_SHIFT 0x04
2945fbc2 1023#define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_MASK 0x0c
45ac60c0 1024#define PALMAS_SMPS_CTRL_SMPS45_PHASE_CTRL_SHIFT 0x02
2945fbc2 1025#define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_MASK 0x03
45ac60c0 1026#define PALMAS_SMPS_CTRL_SMPS123_PHASE_CTRL_SHIFT 0x00
2945fbc2
GG		 1027
1028/* Bit definitions for SMPS_PD_CTRL */
1029#define PALMAS_SMPS_PD_CTRL_SMPS9 0x40
45ac60c0 1030#define PALMAS_SMPS_PD_CTRL_SMPS9_SHIFT 0x06
2945fbc2 1031#define PALMAS_SMPS_PD_CTRL_SMPS8 0x20
45ac60c0 1032#define PALMAS_SMPS_PD_CTRL_SMPS8_SHIFT 0x05
2945fbc2 1033#define PALMAS_SMPS_PD_CTRL_SMPS7 0x10
45ac60c0 1034#define PALMAS_SMPS_PD_CTRL_SMPS7_SHIFT 0x04
2945fbc2 1035#define PALMAS_SMPS_PD_CTRL_SMPS6 0x08
45ac60c0 1036#define PALMAS_SMPS_PD_CTRL_SMPS6_SHIFT 0x03
2945fbc2 1037#define PALMAS_SMPS_PD_CTRL_SMPS45 0x04
45ac60c0 1038#define PALMAS_SMPS_PD_CTRL_SMPS45_SHIFT 0x02
2945fbc2 1039#define PALMAS_SMPS_PD_CTRL_SMPS3 0x02
45ac60c0 1040#define PALMAS_SMPS_PD_CTRL_SMPS3_SHIFT 0x01
2945fbc2 1041#define PALMAS_SMPS_PD_CTRL_SMPS12 0x01
45ac60c0 1042#define PALMAS_SMPS_PD_CTRL_SMPS12_SHIFT 0x00
2945fbc2
GG		 1043
1044/* Bit definitions for SMPS_THERMAL_EN */
1045#define PALMAS_SMPS_THERMAL_EN_SMPS9 0x40
45ac60c0 1046#define PALMAS_SMPS_THERMAL_EN_SMPS9_SHIFT 0x06
2945fbc2 1047#define PALMAS_SMPS_THERMAL_EN_SMPS8 0x20
45ac60c0 1048#define PALMAS_SMPS_THERMAL_EN_SMPS8_SHIFT 0x05
2945fbc2 1049#define PALMAS_SMPS_THERMAL_EN_SMPS6 0x08
45ac60c0 1050#define PALMAS_SMPS_THERMAL_EN_SMPS6_SHIFT 0x03
2945fbc2 1051#define PALMAS_SMPS_THERMAL_EN_SMPS457 0x04
45ac60c0 1052#define PALMAS_SMPS_THERMAL_EN_SMPS457_SHIFT 0x02
2945fbc2 1053#define PALMAS_SMPS_THERMAL_EN_SMPS123 0x01
45ac60c0 1054#define PALMAS_SMPS_THERMAL_EN_SMPS123_SHIFT 0x00
2945fbc2
GG		 1055
1056/* Bit definitions for SMPS_THERMAL_STATUS */
1057#define PALMAS_SMPS_THERMAL_STATUS_SMPS9 0x40
45ac60c0 1058#define PALMAS_SMPS_THERMAL_STATUS_SMPS9_SHIFT 0x06
2945fbc2 1059#define PALMAS_SMPS_THERMAL_STATUS_SMPS8 0x20
45ac60c0 1060#define PALMAS_SMPS_THERMAL_STATUS_SMPS8_SHIFT 0x05
2945fbc2 1061#define PALMAS_SMPS_THERMAL_STATUS_SMPS6 0x08
45ac60c0 1062#define PALMAS_SMPS_THERMAL_STATUS_SMPS6_SHIFT 0x03
2945fbc2 1063#define PALMAS_SMPS_THERMAL_STATUS_SMPS457 0x04
45ac60c0 1064#define PALMAS_SMPS_THERMAL_STATUS_SMPS457_SHIFT 0x02
2945fbc2 1065#define PALMAS_SMPS_THERMAL_STATUS_SMPS123 0x01
45ac60c0 1066#define PALMAS_SMPS_THERMAL_STATUS_SMPS123_SHIFT 0x00
2945fbc2
GG		 1067
1068/* Bit definitions for SMPS_SHORT_STATUS */
1069#define PALMAS_SMPS_SHORT_STATUS_SMPS10 0x80
45ac60c0 1070#define PALMAS_SMPS_SHORT_STATUS_SMPS10_SHIFT 0x07
2945fbc2 1071#define PALMAS_SMPS_SHORT_STATUS_SMPS9 0x40
45ac60c0 1072#define PALMAS_SMPS_SHORT_STATUS_SMPS9_SHIFT 0x06
2945fbc2 1073#define PALMAS_SMPS_SHORT_STATUS_SMPS8 0x20
45ac60c0 1074#define PALMAS_SMPS_SHORT_STATUS_SMPS8_SHIFT 0x05
2945fbc2 1075#define PALMAS_SMPS_SHORT_STATUS_SMPS7 0x10
45ac60c0 1076#define PALMAS_SMPS_SHORT_STATUS_SMPS7_SHIFT 0x04
2945fbc2 1077#define PALMAS_SMPS_SHORT_STATUS_SMPS6 0x08
45ac60c0 1078#define PALMAS_SMPS_SHORT_STATUS_SMPS6_SHIFT 0x03
2945fbc2 1079#define PALMAS_SMPS_SHORT_STATUS_SMPS45 0x04
45ac60c0 1080#define PALMAS_SMPS_SHORT_STATUS_SMPS45_SHIFT 0x02
2945fbc2 1081#define PALMAS_SMPS_SHORT_STATUS_SMPS3 0x02
45ac60c0 1082#define PALMAS_SMPS_SHORT_STATUS_SMPS3_SHIFT 0x01
2945fbc2 1083#define PALMAS_SMPS_SHORT_STATUS_SMPS12 0x01
45ac60c0 1084#define PALMAS_SMPS_SHORT_STATUS_SMPS12_SHIFT 0x00
2945fbc2
GG		 1085
1086/* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */
1087#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9 0x40
45ac60c0 1088#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS9_SHIFT 0x06
2945fbc2 1089#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8 0x20
45ac60c0 1090#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS8_SHIFT 0x05
2945fbc2 1091#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7 0x10
45ac60c0 1092#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS7_SHIFT 0x04
2945fbc2 1093#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6 0x08
45ac60c0 1094#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS6_SHIFT 0x03
2945fbc2 1095#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45 0x04
45ac60c0 1096#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS45_SHIFT 0x02
2945fbc2 1097#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3 0x02
45ac60c0 1098#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT 0x01
2945fbc2 1099#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12 0x01
45ac60c0 1100#define PALMAS_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS12_SHIFT 0x00
2945fbc2
GG		 1101
1102/* Bit definitions for SMPS_POWERGOOD_MASK1 */
1103#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10 0x80
45ac60c0 1104#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS10_SHIFT 0x07
2945fbc2 1105#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9 0x40
45ac60c0 1106#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS9_SHIFT 0x06
2945fbc2 1107#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8 0x20
45ac60c0 1108#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS8_SHIFT 0x05
2945fbc2 1109#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7 0x10
45ac60c0 1110#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS7_SHIFT 0x04
2945fbc2 1111#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6 0x08
45ac60c0 1112#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS6_SHIFT 0x03
2945fbc2 1113#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45 0x04
45ac60c0 1114#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS45_SHIFT 0x02
2945fbc2 1115#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3 0x02
45ac60c0 1116#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT 0x01
2945fbc2 1117#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12 0x01
45ac60c0 1118#define PALMAS_SMPS_POWERGOOD_MASK1_SMPS12_SHIFT 0x00
2945fbc2
GG		 1119
1120/* Bit definitions for SMPS_POWERGOOD_MASK2 */
1121#define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT 0x80
45ac60c0 1122#define PALMAS_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 0x07
2945fbc2 1123#define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7 0x04
45ac60c0 1124#define PALMAS_SMPS_POWERGOOD_MASK2_GPIO_7_SHIFT 0x02
2945fbc2 1125#define PALMAS_SMPS_POWERGOOD_MASK2_VBUS 0x02
45ac60c0 1126#define PALMAS_SMPS_POWERGOOD_MASK2_VBUS_SHIFT 0x01
2945fbc2 1127#define PALMAS_SMPS_POWERGOOD_MASK2_ACOK 0x01
45ac60c0 1128#define PALMAS_SMPS_POWERGOOD_MASK2_ACOK_SHIFT 0x00
2945fbc2
GG		 1129
1130/* Registers for function LDO */
45ac60c0
K		 1131#define PALMAS_LDO1_CTRL 0x00
1132#define PALMAS_LDO1_VOLTAGE 0x01
1133#define PALMAS_LDO2_CTRL 0x02
1134#define PALMAS_LDO2_VOLTAGE 0x03
1135#define PALMAS_LDO3_CTRL 0x04
1136#define PALMAS_LDO3_VOLTAGE 0x05
1137#define PALMAS_LDO4_CTRL 0x06
1138#define PALMAS_LDO4_VOLTAGE 0x07
1139#define PALMAS_LDO5_CTRL 0x08
1140#define PALMAS_LDO5_VOLTAGE 0x09
1141#define PALMAS_LDO6_CTRL 0x0A
1142#define PALMAS_LDO6_VOLTAGE 0x0B
1143#define PALMAS_LDO7_CTRL 0x0C
1144#define PALMAS_LDO7_VOLTAGE 0x0D
1145#define PALMAS_LDO8_CTRL 0x0E
1146#define PALMAS_LDO8_VOLTAGE 0x0F
2945fbc2
GG		 1147#define PALMAS_LDO9_CTRL 0x10
1148#define PALMAS_LDO9_VOLTAGE 0x11
1149#define PALMAS_LDOLN_CTRL 0x12
1150#define PALMAS_LDOLN_VOLTAGE 0x13
1151#define PALMAS_LDOUSB_CTRL 0x14
1152#define PALMAS_LDOUSB_VOLTAGE 0x15
1153#define PALMAS_LDO_CTRL 0x1A
1154#define PALMAS_LDO_PD_CTRL1 0x1B
1155#define PALMAS_LDO_PD_CTRL2 0x1C
1156#define PALMAS_LDO_SHORT_STATUS1 0x1D
1157#define PALMAS_LDO_SHORT_STATUS2 0x1E
1158
1159/* Bit definitions for LDO1_CTRL */
1160#define PALMAS_LDO1_CTRL_WR_S 0x80
45ac60c0 1161#define PALMAS_LDO1_CTRL_WR_S_SHIFT 0x07
2945fbc2 1162#define PALMAS_LDO1_CTRL_STATUS 0x10
45ac60c0 1163#define PALMAS_LDO1_CTRL_STATUS_SHIFT 0x04
2945fbc2 1164#define PALMAS_LDO1_CTRL_MODE_SLEEP 0x04
45ac60c0 1165#define PALMAS_LDO1_CTRL_MODE_SLEEP_SHIFT 0x02
2945fbc2 1166#define PALMAS_LDO1_CTRL_MODE_ACTIVE 0x01
45ac60c0 1167#define PALMAS_LDO1_CTRL_MODE_ACTIVE_SHIFT 0x00
2945fbc2
GG		 1168
1169/* Bit definitions for LDO1_VOLTAGE */
45ac60c0
K		 1170#define PALMAS_LDO1_VOLTAGE_VSEL_MASK 0x3F
1171#define PALMAS_LDO1_VOLTAGE_VSEL_SHIFT 0x00
2945fbc2
GG		 1172
1173/* Bit definitions for LDO2_CTRL */
1174#define PALMAS_LDO2_CTRL_WR_S 0x80
45ac60c0 1175#define PALMAS_LDO2_CTRL_WR_S_SHIFT 0x07
2945fbc2 1176#define PALMAS_LDO2_CTRL_STATUS 0x10
45ac60c0 1177#define PALMAS_LDO2_CTRL_STATUS_SHIFT 0x04
2945fbc2 1178#define PALMAS_LDO2_CTRL_MODE_SLEEP 0x04
45ac60c0 1179#define PALMAS_LDO2_CTRL_MODE_SLEEP_SHIFT 0x02
2945fbc2 1180#define PALMAS_LDO2_CTRL_MODE_ACTIVE 0x01
45ac60c0 1181#define PALMAS_LDO2_CTRL_MODE_ACTIVE_SHIFT 0x00
2945fbc2
GG		 1182
1183/* Bit definitions for LDO2_VOLTAGE */
45ac60c0
K		 1184#define PALMAS_LDO2_VOLTAGE_VSEL_MASK 0x3F
1185#define PALMAS_LDO2_VOLTAGE_VSEL_SHIFT 0x00
2945fbc2
GG		 1186
1187/* Bit definitions for LDO3_CTRL */
1188#define PALMAS_LDO3_CTRL_WR_S 0x80
45ac60c0 1189#define PALMAS_LDO3_CTRL_WR_S_SHIFT 0x07
2945fbc2 1190#define PALMAS_LDO3_CTRL_STATUS 0x10
45ac60c0 1191#define PALMAS_LDO3_CTRL_STATUS_SHIFT 0x04
2945fbc2 1192#define PALMAS_LDO3_CTRL_MODE_SLEEP 0x04
45ac60c0 1193#define PALMAS_LDO3_CTRL_MODE_SLEEP_SHIFT 0x02
2945fbc2 1194#define PALMAS_LDO3_CTRL_MODE_ACTIVE 0x01
45ac60c0 1195#define PALMAS_LDO3_CTRL_MODE_ACTIVE_SHIFT 0x00
2945fbc2
GG		 1196
1197/* Bit definitions for LDO3_VOLTAGE */
45ac60c0
K		 1198#define PALMAS_LDO3_VOLTAGE_VSEL_MASK 0x3F
1199#define PALMAS_LDO3_VOLTAGE_VSEL_SHIFT 0x00
2945fbc2
GG		 1200
1201/* Bit definitions for LDO4_CTRL */
1202#define PALMAS_LDO4_CTRL_WR_S 0x80
45ac60c0 1203#define PALMAS_LDO4_CTRL_WR_S_SHIFT 0x07
2945fbc2 1204#define PALMAS_LDO4_CTRL_STATUS 0x10
45ac60c0 1205#define PALMAS_LDO4_CTRL_STATUS_SHIFT 0x04
2945fbc2 1206#define PALMAS_LDO4_CTRL_MODE_SLEEP 0x04
45ac60c0 1207#define PALMAS_LDO4_CTRL_MODE_SLEEP_SHIFT 0x02
2945fbc2 1208#define PALMAS_LDO4_CTRL_MODE_ACTIVE 0x01
45ac60c0 1209#define PALMAS_LDO4_CTRL_MODE_ACTIVE_SHIFT 0x00
2945fbc2
GG		 1210
1211/* Bit definitions for LDO4_VOLTAGE */
45ac60c0
K		 1212#define PALMAS_LDO4_VOLTAGE_VSEL_MASK 0x3F
1213#define PALMAS_LDO4_VOLTAGE_VSEL_SHIFT 0x00
2945fbc2
GG		 1214
1215/* Bit definitions for LDO5_CTRL */
1216#define PALMAS_LDO5_CTRL_WR_S 0x80
45ac60c0 1217#define PALMAS_LDO5_CTRL_WR_S_SHIFT 0x07
2945fbc2 1218#define PALMAS_LDO5_CTRL_STATUS 0x10
45ac60c0 1219#define PALMAS_LDO5_CTRL_STATUS_SHIFT 0x04
2945fbc2 1220#define PALMAS_LDO5_CTRL_MODE_SLEEP 0x04
45ac60c0 1221#define PALMAS_LDO5_CTRL_MODE_SLEEP_SHIFT 0x02
2945fbc2 1222#define PALMAS_LDO5_CTRL_MODE_ACTIVE 0x01
45ac60c0 1223#define PALMAS_LDO5_CTRL_MODE_ACTIVE_SHIFT 0x00
2945fbc2
GG		 1224
1225/* Bit definitions for LDO5_VOLTAGE */
45ac60c0
K		 1226#define PALMAS_LDO5_VOLTAGE_VSEL_MASK 0x3F
1227#define PALMAS_LDO5_VOLTAGE_VSEL_SHIFT 0x00
2945fbc2
GG		 1228
1229/* Bit definitions for LDO6_CTRL */
1230#define PALMAS_LDO6_CTRL_WR_S 0x80
45ac60c0 1231#define PALMAS_LDO6_CTRL_WR_S_SHIFT 0x07
2945fbc2 1232#define PALMAS_LDO6_CTRL_LDO_VIB_EN 0x40
45ac60c0 1233#define PALMAS_LDO6_CTRL_LDO_VIB_EN_SHIFT 0x06
2945fbc2 1234#define PALMAS_LDO6_CTRL_STATUS 0x10
45ac60c0 1235#define PALMAS_LDO6_CTRL_STATUS_SHIFT 0x04
2945fbc2 1236#define PALMAS_LDO6_CTRL_MODE_SLEEP 0x04
45ac60c0 1237#define PALMAS_LDO6_CTRL_MODE_SLEEP_SHIFT 0x02
2945fbc2 1238#define PALMAS_LDO6_CTRL_MODE_ACTIVE 0x01
45ac60c0 1239#define PALMAS_LDO6_CTRL_MODE_ACTIVE_SHIFT 0x00
2945fbc2
GG		 1240
1241/* Bit definitions for LDO6_VOLTAGE */
45ac60c0
K		 1242#define PALMAS_LDO6_VOLTAGE_VSEL_MASK 0x3F
1243#define PALMAS_LDO6_VOLTAGE_VSEL_SHIFT 0x00
2945fbc2
GG		 1244
1245/* Bit definitions for LDO7_CTRL */
1246#define PALMAS_LDO7_CTRL_WR_S 0x80
45ac60c0 1247#define PALMAS_LDO7_CTRL_WR_S_SHIFT 0x07
2945fbc2 1248#define PALMAS_LDO7_CTRL_STATUS 0x10
45ac60c0 1249#define PALMAS_LDO7_CTRL_STATUS_SHIFT 0x04
2945fbc2 1250#define PALMAS_LDO7_CTRL_MODE_SLEEP 0x04
45ac60c0 1251#define PALMAS_LDO7_CTRL_MODE_SLEEP_SHIFT 0x02
2945fbc2 1252#define PALMAS_LDO7_CTRL_MODE_ACTIVE 0x01
45ac60c0 1253#define PALMAS_LDO7_CTRL_MODE_ACTIVE_SHIFT 0x00
2945fbc2
GG		 1254
1255/* Bit definitions for LDO7_VOLTAGE */
45ac60c0
K		 1256#define PALMAS_LDO7_VOLTAGE_VSEL_MASK 0x3F
1257#define PALMAS_LDO7_VOLTAGE_VSEL_SHIFT 0x00
2945fbc2
GG		 1258
1259/* Bit definitions for LDO8_CTRL */
1260#define PALMAS_LDO8_CTRL_WR_S 0x80
45ac60c0 1261#define PALMAS_LDO8_CTRL_WR_S_SHIFT 0x07
2945fbc2 1262#define PALMAS_LDO8_CTRL_LDO_TRACKING_EN 0x40
45ac60c0 1263#define PALMAS_LDO8_CTRL_LDO_TRACKING_EN_SHIFT 0x06
2945fbc2 1264#define PALMAS_LDO8_CTRL_STATUS 0x10
45ac60c0 1265#define PALMAS_LDO8_CTRL_STATUS_SHIFT 0x04
2945fbc2 1266#define PALMAS_LDO8_CTRL_MODE_SLEEP 0x04
45ac60c0 1267#define PALMAS_LDO8_CTRL_MODE_SLEEP_SHIFT 0x02
2945fbc2 1268#define PALMAS_LDO8_CTRL_MODE_ACTIVE 0x01
45ac60c0 1269#define PALMAS_LDO8_CTRL_MODE_ACTIVE_SHIFT 0x00
2945fbc2
GG		 1270
1271/* Bit definitions for LDO8_VOLTAGE */
45ac60c0
K		 1272#define PALMAS_LDO8_VOLTAGE_VSEL_MASK 0x3F
1273#define PALMAS_LDO8_VOLTAGE_VSEL_SHIFT 0x00
2945fbc2
GG		 1274
1275/* Bit definitions for LDO9_CTRL */
1276#define PALMAS_LDO9_CTRL_WR_S 0x80
45ac60c0 1277#define PALMAS_LDO9_CTRL_WR_S_SHIFT 0x07
2945fbc2 1278#define PALMAS_LDO9_CTRL_LDO_BYPASS_EN 0x40
45ac60c0 1279#define PALMAS_LDO9_CTRL_LDO_BYPASS_EN_SHIFT 0x06
2945fbc2 1280#define PALMAS_LDO9_CTRL_STATUS 0x10
45ac60c0 1281#define PALMAS_LDO9_CTRL_STATUS_SHIFT 0x04
2945fbc2 1282#define PALMAS_LDO9_CTRL_MODE_SLEEP 0x04
45ac60c0 1283#define PALMAS_LDO9_CTRL_MODE_SLEEP_SHIFT 0x02
2945fbc2 1284#define PALMAS_LDO9_CTRL_MODE_ACTIVE 0x01
45ac60c0 1285#define PALMAS_LDO9_CTRL_MODE_ACTIVE_SHIFT 0x00
2945fbc2
GG		 1286
1287/* Bit definitions for LDO9_VOLTAGE */
45ac60c0
K		 1288#define PALMAS_LDO9_VOLTAGE_VSEL_MASK 0x3F
1289#define PALMAS_LDO9_VOLTAGE_VSEL_SHIFT 0x00
2945fbc2
GG		 1290
1291/* Bit definitions for LDOLN_CTRL */
1292#define PALMAS_LDOLN_CTRL_WR_S 0x80
45ac60c0 1293#define PALMAS_LDOLN_CTRL_WR_S_SHIFT 0x07
2945fbc2 1294#define PALMAS_LDOLN_CTRL_STATUS 0x10
45ac60c0 1295#define PALMAS_LDOLN_CTRL_STATUS_SHIFT 0x04
2945fbc2 1296#define PALMAS_LDOLN_CTRL_MODE_SLEEP 0x04
45ac60c0 1297#define PALMAS_LDOLN_CTRL_MODE_SLEEP_SHIFT 0x02
2945fbc2 1298#define PALMAS_LDOLN_CTRL_MODE_ACTIVE 0x01
45ac60c0 1299#define PALMAS_LDOLN_CTRL_MODE_ACTIVE_SHIFT 0x00
2945fbc2
GG		 1300
1301/* Bit definitions for LDOLN_VOLTAGE */
45ac60c0
K		 1302#define PALMAS_LDOLN_VOLTAGE_VSEL_MASK 0x3F
1303#define PALMAS_LDOLN_VOLTAGE_VSEL_SHIFT 0x00
2945fbc2
GG		 1304
1305/* Bit definitions for LDOUSB_CTRL */
1306#define PALMAS_LDOUSB_CTRL_WR_S 0x80
45ac60c0 1307#define PALMAS_LDOUSB_CTRL_WR_S_SHIFT 0x07
2945fbc2 1308#define PALMAS_LDOUSB_CTRL_STATUS 0x10
45ac60c0 1309#define PALMAS_LDOUSB_CTRL_STATUS_SHIFT 0x04
2945fbc2 1310#define PALMAS_LDOUSB_CTRL_MODE_SLEEP 0x04
45ac60c0 1311#define PALMAS_LDOUSB_CTRL_MODE_SLEEP_SHIFT 0x02
2945fbc2 1312#define PALMAS_LDOUSB_CTRL_MODE_ACTIVE 0x01
45ac60c0 1313#define PALMAS_LDOUSB_CTRL_MODE_ACTIVE_SHIFT 0x00
2945fbc2
GG		 1314
1315/* Bit definitions for LDOUSB_VOLTAGE */
45ac60c0
K		 1316#define PALMAS_LDOUSB_VOLTAGE_VSEL_MASK 0x3F
1317#define PALMAS_LDOUSB_VOLTAGE_VSEL_SHIFT 0x00
2945fbc2
GG		 1318
1319/* Bit definitions for LDO_CTRL */
1320#define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS 0x01
45ac60c0 1321#define PALMAS_LDO_CTRL_LDOUSB_ON_VBUS_VSYS_SHIFT 0x00
2945fbc2
GG		 1322
1323/* Bit definitions for LDO_PD_CTRL1 */
1324#define PALMAS_LDO_PD_CTRL1_LDO8 0x80
45ac60c0 1325#define PALMAS_LDO_PD_CTRL1_LDO8_SHIFT 0x07
2945fbc2 1326#define PALMAS_LDO_PD_CTRL1_LDO7 0x40
45ac60c0 1327#define PALMAS_LDO_PD_CTRL1_LDO7_SHIFT 0x06
2945fbc2 1328#define PALMAS_LDO_PD_CTRL1_LDO6 0x20
45ac60c0 1329#define PALMAS_LDO_PD_CTRL1_LDO6_SHIFT 0x05
2945fbc2 1330#define PALMAS_LDO_PD_CTRL1_LDO5 0x10
45ac60c0 1331#define PALMAS_LDO_PD_CTRL1_LDO5_SHIFT 0x04
2945fbc2 1332#define PALMAS_LDO_PD_CTRL1_LDO4 0x08
45ac60c0 1333#define PALMAS_LDO_PD_CTRL1_LDO4_SHIFT 0x03
2945fbc2 1334#define PALMAS_LDO_PD_CTRL1_LDO3 0x04
45ac60c0 1335#define PALMAS_LDO_PD_CTRL1_LDO3_SHIFT 0x02
2945fbc2 1336#define PALMAS_LDO_PD_CTRL1_LDO2 0x02
45ac60c0 1337#define PALMAS_LDO_PD_CTRL1_LDO2_SHIFT 0x01
2945fbc2 1338#define PALMAS_LDO_PD_CTRL1_LDO1 0x01
45ac60c0 1339#define PALMAS_LDO_PD_CTRL1_LDO1_SHIFT 0x00
2945fbc2
GG		 1340
1341/* Bit definitions for LDO_PD_CTRL2 */
1342#define PALMAS_LDO_PD_CTRL2_LDOUSB 0x04
45ac60c0 1343#define PALMAS_LDO_PD_CTRL2_LDOUSB_SHIFT 0x02
2945fbc2 1344#define PALMAS_LDO_PD_CTRL2_LDOLN 0x02
45ac60c0 1345#define PALMAS_LDO_PD_CTRL2_LDOLN_SHIFT 0x01
2945fbc2 1346#define PALMAS_LDO_PD_CTRL2_LDO9 0x01
45ac60c0 1347#define PALMAS_LDO_PD_CTRL2_LDO9_SHIFT 0x00
2945fbc2
GG		 1348
1349/* Bit definitions for LDO_SHORT_STATUS1 */
1350#define PALMAS_LDO_SHORT_STATUS1_LDO8 0x80
45ac60c0 1351#define PALMAS_LDO_SHORT_STATUS1_LDO8_SHIFT 0x07
2945fbc2 1352#define PALMAS_LDO_SHORT_STATUS1_LDO7 0x40
45ac60c0 1353#define PALMAS_LDO_SHORT_STATUS1_LDO7_SHIFT 0x06
2945fbc2 1354#define PALMAS_LDO_SHORT_STATUS1_LDO6 0x20
45ac60c0 1355#define PALMAS_LDO_SHORT_STATUS1_LDO6_SHIFT 0x05
2945fbc2 1356#define PALMAS_LDO_SHORT_STATUS1_LDO5 0x10
45ac60c0 1357#define PALMAS_LDO_SHORT_STATUS1_LDO5_SHIFT 0x04
2945fbc2 1358#define PALMAS_LDO_SHORT_STATUS1_LDO4 0x08
45ac60c0 1359#define PALMAS_LDO_SHORT_STATUS1_LDO4_SHIFT 0x03
2945fbc2 1360#define PALMAS_LDO_SHORT_STATUS1_LDO3 0x04
45ac60c0 1361#define PALMAS_LDO_SHORT_STATUS1_LDO3_SHIFT 0x02
2945fbc2 1362#define PALMAS_LDO_SHORT_STATUS1_LDO2 0x02
45ac60c0 1363#define PALMAS_LDO_SHORT_STATUS1_LDO2_SHIFT 0x01
2945fbc2 1364#define PALMAS_LDO_SHORT_STATUS1_LDO1 0x01
45ac60c0 1365#define PALMAS_LDO_SHORT_STATUS1_LDO1_SHIFT 0x00
2945fbc2
GG		 1366
1367/* Bit definitions for LDO_SHORT_STATUS2 */
1368#define PALMAS_LDO_SHORT_STATUS2_LDOVANA 0x08
45ac60c0 1369#define PALMAS_LDO_SHORT_STATUS2_LDOVANA_SHIFT 0x03
2945fbc2 1370#define PALMAS_LDO_SHORT_STATUS2_LDOUSB 0x04
45ac60c0 1371#define PALMAS_LDO_SHORT_STATUS2_LDOUSB_SHIFT 0x02
2945fbc2 1372#define PALMAS_LDO_SHORT_STATUS2_LDOLN 0x02
45ac60c0 1373#define PALMAS_LDO_SHORT_STATUS2_LDOLN_SHIFT 0x01
2945fbc2 1374#define PALMAS_LDO_SHORT_STATUS2_LDO9 0x01
45ac60c0 1375#define PALMAS_LDO_SHORT_STATUS2_LDO9_SHIFT 0x00
2945fbc2
GG		 1376
1377/* Registers for function PMU_CONTROL */
45ac60c0
K		 1378#define PALMAS_DEV_CTRL 0x00
1379#define PALMAS_POWER_CTRL 0x01
1380#define PALMAS_VSYS_LO 0x02
1381#define PALMAS_VSYS_MON 0x03
1382#define PALMAS_VBAT_MON 0x04
1383#define PALMAS_WATCHDOG 0x05
1384#define PALMAS_BOOT_STATUS 0x06
1385#define PALMAS_BATTERY_BOUNCE 0x07
1386#define PALMAS_BACKUP_BATTERY_CTRL 0x08
1387#define PALMAS_LONG_PRESS_KEY 0x09
1388#define PALMAS_OSC_THERM_CTRL 0x0A
1389#define PALMAS_BATDEBOUNCING 0x0B
1390#define PALMAS_SWOFF_HWRST 0x0F
2945fbc2
GG		 1391#define PALMAS_SWOFF_COLDRST 0x10
1392#define PALMAS_SWOFF_STATUS 0x11
1393#define PALMAS_PMU_CONFIG 0x12
1394#define PALMAS_SPARE 0x14
1395#define PALMAS_PMU_SECONDARY_INT 0x15
1396#define PALMAS_SW_REVISION 0x17
1397#define PALMAS_EXT_CHRG_CTRL 0x18
1398#define PALMAS_PMU_SECONDARY_INT2 0x19
1399
1400/* Bit definitions for DEV_CTRL */
1401#define PALMAS_DEV_CTRL_DEV_STATUS_MASK 0x0c
45ac60c0 1402#define PALMAS_DEV_CTRL_DEV_STATUS_SHIFT 0x02
2945fbc2 1403#define PALMAS_DEV_CTRL_SW_RST 0x02
45ac60c0 1404#define PALMAS_DEV_CTRL_SW_RST_SHIFT 0x01
2945fbc2 1405#define PALMAS_DEV_CTRL_DEV_ON 0x01
45ac60c0 1406#define PALMAS_DEV_CTRL_DEV_ON_SHIFT 0x00
2945fbc2
GG		 1407
1408/* Bit definitions for POWER_CTRL */
1409#define PALMAS_POWER_CTRL_ENABLE2_MASK 0x04
45ac60c0 1410#define PALMAS_POWER_CTRL_ENABLE2_MASK_SHIFT 0x02
2945fbc2 1411#define PALMAS_POWER_CTRL_ENABLE1_MASK 0x02
45ac60c0 1412#define PALMAS_POWER_CTRL_ENABLE1_MASK_SHIFT 0x01
2945fbc2 1413#define PALMAS_POWER_CTRL_NSLEEP_MASK 0x01
45ac60c0 1414#define PALMAS_POWER_CTRL_NSLEEP_MASK_SHIFT 0x00
2945fbc2
GG		 1415
1416/* Bit definitions for VSYS_LO */
45ac60c0
K		 1417#define PALMAS_VSYS_LO_THRESHOLD_MASK 0x1F
1418#define PALMAS_VSYS_LO_THRESHOLD_SHIFT 0x00
2945fbc2
GG		 1419
1420/* Bit definitions for VSYS_MON */
1421#define PALMAS_VSYS_MON_ENABLE 0x80
45ac60c0
K		 1422#define PALMAS_VSYS_MON_ENABLE_SHIFT 0x07
1423#define PALMAS_VSYS_MON_THRESHOLD_MASK 0x3F
1424#define PALMAS_VSYS_MON_THRESHOLD_SHIFT 0x00
2945fbc2
GG		 1425
1426/* Bit definitions for VBAT_MON */
1427#define PALMAS_VBAT_MON_ENABLE 0x80
45ac60c0
K		 1428#define PALMAS_VBAT_MON_ENABLE_SHIFT 0x07
1429#define PALMAS_VBAT_MON_THRESHOLD_MASK 0x3F
1430#define PALMAS_VBAT_MON_THRESHOLD_SHIFT 0x00
2945fbc2
GG		 1431
1432/* Bit definitions for WATCHDOG */
1433#define PALMAS_WATCHDOG_LOCK 0x20
45ac60c0 1434#define PALMAS_WATCHDOG_LOCK_SHIFT 0x05
2945fbc2 1435#define PALMAS_WATCHDOG_ENABLE 0x10
45ac60c0 1436#define PALMAS_WATCHDOG_ENABLE_SHIFT 0x04
2945fbc2 1437#define PALMAS_WATCHDOG_MODE 0x08
45ac60c0 1438#define PALMAS_WATCHDOG_MODE_SHIFT 0x03
2945fbc2 1439#define PALMAS_WATCHDOG_TIMER_MASK 0x07
45ac60c0 1440#define PALMAS_WATCHDOG_TIMER_SHIFT 0x00
2945fbc2
GG		 1441
1442/* Bit definitions for BOOT_STATUS */
1443#define PALMAS_BOOT_STATUS_BOOT1 0x02
45ac60c0 1444#define PALMAS_BOOT_STATUS_BOOT1_SHIFT 0x01
2945fbc2 1445#define PALMAS_BOOT_STATUS_BOOT0 0x01
45ac60c0 1446#define PALMAS_BOOT_STATUS_BOOT0_SHIFT 0x00
2945fbc2
GG		 1447
1448/* Bit definitions for BATTERY_BOUNCE */
45ac60c0
K		 1449#define PALMAS_BATTERY_BOUNCE_BB_DELAY_MASK 0x3F
1450#define PALMAS_BATTERY_BOUNCE_BB_DELAY_SHIFT 0x00
2945fbc2
GG		 1451
1452/* Bit definitions for BACKUP_BATTERY_CTRL */
1453#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15 0x80
45ac60c0 1454#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_18_15_SHIFT 0x07
2945fbc2 1455#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP 0x40
45ac60c0 1456#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_SLP_SHIFT 0x06
2945fbc2 1457#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF 0x20
45ac60c0 1458#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_EN_OFF_SHIFT 0x05
2945fbc2 1459#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN 0x10
45ac60c0 1460#define PALMAS_BACKUP_BATTERY_CTRL_VRTC_PWEN_SHIFT 0x04
2945fbc2 1461#define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG 0x08
45ac60c0 1462#define PALMAS_BACKUP_BATTERY_CTRL_BBS_BBC_LOW_ICHRG_SHIFT 0x03
2945fbc2 1463#define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_MASK 0x06
45ac60c0 1464#define PALMAS_BACKUP_BATTERY_CTRL_BB_SEL_SHIFT 0x01
2945fbc2 1465#define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN 0x01
45ac60c0 1466#define PALMAS_BACKUP_BATTERY_CTRL_BB_CHG_EN_SHIFT 0x00
2945fbc2
GG		 1467
1468/* Bit definitions for LONG_PRESS_KEY */
1469#define PALMAS_LONG_PRESS_KEY_LPK_LOCK 0x80
45ac60c0 1470#define PALMAS_LONG_PRESS_KEY_LPK_LOCK_SHIFT 0x07
2945fbc2 1471#define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR 0x10
45ac60c0 1472#define PALMAS_LONG_PRESS_KEY_LPK_INT_CLR_SHIFT 0x04
2945fbc2 1473#define PALMAS_LONG_PRESS_KEY_LPK_TIME_MASK 0x0c
45ac60c0 1474#define PALMAS_LONG_PRESS_KEY_LPK_TIME_SHIFT 0x02
2945fbc2 1475#define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_MASK 0x03
45ac60c0 1476#define PALMAS_LONG_PRESS_KEY_PWRON_DEBOUNCE_SHIFT 0x00
2945fbc2
GG		 1477
1478/* Bit definitions for OSC_THERM_CTRL */
1479#define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP 0x80
45ac60c0 1480#define PALMAS_OSC_THERM_CTRL_VANA_ON_IN_SLEEP_SHIFT 0x07
2945fbc2 1481#define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP 0x40
45ac60c0 1482#define PALMAS_OSC_THERM_CTRL_INT_MASK_IN_SLEEP_SHIFT 0x06
2945fbc2 1483#define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP 0x20
45ac60c0 1484#define PALMAS_OSC_THERM_CTRL_RC15MHZ_ON_IN_SLEEP_SHIFT 0x05
2945fbc2 1485#define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP 0x10
45ac60c0 1486#define PALMAS_OSC_THERM_CTRL_THERM_OFF_IN_SLEEP_SHIFT 0x04
2945fbc2 1487#define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_MASK 0x0c
45ac60c0 1488#define PALMAS_OSC_THERM_CTRL_THERM_HD_SEL_SHIFT 0x02
2945fbc2 1489#define PALMAS_OSC_THERM_CTRL_OSC_BYPASS 0x02
45ac60c0 1490#define PALMAS_OSC_THERM_CTRL_OSC_BYPASS_SHIFT 0x01
2945fbc2 1491#define PALMAS_OSC_THERM_CTRL_OSC_HPMODE 0x01
45ac60c0 1492#define PALMAS_OSC_THERM_CTRL_OSC_HPMODE_SHIFT 0x00
2945fbc2
GG		 1493
1494/* Bit definitions for BATDEBOUNCING */
1495#define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS 0x80
45ac60c0 1496#define PALMAS_BATDEBOUNCING_BAT_DEB_BYPASS_SHIFT 0x07
2945fbc2 1497#define PALMAS_BATDEBOUNCING_BINS_DEB_MASK 0x78
45ac60c0 1498#define PALMAS_BATDEBOUNCING_BINS_DEB_SHIFT 0x03
2945fbc2 1499#define PALMAS_BATDEBOUNCING_BEXT_DEB_MASK 0x07
45ac60c0 1500#define PALMAS_BATDEBOUNCING_BEXT_DEB_SHIFT 0x00
2945fbc2
GG		 1501
1502/* Bit definitions for SWOFF_HWRST */
1503#define PALMAS_SWOFF_HWRST_PWRON_LPK 0x80
45ac60c0 1504#define PALMAS_SWOFF_HWRST_PWRON_LPK_SHIFT 0x07
2945fbc2 1505#define PALMAS_SWOFF_HWRST_PWRDOWN 0x40
45ac60c0 1506#define PALMAS_SWOFF_HWRST_PWRDOWN_SHIFT 0x06
2945fbc2 1507#define PALMAS_SWOFF_HWRST_WTD 0x20
45ac60c0 1508#define PALMAS_SWOFF_HWRST_WTD_SHIFT 0x05
2945fbc2 1509#define PALMAS_SWOFF_HWRST_TSHUT 0x10
45ac60c0 1510#define PALMAS_SWOFF_HWRST_TSHUT_SHIFT 0x04
2945fbc2 1511#define PALMAS_SWOFF_HWRST_RESET_IN 0x08
45ac60c0 1512#define PALMAS_SWOFF_HWRST_RESET_IN_SHIFT 0x03
2945fbc2 1513#define PALMAS_SWOFF_HWRST_SW_RST 0x04
45ac60c0 1514#define PALMAS_SWOFF_HWRST_SW_RST_SHIFT 0x02
2945fbc2 1515#define PALMAS_SWOFF_HWRST_VSYS_LO 0x02
45ac60c0 1516#define PALMAS_SWOFF_HWRST_VSYS_LO_SHIFT 0x01
2945fbc2 1517#define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN 0x01
45ac60c0 1518#define PALMAS_SWOFF_HWRST_GPADC_SHUTDOWN_SHIFT 0x00
2945fbc2
GG		 1519
1520/* Bit definitions for SWOFF_COLDRST */
1521#define PALMAS_SWOFF_COLDRST_PWRON_LPK 0x80
45ac60c0 1522#define PALMAS_SWOFF_COLDRST_PWRON_LPK_SHIFT 0x07
2945fbc2 1523#define PALMAS_SWOFF_COLDRST_PWRDOWN 0x40
45ac60c0 1524#define PALMAS_SWOFF_COLDRST_PWRDOWN_SHIFT 0x06
2945fbc2 1525#define PALMAS_SWOFF_COLDRST_WTD 0x20
45ac60c0 1526#define PALMAS_SWOFF_COLDRST_WTD_SHIFT 0x05
2945fbc2 1527#define PALMAS_SWOFF_COLDRST_TSHUT 0x10
45ac60c0 1528#define PALMAS_SWOFF_COLDRST_TSHUT_SHIFT 0x04
2945fbc2 1529#define PALMAS_SWOFF_COLDRST_RESET_IN 0x08
45ac60c0 1530#define PALMAS_SWOFF_COLDRST_RESET_IN_SHIFT 0x03
2945fbc2 1531#define PALMAS_SWOFF_COLDRST_SW_RST 0x04
45ac60c0 1532#define PALMAS_SWOFF_COLDRST_SW_RST_SHIFT 0x02
2945fbc2 1533#define PALMAS_SWOFF_COLDRST_VSYS_LO 0x02
45ac60c0 1534#define PALMAS_SWOFF_COLDRST_VSYS_LO_SHIFT 0x01
2945fbc2 1535#define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN 0x01
45ac60c0 1536#define PALMAS_SWOFF_COLDRST_GPADC_SHUTDOWN_SHIFT 0x00
2945fbc2
GG		 1537
1538/* Bit definitions for SWOFF_STATUS */
1539#define PALMAS_SWOFF_STATUS_PWRON_LPK 0x80
45ac60c0 1540#define PALMAS_SWOFF_STATUS_PWRON_LPK_SHIFT 0x07
2945fbc2 1541#define PALMAS_SWOFF_STATUS_PWRDOWN 0x40
45ac60c0 1542#define PALMAS_SWOFF_STATUS_PWRDOWN_SHIFT 0x06
2945fbc2 1543#define PALMAS_SWOFF_STATUS_WTD 0x20
45ac60c0 1544#define PALMAS_SWOFF_STATUS_WTD_SHIFT 0x05
2945fbc2 1545#define PALMAS_SWOFF_STATUS_TSHUT 0x10
45ac60c0 1546#define PALMAS_SWOFF_STATUS_TSHUT_SHIFT 0x04
2945fbc2 1547#define PALMAS_SWOFF_STATUS_RESET_IN 0x08
45ac60c0 1548#define PALMAS_SWOFF_STATUS_RESET_IN_SHIFT 0x03
2945fbc2 1549#define PALMAS_SWOFF_STATUS_SW_RST 0x04
45ac60c0 1550#define PALMAS_SWOFF_STATUS_SW_RST_SHIFT 0x02
2945fbc2 1551#define PALMAS_SWOFF_STATUS_VSYS_LO 0x02
45ac60c0 1552#define PALMAS_SWOFF_STATUS_VSYS_LO_SHIFT 0x01
2945fbc2 1553#define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN 0x01
45ac60c0 1554#define PALMAS_SWOFF_STATUS_GPADC_SHUTDOWN_SHIFT 0x00
2945fbc2
GG		 1555
1556/* Bit definitions for PMU_CONFIG */
1557#define PALMAS_PMU_CONFIG_MULTI_CELL_EN 0x40
45ac60c0 1558#define PALMAS_PMU_CONFIG_MULTI_CELL_EN_SHIFT 0x06
2945fbc2 1559#define PALMAS_PMU_CONFIG_SPARE_MASK 0x30
45ac60c0 1560#define PALMAS_PMU_CONFIG_SPARE_SHIFT 0x04
2945fbc2 1561#define PALMAS_PMU_CONFIG_SWOFF_DLY_MASK 0x0c
45ac60c0 1562#define PALMAS_PMU_CONFIG_SWOFF_DLY_SHIFT 0x02
2945fbc2 1563#define PALMAS_PMU_CONFIG_GATE_RESET_OUT 0x02
45ac60c0 1564#define PALMAS_PMU_CONFIG_GATE_RESET_OUT_SHIFT 0x01
2945fbc2 1565#define PALMAS_PMU_CONFIG_AUTODEVON 0x01
45ac60c0 1566#define PALMAS_PMU_CONFIG_AUTODEVON_SHIFT 0x00
2945fbc2
GG		 1567
1568/* Bit definitions for SPARE */
1569#define PALMAS_SPARE_SPARE_MASK 0xf8
45ac60c0 1570#define PALMAS_SPARE_SPARE_SHIFT 0x03
2945fbc2 1571#define PALMAS_SPARE_REGEN3_OD 0x04
45ac60c0 1572#define PALMAS_SPARE_REGEN3_OD_SHIFT 0x02
2945fbc2 1573#define PALMAS_SPARE_REGEN2_OD 0x02
45ac60c0 1574#define PALMAS_SPARE_REGEN2_OD_SHIFT 0x01
2945fbc2 1575#define PALMAS_SPARE_REGEN1_OD 0x01
45ac60c0 1576#define PALMAS_SPARE_REGEN1_OD_SHIFT 0x00
2945fbc2
GG		 1577
1578/* Bit definitions for PMU_SECONDARY_INT */
1579#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC 0x80
45ac60c0 1580#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_INT_SRC_SHIFT 0x07
2945fbc2 1581#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC 0x40
45ac60c0 1582#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_INT_SRC_SHIFT 0x06
2945fbc2 1583#define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC 0x20
45ac60c0 1584#define PALMAS_PMU_SECONDARY_INT_BB_INT_SRC_SHIFT 0x05
2945fbc2 1585#define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC 0x10
45ac60c0 1586#define PALMAS_PMU_SECONDARY_INT_FBI_INT_SRC_SHIFT 0x04
2945fbc2 1587#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK 0x08
45ac60c0 1588#define PALMAS_PMU_SECONDARY_INT_VBUS_OVV_MASK_SHIFT 0x03
2945fbc2 1589#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK 0x04
45ac60c0 1590#define PALMAS_PMU_SECONDARY_INT_CHARG_DET_N_MASK_SHIFT 0x02
2945fbc2 1591#define PALMAS_PMU_SECONDARY_INT_BB_MASK 0x02
45ac60c0 1592#define PALMAS_PMU_SECONDARY_INT_BB_MASK_SHIFT 0x01
2945fbc2 1593#define PALMAS_PMU_SECONDARY_INT_FBI_MASK 0x01
45ac60c0 1594#define PALMAS_PMU_SECONDARY_INT_FBI_MASK_SHIFT 0x00
2945fbc2
GG		 1595
1596/* Bit definitions for SW_REVISION */
45ac60c0
K		 1597#define PALMAS_SW_REVISION_SW_REVISION_MASK 0xFF
1598#define PALMAS_SW_REVISION_SW_REVISION_SHIFT 0x00
2945fbc2
GG		 1599
1600/* Bit definitions for EXT_CHRG_CTRL */
1601#define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS 0x80
45ac60c0 1602#define PALMAS_EXT_CHRG_CTRL_VBUS_OVV_STATUS_SHIFT 0x07
2945fbc2 1603#define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS 0x40
45ac60c0 1604#define PALMAS_EXT_CHRG_CTRL_CHARG_DET_N_STATUS_SHIFT 0x06
2945fbc2 1605#define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY 0x08
45ac60c0 1606#define PALMAS_EXT_CHRG_CTRL_VSYS_DEBOUNCE_DELAY_SHIFT 0x03
2945fbc2 1607#define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N 0x04
45ac60c0 1608#define PALMAS_EXT_CHRG_CTRL_CHRG_DET_N_SHIFT 0x02
2945fbc2 1609#define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN 0x02
45ac60c0 1610#define PALMAS_EXT_CHRG_CTRL_AUTO_ACA_EN_SHIFT 0x01
2945fbc2 1611#define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN 0x01
45ac60c0 1612#define PALMAS_EXT_CHRG_CTRL_AUTO_LDOUSB_EN_SHIFT 0x00
2945fbc2
GG		 1613
1614/* Bit definitions for PMU_SECONDARY_INT2 */
1615#define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC 0x20
45ac60c0 1616#define PALMAS_PMU_SECONDARY_INT2_DVFS2_INT_SRC_SHIFT 0x05
2945fbc2 1617#define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC 0x10
45ac60c0 1618#define PALMAS_PMU_SECONDARY_INT2_DVFS1_INT_SRC_SHIFT 0x04
2945fbc2 1619#define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK 0x02
45ac60c0 1620#define PALMAS_PMU_SECONDARY_INT2_DVFS2_MASK_SHIFT 0x01
2945fbc2 1621#define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK 0x01
45ac60c0 1622#define PALMAS_PMU_SECONDARY_INT2_DVFS1_MASK_SHIFT 0x00
2945fbc2
GG		 1623
1624/* Registers for function RESOURCE */
45ac60c0
K		 1625#define PALMAS_CLK32KG_CTRL 0x00
1626#define PALMAS_CLK32KGAUDIO_CTRL 0x01
1627#define PALMAS_REGEN1_CTRL 0x02
1628#define PALMAS_REGEN2_CTRL 0x03
1629#define PALMAS_SYSEN1_CTRL 0x04
1630#define PALMAS_SYSEN2_CTRL 0x05
1631#define PALMAS_NSLEEP_RES_ASSIGN 0x06
1632#define PALMAS_NSLEEP_SMPS_ASSIGN 0x07
1633#define PALMAS_NSLEEP_LDO_ASSIGN1 0x08
1634#define PALMAS_NSLEEP_LDO_ASSIGN2 0x09
1635#define PALMAS_ENABLE1_RES_ASSIGN 0x0A
1636#define PALMAS_ENABLE1_SMPS_ASSIGN 0x0B
1637#define PALMAS_ENABLE1_LDO_ASSIGN1 0x0C
1638#define PALMAS_ENABLE1_LDO_ASSIGN2 0x0D
1639#define PALMAS_ENABLE2_RES_ASSIGN 0x0E
1640#define PALMAS_ENABLE2_SMPS_ASSIGN 0x0F
2945fbc2
GG		 1641#define PALMAS_ENABLE2_LDO_ASSIGN1 0x10
1642#define PALMAS_ENABLE2_LDO_ASSIGN2 0x11
1643#define PALMAS_REGEN3_CTRL 0x12
1644
1645/* Bit definitions for CLK32KG_CTRL */
1646#define PALMAS_CLK32KG_CTRL_STATUS 0x10
45ac60c0 1647#define PALMAS_CLK32KG_CTRL_STATUS_SHIFT 0x04
2945fbc2 1648#define PALMAS_CLK32KG_CTRL_MODE_SLEEP 0x04
45ac60c0 1649#define PALMAS_CLK32KG_CTRL_MODE_SLEEP_SHIFT 0x02
2945fbc2 1650#define PALMAS_CLK32KG_CTRL_MODE_ACTIVE 0x01
45ac60c0 1651#define PALMAS_CLK32KG_CTRL_MODE_ACTIVE_SHIFT 0x00
2945fbc2
GG		 1652
1653/* Bit definitions for CLK32KGAUDIO_CTRL */
1654#define PALMAS_CLK32KGAUDIO_CTRL_STATUS 0x10
45ac60c0 1655#define PALMAS_CLK32KGAUDIO_CTRL_STATUS_SHIFT 0x04
2945fbc2 1656#define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3 0x08
45ac60c0 1657#define PALMAS_CLK32KGAUDIO_CTRL_RESERVED3_SHIFT 0x03
2945fbc2 1658#define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP 0x04
45ac60c0 1659#define PALMAS_CLK32KGAUDIO_CTRL_MODE_SLEEP_SHIFT 0x02
2945fbc2 1660#define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE 0x01
45ac60c0 1661#define PALMAS_CLK32KGAUDIO_CTRL_MODE_ACTIVE_SHIFT 0x00
2945fbc2
GG		 1662
1663/* Bit definitions for REGEN1_CTRL */
1664#define PALMAS_REGEN1_CTRL_STATUS 0x10
45ac60c0 1665#define PALMAS_REGEN1_CTRL_STATUS_SHIFT 0x04
2945fbc2 1666#define PALMAS_REGEN1_CTRL_MODE_SLEEP 0x04
45ac60c0 1667#define PALMAS_REGEN1_CTRL_MODE_SLEEP_SHIFT 0x02
2945fbc2 1668#define PALMAS_REGEN1_CTRL_MODE_ACTIVE 0x01
45ac60c0 1669#define PALMAS_REGEN1_CTRL_MODE_ACTIVE_SHIFT 0x00
2945fbc2
GG		 1670
1671/* Bit definitions for REGEN2_CTRL */
1672#define PALMAS_REGEN2_CTRL_STATUS 0x10
45ac60c0 1673#define PALMAS_REGEN2_CTRL_STATUS_SHIFT 0x04
2945fbc2 1674#define PALMAS_REGEN2_CTRL_MODE_SLEEP 0x04
45ac60c0 1675#define PALMAS_REGEN2_CTRL_MODE_SLEEP_SHIFT 0x02
2945fbc2 1676#define PALMAS_REGEN2_CTRL_MODE_ACTIVE 0x01
45ac60c0 1677#define PALMAS_REGEN2_CTRL_MODE_ACTIVE_SHIFT 0x00
2945fbc2
GG		 1678
1679/* Bit definitions for SYSEN1_CTRL */
1680#define PALMAS_SYSEN1_CTRL_STATUS 0x10
45ac60c0 1681#define PALMAS_SYSEN1_CTRL_STATUS_SHIFT 0x04
2945fbc2 1682#define PALMAS_SYSEN1_CTRL_MODE_SLEEP 0x04
45ac60c0 1683#define PALMAS_SYSEN1_CTRL_MODE_SLEEP_SHIFT 0x02
2945fbc2 1684#define PALMAS_SYSEN1_CTRL_MODE_ACTIVE 0x01
45ac60c0 1685#define PALMAS_SYSEN1_CTRL_MODE_ACTIVE_SHIFT 0x00
2945fbc2
GG		 1686
1687/* Bit definitions for SYSEN2_CTRL */
1688#define PALMAS_SYSEN2_CTRL_STATUS 0x10
45ac60c0 1689#define PALMAS_SYSEN2_CTRL_STATUS_SHIFT 0x04
2945fbc2 1690#define PALMAS_SYSEN2_CTRL_MODE_SLEEP 0x04
45ac60c0 1691#define PALMAS_SYSEN2_CTRL_MODE_SLEEP_SHIFT 0x02
2945fbc2 1692#define PALMAS_SYSEN2_CTRL_MODE_ACTIVE 0x01
45ac60c0 1693#define PALMAS_SYSEN2_CTRL_MODE_ACTIVE_SHIFT 0x00
2945fbc2
GG		 1694
1695/* Bit definitions for NSLEEP_RES_ASSIGN */
1696#define PALMAS_NSLEEP_RES_ASSIGN_REGEN3 0x40
45ac60c0 1697#define PALMAS_NSLEEP_RES_ASSIGN_REGEN3_SHIFT 0x06
2945fbc2 1698#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO 0x20
45ac60c0 1699#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KGAUDIO_SHIFT 0x05
2945fbc2 1700#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG 0x10
45ac60c0 1701#define PALMAS_NSLEEP_RES_ASSIGN_CLK32KG_SHIFT 0x04
2945fbc2 1702#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2 0x08
45ac60c0 1703#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN2_SHIFT 0x03
2945fbc2 1704#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1 0x04
45ac60c0 1705#define PALMAS_NSLEEP_RES_ASSIGN_SYSEN1_SHIFT 0x02
2945fbc2 1706#define PALMAS_NSLEEP_RES_ASSIGN_REGEN2 0x02
45ac60c0 1707#define PALMAS_NSLEEP_RES_ASSIGN_REGEN2_SHIFT 0x01
2945fbc2 1708#define PALMAS_NSLEEP_RES_ASSIGN_REGEN1 0x01
45ac60c0 1709#define PALMAS_NSLEEP_RES_ASSIGN_REGEN1_SHIFT 0x00
2945fbc2
GG		 1710
1711/* Bit definitions for NSLEEP_SMPS_ASSIGN */
1712#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10 0x80
45ac60c0 1713#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS10_SHIFT 0x07
2945fbc2 1714#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9 0x40
45ac60c0 1715#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS9_SHIFT 0x06
2945fbc2 1716#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8 0x20
45ac60c0 1717#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS8_SHIFT 0x05
2945fbc2 1718#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7 0x10
45ac60c0 1719#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS7_SHIFT 0x04
2945fbc2 1720#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6 0x08
45ac60c0 1721#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS6_SHIFT 0x03
2945fbc2 1722#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45 0x04
45ac60c0 1723#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS45_SHIFT 0x02
2945fbc2 1724#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3 0x02
45ac60c0 1725#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT 0x01
2945fbc2 1726#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12 0x01
45ac60c0 1727#define PALMAS_NSLEEP_SMPS_ASSIGN_SMPS12_SHIFT 0x00
2945fbc2
GG		 1728
1729/* Bit definitions for NSLEEP_LDO_ASSIGN1 */
1730#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8 0x80
45ac60c0 1731#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO8_SHIFT 0x07
2945fbc2 1732#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7 0x40
45ac60c0 1733#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO7_SHIFT 0x06
2945fbc2 1734#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6 0x20
45ac60c0 1735#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO6_SHIFT 0x05
2945fbc2 1736#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5 0x10
45ac60c0 1737#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO5_SHIFT 0x04
2945fbc2 1738#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4 0x08
45ac60c0 1739#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT 0x03
2945fbc2 1740#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3 0x04
45ac60c0 1741#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO3_SHIFT 0x02
2945fbc2 1742#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2 0x02
45ac60c0 1743#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT 0x01
2945fbc2 1744#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1 0x01
45ac60c0 1745#define PALMAS_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT 0x00
2945fbc2
GG		 1746
1747/* Bit definitions for NSLEEP_LDO_ASSIGN2 */
1748#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB 0x04
45ac60c0 1749#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOUSB_SHIFT 0x02
2945fbc2 1750#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN 0x02
45ac60c0 1751#define PALMAS_NSLEEP_LDO_ASSIGN2_LDOLN_SHIFT 0x01
2945fbc2 1752#define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9 0x01
45ac60c0 1753#define PALMAS_NSLEEP_LDO_ASSIGN2_LDO9_SHIFT 0x00
2945fbc2
GG		 1754
1755/* Bit definitions for ENABLE1_RES_ASSIGN */
1756#define PALMAS_ENABLE1_RES_ASSIGN_REGEN3 0x40
45ac60c0 1757#define PALMAS_ENABLE1_RES_ASSIGN_REGEN3_SHIFT 0x06
2945fbc2 1758#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO 0x20
45ac60c0 1759#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KGAUDIO_SHIFT 0x05
2945fbc2 1760#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG 0x10
45ac60c0 1761#define PALMAS_ENABLE1_RES_ASSIGN_CLK32KG_SHIFT 0x04
2945fbc2 1762#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2 0x08
45ac60c0 1763#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN2_SHIFT 0x03
2945fbc2 1764#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1 0x04
45ac60c0 1765#define PALMAS_ENABLE1_RES_ASSIGN_SYSEN1_SHIFT 0x02
2945fbc2 1766#define PALMAS_ENABLE1_RES_ASSIGN_REGEN2 0x02
45ac60c0 1767#define PALMAS_ENABLE1_RES_ASSIGN_REGEN2_SHIFT 0x01
2945fbc2 1768#define PALMAS_ENABLE1_RES_ASSIGN_REGEN1 0x01
45ac60c0 1769#define PALMAS_ENABLE1_RES_ASSIGN_REGEN1_SHIFT 0x00
2945fbc2
GG		 1770
1771/* Bit definitions for ENABLE1_SMPS_ASSIGN */
1772#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10 0x80
45ac60c0 1773#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS10_SHIFT 0x07
2945fbc2 1774#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9 0x40
45ac60c0 1775#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS9_SHIFT 0x06
2945fbc2 1776#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8 0x20
45ac60c0 1777#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS8_SHIFT 0x05
2945fbc2 1778#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7 0x10
45ac60c0 1779#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS7_SHIFT 0x04
2945fbc2 1780#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6 0x08
45ac60c0 1781#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS6_SHIFT 0x03
2945fbc2 1782#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45 0x04
45ac60c0 1783#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS45_SHIFT 0x02
2945fbc2 1784#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3 0x02
45ac60c0 1785#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT 0x01
2945fbc2 1786#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12 0x01
45ac60c0 1787#define PALMAS_ENABLE1_SMPS_ASSIGN_SMPS12_SHIFT 0x00
2945fbc2
GG		 1788
1789/* Bit definitions for ENABLE1_LDO_ASSIGN1 */
1790#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8 0x80
45ac60c0 1791#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO8_SHIFT 0x07
2945fbc2 1792#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7 0x40
45ac60c0 1793#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO7_SHIFT 0x06
2945fbc2 1794#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6 0x20
45ac60c0 1795#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO6_SHIFT 0x05
2945fbc2 1796#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5 0x10
45ac60c0 1797#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO5_SHIFT 0x04
2945fbc2 1798#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4 0x08
45ac60c0 1799#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT 0x03
2945fbc2 1800#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3 0x04
45ac60c0 1801#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO3_SHIFT 0x02
2945fbc2 1802#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2 0x02
45ac60c0 1803#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT 0x01
2945fbc2 1804#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1 0x01
45ac60c0 1805#define PALMAS_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT 0x00
2945fbc2
GG		 1806
1807/* Bit definitions for ENABLE1_LDO_ASSIGN2 */
1808#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB 0x04
45ac60c0 1809#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOUSB_SHIFT 0x02
2945fbc2 1810#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN 0x02
45ac60c0 1811#define PALMAS_ENABLE1_LDO_ASSIGN2_LDOLN_SHIFT 0x01
2945fbc2 1812#define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9 0x01
45ac60c0 1813#define PALMAS_ENABLE1_LDO_ASSIGN2_LDO9_SHIFT 0x00
2945fbc2
GG		 1814
1815/* Bit definitions for ENABLE2_RES_ASSIGN */
1816#define PALMAS_ENABLE2_RES_ASSIGN_REGEN3 0x40
45ac60c0 1817#define PALMAS_ENABLE2_RES_ASSIGN_REGEN3_SHIFT 0x06
2945fbc2 1818#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO 0x20
45ac60c0 1819#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KGAUDIO_SHIFT 0x05
2945fbc2 1820#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG 0x10
45ac60c0 1821#define PALMAS_ENABLE2_RES_ASSIGN_CLK32KG_SHIFT 0x04
2945fbc2 1822#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2 0x08
45ac60c0 1823#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN2_SHIFT 0x03
2945fbc2 1824#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1 0x04
45ac60c0 1825#define PALMAS_ENABLE2_RES_ASSIGN_SYSEN1_SHIFT 0x02
2945fbc2 1826#define PALMAS_ENABLE2_RES_ASSIGN_REGEN2 0x02
45ac60c0 1827#define PALMAS_ENABLE2_RES_ASSIGN_REGEN2_SHIFT 0x01
2945fbc2 1828#define PALMAS_ENABLE2_RES_ASSIGN_REGEN1 0x01
45ac60c0 1829#define PALMAS_ENABLE2_RES_ASSIGN_REGEN1_SHIFT 0x00
2945fbc2
GG		 1830
1831/* Bit definitions for ENABLE2_SMPS_ASSIGN */
1832#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10 0x80
45ac60c0 1833#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS10_SHIFT 0x07
2945fbc2 1834#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9 0x40
45ac60c0 1835#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS9_SHIFT 0x06
2945fbc2 1836#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8 0x20
45ac60c0 1837#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS8_SHIFT 0x05
2945fbc2 1838#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7 0x10
45ac60c0 1839#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS7_SHIFT 0x04
2945fbc2 1840#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6 0x08
45ac60c0 1841#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS6_SHIFT 0x03
2945fbc2 1842#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45 0x04
45ac60c0 1843#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS45_SHIFT 0x02
2945fbc2 1844#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3 0x02
45ac60c0 1845#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT 0x01
2945fbc2 1846#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12 0x01
45ac60c0 1847#define PALMAS_ENABLE2_SMPS_ASSIGN_SMPS12_SHIFT 0x00
2945fbc2
GG		 1848
1849/* Bit definitions for ENABLE2_LDO_ASSIGN1 */
1850#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8 0x80
45ac60c0 1851#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO8_SHIFT 0x07
2945fbc2 1852#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7 0x40
45ac60c0 1853#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO7_SHIFT 0x06
2945fbc2 1854#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6 0x20
45ac60c0 1855#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO6_SHIFT 0x05
2945fbc2 1856#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5 0x10
45ac60c0 1857#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO5_SHIFT 0x04
2945fbc2 1858#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4 0x08
45ac60c0 1859#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT 0x03
2945fbc2 1860#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3 0x04
45ac60c0 1861#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO3_SHIFT 0x02
2945fbc2 1862#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2 0x02
45ac60c0 1863#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT 0x01
2945fbc2 1864#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1 0x01
45ac60c0 1865#define PALMAS_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT 0x00
2945fbc2
GG		 1866
1867/* Bit definitions for ENABLE2_LDO_ASSIGN2 */
1868#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB 0x04
45ac60c0 1869#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOUSB_SHIFT 0x02
2945fbc2 1870#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN 0x02
45ac60c0 1871#define PALMAS_ENABLE2_LDO_ASSIGN2_LDOLN_SHIFT 0x01
2945fbc2 1872#define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9 0x01
45ac60c0 1873#define PALMAS_ENABLE2_LDO_ASSIGN2_LDO9_SHIFT 0x00
2945fbc2
GG		 1874
1875/* Bit definitions for REGEN3_CTRL */
1876#define PALMAS_REGEN3_CTRL_STATUS 0x10
45ac60c0 1877#define PALMAS_REGEN3_CTRL_STATUS_SHIFT 0x04
2945fbc2 1878#define PALMAS_REGEN3_CTRL_MODE_SLEEP 0x04
45ac60c0 1879#define PALMAS_REGEN3_CTRL_MODE_SLEEP_SHIFT 0x02
2945fbc2 1880#define PALMAS_REGEN3_CTRL_MODE_ACTIVE 0x01
45ac60c0 1881#define PALMAS_REGEN3_CTRL_MODE_ACTIVE_SHIFT 0x00
2945fbc2
GG		 1882
1883/* Registers for function PAD_CONTROL */
45ac60c0
K		 1884#define PALMAS_OD_OUTPUT_CTRL2 0x02
1885#define PALMAS_POLARITY_CTRL2 0x03
1886#define PALMAS_PU_PD_INPUT_CTRL1 0x04
1887#define PALMAS_PU_PD_INPUT_CTRL2 0x05
1888#define PALMAS_PU_PD_INPUT_CTRL3 0x06
1889#define PALMAS_PU_PD_INPUT_CTRL5 0x07
1890#define PALMAS_OD_OUTPUT_CTRL 0x08
1891#define PALMAS_POLARITY_CTRL 0x09
1892#define PALMAS_PRIMARY_SECONDARY_PAD1 0x0A
1893#define PALMAS_PRIMARY_SECONDARY_PAD2 0x0B
1894#define PALMAS_I2C_SPI 0x0C
1895#define PALMAS_PU_PD_INPUT_CTRL4 0x0D
1896#define PALMAS_PRIMARY_SECONDARY_PAD3 0x0E
1897#define PALMAS_PRIMARY_SECONDARY_PAD4 0x0F
2945fbc2
GG		 1898
1899/* Bit definitions for PU_PD_INPUT_CTRL1 */
1900#define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD 0x40
45ac60c0 1901#define PALMAS_PU_PD_INPUT_CTRL1_RESET_IN_PD_SHIFT 0x06
2945fbc2 1902#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU 0x20
45ac60c0 1903#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PU_SHIFT 0x05
2945fbc2 1904#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD 0x10
45ac60c0 1905#define PALMAS_PU_PD_INPUT_CTRL1_GPADC_START_PD_SHIFT 0x04
2945fbc2 1906#define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD 0x04
45ac60c0 1907#define PALMAS_PU_PD_INPUT_CTRL1_PWRDOWN_PD_SHIFT 0x02
2945fbc2 1908#define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU 0x02
45ac60c0 1909#define PALMAS_PU_PD_INPUT_CTRL1_NRESWARM_PU_SHIFT 0x01
2945fbc2
GG		 1910
1911/* Bit definitions for PU_PD_INPUT_CTRL2 */
1912#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU 0x20
45ac60c0 1913#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PU_SHIFT 0x05
2945fbc2 1914#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD 0x10
45ac60c0 1915#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE2_PD_SHIFT 0x04
2945fbc2 1916#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU 0x08
45ac60c0 1917#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PU_SHIFT 0x03
2945fbc2 1918#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD 0x04
45ac60c0 1919#define PALMAS_PU_PD_INPUT_CTRL2_ENABLE1_PD_SHIFT 0x02
2945fbc2 1920#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU 0x02
45ac60c0 1921#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PU_SHIFT 0x01
2945fbc2 1922#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD 0x01
45ac60c0 1923#define PALMAS_PU_PD_INPUT_CTRL2_NSLEEP_PD_SHIFT 0x00
2945fbc2
GG		 1924
1925/* Bit definitions for PU_PD_INPUT_CTRL3 */
1926#define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD 0x40
45ac60c0 1927#define PALMAS_PU_PD_INPUT_CTRL3_ACOK_PD_SHIFT 0x06
2945fbc2 1928#define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD 0x10
45ac60c0 1929#define PALMAS_PU_PD_INPUT_CTRL3_CHRG_DET_N_PD_SHIFT 0x04
2945fbc2 1930#define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD 0x04
45ac60c0 1931#define PALMAS_PU_PD_INPUT_CTRL3_POWERHOLD_PD_SHIFT 0x02
2945fbc2 1932#define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD 0x01
45ac60c0 1933#define PALMAS_PU_PD_INPUT_CTRL3_MSECURE_PD_SHIFT 0x00
2945fbc2
GG		 1934
1935/* Bit definitions for OD_OUTPUT_CTRL */
1936#define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD 0x80
45ac60c0 1937#define PALMAS_OD_OUTPUT_CTRL_PWM_2_OD_SHIFT 0x07
2945fbc2 1938#define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD 0x40
45ac60c0 1939#define PALMAS_OD_OUTPUT_CTRL_VBUSDET_OD_SHIFT 0x06
2945fbc2 1940#define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD 0x20
45ac60c0 1941#define PALMAS_OD_OUTPUT_CTRL_PWM_1_OD_SHIFT 0x05
2945fbc2 1942#define PALMAS_OD_OUTPUT_CTRL_INT_OD 0x08
45ac60c0 1943#define PALMAS_OD_OUTPUT_CTRL_INT_OD_SHIFT 0x03
2945fbc2
GG		 1944
1945/* Bit definitions for POLARITY_CTRL */
1946#define PALMAS_POLARITY_CTRL_INT_POLARITY 0x80
45ac60c0 1947#define PALMAS_POLARITY_CTRL_INT_POLARITY_SHIFT 0x07
2945fbc2 1948#define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY 0x40
45ac60c0 1949#define PALMAS_POLARITY_CTRL_ENABLE2_POLARITY_SHIFT 0x06
2945fbc2 1950#define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY 0x20
45ac60c0 1951#define PALMAS_POLARITY_CTRL_ENABLE1_POLARITY_SHIFT 0x05
2945fbc2 1952#define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY 0x10
45ac60c0 1953#define PALMAS_POLARITY_CTRL_NSLEEP_POLARITY_SHIFT 0x04
2945fbc2 1954#define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY 0x08
45ac60c0 1955#define PALMAS_POLARITY_CTRL_RESET_IN_POLARITY_SHIFT 0x03
2945fbc2 1956#define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY 0x04
45ac60c0 1957#define PALMAS_POLARITY_CTRL_GPIO_3_CHRG_DET_N_POLARITY_SHIFT 0x02
2945fbc2 1958#define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY 0x02
45ac60c0 1959#define PALMAS_POLARITY_CTRL_POWERGOOD_USB_PSEL_POLARITY_SHIFT 0x01
2945fbc2 1960#define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY 0x01
45ac60c0 1961#define PALMAS_POLARITY_CTRL_PWRDOWN_POLARITY_SHIFT 0x00
2945fbc2
GG		 1962
1963/* Bit definitions for PRIMARY_SECONDARY_PAD1 */
1964#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3 0x80
45ac60c0 1965#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_3_SHIFT 0x07
2945fbc2 1966#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_MASK 0x60
45ac60c0 1967#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_2_SHIFT 0x05
2945fbc2 1968#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_MASK 0x18
45ac60c0 1969#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_1_SHIFT 0x03
2945fbc2 1970#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0 0x04
45ac60c0 1971#define PALMAS_PRIMARY_SECONDARY_PAD1_GPIO_0_SHIFT 0x02
2945fbc2 1972#define PALMAS_PRIMARY_SECONDARY_PAD1_VAC 0x02
45ac60c0 1973#define PALMAS_PRIMARY_SECONDARY_PAD1_VAC_SHIFT 0x01
2945fbc2 1974#define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD 0x01
45ac60c0 1975#define PALMAS_PRIMARY_SECONDARY_PAD1_POWERGOOD_SHIFT 0x00
2945fbc2
GG		 1976
1977/* Bit definitions for PRIMARY_SECONDARY_PAD2 */
1978#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_MASK 0x30
45ac60c0 1979#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_7_SHIFT 0x04
2945fbc2 1980#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6 0x08
45ac60c0 1981#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_6_SHIFT 0x03
2945fbc2 1982#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_MASK 0x06
45ac60c0 1983#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_5_SHIFT 0x01
2945fbc2 1984#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4 0x01
45ac60c0 1985#define PALMAS_PRIMARY_SECONDARY_PAD2_GPIO_4_SHIFT 0x00
2945fbc2
GG		 1986
1987/* Bit definitions for I2C_SPI */
1988#define PALMAS_I2C_SPI_I2C2OTP_EN 0x80
45ac60c0 1989#define PALMAS_I2C_SPI_I2C2OTP_EN_SHIFT 0x07
2945fbc2 1990#define PALMAS_I2C_SPI_I2C2OTP_PAGESEL 0x40
45ac60c0 1991#define PALMAS_I2C_SPI_I2C2OTP_PAGESEL_SHIFT 0x06
2945fbc2 1992#define PALMAS_I2C_SPI_ID_I2C2 0x20
45ac60c0 1993#define PALMAS_I2C_SPI_ID_I2C2_SHIFT 0x05
2945fbc2 1994#define PALMAS_I2C_SPI_I2C_SPI 0x10
45ac60c0
K		 1995#define PALMAS_I2C_SPI_I2C_SPI_SHIFT 0x04
1996#define PALMAS_I2C_SPI_ID_I2C1_MASK 0x0F
1997#define PALMAS_I2C_SPI_ID_I2C1_SHIFT 0x00
2945fbc2
GG		 1998
1999/* Bit definitions for PU_PD_INPUT_CTRL4 */
2000#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD 0x40
45ac60c0 2001#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_DAT_PD_SHIFT 0x06
2945fbc2 2002#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD 0x10
45ac60c0 2003#define PALMAS_PU_PD_INPUT_CTRL4_DVFS2_CLK_PD_SHIFT 0x04
2945fbc2 2004#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD 0x04
45ac60c0 2005#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_DAT_PD_SHIFT 0x02
2945fbc2 2006#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD 0x01
45ac60c0 2007#define PALMAS_PU_PD_INPUT_CTRL4_DVFS1_CLK_PD_SHIFT 0x00
2945fbc2
GG		 2008
2009/* Bit definitions for PRIMARY_SECONDARY_PAD3 */
2010#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2 0x02
45ac60c0 2011#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS2_SHIFT 0x01
2945fbc2 2012#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1 0x01
45ac60c0 2013#define PALMAS_PRIMARY_SECONDARY_PAD3_DVFS1_SHIFT 0x00
2945fbc2
GG		 2014
2015/* Registers for function LED_PWM */
45ac60c0
K		 2016#define PALMAS_LED_PERIOD_CTRL 0x00
2017#define PALMAS_LED_CTRL 0x01
2018#define PALMAS_PWM_CTRL1 0x02
2019#define PALMAS_PWM_CTRL2 0x03
2945fbc2
GG		 2020
2021/* Bit definitions for LED_PERIOD_CTRL */
2022#define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_MASK 0x38
45ac60c0 2023#define PALMAS_LED_PERIOD_CTRL_LED_2_PERIOD_SHIFT 0x03
2945fbc2 2024#define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_MASK 0x07
45ac60c0 2025#define PALMAS_LED_PERIOD_CTRL_LED_1_PERIOD_SHIFT 0x00
2945fbc2
GG		 2026
2027/* Bit definitions for LED_CTRL */
2028#define PALMAS_LED_CTRL_LED_2_SEQ 0x20
45ac60c0 2029#define PALMAS_LED_CTRL_LED_2_SEQ_SHIFT 0x05
2945fbc2 2030#define PALMAS_LED_CTRL_LED_1_SEQ 0x10
45ac60c0 2031#define PALMAS_LED_CTRL_LED_1_SEQ_SHIFT 0x04
2945fbc2 2032#define PALMAS_LED_CTRL_LED_2_ON_TIME_MASK 0x0c
45ac60c0 2033#define PALMAS_LED_CTRL_LED_2_ON_TIME_SHIFT 0x02
2945fbc2 2034#define PALMAS_LED_CTRL_LED_1_ON_TIME_MASK 0x03
45ac60c0 2035#define PALMAS_LED_CTRL_LED_1_ON_TIME_SHIFT 0x00
2945fbc2
GG		 2036
2037/* Bit definitions for PWM_CTRL1 */
2038#define PALMAS_PWM_CTRL1_PWM_FREQ_EN 0x02
45ac60c0 2039#define PALMAS_PWM_CTRL1_PWM_FREQ_EN_SHIFT 0x01
2945fbc2 2040#define PALMAS_PWM_CTRL1_PWM_FREQ_SEL 0x01
45ac60c0 2041#define PALMAS_PWM_CTRL1_PWM_FREQ_SEL_SHIFT 0x00
2945fbc2
GG		 2042
2043/* Bit definitions for PWM_CTRL2 */
45ac60c0
K		 2044#define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_MASK 0xFF
2045#define PALMAS_PWM_CTRL2_PWM_DUTY_SEL_SHIFT 0x00
2945fbc2
GG		 2046
2047/* Registers for function INTERRUPT */
45ac60c0
K		 2048#define PALMAS_INT1_STATUS 0x00
2049#define PALMAS_INT1_MASK 0x01
2050#define PALMAS_INT1_LINE_STATE 0x02
2051#define PALMAS_INT1_EDGE_DETECT1_RESERVED 0x03
2052#define PALMAS_INT1_EDGE_DETECT2_RESERVED 0x04
2053#define PALMAS_INT2_STATUS 0x05
2054#define PALMAS_INT2_MASK 0x06
2055#define PALMAS_INT2_LINE_STATE 0x07
2056#define PALMAS_INT2_EDGE_DETECT1_RESERVED 0x08
2057#define PALMAS_INT2_EDGE_DETECT2_RESERVED 0x09
2058#define PALMAS_INT3_STATUS 0x0A
2059#define PALMAS_INT3_MASK 0x0B
2060#define PALMAS_INT3_LINE_STATE 0x0C
2061#define PALMAS_INT3_EDGE_DETECT1_RESERVED 0x0D
2062#define PALMAS_INT3_EDGE_DETECT2_RESERVED 0x0E
2063#define PALMAS_INT4_STATUS 0x0F
2945fbc2
GG		 2064#define PALMAS_INT4_MASK 0x10
2065#define PALMAS_INT4_LINE_STATE 0x11
2066#define PALMAS_INT4_EDGE_DETECT1 0x12
2067#define PALMAS_INT4_EDGE_DETECT2 0x13
2068#define PALMAS_INT_CTRL 0x14
2069
2070/* Bit definitions for INT1_STATUS */
2071#define PALMAS_INT1_STATUS_VBAT_MON 0x80
45ac60c0 2072#define PALMAS_INT1_STATUS_VBAT_MON_SHIFT 0x07
2945fbc2 2073#define PALMAS_INT1_STATUS_VSYS_MON 0x40
45ac60c0 2074#define PALMAS_INT1_STATUS_VSYS_MON_SHIFT 0x06
2945fbc2 2075#define PALMAS_INT1_STATUS_HOTDIE 0x20
45ac60c0 2076#define PALMAS_INT1_STATUS_HOTDIE_SHIFT 0x05
2945fbc2 2077#define PALMAS_INT1_STATUS_PWRDOWN 0x10
45ac60c0 2078#define PALMAS_INT1_STATUS_PWRDOWN_SHIFT 0x04
2945fbc2 2079#define PALMAS_INT1_STATUS_RPWRON 0x08
45ac60c0 2080#define PALMAS_INT1_STATUS_RPWRON_SHIFT 0x03
2945fbc2 2081#define PALMAS_INT1_STATUS_LONG_PRESS_KEY 0x04
45ac60c0 2082#define PALMAS_INT1_STATUS_LONG_PRESS_KEY_SHIFT 0x02
2945fbc2 2083#define PALMAS_INT1_STATUS_PWRON 0x02
45ac60c0 2084#define PALMAS_INT1_STATUS_PWRON_SHIFT 0x01
2945fbc2 2085#define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV 0x01
45ac60c0 2086#define PALMAS_INT1_STATUS_CHARG_DET_N_VBUS_OVV_SHIFT 0x00
2945fbc2
GG		 2087
2088/* Bit definitions for INT1_MASK */
2089#define PALMAS_INT1_MASK_VBAT_MON 0x80
45ac60c0 2090#define PALMAS_INT1_MASK_VBAT_MON_SHIFT 0x07
2945fbc2 2091#define PALMAS_INT1_MASK_VSYS_MON 0x40
45ac60c0 2092#define PALMAS_INT1_MASK_VSYS_MON_SHIFT 0x06
2945fbc2 2093#define PALMAS_INT1_MASK_HOTDIE 0x20
45ac60c0 2094#define PALMAS_INT1_MASK_HOTDIE_SHIFT 0x05
2945fbc2 2095#define PALMAS_INT1_MASK_PWRDOWN 0x10
45ac60c0 2096#define PALMAS_INT1_MASK_PWRDOWN_SHIFT 0x04
2945fbc2 2097#define PALMAS_INT1_MASK_RPWRON 0x08
45ac60c0 2098#define PALMAS_INT1_MASK_RPWRON_SHIFT 0x03
2945fbc2 2099#define PALMAS_INT1_MASK_LONG_PRESS_KEY 0x04
45ac60c0 2100#define PALMAS_INT1_MASK_LONG_PRESS_KEY_SHIFT 0x02
2945fbc2 2101#define PALMAS_INT1_MASK_PWRON 0x02
45ac60c0 2102#define PALMAS_INT1_MASK_PWRON_SHIFT 0x01
2945fbc2 2103#define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV 0x01
45ac60c0 2104#define PALMAS_INT1_MASK_CHARG_DET_N_VBUS_OVV_SHIFT 0x00
2945fbc2
GG		 2105
2106/* Bit definitions for INT1_LINE_STATE */
2107#define PALMAS_INT1_LINE_STATE_VBAT_MON 0x80
45ac60c0 2108#define PALMAS_INT1_LINE_STATE_VBAT_MON_SHIFT 0x07
2945fbc2 2109#define PALMAS_INT1_LINE_STATE_VSYS_MON 0x40
45ac60c0 2110#define PALMAS_INT1_LINE_STATE_VSYS_MON_SHIFT 0x06
2945fbc2 2111#define PALMAS_INT1_LINE_STATE_HOTDIE 0x20
45ac60c0 2112#define PALMAS_INT1_LINE_STATE_HOTDIE_SHIFT 0x05
2945fbc2 2113#define PALMAS_INT1_LINE_STATE_PWRDOWN 0x10
45ac60c0 2114#define PALMAS_INT1_LINE_STATE_PWRDOWN_SHIFT 0x04
2945fbc2 2115#define PALMAS_INT1_LINE_STATE_RPWRON 0x08
45ac60c0 2116#define PALMAS_INT1_LINE_STATE_RPWRON_SHIFT 0x03
2945fbc2 2117#define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY 0x04
45ac60c0 2118#define PALMAS_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT 0x02
2945fbc2 2119#define PALMAS_INT1_LINE_STATE_PWRON 0x02
45ac60c0 2120#define PALMAS_INT1_LINE_STATE_PWRON_SHIFT 0x01
2945fbc2 2121#define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV 0x01
45ac60c0 2122#define PALMAS_INT1_LINE_STATE_CHARG_DET_N_VBUS_OVV_SHIFT 0x00
2945fbc2
GG		 2123
2124/* Bit definitions for INT2_STATUS */
2125#define PALMAS_INT2_STATUS_VAC_ACOK 0x80
45ac60c0 2126#define PALMAS_INT2_STATUS_VAC_ACOK_SHIFT 0x07
2945fbc2 2127#define PALMAS_INT2_STATUS_SHORT 0x40
45ac60c0 2128#define PALMAS_INT2_STATUS_SHORT_SHIFT 0x06
2945fbc2 2129#define PALMAS_INT2_STATUS_FBI_BB 0x20
45ac60c0 2130#define PALMAS_INT2_STATUS_FBI_BB_SHIFT 0x05
2945fbc2 2131#define PALMAS_INT2_STATUS_RESET_IN 0x10
45ac60c0 2132#define PALMAS_INT2_STATUS_RESET_IN_SHIFT 0x04
2945fbc2 2133#define PALMAS_INT2_STATUS_BATREMOVAL 0x08
45ac60c0 2134#define PALMAS_INT2_STATUS_BATREMOVAL_SHIFT 0x03
2945fbc2 2135#define PALMAS_INT2_STATUS_WDT 0x04
45ac60c0 2136#define PALMAS_INT2_STATUS_WDT_SHIFT 0x02
2945fbc2 2137#define PALMAS_INT2_STATUS_RTC_TIMER 0x02
45ac60c0 2138#define PALMAS_INT2_STATUS_RTC_TIMER_SHIFT 0x01
2945fbc2 2139#define PALMAS_INT2_STATUS_RTC_ALARM 0x01
45ac60c0 2140#define PALMAS_INT2_STATUS_RTC_ALARM_SHIFT 0x00
2945fbc2
GG		 2141
2142/* Bit definitions for INT2_MASK */
2143#define PALMAS_INT2_MASK_VAC_ACOK 0x80
45ac60c0 2144#define PALMAS_INT2_MASK_VAC_ACOK_SHIFT 0x07
2945fbc2 2145#define PALMAS_INT2_MASK_SHORT 0x40
45ac60c0 2146#define PALMAS_INT2_MASK_SHORT_SHIFT 0x06
2945fbc2 2147#define PALMAS_INT2_MASK_FBI_BB 0x20
45ac60c0 2148#define PALMAS_INT2_MASK_FBI_BB_SHIFT 0x05
2945fbc2 2149#define PALMAS_INT2_MASK_RESET_IN 0x10
45ac60c0 2150#define PALMAS_INT2_MASK_RESET_IN_SHIFT 0x04
2945fbc2 2151#define PALMAS_INT2_MASK_BATREMOVAL 0x08
45ac60c0 2152#define PALMAS_INT2_MASK_BATREMOVAL_SHIFT 0x03
2945fbc2 2153#define PALMAS_INT2_MASK_WDT 0x04
45ac60c0 2154#define PALMAS_INT2_MASK_WDT_SHIFT 0x02
2945fbc2 2155#define PALMAS_INT2_MASK_RTC_TIMER 0x02
45ac60c0 2156#define PALMAS_INT2_MASK_RTC_TIMER_SHIFT 0x01
2945fbc2 2157#define PALMAS_INT2_MASK_RTC_ALARM 0x01
45ac60c0 2158#define PALMAS_INT2_MASK_RTC_ALARM_SHIFT 0x00
2945fbc2
GG		 2159
2160/* Bit definitions for INT2_LINE_STATE */
2161#define PALMAS_INT2_LINE_STATE_VAC_ACOK 0x80
45ac60c0 2162#define PALMAS_INT2_LINE_STATE_VAC_ACOK_SHIFT 0x07
2945fbc2 2163#define PALMAS_INT2_LINE_STATE_SHORT 0x40
45ac60c0 2164#define PALMAS_INT2_LINE_STATE_SHORT_SHIFT 0x06
2945fbc2 2165#define PALMAS_INT2_LINE_STATE_FBI_BB 0x20
45ac60c0 2166#define PALMAS_INT2_LINE_STATE_FBI_BB_SHIFT 0x05
2945fbc2 2167#define PALMAS_INT2_LINE_STATE_RESET_IN 0x10
45ac60c0 2168#define PALMAS_INT2_LINE_STATE_RESET_IN_SHIFT 0x04
2945fbc2 2169#define PALMAS_INT2_LINE_STATE_BATREMOVAL 0x08
45ac60c0 2170#define PALMAS_INT2_LINE_STATE_BATREMOVAL_SHIFT 0x03
2945fbc2 2171#define PALMAS_INT2_LINE_STATE_WDT 0x04
45ac60c0 2172#define PALMAS_INT2_LINE_STATE_WDT_SHIFT 0x02
2945fbc2 2173#define PALMAS_INT2_LINE_STATE_RTC_TIMER 0x02
45ac60c0 2174#define PALMAS_INT2_LINE_STATE_RTC_TIMER_SHIFT 0x01
2945fbc2 2175#define PALMAS_INT2_LINE_STATE_RTC_ALARM 0x01
45ac60c0 2176#define PALMAS_INT2_LINE_STATE_RTC_ALARM_SHIFT 0x00
2945fbc2
GG		 2177
2178/* Bit definitions for INT3_STATUS */
2179#define PALMAS_INT3_STATUS_VBUS 0x80
45ac60c0 2180#define PALMAS_INT3_STATUS_VBUS_SHIFT 0x07
2945fbc2 2181#define PALMAS_INT3_STATUS_VBUS_OTG 0x40
45ac60c0 2182#define PALMAS_INT3_STATUS_VBUS_OTG_SHIFT 0x06
2945fbc2 2183#define PALMAS_INT3_STATUS_ID 0x20
45ac60c0 2184#define PALMAS_INT3_STATUS_ID_SHIFT 0x05
2945fbc2 2185#define PALMAS_INT3_STATUS_ID_OTG 0x10
45ac60c0 2186#define PALMAS_INT3_STATUS_ID_OTG_SHIFT 0x04
2945fbc2 2187#define PALMAS_INT3_STATUS_GPADC_EOC_RT 0x08
45ac60c0 2188#define PALMAS_INT3_STATUS_GPADC_EOC_RT_SHIFT 0x03
2945fbc2 2189#define PALMAS_INT3_STATUS_GPADC_EOC_SW 0x04
45ac60c0 2190#define PALMAS_INT3_STATUS_GPADC_EOC_SW_SHIFT 0x02
2945fbc2 2191#define PALMAS_INT3_STATUS_GPADC_AUTO_1 0x02
45ac60c0 2192#define PALMAS_INT3_STATUS_GPADC_AUTO_1_SHIFT 0x01
2945fbc2 2193#define PALMAS_INT3_STATUS_GPADC_AUTO_0 0x01
45ac60c0 2194#define PALMAS_INT3_STATUS_GPADC_AUTO_0_SHIFT 0x00
2945fbc2
GG		 2195
2196/* Bit definitions for INT3_MASK */
2197#define PALMAS_INT3_MASK_VBUS 0x80
45ac60c0 2198#define PALMAS_INT3_MASK_VBUS_SHIFT 0x07
2945fbc2 2199#define PALMAS_INT3_MASK_VBUS_OTG 0x40
45ac60c0 2200#define PALMAS_INT3_MASK_VBUS_OTG_SHIFT 0x06
2945fbc2 2201#define PALMAS_INT3_MASK_ID 0x20
45ac60c0 2202#define PALMAS_INT3_MASK_ID_SHIFT 0x05
2945fbc2 2203#define PALMAS_INT3_MASK_ID_OTG 0x10
45ac60c0 2204#define PALMAS_INT3_MASK_ID_OTG_SHIFT 0x04
2945fbc2 2205#define PALMAS_INT3_MASK_GPADC_EOC_RT 0x08
45ac60c0 2206#define PALMAS_INT3_MASK_GPADC_EOC_RT_SHIFT 0x03
2945fbc2 2207#define PALMAS_INT3_MASK_GPADC_EOC_SW 0x04
45ac60c0 2208#define PALMAS_INT3_MASK_GPADC_EOC_SW_SHIFT 0x02
2945fbc2 2209#define PALMAS_INT3_MASK_GPADC_AUTO_1 0x02
45ac60c0 2210#define PALMAS_INT3_MASK_GPADC_AUTO_1_SHIFT 0x01
2945fbc2 2211#define PALMAS_INT3_MASK_GPADC_AUTO_0 0x01
45ac60c0 2212#define PALMAS_INT3_MASK_GPADC_AUTO_0_SHIFT 0x00
2945fbc2
GG		 2213
2214/* Bit definitions for INT3_LINE_STATE */
2215#define PALMAS_INT3_LINE_STATE_VBUS 0x80
45ac60c0 2216#define PALMAS_INT3_LINE_STATE_VBUS_SHIFT 0x07
2945fbc2 2217#define PALMAS_INT3_LINE_STATE_VBUS_OTG 0x40
45ac60c0 2218#define PALMAS_INT3_LINE_STATE_VBUS_OTG_SHIFT 0x06
2945fbc2 2219#define PALMAS_INT3_LINE_STATE_ID 0x20
45ac60c0 2220#define PALMAS_INT3_LINE_STATE_ID_SHIFT 0x05
2945fbc2 2221#define PALMAS_INT3_LINE_STATE_ID_OTG 0x10
45ac60c0 2222#define PALMAS_INT3_LINE_STATE_ID_OTG_SHIFT 0x04
2945fbc2 2223#define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT 0x08
45ac60c0 2224#define PALMAS_INT3_LINE_STATE_GPADC_EOC_RT_SHIFT 0x03
2945fbc2 2225#define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW 0x04
45ac60c0 2226#define PALMAS_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT 0x02
2945fbc2 2227#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1 0x02
45ac60c0 2228#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT 0x01
2945fbc2 2229#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0 0x01
45ac60c0 2230#define PALMAS_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT 0x00
2945fbc2
GG		 2231
2232/* Bit definitions for INT4_STATUS */
2233#define PALMAS_INT4_STATUS_GPIO_7 0x80
45ac60c0 2234#define PALMAS_INT4_STATUS_GPIO_7_SHIFT 0x07
2945fbc2 2235#define PALMAS_INT4_STATUS_GPIO_6 0x40
45ac60c0 2236#define PALMAS_INT4_STATUS_GPIO_6_SHIFT 0x06
2945fbc2 2237#define PALMAS_INT4_STATUS_GPIO_5 0x20
45ac60c0 2238#define PALMAS_INT4_STATUS_GPIO_5_SHIFT 0x05
2945fbc2 2239#define PALMAS_INT4_STATUS_GPIO_4 0x10
45ac60c0 2240#define PALMAS_INT4_STATUS_GPIO_4_SHIFT 0x04
2945fbc2 2241#define PALMAS_INT4_STATUS_GPIO_3 0x08
45ac60c0 2242#define PALMAS_INT4_STATUS_GPIO_3_SHIFT 0x03
2945fbc2 2243#define PALMAS_INT4_STATUS_GPIO_2 0x04
45ac60c0 2244#define PALMAS_INT4_STATUS_GPIO_2_SHIFT 0x02
2945fbc2 2245#define PALMAS_INT4_STATUS_GPIO_1 0x02
45ac60c0 2246#define PALMAS_INT4_STATUS_GPIO_1_SHIFT 0x01
2945fbc2 2247#define PALMAS_INT4_STATUS_GPIO_0 0x01
45ac60c0 2248#define PALMAS_INT4_STATUS_GPIO_0_SHIFT 0x00
2945fbc2
GG		 2249
2250/* Bit definitions for INT4_MASK */
2251#define PALMAS_INT4_MASK_GPIO_7 0x80
45ac60c0 2252#define PALMAS_INT4_MASK_GPIO_7_SHIFT 0x07
2945fbc2 2253#define PALMAS_INT4_MASK_GPIO_6 0x40
45ac60c0 2254#define PALMAS_INT4_MASK_GPIO_6_SHIFT 0x06
2945fbc2 2255#define PALMAS_INT4_MASK_GPIO_5 0x20
45ac60c0 2256#define PALMAS_INT4_MASK_GPIO_5_SHIFT 0x05
2945fbc2 2257#define PALMAS_INT4_MASK_GPIO_4 0x10
45ac60c0 2258#define PALMAS_INT4_MASK_GPIO_4_SHIFT 0x04
2945fbc2 2259#define PALMAS_INT4_MASK_GPIO_3 0x08
45ac60c0 2260#define PALMAS_INT4_MASK_GPIO_3_SHIFT 0x03
2945fbc2 2261#define PALMAS_INT4_MASK_GPIO_2 0x04
45ac60c0 2262#define PALMAS_INT4_MASK_GPIO_2_SHIFT 0x02
2945fbc2 2263#define PALMAS_INT4_MASK_GPIO_1 0x02
45ac60c0 2264#define PALMAS_INT4_MASK_GPIO_1_SHIFT 0x01
2945fbc2 2265#define PALMAS_INT4_MASK_GPIO_0 0x01
45ac60c0 2266#define PALMAS_INT4_MASK_GPIO_0_SHIFT 0x00
2945fbc2
GG		 2267
2268/* Bit definitions for INT4_LINE_STATE */
2269#define PALMAS_INT4_LINE_STATE_GPIO_7 0x80
45ac60c0 2270#define PALMAS_INT4_LINE_STATE_GPIO_7_SHIFT 0x07
2945fbc2 2271#define PALMAS_INT4_LINE_STATE_GPIO_6 0x40
45ac60c0 2272#define PALMAS_INT4_LINE_STATE_GPIO_6_SHIFT 0x06
2945fbc2 2273#define PALMAS_INT4_LINE_STATE_GPIO_5 0x20
45ac60c0 2274#define PALMAS_INT4_LINE_STATE_GPIO_5_SHIFT 0x05
2945fbc2 2275#define PALMAS_INT4_LINE_STATE_GPIO_4 0x10
45ac60c0 2276#define PALMAS_INT4_LINE_STATE_GPIO_4_SHIFT 0x04
2945fbc2 2277#define PALMAS_INT4_LINE_STATE_GPIO_3 0x08
45ac60c0 2278#define PALMAS_INT4_LINE_STATE_GPIO_3_SHIFT 0x03
2945fbc2 2279#define PALMAS_INT4_LINE_STATE_GPIO_2 0x04
45ac60c0 2280#define PALMAS_INT4_LINE_STATE_GPIO_2_SHIFT 0x02
2945fbc2 2281#define PALMAS_INT4_LINE_STATE_GPIO_1 0x02
45ac60c0 2282#define PALMAS_INT4_LINE_STATE_GPIO_1_SHIFT 0x01
2945fbc2 2283#define PALMAS_INT4_LINE_STATE_GPIO_0 0x01
45ac60c0 2284#define PALMAS_INT4_LINE_STATE_GPIO_0_SHIFT 0x00
2945fbc2
GG		 2285
2286/* Bit definitions for INT4_EDGE_DETECT1 */
2287#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING 0x80
45ac60c0 2288#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT 0x07
2945fbc2 2289#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING 0x40
45ac60c0 2290#define PALMAS_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT 0x06
2945fbc2 2291#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING 0x20
45ac60c0 2292#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT 0x05
2945fbc2 2293#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING 0x10
45ac60c0 2294#define PALMAS_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT 0x04
2945fbc2 2295#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING 0x08
45ac60c0 2296#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT 0x03
2945fbc2 2297#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING 0x04
45ac60c0 2298#define PALMAS_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT 0x02
2945fbc2 2299#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING 0x02
45ac60c0 2300#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT 0x01
2945fbc2 2301#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING 0x01
45ac60c0 2302#define PALMAS_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT 0x00
2945fbc2
GG		 2303
2304/* Bit definitions for INT4_EDGE_DETECT2 */
2305#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING 0x80
45ac60c0 2306#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_RISING_SHIFT 0x07
2945fbc2 2307#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING 0x40
45ac60c0 2308#define PALMAS_INT4_EDGE_DETECT2_GPIO_7_FALLING_SHIFT 0x06
2945fbc2 2309#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING 0x20
45ac60c0 2310#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT 0x05
2945fbc2 2311#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING 0x10
45ac60c0 2312#define PALMAS_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT 0x04
2945fbc2 2313#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING 0x08
45ac60c0 2314#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT 0x03
2945fbc2 2315#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING 0x04
45ac60c0 2316#define PALMAS_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT 0x02
2945fbc2 2317#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING 0x02
45ac60c0 2318#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT 0x01
2945fbc2 2319#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING 0x01
45ac60c0 2320#define PALMAS_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT 0x00
2945fbc2
GG		 2321
2322/* Bit definitions for INT_CTRL */
2323#define PALMAS_INT_CTRL_INT_PENDING 0x04
45ac60c0 2324#define PALMAS_INT_CTRL_INT_PENDING_SHIFT 0x02
2945fbc2 2325#define PALMAS_INT_CTRL_INT_CLEAR 0x01
45ac60c0 2326#define PALMAS_INT_CTRL_INT_CLEAR_SHIFT 0x00
2945fbc2
GG		 2327
2328/* Registers for function USB_OTG */
45ac60c0
K		 2329#define PALMAS_USB_WAKEUP 0x03
2330#define PALMAS_USB_VBUS_CTRL_SET 0x04
2331#define PALMAS_USB_VBUS_CTRL_CLR 0x05
2332#define PALMAS_USB_ID_CTRL_SET 0x06
2333#define PALMAS_USB_ID_CTRL_CLEAR 0x07
2334#define PALMAS_USB_VBUS_INT_SRC 0x08
2335#define PALMAS_USB_VBUS_INT_LATCH_SET 0x09
2336#define PALMAS_USB_VBUS_INT_LATCH_CLR 0x0A
2337#define PALMAS_USB_VBUS_INT_EN_LO_SET 0x0B
2338#define PALMAS_USB_VBUS_INT_EN_LO_CLR 0x0C
2339#define PALMAS_USB_VBUS_INT_EN_HI_SET 0x0D
2340#define PALMAS_USB_VBUS_INT_EN_HI_CLR 0x0E
2341#define PALMAS_USB_ID_INT_SRC 0x0F
2945fbc2
GG		 2342#define PALMAS_USB_ID_INT_LATCH_SET 0x10
2343#define PALMAS_USB_ID_INT_LATCH_CLR 0x11
2344#define PALMAS_USB_ID_INT_EN_LO_SET 0x12
2345#define PALMAS_USB_ID_INT_EN_LO_CLR 0x13
2346#define PALMAS_USB_ID_INT_EN_HI_SET 0x14
2347#define PALMAS_USB_ID_INT_EN_HI_CLR 0x15
2348#define PALMAS_USB_OTG_ADP_CTRL 0x16
2349#define PALMAS_USB_OTG_ADP_HIGH 0x17
2350#define PALMAS_USB_OTG_ADP_LOW 0x18
2351#define PALMAS_USB_OTG_ADP_RISE 0x19
2352#define PALMAS_USB_OTG_REVISION 0x1A
2353
2354/* Bit definitions for USB_WAKEUP */
2355#define PALMAS_USB_WAKEUP_ID_WK_UP_COMP 0x01
45ac60c0 2356#define PALMAS_USB_WAKEUP_ID_WK_UP_COMP_SHIFT 0x00
2945fbc2
GG		 2357
2358/* Bit definitions for USB_VBUS_CTRL_SET */
2359#define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS 0x80
45ac60c0 2360#define PALMAS_USB_VBUS_CTRL_SET_VBUS_CHRG_VSYS_SHIFT 0x07
2945fbc2 2361#define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG 0x20
45ac60c0 2362#define PALMAS_USB_VBUS_CTRL_SET_VBUS_DISCHRG_SHIFT 0x05
2945fbc2 2363#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC 0x10
45ac60c0 2364#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SRC_SHIFT 0x04
2945fbc2 2365#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK 0x08
45ac60c0 2366#define PALMAS_USB_VBUS_CTRL_SET_VBUS_IADP_SINK_SHIFT 0x03
2945fbc2 2367#define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP 0x04
45ac60c0 2368#define PALMAS_USB_VBUS_CTRL_SET_VBUS_ACT_COMP_SHIFT 0x02
2945fbc2
GG		 2369
2370/* Bit definitions for USB_VBUS_CTRL_CLR */
2371#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS 0x80
45ac60c0 2372#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_CHRG_VSYS_SHIFT 0x07
2945fbc2 2373#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG 0x20
45ac60c0 2374#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_DISCHRG_SHIFT 0x05
2945fbc2 2375#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC 0x10
45ac60c0 2376#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SRC_SHIFT 0x04
2945fbc2 2377#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK 0x08
45ac60c0 2378#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_IADP_SINK_SHIFT 0x03
2945fbc2 2379#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP 0x04
45ac60c0 2380#define PALMAS_USB_VBUS_CTRL_CLR_VBUS_ACT_COMP_SHIFT 0x02
2945fbc2
GG		 2381
2382/* Bit definitions for USB_ID_CTRL_SET */
2383#define PALMAS_USB_ID_CTRL_SET_ID_PU_220K 0x80
45ac60c0 2384#define PALMAS_USB_ID_CTRL_SET_ID_PU_220K_SHIFT 0x07
2945fbc2 2385#define PALMAS_USB_ID_CTRL_SET_ID_PU_100K 0x40
45ac60c0 2386#define PALMAS_USB_ID_CTRL_SET_ID_PU_100K_SHIFT 0x06
2945fbc2 2387#define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV 0x20
45ac60c0 2388#define PALMAS_USB_ID_CTRL_SET_ID_GND_DRV_SHIFT 0x05
2945fbc2 2389#define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U 0x10
45ac60c0 2390#define PALMAS_USB_ID_CTRL_SET_ID_SRC_16U_SHIFT 0x04
2945fbc2 2391#define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U 0x08
45ac60c0 2392#define PALMAS_USB_ID_CTRL_SET_ID_SRC_5U_SHIFT 0x03
2945fbc2 2393#define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP 0x04
45ac60c0 2394#define PALMAS_USB_ID_CTRL_SET_ID_ACT_COMP_SHIFT 0x02
2945fbc2
GG		 2395
2396/* Bit definitions for USB_ID_CTRL_CLEAR */
2397#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K 0x80
45ac60c0 2398#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_220K_SHIFT 0x07
2945fbc2 2399#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K 0x40
45ac60c0 2400#define PALMAS_USB_ID_CTRL_CLEAR_ID_PU_100K_SHIFT 0x06
2945fbc2 2401#define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV 0x20
45ac60c0 2402#define PALMAS_USB_ID_CTRL_CLEAR_ID_GND_DRV_SHIFT 0x05
2945fbc2 2403#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U 0x10
45ac60c0 2404#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_16U_SHIFT 0x04
2945fbc2 2405#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U 0x08
45ac60c0 2406#define PALMAS_USB_ID_CTRL_CLEAR_ID_SRC_5U_SHIFT 0x03
2945fbc2 2407#define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP 0x04
45ac60c0 2408#define PALMAS_USB_ID_CTRL_CLEAR_ID_ACT_COMP_SHIFT 0x02
2945fbc2
GG		 2409
2410/* Bit definitions for USB_VBUS_INT_SRC */
2411#define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD 0x80
45ac60c0 2412#define PALMAS_USB_VBUS_INT_SRC_VOTG_SESS_VLD_SHIFT 0x07
2945fbc2 2413#define PALMAS_USB_VBUS_INT_SRC_VADP_PRB 0x40
45ac60c0 2414#define PALMAS_USB_VBUS_INT_SRC_VADP_PRB_SHIFT 0x06
2945fbc2 2415#define PALMAS_USB_VBUS_INT_SRC_VADP_SNS 0x20
45ac60c0 2416#define PALMAS_USB_VBUS_INT_SRC_VADP_SNS_SHIFT 0x05
2945fbc2 2417#define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD 0x08
45ac60c0 2418#define PALMAS_USB_VBUS_INT_SRC_VA_VBUS_VLD_SHIFT 0x03
2945fbc2 2419#define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD 0x04
45ac60c0 2420#define PALMAS_USB_VBUS_INT_SRC_VA_SESS_VLD_SHIFT 0x02
2945fbc2 2421#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD 0x02
45ac60c0 2422#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_VLD_SHIFT 0x01
2945fbc2 2423#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END 0x01
45ac60c0 2424#define PALMAS_USB_VBUS_INT_SRC_VB_SESS_END_SHIFT 0x00
2945fbc2
GG		 2425
2426/* Bit definitions for USB_VBUS_INT_LATCH_SET */
2427#define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD 0x80
45ac60c0 2428#define PALMAS_USB_VBUS_INT_LATCH_SET_VOTG_SESS_VLD_SHIFT 0x07
2945fbc2 2429#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB 0x40
45ac60c0 2430#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_PRB_SHIFT 0x06
2945fbc2 2431#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS 0x20
45ac60c0 2432#define PALMAS_USB_VBUS_INT_LATCH_SET_VADP_SNS_SHIFT 0x05
2945fbc2 2433#define PALMAS_USB_VBUS_INT_LATCH_SET_ADP 0x10
45ac60c0 2434#define PALMAS_USB_VBUS_INT_LATCH_SET_ADP_SHIFT 0x04
2945fbc2 2435#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD 0x08
45ac60c0 2436#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_VBUS_VLD_SHIFT 0x03
2945fbc2 2437#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD 0x04
45ac60c0 2438#define PALMAS_USB_VBUS_INT_LATCH_SET_VA_SESS_VLD_SHIFT 0x02
2945fbc2 2439#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD 0x02
45ac60c0 2440#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_VLD_SHIFT 0x01
2945fbc2 2441#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END 0x01
45ac60c0 2442#define PALMAS_USB_VBUS_INT_LATCH_SET_VB_SESS_END_SHIFT 0x00
2945fbc2
GG		 2443
2444/* Bit definitions for USB_VBUS_INT_LATCH_CLR */
2445#define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD 0x80
45ac60c0 2446#define PALMAS_USB_VBUS_INT_LATCH_CLR_VOTG_SESS_VLD_SHIFT 0x07
2945fbc2 2447#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB 0x40
45ac60c0 2448#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_PRB_SHIFT 0x06
2945fbc2 2449#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS 0x20
45ac60c0 2450#define PALMAS_USB_VBUS_INT_LATCH_CLR_VADP_SNS_SHIFT 0x05
2945fbc2 2451#define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP 0x10
45ac60c0 2452#define PALMAS_USB_VBUS_INT_LATCH_CLR_ADP_SHIFT 0x04
2945fbc2 2453#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD 0x08
45ac60c0 2454#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_VBUS_VLD_SHIFT 0x03
2945fbc2 2455#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD 0x04
45ac60c0 2456#define PALMAS_USB_VBUS_INT_LATCH_CLR_VA_SESS_VLD_SHIFT 0x02
2945fbc2 2457#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD 0x02
45ac60c0 2458#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_VLD_SHIFT 0x01
2945fbc2 2459#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END 0x01
45ac60c0 2460#define PALMAS_USB_VBUS_INT_LATCH_CLR_VB_SESS_END_SHIFT 0x00
2945fbc2
GG		 2461
2462/* Bit definitions for USB_VBUS_INT_EN_LO_SET */
2463#define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD 0x80
45ac60c0 2464#define PALMAS_USB_VBUS_INT_EN_LO_SET_VOTG_SESS_VLD_SHIFT 0x07
2945fbc2 2465#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB 0x40
45ac60c0 2466#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_PRB_SHIFT 0x06
2945fbc2 2467#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS 0x20
45ac60c0 2468#define PALMAS_USB_VBUS_INT_EN_LO_SET_VADP_SNS_SHIFT 0x05
2945fbc2 2469#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD 0x08
45ac60c0 2470#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_VBUS_VLD_SHIFT 0x03
2945fbc2 2471#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD 0x04
45ac60c0 2472#define PALMAS_USB_VBUS_INT_EN_LO_SET_VA_SESS_VLD_SHIFT 0x02
2945fbc2 2473#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD 0x02
45ac60c0 2474#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_VLD_SHIFT 0x01
2945fbc2 2475#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END 0x01
45ac60c0 2476#define PALMAS_USB_VBUS_INT_EN_LO_SET_VB_SESS_END_SHIFT 0x00
2945fbc2
GG		 2477
2478/* Bit definitions for USB_VBUS_INT_EN_LO_CLR */
2479#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD 0x80
45ac60c0 2480#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VOTG_SESS_VLD_SHIFT 0x07
2945fbc2 2481#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB 0x40
45ac60c0 2482#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_PRB_SHIFT 0x06
2945fbc2 2483#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS 0x20
45ac60c0 2484#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VADP_SNS_SHIFT 0x05
2945fbc2 2485#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD 0x08
45ac60c0 2486#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_VBUS_VLD_SHIFT 0x03
2945fbc2 2487#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD 0x04
45ac60c0 2488#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VA_SESS_VLD_SHIFT 0x02
2945fbc2 2489#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD 0x02
45ac60c0 2490#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_VLD_SHIFT 0x01
2945fbc2 2491#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END 0x01
45ac60c0 2492#define PALMAS_USB_VBUS_INT_EN_LO_CLR_VB_SESS_END_SHIFT 0x00
2945fbc2
GG		 2493
2494/* Bit definitions for USB_VBUS_INT_EN_HI_SET */
2495#define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD 0x80
45ac60c0 2496#define PALMAS_USB_VBUS_INT_EN_HI_SET_VOTG_SESS_VLD_SHIFT 0x07
2945fbc2 2497#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB 0x40
45ac60c0 2498#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_PRB_SHIFT 0x06
2945fbc2 2499#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS 0x20
45ac60c0 2500#define PALMAS_USB_VBUS_INT_EN_HI_SET_VADP_SNS_SHIFT 0x05
2945fbc2 2501#define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP 0x10
45ac60c0 2502#define PALMAS_USB_VBUS_INT_EN_HI_SET_ADP_SHIFT 0x04
2945fbc2 2503#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD 0x08
45ac60c0 2504#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_VBUS_VLD_SHIFT 0x03
2945fbc2 2505#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD 0x04
45ac60c0 2506#define PALMAS_USB_VBUS_INT_EN_HI_SET_VA_SESS_VLD_SHIFT 0x02
2945fbc2 2507#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD 0x02
45ac60c0 2508#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_VLD_SHIFT 0x01
2945fbc2 2509#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END 0x01
45ac60c0 2510#define PALMAS_USB_VBUS_INT_EN_HI_SET_VB_SESS_END_SHIFT 0x00
2945fbc2
GG		 2511
2512/* Bit definitions for USB_VBUS_INT_EN_HI_CLR */
2513#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD 0x80
45ac60c0 2514#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VOTG_SESS_VLD_SHIFT 0x07
2945fbc2 2515#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB 0x40
45ac60c0 2516#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_PRB_SHIFT 0x06
2945fbc2 2517#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS 0x20
45ac60c0 2518#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VADP_SNS_SHIFT 0x05
2945fbc2 2519#define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP 0x10
45ac60c0 2520#define PALMAS_USB_VBUS_INT_EN_HI_CLR_ADP_SHIFT 0x04
2945fbc2 2521#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD 0x08
45ac60c0 2522#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_VBUS_VLD_SHIFT 0x03
2945fbc2 2523#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD 0x04
45ac60c0 2524#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VA_SESS_VLD_SHIFT 0x02
2945fbc2 2525#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD 0x02
45ac60c0 2526#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_VLD_SHIFT 0x01
2945fbc2 2527#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END 0x01
45ac60c0 2528#define PALMAS_USB_VBUS_INT_EN_HI_CLR_VB_SESS_END_SHIFT 0x00
2945fbc2
GG		 2529
2530/* Bit definitions for USB_ID_INT_SRC */
2531#define PALMAS_USB_ID_INT_SRC_ID_FLOAT 0x10
45ac60c0 2532#define PALMAS_USB_ID_INT_SRC_ID_FLOAT_SHIFT 0x04
2945fbc2 2533#define PALMAS_USB_ID_INT_SRC_ID_A 0x08
45ac60c0 2534#define PALMAS_USB_ID_INT_SRC_ID_A_SHIFT 0x03
2945fbc2 2535#define PALMAS_USB_ID_INT_SRC_ID_B 0x04
45ac60c0 2536#define PALMAS_USB_ID_INT_SRC_ID_B_SHIFT 0x02
2945fbc2 2537#define PALMAS_USB_ID_INT_SRC_ID_C 0x02
45ac60c0 2538#define PALMAS_USB_ID_INT_SRC_ID_C_SHIFT 0x01
2945fbc2 2539#define PALMAS_USB_ID_INT_SRC_ID_GND 0x01
45ac60c0 2540#define PALMAS_USB_ID_INT_SRC_ID_GND_SHIFT 0x00
2945fbc2
GG		 2541
2542/* Bit definitions for USB_ID_INT_LATCH_SET */
2543#define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT 0x10
45ac60c0 2544#define PALMAS_USB_ID_INT_LATCH_SET_ID_FLOAT_SHIFT 0x04
2945fbc2 2545#define PALMAS_USB_ID_INT_LATCH_SET_ID_A 0x08
45ac60c0 2546#define PALMAS_USB_ID_INT_LATCH_SET_ID_A_SHIFT 0x03
2945fbc2 2547#define PALMAS_USB_ID_INT_LATCH_SET_ID_B 0x04
45ac60c0 2548#define PALMAS_USB_ID_INT_LATCH_SET_ID_B_SHIFT 0x02
2945fbc2 2549#define PALMAS_USB_ID_INT_LATCH_SET_ID_C 0x02
45ac60c0 2550#define PALMAS_USB_ID_INT_LATCH_SET_ID_C_SHIFT 0x01
2945fbc2 2551#define PALMAS_USB_ID_INT_LATCH_SET_ID_GND 0x01
45ac60c0 2552#define PALMAS_USB_ID_INT_LATCH_SET_ID_GND_SHIFT 0x00
2945fbc2
GG		 2553
2554/* Bit definitions for USB_ID_INT_LATCH_CLR */
2555#define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT 0x10
45ac60c0 2556#define PALMAS_USB_ID_INT_LATCH_CLR_ID_FLOAT_SHIFT 0x04
2945fbc2 2557#define PALMAS_USB_ID_INT_LATCH_CLR_ID_A 0x08
45ac60c0 2558#define PALMAS_USB_ID_INT_LATCH_CLR_ID_A_SHIFT 0x03
2945fbc2 2559#define PALMAS_USB_ID_INT_LATCH_CLR_ID_B 0x04
45ac60c0 2560#define PALMAS_USB_ID_INT_LATCH_CLR_ID_B_SHIFT 0x02
2945fbc2 2561#define PALMAS_USB_ID_INT_LATCH_CLR_ID_C 0x02
45ac60c0 2562#define PALMAS_USB_ID_INT_LATCH_CLR_ID_C_SHIFT 0x01
2945fbc2 2563#define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND 0x01
45ac60c0 2564#define PALMAS_USB_ID_INT_LATCH_CLR_ID_GND_SHIFT 0x00
2945fbc2
GG		 2565
2566/* Bit definitions for USB_ID_INT_EN_LO_SET */
2567#define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT 0x10
45ac60c0 2568#define PALMAS_USB_ID_INT_EN_LO_SET_ID_FLOAT_SHIFT 0x04
2945fbc2 2569#define PALMAS_USB_ID_INT_EN_LO_SET_ID_A 0x08
45ac60c0 2570#define PALMAS_USB_ID_INT_EN_LO_SET_ID_A_SHIFT 0x03
2945fbc2 2571#define PALMAS_USB_ID_INT_EN_LO_SET_ID_B 0x04
45ac60c0 2572#define PALMAS_USB_ID_INT_EN_LO_SET_ID_B_SHIFT 0x02
2945fbc2 2573#define PALMAS_USB_ID_INT_EN_LO_SET_ID_C 0x02
45ac60c0 2574#define PALMAS_USB_ID_INT_EN_LO_SET_ID_C_SHIFT 0x01
2945fbc2 2575#define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND 0x01
45ac60c0 2576#define PALMAS_USB_ID_INT_EN_LO_SET_ID_GND_SHIFT 0x00
2945fbc2
GG		 2577
2578/* Bit definitions for USB_ID_INT_EN_LO_CLR */
2579#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT 0x10
45ac60c0 2580#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_FLOAT_SHIFT 0x04
2945fbc2 2581#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A 0x08
45ac60c0 2582#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_A_SHIFT 0x03
2945fbc2 2583#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B 0x04
45ac60c0 2584#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_B_SHIFT 0x02
2945fbc2 2585#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C 0x02
45ac60c0 2586#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_C_SHIFT 0x01
2945fbc2 2587#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND 0x01
45ac60c0 2588#define PALMAS_USB_ID_INT_EN_LO_CLR_ID_GND_SHIFT 0x00
2945fbc2
GG		 2589
2590/* Bit definitions for USB_ID_INT_EN_HI_SET */
2591#define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT 0x10
45ac60c0 2592#define PALMAS_USB_ID_INT_EN_HI_SET_ID_FLOAT_SHIFT 0x04
2945fbc2 2593#define PALMAS_USB_ID_INT_EN_HI_SET_ID_A 0x08
45ac60c0 2594#define PALMAS_USB_ID_INT_EN_HI_SET_ID_A_SHIFT 0x03
2945fbc2 2595#define PALMAS_USB_ID_INT_EN_HI_SET_ID_B 0x04
45ac60c0 2596#define PALMAS_USB_ID_INT_EN_HI_SET_ID_B_SHIFT 0x02
2945fbc2 2597#define PALMAS_USB_ID_INT_EN_HI_SET_ID_C 0x02
45ac60c0 2598#define PALMAS_USB_ID_INT_EN_HI_SET_ID_C_SHIFT 0x01
2945fbc2 2599#define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND 0x01
45ac60c0 2600#define PALMAS_USB_ID_INT_EN_HI_SET_ID_GND_SHIFT 0x00
2945fbc2
GG		 2601
2602/* Bit definitions for USB_ID_INT_EN_HI_CLR */
2603#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT 0x10
45ac60c0 2604#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_FLOAT_SHIFT 0x04
2945fbc2 2605#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A 0x08
45ac60c0 2606#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_A_SHIFT 0x03
2945fbc2 2607#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B 0x04
45ac60c0 2608#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_B_SHIFT 0x02
2945fbc2 2609#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C 0x02
45ac60c0 2610#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_C_SHIFT 0x01
2945fbc2 2611#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND 0x01
45ac60c0 2612#define PALMAS_USB_ID_INT_EN_HI_CLR_ID_GND_SHIFT 0x00
2945fbc2
GG		 2613
2614/* Bit definitions for USB_OTG_ADP_CTRL */
2615#define PALMAS_USB_OTG_ADP_CTRL_ADP_EN 0x04
45ac60c0 2616#define PALMAS_USB_OTG_ADP_CTRL_ADP_EN_SHIFT 0x02
2945fbc2 2617#define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_MASK 0x03
45ac60c0 2618#define PALMAS_USB_OTG_ADP_CTRL_ADP_MODE_SHIFT 0x00
2945fbc2
GG		 2619
2620/* Bit definitions for USB_OTG_ADP_HIGH */
45ac60c0
K		 2621#define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_MASK 0xFF
2622#define PALMAS_USB_OTG_ADP_HIGH_T_ADP_HIGH_SHIFT 0x00
2945fbc2
GG		 2623
2624/* Bit definitions for USB_OTG_ADP_LOW */
45ac60c0
K		 2625#define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_MASK 0xFF
2626#define PALMAS_USB_OTG_ADP_LOW_T_ADP_LOW_SHIFT 0x00
2945fbc2
GG		 2627
2628/* Bit definitions for USB_OTG_ADP_RISE */
45ac60c0
K		 2629#define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_MASK 0xFF
2630#define PALMAS_USB_OTG_ADP_RISE_T_ADP_RISE_SHIFT 0x00
2945fbc2
GG		 2631
2632/* Bit definitions for USB_OTG_REVISION */
2633#define PALMAS_USB_OTG_REVISION_OTG_REV 0x01
45ac60c0 2634#define PALMAS_USB_OTG_REVISION_OTG_REV_SHIFT 0x00
2945fbc2
GG		 2635
2636/* Registers for function VIBRATOR */
45ac60c0 2637#define PALMAS_VIBRA_CTRL 0x00
2945fbc2
GG		 2638
2639/* Bit definitions for VIBRA_CTRL */
2640#define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_MASK 0x06
45ac60c0 2641#define PALMAS_VIBRA_CTRL_PWM_DUTY_SEL_SHIFT 0x01
2945fbc2 2642#define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL 0x01
45ac60c0 2643#define PALMAS_VIBRA_CTRL_PWM_FREQ_SEL_SHIFT 0x00
2945fbc2
GG		 2644
2645/* Registers for function GPIO */
45ac60c0
K		 2646#define PALMAS_GPIO_DATA_IN 0x00
2647#define PALMAS_GPIO_DATA_DIR 0x01
2648#define PALMAS_GPIO_DATA_OUT 0x02
2649#define PALMAS_GPIO_DEBOUNCE_EN 0x03
2650#define PALMAS_GPIO_CLEAR_DATA_OUT 0x04
2651#define PALMAS_GPIO_SET_DATA_OUT 0x05
2652#define PALMAS_PU_PD_GPIO_CTRL1 0x06
2653#define PALMAS_PU_PD_GPIO_CTRL2 0x07
2654#define PALMAS_OD_OUTPUT_GPIO_CTRL 0x08
2655#define PALMAS_GPIO_DATA_IN2 0x09
0a8d3e24
LD		 2656#define PALMAS_GPIO_DATA_DIR2 0x0A
2657#define PALMAS_GPIO_DATA_OUT2 0x0B
2658#define PALMAS_GPIO_DEBOUNCE_EN2 0x0C
2659#define PALMAS_GPIO_CLEAR_DATA_OUT2 0x0D
2660#define PALMAS_GPIO_SET_DATA_OUT2 0x0E
2661#define PALMAS_PU_PD_GPIO_CTRL3 0x0F
2662#define PALMAS_PU_PD_GPIO_CTRL4 0x10
2663#define PALMAS_OD_OUTPUT_GPIO_CTRL2 0x11
2945fbc2
GG		 2664
2665/* Bit definitions for GPIO_DATA_IN */
2666#define PALMAS_GPIO_DATA_IN_GPIO_7_IN 0x80
45ac60c0 2667#define PALMAS_GPIO_DATA_IN_GPIO_7_IN_SHIFT 0x07
2945fbc2 2668#define PALMAS_GPIO_DATA_IN_GPIO_6_IN 0x40
45ac60c0 2669#define PALMAS_GPIO_DATA_IN_GPIO_6_IN_SHIFT 0x06
2945fbc2 2670#define PALMAS_GPIO_DATA_IN_GPIO_5_IN 0x20
45ac60c0 2671#define PALMAS_GPIO_DATA_IN_GPIO_5_IN_SHIFT 0x05
2945fbc2 2672#define PALMAS_GPIO_DATA_IN_GPIO_4_IN 0x10
45ac60c0 2673#define PALMAS_GPIO_DATA_IN_GPIO_4_IN_SHIFT 0x04
2945fbc2 2674#define PALMAS_GPIO_DATA_IN_GPIO_3_IN 0x08
45ac60c0 2675#define PALMAS_GPIO_DATA_IN_GPIO_3_IN_SHIFT 0x03
2945fbc2 2676#define PALMAS_GPIO_DATA_IN_GPIO_2_IN 0x04
45ac60c0 2677#define PALMAS_GPIO_DATA_IN_GPIO_2_IN_SHIFT 0x02
2945fbc2 2678#define PALMAS_GPIO_DATA_IN_GPIO_1_IN 0x02
45ac60c0 2679#define PALMAS_GPIO_DATA_IN_GPIO_1_IN_SHIFT 0x01
2945fbc2 2680#define PALMAS_GPIO_DATA_IN_GPIO_0_IN 0x01
45ac60c0 2681#define PALMAS_GPIO_DATA_IN_GPIO_0_IN_SHIFT 0x00
2945fbc2
GG		 2682
2683/* Bit definitions for GPIO_DATA_DIR */
2684#define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR 0x80
45ac60c0 2685#define PALMAS_GPIO_DATA_DIR_GPIO_7_DIR_SHIFT 0x07
2945fbc2 2686#define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR 0x40
45ac60c0 2687#define PALMAS_GPIO_DATA_DIR_GPIO_6_DIR_SHIFT 0x06
2945fbc2 2688#define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR 0x20
45ac60c0 2689#define PALMAS_GPIO_DATA_DIR_GPIO_5_DIR_SHIFT 0x05
2945fbc2 2690#define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR 0x10
45ac60c0 2691#define PALMAS_GPIO_DATA_DIR_GPIO_4_DIR_SHIFT 0x04
2945fbc2 2692#define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR 0x08
45ac60c0 2693#define PALMAS_GPIO_DATA_DIR_GPIO_3_DIR_SHIFT 0x03
2945fbc2 2694#define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR 0x04
45ac60c0 2695#define PALMAS_GPIO_DATA_DIR_GPIO_2_DIR_SHIFT 0x02
2945fbc2 2696#define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR 0x02
45ac60c0 2697#define PALMAS_GPIO_DATA_DIR_GPIO_1_DIR_SHIFT 0x01
2945fbc2 2698#define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR 0x01
45ac60c0 2699#define PALMAS_GPIO_DATA_DIR_GPIO_0_DIR_SHIFT 0x00
2945fbc2
GG		 2700
2701/* Bit definitions for GPIO_DATA_OUT */
2702#define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT 0x80
45ac60c0 2703#define PALMAS_GPIO_DATA_OUT_GPIO_7_OUT_SHIFT 0x07
2945fbc2 2704#define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT 0x40
45ac60c0 2705#define PALMAS_GPIO_DATA_OUT_GPIO_6_OUT_SHIFT 0x06
2945fbc2 2706#define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT 0x20
45ac60c0 2707#define PALMAS_GPIO_DATA_OUT_GPIO_5_OUT_SHIFT 0x05
2945fbc2 2708#define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT 0x10
45ac60c0 2709#define PALMAS_GPIO_DATA_OUT_GPIO_4_OUT_SHIFT 0x04
2945fbc2 2710#define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT 0x08
45ac60c0 2711#define PALMAS_GPIO_DATA_OUT_GPIO_3_OUT_SHIFT 0x03
2945fbc2 2712#define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT 0x04
45ac60c0 2713#define PALMAS_GPIO_DATA_OUT_GPIO_2_OUT_SHIFT 0x02
2945fbc2 2714#define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT 0x02
45ac60c0 2715#define PALMAS_GPIO_DATA_OUT_GPIO_1_OUT_SHIFT 0x01
2945fbc2 2716#define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT 0x01
45ac60c0 2717#define PALMAS_GPIO_DATA_OUT_GPIO_0_OUT_SHIFT 0x00
2945fbc2
GG		 2718
2719/* Bit definitions for GPIO_DEBOUNCE_EN */
2720#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN 0x80
45ac60c0 2721#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_7_DEBOUNCE_EN_SHIFT 0x07
2945fbc2 2722#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN 0x40
45ac60c0 2723#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_6_DEBOUNCE_EN_SHIFT 0x06
2945fbc2 2724#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN 0x20
45ac60c0 2725#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_5_DEBOUNCE_EN_SHIFT 0x05
2945fbc2 2726#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN 0x10
45ac60c0 2727#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_4_DEBOUNCE_EN_SHIFT 0x04
2945fbc2 2728#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN 0x08
45ac60c0 2729#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_3_DEBOUNCE_EN_SHIFT 0x03
2945fbc2 2730#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN 0x04
45ac60c0 2731#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_2_DEBOUNCE_EN_SHIFT 0x02
2945fbc2 2732#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN 0x02
45ac60c0 2733#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_1_DEBOUNCE_EN_SHIFT 0x01
2945fbc2 2734#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN 0x01
45ac60c0 2735#define PALMAS_GPIO_DEBOUNCE_EN_GPIO_0_DEBOUNCE_EN_SHIFT 0x00
2945fbc2
GG		 2736
2737/* Bit definitions for GPIO_CLEAR_DATA_OUT */
2738#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT 0x80
45ac60c0 2739#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_7_CLEAR_DATA_OUT_SHIFT 0x07
2945fbc2 2740#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT 0x40
45ac60c0 2741#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_6_CLEAR_DATA_OUT_SHIFT 0x06
2945fbc2 2742#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT 0x20
45ac60c0 2743#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_5_CLEAR_DATA_OUT_SHIFT 0x05
2945fbc2 2744#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT 0x10
45ac60c0 2745#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_4_CLEAR_DATA_OUT_SHIFT 0x04
2945fbc2 2746#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT 0x08
45ac60c0 2747#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_3_CLEAR_DATA_OUT_SHIFT 0x03
2945fbc2 2748#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT 0x04
45ac60c0 2749#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_2_CLEAR_DATA_OUT_SHIFT 0x02
2945fbc2 2750#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT 0x02
45ac60c0 2751#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_1_CLEAR_DATA_OUT_SHIFT 0x01
2945fbc2 2752#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT 0x01
45ac60c0 2753#define PALMAS_GPIO_CLEAR_DATA_OUT_GPIO_0_CLEAR_DATA_OUT_SHIFT 0x00
2945fbc2
GG		 2754
2755/* Bit definitions for GPIO_SET_DATA_OUT */
2756#define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT 0x80
45ac60c0 2757#define PALMAS_GPIO_SET_DATA_OUT_GPIO_7_SET_DATA_OUT_SHIFT 0x07
2945fbc2 2758#define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT 0x40
45ac60c0 2759#define PALMAS_GPIO_SET_DATA_OUT_GPIO_6_SET_DATA_OUT_SHIFT 0x06
2945fbc2 2760#define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT 0x20
45ac60c0 2761#define PALMAS_GPIO_SET_DATA_OUT_GPIO_5_SET_DATA_OUT_SHIFT 0x05
2945fbc2 2762#define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT 0x10
45ac60c0 2763#define PALMAS_GPIO_SET_DATA_OUT_GPIO_4_SET_DATA_OUT_SHIFT 0x04
2945fbc2 2764#define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT 0x08
45ac60c0 2765#define PALMAS_GPIO_SET_DATA_OUT_GPIO_3_SET_DATA_OUT_SHIFT 0x03
2945fbc2 2766#define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT 0x04
45ac60c0 2767#define PALMAS_GPIO_SET_DATA_OUT_GPIO_2_SET_DATA_OUT_SHIFT 0x02
2945fbc2 2768#define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT 0x02
45ac60c0 2769#define PALMAS_GPIO_SET_DATA_OUT_GPIO_1_SET_DATA_OUT_SHIFT 0x01
2945fbc2 2770#define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT 0x01
45ac60c0 2771#define PALMAS_GPIO_SET_DATA_OUT_GPIO_0_SET_DATA_OUT_SHIFT 0x00
2945fbc2
GG		 2772
2773/* Bit definitions for PU_PD_GPIO_CTRL1 */
2774#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD 0x40
45ac60c0 2775#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_3_PD_SHIFT 0x06
2945fbc2 2776#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU 0x20
45ac60c0 2777#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PU_SHIFT 0x05
2945fbc2 2778#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD 0x10
45ac60c0 2779#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_2_PD_SHIFT 0x04
2945fbc2 2780#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU 0x08
45ac60c0 2781#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PU_SHIFT 0x03
2945fbc2 2782#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD 0x04
45ac60c0 2783#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_1_PD_SHIFT 0x02
2945fbc2 2784#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD 0x01
45ac60c0 2785#define PALMAS_PU_PD_GPIO_CTRL1_GPIO_0_PD_SHIFT 0x00
2945fbc2
GG		 2786
2787/* Bit definitions for PU_PD_GPIO_CTRL2 */
2788#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD 0x40
45ac60c0 2789#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_7_PD_SHIFT 0x06
2945fbc2 2790#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU 0x20
45ac60c0 2791#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PU_SHIFT 0x05
2945fbc2 2792#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD 0x10
45ac60c0 2793#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_6_PD_SHIFT 0x04
2945fbc2 2794#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU 0x08
45ac60c0 2795#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PU_SHIFT 0x03
2945fbc2 2796#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD 0x04
45ac60c0 2797#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_5_PD_SHIFT 0x02
2945fbc2 2798#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU 0x02
45ac60c0 2799#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PU_SHIFT 0x01
2945fbc2 2800#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD 0x01
45ac60c0 2801#define PALMAS_PU_PD_GPIO_CTRL2_GPIO_4_PD_SHIFT 0x00
2945fbc2
GG		 2802
2803/* Bit definitions for OD_OUTPUT_GPIO_CTRL */
2804#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD 0x20
45ac60c0 2805#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_5_OD_SHIFT 0x05
2945fbc2 2806#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD 0x04
45ac60c0 2807#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_2_OD_SHIFT 0x02
2945fbc2 2808#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD 0x02
45ac60c0 2809#define PALMAS_OD_OUTPUT_GPIO_CTRL_GPIO_1_OD_SHIFT 0x01
2945fbc2
GG		 2810
2811/* Registers for function GPADC */
45ac60c0
K		 2812#define PALMAS_GPADC_CTRL1 0x00
2813#define PALMAS_GPADC_CTRL2 0x01
2814#define PALMAS_GPADC_RT_CTRL 0x02
2815#define PALMAS_GPADC_AUTO_CTRL 0x03
2816#define PALMAS_GPADC_STATUS 0x04
2817#define PALMAS_GPADC_RT_SELECT 0x05
2818#define PALMAS_GPADC_RT_CONV0_LSB 0x06
2819#define PALMAS_GPADC_RT_CONV0_MSB 0x07
2820#define PALMAS_GPADC_AUTO_SELECT 0x08
2821#define PALMAS_GPADC_AUTO_CONV0_LSB 0x09
2822#define PALMAS_GPADC_AUTO_CONV0_MSB 0x0A
2823#define PALMAS_GPADC_AUTO_CONV1_LSB 0x0B
2824#define PALMAS_GPADC_AUTO_CONV1_MSB 0x0C
2825#define PALMAS_GPADC_SW_SELECT 0x0D
2826#define PALMAS_GPADC_SW_CONV0_LSB 0x0E
2827#define PALMAS_GPADC_SW_CONV0_MSB 0x0F
2945fbc2
GG		 2828#define PALMAS_GPADC_THRES_CONV0_LSB 0x10
2829#define PALMAS_GPADC_THRES_CONV0_MSB 0x11
2830#define PALMAS_GPADC_THRES_CONV1_LSB 0x12
2831#define PALMAS_GPADC_THRES_CONV1_MSB 0x13
2832#define PALMAS_GPADC_SMPS_ILMONITOR_EN 0x14
2833#define PALMAS_GPADC_SMPS_VSEL_MONITORING 0x15
2834
2835/* Bit definitions for GPADC_CTRL1 */
2836#define PALMAS_GPADC_CTRL1_RESERVED_MASK 0xc0
45ac60c0 2837#define PALMAS_GPADC_CTRL1_RESERVED_SHIFT 0x06
2945fbc2 2838#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_MASK 0x30
45ac60c0 2839#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH3_SHIFT 0x04
2945fbc2 2840#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_MASK 0x0c
45ac60c0 2841#define PALMAS_GPADC_CTRL1_CURRENT_SRC_CH0_SHIFT 0x02
2945fbc2 2842#define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET 0x02
45ac60c0 2843#define PALMAS_GPADC_CTRL1_BAT_REMOVAL_DET_SHIFT 0x01
2945fbc2 2844#define PALMAS_GPADC_CTRL1_GPADC_FORCE 0x01
45ac60c0 2845#define PALMAS_GPADC_CTRL1_GPADC_FORCE_SHIFT 0x00
2945fbc2
GG		 2846
2847/* Bit definitions for GPADC_CTRL2 */
2848#define PALMAS_GPADC_CTRL2_RESERVED_MASK 0x06
45ac60c0 2849#define PALMAS_GPADC_CTRL2_RESERVED_SHIFT 0x01
2945fbc2
GG		 2850
2851/* Bit definitions for GPADC_RT_CTRL */
2852#define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY 0x02
45ac60c0 2853#define PALMAS_GPADC_RT_CTRL_EXTEND_DELAY_SHIFT 0x01
2945fbc2 2854#define PALMAS_GPADC_RT_CTRL_START_POLARITY 0x01
45ac60c0 2855#define PALMAS_GPADC_RT_CTRL_START_POLARITY_SHIFT 0x00
2945fbc2
GG		 2856
2857/* Bit definitions for GPADC_AUTO_CTRL */
2858#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1 0x80
45ac60c0 2859#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV1_SHIFT 0x07
2945fbc2 2860#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0 0x40
45ac60c0 2861#define PALMAS_GPADC_AUTO_CTRL_SHUTDOWN_CONV0_SHIFT 0x06
2945fbc2 2862#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN 0x20
45ac60c0 2863#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV1_EN_SHIFT 0x05
2945fbc2 2864#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN 0x10
45ac60c0
K		 2865#define PALMAS_GPADC_AUTO_CTRL_AUTO_CONV0_EN_SHIFT 0x04
2866#define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_MASK 0x0F
2867#define PALMAS_GPADC_AUTO_CTRL_COUNTER_CONV_SHIFT 0x00
2945fbc2
GG		 2868
2869/* Bit definitions for GPADC_STATUS */
2870#define PALMAS_GPADC_STATUS_GPADC_AVAILABLE 0x10
45ac60c0 2871#define PALMAS_GPADC_STATUS_GPADC_AVAILABLE_SHIFT 0x04
2945fbc2
GG		 2872
2873/* Bit definitions for GPADC_RT_SELECT */
2874#define PALMAS_GPADC_RT_SELECT_RT_CONV_EN 0x80
45ac60c0
K		 2875#define PALMAS_GPADC_RT_SELECT_RT_CONV_EN_SHIFT 0x07
2876#define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_MASK 0x0F
2877#define PALMAS_GPADC_RT_SELECT_RT_CONV0_SEL_SHIFT 0x00
2945fbc2
GG		 2878
2879/* Bit definitions for GPADC_RT_CONV0_LSB */
45ac60c0
K		 2880#define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_MASK 0xFF
2881#define PALMAS_GPADC_RT_CONV0_LSB_RT_CONV0_LSB_SHIFT 0x00
2945fbc2
GG		 2882
2883/* Bit definitions for GPADC_RT_CONV0_MSB */
45ac60c0
K		 2884#define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_MASK 0x0F
2885#define PALMAS_GPADC_RT_CONV0_MSB_RT_CONV0_MSB_SHIFT 0x00
2945fbc2
GG		 2886
2887/* Bit definitions for GPADC_AUTO_SELECT */
45ac60c0
K		 2888#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_MASK 0xF0
2889#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV1_SEL_SHIFT 0x04
2890#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_MASK 0x0F
2891#define PALMAS_GPADC_AUTO_SELECT_AUTO_CONV0_SEL_SHIFT 0x00
2945fbc2
GG		 2892
2893/* Bit definitions for GPADC_AUTO_CONV0_LSB */
45ac60c0
K		 2894#define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_MASK 0xFF
2895#define PALMAS_GPADC_AUTO_CONV0_LSB_AUTO_CONV0_LSB_SHIFT 0x00
2945fbc2
GG		 2896
2897/* Bit definitions for GPADC_AUTO_CONV0_MSB */
45ac60c0
K		 2898#define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_MASK 0x0F
2899#define PALMAS_GPADC_AUTO_CONV0_MSB_AUTO_CONV0_MSB_SHIFT 0x00
2945fbc2
GG		 2900
2901/* Bit definitions for GPADC_AUTO_CONV1_LSB */
45ac60c0
K		 2902#define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_MASK 0xFF
2903#define PALMAS_GPADC_AUTO_CONV1_LSB_AUTO_CONV1_LSB_SHIFT 0x00
2945fbc2
GG		 2904
2905/* Bit definitions for GPADC_AUTO_CONV1_MSB */
45ac60c0
K		 2906#define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_MASK 0x0F
2907#define PALMAS_GPADC_AUTO_CONV1_MSB_AUTO_CONV1_MSB_SHIFT 0x00
2945fbc2
GG		 2908
2909/* Bit definitions for GPADC_SW_SELECT */
2910#define PALMAS_GPADC_SW_SELECT_SW_CONV_EN 0x80
45ac60c0 2911#define PALMAS_GPADC_SW_SELECT_SW_CONV_EN_SHIFT 0x07
2945fbc2 2912#define PALMAS_GPADC_SW_SELECT_SW_START_CONV0 0x10
45ac60c0
K		 2913#define PALMAS_GPADC_SW_SELECT_SW_START_CONV0_SHIFT 0x04
2914#define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_MASK 0x0F
2915#define PALMAS_GPADC_SW_SELECT_SW_CONV0_SEL_SHIFT 0x00
2945fbc2
GG		 2916
2917/* Bit definitions for GPADC_SW_CONV0_LSB */
45ac60c0
K		 2918#define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_MASK 0xFF
2919#define PALMAS_GPADC_SW_CONV0_LSB_SW_CONV0_LSB_SHIFT 0x00
2945fbc2
GG		 2920
2921/* Bit definitions for GPADC_SW_CONV0_MSB */
45ac60c0
K		 2922#define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_MASK 0x0F
2923#define PALMAS_GPADC_SW_CONV0_MSB_SW_CONV0_MSB_SHIFT 0x00
2945fbc2
GG		 2924
2925/* Bit definitions for GPADC_THRES_CONV0_LSB */
45ac60c0
K		 2926#define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_MASK 0xFF
2927#define PALMAS_GPADC_THRES_CONV0_LSB_THRES_CONV0_LSB_SHIFT 0x00
2945fbc2
GG		 2928
2929/* Bit definitions for GPADC_THRES_CONV0_MSB */
2930#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL 0x80
45ac60c0
K		 2931#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_POL_SHIFT 0x07
2932#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_MASK 0x0F
2933#define PALMAS_GPADC_THRES_CONV0_MSB_THRES_CONV0_MSB_SHIFT 0x00
2945fbc2
GG		 2934
2935/* Bit definitions for GPADC_THRES_CONV1_LSB */
45ac60c0
K		 2936#define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_MASK 0xFF
2937#define PALMAS_GPADC_THRES_CONV1_LSB_THRES_CONV1_LSB_SHIFT 0x00
2945fbc2
GG		 2938
2939/* Bit definitions for GPADC_THRES_CONV1_MSB */
2940#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL 0x80
45ac60c0
K		 2941#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_POL_SHIFT 0x07
2942#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_MASK 0x0F
2943#define PALMAS_GPADC_THRES_CONV1_MSB_THRES_CONV1_MSB_SHIFT 0x00
2945fbc2
GG		 2944
2945/* Bit definitions for GPADC_SMPS_ILMONITOR_EN */
2946#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN 0x20
45ac60c0 2947#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_EN_SHIFT 0x05
2945fbc2 2948#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT 0x10
45ac60c0
K		 2949#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_REXT_SHIFT 0x04
2950#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_MASK 0x0F
2951#define PALMAS_GPADC_SMPS_ILMONITOR_EN_SMPS_ILMON_SEL_SHIFT 0x00
2945fbc2
GG		 2952
2953/* Bit definitions for GPADC_SMPS_VSEL_MONITORING */
2954#define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE 0x80
45ac60c0
K		 2955#define PALMAS_GPADC_SMPS_VSEL_MONITORING_ACTIVE_PHASE_SHIFT 0x07
2956#define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_MASK 0x7F
2957#define PALMAS_GPADC_SMPS_VSEL_MONITORING_SMPS_VSEL_MONITORING_SHIFT 0x00
2945fbc2
GG		 2958
2959/* Registers for function GPADC */
45ac60c0
K		 2960#define PALMAS_GPADC_TRIM1 0x00
2961#define PALMAS_GPADC_TRIM2 0x01
2962#define PALMAS_GPADC_TRIM3 0x02
2963#define PALMAS_GPADC_TRIM4 0x03
2964#define PALMAS_GPADC_TRIM5 0x04
2965#define PALMAS_GPADC_TRIM6 0x05
2966#define PALMAS_GPADC_TRIM7 0x06
2967#define PALMAS_GPADC_TRIM8 0x07
2968#define PALMAS_GPADC_TRIM9 0x08
2969#define PALMAS_GPADC_TRIM10 0x09
2970#define PALMAS_GPADC_TRIM11 0x0A
2971#define PALMAS_GPADC_TRIM12 0x0B
2972#define PALMAS_GPADC_TRIM13 0x0C
2973#define PALMAS_GPADC_TRIM14 0x0D
2974#define PALMAS_GPADC_TRIM15 0x0E
2975#define PALMAS_GPADC_TRIM16 0x0F
2945fbc2 2976
027d7c2a
K		 2977/* TPS65917 Interrupt registers */
2978
2979/* Registers for function INTERRUPT */
2980#define TPS65917_INT1_STATUS 0x00
2981#define TPS65917_INT1_MASK 0x01
2982#define TPS65917_INT1_LINE_STATE 0x02
2983#define TPS65917_INT2_STATUS 0x05
2984#define TPS65917_INT2_MASK 0x06
2985#define TPS65917_INT2_LINE_STATE 0x07
2986#define TPS65917_INT3_STATUS 0x0A
2987#define TPS65917_INT3_MASK 0x0B
2988#define TPS65917_INT3_LINE_STATE 0x0C
2989#define TPS65917_INT4_STATUS 0x0F
2990#define TPS65917_INT4_MASK 0x10
2991#define TPS65917_INT4_LINE_STATE 0x11
2992#define TPS65917_INT4_EDGE_DETECT1 0x12
2993#define TPS65917_INT4_EDGE_DETECT2 0x13
2994#define TPS65917_INT_CTRL 0x14
2995
2996/* Bit definitions for INT1_STATUS */
2997#define TPS65917_INT1_STATUS_VSYS_MON 0x40
2998#define TPS65917_INT1_STATUS_VSYS_MON_SHIFT 0x06
2999#define TPS65917_INT1_STATUS_HOTDIE 0x20
3000#define TPS65917_INT1_STATUS_HOTDIE_SHIFT 0x05
3001#define TPS65917_INT1_STATUS_PWRDOWN 0x10
3002#define TPS65917_INT1_STATUS_PWRDOWN_SHIFT 0x04
3003#define TPS65917_INT1_STATUS_LONG_PRESS_KEY 0x04
3004#define TPS65917_INT1_STATUS_LONG_PRESS_KEY_SHIFT 0x02
3005#define TPS65917_INT1_STATUS_PWRON 0x02
3006#define TPS65917_INT1_STATUS_PWRON_SHIFT 0x01
3007
3008/* Bit definitions for INT1_MASK */
3009#define TPS65917_INT1_MASK_VSYS_MON 0x40
3010#define TPS65917_INT1_MASK_VSYS_MON_SHIFT 0x06
3011#define TPS65917_INT1_MASK_HOTDIE 0x20
3012#define TPS65917_INT1_MASK_HOTDIE_SHIFT 0x05
3013#define TPS65917_INT1_MASK_PWRDOWN 0x10
3014#define TPS65917_INT1_MASK_PWRDOWN_SHIFT 0x04
3015#define TPS65917_INT1_MASK_LONG_PRESS_KEY 0x04
3016#define TPS65917_INT1_MASK_LONG_PRESS_KEY_SHIFT 0x02
3017#define TPS65917_INT1_MASK_PWRON 0x02
3018#define TPS65917_INT1_MASK_PWRON_SHIFT 0x01
3019
3020/* Bit definitions for INT1_LINE_STATE */
3021#define TPS65917_INT1_LINE_STATE_VSYS_MON 0x40
3022#define TPS65917_INT1_LINE_STATE_VSYS_MON_SHIFT 0x06
3023#define TPS65917_INT1_LINE_STATE_HOTDIE 0x20
3024#define TPS65917_INT1_LINE_STATE_HOTDIE_SHIFT 0x05
3025#define TPS65917_INT1_LINE_STATE_PWRDOWN 0x10
3026#define TPS65917_INT1_LINE_STATE_PWRDOWN_SHIFT 0x04
3027#define TPS65917_INT1_LINE_STATE_LONG_PRESS_KEY 0x04
3028#define TPS65917_INT1_LINE_STATE_LONG_PRESS_KEY_SHIFT 0x02
3029#define TPS65917_INT1_LINE_STATE_PWRON 0x02
3030#define TPS65917_INT1_LINE_STATE_PWRON_SHIFT 0x01
3031
3032/* Bit definitions for INT2_STATUS */
3033#define TPS65917_INT2_STATUS_SHORT 0x40
3034#define TPS65917_INT2_STATUS_SHORT_SHIFT 0x06
3035#define TPS65917_INT2_STATUS_FSD 0x20
3036#define TPS65917_INT2_STATUS_FSD_SHIFT 0x05
3037#define TPS65917_INT2_STATUS_RESET_IN 0x10
3038#define TPS65917_INT2_STATUS_RESET_IN_SHIFT 0x04
3039#define TPS65917_INT2_STATUS_WDT 0x04
3040#define TPS65917_INT2_STATUS_WDT_SHIFT 0x02
3041#define TPS65917_INT2_STATUS_OTP_ERROR 0x02
3042#define TPS65917_INT2_STATUS_OTP_ERROR_SHIFT 0x01
3043
3044/* Bit definitions for INT2_MASK */
3045#define TPS65917_INT2_MASK_SHORT 0x40
3046#define TPS65917_INT2_MASK_SHORT_SHIFT 0x06
3047#define TPS65917_INT2_MASK_FSD 0x20
3048#define TPS65917_INT2_MASK_FSD_SHIFT 0x05
3049#define TPS65917_INT2_MASK_RESET_IN 0x10
3050#define TPS65917_INT2_MASK_RESET_IN_SHIFT 0x04
3051#define TPS65917_INT2_MASK_WDT 0x04
3052#define TPS65917_INT2_MASK_WDT_SHIFT 0x02
3053#define TPS65917_INT2_MASK_OTP_ERROR_TIMER 0x02
3054#define TPS65917_INT2_MASK_OTP_ERROR_SHIFT 0x01
3055
3056/* Bit definitions for INT2_LINE_STATE */
3057#define TPS65917_INT2_LINE_STATE_SHORT 0x40
3058#define TPS65917_INT2_LINE_STATE_SHORT_SHIFT 0x06
3059#define TPS65917_INT2_LINE_STATE_FSD 0x20
3060#define TPS65917_INT2_LINE_STATE_FSD_SHIFT 0x05
3061#define TPS65917_INT2_LINE_STATE_RESET_IN 0x10
3062#define TPS65917_INT2_LINE_STATE_RESET_IN_SHIFT 0x04
3063#define TPS65917_INT2_LINE_STATE_WDT 0x04
3064#define TPS65917_INT2_LINE_STATE_WDT_SHIFT 0x02
3065#define TPS65917_INT2_LINE_STATE_OTP_ERROR 0x02
3066#define TPS65917_INT2_LINE_STATE_OTP_ERROR_SHIFT 0x01
3067
3068/* Bit definitions for INT3_STATUS */
3069#define TPS65917_INT3_STATUS_VBUS 0x80
3070#define TPS65917_INT3_STATUS_VBUS_SHIFT 0x07
3071#define TPS65917_INT3_STATUS_GPADC_EOC_SW 0x04
3072#define TPS65917_INT3_STATUS_GPADC_EOC_SW_SHIFT 0x02
3073#define TPS65917_INT3_STATUS_GPADC_AUTO_1 0x02
3074#define TPS65917_INT3_STATUS_GPADC_AUTO_1_SHIFT 0x01
3075#define TPS65917_INT3_STATUS_GPADC_AUTO_0 0x01
3076#define TPS65917_INT3_STATUS_GPADC_AUTO_0_SHIFT 0x00
3077
3078/* Bit definitions for INT3_MASK */
3079#define TPS65917_INT3_MASK_VBUS 0x80
3080#define TPS65917_INT3_MASK_VBUS_SHIFT 0x07
3081#define TPS65917_INT3_MASK_GPADC_EOC_SW 0x04
3082#define TPS65917_INT3_MASK_GPADC_EOC_SW_SHIFT 0x02
3083#define TPS65917_INT3_MASK_GPADC_AUTO_1 0x02
3084#define TPS65917_INT3_MASK_GPADC_AUTO_1_SHIFT 0x01
3085#define TPS65917_INT3_MASK_GPADC_AUTO_0 0x01
3086#define TPS65917_INT3_MASK_GPADC_AUTO_0_SHIFT 0x00
3087
3088/* Bit definitions for INT3_LINE_STATE */
3089#define TPS65917_INT3_LINE_STATE_VBUS 0x80
3090#define TPS65917_INT3_LINE_STATE_VBUS_SHIFT 0x07
3091#define TPS65917_INT3_LINE_STATE_GPADC_EOC_SW 0x04
3092#define TPS65917_INT3_LINE_STATE_GPADC_EOC_SW_SHIFT 0x02
3093#define TPS65917_INT3_LINE_STATE_GPADC_AUTO_1 0x02
3094#define TPS65917_INT3_LINE_STATE_GPADC_AUTO_1_SHIFT 0x01
3095#define TPS65917_INT3_LINE_STATE_GPADC_AUTO_0 0x01
3096#define TPS65917_INT3_LINE_STATE_GPADC_AUTO_0_SHIFT 0x00
3097
3098/* Bit definitions for INT4_STATUS */
3099#define TPS65917_INT4_STATUS_GPIO_6 0x40
3100#define TPS65917_INT4_STATUS_GPIO_6_SHIFT 0x06
3101#define TPS65917_INT4_STATUS_GPIO_5 0x20
3102#define TPS65917_INT4_STATUS_GPIO_5_SHIFT 0x05
3103#define TPS65917_INT4_STATUS_GPIO_4 0x10
3104#define TPS65917_INT4_STATUS_GPIO_4_SHIFT 0x04
3105#define TPS65917_INT4_STATUS_GPIO_3 0x08
3106#define TPS65917_INT4_STATUS_GPIO_3_SHIFT 0x03
3107#define TPS65917_INT4_STATUS_GPIO_2 0x04
3108#define TPS65917_INT4_STATUS_GPIO_2_SHIFT 0x02
3109#define TPS65917_INT4_STATUS_GPIO_1 0x02
3110#define TPS65917_INT4_STATUS_GPIO_1_SHIFT 0x01
3111#define TPS65917_INT4_STATUS_GPIO_0 0x01
3112#define TPS65917_INT4_STATUS_GPIO_0_SHIFT 0x00
3113
3114/* Bit definitions for INT4_MASK */
3115#define TPS65917_INT4_MASK_GPIO_6 0x40
3116#define TPS65917_INT4_MASK_GPIO_6_SHIFT 0x06
3117#define TPS65917_INT4_MASK_GPIO_5 0x20
3118#define TPS65917_INT4_MASK_GPIO_5_SHIFT 0x05
3119#define TPS65917_INT4_MASK_GPIO_4 0x10
3120#define TPS65917_INT4_MASK_GPIO_4_SHIFT 0x04
3121#define TPS65917_INT4_MASK_GPIO_3 0x08
3122#define TPS65917_INT4_MASK_GPIO_3_SHIFT 0x03
3123#define TPS65917_INT4_MASK_GPIO_2 0x04
3124#define TPS65917_INT4_MASK_GPIO_2_SHIFT 0x02
3125#define TPS65917_INT4_MASK_GPIO_1 0x02
3126#define TPS65917_INT4_MASK_GPIO_1_SHIFT 0x01
3127#define TPS65917_INT4_MASK_GPIO_0 0x01
3128#define TPS65917_INT4_MASK_GPIO_0_SHIFT 0x00
3129
3130/* Bit definitions for INT4_LINE_STATE */
3131#define TPS65917_INT4_LINE_STATE_GPIO_6 0x40
3132#define TPS65917_INT4_LINE_STATE_GPIO_6_SHIFT 0x06
3133#define TPS65917_INT4_LINE_STATE_GPIO_5 0x20
3134#define TPS65917_INT4_LINE_STATE_GPIO_5_SHIFT 0x05
3135#define TPS65917_INT4_LINE_STATE_GPIO_4 0x10
3136#define TPS65917_INT4_LINE_STATE_GPIO_4_SHIFT 0x04
3137#define TPS65917_INT4_LINE_STATE_GPIO_3 0x08
3138#define TPS65917_INT4_LINE_STATE_GPIO_3_SHIFT 0x03
3139#define TPS65917_INT4_LINE_STATE_GPIO_2 0x04
3140#define TPS65917_INT4_LINE_STATE_GPIO_2_SHIFT 0x02
3141#define TPS65917_INT4_LINE_STATE_GPIO_1 0x02
3142#define TPS65917_INT4_LINE_STATE_GPIO_1_SHIFT 0x01
3143#define TPS65917_INT4_LINE_STATE_GPIO_0 0x01
3144#define TPS65917_INT4_LINE_STATE_GPIO_0_SHIFT 0x00
3145
3146/* Bit definitions for INT4_EDGE_DETECT1 */
3147#define TPS65917_INT4_EDGE_DETECT1_GPIO_3_RISING 0x80
3148#define TPS65917_INT4_EDGE_DETECT1_GPIO_3_RISING_SHIFT 0x07
3149#define TPS65917_INT4_EDGE_DETECT1_GPIO_3_FALLING 0x40
3150#define TPS65917_INT4_EDGE_DETECT1_GPIO_3_FALLING_SHIFT 0x06
3151#define TPS65917_INT4_EDGE_DETECT1_GPIO_2_RISING 0x20
3152#define TPS65917_INT4_EDGE_DETECT1_GPIO_2_RISING_SHIFT 0x05
3153#define TPS65917_INT4_EDGE_DETECT1_GPIO_2_FALLING 0x10
3154#define TPS65917_INT4_EDGE_DETECT1_GPIO_2_FALLING_SHIFT 0x04
3155#define TPS65917_INT4_EDGE_DETECT1_GPIO_1_RISING 0x08
3156#define TPS65917_INT4_EDGE_DETECT1_GPIO_1_RISING_SHIFT 0x03
3157#define TPS65917_INT4_EDGE_DETECT1_GPIO_1_FALLING 0x04
3158#define TPS65917_INT4_EDGE_DETECT1_GPIO_1_FALLING_SHIFT 0x02
3159#define TPS65917_INT4_EDGE_DETECT1_GPIO_0_RISING 0x02
3160#define TPS65917_INT4_EDGE_DETECT1_GPIO_0_RISING_SHIFT 0x01
3161#define TPS65917_INT4_EDGE_DETECT1_GPIO_0_FALLING 0x01
3162#define TPS65917_INT4_EDGE_DETECT1_GPIO_0_FALLING_SHIFT 0x00
3163
3164/* Bit definitions for INT4_EDGE_DETECT2 */
3165#define TPS65917_INT4_EDGE_DETECT2_GPIO_6_RISING 0x20
3166#define TPS65917_INT4_EDGE_DETECT2_GPIO_6_RISING_SHIFT 0x05
3167#define TPS65917_INT4_EDGE_DETECT2_GPIO_6_FALLING 0x10
3168#define TPS65917_INT4_EDGE_DETECT2_GPIO_6_FALLING_SHIFT 0x04
3169#define TPS65917_INT4_EDGE_DETECT2_GPIO_5_RISING 0x08
3170#define TPS65917_INT4_EDGE_DETECT2_GPIO_5_RISING_SHIFT 0x03
3171#define TPS65917_INT4_EDGE_DETECT2_GPIO_5_FALLING 0x04
3172#define TPS65917_INT4_EDGE_DETECT2_GPIO_5_FALLING_SHIFT 0x02
3173#define TPS65917_INT4_EDGE_DETECT2_GPIO_4_RISING 0x02
3174#define TPS65917_INT4_EDGE_DETECT2_GPIO_4_RISING_SHIFT 0x01
3175#define TPS65917_INT4_EDGE_DETECT2_GPIO_4_FALLING 0x01
3176#define TPS65917_INT4_EDGE_DETECT2_GPIO_4_FALLING_SHIFT 0x00
3177
3178/* Bit definitions for INT_CTRL */
3179#define TPS65917_INT_CTRL_INT_PENDING 0x04
3180#define TPS65917_INT_CTRL_INT_PENDING_SHIFT 0x02
3181#define TPS65917_INT_CTRL_INT_CLEAR 0x01
3182#define TPS65917_INT_CTRL_INT_CLEAR_SHIFT 0x00
3183
3184/* TPS65917 SMPS Registers */
3185
3186/* Registers for function SMPS */
3187#define TPS65917_SMPS1_CTRL 0x00
3188#define TPS65917_SMPS1_FORCE 0x02
3189#define TPS65917_SMPS1_VOLTAGE 0x03
3190#define TPS65917_SMPS2_CTRL 0x04
3191#define TPS65917_SMPS2_FORCE 0x06
3192#define TPS65917_SMPS2_VOLTAGE 0x07
3193#define TPS65917_SMPS3_CTRL 0x0C
3194#define TPS65917_SMPS3_FORCE 0x0E
3195#define TPS65917_SMPS3_VOLTAGE 0x0F
3196#define TPS65917_SMPS4_CTRL 0x10
3197#define TPS65917_SMPS4_VOLTAGE 0x13
3198#define TPS65917_SMPS5_CTRL 0x18
3199#define TPS65917_SMPS5_VOLTAGE 0x1B
3200#define TPS65917_SMPS_CTRL 0x24
3201#define TPS65917_SMPS_PD_CTRL 0x25
3202#define TPS65917_SMPS_THERMAL_EN 0x27
3203#define TPS65917_SMPS_THERMAL_STATUS 0x28
3204#define TPS65917_SMPS_SHORT_STATUS 0x29
3205#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN 0x2A
3206#define TPS65917_SMPS_POWERGOOD_MASK1 0x2B
3207#define TPS65917_SMPS_POWERGOOD_MASK2 0x2C
3208
3209/* Bit definitions for SMPS1_CTRL */
3210#define TPS65917_SMPS1_CTRL_WR_S 0x80
3211#define TPS65917_SMPS1_CTRL_WR_S_SHIFT 0x07
3212#define TPS65917_SMPS1_CTRL_ROOF_FLOOR_EN 0x40
3213#define TPS65917_SMPS1_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
3214#define TPS65917_SMPS1_CTRL_STATUS_MASK 0x30
3215#define TPS65917_SMPS1_CTRL_STATUS_SHIFT 0x04
3216#define TPS65917_SMPS1_CTRL_MODE_SLEEP_MASK 0x0C
3217#define TPS65917_SMPS1_CTRL_MODE_SLEEP_SHIFT 0x02
3218#define TPS65917_SMPS1_CTRL_MODE_ACTIVE_MASK 0x03
3219#define TPS65917_SMPS1_CTRL_MODE_ACTIVE_SHIFT 0x00
3220
3221/* Bit definitions for SMPS1_FORCE */
3222#define TPS65917_SMPS1_FORCE_CMD 0x80
3223#define TPS65917_SMPS1_FORCE_CMD_SHIFT 0x07
3224#define TPS65917_SMPS1_FORCE_VSEL_MASK 0x7F
3225#define TPS65917_SMPS1_FORCE_VSEL_SHIFT 0x00
3226
3227/* Bit definitions for SMPS1_VOLTAGE */
3228#define TPS65917_SMPS1_VOLTAGE_RANGE 0x80
3229#define TPS65917_SMPS1_VOLTAGE_RANGE_SHIFT 0x07
3230#define TPS65917_SMPS1_VOLTAGE_VSEL_MASK 0x7F
3231#define TPS65917_SMPS1_VOLTAGE_VSEL_SHIFT 0x00
3232
3233/* Bit definitions for SMPS2_CTRL */
3234#define TPS65917_SMPS2_CTRL_WR_S 0x80
3235#define TPS65917_SMPS2_CTRL_WR_S_SHIFT 0x07
3236#define TPS65917_SMPS2_CTRL_ROOF_FLOOR_EN 0x40
3237#define TPS65917_SMPS2_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
3238#define TPS65917_SMPS2_CTRL_STATUS_MASK 0x30
3239#define TPS65917_SMPS2_CTRL_STATUS_SHIFT 0x04
3240#define TPS65917_SMPS2_CTRL_MODE_SLEEP_MASK 0x0C
3241#define TPS65917_SMPS2_CTRL_MODE_SLEEP_SHIFT 0x02
3242#define TPS65917_SMPS2_CTRL_MODE_ACTIVE_MASK 0x03
3243#define TPS65917_SMPS2_CTRL_MODE_ACTIVE_SHIFT 0x00
3244
3245/* Bit definitions for SMPS2_FORCE */
3246#define TPS65917_SMPS2_FORCE_CMD 0x80
3247#define TPS65917_SMPS2_FORCE_CMD_SHIFT 0x07
3248#define TPS65917_SMPS2_FORCE_VSEL_MASK 0x7F
3249#define TPS65917_SMPS2_FORCE_VSEL_SHIFT 0x00
3250
3251/* Bit definitions for SMPS2_VOLTAGE */
3252#define TPS65917_SMPS2_VOLTAGE_RANGE 0x80
3253#define TPS65917_SMPS2_VOLTAGE_RANGE_SHIFT 0x07
3254#define TPS65917_SMPS2_VOLTAGE_VSEL_MASK 0x7F
3255#define TPS65917_SMPS2_VOLTAGE_VSEL_SHIFT 0x00
3256
3257/* Bit definitions for SMPS3_CTRL */
3258#define TPS65917_SMPS3_CTRL_WR_S 0x80
3259#define TPS65917_SMPS3_CTRL_WR_S_SHIFT 0x07
3260#define TPS65917_SMPS3_CTRL_ROOF_FLOOR_EN 0x40
3261#define TPS65917_SMPS3_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
3262#define TPS65917_SMPS3_CTRL_STATUS_MASK 0x30
3263#define TPS65917_SMPS3_CTRL_STATUS_SHIFT 0x04
3264#define TPS65917_SMPS3_CTRL_MODE_SLEEP_MASK 0x0C
3265#define TPS65917_SMPS3_CTRL_MODE_SLEEP_SHIFT 0x02
3266#define TPS65917_SMPS3_CTRL_MODE_ACTIVE_MASK 0x03
3267#define TPS65917_SMPS3_CTRL_MODE_ACTIVE_SHIFT 0x00
3268
3269/* Bit definitions for SMPS3_FORCE */
3270#define TPS65917_SMPS3_FORCE_CMD 0x80
3271#define TPS65917_SMPS3_FORCE_CMD_SHIFT 0x07
3272#define TPS65917_SMPS3_FORCE_VSEL_MASK 0x7F
3273#define TPS65917_SMPS3_FORCE_VSEL_SHIFT 0x00
3274
3275/* Bit definitions for SMPS3_VOLTAGE */
3276#define TPS65917_SMPS3_VOLTAGE_RANGE 0x80
3277#define TPS65917_SMPS3_VOLTAGE_RANGE_SHIFT 0x07
3278#define TPS65917_SMPS3_VOLTAGE_VSEL_MASK 0x7F
3279#define TPS65917_SMPS3_VOLTAGE_VSEL_SHIFT 0x00
3280
3281/* Bit definitions for SMPS4_CTRL */
3282#define TPS65917_SMPS4_CTRL_WR_S 0x80
3283#define TPS65917_SMPS4_CTRL_WR_S_SHIFT 0x07
3284#define TPS65917_SMPS4_CTRL_ROOF_FLOOR_EN 0x40
3285#define TPS65917_SMPS4_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
3286#define TPS65917_SMPS4_CTRL_STATUS_MASK 0x30
3287#define TPS65917_SMPS4_CTRL_STATUS_SHIFT 0x04
3288#define TPS65917_SMPS4_CTRL_MODE_SLEEP_MASK 0x0C
3289#define TPS65917_SMPS4_CTRL_MODE_SLEEP_SHIFT 0x02
3290#define TPS65917_SMPS4_CTRL_MODE_ACTIVE_MASK 0x03
3291#define TPS65917_SMPS4_CTRL_MODE_ACTIVE_SHIFT 0x00
3292
3293/* Bit definitions for SMPS4_VOLTAGE */
3294#define TPS65917_SMPS4_VOLTAGE_RANGE 0x80
3295#define TPS65917_SMPS4_VOLTAGE_RANGE_SHIFT 0x07
3296#define TPS65917_SMPS4_VOLTAGE_VSEL_MASK 0x7F
3297#define TPS65917_SMPS4_VOLTAGE_VSEL_SHIFT 0x00
3298
3299/* Bit definitions for SMPS5_CTRL */
3300#define TPS65917_SMPS5_CTRL_WR_S 0x80
3301#define TPS65917_SMPS5_CTRL_WR_S_SHIFT 0x07
3302#define TPS65917_SMPS5_CTRL_ROOF_FLOOR_EN 0x40
3303#define TPS65917_SMPS5_CTRL_ROOF_FLOOR_EN_SHIFT 0x06
3304#define TPS65917_SMPS5_CTRL_STATUS_MASK 0x30
3305#define TPS65917_SMPS5_CTRL_STATUS_SHIFT 0x04
3306#define TPS65917_SMPS5_CTRL_MODE_SLEEP_MASK 0x0C
3307#define TPS65917_SMPS5_CTRL_MODE_SLEEP_SHIFT 0x02
3308#define TPS65917_SMPS5_CTRL_MODE_ACTIVE_MASK 0x03
3309#define TPS65917_SMPS5_CTRL_MODE_ACTIVE_SHIFT 0x00
3310
3311/* Bit definitions for SMPS5_VOLTAGE */
3312#define TPS65917_SMPS5_VOLTAGE_RANGE 0x80
3313#define TPS65917_SMPS5_VOLTAGE_RANGE_SHIFT 0x07
3314#define TPS65917_SMPS5_VOLTAGE_VSEL_MASK 0x7F
3315#define TPS65917_SMPS5_VOLTAGE_VSEL_SHIFT 0x00
3316
3317/* Bit definitions for SMPS_CTRL */
3318#define TPS65917_SMPS_CTRL_SMPS1_SMPS12_EN 0x10
3319#define TPS65917_SMPS_CTRL_SMPS1_SMPS12_EN_SHIFT 0x04
3320#define TPS65917_SMPS_CTRL_SMPS12_PHASE_CTRL 0x03
3321#define TPS65917_SMPS_CTRL_SMPS12_PHASE_CTRL_SHIFT 0x00
3322
3323/* Bit definitions for SMPS_PD_CTRL */
3324#define TPS65917_SMPS_PD_CTRL_SMPS5 0x40
3325#define TPS65917_SMPS_PD_CTRL_SMPS5_SHIFT 0x06
3326#define TPS65917_SMPS_PD_CTRL_SMPS4 0x10
3327#define TPS65917_SMPS_PD_CTRL_SMPS4_SHIFT 0x04
3328#define TPS65917_SMPS_PD_CTRL_SMPS3 0x08
3329#define TPS65917_SMPS_PD_CTRL_SMPS3_SHIFT 0x03
3330#define TPS65917_SMPS_PD_CTRL_SMPS2 0x02
3331#define TPS65917_SMPS_PD_CTRL_SMPS2_SHIFT 0x01
3332#define TPS65917_SMPS_PD_CTRL_SMPS1 0x01
3333#define TPS65917_SMPS_PD_CTRL_SMPS1_SHIFT 0x00
3334
3335/* Bit definitions for SMPS_THERMAL_EN */
3336#define TPS65917_SMPS_THERMAL_EN_SMPS5 0x40
3337#define TPS65917_SMPS_THERMAL_EN_SMPS5_SHIFT 0x06
3338#define TPS65917_SMPS_THERMAL_EN_SMPS3 0x08
3339#define TPS65917_SMPS_THERMAL_EN_SMPS3_SHIFT 0x03
3340#define TPS65917_SMPS_THERMAL_EN_SMPS12 0x01
3341#define TPS65917_SMPS_THERMAL_EN_SMPS12_SHIFT 0x00
3342
3343/* Bit definitions for SMPS_THERMAL_STATUS */
3344#define TPS65917_SMPS_THERMAL_STATUS_SMPS5 0x40
3345#define TPS65917_SMPS_THERMAL_STATUS_SMPS5_SHIFT 0x06
3346#define TPS65917_SMPS_THERMAL_STATUS_SMPS3 0x08
3347#define TPS65917_SMPS_THERMAL_STATUS_SMPS3_SHIFT 0x03
3348#define TPS65917_SMPS_THERMAL_STATUS_SMPS12 0x01
3349#define TPS65917_SMPS_THERMAL_STATUS_SMPS12_SHIFT 0x00
3350
3351/* Bit definitions for SMPS_SHORT_STATUS */
3352#define TPS65917_SMPS_SHORT_STATUS_SMPS5 0x40
3353#define TPS65917_SMPS_SHORT_STATUS_SMPS5_SHIFT 0x06
3354#define TPS65917_SMPS_SHORT_STATUS_SMPS4 0x10
3355#define TPS65917_SMPS_SHORT_STATUS_SMPS4_SHIFT 0x04
3356#define TPS65917_SMPS_SHORT_STATUS_SMPS3 0x08
3357#define TPS65917_SMPS_SHORT_STATUS_SMPS3_SHIFT 0x03
3358#define TPS65917_SMPS_SHORT_STATUS_SMPS2 0x02
3359#define TPS65917_SMPS_SHORT_STATUS_SMPS2_SHIFT 0x01
3360#define TPS65917_SMPS_SHORT_STATUS_SMPS1 0x01
3361#define TPS65917_SMPS_SHORT_STATUS_SMPS1_SHIFT 0x00
3362
3363/* Bit definitions for SMPS_NEGATIVE_CURRENT_LIMIT_EN */
3364#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS5 0x40
3365#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS5_SHIFT 0x06
3366#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS4 0x10
3367#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS4_SHIFT 0x04
3368#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3 0x08
3369#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS3_SHIFT 0x03
3370#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS2 0x02
3371#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS2_SHIFT 0x01
3372#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS1 0x01
3373#define TPS65917_SMPS_NEGATIVE_CURRENT_LIMIT_EN_SMPS1_SHIFT 0x00
3374
3375/* Bit definitions for SMPS_POWERGOOD_MASK1 */
3376#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS5 0x40
3377#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS5_SHIFT 0x06
3378#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS4 0x10
3379#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS4_SHIFT 0x04
3380#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS3 0x08
3381#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS3_SHIFT 0x03
3382#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS2 0x02
3383#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS2_SHIFT 0x01
3384#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS1 0x01
3385#define TPS65917_SMPS_POWERGOOD_MASK1_SMPS1_SHIFT 0x00
3386
3387/* Bit definitions for SMPS_POWERGOOD_MASK2 */
3388#define TPS65917_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT 0x80
3389#define TPS65917_SMPS_POWERGOOD_MASK2_POWERGOOD_TYPE_SELECT_SHIFT 0x07
3390#define TPS65917_SMPS_POWERGOOD_MASK2_OVC_ALARM_SHIFT 0x10
3391#define TPS65917_SMPS_POWERGOOD_MASK2_OVC_ALARM 0x04
3392
3393/* Bit definitions for SMPS_PLL_CTRL */
3394
3395#define TPS65917_SMPS_PLL_CTRL_PLL_EN_PLL_BYPASS_SHIFT 0x08
3396#define TPS65917_SMPS_PLL_CTRL_PLL_PLL_EN_BYPASS 0x03
3397#define TPS65917_SMPS_PLL_CTRL_PLL_PLL_BYPASS_CLK_SHIFT 0x04
3398#define TPS65917_SMPS_PLL_CTRL_PLL_PLL_BYPASS_CLK 0x02
3399
3400/* Registers for function LDO */
3401#define TPS65917_LDO1_CTRL 0x00
3402#define TPS65917_LDO1_VOLTAGE 0x01
3403#define TPS65917_LDO2_CTRL 0x02
3404#define TPS65917_LDO2_VOLTAGE 0x03
3405#define TPS65917_LDO3_CTRL 0x04
3406#define TPS65917_LDO3_VOLTAGE 0x05
3407#define TPS65917_LDO4_CTRL 0x0E
3408#define TPS65917_LDO4_VOLTAGE 0x0F
3409#define TPS65917_LDO5_CTRL 0x12
3410#define TPS65917_LDO5_VOLTAGE 0x13
3411#define TPS65917_LDO_PD_CTRL1 0x1B
3412#define TPS65917_LDO_PD_CTRL2 0x1C
3413#define TPS65917_LDO_SHORT_STATUS1 0x1D
3414#define TPS65917_LDO_SHORT_STATUS2 0x1E
3415#define TPS65917_LDO_PD_CTRL3 0x2D
3416#define TPS65917_LDO_SHORT_STATUS3 0x2E
3417
3418/* Bit definitions for LDO1_CTRL */
3419#define TPS65917_LDO1_CTRL_WR_S 0x80
3420#define TPS65917_LDO1_CTRL_WR_S_SHIFT 0x07
3421#define TPS65917_LDO1_CTRL_BYPASS_EN 0x40
3422#define TPS65917_LDO1_CTRL_BYPASS_EN_SHIFT 0x06
3423#define TPS65917_LDO1_CTRL_STATUS 0x10
3424#define TPS65917_LDO1_CTRL_STATUS_SHIFT 0x04
3425#define TPS65917_LDO1_CTRL_MODE_SLEEP 0x04
3426#define TPS65917_LDO1_CTRL_MODE_SLEEP_SHIFT 0x02
3427#define TPS65917_LDO1_CTRL_MODE_ACTIVE 0x01
3428#define TPS65917_LDO1_CTRL_MODE_ACTIVE_SHIFT 0x00
3429
3430/* Bit definitions for LDO1_VOLTAGE */
3431#define TPS65917_LDO1_VOLTAGE_VSEL_MASK 0x2F
3432#define TPS65917_LDO1_VOLTAGE_VSEL_SHIFT 0x00
3433
3434/* Bit definitions for LDO2_CTRL */
3435#define TPS65917_LDO2_CTRL_WR_S 0x80
3436#define TPS65917_LDO2_CTRL_WR_S_SHIFT 0x07
3437#define TPS65917_LDO2_CTRL_BYPASS_EN 0x40
3438#define TPS65917_LDO2_CTRL_BYPASS_EN_SHIFT 0x06
3439#define TPS65917_LDO2_CTRL_STATUS 0x10
3440#define TPS65917_LDO2_CTRL_STATUS_SHIFT 0x04
3441#define TPS65917_LDO2_CTRL_MODE_SLEEP 0x04
3442#define TPS65917_LDO2_CTRL_MODE_SLEEP_SHIFT 0x02
3443#define TPS65917_LDO2_CTRL_MODE_ACTIVE 0x01
3444#define TPS65917_LDO2_CTRL_MODE_ACTIVE_SHIFT 0x00
3445
3446/* Bit definitions for LDO2_VOLTAGE */
3447#define TPS65917_LDO2_VOLTAGE_VSEL_MASK 0x2F
3448#define TPS65917_LDO2_VOLTAGE_VSEL_SHIFT 0x00
3449
3450/* Bit definitions for LDO3_CTRL */
3451#define TPS65917_LDO3_CTRL_WR_S 0x80
3452#define TPS65917_LDO3_CTRL_WR_S_SHIFT 0x07
3453#define TPS65917_LDO3_CTRL_STATUS 0x10
3454#define TPS65917_LDO3_CTRL_STATUS_SHIFT 0x04
3455#define TPS65917_LDO3_CTRL_MODE_SLEEP 0x04
3456#define TPS65917_LDO3_CTRL_MODE_SLEEP_SHIFT 0x02
3457#define TPS65917_LDO3_CTRL_MODE_ACTIVE 0x01
3458#define TPS65917_LDO3_CTRL_MODE_ACTIVE_SHIFT 0x00
3459
3460/* Bit definitions for LDO3_VOLTAGE */
3461#define TPS65917_LDO3_VOLTAGE_VSEL_MASK 0x2F
3462#define TPS65917_LDO3_VOLTAGE_VSEL_SHIFT 0x00
3463
3464/* Bit definitions for LDO4_CTRL */
3465#define TPS65917_LDO4_CTRL_WR_S 0x80
3466#define TPS65917_LDO4_CTRL_WR_S_SHIFT 0x07
3467#define TPS65917_LDO4_CTRL_STATUS 0x10
3468#define TPS65917_LDO4_CTRL_STATUS_SHIFT 0x04
3469#define TPS65917_LDO4_CTRL_MODE_SLEEP 0x04
3470#define TPS65917_LDO4_CTRL_MODE_SLEEP_SHIFT 0x02
3471#define TPS65917_LDO4_CTRL_MODE_ACTIVE 0x01
3472#define TPS65917_LDO4_CTRL_MODE_ACTIVE_SHIFT 0x00
3473
3474/* Bit definitions for LDO4_VOLTAGE */
3475#define TPS65917_LDO4_VOLTAGE_VSEL_MASK 0x2F
3476#define TPS65917_LDO4_VOLTAGE_VSEL_SHIFT 0x00
3477
3478/* Bit definitions for LDO5_CTRL */
3479#define TPS65917_LDO5_CTRL_WR_S 0x80
3480#define TPS65917_LDO5_CTRL_WR_S_SHIFT 0x07
3481#define TPS65917_LDO5_CTRL_STATUS 0x10
3482#define TPS65917_LDO5_CTRL_STATUS_SHIFT 0x04
3483#define TPS65917_LDO5_CTRL_MODE_SLEEP 0x04
3484#define TPS65917_LDO5_CTRL_MODE_SLEEP_SHIFT 0x02
3485#define TPS65917_LDO5_CTRL_MODE_ACTIVE 0x01
3486#define TPS65917_LDO5_CTRL_MODE_ACTIVE_SHIFT 0x00
3487
3488/* Bit definitions for LDO5_VOLTAGE */
3489#define TPS65917_LDO5_VOLTAGE_VSEL_MASK 0x2F
3490#define TPS65917_LDO5_VOLTAGE_VSEL_SHIFT 0x00
3491
3492/* Bit definitions for LDO_PD_CTRL1 */
3493#define TPS65917_LDO_PD_CTRL1_LDO4 0x80
3494#define TPS65917_LDO_PD_CTRL1_LDO4_SHIFT 0x07
3495#define TPS65917_LDO_PD_CTRL1_LDO2 0x02
3496#define TPS65917_LDO_PD_CTRL1_LDO2_SHIFT 0x01
3497#define TPS65917_LDO_PD_CTRL1_LDO1 0x01
3498#define TPS65917_LDO_PD_CTRL1_LDO1_SHIFT 0x00
3499
3500/* Bit definitions for LDO_PD_CTRL2 */
3501#define TPS65917_LDO_PD_CTRL2_LDO3 0x04
3502#define TPS65917_LDO_PD_CTRL2_LDO3_SHIFT 0x02
3503#define TPS65917_LDO_PD_CTRL2_LDO5 0x02
3504#define TPS65917_LDO_PD_CTRL2_LDO5_SHIFT 0x01
3505
3506/* Bit definitions for LDO_PD_CTRL3 */
3507#define TPS65917_LDO_PD_CTRL2_LDOVANA 0x80
3508#define TPS65917_LDO_PD_CTRL2_LDOVANA_SHIFT 0x07
3509
3510/* Bit definitions for LDO_SHORT_STATUS1 */
3511#define TPS65917_LDO_SHORT_STATUS1_LDO4 0x80
3512#define TPS65917_LDO_SHORT_STATUS1_LDO4_SHIFT 0x07
3513#define TPS65917_LDO_SHORT_STATUS1_LDO2 0x02
3514#define TPS65917_LDO_SHORT_STATUS1_LDO2_SHIFT 0x01
3515#define TPS65917_LDO_SHORT_STATUS1_LDO1 0x01
3516#define TPS65917_LDO_SHORT_STATUS1_LDO1_SHIFT 0x00
3517
3518/* Bit definitions for LDO_SHORT_STATUS2 */
3519#define TPS65917_LDO_SHORT_STATUS2_LDO3 0x04
3520#define TPS65917_LDO_SHORT_STATUS2_LDO3_SHIFT 0x02
3521#define TPS65917_LDO_SHORT_STATUS2_LDO5 0x02
3522#define TPS65917_LDO_SHORT_STATUS2_LDO5_SHIFT 0x01
3523
3524/* Bit definitions for LDO_SHORT_STATUS2 */
3525#define TPS65917_LDO_SHORT_STATUS2_LDOVANA 0x80
3526#define TPS65917_LDO_SHORT_STATUS2_LDOVANA_SHIFT 0x07
3527
3528/* Bit definitions for REGEN1_CTRL */
3529#define TPS65917_REGEN1_CTRL_STATUS 0x10
3530#define TPS65917_REGEN1_CTRL_STATUS_SHIFT 0x04
3531#define TPS65917_REGEN1_CTRL_MODE_SLEEP 0x04
3532#define TPS65917_REGEN1_CTRL_MODE_SLEEP_SHIFT 0x02
3533#define TPS65917_REGEN1_CTRL_MODE_ACTIVE 0x01
3534#define TPS65917_REGEN1_CTRL_MODE_ACTIVE_SHIFT 0x00
3535
3536/* Bit definitions for PLLEN_CTRL */
3537#define TPS65917_PLLEN_CTRL_STATUS 0x10
3538#define TPS65917_PLLEN_CTRL_STATUS_SHIFT 0x04
3539#define TPS65917_PLLEN_CTRL_MODE_SLEEP 0x04
3540#define TPS65917_PLLEN_CTRL_MODE_SLEEP_SHIFT 0x02
3541#define TPS65917_PLLEN_CTRL_MODE_ACTIVE 0x01
3542#define TPS65917_PLLEN_CTRL_MODE_ACTIVE_SHIFT 0x00
3543
3544/* Bit definitions for REGEN2_CTRL */
3545#define TPS65917_REGEN2_CTRL_STATUS 0x10
3546#define TPS65917_REGEN2_CTRL_STATUS_SHIFT 0x04
3547#define TPS65917_REGEN2_CTRL_MODE_SLEEP 0x04
3548#define TPS65917_REGEN2_CTRL_MODE_SLEEP_SHIFT 0x02
3549#define TPS65917_REGEN2_CTRL_MODE_ACTIVE 0x01
3550#define TPS65917_REGEN2_CTRL_MODE_ACTIVE_SHIFT 0x00
3551
3552/* Bit definitions for NSLEEP_RES_ASSIGN */
3553#define TPS65917_NSLEEP_RES_ASSIGN_PLL_EN 0x08
3554#define TPS65917_NSLEEP_RES_ASSIGN_PLL_EN_SHIFT 0x03
3555#define TPS65917_NSLEEP_RES_ASSIGN_REGEN3 0x04
3556#define TPS65917_NSLEEP_RES_ASSIGN_REGEN3_SHIFT 0x02
3557#define TPS65917_NSLEEP_RES_ASSIGN_REGEN2 0x02
3558#define TPS65917_NSLEEP_RES_ASSIGN_REGEN2_SHIFT 0x01
3559#define TPS65917_NSLEEP_RES_ASSIGN_REGEN1 0x01
3560#define TPS65917_NSLEEP_RES_ASSIGN_REGEN1_SHIFT 0x00
3561
3562/* Bit definitions for NSLEEP_SMPS_ASSIGN */
3563#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS5 0x40
3564#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS5_SHIFT 0x06
3565#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS4 0x10
3566#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS4_SHIFT 0x04
3567#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS3 0x08
3568#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS3_SHIFT 0x03
3569#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS2 0x02
3570#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS2_SHIFT 0x01
3571#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS1 0x01
3572#define TPS65917_NSLEEP_SMPS_ASSIGN_SMPS1_SHIFT 0x00
3573
3574/* Bit definitions for NSLEEP_LDO_ASSIGN1 */
3575#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO4 0x80
3576#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO4_SHIFT 0x07
3577#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO2 0x02
3578#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO2_SHIFT 0x01
3579#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO1 0x01
3580#define TPS65917_NSLEEP_LDO_ASSIGN1_LDO1_SHIFT 0x00
3581
3582/* Bit definitions for NSLEEP_LDO_ASSIGN2 */
3583#define TPS65917_NSLEEP_LDO_ASSIGN2_LDO3 0x04
3584#define TPS65917_NSLEEP_LDO_ASSIGN2_LDO3_SHIFT 0x02
3585#define TPS65917_NSLEEP_LDO_ASSIGN2_LDO5 0x02
3586#define TPS65917_NSLEEP_LDO_ASSIGN2_LDO5_SHIFT 0x01
3587
3588/* Bit definitions for ENABLE1_RES_ASSIGN */
3589#define TPS65917_ENABLE1_RES_ASSIGN_PLLEN 0x08
3590#define TPS65917_ENABLE1_RES_ASSIGN_PLLEN_SHIFT 0x03
3591#define TPS65917_ENABLE1_RES_ASSIGN_REGEN3 0x04
3592#define TPS65917_ENABLE1_RES_ASSIGN_REGEN3_SHIFT 0x02
3593#define TPS65917_ENABLE1_RES_ASSIGN_REGEN2 0x02
3594#define TPS65917_ENABLE1_RES_ASSIGN_REGEN2_SHIFT 0x01
3595#define TPS65917_ENABLE1_RES_ASSIGN_REGEN1 0x01
3596#define TPS65917_ENABLE1_RES_ASSIGN_REGEN1_SHIFT 0x00
3597
3598/* Bit definitions for ENABLE1_SMPS_ASSIGN */
3599#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS5 0x40
3600#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS5_SHIFT 0x06
3601#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS4 0x10
3602#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS4_SHIFT 0x04
3603#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS3 0x08
3604#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS3_SHIFT 0x03
3605#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS2 0x02
3606#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS2_SHIFT 0x01
3607#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS1 0x01
3608#define TPS65917_ENABLE1_SMPS_ASSIGN_SMPS1_SHIFT 0x00
3609
3610/* Bit definitions for ENABLE1_LDO_ASSIGN1 */
3611#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO4 0x80
3612#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO4_SHIFT 0x07
3613#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO2 0x02
3614#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO2_SHIFT 0x01
3615#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO1 0x01
3616#define TPS65917_ENABLE1_LDO_ASSIGN1_LDO1_SHIFT 0x00
3617
3618/* Bit definitions for ENABLE1_LDO_ASSIGN2 */
3619#define TPS65917_ENABLE1_LDO_ASSIGN2_LDO3 0x04
3620#define TPS65917_ENABLE1_LDO_ASSIGN2_LDO3_SHIFT 0x02
3621#define TPS65917_ENABLE1_LDO_ASSIGN2_LDO5 0x02
3622#define TPS65917_ENABLE1_LDO_ASSIGN2_LDO5_SHIFT 0x01
3623
3624/* Bit definitions for ENABLE2_RES_ASSIGN */
3625#define TPS65917_ENABLE2_RES_ASSIGN_PLLEN 0x08
3626#define TPS65917_ENABLE2_RES_ASSIGN_PLLEN_SHIFT 0x03
3627#define TPS65917_ENABLE2_RES_ASSIGN_REGEN3 0x04
3628#define TPS65917_ENABLE2_RES_ASSIGN_REGEN3_SHIFT 0x02
3629#define TPS65917_ENABLE2_RES_ASSIGN_REGEN2 0x02
3630#define TPS65917_ENABLE2_RES_ASSIGN_REGEN2_SHIFT 0x01
3631#define TPS65917_ENABLE2_RES_ASSIGN_REGEN1 0x01
3632#define TPS65917_ENABLE2_RES_ASSIGN_REGEN1_SHIFT 0x00
3633
3634/* Bit definitions for ENABLE2_SMPS_ASSIGN */
3635#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS5 0x40
3636#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS5_SHIFT 0x06
3637#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS4 0x10
3638#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS4_SHIFT 0x04
3639#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS3 0x08
3640#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS3_SHIFT 0x03
3641#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS2 0x02
3642#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS2_SHIFT 0x01
3643#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS1 0x01
3644#define TPS65917_ENABLE2_SMPS_ASSIGN_SMPS1_SHIFT 0x00
3645
3646/* Bit definitions for ENABLE2_LDO_ASSIGN1 */
3647#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO4 0x80
3648#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO4_SHIFT 0x07
3649#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO2 0x02
3650#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO2_SHIFT 0x01
3651#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO1 0x01
3652#define TPS65917_ENABLE2_LDO_ASSIGN1_LDO1_SHIFT 0x00
3653
3654/* Bit definitions for ENABLE2_LDO_ASSIGN2 */
3655#define TPS65917_ENABLE2_LDO_ASSIGN2_LDO3 0x04
3656#define TPS65917_ENABLE2_LDO_ASSIGN2_LDO3_SHIFT 0x02
3657#define TPS65917_ENABLE2_LDO_ASSIGN2_LDO5 0x02
3658#define TPS65917_ENABLE2_LDO_ASSIGN2_LDO5_SHIFT 0x01
3659
3660/* Bit definitions for REGEN3_CTRL */
3661#define TPS65917_REGEN3_CTRL_STATUS 0x10
3662#define TPS65917_REGEN3_CTRL_STATUS_SHIFT 0x04
3663#define TPS65917_REGEN3_CTRL_MODE_SLEEP 0x04
3664#define TPS65917_REGEN3_CTRL_MODE_SLEEP_SHIFT 0x02
3665#define TPS65917_REGEN3_CTRL_MODE_ACTIVE 0x01
3666#define TPS65917_REGEN3_CTRL_MODE_ACTIVE_SHIFT 0x00
3667
3668/* Registers for function RESOURCE */
3669#define TPS65917_REGEN1_CTRL 0x2
3670#define TPS65917_PLLEN_CTRL 0x3
3671#define TPS65917_NSLEEP_RES_ASSIGN 0x6
3672#define TPS65917_NSLEEP_SMPS_ASSIGN 0x7
3673#define TPS65917_NSLEEP_LDO_ASSIGN1 0x8
3674#define TPS65917_NSLEEP_LDO_ASSIGN2 0x9
3675#define TPS65917_ENABLE1_RES_ASSIGN 0xA
3676#define TPS65917_ENABLE1_SMPS_ASSIGN 0xB
3677#define TPS65917_ENABLE1_LDO_ASSIGN1 0xC
3678#define TPS65917_ENABLE1_LDO_ASSIGN2 0xD
3679#define TPS65917_ENABLE2_RES_ASSIGN 0xE
3680#define TPS65917_ENABLE2_SMPS_ASSIGN 0xF
3681#define TPS65917_ENABLE2_LDO_ASSIGN1 0x10
3682#define TPS65917_ENABLE2_LDO_ASSIGN2 0x11
3683#define TPS65917_REGEN2_CTRL 0x12
3684#define TPS65917_REGEN3_CTRL 0x13
3685
60c185f0
LD		 3686static inline int palmas_read(struct palmas *palmas, unsigned int base,
3687 unsigned int reg, unsigned int *val)
3688{
45ac60c0 3689 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
60c185f0
LD		 3690 int slave_id = PALMAS_BASE_TO_SLAVE(base);
3691
3692 return regmap_read(palmas->regmap[slave_id], addr, val);
3693}
3694
3695static inline int palmas_write(struct palmas *palmas, unsigned int base,
3696 unsigned int reg, unsigned int value)
3697{
3698 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
3699 int slave_id = PALMAS_BASE_TO_SLAVE(base);
3700
3701 return regmap_write(palmas->regmap[slave_id], addr, value);
3702}
3703
3704static inline int palmas_bulk_write(struct palmas *palmas, unsigned int base,
3705 unsigned int reg, const void *val, size_t val_count)
3706{
3707 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
3708 int slave_id = PALMAS_BASE_TO_SLAVE(base);
3709
3710 return regmap_bulk_write(palmas->regmap[slave_id], addr,
3711 val, val_count);
3712}
3713
3714static inline int palmas_bulk_read(struct palmas *palmas, unsigned int base,
3715 unsigned int reg, void *val, size_t val_count)
3716{
3717 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
3718 int slave_id = PALMAS_BASE_TO_SLAVE(base);
3719
3720 return regmap_bulk_read(palmas->regmap[slave_id], addr,
3721 val, val_count);
3722}
3723
3724static inline int palmas_update_bits(struct palmas *palmas, unsigned int base,
3725 unsigned int reg, unsigned int mask, unsigned int val)
3726{
3727 unsigned int addr = PALMAS_BASE_TO_REG(base, reg);
3728 int slave_id = PALMAS_BASE_TO_SLAVE(base);
3729
3730 return regmap_update_bits(palmas->regmap[slave_id], addr, mask, val);
3731}
3732
3733static inline int palmas_irq_get_virq(struct palmas *palmas, int irq)
3734{
3735 return regmap_irq_get_virq(palmas->irq_data, irq);
3736}
3737
cc01b463
LD		 3738
3739int palmas_ext_control_req_config(struct palmas *palmas,
3740 enum palmas_external_requestor_id ext_control_req_id,
3741 int ext_ctrl, bool enable);
3742
2945fbc2 3743#endif /* __LINUX_MFD_PALMAS_H */
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