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Commit | Line | Data |
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1c743ad5 MV |
1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
2 | /* Copyright (C) 2019 ROHM Semiconductors */ | |
3 | ||
4 | #ifndef __LINUX_MFD_BD71828_H__ | |
5 | #define __LINUX_MFD_BD71828_H__ | |
6 | ||
7 | #include <linux/mfd/rohm-generic.h> | |
fe5a591b | 8 | #include <linux/mfd/rohm-shared.h> |
1c743ad5 MV |
9 | |
10 | /* Regulator IDs */ | |
11 | enum { | |
12 | BD71828_BUCK1, | |
13 | BD71828_BUCK2, | |
14 | BD71828_BUCK3, | |
15 | BD71828_BUCK4, | |
16 | BD71828_BUCK5, | |
17 | BD71828_BUCK6, | |
18 | BD71828_BUCK7, | |
19 | BD71828_LDO1, | |
20 | BD71828_LDO2, | |
21 | BD71828_LDO3, | |
22 | BD71828_LDO4, | |
23 | BD71828_LDO5, | |
24 | BD71828_LDO6, | |
25 | BD71828_LDO_SNVS, | |
26 | BD71828_REGULATOR_AMOUNT, | |
27 | }; | |
28 | ||
6160f562 AL |
29 | #define BD71828_BUCK1267_VOLTS 0x100 |
30 | #define BD71828_BUCK3_VOLTS 0x20 | |
31 | #define BD71828_BUCK4_VOLTS 0x40 | |
32 | #define BD71828_BUCK5_VOLTS 0x20 | |
33 | #define BD71828_LDO_VOLTS 0x40 | |
1c743ad5 MV |
34 | /* LDO6 is fixed 1.8V voltage */ |
35 | #define BD71828_LDO_6_VOLTAGE 1800000 | |
36 | ||
37 | /* Registers and masks*/ | |
38 | ||
39 | /* MODE control */ | |
40 | #define BD71828_REG_PS_CTRL_1 0x04 | |
41 | #define BD71828_REG_PS_CTRL_2 0x05 | |
42 | #define BD71828_REG_PS_CTRL_3 0x06 | |
43 | ||
44 | //#define BD71828_REG_SWRESET 0x06 | |
45 | #define BD71828_MASK_RUN_LVL_CTRL 0x30 | |
46 | ||
47 | /* Regulator control masks */ | |
48 | ||
49 | #define BD71828_MASK_RAMP_DELAY 0x6 | |
50 | ||
51 | #define BD71828_MASK_RUN_EN 0x08 | |
52 | #define BD71828_MASK_SUSP_EN 0x04 | |
53 | #define BD71828_MASK_IDLE_EN 0x02 | |
54 | #define BD71828_MASK_LPSR_EN 0x01 | |
55 | ||
56 | #define BD71828_MASK_RUN0_EN 0x01 | |
57 | #define BD71828_MASK_RUN1_EN 0x02 | |
58 | #define BD71828_MASK_RUN2_EN 0x04 | |
59 | #define BD71828_MASK_RUN3_EN 0x08 | |
60 | ||
61 | #define BD71828_MASK_DVS_BUCK1_CTRL 0x10 | |
62 | #define BD71828_DVS_BUCK1_CTRL_I2C 0 | |
63 | #define BD71828_DVS_BUCK1_USE_RUNLVL 0x10 | |
64 | ||
65 | #define BD71828_MASK_DVS_BUCK2_CTRL 0x20 | |
66 | #define BD71828_DVS_BUCK2_CTRL_I2C 0 | |
67 | #define BD71828_DVS_BUCK2_USE_RUNLVL 0x20 | |
68 | ||
69 | #define BD71828_MASK_DVS_BUCK6_CTRL 0x40 | |
70 | #define BD71828_DVS_BUCK6_CTRL_I2C 0 | |
71 | #define BD71828_DVS_BUCK6_USE_RUNLVL 0x40 | |
72 | ||
73 | #define BD71828_MASK_DVS_BUCK7_CTRL 0x80 | |
74 | #define BD71828_DVS_BUCK7_CTRL_I2C 0 | |
75 | #define BD71828_DVS_BUCK7_USE_RUNLVL 0x80 | |
76 | ||
77 | #define BD71828_MASK_BUCK1267_VOLT 0xff | |
78 | #define BD71828_MASK_BUCK3_VOLT 0x1f | |
79 | #define BD71828_MASK_BUCK4_VOLT 0x3f | |
80 | #define BD71828_MASK_BUCK5_VOLT 0x1f | |
81 | #define BD71828_MASK_LDO_VOLT 0x3f | |
82 | ||
83 | /* Regulator control regs */ | |
84 | #define BD71828_REG_BUCK1_EN 0x08 | |
85 | #define BD71828_REG_BUCK1_CTRL 0x09 | |
86 | #define BD71828_REG_BUCK1_MODE 0x0a | |
87 | #define BD71828_REG_BUCK1_IDLE_VOLT 0x0b | |
88 | #define BD71828_REG_BUCK1_SUSP_VOLT 0x0c | |
89 | #define BD71828_REG_BUCK1_VOLT 0x0d | |
90 | ||
91 | #define BD71828_REG_BUCK2_EN 0x12 | |
92 | #define BD71828_REG_BUCK2_CTRL 0x13 | |
93 | #define BD71828_REG_BUCK2_MODE 0x14 | |
94 | #define BD71828_REG_BUCK2_IDLE_VOLT 0x15 | |
95 | #define BD71828_REG_BUCK2_SUSP_VOLT 0x16 | |
96 | #define BD71828_REG_BUCK2_VOLT 0x17 | |
97 | ||
98 | #define BD71828_REG_BUCK3_EN 0x1c | |
99 | #define BD71828_REG_BUCK3_MODE 0x1d | |
100 | #define BD71828_REG_BUCK3_VOLT 0x1e | |
101 | ||
102 | #define BD71828_REG_BUCK4_EN 0x1f | |
103 | #define BD71828_REG_BUCK4_MODE 0x20 | |
104 | #define BD71828_REG_BUCK4_VOLT 0x21 | |
105 | ||
106 | #define BD71828_REG_BUCK5_EN 0x22 | |
107 | #define BD71828_REG_BUCK5_MODE 0x23 | |
108 | #define BD71828_REG_BUCK5_VOLT 0x24 | |
109 | ||
110 | #define BD71828_REG_BUCK6_EN 0x25 | |
111 | #define BD71828_REG_BUCK6_CTRL 0x26 | |
112 | #define BD71828_REG_BUCK6_MODE 0x27 | |
113 | #define BD71828_REG_BUCK6_IDLE_VOLT 0x28 | |
114 | #define BD71828_REG_BUCK6_SUSP_VOLT 0x29 | |
115 | #define BD71828_REG_BUCK6_VOLT 0x2a | |
116 | ||
117 | #define BD71828_REG_BUCK7_EN 0x2f | |
118 | #define BD71828_REG_BUCK7_CTRL 0x30 | |
119 | #define BD71828_REG_BUCK7_MODE 0x31 | |
120 | #define BD71828_REG_BUCK7_IDLE_VOLT 0x32 | |
121 | #define BD71828_REG_BUCK7_SUSP_VOLT 0x33 | |
122 | #define BD71828_REG_BUCK7_VOLT 0x34 | |
123 | ||
124 | #define BD71828_REG_LDO1_EN 0x39 | |
125 | #define BD71828_REG_LDO1_VOLT 0x3a | |
126 | #define BD71828_REG_LDO2_EN 0x3b | |
127 | #define BD71828_REG_LDO2_VOLT 0x3c | |
128 | #define BD71828_REG_LDO3_EN 0x3d | |
129 | #define BD71828_REG_LDO3_VOLT 0x3e | |
130 | #define BD71828_REG_LDO4_EN 0x3f | |
131 | #define BD71828_REG_LDO4_VOLT 0x40 | |
132 | #define BD71828_REG_LDO5_EN 0x41 | |
133 | #define BD71828_REG_LDO5_VOLT 0x43 | |
134 | #define BD71828_REG_LDO5_VOLT_OPT 0x42 | |
135 | #define BD71828_REG_LDO6_EN 0x44 | |
136 | //#define BD71828_REG_LDO6_VOLT 0x4 | |
137 | #define BD71828_REG_LDO7_EN 0x45 | |
138 | #define BD71828_REG_LDO7_VOLT 0x46 | |
139 | ||
140 | /* GPIO */ | |
141 | ||
142 | #define BD71828_GPIO_DRIVE_MASK 0x2 | |
143 | #define BD71828_GPIO_OPEN_DRAIN 0x0 | |
144 | #define BD71828_GPIO_PUSH_PULL 0x2 | |
145 | #define BD71828_GPIO_OUT_HI 0x1 | |
146 | #define BD71828_GPIO_OUT_LO 0x0 | |
147 | #define BD71828_GPIO_OUT_MASK 0x1 | |
148 | ||
149 | #define BD71828_REG_GPIO_CTRL1 0x47 | |
150 | #define BD71828_REG_GPIO_CTRL2 0x48 | |
151 | #define BD71828_REG_GPIO_CTRL3 0x49 | |
152 | #define BD71828_REG_IO_STAT 0xed | |
153 | ||
154 | /* RTC */ | |
155 | #define BD71828_REG_RTC_SEC 0x4c | |
156 | #define BD71828_REG_RTC_MINUTE 0x4d | |
157 | #define BD71828_REG_RTC_HOUR 0x4e | |
158 | #define BD71828_REG_RTC_WEEK 0x4f | |
159 | #define BD71828_REG_RTC_DAY 0x50 | |
160 | #define BD71828_REG_RTC_MONTH 0x51 | |
161 | #define BD71828_REG_RTC_YEAR 0x52 | |
162 | ||
163 | #define BD71828_REG_RTC_ALM0_SEC 0x53 | |
fe5a591b | 164 | #define BD71828_REG_RTC_ALM_START BD71828_REG_RTC_ALM0_SEC |
1c743ad5 MV |
165 | #define BD71828_REG_RTC_ALM0_MINUTE 0x54 |
166 | #define BD71828_REG_RTC_ALM0_HOUR 0x55 | |
167 | #define BD71828_REG_RTC_ALM0_WEEK 0x56 | |
168 | #define BD71828_REG_RTC_ALM0_DAY 0x57 | |
169 | #define BD71828_REG_RTC_ALM0_MONTH 0x58 | |
170 | #define BD71828_REG_RTC_ALM0_YEAR 0x59 | |
171 | #define BD71828_REG_RTC_ALM0_MASK 0x61 | |
172 | ||
173 | #define BD71828_REG_RTC_ALM1_SEC 0x5a | |
174 | #define BD71828_REG_RTC_ALM1_MINUTE 0x5b | |
175 | #define BD71828_REG_RTC_ALM1_HOUR 0x5c | |
176 | #define BD71828_REG_RTC_ALM1_WEEK 0x5d | |
177 | #define BD71828_REG_RTC_ALM1_DAY 0x5e | |
178 | #define BD71828_REG_RTC_ALM1_MONTH 0x5f | |
179 | #define BD71828_REG_RTC_ALM1_YEAR 0x60 | |
180 | #define BD71828_REG_RTC_ALM1_MASK 0x62 | |
181 | ||
182 | #define BD71828_REG_RTC_ALM2 0x63 | |
fe5a591b | 183 | #define BD71828_REG_RTC_START BD71828_REG_RTC_SEC |
1c743ad5 MV |
184 | |
185 | /* Charger/Battey */ | |
186 | #define BD71828_REG_CHG_STATE 0x65 | |
187 | #define BD71828_REG_CHG_FULL 0xd2 | |
188 | ||
1c743ad5 MV |
189 | /* LEDs */ |
190 | #define BD71828_REG_LED_CTRL 0x4A | |
191 | #define BD71828_MASK_LED_AMBER 0x80 | |
192 | #define BD71828_MASK_LED_GREEN 0x40 | |
193 | #define BD71828_LED_ON 0xff | |
194 | #define BD71828_LED_OFF 0x0 | |
195 | ||
196 | /* IRQ registers */ | |
197 | #define BD71828_REG_INT_MASK_BUCK 0xd3 | |
198 | #define BD71828_REG_INT_MASK_DCIN1 0xd4 | |
199 | #define BD71828_REG_INT_MASK_DCIN2 0xd5 | |
200 | #define BD71828_REG_INT_MASK_VSYS 0xd6 | |
201 | #define BD71828_REG_INT_MASK_CHG 0xd7 | |
202 | #define BD71828_REG_INT_MASK_BAT 0xd8 | |
203 | #define BD71828_REG_INT_MASK_BAT_MON1 0xd9 | |
204 | #define BD71828_REG_INT_MASK_BAT_MON2 0xda | |
205 | #define BD71828_REG_INT_MASK_BAT_MON3 0xdb | |
206 | #define BD71828_REG_INT_MASK_BAT_MON4 0xdc | |
207 | #define BD71828_REG_INT_MASK_TEMP 0xdd | |
208 | #define BD71828_REG_INT_MASK_RTC 0xde | |
209 | ||
1c743ad5 MV |
210 | #define BD71828_REG_INT_MAIN 0xdf |
211 | #define BD71828_REG_INT_BUCK 0xe0 | |
212 | #define BD71828_REG_INT_DCIN1 0xe1 | |
213 | #define BD71828_REG_INT_DCIN2 0xe2 | |
214 | #define BD71828_REG_INT_VSYS 0xe3 | |
215 | #define BD71828_REG_INT_CHG 0xe4 | |
216 | #define BD71828_REG_INT_BAT 0xe5 | |
217 | #define BD71828_REG_INT_BAT_MON1 0xe6 | |
218 | #define BD71828_REG_INT_BAT_MON2 0xe7 | |
219 | #define BD71828_REG_INT_BAT_MON3 0xe8 | |
220 | #define BD71828_REG_INT_BAT_MON4 0xe9 | |
221 | #define BD71828_REG_INT_TEMP 0xea | |
222 | #define BD71828_REG_INT_RTC 0xeb | |
223 | #define BD71828_REG_INT_UPDATE 0xec | |
224 | ||
225 | #define BD71828_MAX_REGISTER BD71828_REG_IO_STAT | |
226 | ||
227 | /* Masks for main IRQ register bits */ | |
228 | enum { | |
229 | BD71828_INT_BUCK, | |
230 | #define BD71828_INT_BUCK_MASK BIT(BD71828_INT_BUCK) | |
231 | BD71828_INT_DCIN, | |
232 | #define BD71828_INT_DCIN_MASK BIT(BD71828_INT_DCIN) | |
233 | BD71828_INT_VSYS, | |
234 | #define BD71828_INT_VSYS_MASK BIT(BD71828_INT_VSYS) | |
235 | BD71828_INT_CHG, | |
236 | #define BD71828_INT_CHG_MASK BIT(BD71828_INT_CHG) | |
237 | BD71828_INT_BAT, | |
238 | #define BD71828_INT_BAT_MASK BIT(BD71828_INT_BAT) | |
239 | BD71828_INT_BAT_MON, | |
240 | #define BD71828_INT_BAT_MON_MASK BIT(BD71828_INT_BAT_MON) | |
241 | BD71828_INT_TEMP, | |
242 | #define BD71828_INT_TEMP_MASK BIT(BD71828_INT_TEMP) | |
243 | BD71828_INT_RTC, | |
244 | #define BD71828_INT_RTC_MASK BIT(BD71828_INT_RTC) | |
245 | }; | |
246 | ||
247 | /* Interrupts */ | |
248 | enum { | |
249 | /* BUCK reg interrupts */ | |
250 | BD71828_INT_BUCK1_OCP, | |
251 | BD71828_INT_BUCK2_OCP, | |
252 | BD71828_INT_BUCK3_OCP, | |
253 | BD71828_INT_BUCK4_OCP, | |
254 | BD71828_INT_BUCK5_OCP, | |
255 | BD71828_INT_BUCK6_OCP, | |
256 | BD71828_INT_BUCK7_OCP, | |
257 | BD71828_INT_PGFAULT, | |
258 | /* DCIN1 interrupts */ | |
259 | BD71828_INT_DCIN_DET, | |
260 | BD71828_INT_DCIN_RMV, | |
261 | BD71828_INT_CLPS_OUT, | |
262 | BD71828_INT_CLPS_IN, | |
263 | /* DCIN2 interrupts */ | |
264 | BD71828_INT_DCIN_MON_RES, | |
265 | BD71828_INT_DCIN_MON_DET, | |
266 | BD71828_INT_LONGPUSH, | |
267 | BD71828_INT_MIDPUSH, | |
268 | BD71828_INT_SHORTPUSH, | |
269 | BD71828_INT_PUSH, | |
270 | BD71828_INT_WDOG, | |
271 | BD71828_INT_SWRESET, | |
272 | /* Vsys */ | |
273 | BD71828_INT_VSYS_UV_RES, | |
274 | BD71828_INT_VSYS_UV_DET, | |
275 | BD71828_INT_VSYS_LOW_RES, | |
276 | BD71828_INT_VSYS_LOW_DET, | |
277 | BD71828_INT_VSYS_HALL_IN, | |
278 | BD71828_INT_VSYS_HALL_TOGGLE, | |
279 | BD71828_INT_VSYS_MON_RES, | |
280 | BD71828_INT_VSYS_MON_DET, | |
281 | /* Charger */ | |
282 | BD71828_INT_CHG_DCIN_ILIM, | |
283 | BD71828_INT_CHG_TOPOFF_TO_DONE, | |
284 | BD71828_INT_CHG_WDG_TEMP, | |
285 | BD71828_INT_CHG_WDG_TIME, | |
286 | BD71828_INT_CHG_RECHARGE_RES, | |
287 | BD71828_INT_CHG_RECHARGE_DET, | |
288 | BD71828_INT_CHG_RANGED_TEMP_TRANSITION, | |
289 | BD71828_INT_CHG_STATE_TRANSITION, | |
290 | /* Battery */ | |
291 | BD71828_INT_BAT_TEMP_NORMAL, | |
292 | BD71828_INT_BAT_TEMP_ERANGE, | |
293 | BD71828_INT_BAT_TEMP_WARN, | |
294 | BD71828_INT_BAT_REMOVED, | |
295 | BD71828_INT_BAT_DETECTED, | |
296 | BD71828_INT_THERM_REMOVED, | |
297 | BD71828_INT_THERM_DETECTED, | |
298 | /* Battery Mon 1 */ | |
299 | BD71828_INT_BAT_DEAD, | |
300 | BD71828_INT_BAT_SHORTC_RES, | |
301 | BD71828_INT_BAT_SHORTC_DET, | |
302 | BD71828_INT_BAT_LOW_VOLT_RES, | |
303 | BD71828_INT_BAT_LOW_VOLT_DET, | |
304 | BD71828_INT_BAT_OVER_VOLT_RES, | |
305 | BD71828_INT_BAT_OVER_VOLT_DET, | |
306 | /* Battery Mon 2 */ | |
307 | BD71828_INT_BAT_MON_RES, | |
308 | BD71828_INT_BAT_MON_DET, | |
309 | /* Battery Mon 3 (Coulomb counter) */ | |
310 | BD71828_INT_BAT_CC_MON1, | |
311 | BD71828_INT_BAT_CC_MON2, | |
312 | BD71828_INT_BAT_CC_MON3, | |
313 | /* Battery Mon 4 */ | |
314 | BD71828_INT_BAT_OVER_CURR_1_RES, | |
315 | BD71828_INT_BAT_OVER_CURR_1_DET, | |
316 | BD71828_INT_BAT_OVER_CURR_2_RES, | |
317 | BD71828_INT_BAT_OVER_CURR_2_DET, | |
318 | BD71828_INT_BAT_OVER_CURR_3_RES, | |
319 | BD71828_INT_BAT_OVER_CURR_3_DET, | |
320 | /* Temperature */ | |
321 | BD71828_INT_TEMP_BAT_LOW_RES, | |
322 | BD71828_INT_TEMP_BAT_LOW_DET, | |
323 | BD71828_INT_TEMP_BAT_HI_RES, | |
324 | BD71828_INT_TEMP_BAT_HI_DET, | |
325 | BD71828_INT_TEMP_CHIP_OVER_125_RES, | |
326 | BD71828_INT_TEMP_CHIP_OVER_125_DET, | |
327 | BD71828_INT_TEMP_CHIP_OVER_VF_DET, | |
328 | BD71828_INT_TEMP_CHIP_OVER_VF_RES, | |
329 | /* RTC Alarm */ | |
330 | BD71828_INT_RTC0, | |
331 | BD71828_INT_RTC1, | |
332 | BD71828_INT_RTC2, | |
333 | }; | |
334 | ||
335 | #define BD71828_INT_BUCK1_OCP_MASK 0x1 | |
336 | #define BD71828_INT_BUCK2_OCP_MASK 0x2 | |
337 | #define BD71828_INT_BUCK3_OCP_MASK 0x4 | |
338 | #define BD71828_INT_BUCK4_OCP_MASK 0x8 | |
339 | #define BD71828_INT_BUCK5_OCP_MASK 0x10 | |
340 | #define BD71828_INT_BUCK6_OCP_MASK 0x20 | |
341 | #define BD71828_INT_BUCK7_OCP_MASK 0x40 | |
342 | #define BD71828_INT_PGFAULT_MASK 0x80 | |
343 | ||
344 | #define BD71828_INT_DCIN_DET_MASK 0x1 | |
345 | #define BD71828_INT_DCIN_RMV_MASK 0x2 | |
346 | #define BD71828_INT_CLPS_OUT_MASK 0x4 | |
347 | #define BD71828_INT_CLPS_IN_MASK 0x8 | |
348 | /* DCIN2 interrupts */ | |
349 | #define BD71828_INT_DCIN_MON_RES_MASK 0x1 | |
350 | #define BD71828_INT_DCIN_MON_DET_MASK 0x2 | |
351 | #define BD71828_INT_LONGPUSH_MASK 0x4 | |
352 | #define BD71828_INT_MIDPUSH_MASK 0x8 | |
353 | #define BD71828_INT_SHORTPUSH_MASK 0x10 | |
354 | #define BD71828_INT_PUSH_MASK 0x20 | |
355 | #define BD71828_INT_WDOG_MASK 0x40 | |
356 | #define BD71828_INT_SWRESET_MASK 0x80 | |
357 | /* Vsys */ | |
358 | #define BD71828_INT_VSYS_UV_RES_MASK 0x1 | |
359 | #define BD71828_INT_VSYS_UV_DET_MASK 0x2 | |
360 | #define BD71828_INT_VSYS_LOW_RES_MASK 0x4 | |
361 | #define BD71828_INT_VSYS_LOW_DET_MASK 0x8 | |
362 | #define BD71828_INT_VSYS_HALL_IN_MASK 0x10 | |
363 | #define BD71828_INT_VSYS_HALL_TOGGLE_MASK 0x20 | |
364 | #define BD71828_INT_VSYS_MON_RES_MASK 0x40 | |
365 | #define BD71828_INT_VSYS_MON_DET_MASK 0x80 | |
366 | /* Charger */ | |
367 | #define BD71828_INT_CHG_DCIN_ILIM_MASK 0x1 | |
368 | #define BD71828_INT_CHG_TOPOFF_TO_DONE_MASK 0x2 | |
369 | #define BD71828_INT_CHG_WDG_TEMP_MASK 0x4 | |
370 | #define BD71828_INT_CHG_WDG_TIME_MASK 0x8 | |
371 | #define BD71828_INT_CHG_RECHARGE_RES_MASK 0x10 | |
372 | #define BD71828_INT_CHG_RECHARGE_DET_MASK 0x20 | |
373 | #define BD71828_INT_CHG_RANGED_TEMP_TRANSITION_MASK 0x40 | |
374 | #define BD71828_INT_CHG_STATE_TRANSITION_MASK 0x80 | |
375 | /* Battery */ | |
376 | #define BD71828_INT_BAT_TEMP_NORMAL_MASK 0x1 | |
377 | #define BD71828_INT_BAT_TEMP_ERANGE_MASK 0x2 | |
378 | #define BD71828_INT_BAT_TEMP_WARN_MASK 0x4 | |
379 | #define BD71828_INT_BAT_REMOVED_MASK 0x10 | |
380 | #define BD71828_INT_BAT_DETECTED_MASK 0x20 | |
381 | #define BD71828_INT_THERM_REMOVED_MASK 0x40 | |
382 | #define BD71828_INT_THERM_DETECTED_MASK 0x80 | |
383 | /* Battery Mon 1 */ | |
384 | #define BD71828_INT_BAT_DEAD_MASK 0x2 | |
385 | #define BD71828_INT_BAT_SHORTC_RES_MASK 0x4 | |
386 | #define BD71828_INT_BAT_SHORTC_DET_MASK 0x8 | |
387 | #define BD71828_INT_BAT_LOW_VOLT_RES_MASK 0x10 | |
388 | #define BD71828_INT_BAT_LOW_VOLT_DET_MASK 0x20 | |
389 | #define BD71828_INT_BAT_OVER_VOLT_RES_MASK 0x40 | |
390 | #define BD71828_INT_BAT_OVER_VOLT_DET_MASK 0x80 | |
391 | /* Battery Mon 2 */ | |
392 | #define BD71828_INT_BAT_MON_RES_MASK 0x1 | |
393 | #define BD71828_INT_BAT_MON_DET_MASK 0x2 | |
394 | /* Battery Mon 3 (Coulomb counter) */ | |
395 | #define BD71828_INT_BAT_CC_MON1_MASK 0x1 | |
396 | #define BD71828_INT_BAT_CC_MON2_MASK 0x2 | |
397 | #define BD71828_INT_BAT_CC_MON3_MASK 0x4 | |
398 | /* Battery Mon 4 */ | |
399 | #define BD71828_INT_BAT_OVER_CURR_1_RES_MASK 0x1 | |
400 | #define BD71828_INT_BAT_OVER_CURR_1_DET_MASK 0x2 | |
401 | #define BD71828_INT_BAT_OVER_CURR_2_RES_MASK 0x4 | |
402 | #define BD71828_INT_BAT_OVER_CURR_2_DET_MASK 0x8 | |
403 | #define BD71828_INT_BAT_OVER_CURR_3_RES_MASK 0x10 | |
404 | #define BD71828_INT_BAT_OVER_CURR_3_DET_MASK 0x20 | |
405 | /* Temperature */ | |
406 | #define BD71828_INT_TEMP_BAT_LOW_RES_MASK 0x1 | |
407 | #define BD71828_INT_TEMP_BAT_LOW_DET_MASK 0x2 | |
408 | #define BD71828_INT_TEMP_BAT_HI_RES_MASK 0x4 | |
409 | #define BD71828_INT_TEMP_BAT_HI_DET_MASK 0x8 | |
410 | #define BD71828_INT_TEMP_CHIP_OVER_125_RES_MASK 0x10 | |
411 | #define BD71828_INT_TEMP_CHIP_OVER_125_DET_MASK 0x20 | |
412 | #define BD71828_INT_TEMP_CHIP_OVER_VF_RES_MASK 0x40 | |
413 | #define BD71828_INT_TEMP_CHIP_OVER_VF_DET_MASK 0x80 | |
414 | /* RTC Alarm */ | |
415 | #define BD71828_INT_RTC0_MASK 0x1 | |
416 | #define BD71828_INT_RTC1_MASK 0x2 | |
417 | #define BD71828_INT_RTC2_MASK 0x4 | |
418 | ||
1c743ad5 MV |
419 | #define BD71828_OUT_TYPE_MASK 0x2 |
420 | #define BD71828_OUT_TYPE_OPEN_DRAIN 0x0 | |
421 | #define BD71828_OUT_TYPE_CMOS 0x2 | |
422 | ||
423 | #endif /* __LINUX_MFD_BD71828_H__ */ |