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67d16a46 WW |
1 | /* Driver for Realtek PCI-Express card reader |
2 | * | |
09fd8678 | 3 | * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved. |
67d16a46 WW |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify it | |
6 | * under the terms of the GNU General Public License as published by the | |
7 | * Free Software Foundation; either version 2, or (at your option) any | |
8 | * later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, but | |
11 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
13 | * General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License along | |
16 | * with this program; if not, see <http://www.gnu.org/licenses/>. | |
17 | * | |
18 | * Author: | |
19 | * Wei WANG <wei_wang@realsil.com.cn> | |
67d16a46 WW |
20 | */ |
21 | ||
22 | #ifndef __RTSX_PCI_H | |
23 | #define __RTSX_PCI_H | |
24 | ||
25 | #include <linux/sched.h> | |
26 | #include <linux/pci.h> | |
5947c167 | 27 | #include <linux/mfd/rtsx_common.h> |
67d16a46 WW |
28 | |
29 | #define MAX_RW_REG_CNT 1024 | |
30 | ||
31 | /* PCI Operation Register Address */ | |
32 | #define RTSX_HCBAR 0x00 | |
33 | #define RTSX_HCBCTLR 0x04 | |
34 | #define RTSX_HDBAR 0x08 | |
35 | #define RTSX_HDBCTLR 0x0C | |
36 | #define RTSX_HAIMR 0x10 | |
37 | #define RTSX_BIPR 0x14 | |
38 | #define RTSX_BIER 0x18 | |
39 | ||
40 | /* Host command buffer control register */ | |
41 | #define STOP_CMD (0x01 << 28) | |
42 | ||
43 | /* Host data buffer control register */ | |
44 | #define SDMA_MODE 0x00 | |
45 | #define ADMA_MODE (0x02 << 26) | |
46 | #define STOP_DMA (0x01 << 28) | |
47 | #define TRIG_DMA (0x01 << 31) | |
48 | ||
49 | /* Host access internal memory register */ | |
50 | #define HAIMR_TRANS_START (0x01 << 31) | |
51 | #define HAIMR_READ 0x00 | |
52 | #define HAIMR_WRITE (0x01 << 30) | |
53 | #define HAIMR_READ_START (HAIMR_TRANS_START | HAIMR_READ) | |
54 | #define HAIMR_WRITE_START (HAIMR_TRANS_START | HAIMR_WRITE) | |
55 | #define HAIMR_TRANS_END (HAIMR_TRANS_START) | |
56 | ||
57 | /* Bus interrupt pending register */ | |
58 | #define CMD_DONE_INT (1 << 31) | |
59 | #define DATA_DONE_INT (1 << 30) | |
60 | #define TRANS_OK_INT (1 << 29) | |
61 | #define TRANS_FAIL_INT (1 << 28) | |
62 | #define XD_INT (1 << 27) | |
63 | #define MS_INT (1 << 26) | |
64 | #define SD_INT (1 << 25) | |
65 | #define GPIO0_INT (1 << 24) | |
66 | #define OC_INT (1 << 23) | |
67 | #define SD_WRITE_PROTECT (1 << 19) | |
68 | #define XD_EXIST (1 << 18) | |
69 | #define MS_EXIST (1 << 17) | |
70 | #define SD_EXIST (1 << 16) | |
71 | #define DELINK_INT GPIO0_INT | |
72 | #define MS_OC_INT (1 << 23) | |
73 | #define SD_OC_INT (1 << 22) | |
74 | ||
75 | #define CARD_INT (XD_INT | MS_INT | SD_INT) | |
76 | #define NEED_COMPLETE_INT (DATA_DONE_INT | TRANS_OK_INT | TRANS_FAIL_INT) | |
77 | #define RTSX_INT (CMD_DONE_INT | NEED_COMPLETE_INT | \ | |
78 | CARD_INT | GPIO0_INT | OC_INT) | |
79 | ||
80 | #define CARD_EXIST (XD_EXIST | MS_EXIST | SD_EXIST) | |
81 | ||
82 | /* Bus interrupt enable register */ | |
83 | #define CMD_DONE_INT_EN (1 << 31) | |
84 | #define DATA_DONE_INT_EN (1 << 30) | |
85 | #define TRANS_OK_INT_EN (1 << 29) | |
86 | #define TRANS_FAIL_INT_EN (1 << 28) | |
87 | #define XD_INT_EN (1 << 27) | |
88 | #define MS_INT_EN (1 << 26) | |
89 | #define SD_INT_EN (1 << 25) | |
90 | #define GPIO0_INT_EN (1 << 24) | |
91 | #define OC_INT_EN (1 << 23) | |
92 | #define DELINK_INT_EN GPIO0_INT_EN | |
93 | #define MS_OC_INT_EN (1 << 23) | |
94 | #define SD_OC_INT_EN (1 << 22) | |
95 | ||
96 | #define READ_REG_CMD 0 | |
97 | #define WRITE_REG_CMD 1 | |
98 | #define CHECK_REG_CMD 2 | |
99 | ||
100 | /* | |
101 | * macros for easy use | |
102 | */ | |
103 | #define rtsx_pci_writel(pcr, reg, value) \ | |
104 | iowrite32(value, (pcr)->remap_addr + reg) | |
105 | #define rtsx_pci_readl(pcr, reg) \ | |
106 | ioread32((pcr)->remap_addr + reg) | |
107 | #define rtsx_pci_writew(pcr, reg, value) \ | |
108 | iowrite16(value, (pcr)->remap_addr + reg) | |
109 | #define rtsx_pci_readw(pcr, reg) \ | |
110 | ioread16((pcr)->remap_addr + reg) | |
111 | #define rtsx_pci_writeb(pcr, reg, value) \ | |
112 | iowrite8(value, (pcr)->remap_addr + reg) | |
113 | #define rtsx_pci_readb(pcr, reg) \ | |
114 | ioread8((pcr)->remap_addr + reg) | |
115 | ||
116 | #define rtsx_pci_read_config_byte(pcr, where, val) \ | |
117 | pci_read_config_byte((pcr)->pci, where, val) | |
118 | ||
119 | #define rtsx_pci_write_config_byte(pcr, where, val) \ | |
120 | pci_write_config_byte((pcr)->pci, where, val) | |
121 | ||
122 | #define rtsx_pci_read_config_dword(pcr, where, val) \ | |
123 | pci_read_config_dword((pcr)->pci, where, val) | |
124 | ||
125 | #define rtsx_pci_write_config_dword(pcr, where, val) \ | |
126 | pci_write_config_dword((pcr)->pci, where, val) | |
127 | ||
128 | #define STATE_TRANS_NONE 0 | |
129 | #define STATE_TRANS_CMD 1 | |
130 | #define STATE_TRANS_BUF 2 | |
131 | #define STATE_TRANS_SG 3 | |
132 | ||
133 | #define TRANS_NOT_READY 0 | |
134 | #define TRANS_RESULT_OK 1 | |
135 | #define TRANS_RESULT_FAIL 2 | |
136 | #define TRANS_NO_DEVICE 3 | |
137 | ||
138 | #define RTSX_RESV_BUF_LEN 4096 | |
139 | #define HOST_CMDS_BUF_LEN 1024 | |
140 | #define HOST_SG_TBL_BUF_LEN (RTSX_RESV_BUF_LEN - HOST_CMDS_BUF_LEN) | |
141 | #define HOST_SG_TBL_ITEMS (HOST_SG_TBL_BUF_LEN / 8) | |
142 | #define MAX_SG_ITEM_LEN 0x80000 | |
143 | ||
144 | #define HOST_TO_DEVICE 0 | |
145 | #define DEVICE_TO_HOST 1 | |
146 | ||
abcc6b29 | 147 | #define RTSX_PHASE_MAX 32 |
67d16a46 WW |
148 | #define RX_TUNING_CNT 3 |
149 | ||
150 | /* SG descriptor */ | |
151 | #define SG_INT 0x04 | |
152 | #define SG_END 0x02 | |
153 | #define SG_VALID 0x01 | |
154 | ||
155 | #define SG_NO_OP 0x00 | |
156 | #define SG_TRANS_DATA (0x02 << 4) | |
157 | #define SG_LINK_DESC (0x03 << 4) | |
158 | ||
d817ac4e WW |
159 | /* Output voltage */ |
160 | #define OUTPUT_3V3 0 | |
161 | #define OUTPUT_1V8 1 | |
67d16a46 WW |
162 | |
163 | /* Card Clock Enable Register */ | |
164 | #define SD_CLK_EN 0x04 | |
165 | #define MS_CLK_EN 0x08 | |
166 | ||
167 | /* Card Select Register */ | |
168 | #define SD_MOD_SEL 2 | |
169 | #define MS_MOD_SEL 3 | |
170 | ||
171 | /* Card Output Enable Register */ | |
172 | #define SD_OUTPUT_EN 0x04 | |
173 | #define MS_OUTPUT_EN 0x08 | |
174 | ||
175 | /* CARD_SHARE_MODE */ | |
176 | #define CARD_SHARE_MASK 0x0F | |
177 | #define CARD_SHARE_MULTI_LUN 0x00 | |
178 | #define CARD_SHARE_NORMAL 0x00 | |
179 | #define CARD_SHARE_48_SD 0x04 | |
180 | #define CARD_SHARE_48_MS 0x08 | |
181 | /* CARD_SHARE_MODE for barossa */ | |
182 | #define CARD_SHARE_BAROSSA_SD 0x01 | |
183 | #define CARD_SHARE_BAROSSA_MS 0x02 | |
184 | ||
773ccdfd WW |
185 | /* CARD_DRIVE_SEL */ |
186 | #define MS_DRIVE_8mA (0x01 << 6) | |
187 | #define MMC_DRIVE_8mA (0x01 << 4) | |
188 | #define XD_DRIVE_8mA (0x01 << 2) | |
189 | #define GPIO_DRIVE_8mA 0x01 | |
190 | #define RTS5209_CARD_DRIVE_DEFAULT (MS_DRIVE_8mA | MMC_DRIVE_8mA |\ | |
191 | XD_DRIVE_8mA | GPIO_DRIVE_8mA) | |
192 | #define RTL8411_CARD_DRIVE_DEFAULT (MS_DRIVE_8mA | MMC_DRIVE_8mA |\ | |
193 | XD_DRIVE_8mA) | |
194 | #define RTSX_CARD_DRIVE_DEFAULT (MS_DRIVE_8mA | GPIO_DRIVE_8mA) | |
195 | ||
67d16a46 WW |
196 | /* SD30_DRIVE_SEL */ |
197 | #define DRIVER_TYPE_A 0x05 | |
198 | #define DRIVER_TYPE_B 0x03 | |
199 | #define DRIVER_TYPE_C 0x02 | |
200 | #define DRIVER_TYPE_D 0x01 | |
773ccdfd WW |
201 | #define CFG_DRIVER_TYPE_A 0x02 |
202 | #define CFG_DRIVER_TYPE_B 0x03 | |
203 | #define CFG_DRIVER_TYPE_C 0x01 | |
204 | #define CFG_DRIVER_TYPE_D 0x00 | |
67d16a46 WW |
205 | |
206 | /* FPDCTL */ | |
207 | #define SSC_POWER_DOWN 0x01 | |
208 | #define SD_OC_POWER_DOWN 0x02 | |
209 | #define ALL_POWER_DOWN 0x07 | |
210 | #define OC_POWER_DOWN 0x06 | |
211 | ||
212 | /* CLK_CTL */ | |
213 | #define CHANGE_CLK 0x01 | |
214 | ||
215 | /* LDO_CTL */ | |
d817ac4e WW |
216 | #define BPP_ASIC_1V7 0x00 |
217 | #define BPP_ASIC_1V8 0x01 | |
218 | #define BPP_ASIC_1V9 0x02 | |
219 | #define BPP_ASIC_2V0 0x03 | |
220 | #define BPP_ASIC_2V7 0x04 | |
221 | #define BPP_ASIC_2V8 0x05 | |
222 | #define BPP_ASIC_3V2 0x06 | |
223 | #define BPP_ASIC_3V3 0x07 | |
224 | #define BPP_REG_TUNED18 0x07 | |
225 | #define BPP_TUNED18_SHIFT_8402 5 | |
226 | #define BPP_TUNED18_SHIFT_8411 4 | |
227 | #define BPP_PAD_MASK 0x04 | |
228 | #define BPP_PAD_3V3 0x04 | |
229 | #define BPP_PAD_1V8 0x00 | |
67d16a46 WW |
230 | #define BPP_LDO_POWB 0x03 |
231 | #define BPP_LDO_ON 0x00 | |
232 | #define BPP_LDO_SUSPEND 0x02 | |
233 | #define BPP_LDO_OFF 0x03 | |
234 | ||
235 | /* CD_PAD_CTL */ | |
236 | #define CD_DISABLE_MASK 0x07 | |
237 | #define MS_CD_DISABLE 0x04 | |
238 | #define SD_CD_DISABLE 0x02 | |
239 | #define XD_CD_DISABLE 0x01 | |
240 | #define CD_DISABLE 0x07 | |
241 | #define CD_ENABLE 0x00 | |
242 | #define MS_CD_EN_ONLY 0x03 | |
243 | #define SD_CD_EN_ONLY 0x05 | |
244 | #define XD_CD_EN_ONLY 0x06 | |
245 | #define FORCE_CD_LOW_MASK 0x38 | |
246 | #define FORCE_CD_XD_LOW 0x08 | |
247 | #define FORCE_CD_SD_LOW 0x10 | |
248 | #define FORCE_CD_MS_LOW 0x20 | |
249 | #define CD_AUTO_DISABLE 0x40 | |
250 | ||
251 | /* SD_STAT1 */ | |
252 | #define SD_CRC7_ERR 0x80 | |
253 | #define SD_CRC16_ERR 0x40 | |
254 | #define SD_CRC_WRITE_ERR 0x20 | |
255 | #define SD_CRC_WRITE_ERR_MASK 0x1C | |
256 | #define GET_CRC_TIME_OUT 0x02 | |
257 | #define SD_TUNING_COMPARE_ERR 0x01 | |
258 | ||
259 | /* SD_STAT2 */ | |
260 | #define SD_RSP_80CLK_TIMEOUT 0x01 | |
261 | ||
262 | /* SD_BUS_STAT */ | |
263 | #define SD_CLK_TOGGLE_EN 0x80 | |
264 | #define SD_CLK_FORCE_STOP 0x40 | |
265 | #define SD_DAT3_STATUS 0x10 | |
266 | #define SD_DAT2_STATUS 0x08 | |
267 | #define SD_DAT1_STATUS 0x04 | |
268 | #define SD_DAT0_STATUS 0x02 | |
269 | #define SD_CMD_STATUS 0x01 | |
270 | ||
271 | /* SD_PAD_CTL */ | |
272 | #define SD_IO_USING_1V8 0x80 | |
273 | #define SD_IO_USING_3V3 0x7F | |
274 | #define TYPE_A_DRIVING 0x00 | |
275 | #define TYPE_B_DRIVING 0x01 | |
276 | #define TYPE_C_DRIVING 0x02 | |
277 | #define TYPE_D_DRIVING 0x03 | |
278 | ||
279 | /* SD_SAMPLE_POINT_CTL */ | |
280 | #define DDR_FIX_RX_DAT 0x00 | |
281 | #define DDR_VAR_RX_DAT 0x80 | |
282 | #define DDR_FIX_RX_DAT_EDGE 0x00 | |
283 | #define DDR_FIX_RX_DAT_14_DELAY 0x40 | |
284 | #define DDR_FIX_RX_CMD 0x00 | |
285 | #define DDR_VAR_RX_CMD 0x20 | |
286 | #define DDR_FIX_RX_CMD_POS_EDGE 0x00 | |
287 | #define DDR_FIX_RX_CMD_14_DELAY 0x10 | |
288 | #define SD20_RX_POS_EDGE 0x00 | |
289 | #define SD20_RX_14_DELAY 0x08 | |
290 | #define SD20_RX_SEL_MASK 0x08 | |
291 | ||
292 | /* SD_PUSH_POINT_CTL */ | |
293 | #define DDR_FIX_TX_CMD_DAT 0x00 | |
294 | #define DDR_VAR_TX_CMD_DAT 0x80 | |
295 | #define DDR_FIX_TX_DAT_14_TSU 0x00 | |
296 | #define DDR_FIX_TX_DAT_12_TSU 0x40 | |
297 | #define DDR_FIX_TX_CMD_NEG_EDGE 0x00 | |
298 | #define DDR_FIX_TX_CMD_14_AHEAD 0x20 | |
299 | #define SD20_TX_NEG_EDGE 0x00 | |
300 | #define SD20_TX_14_AHEAD 0x10 | |
301 | #define SD20_TX_SEL_MASK 0x10 | |
302 | #define DDR_VAR_SDCLK_POL_SWAP 0x01 | |
303 | ||
304 | /* SD_TRANSFER */ | |
305 | #define SD_TRANSFER_START 0x80 | |
306 | #define SD_TRANSFER_END 0x40 | |
307 | #define SD_STAT_IDLE 0x20 | |
308 | #define SD_TRANSFER_ERR 0x10 | |
309 | /* SD Transfer Mode definition */ | |
310 | #define SD_TM_NORMAL_WRITE 0x00 | |
311 | #define SD_TM_AUTO_WRITE_3 0x01 | |
312 | #define SD_TM_AUTO_WRITE_4 0x02 | |
313 | #define SD_TM_AUTO_READ_3 0x05 | |
314 | #define SD_TM_AUTO_READ_4 0x06 | |
315 | #define SD_TM_CMD_RSP 0x08 | |
316 | #define SD_TM_AUTO_WRITE_1 0x09 | |
317 | #define SD_TM_AUTO_WRITE_2 0x0A | |
318 | #define SD_TM_NORMAL_READ 0x0C | |
319 | #define SD_TM_AUTO_READ_1 0x0D | |
320 | #define SD_TM_AUTO_READ_2 0x0E | |
321 | #define SD_TM_AUTO_TUNING 0x0F | |
322 | ||
323 | /* SD_VPTX_CTL / SD_VPRX_CTL */ | |
324 | #define PHASE_CHANGE 0x80 | |
325 | #define PHASE_NOT_RESET 0x40 | |
326 | ||
327 | /* SD_DCMPS_TX_CTL / SD_DCMPS_RX_CTL */ | |
328 | #define DCMPS_CHANGE 0x80 | |
329 | #define DCMPS_CHANGE_DONE 0x40 | |
330 | #define DCMPS_ERROR 0x20 | |
331 | #define DCMPS_CURRENT_PHASE 0x1F | |
332 | ||
333 | /* SD Configure 1 Register */ | |
334 | #define SD_CLK_DIVIDE_0 0x00 | |
335 | #define SD_CLK_DIVIDE_256 0xC0 | |
336 | #define SD_CLK_DIVIDE_128 0x80 | |
337 | #define SD_BUS_WIDTH_1BIT 0x00 | |
338 | #define SD_BUS_WIDTH_4BIT 0x01 | |
339 | #define SD_BUS_WIDTH_8BIT 0x02 | |
340 | #define SD_ASYNC_FIFO_NOT_RST 0x10 | |
341 | #define SD_20_MODE 0x00 | |
342 | #define SD_DDR_MODE 0x04 | |
343 | #define SD_30_MODE 0x08 | |
344 | ||
345 | #define SD_CLK_DIVIDE_MASK 0xC0 | |
346 | ||
347 | /* SD_CMD_STATE */ | |
348 | #define SD_CMD_IDLE 0x80 | |
349 | ||
350 | /* SD_DATA_STATE */ | |
351 | #define SD_DATA_IDLE 0x80 | |
352 | ||
353 | /* DCM_DRP_CTL */ | |
354 | #define DCM_RESET 0x08 | |
355 | #define DCM_LOCKED 0x04 | |
356 | #define DCM_208M 0x00 | |
357 | #define DCM_TX 0x01 | |
358 | #define DCM_RX 0x02 | |
359 | ||
360 | /* DCM_DRP_TRIG */ | |
361 | #define DRP_START 0x80 | |
362 | #define DRP_DONE 0x40 | |
363 | ||
364 | /* DCM_DRP_CFG */ | |
365 | #define DRP_WRITE 0x80 | |
366 | #define DRP_READ 0x00 | |
367 | #define DCM_WRITE_ADDRESS_50 0x50 | |
368 | #define DCM_WRITE_ADDRESS_51 0x51 | |
369 | #define DCM_READ_ADDRESS_00 0x00 | |
370 | #define DCM_READ_ADDRESS_51 0x51 | |
371 | ||
372 | /* IRQSTAT0 */ | |
373 | #define DMA_DONE_INT 0x80 | |
374 | #define SUSPEND_INT 0x40 | |
375 | #define LINK_RDY_INT 0x20 | |
376 | #define LINK_DOWN_INT 0x10 | |
377 | ||
378 | /* DMACTL */ | |
379 | #define DMA_RST 0x80 | |
380 | #define DMA_BUSY 0x04 | |
381 | #define DMA_DIR_TO_CARD 0x00 | |
382 | #define DMA_DIR_FROM_CARD 0x02 | |
383 | #define DMA_EN 0x01 | |
384 | #define DMA_128 (0 << 4) | |
385 | #define DMA_256 (1 << 4) | |
386 | #define DMA_512 (2 << 4) | |
387 | #define DMA_1024 (3 << 4) | |
388 | #define DMA_PACK_SIZE_MASK 0x30 | |
389 | ||
390 | /* SSC_CTL1 */ | |
391 | #define SSC_RSTB 0x80 | |
392 | #define SSC_8X_EN 0x40 | |
393 | #define SSC_FIX_FRAC 0x20 | |
394 | #define SSC_SEL_1M 0x00 | |
395 | #define SSC_SEL_2M 0x08 | |
396 | #define SSC_SEL_4M 0x10 | |
397 | #define SSC_SEL_8M 0x18 | |
398 | ||
399 | /* SSC_CTL2 */ | |
400 | #define SSC_DEPTH_MASK 0x07 | |
401 | #define SSC_DEPTH_DISALBE 0x00 | |
402 | #define SSC_DEPTH_4M 0x01 | |
403 | #define SSC_DEPTH_2M 0x02 | |
404 | #define SSC_DEPTH_1M 0x03 | |
405 | #define SSC_DEPTH_500K 0x04 | |
406 | #define SSC_DEPTH_250K 0x05 | |
407 | ||
408 | /* System Clock Control Register */ | |
409 | #define CLK_LOW_FREQ 0x01 | |
410 | ||
411 | /* System Clock Divider Register */ | |
412 | #define CLK_DIV_1 0x01 | |
413 | #define CLK_DIV_2 0x02 | |
414 | #define CLK_DIV_4 0x03 | |
415 | #define CLK_DIV_8 0x04 | |
416 | ||
417 | /* MS_CFG */ | |
418 | #define SAMPLE_TIME_RISING 0x00 | |
419 | #define SAMPLE_TIME_FALLING 0x80 | |
420 | #define PUSH_TIME_DEFAULT 0x00 | |
421 | #define PUSH_TIME_ODD 0x40 | |
422 | #define NO_EXTEND_TOGGLE 0x00 | |
423 | #define EXTEND_TOGGLE_CHK 0x20 | |
424 | #define MS_BUS_WIDTH_1 0x00 | |
425 | #define MS_BUS_WIDTH_4 0x10 | |
426 | #define MS_BUS_WIDTH_8 0x18 | |
427 | #define MS_2K_SECTOR_MODE 0x04 | |
428 | #define MS_512_SECTOR_MODE 0x00 | |
429 | #define MS_TOGGLE_TIMEOUT_EN 0x00 | |
430 | #define MS_TOGGLE_TIMEOUT_DISEN 0x01 | |
431 | #define MS_NO_CHECK_INT 0x02 | |
432 | ||
433 | /* MS_TRANS_CFG */ | |
434 | #define WAIT_INT 0x80 | |
435 | #define NO_WAIT_INT 0x00 | |
436 | #define NO_AUTO_READ_INT_REG 0x00 | |
437 | #define AUTO_READ_INT_REG 0x40 | |
438 | #define MS_CRC16_ERR 0x20 | |
439 | #define MS_RDY_TIMEOUT 0x10 | |
440 | #define MS_INT_CMDNK 0x08 | |
441 | #define MS_INT_BREQ 0x04 | |
442 | #define MS_INT_ERR 0x02 | |
443 | #define MS_INT_CED 0x01 | |
444 | ||
445 | /* MS_TRANSFER */ | |
446 | #define MS_TRANSFER_START 0x80 | |
447 | #define MS_TRANSFER_END 0x40 | |
448 | #define MS_TRANSFER_ERR 0x20 | |
449 | #define MS_BS_STATE 0x10 | |
450 | #define MS_TM_READ_BYTES 0x00 | |
451 | #define MS_TM_NORMAL_READ 0x01 | |
452 | #define MS_TM_WRITE_BYTES 0x04 | |
453 | #define MS_TM_NORMAL_WRITE 0x05 | |
454 | #define MS_TM_AUTO_READ 0x08 | |
455 | #define MS_TM_AUTO_WRITE 0x0C | |
456 | ||
457 | /* SD Configure 2 Register */ | |
458 | #define SD_CALCULATE_CRC7 0x00 | |
459 | #define SD_NO_CALCULATE_CRC7 0x80 | |
460 | #define SD_CHECK_CRC16 0x00 | |
461 | #define SD_NO_CHECK_CRC16 0x40 | |
462 | #define SD_NO_CHECK_WAIT_CRC_TO 0x20 | |
463 | #define SD_WAIT_BUSY_END 0x08 | |
464 | #define SD_NO_WAIT_BUSY_END 0x00 | |
465 | #define SD_CHECK_CRC7 0x00 | |
466 | #define SD_NO_CHECK_CRC7 0x04 | |
467 | #define SD_RSP_LEN_0 0x00 | |
468 | #define SD_RSP_LEN_6 0x01 | |
469 | #define SD_RSP_LEN_17 0x02 | |
470 | /* SD/MMC Response Type Definition */ | |
471 | #define SD_RSP_TYPE_R0 0x04 | |
472 | #define SD_RSP_TYPE_R1 0x01 | |
473 | #define SD_RSP_TYPE_R1b 0x09 | |
474 | #define SD_RSP_TYPE_R2 0x02 | |
475 | #define SD_RSP_TYPE_R3 0x05 | |
476 | #define SD_RSP_TYPE_R4 0x05 | |
477 | #define SD_RSP_TYPE_R5 0x01 | |
478 | #define SD_RSP_TYPE_R6 0x01 | |
479 | #define SD_RSP_TYPE_R7 0x01 | |
480 | ||
3730bb8b | 481 | /* SD_CONFIGURE3 */ |
67d16a46 WW |
482 | #define SD_RSP_80CLK_TIMEOUT_EN 0x01 |
483 | ||
484 | /* Card Transfer Reset Register */ | |
485 | #define SPI_STOP 0x01 | |
486 | #define XD_STOP 0x02 | |
487 | #define SD_STOP 0x04 | |
488 | #define MS_STOP 0x08 | |
489 | #define SPI_CLR_ERR 0x10 | |
490 | #define XD_CLR_ERR 0x20 | |
491 | #define SD_CLR_ERR 0x40 | |
492 | #define MS_CLR_ERR 0x80 | |
493 | ||
494 | /* Card Data Source Register */ | |
495 | #define PINGPONG_BUFFER 0x01 | |
496 | #define RING_BUFFER 0x00 | |
497 | ||
498 | /* Card Power Control Register */ | |
499 | #define PMOS_STRG_MASK 0x10 | |
500 | #define PMOS_STRG_800mA 0x10 | |
501 | #define PMOS_STRG_400mA 0x00 | |
502 | #define SD_POWER_OFF 0x03 | |
503 | #define SD_PARTIAL_POWER_ON 0x01 | |
504 | #define SD_POWER_ON 0x00 | |
505 | #define SD_POWER_MASK 0x03 | |
506 | #define MS_POWER_OFF 0x0C | |
507 | #define MS_PARTIAL_POWER_ON 0x04 | |
508 | #define MS_POWER_ON 0x00 | |
509 | #define MS_POWER_MASK 0x0C | |
510 | #define BPP_POWER_OFF 0x0F | |
511 | #define BPP_POWER_5_PERCENT_ON 0x0E | |
512 | #define BPP_POWER_10_PERCENT_ON 0x0C | |
513 | #define BPP_POWER_15_PERCENT_ON 0x08 | |
514 | #define BPP_POWER_ON 0x00 | |
515 | #define BPP_POWER_MASK 0x0F | |
4c4b8c10 WW |
516 | #define SD_VCC_PARTIAL_POWER_ON 0x02 |
517 | #define SD_VCC_POWER_ON 0x00 | |
67d16a46 WW |
518 | |
519 | /* PWR_GATE_CTRL */ | |
520 | #define PWR_GATE_EN 0x01 | |
521 | #define LDO3318_PWR_MASK 0x06 | |
522 | #define LDO_ON 0x00 | |
523 | #define LDO_SUSPEND 0x04 | |
524 | #define LDO_OFF 0x06 | |
525 | ||
526 | /* CARD_CLK_SOURCE */ | |
527 | #define CRC_FIX_CLK (0x00 << 0) | |
528 | #define CRC_VAR_CLK0 (0x01 << 0) | |
529 | #define CRC_VAR_CLK1 (0x02 << 0) | |
530 | #define SD30_FIX_CLK (0x00 << 2) | |
531 | #define SD30_VAR_CLK0 (0x01 << 2) | |
532 | #define SD30_VAR_CLK1 (0x02 << 2) | |
533 | #define SAMPLE_FIX_CLK (0x00 << 4) | |
534 | #define SAMPLE_VAR_CLK0 (0x01 << 4) | |
535 | #define SAMPLE_VAR_CLK1 (0x02 << 4) | |
536 | ||
5947c167 WW |
537 | /* HOST_SLEEP_STATE */ |
538 | #define HOST_ENTER_S1 1 | |
539 | #define HOST_ENTER_S3 2 | |
540 | ||
67d16a46 WW |
541 | #define MS_CFG 0xFD40 |
542 | #define MS_TPC 0xFD41 | |
543 | #define MS_TRANS_CFG 0xFD42 | |
544 | #define MS_TRANSFER 0xFD43 | |
545 | #define MS_INT_REG 0xFD44 | |
546 | #define MS_BYTE_CNT 0xFD45 | |
547 | #define MS_SECTOR_CNT_L 0xFD46 | |
548 | #define MS_SECTOR_CNT_H 0xFD47 | |
549 | #define MS_DBUS_H 0xFD48 | |
550 | ||
551 | #define SD_CFG1 0xFDA0 | |
552 | #define SD_CFG2 0xFDA1 | |
553 | #define SD_CFG3 0xFDA2 | |
554 | #define SD_STAT1 0xFDA3 | |
555 | #define SD_STAT2 0xFDA4 | |
556 | #define SD_BUS_STAT 0xFDA5 | |
557 | #define SD_PAD_CTL 0xFDA6 | |
558 | #define SD_SAMPLE_POINT_CTL 0xFDA7 | |
559 | #define SD_PUSH_POINT_CTL 0xFDA8 | |
560 | #define SD_CMD0 0xFDA9 | |
a3b63979 | 561 | #define SD_CMD_START 0x40 |
67d16a46 WW |
562 | #define SD_CMD1 0xFDAA |
563 | #define SD_CMD2 0xFDAB | |
564 | #define SD_CMD3 0xFDAC | |
565 | #define SD_CMD4 0xFDAD | |
566 | #define SD_CMD5 0xFDAE | |
567 | #define SD_BYTE_CNT_L 0xFDAF | |
568 | #define SD_BYTE_CNT_H 0xFDB0 | |
569 | #define SD_BLOCK_CNT_L 0xFDB1 | |
570 | #define SD_BLOCK_CNT_H 0xFDB2 | |
571 | #define SD_TRANSFER 0xFDB3 | |
572 | #define SD_CMD_STATE 0xFDB5 | |
573 | #define SD_DATA_STATE 0xFDB6 | |
574 | ||
575 | #define SRCTL 0xFC13 | |
576 | ||
577 | #define DCM_DRP_CTL 0xFC23 | |
578 | #define DCM_DRP_TRIG 0xFC24 | |
579 | #define DCM_DRP_CFG 0xFC25 | |
580 | #define DCM_DRP_WR_DATA_L 0xFC26 | |
581 | #define DCM_DRP_WR_DATA_H 0xFC27 | |
582 | #define DCM_DRP_RD_DATA_L 0xFC28 | |
583 | #define DCM_DRP_RD_DATA_H 0xFC29 | |
584 | #define SD_VPCLK0_CTL 0xFC2A | |
585 | #define SD_VPCLK1_CTL 0xFC2B | |
586 | #define SD_DCMPS0_CTL 0xFC2C | |
587 | #define SD_DCMPS1_CTL 0xFC2D | |
588 | #define SD_VPTX_CTL SD_VPCLK0_CTL | |
589 | #define SD_VPRX_CTL SD_VPCLK1_CTL | |
590 | #define SD_DCMPS_TX_CTL SD_DCMPS0_CTL | |
591 | #define SD_DCMPS_RX_CTL SD_DCMPS1_CTL | |
592 | #define CARD_CLK_SOURCE 0xFC2E | |
593 | ||
594 | #define CARD_PWR_CTL 0xFD50 | |
595 | #define CARD_CLK_SWITCH 0xFD51 | |
9032eabd | 596 | #define RTL8411B_PACKAGE_MODE 0xFD51 |
67d16a46 WW |
597 | #define CARD_SHARE_MODE 0xFD52 |
598 | #define CARD_DRIVE_SEL 0xFD53 | |
599 | #define CARD_STOP 0xFD54 | |
600 | #define CARD_OE 0xFD55 | |
601 | #define CARD_AUTO_BLINK 0xFD56 | |
602 | #define CARD_GPIO_DIR 0xFD57 | |
603 | #define CARD_GPIO 0xFD58 | |
604 | #define CARD_DATA_SOURCE 0xFD5B | |
e1237932 | 605 | #define SD30_CLK_DRIVE_SEL 0xFD5A |
67d16a46 WW |
606 | #define CARD_SELECT 0xFD5C |
607 | #define SD30_DRIVE_SEL 0xFD5E | |
e1237932 RT |
608 | #define SD30_CMD_DRIVE_SEL 0xFD5E |
609 | #define SD30_DAT_DRIVE_SEL 0xFD5F | |
67d16a46 WW |
610 | #define CARD_CLK_EN 0xFD69 |
611 | #define SDIO_CTRL 0xFD6B | |
612 | #define CD_PAD_CTL 0xFD73 | |
613 | ||
614 | #define FPDCTL 0xFC00 | |
615 | #define PDINFO 0xFC01 | |
616 | ||
617 | #define CLK_CTL 0xFC02 | |
618 | #define CLK_DIV 0xFC03 | |
619 | #define CLK_SEL 0xFC04 | |
620 | ||
621 | #define SSC_DIV_N_0 0xFC0F | |
622 | #define SSC_DIV_N_1 0xFC10 | |
623 | #define SSC_CTL1 0xFC11 | |
624 | #define SSC_CTL2 0xFC12 | |
625 | ||
626 | #define RCCTL 0xFC14 | |
627 | ||
628 | #define FPGA_PULL_CTL 0xFC1D | |
629 | #define OLT_LED_CTL 0xFC1E | |
630 | #define GPIO_CTL 0xFC1F | |
631 | ||
632 | #define LDO_CTL 0xFC1E | |
633 | #define SYS_VER 0xFC32 | |
634 | ||
635 | #define CARD_PULL_CTL1 0xFD60 | |
636 | #define CARD_PULL_CTL2 0xFD61 | |
637 | #define CARD_PULL_CTL3 0xFD62 | |
638 | #define CARD_PULL_CTL4 0xFD63 | |
639 | #define CARD_PULL_CTL5 0xFD64 | |
640 | #define CARD_PULL_CTL6 0xFD65 | |
641 | ||
642 | /* PCI Express Related Registers */ | |
643 | #define IRQEN0 0xFE20 | |
644 | #define IRQSTAT0 0xFE21 | |
645 | #define IRQEN1 0xFE22 | |
646 | #define IRQSTAT1 0xFE23 | |
647 | #define TLPRIEN 0xFE24 | |
648 | #define TLPRISTAT 0xFE25 | |
649 | #define TLPTIEN 0xFE26 | |
650 | #define TLPTISTAT 0xFE27 | |
651 | #define DMATC0 0xFE28 | |
652 | #define DMATC1 0xFE29 | |
653 | #define DMATC2 0xFE2A | |
654 | #define DMATC3 0xFE2B | |
655 | #define DMACTL 0xFE2C | |
656 | #define BCTL 0xFE2D | |
657 | #define RBBC0 0xFE2E | |
658 | #define RBBC1 0xFE2F | |
659 | #define RBDAT 0xFE30 | |
660 | #define RBCTL 0xFE34 | |
661 | #define CFGADDR0 0xFE35 | |
662 | #define CFGADDR1 0xFE36 | |
663 | #define CFGDATA0 0xFE37 | |
664 | #define CFGDATA1 0xFE38 | |
665 | #define CFGDATA2 0xFE39 | |
666 | #define CFGDATA3 0xFE3A | |
667 | #define CFGRWCTL 0xFE3B | |
668 | #define PHYRWCTL 0xFE3C | |
669 | #define PHYDATA0 0xFE3D | |
670 | #define PHYDATA1 0xFE3E | |
671 | #define PHYADDR 0xFE3F | |
672 | #define MSGRXDATA0 0xFE40 | |
673 | #define MSGRXDATA1 0xFE41 | |
674 | #define MSGRXDATA2 0xFE42 | |
675 | #define MSGRXDATA3 0xFE43 | |
676 | #define MSGTXDATA0 0xFE44 | |
677 | #define MSGTXDATA1 0xFE45 | |
678 | #define MSGTXDATA2 0xFE46 | |
679 | #define MSGTXDATA3 0xFE47 | |
680 | #define MSGTXCTL 0xFE48 | |
681 | #define PETXCFG 0xFE49 | |
e1237932 RT |
682 | #define LTR_CTL 0xFE4A |
683 | #define OBFF_CFG 0xFE4C | |
67d16a46 WW |
684 | |
685 | #define CDRESUMECTL 0xFE52 | |
686 | #define WAKE_SEL_CTL 0xFE54 | |
687 | #define PME_FORCE_CTL 0xFE56 | |
688 | #define ASPM_FORCE_CTL 0xFE57 | |
689 | #define PM_CLK_FORCE_CTL 0xFE58 | |
0ccc0065 | 690 | #define FUNC_FORCE_CTL 0xFE59 |
67d16a46 WW |
691 | #define PERST_GLITCH_WIDTH 0xFE5C |
692 | #define CHANGE_LINK_STATE 0xFE5B | |
693 | #define RESET_LOAD_REG 0xFE5E | |
694 | #define EFUSE_CONTENT 0xFE5F | |
695 | #define HOST_SLEEP_STATE 0xFE60 | |
696 | #define SDIO_CFG 0xFE70 | |
697 | ||
698 | #define NFTS_TX_CTRL 0xFE72 | |
699 | ||
700 | #define PWR_GATE_CTRL 0xFE75 | |
701 | #define PWD_SUSPEND_EN 0xFE76 | |
702 | #define LDO_PWR_SEL 0xFE78 | |
703 | ||
704 | #define DUMMY_REG_RESET_0 0xFE90 | |
705 | ||
773ccdfd WW |
706 | #define AUTOLOAD_CFG_BASE 0xFF00 |
707 | ||
5947c167 WW |
708 | #define PM_CTRL1 0xFF44 |
709 | #define PM_CTRL2 0xFF45 | |
710 | #define PM_CTRL3 0xFF46 | |
5cb5d961 MC |
711 | #define SDIO_SEND_PME_EN 0x80 |
712 | #define FORCE_RC_MODE_ON 0x40 | |
713 | #define FORCE_RX50_LINK_ON 0x20 | |
714 | #define D3_DELINK_MODE_EN 0x10 | |
715 | #define USE_PESRTB_CTL_DELINK 0x08 | |
716 | #define DELAY_PIN_WAKE 0x04 | |
717 | #define RESET_PIN_WAKE 0x02 | |
718 | #define PM_WAKE_EN 0x01 | |
5947c167 WW |
719 | #define PM_CTRL4 0xFF47 |
720 | ||
67d16a46 WW |
721 | /* Memory mapping */ |
722 | #define SRAM_BASE 0xE600 | |
723 | #define RBUF_BASE 0xF400 | |
724 | #define PPBUF_BASE1 0xF800 | |
725 | #define PPBUF_BASE2 0xFA00 | |
726 | #define IMAGE_FLAG_ADDR0 0xCE80 | |
727 | #define IMAGE_FLAG_ADDR1 0xCE81 | |
728 | ||
4c4b8c10 WW |
729 | /* Phy register */ |
730 | #define PHY_PCR 0x00 | |
731 | #define PHY_RCR0 0x01 | |
732 | #define PHY_RCR1 0x02 | |
733 | #define PHY_RCR2 0x03 | |
734 | #define PHY_RTCR 0x04 | |
735 | #define PHY_RDR 0x05 | |
736 | #define PHY_TCR0 0x06 | |
737 | #define PHY_TCR1 0x07 | |
738 | #define PHY_TUNE 0x08 | |
739 | #define PHY_IMR 0x09 | |
740 | #define PHY_BPCR 0x0A | |
741 | #define PHY_BIST 0x0B | |
742 | #define PHY_RAW_L 0x0C | |
743 | #define PHY_RAW_H 0x0D | |
744 | #define PHY_RAW_DATA 0x0E | |
745 | #define PHY_HOST_CLK_CTRL 0x0F | |
746 | #define PHY_DMR 0x10 | |
747 | #define PHY_BACR 0x11 | |
748 | #define PHY_IER 0x12 | |
749 | #define PHY_BCSR 0x13 | |
750 | #define PHY_BPR 0x14 | |
751 | #define PHY_BPNR2 0x15 | |
752 | #define PHY_BPNR 0x16 | |
753 | #define PHY_BRNR2 0x17 | |
754 | #define PHY_BENR 0x18 | |
755 | #define PHY_REG_REV 0x19 | |
756 | #define PHY_FLD0 0x1A | |
757 | #define PHY_FLD1 0x1B | |
758 | #define PHY_FLD2 0x1C | |
759 | #define PHY_FLD3 0x1D | |
760 | #define PHY_FLD4 0x1E | |
761 | #define PHY_DUM_REG 0x1F | |
762 | ||
773ccdfd | 763 | #define LCTLR 0x80 |
5cb5d961 MC |
764 | #define LCTLR_EXT_SYNC 0x80 |
765 | #define LCTLR_COMMON_CLOCK_CFG 0x40 | |
766 | #define LCTLR_RETRAIN_LINK 0x20 | |
767 | #define LCTLR_LINK_DISABLE 0x10 | |
768 | #define LCTLR_RCB 0x08 | |
769 | #define LCTLR_RESERVED 0x04 | |
770 | #define LCTLR_ASPM_CTL_MASK 0x03 | |
771 | ||
773ccdfd WW |
772 | #define PCR_SETTING_REG1 0x724 |
773 | #define PCR_SETTING_REG2 0x814 | |
774 | #define PCR_SETTING_REG3 0x747 | |
775 | ||
26b81851 WW |
776 | /* Phy bits */ |
777 | #define PHY_PCR_FORCE_CODE 0xB000 | |
778 | #define PHY_PCR_OOBS_CALI_50 0x0800 | |
779 | #define PHY_PCR_OOBS_VCM_08 0x0200 | |
780 | #define PHY_PCR_OOBS_SEN_90 0x0040 | |
781 | #define PHY_PCR_RSSI_EN 0x0002 | |
782 | ||
783 | #define PHY_RCR1_ADP_TIME 0x0100 | |
784 | #define PHY_RCR1_VCO_COARSE 0x001F | |
785 | ||
786 | #define PHY_RCR2_EMPHASE_EN 0x8000 | |
787 | #define PHY_RCR2_NADJR 0x4000 | |
788 | #define PHY_RCR2_CDR_CP_10 0x0400 | |
789 | #define PHY_RCR2_CDR_SR_2 0x0100 | |
790 | #define PHY_RCR2_FREQSEL_12 0x0040 | |
791 | #define PHY_RCR2_CPADJEN 0x0020 | |
792 | #define PHY_RCR2_CDR_SC_8 0x0008 | |
793 | #define PHY_RCR2_CALIB_LATE 0x0002 | |
794 | ||
795 | #define PHY_RDR_RXDSEL_1_9 0x4000 | |
796 | ||
797 | #define PHY_TUNE_TUNEREF_1_0 0x4000 | |
798 | #define PHY_TUNE_VBGSEL_1252 0x0C00 | |
799 | #define PHY_TUNE_SDBUS_33 0x0200 | |
800 | #define PHY_TUNE_TUNED18 0x01C0 | |
801 | #define PHY_TUNE_TUNED12 0X0020 | |
802 | ||
803 | #define PHY_BPCR_IBRXSEL 0x0400 | |
804 | #define PHY_BPCR_IBTXSEL 0x0100 | |
805 | #define PHY_BPCR_IB_FILTER 0x0080 | |
806 | #define PHY_BPCR_CMIRROR_EN 0x0040 | |
807 | ||
808 | #define PHY_REG_REV_RESV 0xE000 | |
809 | #define PHY_REG_REV_RXIDLE_LATCHED 0x1000 | |
810 | #define PHY_REG_REV_P1_EN 0x0800 | |
811 | #define PHY_REG_REV_RXIDLE_EN 0x0400 | |
812 | #define PHY_REG_REV_CLKREQ_DLY_TIMER_1_0 0x0040 | |
813 | #define PHY_REG_REV_STOP_CLKRD 0x0020 | |
814 | #define PHY_REG_REV_RX_PWST 0x0008 | |
815 | #define PHY_REG_REV_STOP_CLKWR 0x0004 | |
816 | ||
817 | #define PHY_FLD3_TIMER_4 0x7800 | |
818 | #define PHY_FLD3_TIMER_6 0x00E0 | |
819 | #define PHY_FLD3_RXDELINK 0x0004 | |
820 | ||
821 | #define PHY_FLD4_FLDEN_SEL 0x4000 | |
822 | #define PHY_FLD4_REQ_REF 0x2000 | |
823 | #define PHY_FLD4_RXAMP_OFF 0x1000 | |
824 | #define PHY_FLD4_REQ_ADDA 0x0800 | |
825 | #define PHY_FLD4_BER_COUNT 0x00E0 | |
826 | #define PHY_FLD4_BER_TIMER 0x000A | |
827 | #define PHY_FLD4_BER_CHK_EN 0x0001 | |
828 | ||
67d16a46 WW |
829 | #define rtsx_pci_init_cmd(pcr) ((pcr)->ci = 0) |
830 | ||
831 | struct rtsx_pcr; | |
832 | ||
833 | struct pcr_handle { | |
834 | struct rtsx_pcr *pcr; | |
835 | }; | |
836 | ||
837 | struct pcr_ops { | |
838 | int (*extra_init_hw)(struct rtsx_pcr *pcr); | |
839 | int (*optimize_phy)(struct rtsx_pcr *pcr); | |
840 | int (*turn_on_led)(struct rtsx_pcr *pcr); | |
841 | int (*turn_off_led)(struct rtsx_pcr *pcr); | |
842 | int (*enable_auto_blink)(struct rtsx_pcr *pcr); | |
843 | int (*disable_auto_blink)(struct rtsx_pcr *pcr); | |
844 | int (*card_power_on)(struct rtsx_pcr *pcr, int card); | |
845 | int (*card_power_off)(struct rtsx_pcr *pcr, int card); | |
d817ac4e WW |
846 | int (*switch_output_voltage)(struct rtsx_pcr *pcr, |
847 | u8 voltage); | |
67d16a46 | 848 | unsigned int (*cd_deglitch)(struct rtsx_pcr *pcr); |
ab4e8f8b | 849 | int (*conv_clk_and_div_n)(int clk, int dir); |
773ccdfd | 850 | void (*fetch_vendor_settings)(struct rtsx_pcr *pcr); |
eb891c65 | 851 | void (*force_power_down)(struct rtsx_pcr *pcr, u8 pm_state); |
67d16a46 WW |
852 | }; |
853 | ||
854 | enum PDEV_STAT {PDEV_STAT_IDLE, PDEV_STAT_RUN}; | |
855 | ||
856 | struct rtsx_pcr { | |
857 | struct pci_dev *pci; | |
858 | unsigned int id; | |
859 | ||
860 | /* pci resources */ | |
861 | unsigned long addr; | |
862 | void __iomem *remap_addr; | |
863 | int irq; | |
864 | ||
865 | /* host reserved buffer */ | |
866 | void *rtsx_resv_buf; | |
867 | dma_addr_t rtsx_resv_buf_addr; | |
868 | ||
869 | void *host_cmds_ptr; | |
870 | dma_addr_t host_cmds_addr; | |
871 | int ci; | |
872 | ||
873 | void *host_sg_tbl_ptr; | |
874 | dma_addr_t host_sg_tbl_addr; | |
875 | int sgi; | |
876 | ||
877 | u32 bier; | |
878 | char trans_result; | |
879 | ||
880 | unsigned int card_inserted; | |
881 | unsigned int card_removed; | |
c3481955 | 882 | unsigned int card_exist; |
67d16a46 WW |
883 | |
884 | struct delayed_work carddet_work; | |
885 | struct delayed_work idle_work; | |
886 | ||
887 | spinlock_t lock; | |
888 | struct mutex pcr_mutex; | |
889 | struct completion *done; | |
890 | struct completion *finish_me; | |
891 | ||
892 | unsigned int cur_clock; | |
67d16a46 WW |
893 | bool remove_pci; |
894 | bool msi_en; | |
895 | ||
896 | #define EXTRA_CAPS_SD_SDR50 (1 << 0) | |
897 | #define EXTRA_CAPS_SD_SDR104 (1 << 1) | |
898 | #define EXTRA_CAPS_SD_DDR50 (1 << 2) | |
899 | #define EXTRA_CAPS_MMC_HSDDR (1 << 3) | |
900 | #define EXTRA_CAPS_MMC_HS200 (1 << 4) | |
901 | #define EXTRA_CAPS_MMC_8BIT (1 << 5) | |
902 | u32 extra_caps; | |
903 | ||
904 | #define IC_VER_A 0 | |
905 | #define IC_VER_B 1 | |
906 | #define IC_VER_C 2 | |
907 | #define IC_VER_D 3 | |
908 | u8 ic_version; | |
909 | ||
773ccdfd WW |
910 | u8 sd30_drive_sel_1v8; |
911 | u8 sd30_drive_sel_3v3; | |
912 | u8 card_drive_sel; | |
913 | #define ASPM_L1_EN 0x02 | |
914 | u8 aspm_en; | |
915 | ||
916 | #define PCR_MS_PMOS (1 << 0) | |
917 | #define PCR_REVERSE_SOCKET (1 << 1) | |
918 | u32 flags; | |
919 | ||
84d72f9c WW |
920 | u32 tx_initial_phase; |
921 | u32 rx_initial_phase; | |
922 | ||
67d16a46 WW |
923 | const u32 *sd_pull_ctl_enable_tbl; |
924 | const u32 *sd_pull_ctl_disable_tbl; | |
925 | const u32 *ms_pull_ctl_enable_tbl; | |
926 | const u32 *ms_pull_ctl_disable_tbl; | |
927 | ||
928 | const struct pcr_ops *ops; | |
929 | enum PDEV_STAT state; | |
930 | ||
931 | int num_slots; | |
932 | struct rtsx_slot *slots; | |
933 | }; | |
934 | ||
935 | #define CHK_PCI_PID(pcr, pid) ((pcr)->pci->device == (pid)) | |
936 | #define PCI_VID(pcr) ((pcr)->pci->vendor) | |
937 | #define PCI_PID(pcr) ((pcr)->pci->device) | |
938 | ||
84d72f9c WW |
939 | #define SDR104_PHASE(val) ((val) & 0xFF) |
940 | #define SDR50_PHASE(val) (((val) >> 8) & 0xFF) | |
941 | #define DDR50_PHASE(val) (((val) >> 16) & 0xFF) | |
942 | #define SDR104_TX_PHASE(pcr) SDR104_PHASE((pcr)->tx_initial_phase) | |
943 | #define SDR50_TX_PHASE(pcr) SDR50_PHASE((pcr)->tx_initial_phase) | |
944 | #define DDR50_TX_PHASE(pcr) DDR50_PHASE((pcr)->tx_initial_phase) | |
945 | #define SDR104_RX_PHASE(pcr) SDR104_PHASE((pcr)->rx_initial_phase) | |
946 | #define SDR50_RX_PHASE(pcr) SDR50_PHASE((pcr)->rx_initial_phase) | |
947 | #define DDR50_RX_PHASE(pcr) DDR50_PHASE((pcr)->rx_initial_phase) | |
948 | #define SET_CLOCK_PHASE(sdr104, sdr50, ddr50) \ | |
949 | (((ddr50) << 16) | ((sdr50) << 8) | (sdr104)) | |
950 | ||
67d16a46 WW |
951 | void rtsx_pci_start_run(struct rtsx_pcr *pcr); |
952 | int rtsx_pci_write_register(struct rtsx_pcr *pcr, u16 addr, u8 mask, u8 data); | |
953 | int rtsx_pci_read_register(struct rtsx_pcr *pcr, u16 addr, u8 *data); | |
954 | int rtsx_pci_write_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 val); | |
955 | int rtsx_pci_read_phy_register(struct rtsx_pcr *pcr, u8 addr, u16 *val); | |
956 | void rtsx_pci_stop_cmd(struct rtsx_pcr *pcr); | |
957 | void rtsx_pci_add_cmd(struct rtsx_pcr *pcr, | |
958 | u8 cmd_type, u16 reg_addr, u8 mask, u8 data); | |
959 | void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr *pcr); | |
960 | int rtsx_pci_send_cmd(struct rtsx_pcr *pcr, int timeout); | |
961 | int rtsx_pci_transfer_data(struct rtsx_pcr *pcr, struct scatterlist *sglist, | |
962 | int num_sg, bool read, int timeout); | |
8cd11830 MC |
963 | int rtsx_pci_dma_map_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist, |
964 | int num_sg, bool read); | |
965 | void rtsx_pci_dma_unmap_sg(struct rtsx_pcr *pcr, struct scatterlist *sglist, | |
966 | int num_sg, bool read); | |
967 | int rtsx_pci_dma_transfer(struct rtsx_pcr *pcr, struct scatterlist *sglist, | |
968 | int count, bool read, int timeout); | |
67d16a46 WW |
969 | int rtsx_pci_read_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len); |
970 | int rtsx_pci_write_ppbuf(struct rtsx_pcr *pcr, u8 *buf, int buf_len); | |
971 | int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr *pcr, int card); | |
972 | int rtsx_pci_card_pull_ctl_disable(struct rtsx_pcr *pcr, int card); | |
973 | int rtsx_pci_switch_clock(struct rtsx_pcr *pcr, unsigned int card_clock, | |
974 | u8 ssc_depth, bool initial_mode, bool double_clk, bool vpclk); | |
975 | int rtsx_pci_card_power_on(struct rtsx_pcr *pcr, int card); | |
976 | int rtsx_pci_card_power_off(struct rtsx_pcr *pcr, int card); | |
c3481955 | 977 | int rtsx_pci_card_exclusive_check(struct rtsx_pcr *pcr, int card); |
d817ac4e | 978 | int rtsx_pci_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage); |
67d16a46 WW |
979 | unsigned int rtsx_pci_card_exist(struct rtsx_pcr *pcr); |
980 | void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr *pcr); | |
981 | ||
982 | static inline u8 *rtsx_pci_get_cmd_data(struct rtsx_pcr *pcr) | |
983 | { | |
984 | return (u8 *)(pcr->host_cmds_ptr); | |
985 | } | |
986 | ||
5cb5d961 MC |
987 | static inline int rtsx_pci_update_cfg_byte(struct rtsx_pcr *pcr, int addr, |
988 | u8 mask, u8 append) | |
989 | { | |
990 | int err; | |
991 | u8 val; | |
992 | ||
993 | err = pci_read_config_byte(pcr->pci, addr, &val); | |
994 | if (err < 0) | |
995 | return err; | |
996 | return pci_write_config_byte(pcr->pci, addr, (val & mask) | append); | |
997 | } | |
998 | ||
a3b63979 MC |
999 | static inline void rtsx_pci_write_be32(struct rtsx_pcr *pcr, u16 reg, u32 val) |
1000 | { | |
1001 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg, 0xFF, val >> 24); | |
1002 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg + 1, 0xFF, val >> 16); | |
1003 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg + 2, 0xFF, val >> 8); | |
1004 | rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, reg + 3, 0xFF, val); | |
1005 | } | |
1006 | ||
67d16a46 | 1007 | #endif |