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1f67b599 | 1 | /* SPDX-License-Identifier: GPL-2.0-only */ |
27e34995 RV |
2 | /* |
3 | * Copyright (C) ST-Ericsson SA 2010 | |
4 | * | |
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5 | * Author: Rabin Vincent <rabin.vincent@stericsson.com> for ST-Ericsson |
6 | */ | |
7 | ||
8 | #ifndef __LINUX_MFD_STMPE_H | |
9 | #define __LINUX_MFD_STMPE_H | |
10 | ||
313162d0 PG |
11 | #include <linux/mutex.h> |
12 | ||
063755ab PS |
13 | #define STMPE_SAMPLE_TIME(x) ((x & 0xf) << 4) |
14 | #define STMPE_MOD_12B(x) ((x & 0x1) << 3) | |
15 | #define STMPE_REF_SEL(x) ((x & 0x1) << 1) | |
16 | #define STMPE_ADC_FREQ(x) (x & 0x3) | |
17 | #define STMPE_AVE_CTRL(x) ((x & 0x3) << 6) | |
18 | #define STMPE_DET_DELAY(x) ((x & 0x7) << 3) | |
19 | #define STMPE_SETTLING(x) (x & 0x7) | |
20 | #define STMPE_FRACTION_Z(x) (x & 0x7) | |
21 | #define STMPE_I_DRIVE(x) (x & 0x1) | |
22 | #define STMPE_OP_MODE(x) ((x & 0x7) << 1) | |
23 | ||
6377cfa3 SA |
24 | #define STMPE811_REG_ADC_CTRL1 0x20 |
25 | #define STMPE811_REG_ADC_CTRL2 0x21 | |
26 | ||
313162d0 | 27 | struct device; |
9c9e3214 | 28 | struct regulator; |
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29 | |
30 | enum stmpe_block { | |
31 | STMPE_BLOCK_GPIO = 1 << 0, | |
32 | STMPE_BLOCK_KEYPAD = 1 << 1, | |
33 | STMPE_BLOCK_TOUCHSCREEN = 1 << 2, | |
34 | STMPE_BLOCK_ADC = 1 << 3, | |
35 | STMPE_BLOCK_PWM = 1 << 4, | |
36 | STMPE_BLOCK_ROTATOR = 1 << 5, | |
37 | }; | |
38 | ||
39 | enum stmpe_partnum { | |
1cda2394 | 40 | STMPE610, |
7f7f4ea1 | 41 | STMPE801, |
27e34995 | 42 | STMPE811, |
6bb9f0d9 | 43 | STMPE1600, |
27e34995 | 44 | STMPE1601, |
230f13a5 | 45 | STMPE1801, |
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46 | STMPE2401, |
47 | STMPE2403, | |
e31f9b82 | 48 | STMPE_NBR_PARTS |
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49 | }; |
50 | ||
51 | /* | |
52 | * For registers whose locations differ on variants, the correct address is | |
53 | * obtained by indexing stmpe->regs with one of the following. | |
54 | */ | |
55 | enum { | |
56 | STMPE_IDX_CHIP_ID, | |
0f4be8cf PC |
57 | STMPE_IDX_SYS_CTRL, |
58 | STMPE_IDX_SYS_CTRL2, | |
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59 | STMPE_IDX_ICR_LSB, |
60 | STMPE_IDX_IER_LSB, | |
897ac667 | 61 | STMPE_IDX_IER_MSB, |
230f13a5 | 62 | STMPE_IDX_ISR_LSB, |
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63 | STMPE_IDX_ISR_MSB, |
64 | STMPE_IDX_GPMR_LSB, | |
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65 | STMPE_IDX_GPMR_CSB, |
66 | STMPE_IDX_GPMR_MSB, | |
27e34995 | 67 | STMPE_IDX_GPSR_LSB, |
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68 | STMPE_IDX_GPSR_CSB, |
69 | STMPE_IDX_GPSR_MSB, | |
27e34995 | 70 | STMPE_IDX_GPCR_LSB, |
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71 | STMPE_IDX_GPCR_CSB, |
72 | STMPE_IDX_GPCR_MSB, | |
27e34995 | 73 | STMPE_IDX_GPDR_LSB, |
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74 | STMPE_IDX_GPDR_CSB, |
75 | STMPE_IDX_GPDR_MSB, | |
76 | STMPE_IDX_GPEDR_LSB, | |
77 | STMPE_IDX_GPEDR_CSB, | |
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78 | STMPE_IDX_GPEDR_MSB, |
79 | STMPE_IDX_GPRER_LSB, | |
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80 | STMPE_IDX_GPRER_CSB, |
81 | STMPE_IDX_GPRER_MSB, | |
27e34995 | 82 | STMPE_IDX_GPFER_LSB, |
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83 | STMPE_IDX_GPFER_CSB, |
84 | STMPE_IDX_GPFER_MSB, | |
80e1dd82 LW |
85 | STMPE_IDX_GPPUR_LSB, |
86 | STMPE_IDX_GPPDR_LSB, | |
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87 | STMPE_IDX_GPAFR_U_MSB, |
88 | STMPE_IDX_IEGPIOR_LSB, | |
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89 | STMPE_IDX_IEGPIOR_CSB, |
90 | STMPE_IDX_IEGPIOR_MSB, | |
230f13a5 | 91 | STMPE_IDX_ISGPIOR_LSB, |
897ac667 | 92 | STMPE_IDX_ISGPIOR_CSB, |
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93 | STMPE_IDX_ISGPIOR_MSB, |
94 | STMPE_IDX_MAX, | |
95 | }; | |
96 | ||
97 | ||
98 | struct stmpe_variant_info; | |
1a6e4b74 | 99 | struct stmpe_client_info; |
fc1882dc | 100 | struct stmpe_platform_data; |
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101 | |
102 | /** | |
103 | * struct stmpe - STMPE MFD structure | |
9c9e3214 LW |
104 | * @vcc: optional VCC regulator |
105 | * @vio: optional VIO regulator | |
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106 | * @lock: lock protecting I/O operations |
107 | * @irq_lock: IRQ bus lock | |
108 | * @dev: device, mostly for dev_dbg() | |
76f93992 | 109 | * @irq_domain: IRQ domain |
1a6e4b74 VK |
110 | * @client: client - i2c or spi |
111 | * @ci: client specific information | |
4dcaa6b6 | 112 | * @partnum: part number |
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113 | * @variant: the detected STMPE model number |
114 | * @regs: list of addresses of registers which are at different addresses on | |
115 | * different variants. Indexed by one of STMPE_IDX_*. | |
73de16db | 116 | * @irq: irq number for stmpe |
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117 | * @num_gpios: number of gpios, differs for variants |
118 | * @ier: cache of IER registers for bus_lock | |
119 | * @oldier: cache of IER registers for bus_lock | |
120 | * @pdata: platform data | |
121 | */ | |
122 | struct stmpe { | |
9c9e3214 LW |
123 | struct regulator *vcc; |
124 | struct regulator *vio; | |
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125 | struct mutex lock; |
126 | struct mutex irq_lock; | |
127 | struct device *dev; | |
76f93992 | 128 | struct irq_domain *domain; |
1a6e4b74 VK |
129 | void *client; |
130 | struct stmpe_client_info *ci; | |
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131 | enum stmpe_partnum partnum; |
132 | struct stmpe_variant_info *variant; | |
133 | const u8 *regs; | |
134 | ||
73de16db | 135 | int irq; |
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136 | int num_gpios; |
137 | u8 ier[2]; | |
138 | u8 oldier[2]; | |
139 | struct stmpe_platform_data *pdata; | |
6377cfa3 SA |
140 | |
141 | /* For devices that use an ADC */ | |
142 | u8 sample_time; | |
143 | u8 mod_12b; | |
144 | u8 ref_sel; | |
145 | u8 adc_freq; | |
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146 | }; |
147 | ||
148 | extern int stmpe_reg_write(struct stmpe *stmpe, u8 reg, u8 data); | |
149 | extern int stmpe_reg_read(struct stmpe *stmpe, u8 reg); | |
150 | extern int stmpe_block_read(struct stmpe *stmpe, u8 reg, u8 length, | |
151 | u8 *values); | |
152 | extern int stmpe_block_write(struct stmpe *stmpe, u8 reg, u8 length, | |
153 | const u8 *values); | |
154 | extern int stmpe_set_bits(struct stmpe *stmpe, u8 reg, u8 mask, u8 val); | |
155 | extern int stmpe_set_altfunc(struct stmpe *stmpe, u32 pins, | |
156 | enum stmpe_block block); | |
157 | extern int stmpe_enable(struct stmpe *stmpe, unsigned int blocks); | |
158 | extern int stmpe_disable(struct stmpe *stmpe, unsigned int blocks); | |
6377cfa3 | 159 | extern int stmpe811_adc_common_init(struct stmpe *stmpe); |
27e34995 | 160 | |
b8e9cf0b WS |
161 | #define STMPE_GPIO_NOREQ_811_TOUCH (0xf0) |
162 | ||
27e34995 | 163 | #endif |