[mirror_ubuntu-artful-kernel.git] / include / linux / mfd / ti_am335x_tscadc.h

#ifndef __LINUX_TI_AM335X_TSCADC_MFD_H
#define __LINUX_TI_AM335X_TSCADC_MFD_H

/*
 * TI Touch Screen / ADC MFD driver
 *
 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation version 2.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/mfd/core.h>

#define REG_RAWIRQSTATUS	0x024
#define REG_IRQSTATUS		0x028
#define REG_IRQENABLE		0x02C
#define REG_IRQCLR		0x030
#define REG_IRQWAKEUP		0x034
#define REG_CTRL		0x040
#define REG_ADCFSM		0x044
#define REG_CLKDIV		0x04C
#define REG_SE			0x054
#define REG_IDLECONFIG		0x058
#define REG_CHARGECONFIG	0x05C
#define REG_CHARGEDELAY		0x060
#define REG_STEPCONFIG(n)	(0x64 + ((n) * 8))
#define REG_STEPDELAY(n)	(0x68 + ((n) * 8))
#define REG_FIFO0CNT		0xE4
#define REG_FIFO0THR		0xE8
#define REG_FIFO1CNT		0xF0
#define REG_FIFO1THR		0xF4
#define REG_FIFO0		0x100
#define REG_FIFO1		0x200

/*	Register Bitfields	*/
/* IRQ wakeup enable */
#define IRQWKUP_ENB		BIT(0)

/* Step Enable */
#define STEPENB_MASK		(0x1FFFF << 0)
#define STEPENB(val)		((val) << 0)
#define ENB(val)			(1 << (val))
#define STPENB_STEPENB		STEPENB(0x1FFFF)
#define STPENB_STEPENB_TC	STEPENB(0x1FFF)

/* IRQ enable */
#define IRQENB_HW_PEN		BIT(0)
#define IRQENB_EOS		BIT(1)
#define IRQENB_FIFO0THRES	BIT(2)
#define IRQENB_FIFO0OVRRUN	BIT(3)
#define IRQENB_FIFO0UNDRFLW	BIT(4)
#define IRQENB_FIFO1THRES	BIT(5)
#define IRQENB_FIFO1OVRRUN	BIT(6)
#define IRQENB_FIFO1UNDRFLW	BIT(7)
#define IRQENB_PENUP		BIT(9)

/* Step Configuration */
#define STEPCONFIG_MODE_MASK	(3 << 0)
#define STEPCONFIG_MODE(val)	((val) << 0)
#define STEPCONFIG_MODE_SWCNT	STEPCONFIG_MODE(1)
#define STEPCONFIG_MODE_HWSYNC	STEPCONFIG_MODE(2)
#define STEPCONFIG_AVG_MASK	(7 << 2)
#define STEPCONFIG_AVG(val)	((val) << 2)
#define STEPCONFIG_AVG_16	STEPCONFIG_AVG(4)
#define STEPCONFIG_XPP		BIT(5)
#define STEPCONFIG_XNN		BIT(6)
#define STEPCONFIG_YPP		BIT(7)
#define STEPCONFIG_YNN		BIT(8)
#define STEPCONFIG_XNP		BIT(9)
#define STEPCONFIG_YPN		BIT(10)
#define STEPCONFIG_INM_MASK	(0xF << 15)
#define STEPCONFIG_INM(val)	((val) << 15)
#define STEPCONFIG_INM_ADCREFM	STEPCONFIG_INM(8)
#define STEPCONFIG_INP_MASK	(0xF << 19)
#define STEPCONFIG_INP(val)	((val) << 19)
#define STEPCONFIG_INP_AN4	STEPCONFIG_INP(4)
#define STEPCONFIG_INP_ADCREFM	STEPCONFIG_INP(8)
#define STEPCONFIG_FIFO1	BIT(26)

/* Delay register */
#define STEPDELAY_OPEN_MASK	(0x3FFFF << 0)
#define STEPDELAY_OPEN(val)	((val) << 0)
#define STEPCONFIG_OPENDLY	STEPDELAY_OPEN(0x098)
#define STEPDELAY_SAMPLE_MASK	(0xFF << 24)
#define STEPDELAY_SAMPLE(val)	((val) << 24)
#define STEPCONFIG_SAMPLEDLY	STEPDELAY_SAMPLE(0)

/* Charge Config */
#define STEPCHARGE_RFP_MASK	(7 << 12)
#define STEPCHARGE_RFP(val)	((val) << 12)
#define STEPCHARGE_RFP_XPUL	STEPCHARGE_RFP(1)
#define STEPCHARGE_INM_MASK	(0xF << 15)
#define STEPCHARGE_INM(val)	((val) << 15)
#define STEPCHARGE_INM_AN1	STEPCHARGE_INM(1)
#define STEPCHARGE_INP_MASK	(0xF << 19)
#define STEPCHARGE_INP(val)	((val) << 19)
#define STEPCHARGE_RFM_MASK	(3 << 23)
#define STEPCHARGE_RFM(val)	((val) << 23)
#define STEPCHARGE_RFM_XNUR	STEPCHARGE_RFM(1)

/* Charge delay */
#define CHARGEDLY_OPEN_MASK	(0x3FFFF << 0)
#define CHARGEDLY_OPEN(val)	((val) << 0)
#define CHARGEDLY_OPENDLY	CHARGEDLY_OPEN(0x400)

/* Control register */
#define CNTRLREG_TSCSSENB	BIT(0)
#define CNTRLREG_STEPID		BIT(1)
#define CNTRLREG_STEPCONFIGWRT	BIT(2)
#define CNTRLREG_POWERDOWN	BIT(4)
#define CNTRLREG_AFE_CTRL_MASK	(3 << 5)
#define CNTRLREG_AFE_CTRL(val)	((val) << 5)
#define CNTRLREG_4WIRE		CNTRLREG_AFE_CTRL(1)
#define CNTRLREG_5WIRE		CNTRLREG_AFE_CTRL(2)
#define CNTRLREG_8WIRE		CNTRLREG_AFE_CTRL(3)
#define CNTRLREG_TSCENB		BIT(7)

/* FIFO READ Register */
#define FIFOREAD_DATA_MASK (0xfff << 0)
#define FIFOREAD_CHNLID_MASK (0xf << 16)

/* Sequencer Status */
#define SEQ_STATUS BIT(5)

#define ADC_CLK			3000000
#define TOTAL_STEPS		16
#define TOTAL_CHANNELS		8
#define FIFO1_THRESHOLD		19

/*
 * time in us for processing a single channel, calculated as follows:
 *
 * num cycles = open delay + (sample delay + conv time) * averaging
 *
 * num cycles: 152 + (1 + 13) * 16 = 376
 *
 * clock frequency: 26MHz / 8 = 3.25MHz
 * clock period: 1 / 3.25MHz = 308ns
 *
 * processing time: 376 * 308ns = 116us
 */
#define IDLE_TIMEOUT 116 /* microsec */

#define TSCADC_CELLS		2

struct ti_tscadc_dev {
	struct device *dev;
	struct regmap *regmap_tscadc;
	void __iomem *tscadc_base;
	int irq;
	int used_cells;	/* 1-2 */
	int tsc_wires;
	int tsc_cell;	/* -1 if not used */
	int adc_cell;	/* -1 if not used */
	struct mfd_cell cells[TSCADC_CELLS];
	u32 reg_se_cache;
	bool adc_waiting;
	bool adc_in_use;
	wait_queue_head_t reg_se_wait;
	spinlock_t reg_lock;
	unsigned int clk_div;

	/* tsc device */
	struct titsc *tsc;

	/* adc device */
	struct adc_device *adc;
};

static inline struct ti_tscadc_dev *ti_tscadc_dev_get(struct platform_device *p)
{
	struct ti_tscadc_dev **tscadc_dev = p->dev.platform_data;

	return *tscadc_dev;
}

void am335x_tsc_se_set_cache(struct ti_tscadc_dev *tsadc, u32 val);
void am335x_tsc_se_set_once(struct ti_tscadc_dev *tsadc, u32 val);
void am335x_tsc_se_clr(struct ti_tscadc_dev *tsadc, u32 val);
void am335x_tsc_se_adc_done(struct ti_tscadc_dev *tsadc);

#endif
Commit	Line	Data
01636eb9 PR	1	#ifndef __LINUX_TI_AM335X_TSCADC_MFD_H
	2	#define __LINUX_TI_AM335X_TSCADC_MFD_H
	3
	4	/*
	5	* TI Touch Screen / ADC MFD driver
	6	*
	7	* Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation version 2.
	12	*
	13	* This program is distributed "as is" WITHOUT ANY WARRANTY of any
	14	* kind, whether express or implied; without even the implied warranty
	15	* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*/
	18
	19	#include <linux/mfd/core.h>
	20
	21	#define REG_RAWIRQSTATUS 0x024
	22	#define REG_IRQSTATUS 0x028
	23	#define REG_IRQENABLE 0x02C
	24	#define REG_IRQCLR 0x030
	25	#define REG_IRQWAKEUP 0x034
	26	#define REG_CTRL 0x040
	27	#define REG_ADCFSM 0x044
	28	#define REG_CLKDIV 0x04C
	29	#define REG_SE 0x054
	30	#define REG_IDLECONFIG 0x058
	31	#define REG_CHARGECONFIG 0x05C
	32	#define REG_CHARGEDELAY 0x060
8c896308 SAS	33	#define REG_STEPCONFIG(n) (0x64 + ((n) * 8))
8c896308 SAS	34	#define REG_STEPDELAY(n) (0x68 + ((n) * 8))
01636eb9 PR	35	#define REG_FIFO0CNT 0xE4
	36	#define REG_FIFO0THR 0xE8
	37	#define REG_FIFO1CNT 0xF0
	38	#define REG_FIFO1THR 0xF4
	39	#define REG_FIFO0 0x100
	40	#define REG_FIFO1 0x200
	41
	42	/* Register Bitfields */
	43	/* IRQ wakeup enable */
	44	#define IRQWKUP_ENB BIT(0)
	45
	46	/* Step Enable */
	47	#define STEPENB_MASK (0x1FFFF << 0)
	48	#define STEPENB(val) ((val) << 0)
ca9a5638 ZL	49	#define ENB(val) (1 << (val))
	50	#define STPENB_STEPENB STEPENB(0x1FFFF)
	51	#define STPENB_STEPENB_TC STEPENB(0x1FFF)
01636eb9 PR	52
	53	/* IRQ enable */
	54	#define IRQENB_HW_PEN BIT(0)
344d635b	55	#define IRQENB_EOS BIT(1)
01636eb9	56	#define IRQENB_FIFO0THRES BIT(2)
ca9a5638 ZL	57	#define IRQENB_FIFO0OVRRUN BIT(3)
ca9a5638 ZL	58	#define IRQENB_FIFO0UNDRFLW BIT(4)
01636eb9	59	#define IRQENB_FIFO1THRES BIT(5)
ca9a5638 ZL	60	#define IRQENB_FIFO1OVRRUN BIT(6)
ca9a5638 ZL	61	#define IRQENB_FIFO1UNDRFLW BIT(7)
01636eb9 PR	62	#define IRQENB_PENUP BIT(9)
	63
	64	/* Step Configuration */
	65	#define STEPCONFIG_MODE_MASK (3 << 0)
	66	#define STEPCONFIG_MODE(val) ((val) << 0)
ca9a5638	67	#define STEPCONFIG_MODE_SWCNT STEPCONFIG_MODE(1)
01636eb9 PR	68	#define STEPCONFIG_MODE_HWSYNC STEPCONFIG_MODE(2)
	69	#define STEPCONFIG_AVG_MASK (7 << 2)
	70	#define STEPCONFIG_AVG(val) ((val) << 2)
	71	#define STEPCONFIG_AVG_16 STEPCONFIG_AVG(4)
	72	#define STEPCONFIG_XPP BIT(5)
	73	#define STEPCONFIG_XNN BIT(6)
	74	#define STEPCONFIG_YPP BIT(7)
	75	#define STEPCONFIG_YNN BIT(8)
	76	#define STEPCONFIG_XNP BIT(9)
	77	#define STEPCONFIG_YPN BIT(10)
	78	#define STEPCONFIG_INM_MASK (0xF << 15)
	79	#define STEPCONFIG_INM(val) ((val) << 15)
	80	#define STEPCONFIG_INM_ADCREFM STEPCONFIG_INM(8)
	81	#define STEPCONFIG_INP_MASK (0xF << 19)
	82	#define STEPCONFIG_INP(val) ((val) << 19)
01636eb9 PR	83	#define STEPCONFIG_INP_AN4 STEPCONFIG_INP(4)
	84	#define STEPCONFIG_INP_ADCREFM STEPCONFIG_INP(8)
	85	#define STEPCONFIG_FIFO1 BIT(26)
	86
	87	/* Delay register */
	88	#define STEPDELAY_OPEN_MASK (0x3FFFF << 0)
	89	#define STEPDELAY_OPEN(val) ((val) << 0)
	90	#define STEPCONFIG_OPENDLY STEPDELAY_OPEN(0x098)
	91	#define STEPDELAY_SAMPLE_MASK (0xFF << 24)
	92	#define STEPDELAY_SAMPLE(val) ((val) << 24)
	93	#define STEPCONFIG_SAMPLEDLY STEPDELAY_SAMPLE(0)
	94
	95	/* Charge Config */
	96	#define STEPCHARGE_RFP_MASK (7 << 12)
	97	#define STEPCHARGE_RFP(val) ((val) << 12)
	98	#define STEPCHARGE_RFP_XPUL STEPCHARGE_RFP(1)
	99	#define STEPCHARGE_INM_MASK (0xF << 15)
	100	#define STEPCHARGE_INM(val) ((val) << 15)
	101	#define STEPCHARGE_INM_AN1 STEPCHARGE_INM(1)
	102	#define STEPCHARGE_INP_MASK (0xF << 19)
	103	#define STEPCHARGE_INP(val) ((val) << 19)
01636eb9 PR	104	#define STEPCHARGE_RFM_MASK (3 << 23)
	105	#define STEPCHARGE_RFM(val) ((val) << 23)
	106	#define STEPCHARGE_RFM_XNUR STEPCHARGE_RFM(1)
	107
	108	/* Charge delay */
	109	#define CHARGEDLY_OPEN_MASK (0x3FFFF << 0)
	110	#define CHARGEDLY_OPEN(val) ((val) << 0)
344d635b	111	#define CHARGEDLY_OPENDLY CHARGEDLY_OPEN(0x400)
01636eb9 PR	112
	113	/* Control register */
	114	#define CNTRLREG_TSCSSENB BIT(0)
	115	#define CNTRLREG_STEPID BIT(1)
	116	#define CNTRLREG_STEPCONFIGWRT BIT(2)
	117	#define CNTRLREG_POWERDOWN BIT(4)
	118	#define CNTRLREG_AFE_CTRL_MASK (3 << 5)
	119	#define CNTRLREG_AFE_CTRL(val) ((val) << 5)
	120	#define CNTRLREG_4WIRE CNTRLREG_AFE_CTRL(1)
	121	#define CNTRLREG_5WIRE CNTRLREG_AFE_CTRL(2)
	122	#define CNTRLREG_8WIRE CNTRLREG_AFE_CTRL(3)
	123	#define CNTRLREG_TSCENB BIT(7)
	124
b1451e54 PR	125	/* FIFO READ Register */
	126	#define FIFOREAD_DATA_MASK (0xfff << 0)
	127	#define FIFOREAD_CHNLID_MASK (0xf << 16)
	128
	129	/* Sequencer Status */
	130	#define SEQ_STATUS BIT(5)
	131
01636eb9	132	#define ADC_CLK 3000000
5e53a69b PR	133	#define TOTAL_STEPS 16
5e53a69b PR	134	#define TOTAL_CHANNELS 8
ca9a5638	135	#define FIFO1_THRESHOLD 19
01636eb9	136
b1451e54	137	/*
1a54b7da MK	138	* time in us for processing a single channel, calculated as follows:
	139	*
	140	* num cycles = open delay + (sample delay + conv time) * averaging
	141	*
	142	* num cycles: 152 + (1 + 13) * 16 = 376
	143	*
	144	* clock frequency: 26MHz / 8 = 3.25MHz
	145	* clock period: 1 / 3.25MHz = 308ns
	146	*
	147	* processing time: 376 * 308ns = 116us
	148	*/
	149	#define IDLE_TIMEOUT 116 /* microsec */
b1451e54	150
5e53a69b	151	#define TSCADC_CELLS 2
2b99bafa	152
01636eb9 PR	153	struct ti_tscadc_dev {
	154	struct device *dev;
	155	struct regmap *regmap_tscadc;
	156	void __iomem *tscadc_base;
	157	int irq;
24d5c82f	158	int used_cells; /* 1-2 */
f0933a60	159	int tsc_wires;
24d5c82f PA	160	int tsc_cell; /* -1 if not used */
24d5c82f PA	161	int adc_cell; /* -1 if not used */
01636eb9	162	struct mfd_cell cells[TSCADC_CELLS];
abeccee4	163	u32 reg_se_cache;
7ca6740c SAS	164	bool adc_waiting;
	165	bool adc_in_use;
	166	wait_queue_head_t reg_se_wait;
abeccee4	167	spinlock_t reg_lock;
e90f8754	168	unsigned int clk_div;
2b99bafa PR	169
	170	/* tsc device */
	171	struct titsc *tsc;
5e53a69b PR	172
	173	/* adc device */
	174	struct adc_device *adc;
01636eb9 PR	175	};
01636eb9 PR	176
a9bce1b0 SAS	177	static inline struct ti_tscadc_dev ti_tscadc_dev_get(struct platform_device p)
	178	{
	179	struct ti_tscadc_dev **tscadc_dev = p->dev.platform_data;
	180
	181	return *tscadc_dev;
	182	}
	183
7e170c6e SAS	184	void am335x_tsc_se_set_cache(struct ti_tscadc_dev *tsadc, u32 val);
7e170c6e SAS	185	void am335x_tsc_se_set_once(struct ti_tscadc_dev *tsadc, u32 val);
abeccee4	186	void am335x_tsc_se_clr(struct ti_tscadc_dev *tsadc, u32 val);
7ca6740c	187	void am335x_tsc_se_adc_done(struct ti_tscadc_dev *tsadc);
abeccee4	188
01636eb9	189	#endif