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01636eb9 PR |
1 | #ifndef __LINUX_TI_AM335X_TSCADC_MFD_H |
2 | #define __LINUX_TI_AM335X_TSCADC_MFD_H | |
3 | ||
4 | /* | |
5 | * TI Touch Screen / ADC MFD driver | |
6 | * | |
7 | * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation version 2. | |
12 | * | |
13 | * This program is distributed "as is" WITHOUT ANY WARRANTY of any | |
14 | * kind, whether express or implied; without even the implied warranty | |
15 | * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | */ | |
18 | ||
19 | #include <linux/mfd/core.h> | |
20 | ||
21 | #define REG_RAWIRQSTATUS 0x024 | |
22 | #define REG_IRQSTATUS 0x028 | |
23 | #define REG_IRQENABLE 0x02C | |
24 | #define REG_IRQCLR 0x030 | |
25 | #define REG_IRQWAKEUP 0x034 | |
26 | #define REG_CTRL 0x040 | |
27 | #define REG_ADCFSM 0x044 | |
28 | #define REG_CLKDIV 0x04C | |
29 | #define REG_SE 0x054 | |
30 | #define REG_IDLECONFIG 0x058 | |
31 | #define REG_CHARGECONFIG 0x05C | |
32 | #define REG_CHARGEDELAY 0x060 | |
8c896308 SAS |
33 | #define REG_STEPCONFIG(n) (0x64 + ((n) * 8)) |
34 | #define REG_STEPDELAY(n) (0x68 + ((n) * 8)) | |
01636eb9 PR |
35 | #define REG_FIFO0CNT 0xE4 |
36 | #define REG_FIFO0THR 0xE8 | |
37 | #define REG_FIFO1CNT 0xF0 | |
38 | #define REG_FIFO1THR 0xF4 | |
39 | #define REG_FIFO0 0x100 | |
40 | #define REG_FIFO1 0x200 | |
41 | ||
42 | /* Register Bitfields */ | |
43 | /* IRQ wakeup enable */ | |
44 | #define IRQWKUP_ENB BIT(0) | |
45 | ||
46 | /* Step Enable */ | |
47 | #define STEPENB_MASK (0x1FFFF << 0) | |
48 | #define STEPENB(val) ((val) << 0) | |
ca9a5638 ZL |
49 | #define ENB(val) (1 << (val)) |
50 | #define STPENB_STEPENB STEPENB(0x1FFFF) | |
51 | #define STPENB_STEPENB_TC STEPENB(0x1FFF) | |
01636eb9 PR |
52 | |
53 | /* IRQ enable */ | |
54 | #define IRQENB_HW_PEN BIT(0) | |
55 | #define IRQENB_FIFO0THRES BIT(2) | |
ca9a5638 ZL |
56 | #define IRQENB_FIFO0OVRRUN BIT(3) |
57 | #define IRQENB_FIFO0UNDRFLW BIT(4) | |
01636eb9 | 58 | #define IRQENB_FIFO1THRES BIT(5) |
ca9a5638 ZL |
59 | #define IRQENB_FIFO1OVRRUN BIT(6) |
60 | #define IRQENB_FIFO1UNDRFLW BIT(7) | |
01636eb9 PR |
61 | #define IRQENB_PENUP BIT(9) |
62 | ||
63 | /* Step Configuration */ | |
64 | #define STEPCONFIG_MODE_MASK (3 << 0) | |
65 | #define STEPCONFIG_MODE(val) ((val) << 0) | |
ca9a5638 | 66 | #define STEPCONFIG_MODE_SWCNT STEPCONFIG_MODE(1) |
01636eb9 PR |
67 | #define STEPCONFIG_MODE_HWSYNC STEPCONFIG_MODE(2) |
68 | #define STEPCONFIG_AVG_MASK (7 << 2) | |
69 | #define STEPCONFIG_AVG(val) ((val) << 2) | |
70 | #define STEPCONFIG_AVG_16 STEPCONFIG_AVG(4) | |
71 | #define STEPCONFIG_XPP BIT(5) | |
72 | #define STEPCONFIG_XNN BIT(6) | |
73 | #define STEPCONFIG_YPP BIT(7) | |
74 | #define STEPCONFIG_YNN BIT(8) | |
75 | #define STEPCONFIG_XNP BIT(9) | |
76 | #define STEPCONFIG_YPN BIT(10) | |
77 | #define STEPCONFIG_INM_MASK (0xF << 15) | |
78 | #define STEPCONFIG_INM(val) ((val) << 15) | |
79 | #define STEPCONFIG_INM_ADCREFM STEPCONFIG_INM(8) | |
80 | #define STEPCONFIG_INP_MASK (0xF << 19) | |
81 | #define STEPCONFIG_INP(val) ((val) << 19) | |
01636eb9 PR |
82 | #define STEPCONFIG_INP_AN4 STEPCONFIG_INP(4) |
83 | #define STEPCONFIG_INP_ADCREFM STEPCONFIG_INP(8) | |
84 | #define STEPCONFIG_FIFO1 BIT(26) | |
85 | ||
86 | /* Delay register */ | |
87 | #define STEPDELAY_OPEN_MASK (0x3FFFF << 0) | |
88 | #define STEPDELAY_OPEN(val) ((val) << 0) | |
89 | #define STEPCONFIG_OPENDLY STEPDELAY_OPEN(0x098) | |
90 | #define STEPDELAY_SAMPLE_MASK (0xFF << 24) | |
91 | #define STEPDELAY_SAMPLE(val) ((val) << 24) | |
92 | #define STEPCONFIG_SAMPLEDLY STEPDELAY_SAMPLE(0) | |
93 | ||
94 | /* Charge Config */ | |
95 | #define STEPCHARGE_RFP_MASK (7 << 12) | |
96 | #define STEPCHARGE_RFP(val) ((val) << 12) | |
97 | #define STEPCHARGE_RFP_XPUL STEPCHARGE_RFP(1) | |
98 | #define STEPCHARGE_INM_MASK (0xF << 15) | |
99 | #define STEPCHARGE_INM(val) ((val) << 15) | |
100 | #define STEPCHARGE_INM_AN1 STEPCHARGE_INM(1) | |
101 | #define STEPCHARGE_INP_MASK (0xF << 19) | |
102 | #define STEPCHARGE_INP(val) ((val) << 19) | |
01636eb9 PR |
103 | #define STEPCHARGE_RFM_MASK (3 << 23) |
104 | #define STEPCHARGE_RFM(val) ((val) << 23) | |
105 | #define STEPCHARGE_RFM_XNUR STEPCHARGE_RFM(1) | |
106 | ||
107 | /* Charge delay */ | |
108 | #define CHARGEDLY_OPEN_MASK (0x3FFFF << 0) | |
109 | #define CHARGEDLY_OPEN(val) ((val) << 0) | |
110 | #define CHARGEDLY_OPENDLY CHARGEDLY_OPEN(1) | |
111 | ||
112 | /* Control register */ | |
113 | #define CNTRLREG_TSCSSENB BIT(0) | |
114 | #define CNTRLREG_STEPID BIT(1) | |
115 | #define CNTRLREG_STEPCONFIGWRT BIT(2) | |
116 | #define CNTRLREG_POWERDOWN BIT(4) | |
117 | #define CNTRLREG_AFE_CTRL_MASK (3 << 5) | |
118 | #define CNTRLREG_AFE_CTRL(val) ((val) << 5) | |
119 | #define CNTRLREG_4WIRE CNTRLREG_AFE_CTRL(1) | |
120 | #define CNTRLREG_5WIRE CNTRLREG_AFE_CTRL(2) | |
121 | #define CNTRLREG_8WIRE CNTRLREG_AFE_CTRL(3) | |
122 | #define CNTRLREG_TSCENB BIT(7) | |
123 | ||
b1451e54 PR |
124 | /* FIFO READ Register */ |
125 | #define FIFOREAD_DATA_MASK (0xfff << 0) | |
126 | #define FIFOREAD_CHNLID_MASK (0xf << 16) | |
127 | ||
128 | /* Sequencer Status */ | |
129 | #define SEQ_STATUS BIT(5) | |
130 | ||
01636eb9 | 131 | #define ADC_CLK 3000000 |
5e53a69b PR |
132 | #define TOTAL_STEPS 16 |
133 | #define TOTAL_CHANNELS 8 | |
ca9a5638 | 134 | #define FIFO1_THRESHOLD 19 |
01636eb9 | 135 | |
b1451e54 | 136 | /* |
1a54b7da MK |
137 | * time in us for processing a single channel, calculated as follows: |
138 | * | |
139 | * num cycles = open delay + (sample delay + conv time) * averaging | |
140 | * | |
141 | * num cycles: 152 + (1 + 13) * 16 = 376 | |
142 | * | |
143 | * clock frequency: 26MHz / 8 = 3.25MHz | |
144 | * clock period: 1 / 3.25MHz = 308ns | |
145 | * | |
146 | * processing time: 376 * 308ns = 116us | |
147 | */ | |
148 | #define IDLE_TIMEOUT 116 /* microsec */ | |
b1451e54 | 149 | |
5e53a69b | 150 | #define TSCADC_CELLS 2 |
2b99bafa | 151 | |
01636eb9 PR |
152 | struct ti_tscadc_dev { |
153 | struct device *dev; | |
154 | struct regmap *regmap_tscadc; | |
155 | void __iomem *tscadc_base; | |
156 | int irq; | |
24d5c82f PA |
157 | int used_cells; /* 1-2 */ |
158 | int tsc_cell; /* -1 if not used */ | |
159 | int adc_cell; /* -1 if not used */ | |
01636eb9 | 160 | struct mfd_cell cells[TSCADC_CELLS]; |
abeccee4 | 161 | u32 reg_se_cache; |
7ca6740c SAS |
162 | bool adc_waiting; |
163 | bool adc_in_use; | |
164 | wait_queue_head_t reg_se_wait; | |
abeccee4 | 165 | spinlock_t reg_lock; |
e90f8754 | 166 | unsigned int clk_div; |
2b99bafa PR |
167 | |
168 | /* tsc device */ | |
169 | struct titsc *tsc; | |
5e53a69b PR |
170 | |
171 | /* adc device */ | |
172 | struct adc_device *adc; | |
01636eb9 PR |
173 | }; |
174 | ||
a9bce1b0 SAS |
175 | static inline struct ti_tscadc_dev *ti_tscadc_dev_get(struct platform_device *p) |
176 | { | |
177 | struct ti_tscadc_dev **tscadc_dev = p->dev.platform_data; | |
178 | ||
179 | return *tscadc_dev; | |
180 | } | |
181 | ||
7e170c6e SAS |
182 | void am335x_tsc_se_set_cache(struct ti_tscadc_dev *tsadc, u32 val); |
183 | void am335x_tsc_se_set_once(struct ti_tscadc_dev *tsadc, u32 val); | |
abeccee4 | 184 | void am335x_tsc_se_clr(struct ti_tscadc_dev *tsadc, u32 val); |
7ca6740c | 185 | void am335x_tsc_se_adc_done(struct ti_tscadc_dev *tsadc); |
abeccee4 | 186 | |
01636eb9 | 187 | #endif |