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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
f024ff10 DES |
2 | #ifndef MFD_TMIO_H |
3 | #define MFD_TMIO_H | |
4 | ||
c8be24c2 | 5 | #include <linux/device.h> |
b53cde35 | 6 | #include <linux/fb.h> |
64e8867b | 7 | #include <linux/io.h> |
c8be24c2 | 8 | #include <linux/jiffies.h> |
bbf0208d | 9 | #include <linux/mmc/card.h> |
64e8867b | 10 | #include <linux/platform_device.h> |
7311bef0 | 11 | #include <linux/pm_runtime.h> |
b53cde35 | 12 | |
d3a2f718 IM |
13 | #define tmio_ioread8(addr) readb(addr) |
14 | #define tmio_ioread16(addr) readw(addr) | |
15 | #define tmio_ioread16_rep(r, b, l) readsw(r, b, l) | |
16 | #define tmio_ioread32(addr) \ | |
f2218db8 | 17 | (((u32)readw((addr))) | (((u32)readw((addr) + 2)) << 16)) |
d3a2f718 IM |
18 | |
19 | #define tmio_iowrite8(val, addr) writeb((val), (addr)) | |
20 | #define tmio_iowrite16(val, addr) writew((val), (addr)) | |
21 | #define tmio_iowrite16_rep(r, b, l) writesw(r, b, l) | |
22 | #define tmio_iowrite32(val, addr) \ | |
23 | do { \ | |
f2218db8 SH |
24 | writew((val), (addr)); \ |
25 | writew((val) >> 16, (addr) + 2); \ | |
d3a2f718 IM |
26 | } while (0) |
27 | ||
64e8867b IM |
28 | #define CNF_CMD 0x04 |
29 | #define CNF_CTL_BASE 0x10 | |
30 | #define CNF_INT_PIN 0x3d | |
31 | #define CNF_STOP_CLK_CTL 0x40 | |
32 | #define CNF_GCLK_CTL 0x41 | |
33 | #define CNF_SD_CLK_MODE 0x42 | |
34 | #define CNF_PIN_STATUS 0x44 | |
35 | #define CNF_PWR_CTL_1 0x48 | |
36 | #define CNF_PWR_CTL_2 0x49 | |
37 | #define CNF_PWR_CTL_3 0x4a | |
38 | #define CNF_CARD_DETECT_MODE 0x4c | |
39 | #define CNF_SD_SLOT 0x50 | |
40 | #define CNF_EXT_GCLK_CTL_1 0xf0 | |
41 | #define CNF_EXT_GCLK_CTL_2 0xf1 | |
42 | #define CNF_EXT_GCLK_CTL_3 0xf9 | |
43 | #define CNF_SD_LED_EN_1 0xfa | |
44 | #define CNF_SD_LED_EN_2 0xfe | |
45 | ||
46 | #define SDCREN 0x2 /* Enable access to MMC CTL regs. (flag in COMMAND_REG)*/ | |
47 | ||
48 | #define sd_config_write8(base, shift, reg, val) \ | |
49 | tmio_iowrite8((val), (base) + ((reg) << (shift))) | |
50 | #define sd_config_write16(base, shift, reg, val) \ | |
51 | tmio_iowrite16((val), (base) + ((reg) << (shift))) | |
52 | #define sd_config_write32(base, shift, reg, val) \ | |
53 | do { \ | |
54 | tmio_iowrite16((val), (base) + ((reg) << (shift))); \ | |
55 | tmio_iowrite16((val) >> 16, (base) + ((reg + 2) << (shift))); \ | |
56 | } while (0) | |
57 | ||
ac8fb3e8 | 58 | /* tmio MMC platform flags */ |
f2218db8 | 59 | #define TMIO_MMC_WRPROTECT_DISABLE BIT(0) |
f1334fb3 YG |
60 | /* |
61 | * Some controllers can support a 2-byte block size when the bus width | |
62 | * is configured in 4-bit mode. | |
63 | */ | |
f2218db8 | 64 | #define TMIO_MMC_BLKSZ_2BYTES BIT(1) |
845ecd20 AH |
65 | /* |
66 | * Some controllers can support SDIO IRQ signalling. | |
67 | */ | |
f2218db8 | 68 | #define TMIO_MMC_SDIO_IRQ BIT(2) |
04e24b80 | 69 | |
d63c2bf4 | 70 | /* Some features are only available or tested on R-Car Gen2 or later */ |
f2218db8 | 71 | #define TMIO_MMC_MIN_RCAR2 BIT(3) |
04e24b80 | 72 | |
973ed3af SH |
73 | /* |
74 | * Some controllers require waiting for the SD bus to become | |
75 | * idle before writing to some registers. | |
76 | */ | |
f2218db8 | 77 | #define TMIO_MMC_HAS_IDLE_WAIT BIT(4) |
c8be24c2 GL |
78 | /* |
79 | * A GPIO is used for card hotplug detection. We need an extra flag for this, | |
80 | * because 0 is a valid GPIO number too, and requiring users to specify | |
81 | * cd_gpio < 0 to disable GPIO hotplug would break backwards compatibility. | |
82 | */ | |
f2218db8 | 83 | #define TMIO_MMC_USE_GPIO_CD BIT(5) |
ac8fb3e8 | 84 | |
5d60e500 KM |
85 | /* |
86 | * Some controllers doesn't have over 0x100 register. | |
87 | * it is used to checking accessibility of | |
88 | * CTL_SD_CARD_CLK_CTL / CTL_CLK_AND_WAIT_CTL | |
89 | */ | |
f2218db8 | 90 | #define TMIO_MMC_HAVE_HIGH_REG BIT(6) |
5d60e500 | 91 | |
b8d11962 SU |
92 | /* |
93 | * Some controllers have CMD12 automatically | |
94 | * issue/non-issue register | |
95 | */ | |
f2218db8 | 96 | #define TMIO_MMC_HAVE_CMD12_CTRL BIT(7) |
b8d11962 | 97 | |
20dd0373 | 98 | /* Controller has some SDIO status bits which must be 1 */ |
f2218db8 | 99 | #define TMIO_MMC_SDIO_STATUS_SETBITS BIT(8) |
6b98757e | 100 | |
8185e51f CB |
101 | /* |
102 | * Some controllers have a 32-bit wide data port register | |
103 | */ | |
f2218db8 | 104 | #define TMIO_MMC_32BIT_DATA_PORT BIT(9) |
8185e51f | 105 | |
da29fe2b SU |
106 | /* |
107 | * Some controllers allows to set SDx actual clock | |
108 | */ | |
f2218db8 | 109 | #define TMIO_MMC_CLK_ACTUAL BIT(10) |
da29fe2b | 110 | |
5124b592 WS |
111 | /* Some controllers have a CBSY bit */ |
112 | #define TMIO_MMC_HAVE_CBSY BIT(11) | |
113 | ||
64e8867b IM |
114 | int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base); |
115 | int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base); | |
116 | void tmio_core_mmc_pwr(void __iomem *cnf, int shift, int state); | |
117 | void tmio_core_mmc_clk_div(void __iomem *cnf, int shift, int state); | |
118 | ||
03a0675b GL |
119 | struct dma_chan; |
120 | ||
f0e46cc4 PZ |
121 | /* |
122 | * data for the MMC controller | |
123 | */ | |
124 | struct tmio_mmc_data { | |
f33c9d65 KM |
125 | void *chan_priv_tx; |
126 | void *chan_priv_rx; | |
707f0b2f | 127 | unsigned int hclk; |
b741d440 | 128 | unsigned long capabilities; |
02cb3221 | 129 | unsigned long capabilities2; |
ac8fb3e8 | 130 | unsigned long flags; |
a2b14dc9 | 131 | u32 ocr_mask; /* available voltages */ |
c8be24c2 | 132 | unsigned int cd_gpio; |
e471df0b | 133 | int alignment_shift; |
8b4c8f32 | 134 | dma_addr_t dma_rx_offset; |
603aa14d YS |
135 | unsigned int max_blk_count; |
136 | unsigned short max_segs; | |
9d731e75 | 137 | void (*set_pwr)(struct platform_device *host, int state); |
64e8867b | 138 | void (*set_clk_div)(struct platform_device *host, int state); |
f0e46cc4 PZ |
139 | }; |
140 | ||
f024ff10 DES |
141 | /* |
142 | * data for the NAND controller | |
143 | */ | |
144 | struct tmio_nand_data { | |
145 | struct nand_bbt_descr *badblock_pattern; | |
146 | struct mtd_partition *partition; | |
147 | unsigned int num_partitions; | |
827dba9d | 148 | const char *const *part_parsers; |
f024ff10 DES |
149 | }; |
150 | ||
b53cde35 DES |
151 | #define FBIO_TMIO_ACC_WRITE 0x7C639300 |
152 | #define FBIO_TMIO_ACC_SYNC 0x7C639301 | |
153 | ||
154 | struct tmio_fb_data { | |
155 | int (*lcd_set_power)(struct platform_device *fb_dev, | |
f2218db8 | 156 | bool on); |
b53cde35 | 157 | int (*lcd_mode)(struct platform_device *fb_dev, |
f2218db8 | 158 | const struct fb_videomode *mode); |
b53cde35 DES |
159 | int num_modes; |
160 | struct fb_videomode *modes; | |
161 | ||
162 | /* in mm: size of screen */ | |
163 | int height; | |
164 | int width; | |
165 | }; | |
166 | ||
f024ff10 | 167 | #endif |