[mirror_ubuntu-artful-kernel.git] / include / linux / mfd / tps65217.h

/*
 * linux/mfd/tps65217.h
 *
 * Functions to access TPS65217 power management chip.
 *
 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation version 2.
 *
 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
 * kind, whether express or implied; without even the implied warranty
 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#ifndef __LINUX_MFD_TPS65217_H
#define __LINUX_MFD_TPS65217_H

#include <linux/i2c.h>
#include <linux/regulator/driver.h>
#include <linux/regulator/machine.h>

/* TPS chip id list */
#define TPS65217			0xF0

/* I2C ID for TPS65217 part */
#define TPS65217_I2C_ID			0x24

/* All register addresses */
#define TPS65217_REG_CHIPID		0X00
#define TPS65217_REG_PPATH		0X01
#define TPS65217_REG_INT		0X02
#define TPS65217_REG_CHGCONFIG0		0X03
#define TPS65217_REG_CHGCONFIG1		0X04
#define TPS65217_REG_CHGCONFIG2		0X05
#define TPS65217_REG_CHGCONFIG3		0X06
#define TPS65217_REG_WLEDCTRL1		0X07
#define TPS65217_REG_WLEDCTRL2		0X08
#define TPS65217_REG_MUXCTRL		0X09
#define TPS65217_REG_STATUS		0X0A
#define TPS65217_REG_PASSWORD		0X0B
#define TPS65217_REG_PGOOD		0X0C
#define TPS65217_REG_DEFPG		0X0D
#define TPS65217_REG_DEFDCDC1		0X0E
#define TPS65217_REG_DEFDCDC2		0X0F
#define TPS65217_REG_DEFDCDC3		0X10
#define TPS65217_REG_DEFSLEW		0X11
#define TPS65217_REG_DEFLDO1		0X12
#define TPS65217_REG_DEFLDO2		0X13
#define TPS65217_REG_DEFLS1		0X14
#define TPS65217_REG_DEFLS2		0X15
#define TPS65217_REG_ENABLE		0X16
#define TPS65217_REG_DEFUVLO		0X18
#define TPS65217_REG_SEQ1		0X19
#define TPS65217_REG_SEQ2		0X1A
#define TPS65217_REG_SEQ3		0X1B
#define TPS65217_REG_SEQ4		0X1C
#define TPS65217_REG_SEQ5		0X1D
#define TPS65217_REG_SEQ6		0X1E

/* Register field definitions */
#define TPS65217_CHIPID_CHIP_MASK	0xF0
#define TPS65217_CHIPID_REV_MASK	0x0F

#define TPS65217_PPATH_ACSINK_ENABLE	BIT(7)
#define TPS65217_PPATH_USBSINK_ENABLE	BIT(6)
#define TPS65217_PPATH_AC_PW_ENABLE	BIT(5)
#define TPS65217_PPATH_USB_PW_ENABLE	BIT(4)
#define TPS65217_PPATH_AC_CURRENT_MASK	0x0C
#define TPS65217_PPATH_USB_CURRENT_MASK	0x03

#define TPS65217_INT_PBM		BIT(6)
#define TPS65217_INT_ACM		BIT(5)
#define TPS65217_INT_USBM		BIT(4)
#define TPS65217_INT_PBI		BIT(2)
#define TPS65217_INT_ACI		BIT(1)
#define TPS65217_INT_USBI		BIT(0)

#define TPS65217_CHGCONFIG0_TREG	BIT(7)
#define TPS65217_CHGCONFIG0_DPPM	BIT(6)
#define TPS65217_CHGCONFIG0_TSUSP	BIT(5)
#define TPS65217_CHGCONFIG0_TERMI	BIT(4)
#define TPS65217_CHGCONFIG0_ACTIVE	BIT(3)
#define TPS65217_CHGCONFIG0_CHGTOUT	BIT(2)
#define TPS65217_CHGCONFIG0_PCHGTOUT	BIT(1)
#define TPS65217_CHGCONFIG0_BATTEMP	BIT(0)

#define TPS65217_CHGCONFIG1_TMR_MASK	0xC0
#define TPS65217_CHGCONFIG1_TMR_ENABLE	BIT(5)
#define TPS65217_CHGCONFIG1_NTC_TYPE	BIT(4)
#define TPS65217_CHGCONFIG1_RESET	BIT(3)
#define TPS65217_CHGCONFIG1_TERM	BIT(2)
#define TPS65217_CHGCONFIG1_SUSP	BIT(1)
#define TPS65217_CHGCONFIG1_CHG_EN	BIT(0)

#define TPS65217_CHGCONFIG2_DYNTMR	BIT(7)
#define TPS65217_CHGCONFIG2_VPREGHG	BIT(6)
#define TPS65217_CHGCONFIG2_VOREG_MASK	0x30

#define TPS65217_CHGCONFIG3_ICHRG_MASK	0xC0
#define TPS65217_CHGCONFIG3_DPPMTH_MASK	0x30
#define TPS65217_CHGCONFIG2_PCHRGT	BIT(3)
#define TPS65217_CHGCONFIG2_TERMIF	0x06
#define TPS65217_CHGCONFIG2_TRANGE	BIT(0)

#define TPS65217_WLEDCTRL1_ISINK_ENABLE	BIT(3)
#define TPS65217_WLEDCTRL1_ISEL		BIT(2)
#define TPS65217_WLEDCTRL1_FDIM_MASK	0x03

#define TPS65217_WLEDCTRL2_DUTY_MASK	0x7F

#define TPS65217_MUXCTRL_MUX_MASK	0x07

#define TPS65217_STATUS_OFF		BIT(7)
#define TPS65217_STATUS_ACPWR		BIT(3)
#define TPS65217_STATUS_USBPWR		BIT(2)
#define TPS65217_STATUS_PB		BIT(0)

#define TPS65217_PASSWORD_REGS_UNLOCK	0x7D

#define TPS65217_PGOOD_LDO3_PG		BIT(6)
#define TPS65217_PGOOD_LDO4_PG		BIT(5)
#define TPS65217_PGOOD_DC1_PG		BIT(4)
#define TPS65217_PGOOD_DC2_PG		BIT(3)
#define TPS65217_PGOOD_DC3_PG		BIT(2)
#define TPS65217_PGOOD_LDO1_PG		BIT(1)
#define TPS65217_PGOOD_LDO2_PG		BIT(0)

#define TPS65217_DEFPG_LDO1PGM		BIT(3)
#define TPS65217_DEFPG_LDO2PGM		BIT(2)
#define TPS65217_DEFPG_PGDLY_MASK	0x03

#define TPS65217_DEFDCDCX_XADJX		BIT(7)
#define TPS65217_DEFDCDCX_DCDC_MASK	0x3F

#define TPS65217_DEFSLEW_GO		BIT(7)
#define TPS65217_DEFSLEW_GODSBL		BIT(6)
#define TPS65217_DEFSLEW_PFM_EN1	BIT(5)
#define TPS65217_DEFSLEW_PFM_EN2	BIT(4)
#define TPS65217_DEFSLEW_PFM_EN3	BIT(3)
#define TPS65217_DEFSLEW_SLEW_MASK	0x07

#define TPS65217_DEFLDO1_LDO1_MASK	0x0F

#define TPS65217_DEFLDO2_TRACK		BIT(6)
#define TPS65217_DEFLDO2_LDO2_MASK	0x3F

#define TPS65217_DEFLDO3_LDO3_EN	BIT(5)
#define TPS65217_DEFLDO3_LDO3_MASK	0x1F

#define TPS65217_DEFLDO4_LDO4_EN	BIT(5)
#define TPS65217_DEFLDO4_LDO4_MASK	0x1F

#define TPS65217_ENABLE_LS1_EN		BIT(6)
#define TPS65217_ENABLE_LS2_EN		BIT(5)
#define TPS65217_ENABLE_DC1_EN		BIT(4)
#define TPS65217_ENABLE_DC2_EN		BIT(3)
#define TPS65217_ENABLE_DC3_EN		BIT(2)
#define TPS65217_ENABLE_LDO1_EN		BIT(1)
#define TPS65217_ENABLE_LDO2_EN		BIT(0)

#define TPS65217_DEFUVLO_UVLOHYS	BIT(2)
#define TPS65217_DEFUVLO_UVLO_MASK	0x03

#define TPS65217_SEQ1_DC1_SEQ_MASK	0xF0
#define TPS65217_SEQ1_DC2_SEQ_MASK	0x0F

#define TPS65217_SEQ2_DC3_SEQ_MASK	0xF0
#define TPS65217_SEQ2_LDO1_SEQ_MASK	0x0F

#define TPS65217_SEQ3_LDO2_SEQ_MASK	0xF0
#define TPS65217_SEQ3_LDO3_SEQ_MASK	0x0F

#define TPS65217_SEQ4_LDO4_SEQ_MASK	0xF0

#define TPS65217_SEQ5_DLY1_MASK		0xC0
#define TPS65217_SEQ5_DLY2_MASK		0x30
#define TPS65217_SEQ5_DLY3_MASK		0x0C
#define TPS65217_SEQ5_DLY4_MASK		0x03

#define TPS65217_SEQ6_DLY5_MASK		0xC0
#define TPS65217_SEQ6_DLY6_MASK		0x30
#define TPS65217_SEQ6_SEQUP		BIT(2)
#define TPS65217_SEQ6_SEQDWN		BIT(1)
#define TPS65217_SEQ6_INSTDWN		BIT(0)

#define TPS65217_MAX_REGISTER		0x1E
#define TPS65217_PROTECT_NONE		0
#define TPS65217_PROTECT_L1		1
#define TPS65217_PROTECT_L2		2


enum tps65217_regulator_id {
	/* DCDC's */
	TPS65217_DCDC_1,
	TPS65217_DCDC_2,
	TPS65217_DCDC_3,
	/* LDOs */
	TPS65217_LDO_1,
	TPS65217_LDO_2,
	TPS65217_LDO_3,
	TPS65217_LDO_4,
};

#define TPS65217_MAX_REG_ID		TPS65217_LDO_4

/* Number of step-down converters available */
#define TPS65217_NUM_DCDC		3
/* Number of LDO voltage regulators available */
#define TPS65217_NUM_LDO		4
/* Number of total regulators available */
#define TPS65217_NUM_REGULATOR		(TPS65217_NUM_DCDC + TPS65217_NUM_LDO)

enum tps65217_bl_isel {
	TPS65217_BL_ISET1 = 1,
	TPS65217_BL_ISET2,
};

enum tps65217_bl_fdim {
	TPS65217_BL_FDIM_100HZ,
	TPS65217_BL_FDIM_200HZ,
	TPS65217_BL_FDIM_500HZ,
	TPS65217_BL_FDIM_1000HZ,
};

struct tps65217_bl_pdata {
	enum tps65217_bl_isel isel;
	enum tps65217_bl_fdim fdim;
	int dft_brightness;
};

/**
 * struct tps65217_board - packages regulator init data
 * @tps65217_regulator_data: regulator initialization values
 *
 * Board data may be used to initialize regulator.
 */
struct tps65217_board {
	struct regulator_init_data *tps65217_init_data[TPS65217_NUM_REGULATOR];
	struct device_node *of_node[TPS65217_NUM_REGULATOR];
	struct tps65217_bl_pdata *bl_pdata;
};

/**
 * struct tps65217 - tps65217 sub-driver chip access routines
 *
 * Device data may be used to access the TPS65217 chip
 */

struct tps65217 {
	struct device *dev;
	struct tps65217_board *pdata;
	unsigned long id;
	struct regulator_desc desc[TPS65217_NUM_REGULATOR];
	struct regulator_dev *rdev[TPS65217_NUM_REGULATOR];
	struct regmap *regmap;
};

static inline struct tps65217 *dev_to_tps65217(struct device *dev)
{
	return dev_get_drvdata(dev);
}

static inline unsigned long tps65217_chip_id(struct tps65217 *tps65217)
{
	return tps65217->id;
}

int tps65217_reg_read(struct tps65217 *tps, unsigned int reg,
					unsigned int *val);
int tps65217_reg_write(struct tps65217 *tps, unsigned int reg,
			unsigned int val, unsigned int level);
int tps65217_set_bits(struct tps65217 *tps, unsigned int reg,
		unsigned int mask, unsigned int val, unsigned int level);
int tps65217_clear_bits(struct tps65217 *tps, unsigned int reg,
		unsigned int mask, unsigned int level);

#endif /*  __LINUX_MFD_TPS65217_H */
Commit	Line	Data
d48f411c AC	1	/*
	2	* linux/mfd/tps65217.h
	3	*
	4	* Functions to access TPS65217 power management chip.
	5	*
	6	* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation version 2.
	11	*
	12	* This program is distributed "as is" WITHOUT ANY WARRANTY of any
	13	* kind, whether express or implied; without even the implied warranty
	14	* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*/
	17
	18	#ifndef __LINUX_MFD_TPS65217_H
	19	#define __LINUX_MFD_TPS65217_H
	20
	21	#include <linux/i2c.h>
	22	#include <linux/regulator/driver.h>
	23	#include <linux/regulator/machine.h>
	24
817bb7fb AC	25	/* TPS chip id list */
	26	#define TPS65217 0xF0
	27
d48f411c AC	28	/* I2C ID for TPS65217 part */
	29	#define TPS65217_I2C_ID 0x24
	30
	31	/* All register addresses */
	32	#define TPS65217_REG_CHIPID 0X00
	33	#define TPS65217_REG_PPATH 0X01
	34	#define TPS65217_REG_INT 0X02
	35	#define TPS65217_REG_CHGCONFIG0 0X03
	36	#define TPS65217_REG_CHGCONFIG1 0X04
	37	#define TPS65217_REG_CHGCONFIG2 0X05
	38	#define TPS65217_REG_CHGCONFIG3 0X06
	39	#define TPS65217_REG_WLEDCTRL1 0X07
	40	#define TPS65217_REG_WLEDCTRL2 0X08
	41	#define TPS65217_REG_MUXCTRL 0X09
	42	#define TPS65217_REG_STATUS 0X0A
	43	#define TPS65217_REG_PASSWORD 0X0B
	44	#define TPS65217_REG_PGOOD 0X0C
	45	#define TPS65217_REG_DEFPG 0X0D
	46	#define TPS65217_REG_DEFDCDC1 0X0E
	47	#define TPS65217_REG_DEFDCDC2 0X0F
	48	#define TPS65217_REG_DEFDCDC3 0X10
	49	#define TPS65217_REG_DEFSLEW 0X11
	50	#define TPS65217_REG_DEFLDO1 0X12
	51	#define TPS65217_REG_DEFLDO2 0X13
	52	#define TPS65217_REG_DEFLS1 0X14
	53	#define TPS65217_REG_DEFLS2 0X15
	54	#define TPS65217_REG_ENABLE 0X16
	55	#define TPS65217_REG_DEFUVLO 0X18
	56	#define TPS65217_REG_SEQ1 0X19
	57	#define TPS65217_REG_SEQ2 0X1A
	58	#define TPS65217_REG_SEQ3 0X1B
	59	#define TPS65217_REG_SEQ4 0X1C
	60	#define TPS65217_REG_SEQ5 0X1D
	61	#define TPS65217_REG_SEQ6 0X1E
	62
	63	/* Register field definitions */
	64	#define TPS65217_CHIPID_CHIP_MASK 0xF0
	65	#define TPS65217_CHIPID_REV_MASK 0x0F
	66
	67	#define TPS65217_PPATH_ACSINK_ENABLE BIT(7)
	68	#define TPS65217_PPATH_USBSINK_ENABLE BIT(6)
	69	#define TPS65217_PPATH_AC_PW_ENABLE BIT(5)
	70	#define TPS65217_PPATH_USB_PW_ENABLE BIT(4)
	71	#define TPS65217_PPATH_AC_CURRENT_MASK 0x0C
	72	#define TPS65217_PPATH_USB_CURRENT_MASK 0x03
	73
	74	#define TPS65217_INT_PBM BIT(6)
	75	#define TPS65217_INT_ACM BIT(5)
	76	#define TPS65217_INT_USBM BIT(4)
	77	#define TPS65217_INT_PBI BIT(2)
	78	#define TPS65217_INT_ACI BIT(1)
	79	#define TPS65217_INT_USBI BIT(0)
	80
	81	#define TPS65217_CHGCONFIG0_TREG BIT(7)
	82	#define TPS65217_CHGCONFIG0_DPPM BIT(6)
	83	#define TPS65217_CHGCONFIG0_TSUSP BIT(5)
	84	#define TPS65217_CHGCONFIG0_TERMI BIT(4)
	85	#define TPS65217_CHGCONFIG0_ACTIVE BIT(3)
	86	#define TPS65217_CHGCONFIG0_CHGTOUT BIT(2)
	87	#define TPS65217_CHGCONFIG0_PCHGTOUT BIT(1)
	88	#define TPS65217_CHGCONFIG0_BATTEMP BIT(0)
	89
	90	#define TPS65217_CHGCONFIG1_TMR_MASK 0xC0
	91	#define TPS65217_CHGCONFIG1_TMR_ENABLE BIT(5)
92	#define TPS65217_CHGCONFIG1_NTC_TYPE BIT(4)
93	#define TPS65217_CHGCONFIG1_RESET BIT(3)
94	#define TPS65217_CHGCONFIG1_TERM BIT(2)
95	#define TPS65217_CHGCONFIG1_SUSP BIT(1)
96	#define TPS65217_CHGCONFIG1_CHG_EN BIT(0)
97
98	#define TPS65217_CHGCONFIG2_DYNTMR BIT(7)
99	#define TPS65217_CHGCONFIG2_VPREGHG BIT(6)
100	#define TPS65217_CHGCONFIG2_VOREG_MASK 0x30
101
102	#define TPS65217_CHGCONFIG3_ICHRG_MASK 0xC0
103	#define TPS65217_CHGCONFIG3_DPPMTH_MASK 0x30
104	#define TPS65217_CHGCONFIG2_PCHRGT BIT(3)
105	#define TPS65217_CHGCONFIG2_TERMIF 0x06
106	#define TPS65217_CHGCONFIG2_TRANGE BIT(0)
107
108	#define TPS65217_WLEDCTRL1_ISINK_ENABLE BIT(3)
109	#define TPS65217_WLEDCTRL1_ISEL BIT(2)
110	#define TPS65217_WLEDCTRL1_FDIM_MASK 0x03
111
112	#define TPS65217_WLEDCTRL2_DUTY_MASK 0x7F
113
114	#define TPS65217_MUXCTRL_MUX_MASK 0x07
115
116	#define TPS65217_STATUS_OFF BIT(7)
117	#define TPS65217_STATUS_ACPWR BIT(3)
118	#define TPS65217_STATUS_USBPWR BIT(2)
119	#define TPS65217_STATUS_PB BIT(0)
120
121	#define TPS65217_PASSWORD_REGS_UNLOCK 0x7D
122
123	#define TPS65217_PGOOD_LDO3_PG BIT(6)
124	#define TPS65217_PGOOD_LDO4_PG BIT(5)
125	#define TPS65217_PGOOD_DC1_PG BIT(4)
126	#define TPS65217_PGOOD_DC2_PG BIT(3)
127	#define TPS65217_PGOOD_DC3_PG BIT(2)
128	#define TPS65217_PGOOD_LDO1_PG BIT(1)
129	#define TPS65217_PGOOD_LDO2_PG BIT(0)
130
131	#define TPS65217_DEFPG_LDO1PGM BIT(3)
132	#define TPS65217_DEFPG_LDO2PGM BIT(2)
133	#define TPS65217_DEFPG_PGDLY_MASK 0x03
134
135	#define TPS65217_DEFDCDCX_XADJX BIT(7)
136	#define TPS65217_DEFDCDCX_DCDC_MASK 0x3F
137
138	#define TPS65217_DEFSLEW_GO BIT(7)
139	#define TPS65217_DEFSLEW_GODSBL BIT(6)
140	#define TPS65217_DEFSLEW_PFM_EN1 BIT(5)
141	#define TPS65217_DEFSLEW_PFM_EN2 BIT(4)
142	#define TPS65217_DEFSLEW_PFM_EN3 BIT(3)
143	#define TPS65217_DEFSLEW_SLEW_MASK 0x07
144
145	#define TPS65217_DEFLDO1_LDO1_MASK 0x0F
146
147	#define TPS65217_DEFLDO2_TRACK BIT(6)
148	#define TPS65217_DEFLDO2_LDO2_MASK 0x3F
149
150	#define TPS65217_DEFLDO3_LDO3_EN BIT(5)
151	#define TPS65217_DEFLDO3_LDO3_MASK 0x1F
152
153	#define TPS65217_DEFLDO4_LDO4_EN BIT(5)
154	#define TPS65217_DEFLDO4_LDO4_MASK 0x1F
155
156	#define TPS65217_ENABLE_LS1_EN BIT(6)
157	#define TPS65217_ENABLE_LS2_EN BIT(5)
158	#define TPS65217_ENABLE_DC1_EN BIT(4)
159	#define TPS65217_ENABLE_DC2_EN BIT(3)
160	#define TPS65217_ENABLE_DC3_EN BIT(2)
161	#define TPS65217_ENABLE_LDO1_EN BIT(1)
162	#define TPS65217_ENABLE_LDO2_EN BIT(0)
163
164	#define TPS65217_DEFUVLO_UVLOHYS BIT(2)
165	#define TPS65217_DEFUVLO_UVLO_MASK 0x03
166
167	#define TPS65217_SEQ1_DC1_SEQ_MASK 0xF0
168	#define TPS65217_SEQ1_DC2_SEQ_MASK 0x0F
169
170	#define TPS65217_SEQ2_DC3_SEQ_MASK 0xF0
171	#define TPS65217_SEQ2_LDO1_SEQ_MASK 0x0F
172
173	#define TPS65217_SEQ3_LDO2_SEQ_MASK 0xF0
174	#define TPS65217_SEQ3_LDO3_SEQ_MASK 0x0F
175
176	#define TPS65217_SEQ4_LDO4_SEQ_MASK 0xF0
177
178	#define TPS65217_SEQ5_DLY1_MASK 0xC0
179	#define TPS65217_SEQ5_DLY2_MASK 0x30
180	#define TPS65217_SEQ5_DLY3_MASK 0x0C
181	#define TPS65217_SEQ5_DLY4_MASK 0x03
182
183	#define TPS65217_SEQ6_DLY5_MASK 0xC0
184	#define TPS65217_SEQ6_DLY6_MASK 0x30
185	#define TPS65217_SEQ6_SEQUP BIT(2)
186	#define TPS65217_SEQ6_SEQDWN BIT(1)
187	#define TPS65217_SEQ6_INSTDWN BIT(0)
188
189	#define TPS65217_MAX_REGISTER 0x1E
190	#define TPS65217_PROTECT_NONE 0
191	#define TPS65217_PROTECT_L1 1
192	#define TPS65217_PROTECT_L2 2
193
194
195	enum tps65217_regulator_id {
196	/* DCDC's */
197	TPS65217_DCDC_1,
198	TPS65217_DCDC_2,
199	TPS65217_DCDC_3,
200	/* LDOs */
201	TPS65217_LDO_1,
202	TPS65217_LDO_2,
203	TPS65217_LDO_3,
204	TPS65217_LDO_4,
205	};
206
207	#define TPS65217_MAX_REG_ID TPS65217_LDO_4
208
209	/* Number of step-down converters available */
210	#define TPS65217_NUM_DCDC 3
211	/* Number of LDO voltage regulators available */
212	#define TPS65217_NUM_LDO 4
213	/* Number of total regulators available */
214	#define TPS65217_NUM_REGULATOR (TPS65217_NUM_DCDC + TPS65217_NUM_LDO)
215
eebfdc17 MK	216	enum tps65217_bl_isel {
	217	TPS65217_BL_ISET1 = 1,
	218	TPS65217_BL_ISET2,
	219	};
	220
	221	enum tps65217_bl_fdim {
	222	TPS65217_BL_FDIM_100HZ,
	223	TPS65217_BL_FDIM_200HZ,
	224	TPS65217_BL_FDIM_500HZ,
	225	TPS65217_BL_FDIM_1000HZ,
	226	};
	227
	228	struct tps65217_bl_pdata {
	229	enum tps65217_bl_isel isel;
	230	enum tps65217_bl_fdim fdim;
4d22f8c3	231	int dft_brightness;
eebfdc17 MK	232	};
eebfdc17 MK	233
d48f411c AC	234	/**
	235	* struct tps65217_board - packages regulator init data
	236	* @tps65217_regulator_data: regulator initialization values
	237	*
	238	* Board data may be used to initialize regulator.
	239	*/
	240	struct tps65217_board {
a7f1b63e AC	241	struct regulator_init_data *tps65217_init_data[TPS65217_NUM_REGULATOR];
a7f1b63e AC	242	struct device_node *of_node[TPS65217_NUM_REGULATOR];
eebfdc17	243	struct tps65217_bl_pdata *bl_pdata;
d48f411c AC	244	};
d48f411c AC	245
d48f411c AC	246	/**
	247	* struct tps65217 - tps65217 sub-driver chip access routines
	248	*
	249	* Device data may be used to access the TPS65217 chip
	250	*/
	251
	252	struct tps65217 {
	253	struct device *dev;
	254	struct tps65217_board *pdata;
5c6fbd56	255	unsigned long id;
d48f411c AC	256	struct regulator_desc desc[TPS65217_NUM_REGULATOR];
d48f411c AC	257	struct regulator_dev *rdev[TPS65217_NUM_REGULATOR];
d48f411c	258	struct regmap *regmap;
d48f411c AC	259	};
	260
	261	static inline struct tps65217 dev_to_tps65217(struct device dev)
	262	{
	263	return dev_get_drvdata(dev);
	264	}
	265
5c6fbd56	266	static inline unsigned long tps65217_chip_id(struct tps65217 *tps65217)
817bb7fb AC	267	{
	268	return tps65217->id;
	269	}
	270
d48f411c AC	271	int tps65217_reg_read(struct tps65217 *tps, unsigned int reg,
	272	unsigned int *val);
	273	int tps65217_reg_write(struct tps65217 *tps, unsigned int reg,
	274	unsigned int val, unsigned int level);
	275	int tps65217_set_bits(struct tps65217 *tps, unsigned int reg,
	276	unsigned int mask, unsigned int val, unsigned int level);
	277	int tps65217_clear_bits(struct tps65217 *tps, unsigned int reg,
	278	unsigned int mask, unsigned int level);
	279
	280	#endif /* __LINUX_MFD_TPS65217_H */