[mirror_ubuntu-artful-kernel.git] / include / linux / mfd / twl6040.h

/*
 * MFD driver for twl6040
 *
 * Authors:     Jorge Eduardo Candelaria <jorge.candelaria@ti.com>
 *              Misael Lopez Cruz <misael.lopez@ti.com>
 *
 * Copyright:   (C) 2011 Texas Instruments, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful, but
 * WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 * General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
 * 02110-1301 USA
 *
 */

#ifndef __TWL6040_CODEC_H__
#define __TWL6040_CODEC_H__

#include <linux/interrupt.h>
#include <linux/mfd/core.h>

#define TWL6040_REG_ASICID		0x01
#define TWL6040_REG_ASICREV		0x02
#define TWL6040_REG_INTID		0x03
#define TWL6040_REG_INTMR		0x04
#define TWL6040_REG_NCPCTL		0x05
#define TWL6040_REG_LDOCTL		0x06
#define TWL6040_REG_HPPLLCTL		0x07
#define TWL6040_REG_LPPLLCTL		0x08
#define TWL6040_REG_LPPLLDIV		0x09
#define TWL6040_REG_AMICBCTL		0x0A
#define TWL6040_REG_DMICBCTL		0x0B
#define TWL6040_REG_MICLCTL		0x0C
#define TWL6040_REG_MICRCTL		0x0D
#define TWL6040_REG_MICGAIN		0x0E
#define TWL6040_REG_LINEGAIN		0x0F
#define TWL6040_REG_HSLCTL		0x10
#define TWL6040_REG_HSRCTL		0x11
#define TWL6040_REG_HSGAIN		0x12
#define TWL6040_REG_EARCTL		0x13
#define TWL6040_REG_HFLCTL		0x14
#define TWL6040_REG_HFLGAIN		0x15
#define TWL6040_REG_HFRCTL		0x16
#define TWL6040_REG_HFRGAIN		0x17
#define TWL6040_REG_VIBCTLL		0x18
#define TWL6040_REG_VIBDATL		0x19
#define TWL6040_REG_VIBCTLR		0x1A
#define TWL6040_REG_VIBDATR		0x1B
#define TWL6040_REG_HKCTL1		0x1C
#define TWL6040_REG_HKCTL2		0x1D
#define TWL6040_REG_GPOCTL		0x1E
#define TWL6040_REG_ALB			0x1F
#define TWL6040_REG_DLB			0x20
#define TWL6040_REG_TRIM1		0x28
#define TWL6040_REG_TRIM2		0x29
#define TWL6040_REG_TRIM3		0x2A
#define TWL6040_REG_HSOTRIM		0x2B
#define TWL6040_REG_HFOTRIM		0x2C
#define TWL6040_REG_ACCCTL		0x2D
#define TWL6040_REG_STATUS		0x2E

/* INTID (0x03) fields */

#define TWL6040_THINT			0x01
#define TWL6040_PLUGINT			0x02
#define TWL6040_UNPLUGINT		0x04
#define TWL6040_HOOKINT			0x08
#define TWL6040_HFINT			0x10
#define TWL6040_VIBINT			0x20
#define TWL6040_READYINT		0x40

/* INTMR (0x04) fields */

#define TWL6040_THMSK			0x01
#define TWL6040_PLUGMSK			0x02
#define TWL6040_HOOKMSK			0x08
#define TWL6040_HFMSK			0x10
#define TWL6040_VIBMSK			0x20
#define TWL6040_READYMSK		0x40
#define TWL6040_ALLINT_MSK		0x7B

/* NCPCTL (0x05) fields */

#define TWL6040_NCPENA			0x01
#define TWL6040_NCPOPEN			0x40

/* LDOCTL (0x06) fields */

#define TWL6040_LSLDOENA		0x01
#define TWL6040_HSLDOENA		0x04
#define TWL6040_REFENA			0x40
#define TWL6040_OSCENA			0x80

/* HPPLLCTL (0x07) fields */

#define TWL6040_HPLLENA			0x01
#define TWL6040_HPLLRST			0x02
#define TWL6040_HPLLBP			0x04
#define TWL6040_HPLLSQRENA		0x08
#define TWL6040_MCLK_12000KHZ		(0 << 5)
#define TWL6040_MCLK_19200KHZ		(1 << 5)
#define TWL6040_MCLK_26000KHZ		(2 << 5)
#define TWL6040_MCLK_38400KHZ		(3 << 5)
#define TWL6040_MCLK_MSK		0x60

/* LPPLLCTL (0x08) fields */

#define TWL6040_LPLLENA			0x01
#define TWL6040_LPLLRST			0x02
#define TWL6040_LPLLSEL			0x04
#define TWL6040_LPLLFIN			0x08
#define TWL6040_HPLLSEL			0x10

/* HSLCTL/R (0x10/0x11) fields */

#define TWL6040_HSDACMODE		(1 << 1)
#define TWL6040_HSDRVMODE		(1 << 3)

/* VIBCTLL/R (0x18/0x1A) fields */

#define TWL6040_VIBENA			(1 << 0)
#define TWL6040_VIBSEL			(1 << 1)
#define TWL6040_VIBCTRL			(1 << 2)
#define TWL6040_VIBCTRL_P		(1 << 3)
#define TWL6040_VIBCTRL_N		(1 << 4)

/* VIBDATL/R (0x19/0x1B) fields */

#define TWL6040_VIBDAT_MAX		0x64

/* GPOCTL (0x1E) fields */

#define TWL6040_GPO1			0x01
#define TWL6040_GPO2			0x02
#define TWL6040_GPO3			0x03

/* ACCCTL (0x2D) fields */

#define TWL6040_I2CSEL			0x01
#define TWL6040_RESETSPLIT		0x04
#define TWL6040_INTCLRMODE		0x08

/* STATUS (0x2E) fields */

#define TWL6040_PLUGCOMP		0x02
#define TWL6040_VIBLOCDET		0x10
#define TWL6040_VIBROCDET		0x20
#define TWL6040_TSHUTDET                0x40

#define TWL6040_CELLS			2

#define TWL6040_REV_ES1_0		0x00
#define TWL6040_REV_ES1_1		0x01
#define TWL6040_REV_ES1_2		0x02

#define TWL6040_IRQ_TH			0
#define TWL6040_IRQ_PLUG		1
#define TWL6040_IRQ_HOOK		2
#define TWL6040_IRQ_HF			3
#define TWL6040_IRQ_VIB			4
#define TWL6040_IRQ_READY		5

/* PLL selection */
#define TWL6040_SYSCLK_SEL_LPPLL	0
#define TWL6040_SYSCLK_SEL_HPPLL	1

struct twl6040 {
	struct device *dev;
	struct mutex mutex;
	struct mutex io_mutex;
	struct mutex irq_mutex;
	struct mfd_cell cells[TWL6040_CELLS];
	struct completion ready;

	int audpwron;
	int power_count;
	int rev;
	u8 vibra_ctrl_cache[2];

	int pll;
	unsigned int sysclk;

	unsigned int irq;
	unsigned int irq_base;
	u8 irq_masks_cur;
	u8 irq_masks_cache;
};

int twl6040_reg_read(struct twl6040 *twl6040, unsigned int reg);
int twl6040_reg_write(struct twl6040 *twl6040, unsigned int reg,
		      u8 val);
int twl6040_set_bits(struct twl6040 *twl6040, unsigned int reg,
		     u8 mask);
int twl6040_clear_bits(struct twl6040 *twl6040, unsigned int reg,
		       u8 mask);
int twl6040_power(struct twl6040 *twl6040, int on);
int twl6040_set_pll(struct twl6040 *twl6040, int pll_id,
		    unsigned int freq_in, unsigned int freq_out);
int twl6040_get_pll(struct twl6040 *twl6040);
unsigned int twl6040_get_sysclk(struct twl6040 *twl6040);
int twl6040_irq_init(struct twl6040 *twl6040);
void twl6040_irq_exit(struct twl6040 *twl6040);
/* Get the combined status of the vibra control register */
int twl6040_get_vibralr_status(struct twl6040 *twl6040);

static inline int twl6040_get_revid(struct twl6040 *twl6040)
{
	return twl6040->rev;
}


#endif  /* End of __TWL6040_CODEC_H__ */
Commit	Line	Data
f19b2823 MLC	1	/*
	2	* MFD driver for twl6040
	3	*
	4	* Authors: Jorge Eduardo Candelaria <jorge.candelaria@ti.com>
	5	* Misael Lopez Cruz <misael.lopez@ti.com>
	6	*
	7	* Copyright: (C) 2011 Texas Instruments, Inc.
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License version 2 as
	11	* published by the Free Software Foundation.
	12	*
	13	* This program is distributed in the hope that it will be useful, but
	14	* WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	16	* General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
	21	* 02110-1301 USA
	22	*
	23	*/
	24
	25	#ifndef __TWL6040_CODEC_H__
	26	#define __TWL6040_CODEC_H__
	27
	28	#include <linux/interrupt.h>
	29	#include <linux/mfd/core.h>
	30
	31	#define TWL6040_REG_ASICID 0x01
	32	#define TWL6040_REG_ASICREV 0x02
	33	#define TWL6040_REG_INTID 0x03
	34	#define TWL6040_REG_INTMR 0x04
	35	#define TWL6040_REG_NCPCTL 0x05
	36	#define TWL6040_REG_LDOCTL 0x06
	37	#define TWL6040_REG_HPPLLCTL 0x07
	38	#define TWL6040_REG_LPPLLCTL 0x08
	39	#define TWL6040_REG_LPPLLDIV 0x09
	40	#define TWL6040_REG_AMICBCTL 0x0A
	41	#define TWL6040_REG_DMICBCTL 0x0B
	42	#define TWL6040_REG_MICLCTL 0x0C
	43	#define TWL6040_REG_MICRCTL 0x0D
	44	#define TWL6040_REG_MICGAIN 0x0E
	45	#define TWL6040_REG_LINEGAIN 0x0F
	46	#define TWL6040_REG_HSLCTL 0x10
	47	#define TWL6040_REG_HSRCTL 0x11
	48	#define TWL6040_REG_HSGAIN 0x12
	49	#define TWL6040_REG_EARCTL 0x13
	50	#define TWL6040_REG_HFLCTL 0x14
	51	#define TWL6040_REG_HFLGAIN 0x15
	52	#define TWL6040_REG_HFRCTL 0x16
	53	#define TWL6040_REG_HFRGAIN 0x17
	54	#define TWL6040_REG_VIBCTLL 0x18
	55	#define TWL6040_REG_VIBDATL 0x19
	56	#define TWL6040_REG_VIBCTLR 0x1A
	57	#define TWL6040_REG_VIBDATR 0x1B
	58	#define TWL6040_REG_HKCTL1 0x1C
	59	#define TWL6040_REG_HKCTL2 0x1D
	60	#define TWL6040_REG_GPOCTL 0x1E
	61	#define TWL6040_REG_ALB 0x1F
	62	#define TWL6040_REG_DLB 0x20
	63	#define TWL6040_REG_TRIM1 0x28
	64	#define TWL6040_REG_TRIM2 0x29
65	#define TWL6040_REG_TRIM3 0x2A
66	#define TWL6040_REG_HSOTRIM 0x2B
67	#define TWL6040_REG_HFOTRIM 0x2C
68	#define TWL6040_REG_ACCCTL 0x2D
69	#define TWL6040_REG_STATUS 0x2E
70
f19b2823 MLC	71	/* INTID (0x03) fields */
	72
	73	#define TWL6040_THINT 0x01
	74	#define TWL6040_PLUGINT 0x02
	75	#define TWL6040_UNPLUGINT 0x04
	76	#define TWL6040_HOOKINT 0x08
	77	#define TWL6040_HFINT 0x10
	78	#define TWL6040_VIBINT 0x20
	79	#define TWL6040_READYINT 0x40
	80
	81	/* INTMR (0x04) fields */
	82
	83	#define TWL6040_THMSK 0x01
	84	#define TWL6040_PLUGMSK 0x02
	85	#define TWL6040_HOOKMSK 0x08
	86	#define TWL6040_HFMSK 0x10
	87	#define TWL6040_VIBMSK 0x20
	88	#define TWL6040_READYMSK 0x40
	89	#define TWL6040_ALLINT_MSK 0x7B
	90
	91	/* NCPCTL (0x05) fields */
	92
	93	#define TWL6040_NCPENA 0x01
	94	#define TWL6040_NCPOPEN 0x40
	95
	96	/* LDOCTL (0x06) fields */
	97
	98	#define TWL6040_LSLDOENA 0x01
	99	#define TWL6040_HSLDOENA 0x04
	100	#define TWL6040_REFENA 0x40
	101	#define TWL6040_OSCENA 0x80
	102
	103	/* HPPLLCTL (0x07) fields */
	104
	105	#define TWL6040_HPLLENA 0x01
	106	#define TWL6040_HPLLRST 0x02
	107	#define TWL6040_HPLLBP 0x04
	108	#define TWL6040_HPLLSQRENA 0x08
	109	#define TWL6040_MCLK_12000KHZ (0 << 5)
	110	#define TWL6040_MCLK_19200KHZ (1 << 5)
	111	#define TWL6040_MCLK_26000KHZ (2 << 5)
	112	#define TWL6040_MCLK_38400KHZ (3 << 5)
	113	#define TWL6040_MCLK_MSK 0x60
	114
	115	/* LPPLLCTL (0x08) fields */
	116
	117	#define TWL6040_LPLLENA 0x01
	118	#define TWL6040_LPLLRST 0x02
	119	#define TWL6040_LPLLSEL 0x04
	120	#define TWL6040_LPLLFIN 0x08
	121	#define TWL6040_HPLLSEL 0x10
	122
ab6cf139	123	/* HSLCTL/R (0x10/0x11) fields */
f19b2823	124
ab6cf139 PU	125	#define TWL6040_HSDACMODE (1 << 1)
ab6cf139 PU	126	#define TWL6040_HSDRVMODE (1 << 3)
f19b2823	127
1e036f65	128	/* VIBCTLL/R (0x18/0x1A) fields */
f19b2823	129
1e036f65 PU	130	#define TWL6040_VIBENA (1 << 0)
	131	#define TWL6040_VIBSEL (1 << 1)
	132	#define TWL6040_VIBCTRL (1 << 2)
	133	#define TWL6040_VIBCTRL_P (1 << 3)
	134	#define TWL6040_VIBCTRL_N (1 << 4)
f19b2823	135
1e036f65	136	/* VIBDATL/R (0x19/0x1B) fields */
f19b2823 MLC	137
	138	#define TWL6040_VIBDAT_MAX 0x64
	139
f19b2823 MLC	140	/* GPOCTL (0x1E) fields */
	141
	142	#define TWL6040_GPO1 0x01
	143	#define TWL6040_GPO2 0x02
	144	#define TWL6040_GPO3 0x03
	145
	146	/* ACCCTL (0x2D) fields */
	147
	148	#define TWL6040_I2CSEL 0x01
	149	#define TWL6040_RESETSPLIT 0x04
	150	#define TWL6040_INTCLRMODE 0x08
	151
f19b2823 MLC	152	/* STATUS (0x2E) fields */
	153
	154	#define TWL6040_PLUGCOMP 0x02
	155	#define TWL6040_VIBLOCDET 0x10
	156	#define TWL6040_VIBROCDET 0x20
	157	#define TWL6040_TSHUTDET 0x40
	158
	159	#define TWL6040_CELLS 2
	160
	161	#define TWL6040_REV_ES1_0 0x00
	162	#define TWL6040_REV_ES1_1 0x01
	163	#define TWL6040_REV_ES1_2 0x02
	164
	165	#define TWL6040_IRQ_TH 0
	166	#define TWL6040_IRQ_PLUG 1
	167	#define TWL6040_IRQ_HOOK 2
	168	#define TWL6040_IRQ_HF 3
	169	#define TWL6040_IRQ_VIB 4
	170	#define TWL6040_IRQ_READY 5
	171
cfb7a33b PU	172	/* PLL selection */
	173	#define TWL6040_SYSCLK_SEL_LPPLL 0
	174	#define TWL6040_SYSCLK_SEL_HPPLL 1
f19b2823 MLC	175
	176	struct twl6040 {
	177	struct device *dev;
	178	struct mutex mutex;
	179	struct mutex io_mutex;
	180	struct mutex irq_mutex;
	181	struct mfd_cell cells[TWL6040_CELLS];
	182	struct completion ready;
	183
	184	int audpwron;
	185	int power_count;
	186	int rev;
31b402e3	187	u8 vibra_ctrl_cache[2];
f19b2823	188
cfb7a33b	189	int pll;
f19b2823 MLC	190	unsigned int sysclk;
	191
	192	unsigned int irq;
	193	unsigned int irq_base;
	194	u8 irq_masks_cur;
	195	u8 irq_masks_cache;
	196	};
	197
f19b2823 MLC	198	int twl6040_reg_read(struct twl6040 *twl6040, unsigned int reg);
	199	int twl6040_reg_write(struct twl6040 *twl6040, unsigned int reg,
	200	u8 val);
	201	int twl6040_set_bits(struct twl6040 *twl6040, unsigned int reg,
	202	u8 mask);
	203	int twl6040_clear_bits(struct twl6040 *twl6040, unsigned int reg,
	204	u8 mask);
	205	int twl6040_power(struct twl6040 *twl6040, int on);
cfb7a33b	206	int twl6040_set_pll(struct twl6040 *twl6040, int pll_id,
f19b2823	207	unsigned int freq_in, unsigned int freq_out);
cfb7a33b	208	int twl6040_get_pll(struct twl6040 *twl6040);
f19b2823 MLC	209	unsigned int twl6040_get_sysclk(struct twl6040 *twl6040);
	210	int twl6040_irq_init(struct twl6040 *twl6040);
	211	void twl6040_irq_exit(struct twl6040 *twl6040);
70601ec1 PU	212	/* Get the combined status of the vibra control register */
70601ec1 PU	213	int twl6040_get_vibralr_status(struct twl6040 *twl6040);
f19b2823	214
a69882ae PU	215	static inline int twl6040_get_revid(struct twl6040 *twl6040)
	216	{
	217	return twl6040->rev;
	218	}
	219
70601ec1	220
f19b2823	221	#endif /* End of __TWL6040_CODEC_H__ */