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225c7b1f RD |
1 | /* |
2 | * Copyright (c) 2006 Cisco Systems, Inc. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef MLX4_CMD_H | |
34 | #define MLX4_CMD_H | |
35 | ||
36 | #include <linux/dma-mapping.h> | |
2cccb9e4 | 37 | #include <linux/if_link.h> |
9616982f | 38 | #include <linux/mlx4/device.h> |
62a89055 | 39 | #include <linux/netdevice.h> |
225c7b1f RD |
40 | |
41 | enum { | |
42 | /* initialization and general commands */ | |
43 | MLX4_CMD_SYS_EN = 0x1, | |
44 | MLX4_CMD_SYS_DIS = 0x2, | |
45 | MLX4_CMD_MAP_FA = 0xfff, | |
46 | MLX4_CMD_UNMAP_FA = 0xffe, | |
47 | MLX4_CMD_RUN_FW = 0xff6, | |
48 | MLX4_CMD_MOD_STAT_CFG = 0x34, | |
49 | MLX4_CMD_QUERY_DEV_CAP = 0x3, | |
50 | MLX4_CMD_QUERY_FW = 0x4, | |
51 | MLX4_CMD_ENABLE_LAM = 0xff8, | |
52 | MLX4_CMD_DISABLE_LAM = 0xff7, | |
53 | MLX4_CMD_QUERY_DDR = 0x5, | |
54 | MLX4_CMD_QUERY_ADAPTER = 0x6, | |
55 | MLX4_CMD_INIT_HCA = 0x7, | |
56 | MLX4_CMD_CLOSE_HCA = 0x8, | |
57 | MLX4_CMD_INIT_PORT = 0x9, | |
58 | MLX4_CMD_CLOSE_PORT = 0xa, | |
59 | MLX4_CMD_QUERY_HCA = 0xb, | |
5ae2a7a8 | 60 | MLX4_CMD_QUERY_PORT = 0x43, |
27bf91d6 | 61 | MLX4_CMD_SENSE_PORT = 0x4d, |
e7c1c2c4 | 62 | MLX4_CMD_HW_HEALTH_CHECK = 0x50, |
225c7b1f | 63 | MLX4_CMD_SET_PORT = 0xc, |
d0d68b86 | 64 | MLX4_CMD_SET_NODE = 0x5a, |
623ed84b | 65 | MLX4_CMD_QUERY_FUNC = 0x56, |
225c7b1f RD |
66 | MLX4_CMD_ACCESS_DDR = 0x2e, |
67 | MLX4_CMD_MAP_ICM = 0xffa, | |
68 | MLX4_CMD_UNMAP_ICM = 0xff9, | |
69 | MLX4_CMD_MAP_ICM_AUX = 0xffc, | |
70 | MLX4_CMD_UNMAP_ICM_AUX = 0xffb, | |
71 | MLX4_CMD_SET_ICM_SIZE = 0xffd, | |
adbc7ac5 | 72 | MLX4_CMD_ACCESS_REG = 0x3b, |
7e95bb99 | 73 | MLX4_CMD_ALLOCATE_VPP = 0x80, |
1c29146d | 74 | MLX4_CMD_SET_VPORT_QOS = 0x81, |
adbc7ac5 | 75 | |
623ed84b JM |
76 | /*master notify fw on finish for slave's flr*/ |
77 | MLX4_CMD_INFORM_FLR_DONE = 0x5b, | |
59e14e32 | 78 | MLX4_CMD_VIRT_PORT_MAP = 0x5c, |
fe6f700d | 79 | MLX4_CMD_GET_OP_REQ = 0x59, |
225c7b1f RD |
80 | |
81 | /* TPT commands */ | |
82 | MLX4_CMD_SW2HW_MPT = 0xd, | |
83 | MLX4_CMD_QUERY_MPT = 0xe, | |
84 | MLX4_CMD_HW2SW_MPT = 0xf, | |
85 | MLX4_CMD_READ_MTT = 0x10, | |
86 | MLX4_CMD_WRITE_MTT = 0x11, | |
87 | MLX4_CMD_SYNC_TPT = 0x2f, | |
88 | ||
89 | /* EQ commands */ | |
90 | MLX4_CMD_MAP_EQ = 0x12, | |
91 | MLX4_CMD_SW2HW_EQ = 0x13, | |
92 | MLX4_CMD_HW2SW_EQ = 0x14, | |
93 | MLX4_CMD_QUERY_EQ = 0x15, | |
94 | ||
95 | /* CQ commands */ | |
96 | MLX4_CMD_SW2HW_CQ = 0x16, | |
97 | MLX4_CMD_HW2SW_CQ = 0x17, | |
98 | MLX4_CMD_QUERY_CQ = 0x18, | |
3fdcb97f | 99 | MLX4_CMD_MODIFY_CQ = 0x2c, |
225c7b1f RD |
100 | |
101 | /* SRQ commands */ | |
102 | MLX4_CMD_SW2HW_SRQ = 0x35, | |
103 | MLX4_CMD_HW2SW_SRQ = 0x36, | |
104 | MLX4_CMD_QUERY_SRQ = 0x37, | |
105 | MLX4_CMD_ARM_SRQ = 0x40, | |
106 | ||
107 | /* QP/EE commands */ | |
108 | MLX4_CMD_RST2INIT_QP = 0x19, | |
109 | MLX4_CMD_INIT2RTR_QP = 0x1a, | |
110 | MLX4_CMD_RTR2RTS_QP = 0x1b, | |
111 | MLX4_CMD_RTS2RTS_QP = 0x1c, | |
112 | MLX4_CMD_SQERR2RTS_QP = 0x1d, | |
113 | MLX4_CMD_2ERR_QP = 0x1e, | |
114 | MLX4_CMD_RTS2SQD_QP = 0x1f, | |
115 | MLX4_CMD_SQD2SQD_QP = 0x38, | |
116 | MLX4_CMD_SQD2RTS_QP = 0x20, | |
117 | MLX4_CMD_2RST_QP = 0x21, | |
118 | MLX4_CMD_QUERY_QP = 0x22, | |
119 | MLX4_CMD_INIT2INIT_QP = 0x2d, | |
120 | MLX4_CMD_SUSPEND_QP = 0x32, | |
121 | MLX4_CMD_UNSUSPEND_QP = 0x33, | |
b01978ca | 122 | MLX4_CMD_UPDATE_QP = 0x61, |
225c7b1f RD |
123 | /* special QP and management commands */ |
124 | MLX4_CMD_CONF_SPECIAL_QP = 0x23, | |
125 | MLX4_CMD_MAD_IFC = 0x24, | |
114840c3 | 126 | MLX4_CMD_MAD_DEMUX = 0x203, |
225c7b1f RD |
127 | |
128 | /* multicast commands */ | |
129 | MLX4_CMD_READ_MCG = 0x25, | |
130 | MLX4_CMD_WRITE_MCG = 0x26, | |
131 | MLX4_CMD_MGID_HASH = 0x27, | |
132 | ||
133 | /* miscellaneous commands */ | |
134 | MLX4_CMD_DIAG_RPRT = 0x30, | |
135 | MLX4_CMD_NOP = 0x31, | |
d18f141a | 136 | MLX4_CMD_CONFIG_DEV = 0x3a, |
623ed84b JM |
137 | MLX4_CMD_ACCESS_MEM = 0x2e, |
138 | MLX4_CMD_SET_VEP = 0x52, | |
139 | ||
140 | /* Ethernet specific commands */ | |
141 | MLX4_CMD_SET_VLAN_FLTR = 0x47, | |
142 | MLX4_CMD_SET_MCAST_FLTR = 0x48, | |
143 | MLX4_CMD_DUMP_ETH_STATS = 0x49, | |
144 | ||
145 | /* Communication channel commands */ | |
146 | MLX4_CMD_ARM_COMM_CHANNEL = 0x57, | |
147 | MLX4_CMD_GEN_EQE = 0x58, | |
148 | ||
149 | /* virtual commands */ | |
150 | MLX4_CMD_ALLOC_RES = 0xf00, | |
151 | MLX4_CMD_FREE_RES = 0xf01, | |
152 | MLX4_CMD_MCAST_ATTACH = 0xf05, | |
153 | MLX4_CMD_UCAST_ATTACH = 0xf06, | |
154 | MLX4_CMD_PROMISC = 0xf08, | |
155 | MLX4_CMD_QUERY_FUNC_CAP = 0xf0a, | |
156 | MLX4_CMD_QP_ATTACH = 0xf0b, | |
225c7b1f RD |
157 | |
158 | /* debug commands */ | |
159 | MLX4_CMD_QUERY_DEBUG_MSG = 0x2a, | |
160 | MLX4_CMD_SET_DEBUG_MSG = 0x2b, | |
f2a3f6a3 OG |
161 | |
162 | /* statistics commands */ | |
163 | MLX4_CMD_QUERY_IF_STAT = 0X54, | |
623ed84b | 164 | MLX4_CMD_SET_IF_STAT = 0X55, |
e5395e92 | 165 | |
8fcfb4db HHZ |
166 | /* register/delete flow steering network rules */ |
167 | MLX4_QP_FLOW_STEERING_ATTACH = 0x65, | |
168 | MLX4_QP_FLOW_STEERING_DETACH = 0x66, | |
4de65803 | 169 | MLX4_FLOW_STEERING_IB_UC_QP_RANGE = 0x64, |
d237baa1 SM |
170 | |
171 | /* Update and read QCN parameters */ | |
172 | MLX4_CMD_CONGESTION_CTRL_OPCODE = 0x68, | |
225c7b1f RD |
173 | }; |
174 | ||
175 | enum { | |
5a031086 JM |
176 | MLX4_CMD_TIME_CLASS_A = 60000, |
177 | MLX4_CMD_TIME_CLASS_B = 60000, | |
178 | MLX4_CMD_TIME_CLASS_C = 60000, | |
225c7b1f RD |
179 | }; |
180 | ||
59e14e32 MS |
181 | enum { |
182 | /* virtual to physical port mapping opcode modifiers */ | |
183 | MLX4_GET_PORT_VIRT2PHY = 0x0, | |
184 | MLX4_SET_PORT_VIRT2PHY = 0x1, | |
185 | }; | |
186 | ||
225c7b1f | 187 | enum { |
623ed84b JM |
188 | MLX4_MAILBOX_SIZE = 4096, |
189 | MLX4_ACCESS_MEM_ALIGN = 256, | |
225c7b1f RD |
190 | }; |
191 | ||
2a2336f8 | 192 | enum { |
a130b590 IS |
193 | /* Set port opcode modifiers */ |
194 | MLX4_SET_PORT_IB_OPCODE = 0x0, | |
195 | MLX4_SET_PORT_ETH_OPCODE = 0x1, | |
51af33cf | 196 | MLX4_SET_PORT_BEACON_OPCODE = 0x4, |
a130b590 IS |
197 | }; |
198 | ||
199 | enum { | |
200 | /* Set port Ethernet input modifiers */ | |
2a2336f8 YP |
201 | MLX4_SET_PORT_GENERAL = 0x0, |
202 | MLX4_SET_PORT_RQP_CALC = 0x1, | |
203 | MLX4_SET_PORT_MAC_TABLE = 0x2, | |
204 | MLX4_SET_PORT_VLAN_TABLE = 0x3, | |
205 | MLX4_SET_PORT_PRIO_MAP = 0x4, | |
96dfa684 | 206 | MLX4_SET_PORT_GID_TABLE = 0x5, |
5930e8d0 OG |
207 | MLX4_SET_PORT_PRIO2TC = 0x8, |
208 | MLX4_SET_PORT_SCHEDULER = 0x9, | |
7e57b85c MS |
209 | MLX4_SET_PORT_VXLAN = 0xB, |
210 | MLX4_SET_PORT_ROCE_ADDR = 0xD | |
2a2336f8 YP |
211 | }; |
212 | ||
114840c3 JM |
213 | enum { |
214 | MLX4_CMD_MAD_DEMUX_CONFIG = 0, | |
215 | MLX4_CMD_MAD_DEMUX_QUERY_STATE = 1, | |
216 | MLX4_CMD_MAD_DEMUX_QUERY_RESTR = 2, /* Query mad demux restrictions */ | |
217 | }; | |
218 | ||
f9baff50 JM |
219 | enum { |
220 | MLX4_CMD_WRAPPED, | |
221 | MLX4_CMD_NATIVE | |
222 | }; | |
223 | ||
d475c95b MB |
224 | /* |
225 | * MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP - | |
226 | * Receive checksum value is reported in CQE also for non TCP/UDP packets. | |
227 | * | |
228 | * MLX4_RX_CSUM_MODE_L4 - | |
229 | * L4_CSUM bit in CQE, which indicates whether or not L4 checksum | |
230 | * was validated correctly, is supported. | |
231 | * | |
232 | * MLX4_RX_CSUM_MODE_IP_OK_IP_NON_TCP_UDP - | |
233 | * IP_OK CQE's field is supported also for non TCP/UDP IP packets. | |
234 | * | |
235 | * MLX4_RX_CSUM_MODE_MULTI_VLAN - | |
236 | * Receive Checksum offload is supported for packets with more than 2 vlan headers. | |
237 | */ | |
238 | enum mlx4_rx_csum_mode { | |
239 | MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP = 1UL << 0, | |
240 | MLX4_RX_CSUM_MODE_L4 = 1UL << 1, | |
241 | MLX4_RX_CSUM_MODE_IP_OK_IP_NON_TCP_UDP = 1UL << 2, | |
242 | MLX4_RX_CSUM_MODE_MULTI_VLAN = 1UL << 3 | |
243 | }; | |
244 | ||
245 | struct mlx4_config_dev_params { | |
246 | u16 vxlan_udp_dport; | |
247 | u8 rx_csum_flags_port_1; | |
248 | u8 rx_csum_flags_port_2; | |
249 | }; | |
250 | ||
d237baa1 SM |
251 | enum mlx4_en_congestion_control_algorithm { |
252 | MLX4_CTRL_ALGO_802_1_QAU_REACTION_POINT = 0, | |
253 | }; | |
254 | ||
255 | enum mlx4_en_congestion_control_opmod { | |
256 | MLX4_CONGESTION_CONTROL_GET_PARAMS, | |
257 | MLX4_CONGESTION_CONTROL_GET_STATISTICS, | |
258 | MLX4_CONGESTION_CONTROL_SET_PARAMS = 4, | |
259 | }; | |
260 | ||
225c7b1f RD |
261 | struct mlx4_dev; |
262 | ||
263 | struct mlx4_cmd_mailbox { | |
264 | void *buf; | |
265 | dma_addr_t dma; | |
266 | }; | |
267 | ||
268 | int __mlx4_cmd(struct mlx4_dev *dev, u64 in_param, u64 *out_param, | |
269 | int out_is_imm, u32 in_modifier, u8 op_modifier, | |
f9baff50 | 270 | u16 op, unsigned long timeout, int native); |
225c7b1f RD |
271 | |
272 | /* Invoke a command with no output parameter */ | |
273 | static inline int mlx4_cmd(struct mlx4_dev *dev, u64 in_param, u32 in_modifier, | |
f9baff50 JM |
274 | u8 op_modifier, u16 op, unsigned long timeout, |
275 | int native) | |
225c7b1f RD |
276 | { |
277 | return __mlx4_cmd(dev, in_param, NULL, 0, in_modifier, | |
f9baff50 | 278 | op_modifier, op, timeout, native); |
225c7b1f RD |
279 | } |
280 | ||
281 | /* Invoke a command with an output mailbox */ | |
282 | static inline int mlx4_cmd_box(struct mlx4_dev *dev, u64 in_param, u64 out_param, | |
283 | u32 in_modifier, u8 op_modifier, u16 op, | |
f9baff50 | 284 | unsigned long timeout, int native) |
225c7b1f RD |
285 | { |
286 | return __mlx4_cmd(dev, in_param, &out_param, 0, in_modifier, | |
f9baff50 | 287 | op_modifier, op, timeout, native); |
225c7b1f RD |
288 | } |
289 | ||
290 | /* | |
291 | * Invoke a command with an immediate output parameter (and copy the | |
292 | * output into the caller's out_param pointer after the command | |
293 | * executes). | |
294 | */ | |
295 | static inline int mlx4_cmd_imm(struct mlx4_dev *dev, u64 in_param, u64 *out_param, | |
296 | u32 in_modifier, u8 op_modifier, u16 op, | |
f9baff50 | 297 | unsigned long timeout, int native) |
225c7b1f RD |
298 | { |
299 | return __mlx4_cmd(dev, in_param, out_param, 1, in_modifier, | |
f9baff50 | 300 | op_modifier, op, timeout, native); |
225c7b1f RD |
301 | } |
302 | ||
303 | struct mlx4_cmd_mailbox *mlx4_alloc_cmd_mailbox(struct mlx4_dev *dev); | |
304 | void mlx4_free_cmd_mailbox(struct mlx4_dev *dev, struct mlx4_cmd_mailbox *mailbox); | |
305 | ||
9616982f EBE |
306 | int mlx4_get_counter_stats(struct mlx4_dev *dev, int counter_index, |
307 | struct mlx4_counter *counter_stats, int reset); | |
62a89055 EBE |
308 | int mlx4_get_vf_stats(struct mlx4_dev *dev, int port, int vf_idx, |
309 | struct ifla_vf_stats *vf_stats); | |
623ed84b | 310 | u32 mlx4_comm_get_version(void); |
745d8ae4 | 311 | int mlx4_set_vf_mac(struct mlx4_dev *dev, int port, int vf, u8 *mac); |
b42959dc MS |
312 | int mlx4_set_vf_vlan(struct mlx4_dev *dev, int port, int vf, u16 vlan, |
313 | u8 qos, __be16 proto); | |
cda373f4 IS |
314 | int mlx4_set_vf_rate(struct mlx4_dev *dev, int port, int vf, int min_tx_rate, |
315 | int max_tx_rate); | |
e6b6a231 | 316 | int mlx4_set_vf_spoofchk(struct mlx4_dev *dev, int port, int vf, bool setting); |
2cccb9e4 | 317 | int mlx4_get_vf_config(struct mlx4_dev *dev, int port, int vf, struct ifla_vf_info *ivf); |
948e306d | 318 | int mlx4_set_vf_link_state(struct mlx4_dev *dev, int port, int vf, int link_state); |
d475c95b MB |
319 | int mlx4_config_dev_retrieval(struct mlx4_dev *dev, |
320 | struct mlx4_config_dev_params *params); | |
f5aef5aa | 321 | void mlx4_cmd_wake_completions(struct mlx4_dev *dev); |
55ad3592 | 322 | void mlx4_report_internal_err_comm_event(struct mlx4_dev *dev); |
5ea8bbfc JM |
323 | /* |
324 | * mlx4_get_slave_default_vlan - | |
325 | * return true if VST ( default vlan) | |
326 | * if VST, will return vlan & qos (if not NULL) | |
327 | */ | |
328 | bool mlx4_get_slave_default_vlan(struct mlx4_dev *dev, int port, int slave, | |
329 | u16 *vlan, u8 *qos); | |
623ed84b | 330 | |
ab9c17a0 | 331 | #define MLX4_COMM_GET_IF_REV(cmd_chan_ver) (u8)((cmd_chan_ver) >> 8) |
55ad3592 | 332 | #define COMM_CHAN_EVENT_INTERNAL_ERR (1 << 17) |
ab9c17a0 | 333 | |
225c7b1f | 334 | #endif /* MLX4_CMD_H */ |