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1/*
2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX4_CQ_H
34#define MLX4_CQ_H
35
36#include <linux/types.h>
37
38#include <linux/mlx4/device.h>
39#include <linux/mlx4/doorbell.h>
40
41struct mlx4_cqe {
42 __be32 my_qpn;
43 __be32 immed_rss_invalid;
44 __be32 g_mlpath_rqpn;
45 u8 sl;
46 u8 reserved1;
47 __be16 rlid;
8ff095ec 48 __be32 ipoib_status;
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49 __be32 byte_cnt;
50 __be16 wqe_index;
51 __be16 checksum;
8ff095ec 52 u8 reserved2[3];
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53 u8 owner_sr_opcode;
54};
55
56struct mlx4_err_cqe {
57 __be32 my_qpn;
58 u32 reserved1[5];
59 __be16 wqe_index;
60 u8 vendor_err_syndrome;
61 u8 syndrome;
62 u8 reserved2[3];
63 u8 owner_sr_opcode;
64};
65
66enum {
67 MLX4_CQE_OWNER_MASK = 0x80,
68 MLX4_CQE_IS_SEND_MASK = 0x40,
69 MLX4_CQE_OPCODE_MASK = 0x1f
70};
71
72enum {
73 MLX4_CQE_SYNDROME_LOCAL_LENGTH_ERR = 0x01,
74 MLX4_CQE_SYNDROME_LOCAL_QP_OP_ERR = 0x02,
75 MLX4_CQE_SYNDROME_LOCAL_PROT_ERR = 0x04,
76 MLX4_CQE_SYNDROME_WR_FLUSH_ERR = 0x05,
77 MLX4_CQE_SYNDROME_MW_BIND_ERR = 0x06,
78 MLX4_CQE_SYNDROME_BAD_RESP_ERR = 0x10,
79 MLX4_CQE_SYNDROME_LOCAL_ACCESS_ERR = 0x11,
80 MLX4_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR = 0x12,
81 MLX4_CQE_SYNDROME_REMOTE_ACCESS_ERR = 0x13,
82 MLX4_CQE_SYNDROME_REMOTE_OP_ERR = 0x14,
83 MLX4_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR = 0x15,
84 MLX4_CQE_SYNDROME_RNR_RETRY_EXC_ERR = 0x16,
85 MLX4_CQE_SYNDROME_REMOTE_ABORTED_ERR = 0x22,
86};
87
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88enum {
89 MLX4_CQE_IPOIB_STATUS_IPV4 = 1 << 22,
90 MLX4_CQE_IPOIB_STATUS_IPV4F = 1 << 23,
91 MLX4_CQE_IPOIB_STATUS_IPV6 = 1 << 24,
92 MLX4_CQE_IPOIB_STATUS_IPV4OPT = 1 << 25,
93 MLX4_CQE_IPOIB_STATUS_TCP = 1 << 26,
94 MLX4_CQE_IPOIB_STATUS_UDP = 1 << 27,
95 MLX4_CQE_IPOIB_STATUS_IPOK = 1 << 28,
96};
97
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98static inline void mlx4_cq_arm(struct mlx4_cq *cq, u32 cmd,
99 void __iomem *uar_page,
100 spinlock_t *doorbell_lock)
101{
102 __be32 doorbell[2];
103 u32 sn;
104 u32 ci;
105
106 sn = cq->arm_sn & 3;
107 ci = cq->cons_index & 0xffffff;
108
109 *cq->arm_db = cpu_to_be32(sn << 28 | cmd | ci);
110
111 /*
112 * Make sure that the doorbell record in host memory is
113 * written before ringing the doorbell via PCI MMIO.
114 */
115 wmb();
116
117 doorbell[0] = cpu_to_be32(sn << 28 | cmd | cq->cqn);
118 doorbell[1] = cpu_to_be32(ci);
119
120 mlx4_write64(doorbell, uar_page + MLX4_CQ_DOORBELL, doorbell_lock);
121}
122
123static inline void mlx4_cq_set_ci(struct mlx4_cq *cq)
124{
125 *cq->set_ci_db = cpu_to_be32(cq->cons_index & 0xffffff);
126}
127
128enum {
129 MLX4_CQ_DB_REQ_NOT_SOL = 1 << 24,
130 MLX4_CQ_DB_REQ_NOT = 2 << 24
131};
132
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133int mlx4_cq_modify(struct mlx4_dev *dev, struct mlx4_cq *cq,
134 u16 count, u16 period);
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135int mlx4_cq_resize(struct mlx4_dev *dev, struct mlx4_cq *cq,
136 int entries, struct mlx4_mtt *mtt);
3fdcb97f 137
225c7b1f 138#endif /* MLX4_CQ_H */