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225c7b1f RD |
1 | /* |
2 | * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef MLX4_DEVICE_H | |
34 | #define MLX4_DEVICE_H | |
35 | ||
36 | #include <linux/pci.h> | |
37 | #include <linux/completion.h> | |
38 | #include <linux/radix-tree.h> | |
39 | ||
60063497 | 40 | #include <linux/atomic.h> |
225c7b1f | 41 | |
0b7ca5a9 YP |
42 | #define MAX_MSIX_P_PORT 17 |
43 | #define MAX_MSIX 64 | |
44 | #define MSIX_LEGACY_SZ 4 | |
45 | #define MIN_MSIX_P_PORT 5 | |
46 | ||
225c7b1f RD |
47 | enum { |
48 | MLX4_FLAG_MSI_X = 1 << 0, | |
5ae2a7a8 | 49 | MLX4_FLAG_OLD_PORT_CMDS = 1 << 1, |
623ed84b JM |
50 | MLX4_FLAG_MASTER = 1 << 2, |
51 | MLX4_FLAG_SLAVE = 1 << 3, | |
52 | MLX4_FLAG_SRIOV = 1 << 4, | |
225c7b1f RD |
53 | }; |
54 | ||
55 | enum { | |
56 | MLX4_MAX_PORTS = 2 | |
57 | }; | |
58 | ||
cd9281d8 JM |
59 | enum { |
60 | MLX4_BOARD_ID_LEN = 64 | |
61 | }; | |
62 | ||
623ed84b JM |
63 | enum { |
64 | MLX4_MAX_NUM_PF = 16, | |
65 | MLX4_MAX_NUM_VF = 64, | |
66 | MLX4_MFUNC_MAX = 80, | |
3fc929e2 | 67 | MLX4_MAX_EQ_NUM = 1024, |
623ed84b JM |
68 | MLX4_MFUNC_EQ_NUM = 4, |
69 | MLX4_MFUNC_MAX_EQES = 8, | |
70 | MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1) | |
71 | }; | |
72 | ||
225c7b1f | 73 | enum { |
52eafc68 OG |
74 | MLX4_DEV_CAP_FLAG_RC = 1LL << 0, |
75 | MLX4_DEV_CAP_FLAG_UC = 1LL << 1, | |
76 | MLX4_DEV_CAP_FLAG_UD = 1LL << 2, | |
012a8ff5 | 77 | MLX4_DEV_CAP_FLAG_XRC = 1LL << 3, |
52eafc68 OG |
78 | MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6, |
79 | MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7, | |
80 | MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8, | |
81 | MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9, | |
82 | MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12, | |
83 | MLX4_DEV_CAP_FLAG_BLH = 1LL << 15, | |
84 | MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16, | |
85 | MLX4_DEV_CAP_FLAG_APM = 1LL << 17, | |
86 | MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18, | |
87 | MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19, | |
88 | MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20, | |
89 | MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21, | |
ccf86321 OG |
90 | MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30, |
91 | MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32, | |
f3a9d1f2 | 92 | MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34, |
559a9f1d OD |
93 | MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37, |
94 | MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38, | |
ccf86321 OG |
95 | MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40, |
96 | MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41, | |
f2a3f6a3 | 97 | MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42, |
58a60168 | 98 | MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48, |
00f5ce99 JM |
99 | MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55, |
100 | MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59, | |
225c7b1f RD |
101 | }; |
102 | ||
b3416f44 SP |
103 | enum { |
104 | MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0, | |
105 | MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1, | |
106 | MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2 | |
107 | }; | |
108 | ||
97285b78 MA |
109 | #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) |
110 | ||
95d04f07 RD |
111 | enum { |
112 | MLX4_BMME_FLAG_LOCAL_INV = 1 << 6, | |
113 | MLX4_BMME_FLAG_REMOTE_INV = 1 << 7, | |
114 | MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9, | |
115 | MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10, | |
116 | MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11, | |
117 | }; | |
118 | ||
225c7b1f RD |
119 | enum mlx4_event { |
120 | MLX4_EVENT_TYPE_COMP = 0x00, | |
121 | MLX4_EVENT_TYPE_PATH_MIG = 0x01, | |
122 | MLX4_EVENT_TYPE_COMM_EST = 0x02, | |
123 | MLX4_EVENT_TYPE_SQ_DRAINED = 0x03, | |
124 | MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13, | |
125 | MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14, | |
126 | MLX4_EVENT_TYPE_CQ_ERROR = 0x04, | |
127 | MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, | |
128 | MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06, | |
129 | MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07, | |
130 | MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, | |
131 | MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, | |
132 | MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, | |
133 | MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08, | |
134 | MLX4_EVENT_TYPE_PORT_CHANGE = 0x09, | |
135 | MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f, | |
136 | MLX4_EVENT_TYPE_ECC_DETECT = 0x0e, | |
623ed84b JM |
137 | MLX4_EVENT_TYPE_CMD = 0x0a, |
138 | MLX4_EVENT_TYPE_VEP_UPDATE = 0x19, | |
139 | MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18, | |
5984be90 | 140 | MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b, |
623ed84b | 141 | MLX4_EVENT_TYPE_FLR_EVENT = 0x1c, |
00f5ce99 | 142 | MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d, |
623ed84b | 143 | MLX4_EVENT_TYPE_NONE = 0xff, |
225c7b1f RD |
144 | }; |
145 | ||
146 | enum { | |
147 | MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1, | |
148 | MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4 | |
149 | }; | |
150 | ||
5984be90 JM |
151 | enum { |
152 | MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0, | |
153 | }; | |
154 | ||
225c7b1f RD |
155 | enum { |
156 | MLX4_PERM_LOCAL_READ = 1 << 10, | |
157 | MLX4_PERM_LOCAL_WRITE = 1 << 11, | |
158 | MLX4_PERM_REMOTE_READ = 1 << 12, | |
159 | MLX4_PERM_REMOTE_WRITE = 1 << 13, | |
160 | MLX4_PERM_ATOMIC = 1 << 14 | |
161 | }; | |
162 | ||
163 | enum { | |
164 | MLX4_OPCODE_NOP = 0x00, | |
165 | MLX4_OPCODE_SEND_INVAL = 0x01, | |
166 | MLX4_OPCODE_RDMA_WRITE = 0x08, | |
167 | MLX4_OPCODE_RDMA_WRITE_IMM = 0x09, | |
168 | MLX4_OPCODE_SEND = 0x0a, | |
169 | MLX4_OPCODE_SEND_IMM = 0x0b, | |
170 | MLX4_OPCODE_LSO = 0x0e, | |
171 | MLX4_OPCODE_RDMA_READ = 0x10, | |
172 | MLX4_OPCODE_ATOMIC_CS = 0x11, | |
173 | MLX4_OPCODE_ATOMIC_FA = 0x12, | |
6fa8f719 VS |
174 | MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14, |
175 | MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15, | |
225c7b1f RD |
176 | MLX4_OPCODE_BIND_MW = 0x18, |
177 | MLX4_OPCODE_FMR = 0x19, | |
178 | MLX4_OPCODE_LOCAL_INVAL = 0x1b, | |
179 | MLX4_OPCODE_CONFIG_CMD = 0x1f, | |
180 | ||
181 | MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, | |
182 | MLX4_RECV_OPCODE_SEND = 0x01, | |
183 | MLX4_RECV_OPCODE_SEND_IMM = 0x02, | |
184 | MLX4_RECV_OPCODE_SEND_INVAL = 0x03, | |
185 | ||
186 | MLX4_CQE_OPCODE_ERROR = 0x1e, | |
187 | MLX4_CQE_OPCODE_RESIZE = 0x16, | |
188 | }; | |
189 | ||
190 | enum { | |
191 | MLX4_STAT_RATE_OFFSET = 5 | |
192 | }; | |
193 | ||
da995a8a | 194 | enum mlx4_protocol { |
0345584e YP |
195 | MLX4_PROT_IB_IPV6 = 0, |
196 | MLX4_PROT_ETH, | |
197 | MLX4_PROT_IB_IPV4, | |
198 | MLX4_PROT_FCOE | |
da995a8a AS |
199 | }; |
200 | ||
29bdc883 VS |
201 | enum { |
202 | MLX4_MTT_FLAG_PRESENT = 1 | |
203 | }; | |
204 | ||
93fc9e1b YP |
205 | enum mlx4_qp_region { |
206 | MLX4_QP_REGION_FW = 0, | |
207 | MLX4_QP_REGION_ETH_ADDR, | |
208 | MLX4_QP_REGION_FC_ADDR, | |
209 | MLX4_QP_REGION_FC_EXCH, | |
210 | MLX4_NUM_QP_REGION | |
211 | }; | |
212 | ||
7ff93f8b | 213 | enum mlx4_port_type { |
623ed84b | 214 | MLX4_PORT_TYPE_NONE = 0, |
27bf91d6 YP |
215 | MLX4_PORT_TYPE_IB = 1, |
216 | MLX4_PORT_TYPE_ETH = 2, | |
217 | MLX4_PORT_TYPE_AUTO = 3 | |
7ff93f8b YP |
218 | }; |
219 | ||
2a2336f8 YP |
220 | enum mlx4_special_vlan_idx { |
221 | MLX4_NO_VLAN_IDX = 0, | |
222 | MLX4_VLAN_MISS_IDX, | |
223 | MLX4_VLAN_REGULAR | |
224 | }; | |
225 | ||
0345584e YP |
226 | enum mlx4_steer_type { |
227 | MLX4_MC_STEER = 0, | |
228 | MLX4_UC_STEER, | |
229 | MLX4_NUM_STEERS | |
230 | }; | |
231 | ||
93fc9e1b YP |
232 | enum { |
233 | MLX4_NUM_FEXCH = 64 * 1024, | |
234 | }; | |
235 | ||
5a0fd094 EC |
236 | enum { |
237 | MLX4_MAX_FAST_REG_PAGES = 511, | |
238 | }; | |
239 | ||
00f5ce99 JM |
240 | enum { |
241 | MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14, | |
242 | MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15, | |
243 | MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16, | |
244 | }; | |
245 | ||
246 | /* Port mgmt change event handling */ | |
247 | enum { | |
248 | MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0, | |
249 | MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1, | |
250 | MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2, | |
251 | MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3, | |
252 | MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4, | |
253 | }; | |
254 | ||
255 | #define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \ | |
256 | MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK) | |
257 | ||
ea54b10c JM |
258 | static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor) |
259 | { | |
260 | return (major << 32) | (minor << 16) | subminor; | |
261 | } | |
262 | ||
3fc929e2 MA |
263 | struct mlx4_phys_caps { |
264 | u32 num_phys_eqs; | |
265 | }; | |
266 | ||
225c7b1f RD |
267 | struct mlx4_caps { |
268 | u64 fw_ver; | |
623ed84b | 269 | u32 function; |
225c7b1f | 270 | int num_ports; |
5ae2a7a8 | 271 | int vl_cap[MLX4_MAX_PORTS + 1]; |
b79acb49 | 272 | int ib_mtu_cap[MLX4_MAX_PORTS + 1]; |
9a5aa622 | 273 | __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1]; |
b79acb49 YP |
274 | u64 def_mac[MLX4_MAX_PORTS + 1]; |
275 | int eth_mtu_cap[MLX4_MAX_PORTS + 1]; | |
5ae2a7a8 RD |
276 | int gid_table_len[MLX4_MAX_PORTS + 1]; |
277 | int pkey_table_len[MLX4_MAX_PORTS + 1]; | |
7699517d YP |
278 | int trans_type[MLX4_MAX_PORTS + 1]; |
279 | int vendor_oui[MLX4_MAX_PORTS + 1]; | |
280 | int wavelength[MLX4_MAX_PORTS + 1]; | |
281 | u64 trans_code[MLX4_MAX_PORTS + 1]; | |
225c7b1f RD |
282 | int local_ca_ack_delay; |
283 | int num_uars; | |
f5311ac1 | 284 | u32 uar_page_size; |
225c7b1f RD |
285 | int bf_reg_size; |
286 | int bf_regs_per_page; | |
287 | int max_sq_sg; | |
288 | int max_rq_sg; | |
289 | int num_qps; | |
290 | int max_wqes; | |
291 | int max_sq_desc_sz; | |
292 | int max_rq_desc_sz; | |
293 | int max_qp_init_rdma; | |
294 | int max_qp_dest_rdma; | |
225c7b1f RD |
295 | int sqp_start; |
296 | int num_srqs; | |
297 | int max_srq_wqes; | |
298 | int max_srq_sge; | |
299 | int reserved_srqs; | |
300 | int num_cqs; | |
301 | int max_cqes; | |
302 | int reserved_cqs; | |
303 | int num_eqs; | |
304 | int reserved_eqs; | |
b8dd786f | 305 | int num_comp_vectors; |
0b7ca5a9 | 306 | int comp_pool; |
225c7b1f | 307 | int num_mpts; |
a5bbe892 | 308 | int max_fmr_maps; |
2b8fb286 | 309 | int num_mtts; |
225c7b1f RD |
310 | int fmr_reserved_mtts; |
311 | int reserved_mtts; | |
312 | int reserved_mrws; | |
313 | int reserved_uars; | |
314 | int num_mgms; | |
315 | int num_amgms; | |
316 | int reserved_mcgs; | |
317 | int num_qp_per_mgm; | |
318 | int num_pds; | |
319 | int reserved_pds; | |
012a8ff5 SH |
320 | int max_xrcds; |
321 | int reserved_xrcds; | |
225c7b1f | 322 | int mtt_entry_sz; |
149983af | 323 | u32 max_msg_sz; |
225c7b1f | 324 | u32 page_size_cap; |
52eafc68 | 325 | u64 flags; |
b3416f44 | 326 | u64 flags2; |
95d04f07 RD |
327 | u32 bmme_flags; |
328 | u32 reserved_lkey; | |
225c7b1f | 329 | u16 stat_rate_support; |
5ae2a7a8 | 330 | u8 port_width_cap[MLX4_MAX_PORTS + 1]; |
b832be1e | 331 | int max_gso_sz; |
b3416f44 | 332 | int max_rss_tbl_sz; |
93fc9e1b YP |
333 | int reserved_qps_cnt[MLX4_NUM_QP_REGION]; |
334 | int reserved_qps; | |
335 | int reserved_qps_base[MLX4_NUM_QP_REGION]; | |
336 | int log_num_macs; | |
337 | int log_num_vlans; | |
338 | int log_num_prios; | |
7ff93f8b YP |
339 | enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1]; |
340 | u8 supported_type[MLX4_MAX_PORTS + 1]; | |
8d0fc7b6 YP |
341 | u8 suggested_type[MLX4_MAX_PORTS + 1]; |
342 | u8 default_sense[MLX4_MAX_PORTS + 1]; | |
65dab25d | 343 | u32 port_mask[MLX4_MAX_PORTS + 1]; |
27bf91d6 | 344 | enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1]; |
f2a3f6a3 | 345 | u32 max_counters; |
096335b3 | 346 | u8 port_ib_mtu[MLX4_MAX_PORTS + 1]; |
225c7b1f RD |
347 | }; |
348 | ||
349 | struct mlx4_buf_list { | |
350 | void *buf; | |
351 | dma_addr_t map; | |
352 | }; | |
353 | ||
354 | struct mlx4_buf { | |
b57aacfa RD |
355 | struct mlx4_buf_list direct; |
356 | struct mlx4_buf_list *page_list; | |
225c7b1f RD |
357 | int nbufs; |
358 | int npages; | |
359 | int page_shift; | |
360 | }; | |
361 | ||
362 | struct mlx4_mtt { | |
2b8fb286 | 363 | u32 offset; |
225c7b1f RD |
364 | int order; |
365 | int page_shift; | |
366 | }; | |
367 | ||
6296883c YP |
368 | enum { |
369 | MLX4_DB_PER_PAGE = PAGE_SIZE / 4 | |
370 | }; | |
371 | ||
372 | struct mlx4_db_pgdir { | |
373 | struct list_head list; | |
374 | DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE); | |
375 | DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2); | |
376 | unsigned long *bits[2]; | |
377 | __be32 *db_page; | |
378 | dma_addr_t db_dma; | |
379 | }; | |
380 | ||
381 | struct mlx4_ib_user_db_page; | |
382 | ||
383 | struct mlx4_db { | |
384 | __be32 *db; | |
385 | union { | |
386 | struct mlx4_db_pgdir *pgdir; | |
387 | struct mlx4_ib_user_db_page *user_page; | |
388 | } u; | |
389 | dma_addr_t dma; | |
390 | int index; | |
391 | int order; | |
392 | }; | |
393 | ||
38ae6a53 YP |
394 | struct mlx4_hwq_resources { |
395 | struct mlx4_db db; | |
396 | struct mlx4_mtt mtt; | |
397 | struct mlx4_buf buf; | |
398 | }; | |
399 | ||
225c7b1f RD |
400 | struct mlx4_mr { |
401 | struct mlx4_mtt mtt; | |
402 | u64 iova; | |
403 | u64 size; | |
404 | u32 key; | |
405 | u32 pd; | |
406 | u32 access; | |
407 | int enabled; | |
408 | }; | |
409 | ||
8ad11fb6 JM |
410 | struct mlx4_fmr { |
411 | struct mlx4_mr mr; | |
412 | struct mlx4_mpt_entry *mpt; | |
413 | __be64 *mtts; | |
414 | dma_addr_t dma_handle; | |
415 | int max_pages; | |
416 | int max_maps; | |
417 | int maps; | |
418 | u8 page_shift; | |
419 | }; | |
420 | ||
225c7b1f RD |
421 | struct mlx4_uar { |
422 | unsigned long pfn; | |
423 | int index; | |
c1b43dca EC |
424 | struct list_head bf_list; |
425 | unsigned free_bf_bmap; | |
426 | void __iomem *map; | |
427 | void __iomem *bf_map; | |
428 | }; | |
429 | ||
430 | struct mlx4_bf { | |
431 | unsigned long offset; | |
432 | int buf_size; | |
433 | struct mlx4_uar *uar; | |
434 | void __iomem *reg; | |
225c7b1f RD |
435 | }; |
436 | ||
437 | struct mlx4_cq { | |
438 | void (*comp) (struct mlx4_cq *); | |
439 | void (*event) (struct mlx4_cq *, enum mlx4_event); | |
440 | ||
441 | struct mlx4_uar *uar; | |
442 | ||
443 | u32 cons_index; | |
444 | ||
445 | __be32 *set_ci_db; | |
446 | __be32 *arm_db; | |
447 | int arm_sn; | |
448 | ||
449 | int cqn; | |
b8dd786f | 450 | unsigned vector; |
225c7b1f RD |
451 | |
452 | atomic_t refcount; | |
453 | struct completion free; | |
454 | }; | |
455 | ||
456 | struct mlx4_qp { | |
457 | void (*event) (struct mlx4_qp *, enum mlx4_event); | |
458 | ||
459 | int qpn; | |
460 | ||
461 | atomic_t refcount; | |
462 | struct completion free; | |
463 | }; | |
464 | ||
465 | struct mlx4_srq { | |
466 | void (*event) (struct mlx4_srq *, enum mlx4_event); | |
467 | ||
468 | int srqn; | |
469 | int max; | |
470 | int max_gs; | |
471 | int wqe_shift; | |
472 | ||
473 | atomic_t refcount; | |
474 | struct completion free; | |
475 | }; | |
476 | ||
477 | struct mlx4_av { | |
478 | __be32 port_pd; | |
479 | u8 reserved1; | |
480 | u8 g_slid; | |
481 | __be16 dlid; | |
482 | u8 reserved2; | |
483 | u8 gid_index; | |
484 | u8 stat_rate; | |
485 | u8 hop_limit; | |
486 | __be32 sl_tclass_flowlabel; | |
487 | u8 dgid[16]; | |
488 | }; | |
489 | ||
fa417f7b EC |
490 | struct mlx4_eth_av { |
491 | __be32 port_pd; | |
492 | u8 reserved1; | |
493 | u8 smac_idx; | |
494 | u16 reserved2; | |
495 | u8 reserved3; | |
496 | u8 gid_index; | |
497 | u8 stat_rate; | |
498 | u8 hop_limit; | |
499 | __be32 sl_tclass_flowlabel; | |
500 | u8 dgid[16]; | |
501 | u32 reserved4[2]; | |
502 | __be16 vlan; | |
503 | u8 mac[6]; | |
504 | }; | |
505 | ||
506 | union mlx4_ext_av { | |
507 | struct mlx4_av ib; | |
508 | struct mlx4_eth_av eth; | |
509 | }; | |
510 | ||
f2a3f6a3 OG |
511 | struct mlx4_counter { |
512 | u8 reserved1[3]; | |
513 | u8 counter_mode; | |
514 | __be32 num_ifc; | |
515 | u32 reserved2[2]; | |
516 | __be64 rx_frames; | |
517 | __be64 rx_bytes; | |
518 | __be64 tx_frames; | |
519 | __be64 tx_bytes; | |
520 | }; | |
521 | ||
225c7b1f RD |
522 | struct mlx4_dev { |
523 | struct pci_dev *pdev; | |
524 | unsigned long flags; | |
623ed84b | 525 | unsigned long num_slaves; |
225c7b1f | 526 | struct mlx4_caps caps; |
3fc929e2 | 527 | struct mlx4_phys_caps phys_caps; |
225c7b1f | 528 | struct radix_tree_root qp_table_tree; |
725c8999 | 529 | u8 rev_id; |
cd9281d8 | 530 | char board_id[MLX4_BOARD_ID_LEN]; |
ab9c17a0 | 531 | int num_vfs; |
225c7b1f RD |
532 | }; |
533 | ||
00f5ce99 JM |
534 | struct mlx4_eqe { |
535 | u8 reserved1; | |
536 | u8 type; | |
537 | u8 reserved2; | |
538 | u8 subtype; | |
539 | union { | |
540 | u32 raw[6]; | |
541 | struct { | |
542 | __be32 cqn; | |
543 | } __packed comp; | |
544 | struct { | |
545 | u16 reserved1; | |
546 | __be16 token; | |
547 | u32 reserved2; | |
548 | u8 reserved3[3]; | |
549 | u8 status; | |
550 | __be64 out_param; | |
551 | } __packed cmd; | |
552 | struct { | |
553 | __be32 qpn; | |
554 | } __packed qp; | |
555 | struct { | |
556 | __be32 srqn; | |
557 | } __packed srq; | |
558 | struct { | |
559 | __be32 cqn; | |
560 | u32 reserved1; | |
561 | u8 reserved2[3]; | |
562 | u8 syndrome; | |
563 | } __packed cq_err; | |
564 | struct { | |
565 | u32 reserved1[2]; | |
566 | __be32 port; | |
567 | } __packed port_change; | |
568 | struct { | |
569 | #define COMM_CHANNEL_BIT_ARRAY_SIZE 4 | |
570 | u32 reserved; | |
571 | u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE]; | |
572 | } __packed comm_channel_arm; | |
573 | struct { | |
574 | u8 port; | |
575 | u8 reserved[3]; | |
576 | __be64 mac; | |
577 | } __packed mac_update; | |
578 | struct { | |
579 | __be32 slave_id; | |
580 | } __packed flr_event; | |
581 | struct { | |
582 | __be16 current_temperature; | |
583 | __be16 warning_threshold; | |
584 | } __packed warming; | |
585 | struct { | |
586 | u8 reserved[3]; | |
587 | u8 port; | |
588 | union { | |
589 | struct { | |
590 | __be16 mstr_sm_lid; | |
591 | __be16 port_lid; | |
592 | __be32 changed_attr; | |
593 | u8 reserved[3]; | |
594 | u8 mstr_sm_sl; | |
595 | __be64 gid_prefix; | |
596 | } __packed port_info; | |
597 | struct { | |
598 | __be32 block_ptr; | |
599 | __be32 tbl_entries_mask; | |
600 | } __packed tbl_change_info; | |
601 | } params; | |
602 | } __packed port_mgmt_change; | |
603 | } event; | |
604 | u8 slave_id; | |
605 | u8 reserved3[2]; | |
606 | u8 owner; | |
607 | } __packed; | |
608 | ||
225c7b1f RD |
609 | struct mlx4_init_port_param { |
610 | int set_guid0; | |
611 | int set_node_guid; | |
612 | int set_si_guid; | |
613 | u16 mtu; | |
614 | int port_width_cap; | |
615 | u16 vl_cap; | |
616 | u16 max_gid; | |
617 | u16 max_pkey; | |
618 | u64 guid0; | |
619 | u64 node_guid; | |
620 | u64 si_guid; | |
621 | }; | |
622 | ||
7ff93f8b YP |
623 | #define mlx4_foreach_port(port, dev, type) \ |
624 | for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ | |
65dab25d | 625 | if ((type) == (dev)->caps.port_mask[(port)]) |
7ff93f8b | 626 | |
65dab25d JM |
627 | #define mlx4_foreach_ib_transport_port(port, dev) \ |
628 | for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ | |
629 | if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \ | |
630 | ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE)) | |
623ed84b | 631 | |
752a50ca JM |
632 | #define MLX4_INVALID_SLAVE_ID 0xFF |
633 | ||
00f5ce99 JM |
634 | void handle_port_mgmt_change_event(struct work_struct *work); |
635 | ||
623ed84b JM |
636 | static inline int mlx4_is_master(struct mlx4_dev *dev) |
637 | { | |
638 | return dev->flags & MLX4_FLAG_MASTER; | |
639 | } | |
640 | ||
641 | static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn) | |
642 | { | |
643 | return (qpn < dev->caps.sqp_start + 8); | |
644 | } | |
fa417f7b | 645 | |
623ed84b JM |
646 | static inline int mlx4_is_mfunc(struct mlx4_dev *dev) |
647 | { | |
648 | return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER); | |
649 | } | |
650 | ||
651 | static inline int mlx4_is_slave(struct mlx4_dev *dev) | |
652 | { | |
653 | return dev->flags & MLX4_FLAG_SLAVE; | |
654 | } | |
fa417f7b | 655 | |
225c7b1f RD |
656 | int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct, |
657 | struct mlx4_buf *buf); | |
658 | void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf); | |
1c69fc2a RD |
659 | static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset) |
660 | { | |
313abe55 | 661 | if (BITS_PER_LONG == 64 || buf->nbufs == 1) |
b57aacfa | 662 | return buf->direct.buf + offset; |
1c69fc2a | 663 | else |
b57aacfa | 664 | return buf->page_list[offset >> PAGE_SHIFT].buf + |
1c69fc2a RD |
665 | (offset & (PAGE_SIZE - 1)); |
666 | } | |
225c7b1f RD |
667 | |
668 | int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn); | |
669 | void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn); | |
012a8ff5 SH |
670 | int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn); |
671 | void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn); | |
225c7b1f RD |
672 | |
673 | int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar); | |
674 | void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar); | |
c1b43dca EC |
675 | int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf); |
676 | void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf); | |
225c7b1f RD |
677 | |
678 | int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift, | |
679 | struct mlx4_mtt *mtt); | |
680 | void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt); | |
681 | u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt); | |
682 | ||
683 | int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access, | |
684 | int npages, int page_shift, struct mlx4_mr *mr); | |
685 | void mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr); | |
686 | int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr); | |
687 | int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, | |
688 | int start_index, int npages, u64 *page_list); | |
689 | int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, | |
690 | struct mlx4_buf *buf); | |
691 | ||
6296883c YP |
692 | int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order); |
693 | void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db); | |
694 | ||
38ae6a53 YP |
695 | int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres, |
696 | int size, int max_direct); | |
697 | void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres, | |
698 | int size); | |
699 | ||
225c7b1f | 700 | int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt, |
e463c7b1 | 701 | struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq, |
b8dd786f | 702 | unsigned vector, int collapsed); |
225c7b1f RD |
703 | void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq); |
704 | ||
a3cdcbfa YP |
705 | int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base); |
706 | void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt); | |
707 | ||
708 | int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp); | |
225c7b1f RD |
709 | void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp); |
710 | ||
18abd5ea SH |
711 | int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn, |
712 | struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq); | |
225c7b1f RD |
713 | void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq); |
714 | int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark); | |
65541cb7 | 715 | int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark); |
225c7b1f | 716 | |
5ae2a7a8 | 717 | int mlx4_INIT_PORT(struct mlx4_dev *dev, int port); |
225c7b1f RD |
718 | int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port); |
719 | ||
ffe455ad EE |
720 | int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], |
721 | int block_mcast_loopback, enum mlx4_protocol prot); | |
722 | int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], | |
723 | enum mlx4_protocol prot); | |
521e575b | 724 | int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], |
da995a8a AS |
725 | int block_mcast_loopback, enum mlx4_protocol protocol); |
726 | int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], | |
727 | enum mlx4_protocol protocol); | |
1679200f YP |
728 | int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); |
729 | int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); | |
730 | int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); | |
731 | int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); | |
732 | int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode); | |
733 | ||
ffe455ad EE |
734 | int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac); |
735 | void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac); | |
736 | int mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac); | |
737 | int mlx4_get_eth_qp(struct mlx4_dev *dev, u8 port, u64 mac, int *qpn); | |
738 | void mlx4_put_eth_qp(struct mlx4_dev *dev, u8 port, u64 mac, int qpn); | |
93ece0c1 | 739 | void mlx4_set_stats_bitmap(struct mlx4_dev *dev, u64 *stats_bitmap); |
9a9a232a YP |
740 | int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu, |
741 | u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx); | |
742 | int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn, | |
743 | u8 promisc); | |
e5395e92 AV |
744 | int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc); |
745 | int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw, | |
746 | u8 *pg, u16 *ratelimit); | |
4c3eb3ca | 747 | int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx); |
2a2336f8 YP |
748 | int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index); |
749 | void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index); | |
750 | ||
8ad11fb6 JM |
751 | int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list, |
752 | int npages, u64 iova, u32 *lkey, u32 *rkey); | |
753 | int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages, | |
754 | int max_maps, u8 page_shift, struct mlx4_fmr *fmr); | |
755 | int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr); | |
756 | void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr, | |
757 | u32 *lkey, u32 *rkey); | |
758 | int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr); | |
759 | int mlx4_SYNC_TPT(struct mlx4_dev *dev); | |
e7c1c2c4 | 760 | int mlx4_test_interrupts(struct mlx4_dev *dev); |
0b7ca5a9 YP |
761 | int mlx4_assign_eq(struct mlx4_dev *dev, char* name , int* vector); |
762 | void mlx4_release_eq(struct mlx4_dev *dev, int vec); | |
8ad11fb6 | 763 | |
14c07b13 YP |
764 | int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port); |
765 | int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port); | |
766 | ||
f2a3f6a3 OG |
767 | int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx); |
768 | void mlx4_counter_free(struct mlx4_dev *dev, u32 idx); | |
769 | ||
225c7b1f | 770 | #endif /* MLX4_DEVICE_H */ |