[mirror_ubuntu-hirsute-kernel.git] / include / linux / mlx4 / device.h

/*
 * Copyright (c) 2006, 2007 Cisco Systems, Inc.  All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *	- Redistributions of source code must retain the above
 *	  copyright notice, this list of conditions and the following
 *	  disclaimer.
 *
 *	- Redistributions in binary form must reproduce the above
 *	  copyright notice, this list of conditions and the following
 *	  disclaimer in the documentation and/or other materials
 *	  provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#ifndef MLX4_DEVICE_H
#define MLX4_DEVICE_H

#include <linux/pci.h>
#include <linux/completion.h>
#include <linux/radix-tree.h>

#include <asm/atomic.h>

enum {
	MLX4_FLAG_MSI_X		= 1 << 0,
	MLX4_FLAG_OLD_PORT_CMDS	= 1 << 1,
};

enum {
	MLX4_MAX_PORTS		= 2
};

enum {
	MLX4_BOARD_ID_LEN = 64
};

enum {
	MLX4_DEV_CAP_FLAG_RC		= 1 <<  0,
	MLX4_DEV_CAP_FLAG_UC		= 1 <<  1,
	MLX4_DEV_CAP_FLAG_UD		= 1 <<  2,
	MLX4_DEV_CAP_FLAG_SRQ		= 1 <<  6,
	MLX4_DEV_CAP_FLAG_IPOIB_CSUM	= 1 <<  7,
	MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR	= 1 <<  8,
	MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR	= 1 <<  9,
	MLX4_DEV_CAP_FLAG_MEM_WINDOW	= 1 << 16,
	MLX4_DEV_CAP_FLAG_APM		= 1 << 17,
	MLX4_DEV_CAP_FLAG_ATOMIC	= 1 << 18,
	MLX4_DEV_CAP_FLAG_RAW_MCAST	= 1 << 19,
	MLX4_DEV_CAP_FLAG_UD_AV_PORT	= 1 << 20,
	MLX4_DEV_CAP_FLAG_UD_MCAST	= 1 << 21
};

enum {
	MLX4_BMME_FLAG_LOCAL_INV	= 1 <<  6,
	MLX4_BMME_FLAG_REMOTE_INV	= 1 <<  7,
	MLX4_BMME_FLAG_TYPE_2_WIN	= 1 <<  9,
	MLX4_BMME_FLAG_RESERVED_LKEY	= 1 << 10,
	MLX4_BMME_FLAG_FAST_REG_WR	= 1 << 11,
};

enum mlx4_event {
	MLX4_EVENT_TYPE_COMP		   = 0x00,
	MLX4_EVENT_TYPE_PATH_MIG	   = 0x01,
	MLX4_EVENT_TYPE_COMM_EST	   = 0x02,
	MLX4_EVENT_TYPE_SQ_DRAINED	   = 0x03,
	MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE	   = 0x13,
	MLX4_EVENT_TYPE_SRQ_LIMIT	   = 0x14,
	MLX4_EVENT_TYPE_CQ_ERROR	   = 0x04,
	MLX4_EVENT_TYPE_WQ_CATAS_ERROR	   = 0x05,
	MLX4_EVENT_TYPE_EEC_CATAS_ERROR	   = 0x06,
	MLX4_EVENT_TYPE_PATH_MIG_FAILED	   = 0x07,
	MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
	MLX4_EVENT_TYPE_WQ_ACCESS_ERROR	   = 0x11,
	MLX4_EVENT_TYPE_SRQ_CATAS_ERROR	   = 0x12,
	MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR  = 0x08,
	MLX4_EVENT_TYPE_PORT_CHANGE	   = 0x09,
	MLX4_EVENT_TYPE_EQ_OVERFLOW	   = 0x0f,
	MLX4_EVENT_TYPE_ECC_DETECT	   = 0x0e,
	MLX4_EVENT_TYPE_CMD		   = 0x0a
};

enum {
	MLX4_PORT_CHANGE_SUBTYPE_DOWN	= 1,
	MLX4_PORT_CHANGE_SUBTYPE_ACTIVE	= 4
};

enum {
	MLX4_PERM_LOCAL_READ	= 1 << 10,
	MLX4_PERM_LOCAL_WRITE	= 1 << 11,
	MLX4_PERM_REMOTE_READ	= 1 << 12,
	MLX4_PERM_REMOTE_WRITE	= 1 << 13,
	MLX4_PERM_ATOMIC	= 1 << 14
};

enum {
	MLX4_OPCODE_NOP			= 0x00,
	MLX4_OPCODE_SEND_INVAL		= 0x01,
	MLX4_OPCODE_RDMA_WRITE		= 0x08,
	MLX4_OPCODE_RDMA_WRITE_IMM	= 0x09,
	MLX4_OPCODE_SEND		= 0x0a,
	MLX4_OPCODE_SEND_IMM		= 0x0b,
	MLX4_OPCODE_LSO			= 0x0e,
	MLX4_OPCODE_RDMA_READ		= 0x10,
	MLX4_OPCODE_ATOMIC_CS		= 0x11,
	MLX4_OPCODE_ATOMIC_FA		= 0x12,
	MLX4_OPCODE_ATOMIC_MASK_CS	= 0x14,
	MLX4_OPCODE_ATOMIC_MASK_FA	= 0x15,
	MLX4_OPCODE_BIND_MW		= 0x18,
	MLX4_OPCODE_FMR			= 0x19,
	MLX4_OPCODE_LOCAL_INVAL		= 0x1b,
	MLX4_OPCODE_CONFIG_CMD		= 0x1f,

	MLX4_RECV_OPCODE_RDMA_WRITE_IMM	= 0x00,
	MLX4_RECV_OPCODE_SEND		= 0x01,
	MLX4_RECV_OPCODE_SEND_IMM	= 0x02,
	MLX4_RECV_OPCODE_SEND_INVAL	= 0x03,

	MLX4_CQE_OPCODE_ERROR		= 0x1e,
	MLX4_CQE_OPCODE_RESIZE		= 0x16,
};

enum {
	MLX4_STAT_RATE_OFFSET	= 5
};

enum {
	MLX4_MTT_FLAG_PRESENT		= 1
};

enum mlx4_qp_region {
	MLX4_QP_REGION_FW = 0,
	MLX4_QP_REGION_ETH_ADDR,
	MLX4_QP_REGION_FC_ADDR,
	MLX4_QP_REGION_FC_EXCH,
	MLX4_NUM_QP_REGION
};

enum mlx4_special_vlan_idx {
	MLX4_NO_VLAN_IDX        = 0,
	MLX4_VLAN_MISS_IDX,
	MLX4_VLAN_REGULAR
};

enum {
	MLX4_NUM_FEXCH          = 64 * 1024,
};

static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
{
	return (major << 32) | (minor << 16) | subminor;
}

struct mlx4_caps {
	u64			fw_ver;
	int			num_ports;
	int			vl_cap[MLX4_MAX_PORTS + 1];
	int			ib_mtu_cap[MLX4_MAX_PORTS + 1];
	u64			def_mac[MLX4_MAX_PORTS + 1];
	int			eth_mtu_cap[MLX4_MAX_PORTS + 1];
	int			gid_table_len[MLX4_MAX_PORTS + 1];
	int			pkey_table_len[MLX4_MAX_PORTS + 1];
	int			local_ca_ack_delay;
	int			num_uars;
	int			bf_reg_size;
	int			bf_regs_per_page;
	int			max_sq_sg;
	int			max_rq_sg;
	int			num_qps;
	int			max_wqes;
	int			max_sq_desc_sz;
	int			max_rq_desc_sz;
	int			max_qp_init_rdma;
	int			max_qp_dest_rdma;
	int			sqp_start;
	int			num_srqs;
	int			max_srq_wqes;
	int			max_srq_sge;
	int			reserved_srqs;
	int			num_cqs;
	int			max_cqes;
	int			reserved_cqs;
	int			num_eqs;
	int			reserved_eqs;
	int			num_mpts;
	int			num_mtt_segs;
	int			fmr_reserved_mtts;
	int			reserved_mtts;
	int			reserved_mrws;
	int			reserved_uars;
	int			num_mgms;
	int			num_amgms;
	int			reserved_mcgs;
	int			num_qp_per_mgm;
	int			num_pds;
	int			reserved_pds;
	int			mtt_entry_sz;
	u32			max_msg_sz;
	u32			page_size_cap;
	u32			flags;
	u32			bmme_flags;
	u32			reserved_lkey;
	u16			stat_rate_support;
	u8			port_width_cap[MLX4_MAX_PORTS + 1];
	int			max_gso_sz;
	int                     reserved_qps_cnt[MLX4_NUM_QP_REGION];
	int			reserved_qps;
	int                     reserved_qps_base[MLX4_NUM_QP_REGION];
	int                     log_num_macs;
	int                     log_num_vlans;
	int                     log_num_prios;
};

struct mlx4_buf_list {
	void		       *buf;
	dma_addr_t		map;
};

struct mlx4_buf {
	struct mlx4_buf_list	direct;
	struct mlx4_buf_list   *page_list;
	int			nbufs;
	int			npages;
	int			page_shift;
};

struct mlx4_mtt {
	u32			first_seg;
	int			order;
	int			page_shift;
};

enum {
	MLX4_DB_PER_PAGE = PAGE_SIZE / 4
};

struct mlx4_db_pgdir {
	struct list_head	list;
	DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
	DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
	unsigned long	       *bits[2];
	__be32		       *db_page;
	dma_addr_t		db_dma;
};

struct mlx4_ib_user_db_page;

struct mlx4_db {
	__be32			*db;
	union {
		struct mlx4_db_pgdir		*pgdir;
		struct mlx4_ib_user_db_page	*user_page;
	}			u;
	dma_addr_t		dma;
	int			index;
	int			order;
};

struct mlx4_hwq_resources {
	struct mlx4_db		db;
	struct mlx4_mtt		mtt;
	struct mlx4_buf		buf;
};

struct mlx4_mr {
	struct mlx4_mtt		mtt;
	u64			iova;
	u64			size;
	u32			key;
	u32			pd;
	u32			access;
	int			enabled;
};

struct mlx4_fmr {
	struct mlx4_mr		mr;
	struct mlx4_mpt_entry  *mpt;
	__be64		       *mtts;
	dma_addr_t		dma_handle;
	int			max_pages;
	int			max_maps;
	int			maps;
	u8			page_shift;
};

struct mlx4_uar {
	unsigned long		pfn;
	int			index;
};

struct mlx4_cq {
	void (*comp)		(struct mlx4_cq *);
	void (*event)		(struct mlx4_cq *, enum mlx4_event);

	struct mlx4_uar	       *uar;

	u32			cons_index;

	__be32		       *set_ci_db;
	__be32		       *arm_db;
	int			arm_sn;

	int			cqn;

	atomic_t		refcount;
	struct completion	free;
};

struct mlx4_qp {
	void (*event)		(struct mlx4_qp *, enum mlx4_event);

	int			qpn;

	atomic_t		refcount;
	struct completion	free;
};

struct mlx4_srq {
	void (*event)		(struct mlx4_srq *, enum mlx4_event);

	int			srqn;
	int			max;
	int			max_gs;
	int			wqe_shift;

	atomic_t		refcount;
	struct completion	free;
};

struct mlx4_av {
	__be32			port_pd;
	u8			reserved1;
	u8			g_slid;
	__be16			dlid;
	u8			reserved2;
	u8			gid_index;
	u8			stat_rate;
	u8			hop_limit;
	__be32			sl_tclass_flowlabel;
	u8			dgid[16];
};

struct mlx4_dev {
	struct pci_dev	       *pdev;
	unsigned long		flags;
	struct mlx4_caps	caps;
	struct radix_tree_root	qp_table_tree;
	u32			rev_id;
	char			board_id[MLX4_BOARD_ID_LEN];
};

struct mlx4_init_port_param {
	int			set_guid0;
	int			set_node_guid;
	int			set_si_guid;
	u16			mtu;
	int			port_width_cap;
	u16			vl_cap;
	u16			max_gid;
	u16			max_pkey;
	u64			guid0;
	u64			node_guid;
	u64			si_guid;
};

int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
		   struct mlx4_buf *buf);
void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
{
	if (BITS_PER_LONG == 64 || buf->nbufs == 1)
		return buf->direct.buf + offset;
	else
		return buf->page_list[offset >> PAGE_SHIFT].buf +
			(offset & (PAGE_SIZE - 1));
}

int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);

int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);

int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
		  struct mlx4_mtt *mtt);
void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);

int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
		  int npages, int page_shift, struct mlx4_mr *mr);
void mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
		   int start_index, int npages, u64 *page_list);
int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
		       struct mlx4_buf *buf);

int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order);
void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db);

int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres,
		       int size, int max_direct);
void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
		       int size);

int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
		  struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
		  int collapsed);
void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);

int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base);
void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);

int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp);
void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);

int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, struct mlx4_mtt *mtt,
		   u64 db_rec, struct mlx4_srq *srq);
void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);

int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);

int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
			  int block_mcast_loopback);
int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16]);

int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *index);
void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, int index);

int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index);

int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
		      int npages, u64 iova, u32 *lkey, u32 *rkey);
int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
		   int max_maps, u8 page_shift, struct mlx4_fmr *fmr);
int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
		    u32 *lkey, u32 *rkey);
int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
int mlx4_SYNC_TPT(struct mlx4_dev *dev);

#endif /* MLX4_DEVICE_H */
Commit	Line	Data
225c7b1f RD	1	/*
	2	* Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
	3	*
	4	* This software is available to you under a choice of one of two
	5	* licenses. You may choose to be licensed under the terms of the GNU
	6	* General Public License (GPL) Version 2, available from the file
	7	* COPYING in the main directory of this source tree, or the
	8	* OpenIB.org BSD license below:
	9	*
	10	* Redistribution and use in source and binary forms, with or
	11	* without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistributions of source code must retain the above
	15	* copyright notice, this list of conditions and the following
	16	* disclaimer.
	17	*
	18	* - Redistributions in binary form must reproduce the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer in the documentation and/or other materials
	21	* provided with the distribution.
	22	*
	23	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	24	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	25	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	26	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	27	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	28	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	29	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	30	* SOFTWARE.
	31	*/
	32
	33	#ifndef MLX4_DEVICE_H
	34	#define MLX4_DEVICE_H
	35
	36	#include <linux/pci.h>
	37	#include <linux/completion.h>
	38	#include <linux/radix-tree.h>
	39
	40	#include <asm/atomic.h>
	41
	42	enum {
	43	MLX4_FLAG_MSI_X = 1 << 0,
5ae2a7a8	44	MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
225c7b1f RD	45	};
	46
	47	enum {
	48	MLX4_MAX_PORTS = 2
	49	};
	50
cd9281d8 JM	51	enum {
	52	MLX4_BOARD_ID_LEN = 64
	53	};
	54
225c7b1f RD	55	enum {
	56	MLX4_DEV_CAP_FLAG_RC = 1 << 0,
	57	MLX4_DEV_CAP_FLAG_UC = 1 << 1,
	58	MLX4_DEV_CAP_FLAG_UD = 1 << 2,
	59	MLX4_DEV_CAP_FLAG_SRQ = 1 << 6,
	60	MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1 << 7,
	61	MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1 << 8,
	62	MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1 << 9,
	63	MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1 << 16,
	64	MLX4_DEV_CAP_FLAG_APM = 1 << 17,
	65	MLX4_DEV_CAP_FLAG_ATOMIC = 1 << 18,
	66	MLX4_DEV_CAP_FLAG_RAW_MCAST = 1 << 19,
	67	MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1 << 20,
	68	MLX4_DEV_CAP_FLAG_UD_MCAST = 1 << 21
	69	};
	70
95d04f07 RD	71	enum {
	72	MLX4_BMME_FLAG_LOCAL_INV = 1 << 6,
	73	MLX4_BMME_FLAG_REMOTE_INV = 1 << 7,
	74	MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9,
	75	MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10,
	76	MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11,
	77	};
	78
225c7b1f RD	79	enum mlx4_event {
	80	MLX4_EVENT_TYPE_COMP = 0x00,
	81	MLX4_EVENT_TYPE_PATH_MIG = 0x01,
	82	MLX4_EVENT_TYPE_COMM_EST = 0x02,
	83	MLX4_EVENT_TYPE_SQ_DRAINED = 0x03,
	84	MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
	85	MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14,
	86	MLX4_EVENT_TYPE_CQ_ERROR = 0x04,
	87	MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
	88	MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
	89	MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
	90	MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
	91	MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
	92	MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
	93	MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
	94	MLX4_EVENT_TYPE_PORT_CHANGE = 0x09,
	95	MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
	96	MLX4_EVENT_TYPE_ECC_DETECT = 0x0e,
	97	MLX4_EVENT_TYPE_CMD = 0x0a
	98	};
	99
	100	enum {
	101	MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1,
	102	MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
	103	};
	104
	105	enum {
	106	MLX4_PERM_LOCAL_READ = 1 << 10,
	107	MLX4_PERM_LOCAL_WRITE = 1 << 11,
	108	MLX4_PERM_REMOTE_READ = 1 << 12,
	109	MLX4_PERM_REMOTE_WRITE = 1 << 13,
	110	MLX4_PERM_ATOMIC = 1 << 14
	111	};
	112
	113	enum {
	114	MLX4_OPCODE_NOP = 0x00,
	115	MLX4_OPCODE_SEND_INVAL = 0x01,
	116	MLX4_OPCODE_RDMA_WRITE = 0x08,
	117	MLX4_OPCODE_RDMA_WRITE_IMM = 0x09,
	118	MLX4_OPCODE_SEND = 0x0a,
	119	MLX4_OPCODE_SEND_IMM = 0x0b,
	120	MLX4_OPCODE_LSO = 0x0e,
	121	MLX4_OPCODE_RDMA_READ = 0x10,
	122	MLX4_OPCODE_ATOMIC_CS = 0x11,
	123	MLX4_OPCODE_ATOMIC_FA = 0x12,
	124	MLX4_OPCODE_ATOMIC_MASK_CS = 0x14,
	125	MLX4_OPCODE_ATOMIC_MASK_FA = 0x15,
	126	MLX4_OPCODE_BIND_MW = 0x18,
	127	MLX4_OPCODE_FMR = 0x19,
	128	MLX4_OPCODE_LOCAL_INVAL = 0x1b,
	129	MLX4_OPCODE_CONFIG_CMD = 0x1f,
	130
	131	MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
	132	MLX4_RECV_OPCODE_SEND = 0x01,
	133	MLX4_RECV_OPCODE_SEND_IMM = 0x02,
	134	MLX4_RECV_OPCODE_SEND_INVAL = 0x03,
	135
	136	MLX4_CQE_OPCODE_ERROR = 0x1e,
	137	MLX4_CQE_OPCODE_RESIZE = 0x16,
	138	};
	139
	140	enum {
	141	MLX4_STAT_RATE_OFFSET = 5
	142	};
143
29bdc883 VS	144	enum {
	145	MLX4_MTT_FLAG_PRESENT = 1
	146	};
	147
93fc9e1b YP	148	enum mlx4_qp_region {
	149	MLX4_QP_REGION_FW = 0,
	150	MLX4_QP_REGION_ETH_ADDR,
	151	MLX4_QP_REGION_FC_ADDR,
	152	MLX4_QP_REGION_FC_EXCH,
	153	MLX4_NUM_QP_REGION
	154	};
	155
2a2336f8 YP	156	enum mlx4_special_vlan_idx {
	157	MLX4_NO_VLAN_IDX = 0,
	158	MLX4_VLAN_MISS_IDX,
	159	MLX4_VLAN_REGULAR
	160	};
	161
93fc9e1b YP	162	enum {
	163	MLX4_NUM_FEXCH = 64 * 1024,
	164	};
	165
ea54b10c JM	166	static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
	167	{
	168	return (major << 32) \| (minor << 16) \| subminor;
	169	}
	170
225c7b1f RD	171	struct mlx4_caps {
	172	u64 fw_ver;
	173	int num_ports;
5ae2a7a8	174	int vl_cap[MLX4_MAX_PORTS + 1];
b79acb49 YP	175	int ib_mtu_cap[MLX4_MAX_PORTS + 1];
	176	u64 def_mac[MLX4_MAX_PORTS + 1];
	177	int eth_mtu_cap[MLX4_MAX_PORTS + 1];
5ae2a7a8 RD	178	int gid_table_len[MLX4_MAX_PORTS + 1];
5ae2a7a8 RD	179	int pkey_table_len[MLX4_MAX_PORTS + 1];
225c7b1f RD	180	int local_ca_ack_delay;
	181	int num_uars;
	182	int bf_reg_size;
	183	int bf_regs_per_page;
	184	int max_sq_sg;
	185	int max_rq_sg;
	186	int num_qps;
	187	int max_wqes;
	188	int max_sq_desc_sz;
	189	int max_rq_desc_sz;
	190	int max_qp_init_rdma;
	191	int max_qp_dest_rdma;
225c7b1f RD	192	int sqp_start;
	193	int num_srqs;
	194	int max_srq_wqes;
	195	int max_srq_sge;
	196	int reserved_srqs;
	197	int num_cqs;
	198	int max_cqes;
	199	int reserved_cqs;
	200	int num_eqs;
	201	int reserved_eqs;
	202	int num_mpts;
	203	int num_mtt_segs;
	204	int fmr_reserved_mtts;
	205	int reserved_mtts;
	206	int reserved_mrws;
	207	int reserved_uars;
	208	int num_mgms;
	209	int num_amgms;
	210	int reserved_mcgs;
	211	int num_qp_per_mgm;
	212	int num_pds;
	213	int reserved_pds;
	214	int mtt_entry_sz;
149983af	215	u32 max_msg_sz;
225c7b1f RD	216	u32 page_size_cap;
225c7b1f RD	217	u32 flags;
95d04f07 RD	218	u32 bmme_flags;
95d04f07 RD	219	u32 reserved_lkey;
225c7b1f	220	u16 stat_rate_support;
5ae2a7a8	221	u8 port_width_cap[MLX4_MAX_PORTS + 1];
b832be1e	222	int max_gso_sz;
93fc9e1b YP	223	int reserved_qps_cnt[MLX4_NUM_QP_REGION];
	224	int reserved_qps;
	225	int reserved_qps_base[MLX4_NUM_QP_REGION];
	226	int log_num_macs;
	227	int log_num_vlans;
	228	int log_num_prios;
225c7b1f RD	229	};
	230
	231	struct mlx4_buf_list {
	232	void *buf;
	233	dma_addr_t map;
	234	};
	235
	236	struct mlx4_buf {
b57aacfa RD	237	struct mlx4_buf_list direct;
b57aacfa RD	238	struct mlx4_buf_list *page_list;
225c7b1f RD	239	int nbufs;
	240	int npages;
	241	int page_shift;
	242	};
	243
	244	struct mlx4_mtt {
	245	u32 first_seg;
	246	int order;
	247	int page_shift;
	248	};
	249
6296883c YP	250	enum {
	251	MLX4_DB_PER_PAGE = PAGE_SIZE / 4
	252	};
	253
	254	struct mlx4_db_pgdir {
	255	struct list_head list;
	256	DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
	257	DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
	258	unsigned long *bits[2];
	259	__be32 *db_page;
	260	dma_addr_t db_dma;
	261	};
	262
	263	struct mlx4_ib_user_db_page;
	264
	265	struct mlx4_db {
	266	__be32 *db;
	267	union {
	268	struct mlx4_db_pgdir *pgdir;
	269	struct mlx4_ib_user_db_page *user_page;
	270	} u;
	271	dma_addr_t dma;
	272	int index;
	273	int order;
	274	};
	275
38ae6a53 YP	276	struct mlx4_hwq_resources {
	277	struct mlx4_db db;
	278	struct mlx4_mtt mtt;
	279	struct mlx4_buf buf;
	280	};
	281
225c7b1f RD	282	struct mlx4_mr {
	283	struct mlx4_mtt mtt;
	284	u64 iova;
	285	u64 size;
	286	u32 key;
	287	u32 pd;
	288	u32 access;
	289	int enabled;
	290	};
	291
8ad11fb6 JM	292	struct mlx4_fmr {
	293	struct mlx4_mr mr;
	294	struct mlx4_mpt_entry *mpt;
	295	__be64 *mtts;
	296	dma_addr_t dma_handle;
	297	int max_pages;
	298	int max_maps;
	299	int maps;
	300	u8 page_shift;
	301	};
	302
225c7b1f RD	303	struct mlx4_uar {
	304	unsigned long pfn;
	305	int index;
	306	};
	307
	308	struct mlx4_cq {
	309	void (comp) (struct mlx4_cq );
	310	void (event) (struct mlx4_cq , enum mlx4_event);
	311
	312	struct mlx4_uar *uar;
	313
	314	u32 cons_index;
	315
	316	__be32 *set_ci_db;
	317	__be32 *arm_db;
	318	int arm_sn;
	319
	320	int cqn;
	321
	322	atomic_t refcount;
	323	struct completion free;
	324	};
	325
	326	struct mlx4_qp {
	327	void (event) (struct mlx4_qp , enum mlx4_event);
	328
	329	int qpn;
	330
	331	atomic_t refcount;
	332	struct completion free;
	333	};
	334
	335	struct mlx4_srq {
	336	void (event) (struct mlx4_srq , enum mlx4_event);
	337
	338	int srqn;
	339	int max;
	340	int max_gs;
	341	int wqe_shift;
	342
	343	atomic_t refcount;
	344	struct completion free;
	345	};
	346
	347	struct mlx4_av {
	348	__be32 port_pd;
	349	u8 reserved1;
	350	u8 g_slid;
	351	__be16 dlid;
	352	u8 reserved2;
	353	u8 gid_index;
	354	u8 stat_rate;
	355	u8 hop_limit;
	356	__be32 sl_tclass_flowlabel;
	357	u8 dgid[16];
	358	};
	359
	360	struct mlx4_dev {
	361	struct pci_dev *pdev;
	362	unsigned long flags;
	363	struct mlx4_caps caps;
	364	struct radix_tree_root qp_table_tree;
cd9281d8 JM	365	u32 rev_id;
cd9281d8 JM	366	char board_id[MLX4_BOARD_ID_LEN];
225c7b1f RD	367	};
	368
	369	struct mlx4_init_port_param {
	370	int set_guid0;
	371	int set_node_guid;
	372	int set_si_guid;
	373	u16 mtu;
	374	int port_width_cap;
	375	u16 vl_cap;
	376	u16 max_gid;
	377	u16 max_pkey;
	378	u64 guid0;
	379	u64 node_guid;
	380	u64 si_guid;
	381	};
	382
	383	int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
	384	struct mlx4_buf *buf);
	385	void mlx4_buf_free(struct mlx4_dev dev, int size, struct mlx4_buf buf);
1c69fc2a RD	386	static inline void mlx4_buf_offset(struct mlx4_buf buf, int offset)
1c69fc2a RD	387	{
313abe55	388	if (BITS_PER_LONG == 64 \|\| buf->nbufs == 1)
b57aacfa	389	return buf->direct.buf + offset;
1c69fc2a	390	else
b57aacfa	391	return buf->page_list[offset >> PAGE_SHIFT].buf +
1c69fc2a RD	392	(offset & (PAGE_SIZE - 1));
1c69fc2a RD	393	}
225c7b1f RD	394
	395	int mlx4_pd_alloc(struct mlx4_dev dev, u32 pdn);
	396	void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
	397
	398	int mlx4_uar_alloc(struct mlx4_dev dev, struct mlx4_uar uar);
	399	void mlx4_uar_free(struct mlx4_dev dev, struct mlx4_uar uar);
	400
	401	int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
	402	struct mlx4_mtt *mtt);
	403	void mlx4_mtt_cleanup(struct mlx4_dev dev, struct mlx4_mtt mtt);
	404	u64 mlx4_mtt_addr(struct mlx4_dev dev, struct mlx4_mtt mtt);
	405
	406	int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
	407	int npages, int page_shift, struct mlx4_mr *mr);
	408	void mlx4_mr_free(struct mlx4_dev dev, struct mlx4_mr mr);
	409	int mlx4_mr_enable(struct mlx4_dev dev, struct mlx4_mr mr);
	410	int mlx4_write_mtt(struct mlx4_dev dev, struct mlx4_mtt mtt,
	411	int start_index, int npages, u64 *page_list);
	412	int mlx4_buf_write_mtt(struct mlx4_dev dev, struct mlx4_mtt mtt,
	413	struct mlx4_buf *buf);
	414
6296883c YP	415	int mlx4_db_alloc(struct mlx4_dev dev, struct mlx4_db db, int order);
	416	void mlx4_db_free(struct mlx4_dev dev, struct mlx4_db db);
	417
38ae6a53 YP	418	int mlx4_alloc_hwq_res(struct mlx4_dev dev, struct mlx4_hwq_resources wqres,
	419	int size, int max_direct);
	420	void mlx4_free_hwq_res(struct mlx4_dev mdev, struct mlx4_hwq_resources wqres,
	421	int size);
	422
225c7b1f	423	int mlx4_cq_alloc(struct mlx4_dev dev, int nent, struct mlx4_mtt mtt,
e463c7b1 YP	424	struct mlx4_uar uar, u64 db_rec, struct mlx4_cq cq,
e463c7b1 YP	425	int collapsed);
225c7b1f RD	426	void mlx4_cq_free(struct mlx4_dev dev, struct mlx4_cq cq);
225c7b1f RD	427
a3cdcbfa YP	428	int mlx4_qp_reserve_range(struct mlx4_dev dev, int cnt, int align, int base);
	429	void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
	430
	431	int mlx4_qp_alloc(struct mlx4_dev dev, int qpn, struct mlx4_qp qp);
225c7b1f RD	432	void mlx4_qp_free(struct mlx4_dev dev, struct mlx4_qp qp);
	433
	434	int mlx4_srq_alloc(struct mlx4_dev dev, u32 pdn, struct mlx4_mtt mtt,
	435	u64 db_rec, struct mlx4_srq *srq);
	436	void mlx4_srq_free(struct mlx4_dev dev, struct mlx4_srq srq);
	437	int mlx4_srq_arm(struct mlx4_dev dev, struct mlx4_srq srq, int limit_watermark);
65541cb7	438	int mlx4_srq_query(struct mlx4_dev dev, struct mlx4_srq srq, int *limit_watermark);
225c7b1f	439
5ae2a7a8	440	int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
225c7b1f RD	441	int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
225c7b1f RD	442
521e575b RL	443	int mlx4_multicast_attach(struct mlx4_dev dev, struct mlx4_qp qp, u8 gid[16],
521e575b RL	444	int block_mcast_loopback);
225c7b1f RD	445	int mlx4_multicast_detach(struct mlx4_dev dev, struct mlx4_qp qp, u8 gid[16]);
225c7b1f RD	446
2a2336f8 YP	447	int mlx4_register_mac(struct mlx4_dev dev, u8 port, u64 mac, int index);
	448	void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, int index);
	449
	450	int mlx4_register_vlan(struct mlx4_dev dev, u8 port, u16 vlan, int index);
	451	void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index);
	452
8ad11fb6 JM	453	int mlx4_map_phys_fmr(struct mlx4_dev dev, struct mlx4_fmr fmr, u64 *page_list,
	454	int npages, u64 iova, u32 lkey, u32 rkey);
	455	int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
	456	int max_maps, u8 page_shift, struct mlx4_fmr *fmr);
	457	int mlx4_fmr_enable(struct mlx4_dev dev, struct mlx4_fmr fmr);
	458	void mlx4_fmr_unmap(struct mlx4_dev dev, struct mlx4_fmr fmr,
	459	u32 lkey, u32 rkey);
	460	int mlx4_fmr_free(struct mlx4_dev dev, struct mlx4_fmr fmr);
	461	int mlx4_SYNC_TPT(struct mlx4_dev *dev);
	462
225c7b1f	463	#endif /* MLX4_DEVICE_H */