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IB/mlx4: Miscellaneous adjustments for SR-IOV IB support
[mirror_ubuntu-bionic-kernel.git] / include / linux / mlx4 / device.h
CommitLineData
225c7b1f
RD		 1/*
2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX4_DEVICE_H
34#define MLX4_DEVICE_H
35
36#include <linux/pci.h>
37#include <linux/completion.h>
38#include <linux/radix-tree.h>
d9236c3f 39#include <linux/cpu_rmap.h>
225c7b1f 40
60063497 41#include <linux/atomic.h>
225c7b1f 42
0b7ca5a9
YP		 43#define MAX_MSIX_P_PORT 17
44#define MAX_MSIX 64
45#define MSIX_LEGACY_SZ 4
46#define MIN_MSIX_P_PORT 5
47
225c7b1f
RD		 48enum {
49 MLX4_FLAG_MSI_X = 1 << 0,
5ae2a7a8 50 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
623ed84b
JM		 51 MLX4_FLAG_MASTER = 1 << 2,
52 MLX4_FLAG_SLAVE = 1 << 3,
53 MLX4_FLAG_SRIOV = 1 << 4,
225c7b1f
RD		 54};
55
efcd235d
JM		 56enum {
57 MLX4_PORT_CAP_IS_SM = 1 << 1,
58 MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19,
59};
60
225c7b1f 61enum {
fc06573d
JM		 62 MLX4_MAX_PORTS = 2,
63 MLX4_MAX_PORT_PKEYS = 128
225c7b1f
RD		 64};
65
396f2feb
JM		 66/* base qkey for use in sriov tunnel-qp/proxy-qp communication.
67 * These qkeys must not be allowed for general use. This is a 64k range,
68 * and to test for violation, we use the mask (protect against future chg).
69 */
70#define MLX4_RESERVED_QKEY_BASE (0xFFFF0000)
71#define MLX4_RESERVED_QKEY_MASK (0xFFFF0000)
72
cd9281d8
JM		 73enum {
74 MLX4_BOARD_ID_LEN = 64
75};
76
623ed84b
JM		 77enum {
78 MLX4_MAX_NUM_PF = 16,
79 MLX4_MAX_NUM_VF = 64,
80 MLX4_MFUNC_MAX = 80,
3fc929e2 81 MLX4_MAX_EQ_NUM = 1024,
623ed84b
JM		 82 MLX4_MFUNC_EQ_NUM = 4,
83 MLX4_MFUNC_MAX_EQES = 8,
84 MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1)
85};
86
0ff1fb65
HHZ		 87/* Driver supports 3 diffrent device methods to manage traffic steering:
88 * -device managed - High level API for ib and eth flow steering. FW is
89 * managing flow steering tables.
c96d97f4
HHZ		 90 * - B0 steering mode - Common low level API for ib and (if supported) eth.
91 * - A0 steering mode - Limited low level API for eth. In case of IB,
92 * B0 mode is in use.
93 */
94enum {
95 MLX4_STEERING_MODE_A0,
0ff1fb65
HHZ		 96 MLX4_STEERING_MODE_B0,
97 MLX4_STEERING_MODE_DEVICE_MANAGED
c96d97f4
HHZ		 98};
99
100static inline const char *mlx4_steering_mode_str(int steering_mode)
101{
102 switch (steering_mode) {
103 case MLX4_STEERING_MODE_A0:
104 return "A0 steering";
105
106 case MLX4_STEERING_MODE_B0:
107 return "B0 steering";
0ff1fb65
HHZ		 108
109 case MLX4_STEERING_MODE_DEVICE_MANAGED:
110 return "Device managed flow steering";
111
c96d97f4
HHZ		 112 default:
113 return "Unrecognize steering mode";
114 }
115}
116
225c7b1f 117enum {
52eafc68
OG		 118 MLX4_DEV_CAP_FLAG_RC = 1LL << 0,
119 MLX4_DEV_CAP_FLAG_UC = 1LL << 1,
120 MLX4_DEV_CAP_FLAG_UD = 1LL << 2,
012a8ff5 121 MLX4_DEV_CAP_FLAG_XRC = 1LL << 3,
52eafc68
OG		 122 MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6,
123 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7,
124 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
125 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
126 MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12,
127 MLX4_DEV_CAP_FLAG_BLH = 1LL << 15,
128 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16,
129 MLX4_DEV_CAP_FLAG_APM = 1LL << 17,
130 MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
131 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19,
132 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20,
133 MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21,
ccf86321
OG		 134 MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30,
135 MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32,
f3a9d1f2 136 MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34,
559a9f1d
OD		 137 MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37,
138 MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38,
ccf86321
OG		 139 MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40,
140 MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41,
f2a3f6a3 141 MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42,
58a60168 142 MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48,
00f5ce99
JM		 143 MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55,
144 MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59,
225c7b1f
RD		 145};
146
b3416f44
SP		 147enum {
148 MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0,
149 MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1,
0ff1fb65
HHZ		 150 MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2,
151 MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3
b3416f44
SP		 152};
153
97285b78
MA		 154#define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
155
95d04f07
RD		 156enum {
157 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6,
158 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7,
159 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9,
160 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10,
161 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11,
162};
163
225c7b1f
RD		 164enum mlx4_event {
165 MLX4_EVENT_TYPE_COMP = 0x00,
166 MLX4_EVENT_TYPE_PATH_MIG = 0x01,
167 MLX4_EVENT_TYPE_COMM_EST = 0x02,
168 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03,
169 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
170 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14,
171 MLX4_EVENT_TYPE_CQ_ERROR = 0x04,
172 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
173 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
174 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
175 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
176 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
177 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
178 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
179 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09,
180 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
181 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e,
623ed84b
JM		 182 MLX4_EVENT_TYPE_CMD = 0x0a,
183 MLX4_EVENT_TYPE_VEP_UPDATE = 0x19,
184 MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18,
5984be90 185 MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b,
623ed84b 186 MLX4_EVENT_TYPE_FLR_EVENT = 0x1c,
00f5ce99 187 MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d,
623ed84b 188 MLX4_EVENT_TYPE_NONE = 0xff,
225c7b1f
RD		 189};
190
191enum {
192 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1,
193 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
194};
195
5984be90
JM		 196enum {
197 MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0,
198};
199
993c401e
JM		 200enum slave_port_state {
201 SLAVE_PORT_DOWN = 0,
202 SLAVE_PENDING_UP,
203 SLAVE_PORT_UP,
204};
205
206enum slave_port_gen_event {
207 SLAVE_PORT_GEN_EVENT_DOWN = 0,
208 SLAVE_PORT_GEN_EVENT_UP,
209 SLAVE_PORT_GEN_EVENT_NONE,
210};
211
212enum slave_port_state_event {
213 MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN,
214 MLX4_PORT_STATE_DEV_EVENT_PORT_UP,
215 MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID,
216 MLX4_PORT_STATE_IB_EVENT_GID_INVALID,
217};
218
225c7b1f
RD		 219enum {
220 MLX4_PERM_LOCAL_READ = 1 << 10,
221 MLX4_PERM_LOCAL_WRITE = 1 << 11,
222 MLX4_PERM_REMOTE_READ = 1 << 12,
223 MLX4_PERM_REMOTE_WRITE = 1 << 13,
224 MLX4_PERM_ATOMIC = 1 << 14
225};
226
227enum {
228 MLX4_OPCODE_NOP = 0x00,
229 MLX4_OPCODE_SEND_INVAL = 0x01,
230 MLX4_OPCODE_RDMA_WRITE = 0x08,
231 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09,
232 MLX4_OPCODE_SEND = 0x0a,
233 MLX4_OPCODE_SEND_IMM = 0x0b,
234 MLX4_OPCODE_LSO = 0x0e,
235 MLX4_OPCODE_RDMA_READ = 0x10,
236 MLX4_OPCODE_ATOMIC_CS = 0x11,
237 MLX4_OPCODE_ATOMIC_FA = 0x12,
6fa8f719
VS		 238 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14,
239 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15,
225c7b1f
RD		 240 MLX4_OPCODE_BIND_MW = 0x18,
241 MLX4_OPCODE_FMR = 0x19,
242 MLX4_OPCODE_LOCAL_INVAL = 0x1b,
243 MLX4_OPCODE_CONFIG_CMD = 0x1f,
244
245 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
246 MLX4_RECV_OPCODE_SEND = 0x01,
247 MLX4_RECV_OPCODE_SEND_IMM = 0x02,
248 MLX4_RECV_OPCODE_SEND_INVAL = 0x03,
249
250 MLX4_CQE_OPCODE_ERROR = 0x1e,
251 MLX4_CQE_OPCODE_RESIZE = 0x16,
252};
253
254enum {
255 MLX4_STAT_RATE_OFFSET = 5
256};
257
da995a8a 258enum mlx4_protocol {
0345584e
YP		 259 MLX4_PROT_IB_IPV6 = 0,
260 MLX4_PROT_ETH,
261 MLX4_PROT_IB_IPV4,
262 MLX4_PROT_FCOE
da995a8a
AS		 263};
264
29bdc883
VS		 265enum {
266 MLX4_MTT_FLAG_PRESENT = 1
267};
268
93fc9e1b
YP		 269enum mlx4_qp_region {
270 MLX4_QP_REGION_FW = 0,
271 MLX4_QP_REGION_ETH_ADDR,
272 MLX4_QP_REGION_FC_ADDR,
273 MLX4_QP_REGION_FC_EXCH,
274 MLX4_NUM_QP_REGION
275};
276
7ff93f8b 277enum mlx4_port_type {
623ed84b 278 MLX4_PORT_TYPE_NONE = 0,
27bf91d6
YP		 279 MLX4_PORT_TYPE_IB = 1,
280 MLX4_PORT_TYPE_ETH = 2,
281 MLX4_PORT_TYPE_AUTO = 3
7ff93f8b
YP		 282};
283
2a2336f8
YP		 284enum mlx4_special_vlan_idx {
285 MLX4_NO_VLAN_IDX = 0,
286 MLX4_VLAN_MISS_IDX,
287 MLX4_VLAN_REGULAR
288};
289
0345584e
YP		 290enum mlx4_steer_type {
291 MLX4_MC_STEER = 0,
292 MLX4_UC_STEER,
293 MLX4_NUM_STEERS
294};
295
93fc9e1b
YP		 296enum {
297 MLX4_NUM_FEXCH = 64 * 1024,
298};
299
5a0fd094
EC		 300enum {
301 MLX4_MAX_FAST_REG_PAGES = 511,
302};
303
00f5ce99
JM		 304enum {
305 MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14,
306 MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15,
307 MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16,
308};
309
310/* Port mgmt change event handling */
311enum {
312 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0,
313 MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1,
314 MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2,
315 MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3,
316 MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4,
317};
318
319#define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \
320 MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK)
321
ea54b10c
JM		 322static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
323{
324 return (major << 32) | (minor << 16) | subminor;
325}
326
3fc929e2 327struct mlx4_phys_caps {
6634961c
JM		 328 u32 gid_phys_table_len[MLX4_MAX_PORTS + 1];
329 u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1];
3fc929e2
MA		 330 u32 num_phys_eqs;
331};
332
225c7b1f
RD		 333struct mlx4_caps {
334 u64 fw_ver;
623ed84b 335 u32 function;
225c7b1f 336 int num_ports;
5ae2a7a8 337 int vl_cap[MLX4_MAX_PORTS + 1];
b79acb49 338 int ib_mtu_cap[MLX4_MAX_PORTS + 1];
9a5aa622 339 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1];
b79acb49
YP		 340 u64 def_mac[MLX4_MAX_PORTS + 1];
341 int eth_mtu_cap[MLX4_MAX_PORTS + 1];
5ae2a7a8
RD		 342 int gid_table_len[MLX4_MAX_PORTS + 1];
343 int pkey_table_len[MLX4_MAX_PORTS + 1];
7699517d
YP		 344 int trans_type[MLX4_MAX_PORTS + 1];
345 int vendor_oui[MLX4_MAX_PORTS + 1];
346 int wavelength[MLX4_MAX_PORTS + 1];
347 u64 trans_code[MLX4_MAX_PORTS + 1];
225c7b1f
RD		 348 int local_ca_ack_delay;
349 int num_uars;
f5311ac1 350 u32 uar_page_size;
225c7b1f
RD		 351 int bf_reg_size;
352 int bf_regs_per_page;
353 int max_sq_sg;
354 int max_rq_sg;
355 int num_qps;
356 int max_wqes;
357 int max_sq_desc_sz;
358 int max_rq_desc_sz;
359 int max_qp_init_rdma;
360 int max_qp_dest_rdma;
225c7b1f 361 int sqp_start;
396f2feb
JM		 362 u32 base_sqpn;
363 u32 base_tunnel_sqpn;
225c7b1f
RD		 364 int num_srqs;
365 int max_srq_wqes;
366 int max_srq_sge;
367 int reserved_srqs;
368 int num_cqs;
369 int max_cqes;
370 int reserved_cqs;
371 int num_eqs;
372 int reserved_eqs;
b8dd786f 373 int num_comp_vectors;
0b7ca5a9 374 int comp_pool;
225c7b1f 375 int num_mpts;
a5bbe892 376 int max_fmr_maps;
2b8fb286 377 int num_mtts;
225c7b1f
RD		 378 int fmr_reserved_mtts;
379 int reserved_mtts;
380 int reserved_mrws;
381 int reserved_uars;
382 int num_mgms;
383 int num_amgms;
384 int reserved_mcgs;
385 int num_qp_per_mgm;
c96d97f4 386 int steering_mode;
0ff1fb65 387 int fs_log_max_ucast_qp_range_size;
225c7b1f
RD		 388 int num_pds;
389 int reserved_pds;
012a8ff5
SH		 390 int max_xrcds;
391 int reserved_xrcds;
225c7b1f 392 int mtt_entry_sz;
149983af 393 u32 max_msg_sz;
225c7b1f 394 u32 page_size_cap;
52eafc68 395 u64 flags;
b3416f44 396 u64 flags2;
95d04f07
RD		 397 u32 bmme_flags;
398 u32 reserved_lkey;
225c7b1f 399 u16 stat_rate_support;
5ae2a7a8 400 u8 port_width_cap[MLX4_MAX_PORTS + 1];
b832be1e 401 int max_gso_sz;
b3416f44 402 int max_rss_tbl_sz;
93fc9e1b
YP		 403 int reserved_qps_cnt[MLX4_NUM_QP_REGION];
404 int reserved_qps;
405 int reserved_qps_base[MLX4_NUM_QP_REGION];
406 int log_num_macs;
407 int log_num_vlans;
408 int log_num_prios;
7ff93f8b
YP		 409 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
410 u8 supported_type[MLX4_MAX_PORTS + 1];
8d0fc7b6
YP		 411 u8 suggested_type[MLX4_MAX_PORTS + 1];
412 u8 default_sense[MLX4_MAX_PORTS + 1];
65dab25d 413 u32 port_mask[MLX4_MAX_PORTS + 1];
27bf91d6 414 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1];
f2a3f6a3 415 u32 max_counters;
096335b3 416 u8 port_ib_mtu[MLX4_MAX_PORTS + 1];
1ffeb2eb 417 u16 sqp_demux;
225c7b1f
RD		 418};
419
420struct mlx4_buf_list {
421 void *buf;
422 dma_addr_t map;
423};
424
425struct mlx4_buf {
b57aacfa
RD		 426 struct mlx4_buf_list direct;
427 struct mlx4_buf_list *page_list;
225c7b1f
RD		 428 int nbufs;
429 int npages;
430 int page_shift;
431};
432
433struct mlx4_mtt {
2b8fb286 434 u32 offset;
225c7b1f
RD		 435 int order;
436 int page_shift;
437};
438
6296883c
YP		 439enum {
440 MLX4_DB_PER_PAGE = PAGE_SIZE / 4
441};
442
443struct mlx4_db_pgdir {
444 struct list_head list;
445 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
446 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
447 unsigned long *bits[2];
448 __be32 *db_page;
449 dma_addr_t db_dma;
450};
451
452struct mlx4_ib_user_db_page;
453
454struct mlx4_db {
455 __be32 *db;
456 union {
457 struct mlx4_db_pgdir *pgdir;
458 struct mlx4_ib_user_db_page *user_page;
459 } u;
460 dma_addr_t dma;
461 int index;
462 int order;
463};
464
38ae6a53
YP		 465struct mlx4_hwq_resources {
466 struct mlx4_db db;
467 struct mlx4_mtt mtt;
468 struct mlx4_buf buf;
469};
470
225c7b1f
RD		 471struct mlx4_mr {
472 struct mlx4_mtt mtt;
473 u64 iova;
474 u64 size;
475 u32 key;
476 u32 pd;
477 u32 access;
478 int enabled;
479};
480
8ad11fb6
JM		 481struct mlx4_fmr {
482 struct mlx4_mr mr;
483 struct mlx4_mpt_entry *mpt;
484 __be64 *mtts;
485 dma_addr_t dma_handle;
486 int max_pages;
487 int max_maps;
488 int maps;
489 u8 page_shift;
490};
491
225c7b1f
RD		 492struct mlx4_uar {
493 unsigned long pfn;
494 int index;
c1b43dca
EC		 495 struct list_head bf_list;
496 unsigned free_bf_bmap;
497 void __iomem *map;
498 void __iomem *bf_map;
499};
500
501struct mlx4_bf {
502 unsigned long offset;
503 int buf_size;
504 struct mlx4_uar *uar;
505 void __iomem *reg;
225c7b1f
RD		 506};
507
508struct mlx4_cq {
509 void (*comp) (struct mlx4_cq *);
510 void (*event) (struct mlx4_cq *, enum mlx4_event);
511
512 struct mlx4_uar *uar;
513
514 u32 cons_index;
515
516 __be32 *set_ci_db;
517 __be32 *arm_db;
518 int arm_sn;
519
520 int cqn;
b8dd786f 521 unsigned vector;
225c7b1f
RD		 522
523 atomic_t refcount;
524 struct completion free;
525};
526
527struct mlx4_qp {
528 void (*event) (struct mlx4_qp *, enum mlx4_event);
529
530 int qpn;
531
532 atomic_t refcount;
533 struct completion free;
534};
535
536struct mlx4_srq {
537 void (*event) (struct mlx4_srq *, enum mlx4_event);
538
539 int srqn;
540 int max;
541 int max_gs;
542 int wqe_shift;
543
544 atomic_t refcount;
545 struct completion free;
546};
547
548struct mlx4_av {
549 __be32 port_pd;
550 u8 reserved1;
551 u8 g_slid;
552 __be16 dlid;
553 u8 reserved2;
554 u8 gid_index;
555 u8 stat_rate;
556 u8 hop_limit;
557 __be32 sl_tclass_flowlabel;
558 u8 dgid[16];
559};
560
fa417f7b
EC		 561struct mlx4_eth_av {
562 __be32 port_pd;
563 u8 reserved1;
564 u8 smac_idx;
565 u16 reserved2;
566 u8 reserved3;
567 u8 gid_index;
568 u8 stat_rate;
569 u8 hop_limit;
570 __be32 sl_tclass_flowlabel;
571 u8 dgid[16];
572 u32 reserved4[2];
573 __be16 vlan;
574 u8 mac[6];
575};
576
577union mlx4_ext_av {
578 struct mlx4_av ib;
579 struct mlx4_eth_av eth;
580};
581
f2a3f6a3
OG		 582struct mlx4_counter {
583 u8 reserved1[3];
584 u8 counter_mode;
585 __be32 num_ifc;
586 u32 reserved2[2];
587 __be64 rx_frames;
588 __be64 rx_bytes;
589 __be64 tx_frames;
590 __be64 tx_bytes;
591};
592
225c7b1f
RD		 593struct mlx4_dev {
594 struct pci_dev *pdev;
595 unsigned long flags;
623ed84b 596 unsigned long num_slaves;
225c7b1f 597 struct mlx4_caps caps;
3fc929e2 598 struct mlx4_phys_caps phys_caps;
225c7b1f 599 struct radix_tree_root qp_table_tree;
725c8999 600 u8 rev_id;
cd9281d8 601 char board_id[MLX4_BOARD_ID_LEN];
ab9c17a0 602 int num_vfs;
592e49dd
HHZ		 603 u64 regid_promisc_array[MLX4_MAX_PORTS + 1];
604 u64 regid_allmulti_array[MLX4_MAX_PORTS + 1];
225c7b1f
RD		 605};
606
00f5ce99
JM		 607struct mlx4_eqe {
608 u8 reserved1;
609 u8 type;
610 u8 reserved2;
611 u8 subtype;
612 union {
613 u32 raw[6];
614 struct {
615 __be32 cqn;
616 } __packed comp;
617 struct {
618 u16 reserved1;
619 __be16 token;
620 u32 reserved2;
621 u8 reserved3[3];
622 u8 status;
623 __be64 out_param;
624 } __packed cmd;
625 struct {
626 __be32 qpn;
627 } __packed qp;
628 struct {
629 __be32 srqn;
630 } __packed srq;
631 struct {
632 __be32 cqn;
633 u32 reserved1;
634 u8 reserved2[3];
635 u8 syndrome;
636 } __packed cq_err;
637 struct {
638 u32 reserved1[2];
639 __be32 port;
640 } __packed port_change;
641 struct {
642 #define COMM_CHANNEL_BIT_ARRAY_SIZE 4
643 u32 reserved;
644 u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE];
645 } __packed comm_channel_arm;
646 struct {
647 u8 port;
648 u8 reserved[3];
649 __be64 mac;
650 } __packed mac_update;
651 struct {
652 __be32 slave_id;
653 } __packed flr_event;
654 struct {
655 __be16 current_temperature;
656 __be16 warning_threshold;
657 } __packed warming;
658 struct {
659 u8 reserved[3];
660 u8 port;
661 union {
662 struct {
663 __be16 mstr_sm_lid;
664 __be16 port_lid;
665 __be32 changed_attr;
666 u8 reserved[3];
667 u8 mstr_sm_sl;
668 __be64 gid_prefix;
669 } __packed port_info;
670 struct {
671 __be32 block_ptr;
672 __be32 tbl_entries_mask;
673 } __packed tbl_change_info;
674 } params;
675 } __packed port_mgmt_change;
676 } event;
677 u8 slave_id;
678 u8 reserved3[2];
679 u8 owner;
680} __packed;
681
225c7b1f
RD		 682struct mlx4_init_port_param {
683 int set_guid0;
684 int set_node_guid;
685 int set_si_guid;
686 u16 mtu;
687 int port_width_cap;
688 u16 vl_cap;
689 u16 max_gid;
690 u16 max_pkey;
691 u64 guid0;
692 u64 node_guid;
693 u64 si_guid;
694};
695
7ff93f8b
YP		 696#define mlx4_foreach_port(port, dev, type) \
697 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
65dab25d 698 if ((type) == (dev)->caps.port_mask[(port)])
7ff93f8b 699
65dab25d
JM		 700#define mlx4_foreach_ib_transport_port(port, dev) \
701 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
702 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \
703 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
623ed84b 704
752a50ca
JM		 705#define MLX4_INVALID_SLAVE_ID 0xFF
706
00f5ce99
JM		 707void handle_port_mgmt_change_event(struct work_struct *work);
708
2aca1172
JM		 709static inline int mlx4_master_func_num(struct mlx4_dev *dev)
710{
711 return dev->caps.function;
712}
713
623ed84b
JM		 714static inline int mlx4_is_master(struct mlx4_dev *dev)
715{
716 return dev->flags & MLX4_FLAG_MASTER;
717}
718
719static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn)
720{
e2c76824
JM		 721 return (qpn < dev->caps.base_sqpn + 8 +
722 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev));
723}
724
725static inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn)
726{
727 int base = dev->caps.sqp_start + slave * 8;
728
729 if (qpn >= base && qpn < base + 8)
730 return 1;
731
732 return 0;
623ed84b 733}
fa417f7b 734
623ed84b
JM		 735static inline int mlx4_is_mfunc(struct mlx4_dev *dev)
736{
737 return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER);
738}
739
740static inline int mlx4_is_slave(struct mlx4_dev *dev)
741{
742 return dev->flags & MLX4_FLAG_SLAVE;
743}
fa417f7b 744
225c7b1f
RD		 745int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
746 struct mlx4_buf *buf);
747void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
1c69fc2a
RD		 748static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
749{
313abe55 750 if (BITS_PER_LONG == 64 || buf->nbufs == 1)
b57aacfa 751 return buf->direct.buf + offset;
1c69fc2a 752 else
b57aacfa 753 return buf->page_list[offset >> PAGE_SHIFT].buf +
1c69fc2a
RD		 754 (offset & (PAGE_SIZE - 1));
755}
225c7b1f
RD		 756
757int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
758void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
012a8ff5
SH		 759int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
760void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
225c7b1f
RD		 761
762int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
763void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);
c1b43dca
EC		 764int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf);
765void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf);
225c7b1f
RD		 766
767int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
768 struct mlx4_mtt *mtt);
769void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
770u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
771
772int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
773 int npages, int page_shift, struct mlx4_mr *mr);
774void mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
775int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
776int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
777 int start_index, int npages, u64 *page_list);
778int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
779 struct mlx4_buf *buf);
780
6296883c
YP		 781int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order);
782void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db);
783
38ae6a53
YP		 784int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres,
785 int size, int max_direct);
786void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
787 int size);
788
225c7b1f 789int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
e463c7b1 790 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
b8dd786f 791 unsigned vector, int collapsed);
225c7b1f
RD		 792void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);
793
a3cdcbfa
YP		 794int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base);
795void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
796
797int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp);
225c7b1f
RD		 798void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);
799
18abd5ea
SH		 800int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn,
801 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq);
225c7b1f
RD		 802void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
803int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
65541cb7 804int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);
225c7b1f 805
5ae2a7a8 806int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
225c7b1f
RD		 807int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
808
ffe455ad
EE		 809int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
810 int block_mcast_loopback, enum mlx4_protocol prot);
811int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
812 enum mlx4_protocol prot);
521e575b 813int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
0ff1fb65
HHZ		 814 u8 port, int block_mcast_loopback,
815 enum mlx4_protocol protocol, u64 *reg_id);
da995a8a 816int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
0ff1fb65
HHZ		 817 enum mlx4_protocol protocol, u64 reg_id);
818
819enum {
820 MLX4_DOMAIN_UVERBS = 0x1000,
821 MLX4_DOMAIN_ETHTOOL = 0x2000,
822 MLX4_DOMAIN_RFS = 0x3000,
823 MLX4_DOMAIN_NIC = 0x5000,
824};
825
826enum mlx4_net_trans_rule_id {
827 MLX4_NET_TRANS_RULE_ID_ETH = 0,
828 MLX4_NET_TRANS_RULE_ID_IB,
829 MLX4_NET_TRANS_RULE_ID_IPV6,
830 MLX4_NET_TRANS_RULE_ID_IPV4,
831 MLX4_NET_TRANS_RULE_ID_TCP,
832 MLX4_NET_TRANS_RULE_ID_UDP,
833 MLX4_NET_TRANS_RULE_NUM, /* should be last */
834};
835
a8edc3bf
HHZ		 836extern const u16 __sw_id_hw[];
837
7fb40f87
HHZ		 838static inline int map_hw_to_sw_id(u16 header_id)
839{
840
841 int i;
842 for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) {
843 if (header_id == __sw_id_hw[i])
844 return i;
845 }
846 return -EINVAL;
847}
848
0ff1fb65
HHZ		 849enum mlx4_net_trans_promisc_mode {
850 MLX4_FS_PROMISC_NONE = 0,
851 MLX4_FS_PROMISC_UPLINK,
592e49dd 852 /* For future use. Not implemented yet */
0ff1fb65
HHZ		 853 MLX4_FS_PROMISC_FUNCTION_PORT,
854 MLX4_FS_PROMISC_ALL_MULTI,
855};
856
857struct mlx4_spec_eth {
858 u8 dst_mac[6];
859 u8 dst_mac_msk[6];
860 u8 src_mac[6];
861 u8 src_mac_msk[6];
862 u8 ether_type_enable;
863 __be16 ether_type;
864 __be16 vlan_id_msk;
865 __be16 vlan_id;
866};
867
868struct mlx4_spec_tcp_udp {
869 __be16 dst_port;
870 __be16 dst_port_msk;
871 __be16 src_port;
872 __be16 src_port_msk;
873};
874
875struct mlx4_spec_ipv4 {
876 __be32 dst_ip;
877 __be32 dst_ip_msk;
878 __be32 src_ip;
879 __be32 src_ip_msk;
880};
881
882struct mlx4_spec_ib {
883 __be32 r_qpn;
884 __be32 qpn_msk;
885 u8 dst_gid[16];
886 u8 dst_gid_msk[16];
887};
888
889struct mlx4_spec_list {
890 struct list_head list;
891 enum mlx4_net_trans_rule_id id;
892 union {
893 struct mlx4_spec_eth eth;
894 struct mlx4_spec_ib ib;
895 struct mlx4_spec_ipv4 ipv4;
896 struct mlx4_spec_tcp_udp tcp_udp;
897 };
898};
899
900enum mlx4_net_trans_hw_rule_queue {
901 MLX4_NET_TRANS_Q_FIFO,
902 MLX4_NET_TRANS_Q_LIFO,
903};
904
905struct mlx4_net_trans_rule {
906 struct list_head list;
907 enum mlx4_net_trans_hw_rule_queue queue_mode;
908 bool exclusive;
909 bool allow_loopback;
910 enum mlx4_net_trans_promisc_mode promisc_mode;
911 u8 port;
912 u16 priority;
913 u32 qpn;
914};
915
592e49dd
HHZ		 916int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn,
917 enum mlx4_net_trans_promisc_mode mode);
918int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port,
919 enum mlx4_net_trans_promisc_mode mode);
1679200f
YP		 920int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
921int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
922int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
923int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
924int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
925
ffe455ad
EE		 926int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac);
927void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac);
928int mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac);
929int mlx4_get_eth_qp(struct mlx4_dev *dev, u8 port, u64 mac, int *qpn);
930void mlx4_put_eth_qp(struct mlx4_dev *dev, u8 port, u64 mac, int qpn);
93ece0c1 931void mlx4_set_stats_bitmap(struct mlx4_dev *dev, u64 *stats_bitmap);
9a9a232a
YP		 932int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu,
933 u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx);
934int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn,
935 u8 promisc);
e5395e92
AV		 936int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc);
937int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw,
938 u8 *pg, u16 *ratelimit);
4c3eb3ca 939int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx);
2a2336f8
YP		 940int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
941void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index);
942
8ad11fb6
JM		 943int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
944 int npages, u64 iova, u32 *lkey, u32 *rkey);
945int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
946 int max_maps, u8 page_shift, struct mlx4_fmr *fmr);
947int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
948void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
949 u32 *lkey, u32 *rkey);
950int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
951int mlx4_SYNC_TPT(struct mlx4_dev *dev);
e7c1c2c4 952int mlx4_test_interrupts(struct mlx4_dev *dev);
d9236c3f
AV		 953int mlx4_assign_eq(struct mlx4_dev *dev, char *name, struct cpu_rmap *rmap,
954 int *vector);
0b7ca5a9 955void mlx4_release_eq(struct mlx4_dev *dev, int vec);
8ad11fb6 956
14c07b13
YP		 957int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port);
958int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port);
959
f2a3f6a3
OG		 960int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
961void mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
962
0ff1fb65
HHZ		 963int mlx4_flow_attach(struct mlx4_dev *dev,
964 struct mlx4_net_trans_rule *rule, u64 *reg_id);
965int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id);
966
54679e14
JM		 967void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port,
968 int i, int val);
969
396f2feb
JM		 970int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey);
971
993c401e
JM		 972int mlx4_is_slave_active(struct mlx4_dev *dev, int slave);
973int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port);
974int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port);
975int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr);
976int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change);
977enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port);
978int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event);
979
980
225c7b1f 981#endif /* MLX4_DEVICE_H */
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