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225c7b1f RD |
1 | /* |
2 | * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef MLX4_DEVICE_H | |
34 | #define MLX4_DEVICE_H | |
35 | ||
574e2af7 | 36 | #include <linux/if_ether.h> |
225c7b1f RD |
37 | #include <linux/pci.h> |
38 | #include <linux/completion.h> | |
39 | #include <linux/radix-tree.h> | |
d9236c3f | 40 | #include <linux/cpu_rmap.h> |
48ea526a | 41 | #include <linux/crash_dump.h> |
225c7b1f | 42 | |
60063497 | 43 | #include <linux/atomic.h> |
225c7b1f | 44 | |
ec693d47 AV |
45 | #include <linux/clocksource.h> |
46 | ||
0b7ca5a9 YP |
47 | #define MAX_MSIX_P_PORT 17 |
48 | #define MAX_MSIX 64 | |
49 | #define MSIX_LEGACY_SZ 4 | |
50 | #define MIN_MSIX_P_PORT 5 | |
51 | ||
523ece88 EE |
52 | #define MLX4_NUM_UP 8 |
53 | #define MLX4_NUM_TC 8 | |
54 | #define MLX4_MAX_100M_UNITS_VAL 255 /* | |
55 | * work around: can't set values | |
56 | * greater then this value when | |
57 | * using 100 Mbps units. | |
58 | */ | |
59 | #define MLX4_RATELIMIT_100M_UNITS 3 /* 100 Mbps */ | |
60 | #define MLX4_RATELIMIT_1G_UNITS 4 /* 1 Gbps */ | |
61 | #define MLX4_RATELIMIT_DEFAULT 0x00ff | |
62 | ||
6ee51a4e | 63 | #define MLX4_ROCE_MAX_GIDS 128 |
b6ffaeff | 64 | #define MLX4_ROCE_PF_GIDS 16 |
6ee51a4e | 65 | |
225c7b1f RD |
66 | enum { |
67 | MLX4_FLAG_MSI_X = 1 << 0, | |
5ae2a7a8 | 68 | MLX4_FLAG_OLD_PORT_CMDS = 1 << 1, |
623ed84b JM |
69 | MLX4_FLAG_MASTER = 1 << 2, |
70 | MLX4_FLAG_SLAVE = 1 << 3, | |
71 | MLX4_FLAG_SRIOV = 1 << 4, | |
acddd5dd | 72 | MLX4_FLAG_OLD_REG_MAC = 1 << 6, |
225c7b1f RD |
73 | }; |
74 | ||
efcd235d JM |
75 | enum { |
76 | MLX4_PORT_CAP_IS_SM = 1 << 1, | |
77 | MLX4_PORT_CAP_DEV_MGMT_SUP = 1 << 19, | |
78 | }; | |
79 | ||
225c7b1f | 80 | enum { |
fc06573d JM |
81 | MLX4_MAX_PORTS = 2, |
82 | MLX4_MAX_PORT_PKEYS = 128 | |
225c7b1f RD |
83 | }; |
84 | ||
396f2feb JM |
85 | /* base qkey for use in sriov tunnel-qp/proxy-qp communication. |
86 | * These qkeys must not be allowed for general use. This is a 64k range, | |
87 | * and to test for violation, we use the mask (protect against future chg). | |
88 | */ | |
89 | #define MLX4_RESERVED_QKEY_BASE (0xFFFF0000) | |
90 | #define MLX4_RESERVED_QKEY_MASK (0xFFFF0000) | |
91 | ||
cd9281d8 JM |
92 | enum { |
93 | MLX4_BOARD_ID_LEN = 64 | |
94 | }; | |
95 | ||
623ed84b JM |
96 | enum { |
97 | MLX4_MAX_NUM_PF = 16, | |
98 | MLX4_MAX_NUM_VF = 64, | |
1ab95d37 | 99 | MLX4_MAX_NUM_VF_P_PORT = 64, |
623ed84b | 100 | MLX4_MFUNC_MAX = 80, |
3fc929e2 | 101 | MLX4_MAX_EQ_NUM = 1024, |
623ed84b JM |
102 | MLX4_MFUNC_EQ_NUM = 4, |
103 | MLX4_MFUNC_MAX_EQES = 8, | |
104 | MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1) | |
105 | }; | |
106 | ||
0ff1fb65 HHZ |
107 | /* Driver supports 3 diffrent device methods to manage traffic steering: |
108 | * -device managed - High level API for ib and eth flow steering. FW is | |
109 | * managing flow steering tables. | |
c96d97f4 HHZ |
110 | * - B0 steering mode - Common low level API for ib and (if supported) eth. |
111 | * - A0 steering mode - Limited low level API for eth. In case of IB, | |
112 | * B0 mode is in use. | |
113 | */ | |
114 | enum { | |
115 | MLX4_STEERING_MODE_A0, | |
0ff1fb65 HHZ |
116 | MLX4_STEERING_MODE_B0, |
117 | MLX4_STEERING_MODE_DEVICE_MANAGED | |
c96d97f4 HHZ |
118 | }; |
119 | ||
120 | static inline const char *mlx4_steering_mode_str(int steering_mode) | |
121 | { | |
122 | switch (steering_mode) { | |
123 | case MLX4_STEERING_MODE_A0: | |
124 | return "A0 steering"; | |
125 | ||
126 | case MLX4_STEERING_MODE_B0: | |
127 | return "B0 steering"; | |
0ff1fb65 HHZ |
128 | |
129 | case MLX4_STEERING_MODE_DEVICE_MANAGED: | |
130 | return "Device managed flow steering"; | |
131 | ||
c96d97f4 HHZ |
132 | default: |
133 | return "Unrecognize steering mode"; | |
134 | } | |
135 | } | |
136 | ||
7ffdf726 OG |
137 | enum { |
138 | MLX4_TUNNEL_OFFLOAD_MODE_NONE, | |
139 | MLX4_TUNNEL_OFFLOAD_MODE_VXLAN | |
140 | }; | |
141 | ||
225c7b1f | 142 | enum { |
52eafc68 OG |
143 | MLX4_DEV_CAP_FLAG_RC = 1LL << 0, |
144 | MLX4_DEV_CAP_FLAG_UC = 1LL << 1, | |
145 | MLX4_DEV_CAP_FLAG_UD = 1LL << 2, | |
012a8ff5 | 146 | MLX4_DEV_CAP_FLAG_XRC = 1LL << 3, |
52eafc68 OG |
147 | MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6, |
148 | MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7, | |
149 | MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8, | |
150 | MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9, | |
151 | MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12, | |
152 | MLX4_DEV_CAP_FLAG_BLH = 1LL << 15, | |
153 | MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16, | |
154 | MLX4_DEV_CAP_FLAG_APM = 1LL << 17, | |
155 | MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18, | |
156 | MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19, | |
157 | MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20, | |
158 | MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21, | |
ccf86321 OG |
159 | MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30, |
160 | MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32, | |
f3a9d1f2 | 161 | MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34, |
559a9f1d OD |
162 | MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37, |
163 | MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38, | |
ccf86321 OG |
164 | MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40, |
165 | MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41, | |
f2a3f6a3 | 166 | MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42, |
58a60168 | 167 | MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48, |
540b3a39 | 168 | MLX4_DEV_CAP_FLAG_SET_ETH_SCHED = 1LL << 53, |
00f5ce99 JM |
169 | MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55, |
170 | MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV = 1LL << 59, | |
08ff3235 OG |
171 | MLX4_DEV_CAP_FLAG_64B_EQE = 1LL << 61, |
172 | MLX4_DEV_CAP_FLAG_64B_CQE = 1LL << 62 | |
225c7b1f RD |
173 | }; |
174 | ||
b3416f44 SP |
175 | enum { |
176 | MLX4_DEV_CAP_FLAG2_RSS = 1LL << 0, | |
177 | MLX4_DEV_CAP_FLAG2_RSS_TOP = 1LL << 1, | |
0ff1fb65 | 178 | MLX4_DEV_CAP_FLAG2_RSS_XOR = 1LL << 2, |
955154fa | 179 | MLX4_DEV_CAP_FLAG2_FS_EN = 1LL << 3, |
5930e8d0 | 180 | MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN = 1LL << 4, |
3f7fb021 | 181 | MLX4_DEV_CAP_FLAG2_TS = 1LL << 5, |
e6b6a231 | 182 | MLX4_DEV_CAP_FLAG2_VLAN_CONTROL = 1LL << 6, |
b01978ca | 183 | MLX4_DEV_CAP_FLAG2_FSM = 1LL << 7, |
4de65803 | 184 | MLX4_DEV_CAP_FLAG2_UPDATE_QP = 1LL << 8, |
4ba9920e LT |
185 | MLX4_DEV_CAP_FLAG2_DMFS_IPOIB = 1LL << 9, |
186 | MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS = 1LL << 10, | |
114840c3 | 187 | MLX4_DEV_CAP_FLAG2_MAD_DEMUX = 1LL << 11, |
77507aa2 | 188 | MLX4_DEV_CAP_FLAG2_CQE_STRIDE = 1LL << 12, |
adbc7ac5 SM |
189 | MLX4_DEV_CAP_FLAG2_EQE_STRIDE = 1LL << 13, |
190 | MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL = 1LL << 14 | |
b3416f44 SP |
191 | }; |
192 | ||
08ff3235 OG |
193 | enum { |
194 | MLX4_DEV_CAP_64B_EQE_ENABLED = 1LL << 0, | |
77507aa2 IS |
195 | MLX4_DEV_CAP_64B_CQE_ENABLED = 1LL << 1, |
196 | MLX4_DEV_CAP_CQE_STRIDE_ENABLED = 1LL << 2, | |
197 | MLX4_DEV_CAP_EQE_STRIDE_ENABLED = 1LL << 3 | |
08ff3235 OG |
198 | }; |
199 | ||
200 | enum { | |
77507aa2 | 201 | MLX4_USER_DEV_CAP_LARGE_CQE = 1L << 0 |
08ff3235 OG |
202 | }; |
203 | ||
204 | enum { | |
77507aa2 IS |
205 | MLX4_FUNC_CAP_64B_EQE_CQE = 1L << 0, |
206 | MLX4_FUNC_CAP_EQE_CQE_STRIDE = 1L << 1 | |
08ff3235 OG |
207 | }; |
208 | ||
209 | ||
97285b78 MA |
210 | #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) |
211 | ||
95d04f07 | 212 | enum { |
804d6a89 | 213 | MLX4_BMME_FLAG_WIN_TYPE_2B = 1 << 1, |
95d04f07 RD |
214 | MLX4_BMME_FLAG_LOCAL_INV = 1 << 6, |
215 | MLX4_BMME_FLAG_REMOTE_INV = 1 << 7, | |
216 | MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9, | |
217 | MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10, | |
218 | MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11, | |
09e05c3f | 219 | MLX4_BMME_FLAG_VSD_INIT2RTR = 1 << 28, |
95d04f07 RD |
220 | }; |
221 | ||
225c7b1f RD |
222 | enum mlx4_event { |
223 | MLX4_EVENT_TYPE_COMP = 0x00, | |
224 | MLX4_EVENT_TYPE_PATH_MIG = 0x01, | |
225 | MLX4_EVENT_TYPE_COMM_EST = 0x02, | |
226 | MLX4_EVENT_TYPE_SQ_DRAINED = 0x03, | |
227 | MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13, | |
228 | MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14, | |
229 | MLX4_EVENT_TYPE_CQ_ERROR = 0x04, | |
230 | MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, | |
231 | MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06, | |
232 | MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07, | |
233 | MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, | |
234 | MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, | |
235 | MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, | |
236 | MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08, | |
237 | MLX4_EVENT_TYPE_PORT_CHANGE = 0x09, | |
238 | MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f, | |
239 | MLX4_EVENT_TYPE_ECC_DETECT = 0x0e, | |
623ed84b JM |
240 | MLX4_EVENT_TYPE_CMD = 0x0a, |
241 | MLX4_EVENT_TYPE_VEP_UPDATE = 0x19, | |
242 | MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18, | |
fe6f700d | 243 | MLX4_EVENT_TYPE_OP_REQUIRED = 0x1a, |
5984be90 | 244 | MLX4_EVENT_TYPE_FATAL_WARNING = 0x1b, |
623ed84b | 245 | MLX4_EVENT_TYPE_FLR_EVENT = 0x1c, |
00f5ce99 | 246 | MLX4_EVENT_TYPE_PORT_MNG_CHG_EVENT = 0x1d, |
623ed84b | 247 | MLX4_EVENT_TYPE_NONE = 0xff, |
225c7b1f RD |
248 | }; |
249 | ||
250 | enum { | |
251 | MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1, | |
252 | MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4 | |
253 | }; | |
254 | ||
5984be90 JM |
255 | enum { |
256 | MLX4_FATAL_WARNING_SUBTYPE_WARMING = 0, | |
257 | }; | |
258 | ||
993c401e JM |
259 | enum slave_port_state { |
260 | SLAVE_PORT_DOWN = 0, | |
261 | SLAVE_PENDING_UP, | |
262 | SLAVE_PORT_UP, | |
263 | }; | |
264 | ||
265 | enum slave_port_gen_event { | |
266 | SLAVE_PORT_GEN_EVENT_DOWN = 0, | |
267 | SLAVE_PORT_GEN_EVENT_UP, | |
268 | SLAVE_PORT_GEN_EVENT_NONE, | |
269 | }; | |
270 | ||
271 | enum slave_port_state_event { | |
272 | MLX4_PORT_STATE_DEV_EVENT_PORT_DOWN, | |
273 | MLX4_PORT_STATE_DEV_EVENT_PORT_UP, | |
274 | MLX4_PORT_STATE_IB_PORT_STATE_EVENT_GID_VALID, | |
275 | MLX4_PORT_STATE_IB_EVENT_GID_INVALID, | |
276 | }; | |
277 | ||
225c7b1f RD |
278 | enum { |
279 | MLX4_PERM_LOCAL_READ = 1 << 10, | |
280 | MLX4_PERM_LOCAL_WRITE = 1 << 11, | |
281 | MLX4_PERM_REMOTE_READ = 1 << 12, | |
282 | MLX4_PERM_REMOTE_WRITE = 1 << 13, | |
804d6a89 SM |
283 | MLX4_PERM_ATOMIC = 1 << 14, |
284 | MLX4_PERM_BIND_MW = 1 << 15, | |
e630664c | 285 | MLX4_PERM_MASK = 0xFC00 |
225c7b1f RD |
286 | }; |
287 | ||
288 | enum { | |
289 | MLX4_OPCODE_NOP = 0x00, | |
290 | MLX4_OPCODE_SEND_INVAL = 0x01, | |
291 | MLX4_OPCODE_RDMA_WRITE = 0x08, | |
292 | MLX4_OPCODE_RDMA_WRITE_IMM = 0x09, | |
293 | MLX4_OPCODE_SEND = 0x0a, | |
294 | MLX4_OPCODE_SEND_IMM = 0x0b, | |
295 | MLX4_OPCODE_LSO = 0x0e, | |
296 | MLX4_OPCODE_RDMA_READ = 0x10, | |
297 | MLX4_OPCODE_ATOMIC_CS = 0x11, | |
298 | MLX4_OPCODE_ATOMIC_FA = 0x12, | |
6fa8f719 VS |
299 | MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14, |
300 | MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15, | |
225c7b1f RD |
301 | MLX4_OPCODE_BIND_MW = 0x18, |
302 | MLX4_OPCODE_FMR = 0x19, | |
303 | MLX4_OPCODE_LOCAL_INVAL = 0x1b, | |
304 | MLX4_OPCODE_CONFIG_CMD = 0x1f, | |
305 | ||
306 | MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, | |
307 | MLX4_RECV_OPCODE_SEND = 0x01, | |
308 | MLX4_RECV_OPCODE_SEND_IMM = 0x02, | |
309 | MLX4_RECV_OPCODE_SEND_INVAL = 0x03, | |
310 | ||
311 | MLX4_CQE_OPCODE_ERROR = 0x1e, | |
312 | MLX4_CQE_OPCODE_RESIZE = 0x16, | |
313 | }; | |
314 | ||
315 | enum { | |
316 | MLX4_STAT_RATE_OFFSET = 5 | |
317 | }; | |
318 | ||
da995a8a | 319 | enum mlx4_protocol { |
0345584e YP |
320 | MLX4_PROT_IB_IPV6 = 0, |
321 | MLX4_PROT_ETH, | |
322 | MLX4_PROT_IB_IPV4, | |
323 | MLX4_PROT_FCOE | |
da995a8a AS |
324 | }; |
325 | ||
29bdc883 VS |
326 | enum { |
327 | MLX4_MTT_FLAG_PRESENT = 1 | |
328 | }; | |
329 | ||
93fc9e1b YP |
330 | enum mlx4_qp_region { |
331 | MLX4_QP_REGION_FW = 0, | |
332 | MLX4_QP_REGION_ETH_ADDR, | |
333 | MLX4_QP_REGION_FC_ADDR, | |
334 | MLX4_QP_REGION_FC_EXCH, | |
335 | MLX4_NUM_QP_REGION | |
336 | }; | |
337 | ||
7ff93f8b | 338 | enum mlx4_port_type { |
623ed84b | 339 | MLX4_PORT_TYPE_NONE = 0, |
27bf91d6 YP |
340 | MLX4_PORT_TYPE_IB = 1, |
341 | MLX4_PORT_TYPE_ETH = 2, | |
342 | MLX4_PORT_TYPE_AUTO = 3 | |
7ff93f8b YP |
343 | }; |
344 | ||
2a2336f8 YP |
345 | enum mlx4_special_vlan_idx { |
346 | MLX4_NO_VLAN_IDX = 0, | |
347 | MLX4_VLAN_MISS_IDX, | |
348 | MLX4_VLAN_REGULAR | |
349 | }; | |
350 | ||
0345584e YP |
351 | enum mlx4_steer_type { |
352 | MLX4_MC_STEER = 0, | |
353 | MLX4_UC_STEER, | |
354 | MLX4_NUM_STEERS | |
355 | }; | |
356 | ||
93fc9e1b YP |
357 | enum { |
358 | MLX4_NUM_FEXCH = 64 * 1024, | |
359 | }; | |
360 | ||
5a0fd094 EC |
361 | enum { |
362 | MLX4_MAX_FAST_REG_PAGES = 511, | |
363 | }; | |
364 | ||
00f5ce99 JM |
365 | enum { |
366 | MLX4_DEV_PMC_SUBTYPE_GUID_INFO = 0x14, | |
367 | MLX4_DEV_PMC_SUBTYPE_PORT_INFO = 0x15, | |
368 | MLX4_DEV_PMC_SUBTYPE_PKEY_TABLE = 0x16, | |
369 | }; | |
370 | ||
371 | /* Port mgmt change event handling */ | |
372 | enum { | |
373 | MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK = 1 << 0, | |
374 | MLX4_EQ_PORT_INFO_GID_PFX_CHANGE_MASK = 1 << 1, | |
375 | MLX4_EQ_PORT_INFO_LID_CHANGE_MASK = 1 << 2, | |
376 | MLX4_EQ_PORT_INFO_CLIENT_REREG_MASK = 1 << 3, | |
377 | MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK = 1 << 4, | |
378 | }; | |
379 | ||
380 | #define MSTR_SM_CHANGE_MASK (MLX4_EQ_PORT_INFO_MSTR_SM_SL_CHANGE_MASK | \ | |
381 | MLX4_EQ_PORT_INFO_MSTR_SM_LID_CHANGE_MASK) | |
382 | ||
32a173c7 SM |
383 | enum mlx4_module_id { |
384 | MLX4_MODULE_ID_SFP = 0x3, | |
385 | MLX4_MODULE_ID_QSFP = 0xC, | |
386 | MLX4_MODULE_ID_QSFP_PLUS = 0xD, | |
387 | MLX4_MODULE_ID_QSFP28 = 0x11, | |
388 | }; | |
389 | ||
ea54b10c JM |
390 | static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor) |
391 | { | |
392 | return (major << 32) | (minor << 16) | subminor; | |
393 | } | |
394 | ||
3fc929e2 | 395 | struct mlx4_phys_caps { |
6634961c JM |
396 | u32 gid_phys_table_len[MLX4_MAX_PORTS + 1]; |
397 | u32 pkey_phys_table_len[MLX4_MAX_PORTS + 1]; | |
3fc929e2 | 398 | u32 num_phys_eqs; |
47605df9 JM |
399 | u32 base_sqpn; |
400 | u32 base_proxy_sqpn; | |
401 | u32 base_tunnel_sqpn; | |
3fc929e2 MA |
402 | }; |
403 | ||
225c7b1f RD |
404 | struct mlx4_caps { |
405 | u64 fw_ver; | |
623ed84b | 406 | u32 function; |
225c7b1f | 407 | int num_ports; |
5ae2a7a8 | 408 | int vl_cap[MLX4_MAX_PORTS + 1]; |
b79acb49 | 409 | int ib_mtu_cap[MLX4_MAX_PORTS + 1]; |
9a5aa622 | 410 | __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1]; |
b79acb49 YP |
411 | u64 def_mac[MLX4_MAX_PORTS + 1]; |
412 | int eth_mtu_cap[MLX4_MAX_PORTS + 1]; | |
5ae2a7a8 RD |
413 | int gid_table_len[MLX4_MAX_PORTS + 1]; |
414 | int pkey_table_len[MLX4_MAX_PORTS + 1]; | |
7699517d YP |
415 | int trans_type[MLX4_MAX_PORTS + 1]; |
416 | int vendor_oui[MLX4_MAX_PORTS + 1]; | |
417 | int wavelength[MLX4_MAX_PORTS + 1]; | |
418 | u64 trans_code[MLX4_MAX_PORTS + 1]; | |
225c7b1f RD |
419 | int local_ca_ack_delay; |
420 | int num_uars; | |
f5311ac1 | 421 | u32 uar_page_size; |
225c7b1f RD |
422 | int bf_reg_size; |
423 | int bf_regs_per_page; | |
424 | int max_sq_sg; | |
425 | int max_rq_sg; | |
426 | int num_qps; | |
427 | int max_wqes; | |
428 | int max_sq_desc_sz; | |
429 | int max_rq_desc_sz; | |
430 | int max_qp_init_rdma; | |
431 | int max_qp_dest_rdma; | |
99ec41d0 | 432 | u32 *qp0_qkey; |
47605df9 JM |
433 | u32 *qp0_proxy; |
434 | u32 *qp1_proxy; | |
435 | u32 *qp0_tunnel; | |
436 | u32 *qp1_tunnel; | |
225c7b1f RD |
437 | int num_srqs; |
438 | int max_srq_wqes; | |
439 | int max_srq_sge; | |
440 | int reserved_srqs; | |
441 | int num_cqs; | |
442 | int max_cqes; | |
443 | int reserved_cqs; | |
444 | int num_eqs; | |
445 | int reserved_eqs; | |
b8dd786f | 446 | int num_comp_vectors; |
0b7ca5a9 | 447 | int comp_pool; |
225c7b1f | 448 | int num_mpts; |
a5bbe892 | 449 | int max_fmr_maps; |
2b8fb286 | 450 | int num_mtts; |
225c7b1f RD |
451 | int fmr_reserved_mtts; |
452 | int reserved_mtts; | |
453 | int reserved_mrws; | |
454 | int reserved_uars; | |
455 | int num_mgms; | |
456 | int num_amgms; | |
457 | int reserved_mcgs; | |
458 | int num_qp_per_mgm; | |
c96d97f4 | 459 | int steering_mode; |
0ff1fb65 | 460 | int fs_log_max_ucast_qp_range_size; |
225c7b1f RD |
461 | int num_pds; |
462 | int reserved_pds; | |
012a8ff5 SH |
463 | int max_xrcds; |
464 | int reserved_xrcds; | |
225c7b1f | 465 | int mtt_entry_sz; |
149983af | 466 | u32 max_msg_sz; |
225c7b1f | 467 | u32 page_size_cap; |
52eafc68 | 468 | u64 flags; |
b3416f44 | 469 | u64 flags2; |
95d04f07 RD |
470 | u32 bmme_flags; |
471 | u32 reserved_lkey; | |
225c7b1f | 472 | u16 stat_rate_support; |
5ae2a7a8 | 473 | u8 port_width_cap[MLX4_MAX_PORTS + 1]; |
b832be1e | 474 | int max_gso_sz; |
b3416f44 | 475 | int max_rss_tbl_sz; |
93fc9e1b YP |
476 | int reserved_qps_cnt[MLX4_NUM_QP_REGION]; |
477 | int reserved_qps; | |
478 | int reserved_qps_base[MLX4_NUM_QP_REGION]; | |
479 | int log_num_macs; | |
480 | int log_num_vlans; | |
7ff93f8b YP |
481 | enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1]; |
482 | u8 supported_type[MLX4_MAX_PORTS + 1]; | |
8d0fc7b6 YP |
483 | u8 suggested_type[MLX4_MAX_PORTS + 1]; |
484 | u8 default_sense[MLX4_MAX_PORTS + 1]; | |
65dab25d | 485 | u32 port_mask[MLX4_MAX_PORTS + 1]; |
27bf91d6 | 486 | enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1]; |
f2a3f6a3 | 487 | u32 max_counters; |
096335b3 | 488 | u8 port_ib_mtu[MLX4_MAX_PORTS + 1]; |
1ffeb2eb | 489 | u16 sqp_demux; |
08ff3235 OG |
490 | u32 eqe_size; |
491 | u32 cqe_size; | |
492 | u8 eqe_factor; | |
493 | u32 userspace_caps; /* userspace must be aware of these */ | |
494 | u32 function_caps; /* VFs must be aware of these */ | |
ddd8a6c1 | 495 | u16 hca_core_clock; |
8e1a28e8 | 496 | u64 phys_port_id[MLX4_MAX_PORTS + 1]; |
7ffdf726 | 497 | int tunnel_offload_mode; |
225c7b1f RD |
498 | }; |
499 | ||
500 | struct mlx4_buf_list { | |
501 | void *buf; | |
502 | dma_addr_t map; | |
503 | }; | |
504 | ||
505 | struct mlx4_buf { | |
b57aacfa RD |
506 | struct mlx4_buf_list direct; |
507 | struct mlx4_buf_list *page_list; | |
225c7b1f RD |
508 | int nbufs; |
509 | int npages; | |
510 | int page_shift; | |
511 | }; | |
512 | ||
513 | struct mlx4_mtt { | |
2b8fb286 | 514 | u32 offset; |
225c7b1f RD |
515 | int order; |
516 | int page_shift; | |
517 | }; | |
518 | ||
6296883c YP |
519 | enum { |
520 | MLX4_DB_PER_PAGE = PAGE_SIZE / 4 | |
521 | }; | |
522 | ||
523 | struct mlx4_db_pgdir { | |
524 | struct list_head list; | |
525 | DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE); | |
526 | DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2); | |
527 | unsigned long *bits[2]; | |
528 | __be32 *db_page; | |
529 | dma_addr_t db_dma; | |
530 | }; | |
531 | ||
532 | struct mlx4_ib_user_db_page; | |
533 | ||
534 | struct mlx4_db { | |
535 | __be32 *db; | |
536 | union { | |
537 | struct mlx4_db_pgdir *pgdir; | |
538 | struct mlx4_ib_user_db_page *user_page; | |
539 | } u; | |
540 | dma_addr_t dma; | |
541 | int index; | |
542 | int order; | |
543 | }; | |
544 | ||
38ae6a53 YP |
545 | struct mlx4_hwq_resources { |
546 | struct mlx4_db db; | |
547 | struct mlx4_mtt mtt; | |
548 | struct mlx4_buf buf; | |
549 | }; | |
550 | ||
225c7b1f RD |
551 | struct mlx4_mr { |
552 | struct mlx4_mtt mtt; | |
553 | u64 iova; | |
554 | u64 size; | |
555 | u32 key; | |
556 | u32 pd; | |
557 | u32 access; | |
558 | int enabled; | |
559 | }; | |
560 | ||
804d6a89 SM |
561 | enum mlx4_mw_type { |
562 | MLX4_MW_TYPE_1 = 1, | |
563 | MLX4_MW_TYPE_2 = 2, | |
564 | }; | |
565 | ||
566 | struct mlx4_mw { | |
567 | u32 key; | |
568 | u32 pd; | |
569 | enum mlx4_mw_type type; | |
570 | int enabled; | |
571 | }; | |
572 | ||
8ad11fb6 JM |
573 | struct mlx4_fmr { |
574 | struct mlx4_mr mr; | |
575 | struct mlx4_mpt_entry *mpt; | |
576 | __be64 *mtts; | |
577 | dma_addr_t dma_handle; | |
578 | int max_pages; | |
579 | int max_maps; | |
580 | int maps; | |
581 | u8 page_shift; | |
582 | }; | |
583 | ||
225c7b1f RD |
584 | struct mlx4_uar { |
585 | unsigned long pfn; | |
586 | int index; | |
c1b43dca EC |
587 | struct list_head bf_list; |
588 | unsigned free_bf_bmap; | |
589 | void __iomem *map; | |
590 | void __iomem *bf_map; | |
591 | }; | |
592 | ||
593 | struct mlx4_bf { | |
7dfa4b41 | 594 | unsigned int offset; |
c1b43dca EC |
595 | int buf_size; |
596 | struct mlx4_uar *uar; | |
597 | void __iomem *reg; | |
225c7b1f RD |
598 | }; |
599 | ||
600 | struct mlx4_cq { | |
601 | void (*comp) (struct mlx4_cq *); | |
602 | void (*event) (struct mlx4_cq *, enum mlx4_event); | |
603 | ||
604 | struct mlx4_uar *uar; | |
605 | ||
606 | u32 cons_index; | |
607 | ||
2eacc23c | 608 | u16 irq; |
225c7b1f RD |
609 | __be32 *set_ci_db; |
610 | __be32 *arm_db; | |
611 | int arm_sn; | |
612 | ||
613 | int cqn; | |
b8dd786f | 614 | unsigned vector; |
225c7b1f RD |
615 | |
616 | atomic_t refcount; | |
617 | struct completion free; | |
618 | }; | |
619 | ||
620 | struct mlx4_qp { | |
621 | void (*event) (struct mlx4_qp *, enum mlx4_event); | |
622 | ||
623 | int qpn; | |
624 | ||
625 | atomic_t refcount; | |
626 | struct completion free; | |
627 | }; | |
628 | ||
629 | struct mlx4_srq { | |
630 | void (*event) (struct mlx4_srq *, enum mlx4_event); | |
631 | ||
632 | int srqn; | |
633 | int max; | |
634 | int max_gs; | |
635 | int wqe_shift; | |
636 | ||
637 | atomic_t refcount; | |
638 | struct completion free; | |
639 | }; | |
640 | ||
641 | struct mlx4_av { | |
642 | __be32 port_pd; | |
643 | u8 reserved1; | |
644 | u8 g_slid; | |
645 | __be16 dlid; | |
646 | u8 reserved2; | |
647 | u8 gid_index; | |
648 | u8 stat_rate; | |
649 | u8 hop_limit; | |
650 | __be32 sl_tclass_flowlabel; | |
651 | u8 dgid[16]; | |
652 | }; | |
653 | ||
fa417f7b EC |
654 | struct mlx4_eth_av { |
655 | __be32 port_pd; | |
656 | u8 reserved1; | |
657 | u8 smac_idx; | |
658 | u16 reserved2; | |
659 | u8 reserved3; | |
660 | u8 gid_index; | |
661 | u8 stat_rate; | |
662 | u8 hop_limit; | |
663 | __be32 sl_tclass_flowlabel; | |
664 | u8 dgid[16]; | |
5ea8bbfc JM |
665 | u8 s_mac[6]; |
666 | u8 reserved4[2]; | |
fa417f7b | 667 | __be16 vlan; |
574e2af7 | 668 | u8 mac[ETH_ALEN]; |
fa417f7b EC |
669 | }; |
670 | ||
671 | union mlx4_ext_av { | |
672 | struct mlx4_av ib; | |
673 | struct mlx4_eth_av eth; | |
674 | }; | |
675 | ||
f2a3f6a3 OG |
676 | struct mlx4_counter { |
677 | u8 reserved1[3]; | |
678 | u8 counter_mode; | |
679 | __be32 num_ifc; | |
680 | u32 reserved2[2]; | |
681 | __be64 rx_frames; | |
682 | __be64 rx_bytes; | |
683 | __be64 tx_frames; | |
684 | __be64 tx_bytes; | |
685 | }; | |
686 | ||
5a0d0a61 JM |
687 | struct mlx4_quotas { |
688 | int qp; | |
689 | int cq; | |
690 | int srq; | |
691 | int mpt; | |
692 | int mtt; | |
693 | int counter; | |
694 | int xrcd; | |
695 | }; | |
696 | ||
1ab95d37 MB |
697 | struct mlx4_vf_dev { |
698 | u8 min_port; | |
699 | u8 n_ports; | |
700 | }; | |
701 | ||
225c7b1f RD |
702 | struct mlx4_dev { |
703 | struct pci_dev *pdev; | |
704 | unsigned long flags; | |
623ed84b | 705 | unsigned long num_slaves; |
225c7b1f | 706 | struct mlx4_caps caps; |
3fc929e2 | 707 | struct mlx4_phys_caps phys_caps; |
5a0d0a61 | 708 | struct mlx4_quotas quotas; |
225c7b1f | 709 | struct radix_tree_root qp_table_tree; |
725c8999 | 710 | u8 rev_id; |
cd9281d8 | 711 | char board_id[MLX4_BOARD_ID_LEN]; |
ab9c17a0 | 712 | int num_vfs; |
6e7136ed | 713 | int numa_node; |
3c439b55 | 714 | int oper_log_mgm_entry_size; |
592e49dd HHZ |
715 | u64 regid_promisc_array[MLX4_MAX_PORTS + 1]; |
716 | u64 regid_allmulti_array[MLX4_MAX_PORTS + 1]; | |
1ab95d37 | 717 | struct mlx4_vf_dev *dev_vfs; |
e1c00e10 | 718 | int nvfs[MLX4_MAX_PORTS + 1]; |
225c7b1f RD |
719 | }; |
720 | ||
00f5ce99 JM |
721 | struct mlx4_eqe { |
722 | u8 reserved1; | |
723 | u8 type; | |
724 | u8 reserved2; | |
725 | u8 subtype; | |
726 | union { | |
727 | u32 raw[6]; | |
728 | struct { | |
729 | __be32 cqn; | |
730 | } __packed comp; | |
731 | struct { | |
732 | u16 reserved1; | |
733 | __be16 token; | |
734 | u32 reserved2; | |
735 | u8 reserved3[3]; | |
736 | u8 status; | |
737 | __be64 out_param; | |
738 | } __packed cmd; | |
739 | struct { | |
740 | __be32 qpn; | |
741 | } __packed qp; | |
742 | struct { | |
743 | __be32 srqn; | |
744 | } __packed srq; | |
745 | struct { | |
746 | __be32 cqn; | |
747 | u32 reserved1; | |
748 | u8 reserved2[3]; | |
749 | u8 syndrome; | |
750 | } __packed cq_err; | |
751 | struct { | |
752 | u32 reserved1[2]; | |
753 | __be32 port; | |
754 | } __packed port_change; | |
755 | struct { | |
756 | #define COMM_CHANNEL_BIT_ARRAY_SIZE 4 | |
757 | u32 reserved; | |
758 | u32 bit_vec[COMM_CHANNEL_BIT_ARRAY_SIZE]; | |
759 | } __packed comm_channel_arm; | |
760 | struct { | |
761 | u8 port; | |
762 | u8 reserved[3]; | |
763 | __be64 mac; | |
764 | } __packed mac_update; | |
765 | struct { | |
766 | __be32 slave_id; | |
767 | } __packed flr_event; | |
768 | struct { | |
769 | __be16 current_temperature; | |
770 | __be16 warning_threshold; | |
771 | } __packed warming; | |
772 | struct { | |
773 | u8 reserved[3]; | |
774 | u8 port; | |
775 | union { | |
776 | struct { | |
777 | __be16 mstr_sm_lid; | |
778 | __be16 port_lid; | |
779 | __be32 changed_attr; | |
780 | u8 reserved[3]; | |
781 | u8 mstr_sm_sl; | |
782 | __be64 gid_prefix; | |
783 | } __packed port_info; | |
784 | struct { | |
785 | __be32 block_ptr; | |
786 | __be32 tbl_entries_mask; | |
787 | } __packed tbl_change_info; | |
788 | } params; | |
789 | } __packed port_mgmt_change; | |
790 | } event; | |
791 | u8 slave_id; | |
792 | u8 reserved3[2]; | |
793 | u8 owner; | |
794 | } __packed; | |
795 | ||
225c7b1f RD |
796 | struct mlx4_init_port_param { |
797 | int set_guid0; | |
798 | int set_node_guid; | |
799 | int set_si_guid; | |
800 | u16 mtu; | |
801 | int port_width_cap; | |
802 | u16 vl_cap; | |
803 | u16 max_gid; | |
804 | u16 max_pkey; | |
805 | u64 guid0; | |
806 | u64 node_guid; | |
807 | u64 si_guid; | |
808 | }; | |
809 | ||
32a173c7 SM |
810 | #define MAD_IFC_DATA_SZ 192 |
811 | /* MAD IFC Mailbox */ | |
812 | struct mlx4_mad_ifc { | |
813 | u8 base_version; | |
814 | u8 mgmt_class; | |
815 | u8 class_version; | |
816 | u8 method; | |
817 | __be16 status; | |
818 | __be16 class_specific; | |
819 | __be64 tid; | |
820 | __be16 attr_id; | |
821 | __be16 resv; | |
822 | __be32 attr_mod; | |
823 | __be64 mkey; | |
824 | __be16 dr_slid; | |
825 | __be16 dr_dlid; | |
826 | u8 reserved[28]; | |
827 | u8 data[MAD_IFC_DATA_SZ]; | |
828 | } __packed; | |
829 | ||
7ff93f8b YP |
830 | #define mlx4_foreach_port(port, dev, type) \ |
831 | for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ | |
65dab25d | 832 | if ((type) == (dev)->caps.port_mask[(port)]) |
7ff93f8b | 833 | |
026149cb JM |
834 | #define mlx4_foreach_non_ib_transport_port(port, dev) \ |
835 | for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ | |
836 | if (((dev)->caps.port_mask[port] != MLX4_PORT_TYPE_IB)) | |
837 | ||
65dab25d JM |
838 | #define mlx4_foreach_ib_transport_port(port, dev) \ |
839 | for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ | |
840 | if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \ | |
841 | ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE)) | |
623ed84b | 842 | |
752a50ca JM |
843 | #define MLX4_INVALID_SLAVE_ID 0xFF |
844 | ||
00f5ce99 JM |
845 | void handle_port_mgmt_change_event(struct work_struct *work); |
846 | ||
2aca1172 JM |
847 | static inline int mlx4_master_func_num(struct mlx4_dev *dev) |
848 | { | |
849 | return dev->caps.function; | |
850 | } | |
851 | ||
623ed84b JM |
852 | static inline int mlx4_is_master(struct mlx4_dev *dev) |
853 | { | |
854 | return dev->flags & MLX4_FLAG_MASTER; | |
855 | } | |
856 | ||
5a0d0a61 JM |
857 | static inline int mlx4_num_reserved_sqps(struct mlx4_dev *dev) |
858 | { | |
859 | return dev->phys_caps.base_sqpn + 8 + | |
860 | 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev); | |
861 | } | |
862 | ||
623ed84b JM |
863 | static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn) |
864 | { | |
47605df9 | 865 | return (qpn < dev->phys_caps.base_sqpn + 8 + |
e2c76824 JM |
866 | 16 * MLX4_MFUNC_MAX * !!mlx4_is_master(dev)); |
867 | } | |
868 | ||
869 | static inline int mlx4_is_guest_proxy(struct mlx4_dev *dev, int slave, u32 qpn) | |
870 | { | |
47605df9 | 871 | int guest_proxy_base = dev->phys_caps.base_proxy_sqpn + slave * 8; |
e2c76824 | 872 | |
47605df9 | 873 | if (qpn >= guest_proxy_base && qpn < guest_proxy_base + 8) |
e2c76824 JM |
874 | return 1; |
875 | ||
876 | return 0; | |
623ed84b | 877 | } |
fa417f7b | 878 | |
623ed84b JM |
879 | static inline int mlx4_is_mfunc(struct mlx4_dev *dev) |
880 | { | |
881 | return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER); | |
882 | } | |
883 | ||
884 | static inline int mlx4_is_slave(struct mlx4_dev *dev) | |
885 | { | |
886 | return dev->flags & MLX4_FLAG_SLAVE; | |
887 | } | |
fa417f7b | 888 | |
225c7b1f | 889 | int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct, |
40f2287b | 890 | struct mlx4_buf *buf, gfp_t gfp); |
225c7b1f | 891 | void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf); |
1c69fc2a RD |
892 | static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset) |
893 | { | |
313abe55 | 894 | if (BITS_PER_LONG == 64 || buf->nbufs == 1) |
b57aacfa | 895 | return buf->direct.buf + offset; |
1c69fc2a | 896 | else |
b57aacfa | 897 | return buf->page_list[offset >> PAGE_SHIFT].buf + |
1c69fc2a RD |
898 | (offset & (PAGE_SIZE - 1)); |
899 | } | |
225c7b1f RD |
900 | |
901 | int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn); | |
902 | void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn); | |
012a8ff5 SH |
903 | int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn); |
904 | void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn); | |
225c7b1f RD |
905 | |
906 | int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar); | |
907 | void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar); | |
163561a4 | 908 | int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf, int node); |
c1b43dca | 909 | void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf); |
225c7b1f RD |
910 | |
911 | int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift, | |
912 | struct mlx4_mtt *mtt); | |
913 | void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt); | |
914 | u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt); | |
915 | ||
916 | int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access, | |
917 | int npages, int page_shift, struct mlx4_mr *mr); | |
61083720 | 918 | int mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr); |
225c7b1f | 919 | int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr); |
804d6a89 SM |
920 | int mlx4_mw_alloc(struct mlx4_dev *dev, u32 pd, enum mlx4_mw_type type, |
921 | struct mlx4_mw *mw); | |
922 | void mlx4_mw_free(struct mlx4_dev *dev, struct mlx4_mw *mw); | |
923 | int mlx4_mw_enable(struct mlx4_dev *dev, struct mlx4_mw *mw); | |
225c7b1f RD |
924 | int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, |
925 | int start_index, int npages, u64 *page_list); | |
926 | int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, | |
40f2287b | 927 | struct mlx4_buf *buf, gfp_t gfp); |
225c7b1f | 928 | |
40f2287b JK |
929 | int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order, |
930 | gfp_t gfp); | |
6296883c YP |
931 | void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db); |
932 | ||
38ae6a53 YP |
933 | int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres, |
934 | int size, int max_direct); | |
935 | void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres, | |
936 | int size); | |
937 | ||
225c7b1f | 938 | int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt, |
e463c7b1 | 939 | struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq, |
ec693d47 | 940 | unsigned vector, int collapsed, int timestamp_en); |
225c7b1f RD |
941 | void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq); |
942 | ||
a3cdcbfa YP |
943 | int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base); |
944 | void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt); | |
945 | ||
40f2287b JK |
946 | int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp, |
947 | gfp_t gfp); | |
225c7b1f RD |
948 | void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp); |
949 | ||
18abd5ea SH |
950 | int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn, |
951 | struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq); | |
225c7b1f RD |
952 | void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq); |
953 | int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark); | |
65541cb7 | 954 | int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark); |
225c7b1f | 955 | |
5ae2a7a8 | 956 | int mlx4_INIT_PORT(struct mlx4_dev *dev, int port); |
225c7b1f RD |
957 | int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port); |
958 | ||
ffe455ad EE |
959 | int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], |
960 | int block_mcast_loopback, enum mlx4_protocol prot); | |
961 | int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], | |
962 | enum mlx4_protocol prot); | |
521e575b | 963 | int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], |
0ff1fb65 HHZ |
964 | u8 port, int block_mcast_loopback, |
965 | enum mlx4_protocol protocol, u64 *reg_id); | |
da995a8a | 966 | int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], |
0ff1fb65 HHZ |
967 | enum mlx4_protocol protocol, u64 reg_id); |
968 | ||
969 | enum { | |
970 | MLX4_DOMAIN_UVERBS = 0x1000, | |
971 | MLX4_DOMAIN_ETHTOOL = 0x2000, | |
972 | MLX4_DOMAIN_RFS = 0x3000, | |
973 | MLX4_DOMAIN_NIC = 0x5000, | |
974 | }; | |
975 | ||
976 | enum mlx4_net_trans_rule_id { | |
977 | MLX4_NET_TRANS_RULE_ID_ETH = 0, | |
978 | MLX4_NET_TRANS_RULE_ID_IB, | |
979 | MLX4_NET_TRANS_RULE_ID_IPV6, | |
980 | MLX4_NET_TRANS_RULE_ID_IPV4, | |
981 | MLX4_NET_TRANS_RULE_ID_TCP, | |
982 | MLX4_NET_TRANS_RULE_ID_UDP, | |
7ffdf726 | 983 | MLX4_NET_TRANS_RULE_ID_VXLAN, |
0ff1fb65 HHZ |
984 | MLX4_NET_TRANS_RULE_NUM, /* should be last */ |
985 | }; | |
986 | ||
a8edc3bf HHZ |
987 | extern const u16 __sw_id_hw[]; |
988 | ||
7fb40f87 HHZ |
989 | static inline int map_hw_to_sw_id(u16 header_id) |
990 | { | |
991 | ||
992 | int i; | |
993 | for (i = 0; i < MLX4_NET_TRANS_RULE_NUM; i++) { | |
994 | if (header_id == __sw_id_hw[i]) | |
995 | return i; | |
996 | } | |
997 | return -EINVAL; | |
998 | } | |
999 | ||
0ff1fb65 | 1000 | enum mlx4_net_trans_promisc_mode { |
f9162539 HHZ |
1001 | MLX4_FS_REGULAR = 1, |
1002 | MLX4_FS_ALL_DEFAULT, | |
1003 | MLX4_FS_MC_DEFAULT, | |
1004 | MLX4_FS_UC_SNIFFER, | |
1005 | MLX4_FS_MC_SNIFFER, | |
c2c19dc3 | 1006 | MLX4_FS_MODE_NUM, /* should be last */ |
0ff1fb65 HHZ |
1007 | }; |
1008 | ||
1009 | struct mlx4_spec_eth { | |
574e2af7 JP |
1010 | u8 dst_mac[ETH_ALEN]; |
1011 | u8 dst_mac_msk[ETH_ALEN]; | |
1012 | u8 src_mac[ETH_ALEN]; | |
1013 | u8 src_mac_msk[ETH_ALEN]; | |
0ff1fb65 HHZ |
1014 | u8 ether_type_enable; |
1015 | __be16 ether_type; | |
1016 | __be16 vlan_id_msk; | |
1017 | __be16 vlan_id; | |
1018 | }; | |
1019 | ||
1020 | struct mlx4_spec_tcp_udp { | |
1021 | __be16 dst_port; | |
1022 | __be16 dst_port_msk; | |
1023 | __be16 src_port; | |
1024 | __be16 src_port_msk; | |
1025 | }; | |
1026 | ||
1027 | struct mlx4_spec_ipv4 { | |
1028 | __be32 dst_ip; | |
1029 | __be32 dst_ip_msk; | |
1030 | __be32 src_ip; | |
1031 | __be32 src_ip_msk; | |
1032 | }; | |
1033 | ||
1034 | struct mlx4_spec_ib { | |
ba60a356 | 1035 | __be32 l3_qpn; |
0ff1fb65 HHZ |
1036 | __be32 qpn_msk; |
1037 | u8 dst_gid[16]; | |
1038 | u8 dst_gid_msk[16]; | |
1039 | }; | |
1040 | ||
7ffdf726 OG |
1041 | struct mlx4_spec_vxlan { |
1042 | __be32 vni; | |
1043 | __be32 vni_mask; | |
1044 | ||
1045 | }; | |
1046 | ||
0ff1fb65 HHZ |
1047 | struct mlx4_spec_list { |
1048 | struct list_head list; | |
1049 | enum mlx4_net_trans_rule_id id; | |
1050 | union { | |
1051 | struct mlx4_spec_eth eth; | |
1052 | struct mlx4_spec_ib ib; | |
1053 | struct mlx4_spec_ipv4 ipv4; | |
1054 | struct mlx4_spec_tcp_udp tcp_udp; | |
7ffdf726 | 1055 | struct mlx4_spec_vxlan vxlan; |
0ff1fb65 HHZ |
1056 | }; |
1057 | }; | |
1058 | ||
1059 | enum mlx4_net_trans_hw_rule_queue { | |
1060 | MLX4_NET_TRANS_Q_FIFO, | |
1061 | MLX4_NET_TRANS_Q_LIFO, | |
1062 | }; | |
1063 | ||
1064 | struct mlx4_net_trans_rule { | |
1065 | struct list_head list; | |
1066 | enum mlx4_net_trans_hw_rule_queue queue_mode; | |
1067 | bool exclusive; | |
1068 | bool allow_loopback; | |
1069 | enum mlx4_net_trans_promisc_mode promisc_mode; | |
1070 | u8 port; | |
1071 | u16 priority; | |
1072 | u32 qpn; | |
1073 | }; | |
1074 | ||
3cd0e178 | 1075 | struct mlx4_net_trans_rule_hw_ctrl { |
bcf37297 HHZ |
1076 | __be16 prio; |
1077 | u8 type; | |
1078 | u8 flags; | |
3cd0e178 HHZ |
1079 | u8 rsvd1; |
1080 | u8 funcid; | |
1081 | u8 vep; | |
1082 | u8 port; | |
1083 | __be32 qpn; | |
1084 | __be32 rsvd2; | |
1085 | }; | |
1086 | ||
1087 | struct mlx4_net_trans_rule_hw_ib { | |
1088 | u8 size; | |
1089 | u8 rsvd1; | |
1090 | __be16 id; | |
1091 | u32 rsvd2; | |
ba60a356 | 1092 | __be32 l3_qpn; |
3cd0e178 HHZ |
1093 | __be32 qpn_mask; |
1094 | u8 dst_gid[16]; | |
1095 | u8 dst_gid_msk[16]; | |
1096 | } __packed; | |
1097 | ||
1098 | struct mlx4_net_trans_rule_hw_eth { | |
1099 | u8 size; | |
1100 | u8 rsvd; | |
1101 | __be16 id; | |
1102 | u8 rsvd1[6]; | |
1103 | u8 dst_mac[6]; | |
1104 | u16 rsvd2; | |
1105 | u8 dst_mac_msk[6]; | |
1106 | u16 rsvd3; | |
1107 | u8 src_mac[6]; | |
1108 | u16 rsvd4; | |
1109 | u8 src_mac_msk[6]; | |
1110 | u8 rsvd5; | |
1111 | u8 ether_type_enable; | |
1112 | __be16 ether_type; | |
ba60a356 HHZ |
1113 | __be16 vlan_tag_msk; |
1114 | __be16 vlan_tag; | |
3cd0e178 HHZ |
1115 | } __packed; |
1116 | ||
1117 | struct mlx4_net_trans_rule_hw_tcp_udp { | |
1118 | u8 size; | |
1119 | u8 rsvd; | |
1120 | __be16 id; | |
1121 | __be16 rsvd1[3]; | |
1122 | __be16 dst_port; | |
1123 | __be16 rsvd2; | |
1124 | __be16 dst_port_msk; | |
1125 | __be16 rsvd3; | |
1126 | __be16 src_port; | |
1127 | __be16 rsvd4; | |
1128 | __be16 src_port_msk; | |
1129 | } __packed; | |
1130 | ||
1131 | struct mlx4_net_trans_rule_hw_ipv4 { | |
1132 | u8 size; | |
1133 | u8 rsvd; | |
1134 | __be16 id; | |
1135 | __be32 rsvd1; | |
1136 | __be32 dst_ip; | |
1137 | __be32 dst_ip_msk; | |
1138 | __be32 src_ip; | |
1139 | __be32 src_ip_msk; | |
1140 | } __packed; | |
1141 | ||
7ffdf726 OG |
1142 | struct mlx4_net_trans_rule_hw_vxlan { |
1143 | u8 size; | |
1144 | u8 rsvd; | |
1145 | __be16 id; | |
1146 | __be32 rsvd1; | |
1147 | __be32 vni; | |
1148 | __be32 vni_mask; | |
1149 | } __packed; | |
1150 | ||
3cd0e178 HHZ |
1151 | struct _rule_hw { |
1152 | union { | |
1153 | struct { | |
1154 | u8 size; | |
1155 | u8 rsvd; | |
1156 | __be16 id; | |
1157 | }; | |
1158 | struct mlx4_net_trans_rule_hw_eth eth; | |
1159 | struct mlx4_net_trans_rule_hw_ib ib; | |
1160 | struct mlx4_net_trans_rule_hw_ipv4 ipv4; | |
1161 | struct mlx4_net_trans_rule_hw_tcp_udp tcp_udp; | |
7ffdf726 | 1162 | struct mlx4_net_trans_rule_hw_vxlan vxlan; |
3cd0e178 HHZ |
1163 | }; |
1164 | }; | |
1165 | ||
7ffdf726 OG |
1166 | enum { |
1167 | VXLAN_STEER_BY_OUTER_MAC = 1 << 0, | |
1168 | VXLAN_STEER_BY_OUTER_VLAN = 1 << 1, | |
1169 | VXLAN_STEER_BY_VSID_VNI = 1 << 2, | |
1170 | VXLAN_STEER_BY_INNER_MAC = 1 << 3, | |
1171 | VXLAN_STEER_BY_INNER_VLAN = 1 << 4, | |
1172 | }; | |
1173 | ||
1174 | ||
592e49dd HHZ |
1175 | int mlx4_flow_steer_promisc_add(struct mlx4_dev *dev, u8 port, u32 qpn, |
1176 | enum mlx4_net_trans_promisc_mode mode); | |
1177 | int mlx4_flow_steer_promisc_remove(struct mlx4_dev *dev, u8 port, | |
1178 | enum mlx4_net_trans_promisc_mode mode); | |
1679200f YP |
1179 | int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); |
1180 | int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); | |
1181 | int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); | |
1182 | int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); | |
1183 | int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode); | |
1184 | ||
ffe455ad EE |
1185 | int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac); |
1186 | void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac); | |
16a10ffd YB |
1187 | int mlx4_get_base_qpn(struct mlx4_dev *dev, u8 port); |
1188 | int __mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac); | |
93ece0c1 | 1189 | void mlx4_set_stats_bitmap(struct mlx4_dev *dev, u64 *stats_bitmap); |
9a9a232a YP |
1190 | int mlx4_SET_PORT_general(struct mlx4_dev *dev, u8 port, int mtu, |
1191 | u8 pptx, u8 pfctx, u8 pprx, u8 pfcrx); | |
1192 | int mlx4_SET_PORT_qpn_calc(struct mlx4_dev *dev, u8 port, u32 base_qpn, | |
1193 | u8 promisc); | |
e5395e92 AV |
1194 | int mlx4_SET_PORT_PRIO2TC(struct mlx4_dev *dev, u8 port, u8 *prio2tc); |
1195 | int mlx4_SET_PORT_SCHEDULER(struct mlx4_dev *dev, u8 port, u8 *tc_tx_bw, | |
1196 | u8 *pg, u16 *ratelimit); | |
1b136de1 | 1197 | int mlx4_SET_PORT_VXLAN(struct mlx4_dev *dev, u8 port, u8 steering, int enable); |
dd5f03be | 1198 | int mlx4_find_cached_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *idx); |
4c3eb3ca | 1199 | int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx); |
2a2336f8 | 1200 | int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index); |
2009d005 | 1201 | void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, u16 vlan); |
2a2336f8 | 1202 | |
8ad11fb6 JM |
1203 | int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list, |
1204 | int npages, u64 iova, u32 *lkey, u32 *rkey); | |
1205 | int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages, | |
1206 | int max_maps, u8 page_shift, struct mlx4_fmr *fmr); | |
1207 | int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr); | |
1208 | void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr, | |
1209 | u32 *lkey, u32 *rkey); | |
1210 | int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr); | |
1211 | int mlx4_SYNC_TPT(struct mlx4_dev *dev); | |
e7c1c2c4 | 1212 | int mlx4_test_interrupts(struct mlx4_dev *dev); |
d9236c3f AV |
1213 | int mlx4_assign_eq(struct mlx4_dev *dev, char *name, struct cpu_rmap *rmap, |
1214 | int *vector); | |
0b7ca5a9 | 1215 | void mlx4_release_eq(struct mlx4_dev *dev, int vec); |
8ad11fb6 | 1216 | |
35f6f453 AV |
1217 | int mlx4_eq_get_irq(struct mlx4_dev *dev, int vec); |
1218 | ||
8e1a28e8 | 1219 | int mlx4_get_phys_port_id(struct mlx4_dev *dev); |
14c07b13 YP |
1220 | int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port); |
1221 | int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port); | |
1222 | ||
f2a3f6a3 OG |
1223 | int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx); |
1224 | void mlx4_counter_free(struct mlx4_dev *dev, u32 idx); | |
1225 | ||
0ff1fb65 HHZ |
1226 | int mlx4_flow_attach(struct mlx4_dev *dev, |
1227 | struct mlx4_net_trans_rule *rule, u64 *reg_id); | |
1228 | int mlx4_flow_detach(struct mlx4_dev *dev, u64 reg_id); | |
c2c19dc3 HHZ |
1229 | int mlx4_map_sw_to_hw_steering_mode(struct mlx4_dev *dev, |
1230 | enum mlx4_net_trans_promisc_mode flow_type); | |
1231 | int mlx4_map_sw_to_hw_steering_id(struct mlx4_dev *dev, | |
1232 | enum mlx4_net_trans_rule_id id); | |
1233 | int mlx4_hw_rule_sz(struct mlx4_dev *dev, enum mlx4_net_trans_rule_id id); | |
0ff1fb65 | 1234 | |
b95089d0 OG |
1235 | int mlx4_tunnel_steer_add(struct mlx4_dev *dev, unsigned char *addr, |
1236 | int port, int qpn, u16 prio, u64 *reg_id); | |
1237 | ||
54679e14 JM |
1238 | void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, |
1239 | int i, int val); | |
1240 | ||
396f2feb JM |
1241 | int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey); |
1242 | ||
993c401e JM |
1243 | int mlx4_is_slave_active(struct mlx4_dev *dev, int slave); |
1244 | int mlx4_gen_pkey_eqe(struct mlx4_dev *dev, int slave, u8 port); | |
1245 | int mlx4_gen_guid_change_eqe(struct mlx4_dev *dev, int slave, u8 port); | |
1246 | int mlx4_gen_slaves_port_mgt_ev(struct mlx4_dev *dev, u8 port, int attr); | |
1247 | int mlx4_gen_port_state_change_eqe(struct mlx4_dev *dev, int slave, u8 port, u8 port_subtype_change); | |
1248 | enum slave_port_state mlx4_get_slave_port_state(struct mlx4_dev *dev, int slave, u8 port); | |
1249 | int set_and_calc_slave_port_state(struct mlx4_dev *dev, int slave, u8 port, int event, enum slave_port_gen_event *gen_event); | |
1250 | ||
afa8fd1d JM |
1251 | void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid); |
1252 | __be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave); | |
9cd59352 JM |
1253 | |
1254 | int mlx4_get_slave_from_roce_gid(struct mlx4_dev *dev, int port, u8 *gid, | |
1255 | int *slave_id); | |
1256 | int mlx4_get_roce_gid_from_slave(struct mlx4_dev *dev, int port, int slave_id, | |
1257 | u8 *gid); | |
993c401e | 1258 | |
4de65803 MB |
1259 | int mlx4_FLOW_STEERING_IB_UC_QP_RANGE(struct mlx4_dev *dev, u32 min_range_qpn, |
1260 | u32 max_range_qpn); | |
1261 | ||
ec693d47 AV |
1262 | cycle_t mlx4_read_clock(struct mlx4_dev *dev); |
1263 | ||
f74462ac MB |
1264 | struct mlx4_active_ports { |
1265 | DECLARE_BITMAP(ports, MLX4_MAX_PORTS); | |
1266 | }; | |
1267 | /* Returns a bitmap of the physical ports which are assigned to slave */ | |
1268 | struct mlx4_active_ports mlx4_get_active_ports(struct mlx4_dev *dev, int slave); | |
1269 | ||
1270 | /* Returns the physical port that represents the virtual port of the slave, */ | |
1271 | /* or a value < 0 in case of an error. If a slave has 2 ports, the identity */ | |
1272 | /* mapping is returned. */ | |
1273 | int mlx4_slave_convert_port(struct mlx4_dev *dev, int slave, int port); | |
1274 | ||
1275 | struct mlx4_slaves_pport { | |
1276 | DECLARE_BITMAP(slaves, MLX4_MFUNC_MAX); | |
1277 | }; | |
1278 | /* Returns a bitmap of all slaves that are assigned to port. */ | |
1279 | struct mlx4_slaves_pport mlx4_phys_to_slaves_pport(struct mlx4_dev *dev, | |
1280 | int port); | |
1281 | ||
1282 | /* Returns a bitmap of all slaves that are assigned exactly to all the */ | |
1283 | /* the ports that are set in crit_ports. */ | |
1284 | struct mlx4_slaves_pport mlx4_phys_to_slaves_pport_actv( | |
1285 | struct mlx4_dev *dev, | |
1286 | const struct mlx4_active_ports *crit_ports); | |
1287 | ||
1288 | /* Returns the slave's virtual port that represents the physical port. */ | |
1289 | int mlx4_phys_to_slave_port(struct mlx4_dev *dev, int slave, int port); | |
1290 | ||
449fc488 | 1291 | int mlx4_get_base_gid_ix(struct mlx4_dev *dev, int slave, int port); |
d18f141a OG |
1292 | |
1293 | int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port); | |
97982f5a | 1294 | int mlx4_vf_smi_enabled(struct mlx4_dev *dev, int slave, int port); |
65fed8a8 JM |
1295 | int mlx4_vf_get_enable_smi_admin(struct mlx4_dev *dev, int slave, int port); |
1296 | int mlx4_vf_set_enable_smi_admin(struct mlx4_dev *dev, int slave, int port, | |
1297 | int enable); | |
e630664c MB |
1298 | int mlx4_mr_hw_get_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr, |
1299 | struct mlx4_mpt_entry ***mpt_entry); | |
1300 | int mlx4_mr_hw_write_mpt(struct mlx4_dev *dev, struct mlx4_mr *mmr, | |
1301 | struct mlx4_mpt_entry **mpt_entry); | |
1302 | int mlx4_mr_hw_change_pd(struct mlx4_dev *dev, struct mlx4_mpt_entry *mpt_entry, | |
1303 | u32 pdn); | |
1304 | int mlx4_mr_hw_change_access(struct mlx4_dev *dev, | |
1305 | struct mlx4_mpt_entry *mpt_entry, | |
1306 | u32 access); | |
1307 | void mlx4_mr_hw_put_mpt(struct mlx4_dev *dev, | |
1308 | struct mlx4_mpt_entry **mpt_entry); | |
1309 | void mlx4_mr_rereg_mem_cleanup(struct mlx4_dev *dev, struct mlx4_mr *mr); | |
1310 | int mlx4_mr_rereg_mem_write(struct mlx4_dev *dev, struct mlx4_mr *mr, | |
1311 | u64 iova, u64 size, int npages, | |
1312 | int page_shift, struct mlx4_mpt_entry *mpt_entry); | |
2599d858 | 1313 | |
32a173c7 SM |
1314 | int mlx4_get_module_info(struct mlx4_dev *dev, u8 port, |
1315 | u16 offset, u16 size, u8 *data); | |
1316 | ||
2599d858 AV |
1317 | /* Returns true if running in low memory profile (kdump kernel) */ |
1318 | static inline bool mlx4_low_memory_profile(void) | |
1319 | { | |
48ea526a | 1320 | return is_kdump_kernel(); |
2599d858 AV |
1321 | } |
1322 | ||
adbc7ac5 SM |
1323 | /* ACCESS REG commands */ |
1324 | enum mlx4_access_reg_method { | |
1325 | MLX4_ACCESS_REG_QUERY = 0x1, | |
1326 | MLX4_ACCESS_REG_WRITE = 0x2, | |
1327 | }; | |
1328 | ||
1329 | /* ACCESS PTYS Reg command */ | |
1330 | enum mlx4_ptys_proto { | |
1331 | MLX4_PTYS_IB = 1<<0, | |
1332 | MLX4_PTYS_EN = 1<<2, | |
1333 | }; | |
1334 | ||
1335 | struct mlx4_ptys_reg { | |
1336 | u8 resrvd1; | |
1337 | u8 local_port; | |
1338 | u8 resrvd2; | |
1339 | u8 proto_mask; | |
1340 | __be32 resrvd3[2]; | |
1341 | __be32 eth_proto_cap; | |
1342 | __be16 ib_width_cap; | |
1343 | __be16 ib_speed_cap; | |
1344 | __be32 resrvd4; | |
1345 | __be32 eth_proto_admin; | |
1346 | __be16 ib_width_admin; | |
1347 | __be16 ib_speed_admin; | |
1348 | __be32 resrvd5; | |
1349 | __be32 eth_proto_oper; | |
1350 | __be16 ib_width_oper; | |
1351 | __be16 ib_speed_oper; | |
1352 | __be32 resrvd6; | |
1353 | __be32 eth_proto_lp_adv; | |
1354 | } __packed; | |
1355 | ||
1356 | int mlx4_ACCESS_PTYS_REG(struct mlx4_dev *dev, | |
1357 | enum mlx4_access_reg_method method, | |
1358 | struct mlx4_ptys_reg *ptys_reg); | |
1359 | ||
225c7b1f | 1360 | #endif /* MLX4_DEVICE_H */ |