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225c7b1f RD |
1 | /* |
2 | * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. | |
3 | * | |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef MLX4_DEVICE_H | |
34 | #define MLX4_DEVICE_H | |
35 | ||
36 | #include <linux/pci.h> | |
37 | #include <linux/completion.h> | |
38 | #include <linux/radix-tree.h> | |
39 | ||
60063497 | 40 | #include <linux/atomic.h> |
225c7b1f | 41 | |
0b7ca5a9 YP |
42 | #define MAX_MSIX_P_PORT 17 |
43 | #define MAX_MSIX 64 | |
44 | #define MSIX_LEGACY_SZ 4 | |
45 | #define MIN_MSIX_P_PORT 5 | |
46 | ||
225c7b1f RD |
47 | enum { |
48 | MLX4_FLAG_MSI_X = 1 << 0, | |
5ae2a7a8 | 49 | MLX4_FLAG_OLD_PORT_CMDS = 1 << 1, |
623ed84b JM |
50 | MLX4_FLAG_MASTER = 1 << 2, |
51 | MLX4_FLAG_SLAVE = 1 << 3, | |
52 | MLX4_FLAG_SRIOV = 1 << 4, | |
225c7b1f RD |
53 | }; |
54 | ||
55 | enum { | |
56 | MLX4_MAX_PORTS = 2 | |
57 | }; | |
58 | ||
cd9281d8 JM |
59 | enum { |
60 | MLX4_BOARD_ID_LEN = 64 | |
61 | }; | |
62 | ||
623ed84b JM |
63 | enum { |
64 | MLX4_MAX_NUM_PF = 16, | |
65 | MLX4_MAX_NUM_VF = 64, | |
66 | MLX4_MFUNC_MAX = 80, | |
67 | MLX4_MFUNC_EQ_NUM = 4, | |
68 | MLX4_MFUNC_MAX_EQES = 8, | |
69 | MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1) | |
70 | }; | |
71 | ||
225c7b1f | 72 | enum { |
52eafc68 OG |
73 | MLX4_DEV_CAP_FLAG_RC = 1LL << 0, |
74 | MLX4_DEV_CAP_FLAG_UC = 1LL << 1, | |
75 | MLX4_DEV_CAP_FLAG_UD = 1LL << 2, | |
012a8ff5 | 76 | MLX4_DEV_CAP_FLAG_XRC = 1LL << 3, |
52eafc68 OG |
77 | MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6, |
78 | MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7, | |
79 | MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8, | |
80 | MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9, | |
81 | MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12, | |
82 | MLX4_DEV_CAP_FLAG_BLH = 1LL << 15, | |
83 | MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16, | |
84 | MLX4_DEV_CAP_FLAG_APM = 1LL << 17, | |
85 | MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18, | |
86 | MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19, | |
87 | MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20, | |
88 | MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21, | |
ccf86321 OG |
89 | MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30, |
90 | MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32, | |
f3a9d1f2 | 91 | MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34, |
559a9f1d OD |
92 | MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37, |
93 | MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38, | |
ccf86321 OG |
94 | MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40, |
95 | MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41, | |
f2a3f6a3 | 96 | MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42, |
58a60168 YP |
97 | MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48, |
98 | MLX4_DEV_CAP_FLAG_SENSE_SUPPORT = 1LL << 55 | |
225c7b1f RD |
99 | }; |
100 | ||
97285b78 MA |
101 | #define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) |
102 | ||
103 | enum { | |
104 | MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0 | |
105 | }; | |
106 | ||
95d04f07 RD |
107 | enum { |
108 | MLX4_BMME_FLAG_LOCAL_INV = 1 << 6, | |
109 | MLX4_BMME_FLAG_REMOTE_INV = 1 << 7, | |
110 | MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9, | |
111 | MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10, | |
112 | MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11, | |
113 | }; | |
114 | ||
225c7b1f RD |
115 | enum mlx4_event { |
116 | MLX4_EVENT_TYPE_COMP = 0x00, | |
117 | MLX4_EVENT_TYPE_PATH_MIG = 0x01, | |
118 | MLX4_EVENT_TYPE_COMM_EST = 0x02, | |
119 | MLX4_EVENT_TYPE_SQ_DRAINED = 0x03, | |
120 | MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13, | |
121 | MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14, | |
122 | MLX4_EVENT_TYPE_CQ_ERROR = 0x04, | |
123 | MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, | |
124 | MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06, | |
125 | MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07, | |
126 | MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, | |
127 | MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, | |
128 | MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, | |
129 | MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08, | |
130 | MLX4_EVENT_TYPE_PORT_CHANGE = 0x09, | |
131 | MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f, | |
132 | MLX4_EVENT_TYPE_ECC_DETECT = 0x0e, | |
623ed84b JM |
133 | MLX4_EVENT_TYPE_CMD = 0x0a, |
134 | MLX4_EVENT_TYPE_VEP_UPDATE = 0x19, | |
135 | MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18, | |
136 | MLX4_EVENT_TYPE_FLR_EVENT = 0x1c, | |
137 | MLX4_EVENT_TYPE_NONE = 0xff, | |
225c7b1f RD |
138 | }; |
139 | ||
140 | enum { | |
141 | MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1, | |
142 | MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4 | |
143 | }; | |
144 | ||
145 | enum { | |
146 | MLX4_PERM_LOCAL_READ = 1 << 10, | |
147 | MLX4_PERM_LOCAL_WRITE = 1 << 11, | |
148 | MLX4_PERM_REMOTE_READ = 1 << 12, | |
149 | MLX4_PERM_REMOTE_WRITE = 1 << 13, | |
150 | MLX4_PERM_ATOMIC = 1 << 14 | |
151 | }; | |
152 | ||
153 | enum { | |
154 | MLX4_OPCODE_NOP = 0x00, | |
155 | MLX4_OPCODE_SEND_INVAL = 0x01, | |
156 | MLX4_OPCODE_RDMA_WRITE = 0x08, | |
157 | MLX4_OPCODE_RDMA_WRITE_IMM = 0x09, | |
158 | MLX4_OPCODE_SEND = 0x0a, | |
159 | MLX4_OPCODE_SEND_IMM = 0x0b, | |
160 | MLX4_OPCODE_LSO = 0x0e, | |
161 | MLX4_OPCODE_RDMA_READ = 0x10, | |
162 | MLX4_OPCODE_ATOMIC_CS = 0x11, | |
163 | MLX4_OPCODE_ATOMIC_FA = 0x12, | |
6fa8f719 VS |
164 | MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14, |
165 | MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15, | |
225c7b1f RD |
166 | MLX4_OPCODE_BIND_MW = 0x18, |
167 | MLX4_OPCODE_FMR = 0x19, | |
168 | MLX4_OPCODE_LOCAL_INVAL = 0x1b, | |
169 | MLX4_OPCODE_CONFIG_CMD = 0x1f, | |
170 | ||
171 | MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, | |
172 | MLX4_RECV_OPCODE_SEND = 0x01, | |
173 | MLX4_RECV_OPCODE_SEND_IMM = 0x02, | |
174 | MLX4_RECV_OPCODE_SEND_INVAL = 0x03, | |
175 | ||
176 | MLX4_CQE_OPCODE_ERROR = 0x1e, | |
177 | MLX4_CQE_OPCODE_RESIZE = 0x16, | |
178 | }; | |
179 | ||
180 | enum { | |
181 | MLX4_STAT_RATE_OFFSET = 5 | |
182 | }; | |
183 | ||
da995a8a | 184 | enum mlx4_protocol { |
0345584e YP |
185 | MLX4_PROT_IB_IPV6 = 0, |
186 | MLX4_PROT_ETH, | |
187 | MLX4_PROT_IB_IPV4, | |
188 | MLX4_PROT_FCOE | |
da995a8a AS |
189 | }; |
190 | ||
29bdc883 VS |
191 | enum { |
192 | MLX4_MTT_FLAG_PRESENT = 1 | |
193 | }; | |
194 | ||
93fc9e1b YP |
195 | enum mlx4_qp_region { |
196 | MLX4_QP_REGION_FW = 0, | |
197 | MLX4_QP_REGION_ETH_ADDR, | |
198 | MLX4_QP_REGION_FC_ADDR, | |
199 | MLX4_QP_REGION_FC_EXCH, | |
200 | MLX4_NUM_QP_REGION | |
201 | }; | |
202 | ||
7ff93f8b | 203 | enum mlx4_port_type { |
623ed84b | 204 | MLX4_PORT_TYPE_NONE = 0, |
27bf91d6 YP |
205 | MLX4_PORT_TYPE_IB = 1, |
206 | MLX4_PORT_TYPE_ETH = 2, | |
207 | MLX4_PORT_TYPE_AUTO = 3 | |
7ff93f8b YP |
208 | }; |
209 | ||
2a2336f8 YP |
210 | enum mlx4_special_vlan_idx { |
211 | MLX4_NO_VLAN_IDX = 0, | |
212 | MLX4_VLAN_MISS_IDX, | |
213 | MLX4_VLAN_REGULAR | |
214 | }; | |
215 | ||
0345584e YP |
216 | enum mlx4_steer_type { |
217 | MLX4_MC_STEER = 0, | |
218 | MLX4_UC_STEER, | |
219 | MLX4_NUM_STEERS | |
220 | }; | |
221 | ||
93fc9e1b YP |
222 | enum { |
223 | MLX4_NUM_FEXCH = 64 * 1024, | |
224 | }; | |
225 | ||
5a0fd094 EC |
226 | enum { |
227 | MLX4_MAX_FAST_REG_PAGES = 511, | |
228 | }; | |
229 | ||
ea54b10c JM |
230 | static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor) |
231 | { | |
232 | return (major << 32) | (minor << 16) | subminor; | |
233 | } | |
234 | ||
225c7b1f RD |
235 | struct mlx4_caps { |
236 | u64 fw_ver; | |
623ed84b | 237 | u32 function; |
225c7b1f | 238 | int num_ports; |
5ae2a7a8 | 239 | int vl_cap[MLX4_MAX_PORTS + 1]; |
b79acb49 | 240 | int ib_mtu_cap[MLX4_MAX_PORTS + 1]; |
9a5aa622 | 241 | __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1]; |
b79acb49 YP |
242 | u64 def_mac[MLX4_MAX_PORTS + 1]; |
243 | int eth_mtu_cap[MLX4_MAX_PORTS + 1]; | |
5ae2a7a8 RD |
244 | int gid_table_len[MLX4_MAX_PORTS + 1]; |
245 | int pkey_table_len[MLX4_MAX_PORTS + 1]; | |
7699517d YP |
246 | int trans_type[MLX4_MAX_PORTS + 1]; |
247 | int vendor_oui[MLX4_MAX_PORTS + 1]; | |
248 | int wavelength[MLX4_MAX_PORTS + 1]; | |
249 | u64 trans_code[MLX4_MAX_PORTS + 1]; | |
225c7b1f RD |
250 | int local_ca_ack_delay; |
251 | int num_uars; | |
f5311ac1 | 252 | u32 uar_page_size; |
225c7b1f RD |
253 | int bf_reg_size; |
254 | int bf_regs_per_page; | |
255 | int max_sq_sg; | |
256 | int max_rq_sg; | |
257 | int num_qps; | |
258 | int max_wqes; | |
259 | int max_sq_desc_sz; | |
260 | int max_rq_desc_sz; | |
261 | int max_qp_init_rdma; | |
262 | int max_qp_dest_rdma; | |
225c7b1f RD |
263 | int sqp_start; |
264 | int num_srqs; | |
265 | int max_srq_wqes; | |
266 | int max_srq_sge; | |
267 | int reserved_srqs; | |
268 | int num_cqs; | |
269 | int max_cqes; | |
270 | int reserved_cqs; | |
271 | int num_eqs; | |
272 | int reserved_eqs; | |
b8dd786f | 273 | int num_comp_vectors; |
0b7ca5a9 | 274 | int comp_pool; |
225c7b1f | 275 | int num_mpts; |
a5bbe892 | 276 | int max_fmr_maps; |
2b8fb286 | 277 | int num_mtts; |
225c7b1f RD |
278 | int fmr_reserved_mtts; |
279 | int reserved_mtts; | |
280 | int reserved_mrws; | |
281 | int reserved_uars; | |
282 | int num_mgms; | |
283 | int num_amgms; | |
284 | int reserved_mcgs; | |
285 | int num_qp_per_mgm; | |
286 | int num_pds; | |
287 | int reserved_pds; | |
012a8ff5 SH |
288 | int max_xrcds; |
289 | int reserved_xrcds; | |
225c7b1f | 290 | int mtt_entry_sz; |
149983af | 291 | u32 max_msg_sz; |
225c7b1f | 292 | u32 page_size_cap; |
52eafc68 | 293 | u64 flags; |
95d04f07 RD |
294 | u32 bmme_flags; |
295 | u32 reserved_lkey; | |
225c7b1f | 296 | u16 stat_rate_support; |
5ae2a7a8 | 297 | u8 port_width_cap[MLX4_MAX_PORTS + 1]; |
b832be1e | 298 | int max_gso_sz; |
93fc9e1b YP |
299 | int reserved_qps_cnt[MLX4_NUM_QP_REGION]; |
300 | int reserved_qps; | |
301 | int reserved_qps_base[MLX4_NUM_QP_REGION]; | |
302 | int log_num_macs; | |
303 | int log_num_vlans; | |
304 | int log_num_prios; | |
7ff93f8b YP |
305 | enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1]; |
306 | u8 supported_type[MLX4_MAX_PORTS + 1]; | |
8d0fc7b6 YP |
307 | u8 suggested_type[MLX4_MAX_PORTS + 1]; |
308 | u8 default_sense[MLX4_MAX_PORTS + 1]; | |
65dab25d | 309 | u32 port_mask[MLX4_MAX_PORTS + 1]; |
27bf91d6 | 310 | enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1]; |
f2a3f6a3 | 311 | u32 max_counters; |
97285b78 | 312 | u8 ext_port_cap[MLX4_MAX_PORTS + 1]; |
225c7b1f RD |
313 | }; |
314 | ||
315 | struct mlx4_buf_list { | |
316 | void *buf; | |
317 | dma_addr_t map; | |
318 | }; | |
319 | ||
320 | struct mlx4_buf { | |
b57aacfa RD |
321 | struct mlx4_buf_list direct; |
322 | struct mlx4_buf_list *page_list; | |
225c7b1f RD |
323 | int nbufs; |
324 | int npages; | |
325 | int page_shift; | |
326 | }; | |
327 | ||
328 | struct mlx4_mtt { | |
2b8fb286 | 329 | u32 offset; |
225c7b1f RD |
330 | int order; |
331 | int page_shift; | |
332 | }; | |
333 | ||
6296883c YP |
334 | enum { |
335 | MLX4_DB_PER_PAGE = PAGE_SIZE / 4 | |
336 | }; | |
337 | ||
338 | struct mlx4_db_pgdir { | |
339 | struct list_head list; | |
340 | DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE); | |
341 | DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2); | |
342 | unsigned long *bits[2]; | |
343 | __be32 *db_page; | |
344 | dma_addr_t db_dma; | |
345 | }; | |
346 | ||
347 | struct mlx4_ib_user_db_page; | |
348 | ||
349 | struct mlx4_db { | |
350 | __be32 *db; | |
351 | union { | |
352 | struct mlx4_db_pgdir *pgdir; | |
353 | struct mlx4_ib_user_db_page *user_page; | |
354 | } u; | |
355 | dma_addr_t dma; | |
356 | int index; | |
357 | int order; | |
358 | }; | |
359 | ||
38ae6a53 YP |
360 | struct mlx4_hwq_resources { |
361 | struct mlx4_db db; | |
362 | struct mlx4_mtt mtt; | |
363 | struct mlx4_buf buf; | |
364 | }; | |
365 | ||
225c7b1f RD |
366 | struct mlx4_mr { |
367 | struct mlx4_mtt mtt; | |
368 | u64 iova; | |
369 | u64 size; | |
370 | u32 key; | |
371 | u32 pd; | |
372 | u32 access; | |
373 | int enabled; | |
374 | }; | |
375 | ||
8ad11fb6 JM |
376 | struct mlx4_fmr { |
377 | struct mlx4_mr mr; | |
378 | struct mlx4_mpt_entry *mpt; | |
379 | __be64 *mtts; | |
380 | dma_addr_t dma_handle; | |
381 | int max_pages; | |
382 | int max_maps; | |
383 | int maps; | |
384 | u8 page_shift; | |
385 | }; | |
386 | ||
225c7b1f RD |
387 | struct mlx4_uar { |
388 | unsigned long pfn; | |
389 | int index; | |
c1b43dca EC |
390 | struct list_head bf_list; |
391 | unsigned free_bf_bmap; | |
392 | void __iomem *map; | |
393 | void __iomem *bf_map; | |
394 | }; | |
395 | ||
396 | struct mlx4_bf { | |
397 | unsigned long offset; | |
398 | int buf_size; | |
399 | struct mlx4_uar *uar; | |
400 | void __iomem *reg; | |
225c7b1f RD |
401 | }; |
402 | ||
403 | struct mlx4_cq { | |
404 | void (*comp) (struct mlx4_cq *); | |
405 | void (*event) (struct mlx4_cq *, enum mlx4_event); | |
406 | ||
407 | struct mlx4_uar *uar; | |
408 | ||
409 | u32 cons_index; | |
410 | ||
411 | __be32 *set_ci_db; | |
412 | __be32 *arm_db; | |
413 | int arm_sn; | |
414 | ||
415 | int cqn; | |
b8dd786f | 416 | unsigned vector; |
225c7b1f RD |
417 | |
418 | atomic_t refcount; | |
419 | struct completion free; | |
420 | }; | |
421 | ||
422 | struct mlx4_qp { | |
423 | void (*event) (struct mlx4_qp *, enum mlx4_event); | |
424 | ||
425 | int qpn; | |
426 | ||
427 | atomic_t refcount; | |
428 | struct completion free; | |
429 | }; | |
430 | ||
431 | struct mlx4_srq { | |
432 | void (*event) (struct mlx4_srq *, enum mlx4_event); | |
433 | ||
434 | int srqn; | |
435 | int max; | |
436 | int max_gs; | |
437 | int wqe_shift; | |
438 | ||
439 | atomic_t refcount; | |
440 | struct completion free; | |
441 | }; | |
442 | ||
443 | struct mlx4_av { | |
444 | __be32 port_pd; | |
445 | u8 reserved1; | |
446 | u8 g_slid; | |
447 | __be16 dlid; | |
448 | u8 reserved2; | |
449 | u8 gid_index; | |
450 | u8 stat_rate; | |
451 | u8 hop_limit; | |
452 | __be32 sl_tclass_flowlabel; | |
453 | u8 dgid[16]; | |
454 | }; | |
455 | ||
fa417f7b EC |
456 | struct mlx4_eth_av { |
457 | __be32 port_pd; | |
458 | u8 reserved1; | |
459 | u8 smac_idx; | |
460 | u16 reserved2; | |
461 | u8 reserved3; | |
462 | u8 gid_index; | |
463 | u8 stat_rate; | |
464 | u8 hop_limit; | |
465 | __be32 sl_tclass_flowlabel; | |
466 | u8 dgid[16]; | |
467 | u32 reserved4[2]; | |
468 | __be16 vlan; | |
469 | u8 mac[6]; | |
470 | }; | |
471 | ||
472 | union mlx4_ext_av { | |
473 | struct mlx4_av ib; | |
474 | struct mlx4_eth_av eth; | |
475 | }; | |
476 | ||
f2a3f6a3 OG |
477 | struct mlx4_counter { |
478 | u8 reserved1[3]; | |
479 | u8 counter_mode; | |
480 | __be32 num_ifc; | |
481 | u32 reserved2[2]; | |
482 | __be64 rx_frames; | |
483 | __be64 rx_bytes; | |
484 | __be64 tx_frames; | |
485 | __be64 tx_bytes; | |
486 | }; | |
487 | ||
225c7b1f RD |
488 | struct mlx4_dev { |
489 | struct pci_dev *pdev; | |
490 | unsigned long flags; | |
623ed84b | 491 | unsigned long num_slaves; |
225c7b1f RD |
492 | struct mlx4_caps caps; |
493 | struct radix_tree_root qp_table_tree; | |
725c8999 | 494 | u8 rev_id; |
cd9281d8 | 495 | char board_id[MLX4_BOARD_ID_LEN]; |
ab9c17a0 | 496 | int num_vfs; |
225c7b1f RD |
497 | }; |
498 | ||
499 | struct mlx4_init_port_param { | |
500 | int set_guid0; | |
501 | int set_node_guid; | |
502 | int set_si_guid; | |
503 | u16 mtu; | |
504 | int port_width_cap; | |
505 | u16 vl_cap; | |
506 | u16 max_gid; | |
507 | u16 max_pkey; | |
508 | u64 guid0; | |
509 | u64 node_guid; | |
510 | u64 si_guid; | |
511 | }; | |
512 | ||
7ff93f8b YP |
513 | #define mlx4_foreach_port(port, dev, type) \ |
514 | for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ | |
65dab25d | 515 | if ((type) == (dev)->caps.port_mask[(port)]) |
7ff93f8b | 516 | |
65dab25d JM |
517 | #define mlx4_foreach_ib_transport_port(port, dev) \ |
518 | for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ | |
519 | if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \ | |
520 | ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE)) | |
623ed84b JM |
521 | |
522 | static inline int mlx4_is_master(struct mlx4_dev *dev) | |
523 | { | |
524 | return dev->flags & MLX4_FLAG_MASTER; | |
525 | } | |
526 | ||
527 | static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn) | |
528 | { | |
529 | return (qpn < dev->caps.sqp_start + 8); | |
530 | } | |
fa417f7b | 531 | |
623ed84b JM |
532 | static inline int mlx4_is_mfunc(struct mlx4_dev *dev) |
533 | { | |
534 | return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER); | |
535 | } | |
536 | ||
537 | static inline int mlx4_is_slave(struct mlx4_dev *dev) | |
538 | { | |
539 | return dev->flags & MLX4_FLAG_SLAVE; | |
540 | } | |
fa417f7b | 541 | |
225c7b1f RD |
542 | int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct, |
543 | struct mlx4_buf *buf); | |
544 | void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf); | |
1c69fc2a RD |
545 | static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset) |
546 | { | |
313abe55 | 547 | if (BITS_PER_LONG == 64 || buf->nbufs == 1) |
b57aacfa | 548 | return buf->direct.buf + offset; |
1c69fc2a | 549 | else |
b57aacfa | 550 | return buf->page_list[offset >> PAGE_SHIFT].buf + |
1c69fc2a RD |
551 | (offset & (PAGE_SIZE - 1)); |
552 | } | |
225c7b1f RD |
553 | |
554 | int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn); | |
555 | void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn); | |
012a8ff5 SH |
556 | int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn); |
557 | void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn); | |
225c7b1f RD |
558 | |
559 | int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar); | |
560 | void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar); | |
c1b43dca EC |
561 | int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf); |
562 | void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf); | |
225c7b1f RD |
563 | |
564 | int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift, | |
565 | struct mlx4_mtt *mtt); | |
566 | void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt); | |
567 | u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt); | |
568 | ||
569 | int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access, | |
570 | int npages, int page_shift, struct mlx4_mr *mr); | |
571 | void mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr); | |
572 | int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr); | |
573 | int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, | |
574 | int start_index, int npages, u64 *page_list); | |
575 | int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, | |
576 | struct mlx4_buf *buf); | |
577 | ||
6296883c YP |
578 | int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order); |
579 | void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db); | |
580 | ||
38ae6a53 YP |
581 | int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres, |
582 | int size, int max_direct); | |
583 | void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres, | |
584 | int size); | |
585 | ||
225c7b1f | 586 | int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt, |
e463c7b1 | 587 | struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq, |
b8dd786f | 588 | unsigned vector, int collapsed); |
225c7b1f RD |
589 | void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq); |
590 | ||
a3cdcbfa YP |
591 | int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base); |
592 | void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt); | |
593 | ||
594 | int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp); | |
225c7b1f RD |
595 | void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp); |
596 | ||
18abd5ea SH |
597 | int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn, |
598 | struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq); | |
225c7b1f RD |
599 | void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq); |
600 | int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark); | |
65541cb7 | 601 | int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark); |
225c7b1f | 602 | |
5ae2a7a8 | 603 | int mlx4_INIT_PORT(struct mlx4_dev *dev, int port); |
225c7b1f RD |
604 | int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port); |
605 | ||
ffe455ad EE |
606 | int mlx4_unicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], |
607 | int block_mcast_loopback, enum mlx4_protocol prot); | |
608 | int mlx4_unicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], | |
609 | enum mlx4_protocol prot); | |
521e575b | 610 | int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], |
da995a8a AS |
611 | int block_mcast_loopback, enum mlx4_protocol protocol); |
612 | int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], | |
613 | enum mlx4_protocol protocol); | |
1679200f YP |
614 | int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); |
615 | int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); | |
616 | int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port); | |
617 | int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port); | |
618 | int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode); | |
619 | ||
ffe455ad EE |
620 | int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac); |
621 | void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, u64 mac); | |
622 | int mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac); | |
623 | int mlx4_get_eth_qp(struct mlx4_dev *dev, u8 port, u64 mac, int *qpn); | |
624 | void mlx4_put_eth_qp(struct mlx4_dev *dev, u8 port, u64 mac, int qpn); | |
93ece0c1 | 625 | void mlx4_set_stats_bitmap(struct mlx4_dev *dev, u64 *stats_bitmap); |
2a2336f8 | 626 | |
4c3eb3ca | 627 | int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx); |
2a2336f8 YP |
628 | int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index); |
629 | void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index); | |
630 | ||
8ad11fb6 JM |
631 | int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list, |
632 | int npages, u64 iova, u32 *lkey, u32 *rkey); | |
633 | int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages, | |
634 | int max_maps, u8 page_shift, struct mlx4_fmr *fmr); | |
635 | int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr); | |
636 | void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr, | |
637 | u32 *lkey, u32 *rkey); | |
638 | int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr); | |
639 | int mlx4_SYNC_TPT(struct mlx4_dev *dev); | |
e7c1c2c4 | 640 | int mlx4_test_interrupts(struct mlx4_dev *dev); |
0b7ca5a9 YP |
641 | int mlx4_assign_eq(struct mlx4_dev *dev, char* name , int* vector); |
642 | void mlx4_release_eq(struct mlx4_dev *dev, int vec); | |
8ad11fb6 | 643 | |
14c07b13 YP |
644 | int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port); |
645 | int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port); | |
646 | ||
f2a3f6a3 OG |
647 | int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx); |
648 | void mlx4_counter_free(struct mlx4_dev *dev, u32 idx); | |
649 | ||
225c7b1f | 650 | #endif /* MLX4_DEVICE_H */ |