[mirror_ubuntu-hirsute-kernel.git] / include / linux / mlx4 / device.h

/*
 * Copyright (c) 2006, 2007 Cisco Systems, Inc.  All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *	- Redistributions of source code must retain the above
 *	  copyright notice, this list of conditions and the following
 *	  disclaimer.
 *
 *	- Redistributions in binary form must reproduce the above
 *	  copyright notice, this list of conditions and the following
 *	  disclaimer in the documentation and/or other materials
 *	  provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#ifndef MLX4_DEVICE_H
#define MLX4_DEVICE_H

#include <linux/pci.h>
#include <linux/completion.h>
#include <linux/radix-tree.h>

#include <linux/atomic.h>

#define MAX_MSIX_P_PORT		17
#define MAX_MSIX		64
#define MSIX_LEGACY_SZ		4
#define MIN_MSIX_P_PORT		5

enum {
	MLX4_FLAG_MSI_X		= 1 << 0,
	MLX4_FLAG_OLD_PORT_CMDS	= 1 << 1,
	MLX4_FLAG_MASTER	= 1 << 2,
	MLX4_FLAG_SLAVE		= 1 << 3,
	MLX4_FLAG_SRIOV		= 1 << 4,
};

enum {
	MLX4_MAX_PORTS		= 2
};

enum {
	MLX4_BOARD_ID_LEN = 64
};

enum {
	MLX4_MAX_NUM_PF		= 16,
	MLX4_MAX_NUM_VF		= 64,
	MLX4_MFUNC_MAX		= 80,
	MLX4_MFUNC_EQ_NUM	= 4,
	MLX4_MFUNC_MAX_EQES     = 8,
	MLX4_MFUNC_EQE_MASK     = (MLX4_MFUNC_MAX_EQES - 1)
};

enum {
	MLX4_DEV_CAP_FLAG_RC		= 1LL <<  0,
	MLX4_DEV_CAP_FLAG_UC		= 1LL <<  1,
	MLX4_DEV_CAP_FLAG_UD		= 1LL <<  2,
	MLX4_DEV_CAP_FLAG_XRC		= 1LL <<  3,
	MLX4_DEV_CAP_FLAG_SRQ		= 1LL <<  6,
	MLX4_DEV_CAP_FLAG_IPOIB_CSUM	= 1LL <<  7,
	MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR	= 1LL <<  8,
	MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR	= 1LL <<  9,
	MLX4_DEV_CAP_FLAG_DPDP		= 1LL << 12,
	MLX4_DEV_CAP_FLAG_BLH		= 1LL << 15,
	MLX4_DEV_CAP_FLAG_MEM_WINDOW	= 1LL << 16,
	MLX4_DEV_CAP_FLAG_APM		= 1LL << 17,
	MLX4_DEV_CAP_FLAG_ATOMIC	= 1LL << 18,
	MLX4_DEV_CAP_FLAG_RAW_MCAST	= 1LL << 19,
	MLX4_DEV_CAP_FLAG_UD_AV_PORT	= 1LL << 20,
	MLX4_DEV_CAP_FLAG_UD_MCAST	= 1LL << 21,
	MLX4_DEV_CAP_FLAG_IBOE		= 1LL << 30,
	MLX4_DEV_CAP_FLAG_UC_LOOPBACK	= 1LL << 32,
	MLX4_DEV_CAP_FLAG_FCS_KEEP	= 1LL << 34,
	MLX4_DEV_CAP_FLAG_WOL_PORT1	= 1LL << 37,
	MLX4_DEV_CAP_FLAG_WOL_PORT2	= 1LL << 38,
	MLX4_DEV_CAP_FLAG_UDP_RSS	= 1LL << 40,
	MLX4_DEV_CAP_FLAG_VEP_UC_STEER	= 1LL << 41,
	MLX4_DEV_CAP_FLAG_VEP_MC_STEER	= 1LL << 42,
	MLX4_DEV_CAP_FLAG_COUNTERS	= 1LL << 48
};

#define MLX4_ATTR_EXTENDED_PORT_INFO	cpu_to_be16(0xff90)

enum {
	MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO	= 1 <<  0
};

enum {
	MLX4_BMME_FLAG_LOCAL_INV	= 1 <<  6,
	MLX4_BMME_FLAG_REMOTE_INV	= 1 <<  7,
	MLX4_BMME_FLAG_TYPE_2_WIN	= 1 <<  9,
	MLX4_BMME_FLAG_RESERVED_LKEY	= 1 << 10,
	MLX4_BMME_FLAG_FAST_REG_WR	= 1 << 11,
};

enum mlx4_event {
	MLX4_EVENT_TYPE_COMP		   = 0x00,
	MLX4_EVENT_TYPE_PATH_MIG	   = 0x01,
	MLX4_EVENT_TYPE_COMM_EST	   = 0x02,
	MLX4_EVENT_TYPE_SQ_DRAINED	   = 0x03,
	MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE	   = 0x13,
	MLX4_EVENT_TYPE_SRQ_LIMIT	   = 0x14,
	MLX4_EVENT_TYPE_CQ_ERROR	   = 0x04,
	MLX4_EVENT_TYPE_WQ_CATAS_ERROR	   = 0x05,
	MLX4_EVENT_TYPE_EEC_CATAS_ERROR	   = 0x06,
	MLX4_EVENT_TYPE_PATH_MIG_FAILED	   = 0x07,
	MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
	MLX4_EVENT_TYPE_WQ_ACCESS_ERROR	   = 0x11,
	MLX4_EVENT_TYPE_SRQ_CATAS_ERROR	   = 0x12,
	MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR  = 0x08,
	MLX4_EVENT_TYPE_PORT_CHANGE	   = 0x09,
	MLX4_EVENT_TYPE_EQ_OVERFLOW	   = 0x0f,
	MLX4_EVENT_TYPE_ECC_DETECT	   = 0x0e,
	MLX4_EVENT_TYPE_CMD		   = 0x0a,
	MLX4_EVENT_TYPE_VEP_UPDATE	   = 0x19,
	MLX4_EVENT_TYPE_COMM_CHANNEL	   = 0x18,
	MLX4_EVENT_TYPE_FLR_EVENT	   = 0x1c,
	MLX4_EVENT_TYPE_NONE		   = 0xff,
};

enum {
	MLX4_PORT_CHANGE_SUBTYPE_DOWN	= 1,
	MLX4_PORT_CHANGE_SUBTYPE_ACTIVE	= 4
};

enum {
	MLX4_PERM_LOCAL_READ	= 1 << 10,
	MLX4_PERM_LOCAL_WRITE	= 1 << 11,
	MLX4_PERM_REMOTE_READ	= 1 << 12,
	MLX4_PERM_REMOTE_WRITE	= 1 << 13,
	MLX4_PERM_ATOMIC	= 1 << 14
};

enum {
	MLX4_OPCODE_NOP			= 0x00,
	MLX4_OPCODE_SEND_INVAL		= 0x01,
	MLX4_OPCODE_RDMA_WRITE		= 0x08,
	MLX4_OPCODE_RDMA_WRITE_IMM	= 0x09,
	MLX4_OPCODE_SEND		= 0x0a,
	MLX4_OPCODE_SEND_IMM		= 0x0b,
	MLX4_OPCODE_LSO			= 0x0e,
	MLX4_OPCODE_RDMA_READ		= 0x10,
	MLX4_OPCODE_ATOMIC_CS		= 0x11,
	MLX4_OPCODE_ATOMIC_FA		= 0x12,
	MLX4_OPCODE_MASKED_ATOMIC_CS	= 0x14,
	MLX4_OPCODE_MASKED_ATOMIC_FA	= 0x15,
	MLX4_OPCODE_BIND_MW		= 0x18,
	MLX4_OPCODE_FMR			= 0x19,
	MLX4_OPCODE_LOCAL_INVAL		= 0x1b,
	MLX4_OPCODE_CONFIG_CMD		= 0x1f,

	MLX4_RECV_OPCODE_RDMA_WRITE_IMM	= 0x00,
	MLX4_RECV_OPCODE_SEND		= 0x01,
	MLX4_RECV_OPCODE_SEND_IMM	= 0x02,
	MLX4_RECV_OPCODE_SEND_INVAL	= 0x03,

	MLX4_CQE_OPCODE_ERROR		= 0x1e,
	MLX4_CQE_OPCODE_RESIZE		= 0x16,
};

enum {
	MLX4_STAT_RATE_OFFSET	= 5
};

enum mlx4_protocol {
	MLX4_PROT_IB_IPV6 = 0,
	MLX4_PROT_ETH,
	MLX4_PROT_IB_IPV4,
	MLX4_PROT_FCOE
};

enum {
	MLX4_MTT_FLAG_PRESENT		= 1
};

enum mlx4_qp_region {
	MLX4_QP_REGION_FW = 0,
	MLX4_QP_REGION_ETH_ADDR,
	MLX4_QP_REGION_FC_ADDR,
	MLX4_QP_REGION_FC_EXCH,
	MLX4_NUM_QP_REGION
};

enum mlx4_port_type {
	MLX4_PORT_TYPE_NONE	= 0,
	MLX4_PORT_TYPE_IB	= 1,
	MLX4_PORT_TYPE_ETH	= 2,
	MLX4_PORT_TYPE_AUTO	= 3
};

enum mlx4_special_vlan_idx {
	MLX4_NO_VLAN_IDX        = 0,
	MLX4_VLAN_MISS_IDX,
	MLX4_VLAN_REGULAR
};

enum mlx4_steer_type {
	MLX4_MC_STEER = 0,
	MLX4_UC_STEER,
	MLX4_NUM_STEERS
};

enum {
	MLX4_NUM_FEXCH          = 64 * 1024,
};

enum {
	MLX4_MAX_FAST_REG_PAGES = 511,
};

static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
{
	return (major << 32) | (minor << 16) | subminor;
}

struct mlx4_caps {
	u64			fw_ver;
	u32			function;
	int			num_ports;
	int			vl_cap[MLX4_MAX_PORTS + 1];
	int			ib_mtu_cap[MLX4_MAX_PORTS + 1];
	__be32			ib_port_def_cap[MLX4_MAX_PORTS + 1];
	u64			def_mac[MLX4_MAX_PORTS + 1];
	int			eth_mtu_cap[MLX4_MAX_PORTS + 1];
	int			gid_table_len[MLX4_MAX_PORTS + 1];
	int			pkey_table_len[MLX4_MAX_PORTS + 1];
	int			trans_type[MLX4_MAX_PORTS + 1];
	int			vendor_oui[MLX4_MAX_PORTS + 1];
	int			wavelength[MLX4_MAX_PORTS + 1];
	u64			trans_code[MLX4_MAX_PORTS + 1];
	int			local_ca_ack_delay;
	int			num_uars;
	int			bf_reg_size;
	int			bf_regs_per_page;
	int			max_sq_sg;
	int			max_rq_sg;
	int			num_qps;
	int			max_wqes;
	int			max_sq_desc_sz;
	int			max_rq_desc_sz;
	int			max_qp_init_rdma;
	int			max_qp_dest_rdma;
	int			sqp_start;
	int			num_srqs;
	int			max_srq_wqes;
	int			max_srq_sge;
	int			reserved_srqs;
	int			num_cqs;
	int			max_cqes;
	int			reserved_cqs;
	int			num_eqs;
	int			reserved_eqs;
	int			num_comp_vectors;
	int			comp_pool;
	int			num_mpts;
	int			num_mtt_segs;
	int			mtts_per_seg;
	int			fmr_reserved_mtts;
	int			reserved_mtts;
	int			reserved_mrws;
	int			reserved_uars;
	int			num_mgms;
	int			num_amgms;
	int			reserved_mcgs;
	int			num_qp_per_mgm;
	int			num_pds;
	int			reserved_pds;
	int			max_xrcds;
	int			reserved_xrcds;
	int			mtt_entry_sz;
	u32			max_msg_sz;
	u32			page_size_cap;
	u64			flags;
	u32			bmme_flags;
	u32			reserved_lkey;
	u16			stat_rate_support;
	u8			port_width_cap[MLX4_MAX_PORTS + 1];
	int			max_gso_sz;
	int                     reserved_qps_cnt[MLX4_NUM_QP_REGION];
	int			reserved_qps;
	int                     reserved_qps_base[MLX4_NUM_QP_REGION];
	int                     log_num_macs;
	int                     log_num_vlans;
	int                     log_num_prios;
	enum mlx4_port_type	port_type[MLX4_MAX_PORTS + 1];
	u8			supported_type[MLX4_MAX_PORTS + 1];
	u32			port_mask[MLX4_MAX_PORTS + 1];
	enum mlx4_port_type	possible_type[MLX4_MAX_PORTS + 1];
	u32			max_counters;
	u8			ext_port_cap[MLX4_MAX_PORTS + 1];
};

struct mlx4_buf_list {
	void		       *buf;
	dma_addr_t		map;
};

struct mlx4_buf {
	struct mlx4_buf_list	direct;
	struct mlx4_buf_list   *page_list;
	int			nbufs;
	int			npages;
	int			page_shift;
};

struct mlx4_mtt {
	u32			first_seg;
	int			order;
	int			page_shift;
};

enum {
	MLX4_DB_PER_PAGE = PAGE_SIZE / 4
};

struct mlx4_db_pgdir {
	struct list_head	list;
	DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
	DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
	unsigned long	       *bits[2];
	__be32		       *db_page;
	dma_addr_t		db_dma;
};

struct mlx4_ib_user_db_page;

struct mlx4_db {
	__be32			*db;
	union {
		struct mlx4_db_pgdir		*pgdir;
		struct mlx4_ib_user_db_page	*user_page;
	}			u;
	dma_addr_t		dma;
	int			index;
	int			order;
};

struct mlx4_hwq_resources {
	struct mlx4_db		db;
	struct mlx4_mtt		mtt;
	struct mlx4_buf		buf;
};

struct mlx4_mr {
	struct mlx4_mtt		mtt;
	u64			iova;
	u64			size;
	u32			key;
	u32			pd;
	u32			access;
	int			enabled;
};

struct mlx4_fmr {
	struct mlx4_mr		mr;
	struct mlx4_mpt_entry  *mpt;
	__be64		       *mtts;
	dma_addr_t		dma_handle;
	int			max_pages;
	int			max_maps;
	int			maps;
	u8			page_shift;
};

struct mlx4_uar {
	unsigned long		pfn;
	int			index;
	struct list_head	bf_list;
	unsigned		free_bf_bmap;
	void __iomem	       *map;
	void __iomem	       *bf_map;
};

struct mlx4_bf {
	unsigned long		offset;
	int			buf_size;
	struct mlx4_uar	       *uar;
	void __iomem	       *reg;
};

struct mlx4_cq {
	void (*comp)		(struct mlx4_cq *);
	void (*event)		(struct mlx4_cq *, enum mlx4_event);

	struct mlx4_uar	       *uar;

	u32			cons_index;

	__be32		       *set_ci_db;
	__be32		       *arm_db;
	int			arm_sn;

	int			cqn;
	unsigned		vector;

	atomic_t		refcount;
	struct completion	free;
};

struct mlx4_qp {
	void (*event)		(struct mlx4_qp *, enum mlx4_event);

	int			qpn;

	atomic_t		refcount;
	struct completion	free;
};

struct mlx4_srq {
	void (*event)		(struct mlx4_srq *, enum mlx4_event);

	int			srqn;
	int			max;
	int			max_gs;
	int			wqe_shift;

	atomic_t		refcount;
	struct completion	free;
};

struct mlx4_av {
	__be32			port_pd;
	u8			reserved1;
	u8			g_slid;
	__be16			dlid;
	u8			reserved2;
	u8			gid_index;
	u8			stat_rate;
	u8			hop_limit;
	__be32			sl_tclass_flowlabel;
	u8			dgid[16];
};

struct mlx4_eth_av {
	__be32		port_pd;
	u8		reserved1;
	u8		smac_idx;
	u16		reserved2;
	u8		reserved3;
	u8		gid_index;
	u8		stat_rate;
	u8		hop_limit;
	__be32		sl_tclass_flowlabel;
	u8		dgid[16];
	u32		reserved4[2];
	__be16		vlan;
	u8		mac[6];
};

union mlx4_ext_av {
	struct mlx4_av		ib;
	struct mlx4_eth_av	eth;
};

struct mlx4_counter {
	u8	reserved1[3];
	u8	counter_mode;
	__be32	num_ifc;
	u32	reserved2[2];
	__be64	rx_frames;
	__be64	rx_bytes;
	__be64	tx_frames;
	__be64	tx_bytes;
};

struct mlx4_dev {
	struct pci_dev	       *pdev;
	unsigned long		flags;
	unsigned long		num_slaves;
	struct mlx4_caps	caps;
	struct radix_tree_root	qp_table_tree;
	u8			rev_id;
	char			board_id[MLX4_BOARD_ID_LEN];
};

struct mlx4_init_port_param {
	int			set_guid0;
	int			set_node_guid;
	int			set_si_guid;
	u16			mtu;
	int			port_width_cap;
	u16			vl_cap;
	u16			max_gid;
	u16			max_pkey;
	u64			guid0;
	u64			node_guid;
	u64			si_guid;
};

#define mlx4_foreach_port(port, dev, type)				\
	for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++)	\
		if ((type) == (dev)->caps.port_mask[(port)])

#define mlx4_foreach_ib_transport_port(port, dev)                         \
	for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++)	  \
		if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \
			((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))

static inline int mlx4_is_master(struct mlx4_dev *dev)
{
	return dev->flags & MLX4_FLAG_MASTER;
}

static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn)
{
	return (qpn < dev->caps.sqp_start + 8);
}

static inline int mlx4_is_mfunc(struct mlx4_dev *dev)
{
	return dev->flags & (MLX4_FLAG_SLAVE | MLX4_FLAG_MASTER);
}

static inline int mlx4_is_slave(struct mlx4_dev *dev)
{
	return dev->flags & MLX4_FLAG_SLAVE;
}

int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
		   struct mlx4_buf *buf);
void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf);
static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset)
{
	if (BITS_PER_LONG == 64 || buf->nbufs == 1)
		return buf->direct.buf + offset;
	else
		return buf->page_list[offset >> PAGE_SHIFT].buf +
			(offset & (PAGE_SIZE - 1));
}

int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn);
void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn);
void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);

int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar);
void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar);
int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf);
void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf);

int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
		  struct mlx4_mtt *mtt);
void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt);
u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt);

int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
		  int npages, int page_shift, struct mlx4_mr *mr);
void mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr);
int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr);
int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
		   int start_index, int npages, u64 *page_list);
int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
		       struct mlx4_buf *buf);

int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order);
void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db);

int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres,
		       int size, int max_direct);
void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres,
		       int size);

int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
		  struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq,
		  unsigned vector, int collapsed);
void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq);

int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base);
void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);

int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp);
void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp);

int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn,
		   struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq);
void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq);
int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark);
int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark);

int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);

int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
			  int block_mcast_loopback, enum mlx4_protocol protocol);
int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16],
			  enum mlx4_protocol protocol);
int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);

int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *qpn, u8 wrap);
void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, int qpn);
int mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac, u8 wrap);

int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx);
int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index);
void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index);

int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list,
		      int npages, u64 iova, u32 *lkey, u32 *rkey);
int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
		   int max_maps, u8 page_shift, struct mlx4_fmr *fmr);
int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr,
		    u32 *lkey, u32 *rkey);
int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr);
int mlx4_SYNC_TPT(struct mlx4_dev *dev);
int mlx4_test_interrupts(struct mlx4_dev *dev);
int mlx4_assign_eq(struct mlx4_dev *dev, char* name , int* vector);
void mlx4_release_eq(struct mlx4_dev *dev, int vec);

int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port);
int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port);

int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx);
void mlx4_counter_free(struct mlx4_dev *dev, u32 idx);

#endif /* MLX4_DEVICE_H */
Commit	Line	Data
225c7b1f RD	1	/*
	2	* Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
	3	*
	4	* This software is available to you under a choice of one of two
	5	* licenses. You may choose to be licensed under the terms of the GNU
	6	* General Public License (GPL) Version 2, available from the file
	7	* COPYING in the main directory of this source tree, or the
	8	* OpenIB.org BSD license below:
	9	*
	10	* Redistribution and use in source and binary forms, with or
	11	* without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistributions of source code must retain the above
	15	* copyright notice, this list of conditions and the following
	16	* disclaimer.
	17	*
	18	* - Redistributions in binary form must reproduce the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer in the documentation and/or other materials
	21	* provided with the distribution.
	22	*
	23	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	24	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	25	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	26	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	27	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	28	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	29	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	30	* SOFTWARE.
	31	*/
	32
	33	#ifndef MLX4_DEVICE_H
	34	#define MLX4_DEVICE_H
	35
	36	#include <linux/pci.h>
	37	#include <linux/completion.h>
	38	#include <linux/radix-tree.h>
	39
60063497	40	#include <linux/atomic.h>
225c7b1f	41
0b7ca5a9 YP	42	#define MAX_MSIX_P_PORT 17
	43	#define MAX_MSIX 64
	44	#define MSIX_LEGACY_SZ 4
	45	#define MIN_MSIX_P_PORT 5
	46
225c7b1f RD	47	enum {
225c7b1f RD	48	MLX4_FLAG_MSI_X = 1 << 0,
5ae2a7a8	49	MLX4_FLAG_OLD_PORT_CMDS = 1 << 1,
623ed84b JM	50	MLX4_FLAG_MASTER = 1 << 2,
	51	MLX4_FLAG_SLAVE = 1 << 3,
	52	MLX4_FLAG_SRIOV = 1 << 4,
225c7b1f RD	53	};
	54
	55	enum {
	56	MLX4_MAX_PORTS = 2
	57	};
	58
cd9281d8 JM	59	enum {
	60	MLX4_BOARD_ID_LEN = 64
	61	};
	62
623ed84b JM	63	enum {
	64	MLX4_MAX_NUM_PF = 16,
	65	MLX4_MAX_NUM_VF = 64,
	66	MLX4_MFUNC_MAX = 80,
	67	MLX4_MFUNC_EQ_NUM = 4,
	68	MLX4_MFUNC_MAX_EQES = 8,
	69	MLX4_MFUNC_EQE_MASK = (MLX4_MFUNC_MAX_EQES - 1)
	70	};
	71
225c7b1f	72	enum {
52eafc68 OG	73	MLX4_DEV_CAP_FLAG_RC = 1LL << 0,
	74	MLX4_DEV_CAP_FLAG_UC = 1LL << 1,
	75	MLX4_DEV_CAP_FLAG_UD = 1LL << 2,
012a8ff5	76	MLX4_DEV_CAP_FLAG_XRC = 1LL << 3,
52eafc68 OG	77	MLX4_DEV_CAP_FLAG_SRQ = 1LL << 6,
	78	MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1LL << 7,
	79	MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
	80	MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
	81	MLX4_DEV_CAP_FLAG_DPDP = 1LL << 12,
	82	MLX4_DEV_CAP_FLAG_BLH = 1LL << 15,
	83	MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1LL << 16,
	84	MLX4_DEV_CAP_FLAG_APM = 1LL << 17,
	85	MLX4_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
	86	MLX4_DEV_CAP_FLAG_RAW_MCAST = 1LL << 19,
	87	MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1LL << 20,
	88	MLX4_DEV_CAP_FLAG_UD_MCAST = 1LL << 21,
ccf86321 OG	89	MLX4_DEV_CAP_FLAG_IBOE = 1LL << 30,
ccf86321 OG	90	MLX4_DEV_CAP_FLAG_UC_LOOPBACK = 1LL << 32,
f3a9d1f2	91	MLX4_DEV_CAP_FLAG_FCS_KEEP = 1LL << 34,
559a9f1d OD	92	MLX4_DEV_CAP_FLAG_WOL_PORT1 = 1LL << 37,
559a9f1d OD	93	MLX4_DEV_CAP_FLAG_WOL_PORT2 = 1LL << 38,
ccf86321 OG	94	MLX4_DEV_CAP_FLAG_UDP_RSS = 1LL << 40,
ccf86321 OG	95	MLX4_DEV_CAP_FLAG_VEP_UC_STEER = 1LL << 41,
f2a3f6a3 OG	96	MLX4_DEV_CAP_FLAG_VEP_MC_STEER = 1LL << 42,
f2a3f6a3 OG	97	MLX4_DEV_CAP_FLAG_COUNTERS = 1LL << 48
225c7b1f RD	98	};
225c7b1f RD	99
97285b78 MA	100	#define MLX4_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
	101
	102	enum {
	103	MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0
	104	};
	105
95d04f07 RD	106	enum {
	107	MLX4_BMME_FLAG_LOCAL_INV = 1 << 6,
	108	MLX4_BMME_FLAG_REMOTE_INV = 1 << 7,
	109	MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9,
	110	MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10,
	111	MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11,
	112	};
	113
225c7b1f RD	114	enum mlx4_event {
	115	MLX4_EVENT_TYPE_COMP = 0x00,
	116	MLX4_EVENT_TYPE_PATH_MIG = 0x01,
	117	MLX4_EVENT_TYPE_COMM_EST = 0x02,
	118	MLX4_EVENT_TYPE_SQ_DRAINED = 0x03,
	119	MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13,
	120	MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14,
	121	MLX4_EVENT_TYPE_CQ_ERROR = 0x04,
	122	MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
	123	MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06,
	124	MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
	125	MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
	126	MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
	127	MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
	128	MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08,
	129	MLX4_EVENT_TYPE_PORT_CHANGE = 0x09,
	130	MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f,
	131	MLX4_EVENT_TYPE_ECC_DETECT = 0x0e,
623ed84b JM	132	MLX4_EVENT_TYPE_CMD = 0x0a,
	133	MLX4_EVENT_TYPE_VEP_UPDATE = 0x19,
	134	MLX4_EVENT_TYPE_COMM_CHANNEL = 0x18,
	135	MLX4_EVENT_TYPE_FLR_EVENT = 0x1c,
	136	MLX4_EVENT_TYPE_NONE = 0xff,
225c7b1f RD	137	};
	138
	139	enum {
	140	MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1,
	141	MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4
	142	};
	143
	144	enum {
	145	MLX4_PERM_LOCAL_READ = 1 << 10,
	146	MLX4_PERM_LOCAL_WRITE = 1 << 11,
	147	MLX4_PERM_REMOTE_READ = 1 << 12,
	148	MLX4_PERM_REMOTE_WRITE = 1 << 13,
	149	MLX4_PERM_ATOMIC = 1 << 14
	150	};
	151
	152	enum {
	153	MLX4_OPCODE_NOP = 0x00,
	154	MLX4_OPCODE_SEND_INVAL = 0x01,
	155	MLX4_OPCODE_RDMA_WRITE = 0x08,
	156	MLX4_OPCODE_RDMA_WRITE_IMM = 0x09,
	157	MLX4_OPCODE_SEND = 0x0a,
	158	MLX4_OPCODE_SEND_IMM = 0x0b,
	159	MLX4_OPCODE_LSO = 0x0e,
	160	MLX4_OPCODE_RDMA_READ = 0x10,
	161	MLX4_OPCODE_ATOMIC_CS = 0x11,
	162	MLX4_OPCODE_ATOMIC_FA = 0x12,
6fa8f719 VS	163	MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14,
6fa8f719 VS	164	MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15,
225c7b1f RD	165	MLX4_OPCODE_BIND_MW = 0x18,
	166	MLX4_OPCODE_FMR = 0x19,
	167	MLX4_OPCODE_LOCAL_INVAL = 0x1b,
	168	MLX4_OPCODE_CONFIG_CMD = 0x1f,
	169
	170	MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
	171	MLX4_RECV_OPCODE_SEND = 0x01,
	172	MLX4_RECV_OPCODE_SEND_IMM = 0x02,
	173	MLX4_RECV_OPCODE_SEND_INVAL = 0x03,
	174
	175	MLX4_CQE_OPCODE_ERROR = 0x1e,
	176	MLX4_CQE_OPCODE_RESIZE = 0x16,
	177	};
	178
	179	enum {
	180	MLX4_STAT_RATE_OFFSET = 5
	181	};
	182
da995a8a	183	enum mlx4_protocol {
0345584e YP	184	MLX4_PROT_IB_IPV6 = 0,
	185	MLX4_PROT_ETH,
	186	MLX4_PROT_IB_IPV4,
	187	MLX4_PROT_FCOE
da995a8a AS	188	};
da995a8a AS	189
29bdc883 VS	190	enum {
	191	MLX4_MTT_FLAG_PRESENT = 1
	192	};
	193
93fc9e1b YP	194	enum mlx4_qp_region {
	195	MLX4_QP_REGION_FW = 0,
	196	MLX4_QP_REGION_ETH_ADDR,
	197	MLX4_QP_REGION_FC_ADDR,
	198	MLX4_QP_REGION_FC_EXCH,
	199	MLX4_NUM_QP_REGION
	200	};
	201
7ff93f8b	202	enum mlx4_port_type {
623ed84b	203	MLX4_PORT_TYPE_NONE = 0,
27bf91d6 YP	204	MLX4_PORT_TYPE_IB = 1,
	205	MLX4_PORT_TYPE_ETH = 2,
	206	MLX4_PORT_TYPE_AUTO = 3
7ff93f8b YP	207	};
7ff93f8b YP	208
2a2336f8 YP	209	enum mlx4_special_vlan_idx {
	210	MLX4_NO_VLAN_IDX = 0,
	211	MLX4_VLAN_MISS_IDX,
	212	MLX4_VLAN_REGULAR
	213	};
	214
0345584e YP	215	enum mlx4_steer_type {
	216	MLX4_MC_STEER = 0,
	217	MLX4_UC_STEER,
	218	MLX4_NUM_STEERS
	219	};
	220
93fc9e1b YP	221	enum {
	222	MLX4_NUM_FEXCH = 64 * 1024,
	223	};
	224
5a0fd094 EC	225	enum {
	226	MLX4_MAX_FAST_REG_PAGES = 511,
	227	};
	228
ea54b10c JM	229	static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
	230	{
	231	return (major << 32) \| (minor << 16) \| subminor;
	232	}
	233
225c7b1f RD	234	struct mlx4_caps {
225c7b1f RD	235	u64 fw_ver;
623ed84b	236	u32 function;
225c7b1f	237	int num_ports;
5ae2a7a8	238	int vl_cap[MLX4_MAX_PORTS + 1];
b79acb49	239	int ib_mtu_cap[MLX4_MAX_PORTS + 1];
9a5aa622	240	__be32 ib_port_def_cap[MLX4_MAX_PORTS + 1];
b79acb49 YP	241	u64 def_mac[MLX4_MAX_PORTS + 1];
b79acb49 YP	242	int eth_mtu_cap[MLX4_MAX_PORTS + 1];
5ae2a7a8 RD	243	int gid_table_len[MLX4_MAX_PORTS + 1];
5ae2a7a8 RD	244	int pkey_table_len[MLX4_MAX_PORTS + 1];
7699517d YP	245	int trans_type[MLX4_MAX_PORTS + 1];
	246	int vendor_oui[MLX4_MAX_PORTS + 1];
	247	int wavelength[MLX4_MAX_PORTS + 1];
	248	u64 trans_code[MLX4_MAX_PORTS + 1];
225c7b1f RD	249	int local_ca_ack_delay;
	250	int num_uars;
	251	int bf_reg_size;
	252	int bf_regs_per_page;
	253	int max_sq_sg;
	254	int max_rq_sg;
	255	int num_qps;
	256	int max_wqes;
	257	int max_sq_desc_sz;
	258	int max_rq_desc_sz;
	259	int max_qp_init_rdma;
	260	int max_qp_dest_rdma;
225c7b1f RD	261	int sqp_start;
	262	int num_srqs;
	263	int max_srq_wqes;
	264	int max_srq_sge;
	265	int reserved_srqs;
	266	int num_cqs;
	267	int max_cqes;
	268	int reserved_cqs;
	269	int num_eqs;
	270	int reserved_eqs;
b8dd786f	271	int num_comp_vectors;
0b7ca5a9	272	int comp_pool;
225c7b1f RD	273	int num_mpts;
225c7b1f RD	274	int num_mtt_segs;
ab6bf42e	275	int mtts_per_seg;
225c7b1f RD	276	int fmr_reserved_mtts;
	277	int reserved_mtts;
	278	int reserved_mrws;
	279	int reserved_uars;
	280	int num_mgms;
	281	int num_amgms;
	282	int reserved_mcgs;
	283	int num_qp_per_mgm;
	284	int num_pds;
	285	int reserved_pds;
012a8ff5 SH	286	int max_xrcds;
012a8ff5 SH	287	int reserved_xrcds;
225c7b1f	288	int mtt_entry_sz;
149983af	289	u32 max_msg_sz;
225c7b1f	290	u32 page_size_cap;
52eafc68	291	u64 flags;
95d04f07 RD	292	u32 bmme_flags;
95d04f07 RD	293	u32 reserved_lkey;
225c7b1f	294	u16 stat_rate_support;
5ae2a7a8	295	u8 port_width_cap[MLX4_MAX_PORTS + 1];
b832be1e	296	int max_gso_sz;
93fc9e1b YP	297	int reserved_qps_cnt[MLX4_NUM_QP_REGION];
	298	int reserved_qps;
	299	int reserved_qps_base[MLX4_NUM_QP_REGION];
	300	int log_num_macs;
	301	int log_num_vlans;
	302	int log_num_prios;
7ff93f8b YP	303	enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
7ff93f8b YP	304	u8 supported_type[MLX4_MAX_PORTS + 1];
65dab25d	305	u32 port_mask[MLX4_MAX_PORTS + 1];
27bf91d6	306	enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1];
f2a3f6a3	307	u32 max_counters;
97285b78	308	u8 ext_port_cap[MLX4_MAX_PORTS + 1];
225c7b1f RD	309	};
	310
	311	struct mlx4_buf_list {
	312	void *buf;
	313	dma_addr_t map;
	314	};
	315
	316	struct mlx4_buf {
b57aacfa RD	317	struct mlx4_buf_list direct;
b57aacfa RD	318	struct mlx4_buf_list *page_list;
225c7b1f RD	319	int nbufs;
	320	int npages;
	321	int page_shift;
	322	};
	323
	324	struct mlx4_mtt {
	325	u32 first_seg;
	326	int order;
	327	int page_shift;
	328	};
	329
6296883c YP	330	enum {
	331	MLX4_DB_PER_PAGE = PAGE_SIZE / 4
	332	};
	333
	334	struct mlx4_db_pgdir {
	335	struct list_head list;
	336	DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE);
	337	DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2);
	338	unsigned long *bits[2];
	339	__be32 *db_page;
	340	dma_addr_t db_dma;
	341	};
	342
	343	struct mlx4_ib_user_db_page;
	344
	345	struct mlx4_db {
	346	__be32 *db;
	347	union {
	348	struct mlx4_db_pgdir *pgdir;
	349	struct mlx4_ib_user_db_page *user_page;
	350	} u;
	351	dma_addr_t dma;
	352	int index;
	353	int order;
	354	};
	355
38ae6a53 YP	356	struct mlx4_hwq_resources {
	357	struct mlx4_db db;
	358	struct mlx4_mtt mtt;
	359	struct mlx4_buf buf;
	360	};
	361
225c7b1f RD	362	struct mlx4_mr {
	363	struct mlx4_mtt mtt;
	364	u64 iova;
	365	u64 size;
	366	u32 key;
	367	u32 pd;
	368	u32 access;
	369	int enabled;
	370	};
	371
8ad11fb6 JM	372	struct mlx4_fmr {
	373	struct mlx4_mr mr;
	374	struct mlx4_mpt_entry *mpt;
	375	__be64 *mtts;
	376	dma_addr_t dma_handle;
	377	int max_pages;
	378	int max_maps;
	379	int maps;
	380	u8 page_shift;
	381	};
	382
225c7b1f RD	383	struct mlx4_uar {
	384	unsigned long pfn;
	385	int index;
c1b43dca EC	386	struct list_head bf_list;
	387	unsigned free_bf_bmap;
	388	void __iomem *map;
	389	void __iomem *bf_map;
	390	};
	391
	392	struct mlx4_bf {
	393	unsigned long offset;
	394	int buf_size;
	395	struct mlx4_uar *uar;
	396	void __iomem *reg;
225c7b1f RD	397	};
	398
	399	struct mlx4_cq {
	400	void (comp) (struct mlx4_cq );
	401	void (event) (struct mlx4_cq , enum mlx4_event);
	402
	403	struct mlx4_uar *uar;
	404
	405	u32 cons_index;
	406
	407	__be32 *set_ci_db;
	408	__be32 *arm_db;
	409	int arm_sn;
	410
	411	int cqn;
b8dd786f	412	unsigned vector;
225c7b1f RD	413
	414	atomic_t refcount;
	415	struct completion free;
	416	};
	417
	418	struct mlx4_qp {
	419	void (event) (struct mlx4_qp , enum mlx4_event);
	420
	421	int qpn;
	422
	423	atomic_t refcount;
	424	struct completion free;
	425	};
	426
	427	struct mlx4_srq {
	428	void (event) (struct mlx4_srq , enum mlx4_event);
	429
	430	int srqn;
	431	int max;
	432	int max_gs;
	433	int wqe_shift;
	434
	435	atomic_t refcount;
	436	struct completion free;
	437	};
	438
	439	struct mlx4_av {
	440	__be32 port_pd;
	441	u8 reserved1;
	442	u8 g_slid;
	443	__be16 dlid;
	444	u8 reserved2;
	445	u8 gid_index;
	446	u8 stat_rate;
	447	u8 hop_limit;
	448	__be32 sl_tclass_flowlabel;
	449	u8 dgid[16];
	450	};
	451
fa417f7b EC	452	struct mlx4_eth_av {
	453	__be32 port_pd;
	454	u8 reserved1;
	455	u8 smac_idx;
	456	u16 reserved2;
	457	u8 reserved3;
	458	u8 gid_index;
	459	u8 stat_rate;
	460	u8 hop_limit;
	461	__be32 sl_tclass_flowlabel;
	462	u8 dgid[16];
	463	u32 reserved4[2];
	464	__be16 vlan;
	465	u8 mac[6];
	466	};
	467
	468	union mlx4_ext_av {
	469	struct mlx4_av ib;
	470	struct mlx4_eth_av eth;
	471	};
	472
f2a3f6a3 OG	473	struct mlx4_counter {
	474	u8 reserved1[3];
	475	u8 counter_mode;
	476	__be32 num_ifc;
	477	u32 reserved2[2];
	478	__be64 rx_frames;
	479	__be64 rx_bytes;
	480	__be64 tx_frames;
	481	__be64 tx_bytes;
	482	};
	483
225c7b1f RD	484	struct mlx4_dev {
	485	struct pci_dev *pdev;
	486	unsigned long flags;
623ed84b	487	unsigned long num_slaves;
225c7b1f RD	488	struct mlx4_caps caps;
225c7b1f RD	489	struct radix_tree_root qp_table_tree;
725c8999	490	u8 rev_id;
cd9281d8	491	char board_id[MLX4_BOARD_ID_LEN];
225c7b1f RD	492	};
	493
	494	struct mlx4_init_port_param {
	495	int set_guid0;
	496	int set_node_guid;
	497	int set_si_guid;
	498	u16 mtu;
	499	int port_width_cap;
	500	u16 vl_cap;
	501	u16 max_gid;
	502	u16 max_pkey;
	503	u64 guid0;
	504	u64 node_guid;
	505	u64 si_guid;
	506	};
	507
7ff93f8b YP	508	#define mlx4_foreach_port(port, dev, type) \
7ff93f8b YP	509	for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
65dab25d	510	if ((type) == (dev)->caps.port_mask[(port)])
7ff93f8b	511
65dab25d JM	512	#define mlx4_foreach_ib_transport_port(port, dev) \
	513	for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \
	514	if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) \|\| \
	515	((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
623ed84b JM	516
	517	static inline int mlx4_is_master(struct mlx4_dev *dev)
	518	{
	519	return dev->flags & MLX4_FLAG_MASTER;
	520	}
	521
	522	static inline int mlx4_is_qp_reserved(struct mlx4_dev *dev, u32 qpn)
	523	{
	524	return (qpn < dev->caps.sqp_start + 8);
	525	}
fa417f7b	526
623ed84b JM	527	static inline int mlx4_is_mfunc(struct mlx4_dev *dev)
	528	{
	529	return dev->flags & (MLX4_FLAG_SLAVE \| MLX4_FLAG_MASTER);
	530	}
	531
	532	static inline int mlx4_is_slave(struct mlx4_dev *dev)
	533	{
	534	return dev->flags & MLX4_FLAG_SLAVE;
	535	}
fa417f7b	536
225c7b1f RD	537	int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct,
	538	struct mlx4_buf *buf);
	539	void mlx4_buf_free(struct mlx4_dev dev, int size, struct mlx4_buf buf);
1c69fc2a RD	540	static inline void mlx4_buf_offset(struct mlx4_buf buf, int offset)
1c69fc2a RD	541	{
313abe55	542	if (BITS_PER_LONG == 64 \|\| buf->nbufs == 1)
b57aacfa	543	return buf->direct.buf + offset;
1c69fc2a	544	else
b57aacfa	545	return buf->page_list[offset >> PAGE_SHIFT].buf +
1c69fc2a RD	546	(offset & (PAGE_SIZE - 1));
1c69fc2a RD	547	}
225c7b1f RD	548
	549	int mlx4_pd_alloc(struct mlx4_dev dev, u32 pdn);
	550	void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn);
012a8ff5 SH	551	int mlx4_xrcd_alloc(struct mlx4_dev dev, u32 xrcdn);
012a8ff5 SH	552	void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn);
225c7b1f RD	553
	554	int mlx4_uar_alloc(struct mlx4_dev dev, struct mlx4_uar uar);
	555	void mlx4_uar_free(struct mlx4_dev dev, struct mlx4_uar uar);
c1b43dca EC	556	int mlx4_bf_alloc(struct mlx4_dev dev, struct mlx4_bf bf);
c1b43dca EC	557	void mlx4_bf_free(struct mlx4_dev dev, struct mlx4_bf bf);
225c7b1f RD	558
	559	int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift,
	560	struct mlx4_mtt *mtt);
	561	void mlx4_mtt_cleanup(struct mlx4_dev dev, struct mlx4_mtt mtt);
	562	u64 mlx4_mtt_addr(struct mlx4_dev dev, struct mlx4_mtt mtt);
	563
	564	int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access,
	565	int npages, int page_shift, struct mlx4_mr *mr);
	566	void mlx4_mr_free(struct mlx4_dev dev, struct mlx4_mr mr);
	567	int mlx4_mr_enable(struct mlx4_dev dev, struct mlx4_mr mr);
	568	int mlx4_write_mtt(struct mlx4_dev dev, struct mlx4_mtt mtt,
	569	int start_index, int npages, u64 *page_list);
	570	int mlx4_buf_write_mtt(struct mlx4_dev dev, struct mlx4_mtt mtt,
	571	struct mlx4_buf *buf);
	572
6296883c YP	573	int mlx4_db_alloc(struct mlx4_dev dev, struct mlx4_db db, int order);
	574	void mlx4_db_free(struct mlx4_dev dev, struct mlx4_db db);
	575
38ae6a53 YP	576	int mlx4_alloc_hwq_res(struct mlx4_dev dev, struct mlx4_hwq_resources wqres,
	577	int size, int max_direct);
	578	void mlx4_free_hwq_res(struct mlx4_dev mdev, struct mlx4_hwq_resources wqres,
	579	int size);
	580
225c7b1f	581	int mlx4_cq_alloc(struct mlx4_dev dev, int nent, struct mlx4_mtt mtt,
e463c7b1	582	struct mlx4_uar uar, u64 db_rec, struct mlx4_cq cq,
b8dd786f	583	unsigned vector, int collapsed);
225c7b1f RD	584	void mlx4_cq_free(struct mlx4_dev dev, struct mlx4_cq cq);
225c7b1f RD	585
a3cdcbfa YP	586	int mlx4_qp_reserve_range(struct mlx4_dev dev, int cnt, int align, int base);
	587	void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt);
	588
	589	int mlx4_qp_alloc(struct mlx4_dev dev, int qpn, struct mlx4_qp qp);
225c7b1f RD	590	void mlx4_qp_free(struct mlx4_dev dev, struct mlx4_qp qp);
225c7b1f RD	591
18abd5ea SH	592	int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcdn,
18abd5ea SH	593	struct mlx4_mtt mtt, u64 db_rec, struct mlx4_srq srq);
225c7b1f RD	594	void mlx4_srq_free(struct mlx4_dev dev, struct mlx4_srq srq);
225c7b1f RD	595	int mlx4_srq_arm(struct mlx4_dev dev, struct mlx4_srq srq, int limit_watermark);
65541cb7	596	int mlx4_srq_query(struct mlx4_dev dev, struct mlx4_srq srq, int *limit_watermark);
225c7b1f	597
5ae2a7a8	598	int mlx4_INIT_PORT(struct mlx4_dev *dev, int port);
225c7b1f RD	599	int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port);
225c7b1f RD	600
521e575b	601	int mlx4_multicast_attach(struct mlx4_dev dev, struct mlx4_qp qp, u8 gid[16],
da995a8a AS	602	int block_mcast_loopback, enum mlx4_protocol protocol);
	603	int mlx4_multicast_detach(struct mlx4_dev dev, struct mlx4_qp qp, u8 gid[16],
	604	enum mlx4_protocol protocol);
1679200f YP	605	int mlx4_multicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
	606	int mlx4_multicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
	607	int mlx4_unicast_promisc_add(struct mlx4_dev *dev, u32 qpn, u8 port);
	608	int mlx4_unicast_promisc_remove(struct mlx4_dev *dev, u32 qpn, u8 port);
	609	int mlx4_SET_MCAST_FLTR(struct mlx4_dev *dev, u8 port, u64 mac, u64 clear, u8 mode);
	610
	611	int mlx4_register_mac(struct mlx4_dev dev, u8 port, u64 mac, int qpn, u8 wrap);
	612	void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, int qpn);
	613	int mlx4_replace_mac(struct mlx4_dev *dev, u8 port, int qpn, u64 new_mac, u8 wrap);
2a2336f8	614
4c3eb3ca	615	int mlx4_find_cached_vlan(struct mlx4_dev dev, u8 port, u16 vid, int idx);
2a2336f8 YP	616	int mlx4_register_vlan(struct mlx4_dev dev, u8 port, u16 vlan, int index);
	617	void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index);
	618
8ad11fb6 JM	619	int mlx4_map_phys_fmr(struct mlx4_dev dev, struct mlx4_fmr fmr, u64 *page_list,
	620	int npages, u64 iova, u32 lkey, u32 rkey);
	621	int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages,
	622	int max_maps, u8 page_shift, struct mlx4_fmr *fmr);
	623	int mlx4_fmr_enable(struct mlx4_dev dev, struct mlx4_fmr fmr);
	624	void mlx4_fmr_unmap(struct mlx4_dev dev, struct mlx4_fmr fmr,
	625	u32 lkey, u32 rkey);
	626	int mlx4_fmr_free(struct mlx4_dev dev, struct mlx4_fmr fmr);
	627	int mlx4_SYNC_TPT(struct mlx4_dev *dev);
e7c1c2c4	628	int mlx4_test_interrupts(struct mlx4_dev *dev);
0b7ca5a9 YP	629	int mlx4_assign_eq(struct mlx4_dev dev, char name , int* vector);
0b7ca5a9 YP	630	void mlx4_release_eq(struct mlx4_dev *dev, int vec);
8ad11fb6	631
14c07b13 YP	632	int mlx4_wol_read(struct mlx4_dev dev, u64 config, int port);
	633	int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port);
	634
f2a3f6a3 OG	635	int mlx4_counter_alloc(struct mlx4_dev dev, u32 idx);
	636	void mlx4_counter_free(struct mlx4_dev *dev, u32 idx);
	637
225c7b1f	638	#endif /* MLX4_DEVICE_H */