[mirror_ubuntu-artful-kernel.git] / include / linux / mlx4 / qp.h

/*
 * Copyright (c) 2007 Cisco Systems, Inc.  All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *	- Redistributions of source code must retain the above
 *	  copyright notice, this list of conditions and the following
 *	  disclaimer.
 *
 *	- Redistributions in binary form must reproduce the above
 *	  copyright notice, this list of conditions and the following
 *	  disclaimer in the documentation and/or other materials
 *	  provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#ifndef MLX4_QP_H
#define MLX4_QP_H

#include <linux/types.h>
#include <linux/if_ether.h>

#include <linux/mlx4/device.h>

#define MLX4_INVALID_LKEY	0x100

enum mlx4_qp_optpar {
	MLX4_QP_OPTPAR_ALT_ADDR_PATH		= 1 << 0,
	MLX4_QP_OPTPAR_RRE			= 1 << 1,
	MLX4_QP_OPTPAR_RAE			= 1 << 2,
	MLX4_QP_OPTPAR_RWE			= 1 << 3,
	MLX4_QP_OPTPAR_PKEY_INDEX		= 1 << 4,
	MLX4_QP_OPTPAR_Q_KEY			= 1 << 5,
	MLX4_QP_OPTPAR_RNR_TIMEOUT		= 1 << 6,
	MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH	= 1 << 7,
	MLX4_QP_OPTPAR_SRA_MAX			= 1 << 8,
	MLX4_QP_OPTPAR_RRA_MAX			= 1 << 9,
	MLX4_QP_OPTPAR_PM_STATE			= 1 << 10,
	MLX4_QP_OPTPAR_RETRY_COUNT		= 1 << 12,
	MLX4_QP_OPTPAR_RNR_RETRY		= 1 << 13,
	MLX4_QP_OPTPAR_ACK_TIMEOUT		= 1 << 14,
	MLX4_QP_OPTPAR_SCHED_QUEUE		= 1 << 16,
	MLX4_QP_OPTPAR_COUNTER_INDEX		= 1 << 20,
	MLX4_QP_OPTPAR_VLAN_STRIPPING		= 1 << 21,
};

enum mlx4_qp_state {
	MLX4_QP_STATE_RST			= 0,
	MLX4_QP_STATE_INIT			= 1,
	MLX4_QP_STATE_RTR			= 2,
	MLX4_QP_STATE_RTS			= 3,
	MLX4_QP_STATE_SQER			= 4,
	MLX4_QP_STATE_SQD			= 5,
	MLX4_QP_STATE_ERR			= 6,
	MLX4_QP_STATE_SQ_DRAINING		= 7,
	MLX4_QP_NUM_STATE
};

enum {
	MLX4_QP_ST_RC				= 0x0,
	MLX4_QP_ST_UC				= 0x1,
	MLX4_QP_ST_RD				= 0x2,
	MLX4_QP_ST_UD				= 0x3,
	MLX4_QP_ST_XRC				= 0x6,
	MLX4_QP_ST_MLX				= 0x7
};

enum {
	MLX4_QP_PM_MIGRATED			= 0x3,
	MLX4_QP_PM_ARMED			= 0x0,
	MLX4_QP_PM_REARM			= 0x1
};

enum {
	/* params1 */
	MLX4_QP_BIT_SRE				= 1 << 15,
	MLX4_QP_BIT_SWE				= 1 << 14,
	MLX4_QP_BIT_SAE				= 1 << 13,
	/* params2 */
	MLX4_QP_BIT_RRE				= 1 << 15,
	MLX4_QP_BIT_RWE				= 1 << 14,
	MLX4_QP_BIT_RAE				= 1 << 13,
	MLX4_QP_BIT_FPP				= 1 <<	3,
	MLX4_QP_BIT_RIC				= 1 <<	4,
};

enum {
	MLX4_RSS_HASH_XOR			= 0,
	MLX4_RSS_HASH_TOP			= 1,

	MLX4_RSS_UDP_IPV6			= 1 << 0,
	MLX4_RSS_UDP_IPV4			= 1 << 1,
	MLX4_RSS_TCP_IPV6			= 1 << 2,
	MLX4_RSS_IPV6				= 1 << 3,
	MLX4_RSS_TCP_IPV4			= 1 << 4,
	MLX4_RSS_IPV4				= 1 << 5,

	MLX4_RSS_BY_OUTER_HEADERS		= 0 << 6,
	MLX4_RSS_BY_INNER_HEADERS		= 2 << 6,
	MLX4_RSS_BY_INNER_HEADERS_IPONLY	= 3 << 6,

	/* offset of mlx4_rss_context within mlx4_qp_context.pri_path */
	MLX4_RSS_OFFSET_IN_QPC_PRI_PATH		= 0x24,
	/* offset of being RSS indirection QP within mlx4_qp_context.flags */
	MLX4_RSS_QPC_FLAG_OFFSET		= 13,
};

#define MLX4_EN_RSS_KEY_SIZE 40

struct mlx4_rss_context {
	__be32			base_qpn;
	__be32			default_qpn;
	u16			reserved;
	u8			hash_fn;
	u8			flags;
	__be32			rss_key[MLX4_EN_RSS_KEY_SIZE / sizeof(__be32)];
	__be32			base_qpn_udp;
};

struct mlx4_qp_path {
	u8			fl;
	union {
		u8			vlan_control;
		u8			control;
	};
	u8			disable_pkey_check;
	u8			pkey_index;
	u8			counter_index;
	u8			grh_mylmc;
	__be16			rlid;
	u8			ackto;
	u8			mgid_index;
	u8			static_rate;
	u8			hop_limit;
	__be32			tclass_flowlabel;
	u8			rgid[16];
	u8			sched_queue;
	u8			vlan_index;
	u8			feup;
	u8			fvl_rx;
	u8			reserved4[2];
	u8			dmac[ETH_ALEN];
};

enum { /* fl */
	MLX4_FL_CV	= 1 << 6,
	MLX4_FL_SV	= 1 << 5,
	MLX4_FL_ETH_HIDE_CQE_VLAN	= 1 << 2,
	MLX4_FL_ETH_SRC_CHECK_MC_LB	= 1 << 1,
	MLX4_FL_ETH_SRC_CHECK_UC_LB	= 1 << 0,
};

enum { /* control */
	MLX4_CTRL_ETH_SRC_CHECK_IF_COUNTER	= 1 << 7,
};

enum { /* vlan_control */
	MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED	= 1 << 6,
	MLX4_VLAN_CTRL_ETH_TX_BLOCK_PRIO_TAGGED	= 1 << 5, /* 802.1p priority tag */
	MLX4_VLAN_CTRL_ETH_TX_BLOCK_UNTAGGED	= 1 << 4,
	MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED	= 1 << 2,
	MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED	= 1 << 1, /* 802.1p priority tag */
	MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED	= 1 << 0
};

enum { /* feup */
	MLX4_FEUP_FORCE_ETH_UP          = 1 << 6, /* force Eth UP */
	MLX4_FSM_FORCE_ETH_SRC_MAC      = 1 << 5, /* force Source MAC */
	MLX4_FVL_FORCE_ETH_VLAN         = 1 << 3  /* force Eth vlan */
};

enum { /* fvl_rx */
	MLX4_FVL_RX_FORCE_ETH_VLAN      = 1 << 0 /* enforce Eth rx vlan */
};

struct mlx4_qp_context {
	__be32			flags;
	__be32			pd;
	u8			mtu_msgmax;
	u8			rq_size_stride;
	u8			sq_size_stride;
	u8			rlkey_roce_mode;
	__be32			usr_page;
	__be32			local_qpn;
	__be32			remote_qpn;
	struct			mlx4_qp_path pri_path;
	struct			mlx4_qp_path alt_path;
	__be32			params1;
	u32			reserved1;
	__be32			next_send_psn;
	__be32			cqn_send;
	__be16                  roce_entropy;
	__be16                  reserved2[3];
	__be32			last_acked_psn;
	__be32			ssn;
	__be32			params2;
	__be32			rnr_nextrecvpsn;
	__be32			xrcd;
	__be32			cqn_recv;
	__be64			db_rec_addr;
	__be32			qkey;
	__be32			srqn;
	__be32			msn;
	__be16			rq_wqe_counter;
	__be16			sq_wqe_counter;
	u32			reserved3;
	__be16			rate_limit_params;
	u8			reserved4;
	u8			qos_vport;
	__be32			param3;
	__be32			nummmcpeers_basemkey;
	u8			log_page_size;
	u8			reserved5[2];
	u8			mtt_base_addr_h;
	__be32			mtt_base_addr_l;
	u32			reserved6[10];
};

struct mlx4_update_qp_context {
	__be64			qp_mask;
	__be64			primary_addr_path_mask;
	__be64			secondary_addr_path_mask;
	u64			reserved1;
	struct mlx4_qp_context	qp_context;
	u64			reserved2[58];
};

enum {
	MLX4_UPD_QP_MASK_PM_STATE	= 32,
	MLX4_UPD_QP_MASK_VSD		= 33,
	MLX4_UPD_QP_MASK_QOS_VPP	= 34,
	MLX4_UPD_QP_MASK_RATE_LIMIT	= 35,
};

enum {
	MLX4_UPD_QP_PATH_MASK_PKEY_INDEX		= 0 + 32,
	MLX4_UPD_QP_PATH_MASK_FSM			= 1 + 32,
	MLX4_UPD_QP_PATH_MASK_MAC_INDEX			= 2 + 32,
	MLX4_UPD_QP_PATH_MASK_FVL			= 3 + 32,
	MLX4_UPD_QP_PATH_MASK_CV			= 4 + 32,
	MLX4_UPD_QP_PATH_MASK_VLAN_INDEX		= 5 + 32,
	MLX4_UPD_QP_PATH_MASK_ETH_HIDE_CQE_VLAN		= 6 + 32,
	MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_UNTAGGED	= 7 + 32,
	MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_1P		= 8 + 32,
	MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_TAGGED	= 9 + 32,
	MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_UNTAGGED	= 10 + 32,
	MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_1P		= 11 + 32,
	MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_TAGGED	= 12 + 32,
	MLX4_UPD_QP_PATH_MASK_FEUP			= 13 + 32,
	MLX4_UPD_QP_PATH_MASK_SCHED_QUEUE		= 14 + 32,
	MLX4_UPD_QP_PATH_MASK_IF_COUNTER_INDEX		= 15 + 32,
	MLX4_UPD_QP_PATH_MASK_FVL_RX			= 16 + 32,
	MLX4_UPD_QP_PATH_MASK_ETH_SRC_CHECK_UC_LB	= 18 + 32,
	MLX4_UPD_QP_PATH_MASK_ETH_SRC_CHECK_MC_LB	= 19 + 32,
	MLX4_UPD_QP_PATH_MASK_SV			= 22 + 32,
};

enum { /* param3 */
	MLX4_STRIP_VLAN = 1 << 30
};

/* Which firmware version adds support for NEC (NoErrorCompletion) bit */
#define MLX4_FW_VER_WQE_CTRL_NEC mlx4_fw_ver(2, 2, 232)

enum {
	MLX4_WQE_CTRL_NEC		= 1 << 29,
	MLX4_WQE_CTRL_IIP		= 1 << 28,
	MLX4_WQE_CTRL_ILP		= 1 << 27,
	MLX4_WQE_CTRL_FENCE		= 1 << 6,
	MLX4_WQE_CTRL_CQ_UPDATE		= 3 << 2,
	MLX4_WQE_CTRL_SOLICITED		= 1 << 1,
	MLX4_WQE_CTRL_IP_CSUM		= 1 << 4,
	MLX4_WQE_CTRL_TCP_UDP_CSUM	= 1 << 5,
	MLX4_WQE_CTRL_INS_CVLAN		= 1 << 6,
	MLX4_WQE_CTRL_INS_SVLAN		= 1 << 7,
	MLX4_WQE_CTRL_STRONG_ORDER	= 1 << 7,
	MLX4_WQE_CTRL_FORCE_LOOPBACK	= 1 << 0,
};

union mlx4_wqe_qpn_vlan {
	struct {
		__be16	vlan_tag;
		u8	ins_vlan;
		u8	fence_size;
	};
	__be32		bf_qpn;
};

struct mlx4_wqe_ctrl_seg {
	__be32			owner_opcode;
	union mlx4_wqe_qpn_vlan	qpn_vlan;
	/*
	 * High 24 bits are SRC remote buffer; low 8 bits are flags:
	 * [7]   SO (strong ordering)
	 * [5]   TCP/UDP checksum
	 * [4]   IP checksum
	 * [3:2] C (generate completion queue entry)
	 * [1]   SE (solicited event)
	 * [0]   FL (force loopback)
	 */
	union {
		__be32			srcrb_flags;
		__be16			srcrb_flags16[2];
	};
	/*
	 * imm is immediate data for send/RDMA write w/ immediate;
	 * also invalidation key for send with invalidate; input
	 * modifier for WQEs on CCQs.
	 */
	__be32			imm;
};

enum {
	MLX4_WQE_MLX_VL15	= 1 << 17,
	MLX4_WQE_MLX_SLR	= 1 << 16
};

struct mlx4_wqe_mlx_seg {
	u8			owner;
	u8			reserved1[2];
	u8			opcode;
	__be16			sched_prio;
	u8			reserved2;
	u8			size;
	/*
	 * [17]    VL15
	 * [16]    SLR
	 * [15:12] static rate
	 * [11:8]  SL
	 * [4]     ICRC
	 * [3:2]   C
	 * [0]     FL (force loopback)
	 */
	__be32			flags;
	__be16			rlid;
	u16			reserved3;
};

struct mlx4_wqe_datagram_seg {
	__be32			av[8];
	__be32			dqpn;
	__be32			qkey;
	__be16			vlan;
	u8			mac[ETH_ALEN];
};

struct mlx4_wqe_lso_seg {
	__be32			mss_hdr_size;
	__be32			header[0];
};

enum mlx4_wqe_bind_seg_flags2 {
	MLX4_WQE_BIND_ZERO_BASED = (1 << 30),
	MLX4_WQE_BIND_TYPE_2     = (1 << 31),
};

struct mlx4_wqe_bind_seg {
	__be32			flags1;
	__be32			flags2;
	__be32			new_rkey;
	__be32			lkey;
	__be64			addr;
	__be64			length;
};

enum {
	MLX4_WQE_FMR_PERM_LOCAL_READ	= 1 << 27,
	MLX4_WQE_FMR_PERM_LOCAL_WRITE	= 1 << 28,
	MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ	= 1 << 29,
	MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE	= 1 << 30,
	MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC	= 1 << 31
};

struct mlx4_wqe_fmr_seg {
	__be32			flags;
	__be32			mem_key;
	__be64			buf_list;
	__be64			start_addr;
	__be64			reg_len;
	__be32			offset;
	__be32			page_size;
	u32			reserved[2];
};

struct mlx4_wqe_fmr_ext_seg {
	u8			flags;
	u8			reserved;
	__be16			app_mask;
	__be16			wire_app_tag;
	__be16			mem_app_tag;
	__be32			wire_ref_tag_base;
	__be32			mem_ref_tag_base;
};

struct mlx4_wqe_local_inval_seg {
	u64			reserved1;
	__be32			mem_key;
	u32			reserved2;
	u64			reserved3[2];
};

struct mlx4_wqe_raddr_seg {
	__be64			raddr;
	__be32			rkey;
	u32			reserved;
};

struct mlx4_wqe_atomic_seg {
	__be64			swap_add;
	__be64			compare;
};

struct mlx4_wqe_masked_atomic_seg {
	__be64			swap_add;
	__be64			compare;
	__be64			swap_add_mask;
	__be64			compare_mask;
};

struct mlx4_wqe_data_seg {
	__be32			byte_count;
	__be32			lkey;
	__be64			addr;
};

enum {
	MLX4_INLINE_ALIGN	= 64,
	MLX4_INLINE_SEG		= 1 << 31,
};

struct mlx4_wqe_inline_seg {
	__be32			byte_count;
};

enum mlx4_update_qp_attr {
	MLX4_UPDATE_QP_SMAC		= 1 << 0,
	MLX4_UPDATE_QP_VSD		= 1 << 1,
	MLX4_UPDATE_QP_RATE_LIMIT	= 1 << 2,
	MLX4_UPDATE_QP_QOS_VPORT	= 1 << 3,
	MLX4_UPDATE_QP_ETH_SRC_CHECK_MC_LB      = 1 << 4,
	MLX4_UPDATE_QP_SUPPORTED_ATTRS	= (1 << 5) - 1
};

enum mlx4_update_qp_params_flags {
	MLX4_UPDATE_QP_PARAMS_FLAGS_ETH_CHECK_MC_LB     = 1 << 0,
	MLX4_UPDATE_QP_PARAMS_FLAGS_VSD_ENABLE		= 1 << 1,
};

struct mlx4_update_qp_params {
	u8	smac_index;
	u8	qos_vport;
	u32	flags;
	u16	rate_unit;
	u16	rate_val;
};

struct mlx4_qp *mlx4_qp_lookup(struct mlx4_dev *dev, u32 qpn);
int mlx4_update_qp(struct mlx4_dev *dev, u32 qpn,
		   enum mlx4_update_qp_attr attr,
		   struct mlx4_update_qp_params *params);
int mlx4_qp_modify(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
		   enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state,
		   struct mlx4_qp_context *context, enum mlx4_qp_optpar optpar,
		   int sqd_event, struct mlx4_qp *qp);

int mlx4_qp_query(struct mlx4_dev *dev, struct mlx4_qp *qp,
		  struct mlx4_qp_context *context);

int mlx4_qp_to_ready(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
		     struct mlx4_qp_context *context,
		     struct mlx4_qp *qp, enum mlx4_qp_state *qp_state);

static inline struct mlx4_qp *__mlx4_qp_lookup(struct mlx4_dev *dev, u32 qpn)
{
	return radix_tree_lookup(&dev->qp_table_tree, qpn & (dev->caps.num_qps - 1));
}

void mlx4_qp_remove(struct mlx4_dev *dev, struct mlx4_qp *qp);

static inline u16 folded_qp(u32 q)
{
	u16 res;

	res = ((q & 0xff) ^ ((q & 0xff0000) >> 16)) | (q & 0xff00);
	return res;
}

u16 mlx4_qp_roce_entropy(struct mlx4_dev *dev, u32 qpn);

#endif /* MLX4_QP_H */
Commit	Line	Data
225c7b1f RD	1	/*
	2	* Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
	3	*
	4	* This software is available to you under a choice of one of two
	5	* licenses. You may choose to be licensed under the terms of the GNU
	6	* General Public License (GPL) Version 2, available from the file
	7	* COPYING in the main directory of this source tree, or the
	8	* OpenIB.org BSD license below:
	9	*
	10	* Redistribution and use in source and binary forms, with or
	11	* without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistributions of source code must retain the above
	15	* copyright notice, this list of conditions and the following
	16	* disclaimer.
	17	*
	18	* - Redistributions in binary form must reproduce the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer in the documentation and/or other materials
	21	* provided with the distribution.
	22	*
	23	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	24	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	25	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	26	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	27	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	28	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	29	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	30	* SOFTWARE.
	31	*/
	32
	33	#ifndef MLX4_QP_H
	34	#define MLX4_QP_H
	35
	36	#include <linux/types.h>
574e2af7	37	#include <linux/if_ether.h>
225c7b1f RD	38
	39	#include <linux/mlx4/device.h>
	40
	41	#define MLX4_INVALID_LKEY 0x100
	42
	43	enum mlx4_qp_optpar {
	44	MLX4_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0,
	45	MLX4_QP_OPTPAR_RRE = 1 << 1,
	46	MLX4_QP_OPTPAR_RAE = 1 << 2,
	47	MLX4_QP_OPTPAR_RWE = 1 << 3,
	48	MLX4_QP_OPTPAR_PKEY_INDEX = 1 << 4,
	49	MLX4_QP_OPTPAR_Q_KEY = 1 << 5,
	50	MLX4_QP_OPTPAR_RNR_TIMEOUT = 1 << 6,
	51	MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
	52	MLX4_QP_OPTPAR_SRA_MAX = 1 << 8,
	53	MLX4_QP_OPTPAR_RRA_MAX = 1 << 9,
	54	MLX4_QP_OPTPAR_PM_STATE = 1 << 10,
	55	MLX4_QP_OPTPAR_RETRY_COUNT = 1 << 12,
	56	MLX4_QP_OPTPAR_RNR_RETRY = 1 << 13,
	57	MLX4_QP_OPTPAR_ACK_TIMEOUT = 1 << 14,
cfcde11c	58	MLX4_QP_OPTPAR_SCHED_QUEUE = 1 << 16,
09e05c3f MB	59	MLX4_QP_OPTPAR_COUNTER_INDEX = 1 << 20,
09e05c3f MB	60	MLX4_QP_OPTPAR_VLAN_STRIPPING = 1 << 21,
225c7b1f RD	61	};
	62
	63	enum mlx4_qp_state {
	64	MLX4_QP_STATE_RST = 0,
	65	MLX4_QP_STATE_INIT = 1,
	66	MLX4_QP_STATE_RTR = 2,
	67	MLX4_QP_STATE_RTS = 3,
	68	MLX4_QP_STATE_SQER = 4,
	69	MLX4_QP_STATE_SQD = 5,
	70	MLX4_QP_STATE_ERR = 6,
	71	MLX4_QP_STATE_SQ_DRAINING = 7,
	72	MLX4_QP_NUM_STATE
	73	};
	74
	75	enum {
	76	MLX4_QP_ST_RC = 0x0,
	77	MLX4_QP_ST_UC = 0x1,
	78	MLX4_QP_ST_RD = 0x2,
	79	MLX4_QP_ST_UD = 0x3,
0a1405da	80	MLX4_QP_ST_XRC = 0x6,
225c7b1f RD	81	MLX4_QP_ST_MLX = 0x7
	82	};
	83
	84	enum {
	85	MLX4_QP_PM_MIGRATED = 0x3,
	86	MLX4_QP_PM_ARMED = 0x0,
	87	MLX4_QP_PM_REARM = 0x1
	88	};
	89
	90	enum {
	91	/* params1 */
	92	MLX4_QP_BIT_SRE = 1 << 15,
	93	MLX4_QP_BIT_SWE = 1 << 14,
	94	MLX4_QP_BIT_SAE = 1 << 13,
	95	/* params2 */
	96	MLX4_QP_BIT_RRE = 1 << 15,
	97	MLX4_QP_BIT_RWE = 1 << 14,
	98	MLX4_QP_BIT_RAE = 1 << 13,
59e14e32	99	MLX4_QP_BIT_FPP = 1 << 3,
225c7b1f RD	100	MLX4_QP_BIT_RIC = 1 << 4,
	101	};
	102
876f6e67 OG	103	enum {
	104	MLX4_RSS_HASH_XOR = 0,
	105	MLX4_RSS_HASH_TOP = 1,
	106
	107	MLX4_RSS_UDP_IPV6 = 1 << 0,
	108	MLX4_RSS_UDP_IPV4 = 1 << 1,
	109	MLX4_RSS_TCP_IPV6 = 1 << 2,
	110	MLX4_RSS_IPV6 = 1 << 3,
	111	MLX4_RSS_TCP_IPV4 = 1 << 4,
	112	MLX4_RSS_IPV4 = 1 << 5,
	113
7ffdf726 OG	114	MLX4_RSS_BY_OUTER_HEADERS = 0 << 6,
	115	MLX4_RSS_BY_INNER_HEADERS = 2 << 6,
	116	MLX4_RSS_BY_INNER_HEADERS_IPONLY = 3 << 6,
	117
876f6e67 OG	118	/* offset of mlx4_rss_context within mlx4_qp_context.pri_path */
	119	MLX4_RSS_OFFSET_IN_QPC_PRI_PATH = 0x24,
	120	/* offset of being RSS indirection QP within mlx4_qp_context.flags */
	121	MLX4_RSS_QPC_FLAG_OFFSET = 13,
	122	};
	123
b9d1ab7e ED	124	#define MLX4_EN_RSS_KEY_SIZE 40
b9d1ab7e ED	125
876f6e67 OG	126	struct mlx4_rss_context {
	127	__be32 base_qpn;
	128	__be32 default_qpn;
	129	u16 reserved;
	130	u8 hash_fn;
	131	u8 flags;
b9d1ab7e	132	__be32 rss_key[MLX4_EN_RSS_KEY_SIZE / sizeof(__be32)];
876f6e67 OG	133	__be32 base_qpn_udp;
	134	};
	135
225c7b1f RD	136	struct mlx4_qp_path {
225c7b1f RD	137	u8 fl;
9a892835 MG	138	union {
	139	u8 vlan_control;
	140	u8 control;
	141	};
1ffeb2eb	142	u8 disable_pkey_check;
225c7b1f	143	u8 pkey_index;
98a13e48	144	u8 counter_index;
225c7b1f RD	145	u8 grh_mylmc;
	146	__be16 rlid;
	147	u8 ackto;
	148	u8 mgid_index;
	149	u8 static_rate;
	150	u8 hop_limit;
	151	__be32 tclass_flowlabel;
	152	u8 rgid[16];
	153	u8 sched_queue;
4c3eb3ca	154	u8 vlan_index;
0e98b523	155	u8 feup;
7677fc96	156	u8 fvl_rx;
98a13e48	157	u8 reserved4[2];
574e2af7	158	u8 dmac[ETH_ALEN];
225c7b1f RD	159	};
225c7b1f RD	160
7677fc96	161	enum { /* fl */
9a892835	162	MLX4_FL_CV = 1 << 6,
7c3d21c8	163	MLX4_FL_SV = 1 << 5,
9a892835 MG	164	MLX4_FL_ETH_HIDE_CQE_VLAN = 1 << 2,
	165	MLX4_FL_ETH_SRC_CHECK_MC_LB = 1 << 1,
	166	MLX4_FL_ETH_SRC_CHECK_UC_LB = 1 << 0,
7677fc96	167	};
9a892835 MG	168
	169	enum { /* control */
	170	MLX4_CTRL_ETH_SRC_CHECK_IF_COUNTER = 1 << 7,
	171	};
	172
7677fc96 RE	173	enum { /* vlan_control */
7677fc96 RE	174	MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED = 1 << 6,
0a6eac24 RE	175	MLX4_VLAN_CTRL_ETH_TX_BLOCK_PRIO_TAGGED = 1 << 5, /* 802.1p priority tag */
0a6eac24 RE	176	MLX4_VLAN_CTRL_ETH_TX_BLOCK_UNTAGGED = 1 << 4,
7677fc96 RE	177	MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED = 1 << 2,
	178	MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED = 1 << 1, /* 802.1p priority tag */
	179	MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED = 1 << 0
	180	};
	181
	182	enum { /* feup */
	183	MLX4_FEUP_FORCE_ETH_UP = 1 << 6, /* force Eth UP */
	184	MLX4_FSM_FORCE_ETH_SRC_MAC = 1 << 5, /* force Source MAC */
	185	MLX4_FVL_FORCE_ETH_VLAN = 1 << 3 /* force Eth vlan */
	186	};
	187
	188	enum { /* fvl_rx */
	189	MLX4_FVL_RX_FORCE_ETH_VLAN = 1 << 0 /* enforce Eth rx vlan */
	190	};
	191
225c7b1f RD	192	struct mlx4_qp_context {
	193	__be32 flags;
	194	__be32 pd;
	195	u8 mtu_msgmax;
	196	u8 rq_size_stride;
	197	u8 sq_size_stride;
3b5daf28	198	u8 rlkey_roce_mode;
225c7b1f RD	199	__be32 usr_page;
	200	__be32 local_qpn;
	201	__be32 remote_qpn;
	202	struct mlx4_qp_path pri_path;
	203	struct mlx4_qp_path alt_path;
	204	__be32 params1;
	205	u32 reserved1;
	206	__be32 next_send_psn;
	207	__be32 cqn_send;
3f723f42 MS	208	__be16 roce_entropy;
3f723f42 MS	209	__be16 reserved2[3];
225c7b1f RD	210	__be32 last_acked_psn;
	211	__be32 ssn;
	212	__be32 params2;
	213	__be32 rnr_nextrecvpsn;
0a1405da	214	__be32 xrcd;
225c7b1f RD	215	__be32 cqn_recv;
	216	__be64 db_rec_addr;
	217	__be32 qkey;
	218	__be32 srqn;
	219	__be32 msn;
	220	__be16 rq_wqe_counter;
	221	__be16 sq_wqe_counter;
fc31e256 OG	222	u32 reserved3;
fc31e256 OG	223	__be16 rate_limit_params;
08068cd5 IS	224	u8 reserved4;
08068cd5 IS	225	u8 qos_vport;
225c7b1f RD	226	__be32 param3;
	227	__be32 nummmcpeers_basemkey;
	228	u8 log_page_size;
fc31e256	229	u8 reserved5[2];
225c7b1f RD	230	u8 mtt_base_addr_h;
225c7b1f RD	231	__be32 mtt_base_addr_l;
fc31e256	232	u32 reserved6[10];
225c7b1f RD	233	};
225c7b1f RD	234
b01978ca JM	235	struct mlx4_update_qp_context {
	236	__be64 qp_mask;
	237	__be64 primary_addr_path_mask;
	238	__be64 secondary_addr_path_mask;
	239	u64 reserved1;
	240	struct mlx4_qp_context qp_context;
	241	u64 reserved2[58];
	242	};
	243
	244	enum {
	245	MLX4_UPD_QP_MASK_PM_STATE = 32,
	246	MLX4_UPD_QP_MASK_VSD = 33,
08068cd5	247	MLX4_UPD_QP_MASK_QOS_VPP = 34,
fc31e256	248	MLX4_UPD_QP_MASK_RATE_LIMIT = 35,
b01978ca JM	249	};
	250
	251	enum {
	252	MLX4_UPD_QP_PATH_MASK_PKEY_INDEX = 0 + 32,
	253	MLX4_UPD_QP_PATH_MASK_FSM = 1 + 32,
	254	MLX4_UPD_QP_PATH_MASK_MAC_INDEX = 2 + 32,
	255	MLX4_UPD_QP_PATH_MASK_FVL = 3 + 32,
	256	MLX4_UPD_QP_PATH_MASK_CV = 4 + 32,
	257	MLX4_UPD_QP_PATH_MASK_VLAN_INDEX = 5 + 32,
	258	MLX4_UPD_QP_PATH_MASK_ETH_HIDE_CQE_VLAN = 6 + 32,
	259	MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_UNTAGGED = 7 + 32,
	260	MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_1P = 8 + 32,
	261	MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_TAGGED = 9 + 32,
	262	MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_UNTAGGED = 10 + 32,
	263	MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_1P = 11 + 32,
	264	MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_TAGGED = 12 + 32,
	265	MLX4_UPD_QP_PATH_MASK_FEUP = 13 + 32,
	266	MLX4_UPD_QP_PATH_MASK_SCHED_QUEUE = 14 + 32,
	267	MLX4_UPD_QP_PATH_MASK_IF_COUNTER_INDEX = 15 + 32,
	268	MLX4_UPD_QP_PATH_MASK_FVL_RX = 16 + 32,
9a892835 MG	269	MLX4_UPD_QP_PATH_MASK_ETH_SRC_CHECK_UC_LB = 18 + 32,
9a892835 MG	270	MLX4_UPD_QP_PATH_MASK_ETH_SRC_CHECK_MC_LB = 19 + 32,
7c3d21c8	271	MLX4_UPD_QP_PATH_MASK_SV = 22 + 32,
b01978ca JM	272	};
b01978ca JM	273
7677fc96 RE	274	enum { /* param3 */
	275	MLX4_STRIP_VLAN = 1 << 30
	276	};
	277
ea54b10c JM	278	/* Which firmware version adds support for NEC (NoErrorCompletion) bit */
	279	#define MLX4_FW_VER_WQE_CTRL_NEC mlx4_fw_ver(2, 2, 232)
	280
225c7b1f	281	enum {
8ff095ec	282	MLX4_WQE_CTRL_NEC = 1 << 29,
7ffdf726 OG	283	MLX4_WQE_CTRL_IIP = 1 << 28,
7ffdf726 OG	284	MLX4_WQE_CTRL_ILP = 1 << 27,
8ff095ec EC	285	MLX4_WQE_CTRL_FENCE = 1 << 6,
	286	MLX4_WQE_CTRL_CQ_UPDATE = 3 << 2,
	287	MLX4_WQE_CTRL_SOLICITED = 1 << 1,
	288	MLX4_WQE_CTRL_IP_CSUM = 1 << 4,
	289	MLX4_WQE_CTRL_TCP_UDP_CSUM = 1 << 5,
e802f8e4	290	MLX4_WQE_CTRL_INS_CVLAN = 1 << 6,
e38af4fa	291	MLX4_WQE_CTRL_INS_SVLAN = 1 << 7,
2ac6bf4d	292	MLX4_WQE_CTRL_STRONG_ORDER = 1 << 7,
96dfa684	293	MLX4_WQE_CTRL_FORCE_LOOPBACK = 1 << 0,
225c7b1f RD	294	};
225c7b1f RD	295
224e92e0 BB	296	union mlx4_wqe_qpn_vlan {
	297	struct {
	298	__be16 vlan_tag;
	299	u8 ins_vlan;
	300	u8 fence_size;
	301	};
	302	__be32 bf_qpn;
	303	};
	304
225c7b1f RD	305	struct mlx4_wqe_ctrl_seg {
225c7b1f RD	306	__be32 owner_opcode;
224e92e0	307	union mlx4_wqe_qpn_vlan qpn_vlan;
225c7b1f RD	308	/*
	309	* High 24 bits are SRC remote buffer; low 8 bits are flags:
	310	* [7] SO (strong ordering)
	311	* [5] TCP/UDP checksum
	312	* [4] IP checksum
	313	* [3:2] C (generate completion queue entry)
	314	* [1] SE (solicited event)
60d6fe99	315	* [0] FL (force loopback)
225c7b1f	316	*/
62212171 ED	317	union {
	318	__be32 srcrb_flags;
	319	__be16 srcrb_flags16[2];
	320	};
225c7b1f RD	321	/*
	322	* imm is immediate data for send/RDMA write w/ immediate;
	323	* also invalidation key for send with invalidate; input
	324	* modifier for WQEs on CCQs.
	325	*/
	326	__be32 imm;
	327	};
	328
	329	enum {
	330	MLX4_WQE_MLX_VL15 = 1 << 17,
	331	MLX4_WQE_MLX_SLR = 1 << 16
	332	};
	333
	334	struct mlx4_wqe_mlx_seg {
	335	u8 owner;
	336	u8 reserved1[2];
	337	u8 opcode;
c0c1d3d7 OD	338	__be16 sched_prio;
c0c1d3d7 OD	339	u8 reserved2;
225c7b1f RD	340	u8 size;
	341	/*
	342	* [17] VL15
	343	* [16] SLR
	344	* [15:12] static rate
	345	* [11:8] SL
	346	* [4] ICRC
	347	* [3:2] C
	348	* [0] FL (force loopback)
	349	*/
	350	__be32 flags;
	351	__be16 rlid;
	352	u16 reserved3;
	353	};
	354
	355	struct mlx4_wqe_datagram_seg {
	356	__be32 av[8];
	357	__be32 dqpn;
	358	__be32 qkey;
96dfa684	359	__be16 vlan;
574e2af7	360	u8 mac[ETH_ALEN];
225c7b1f RD	361	};
225c7b1f RD	362
47b37475	363	struct mlx4_wqe_lso_seg {
b832be1e EC	364	__be32 mss_hdr_size;
	365	__be32 header[0];
	366	};
	367
6ff63e19 SM	368	enum mlx4_wqe_bind_seg_flags2 {
	369	MLX4_WQE_BIND_ZERO_BASED = (1 << 30),
	370	MLX4_WQE_BIND_TYPE_2 = (1 << 31),
	371	};
	372
225c7b1f RD	373	struct mlx4_wqe_bind_seg {
	374	__be32 flags1;
	375	__be32 flags2;
	376	__be32 new_rkey;
	377	__be32 lkey;
	378	__be64 addr;
	379	__be64 length;
	380	};
	381
95d04f07 RD	382	enum {
	383	MLX4_WQE_FMR_PERM_LOCAL_READ = 1 << 27,
	384	MLX4_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28,
6ff63e19 SM	385	MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ = 1 << 29,
	386	MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE = 1 << 30,
	387	MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC = 1 << 31
95d04f07 RD	388	};
95d04f07 RD	389
225c7b1f RD	390	struct mlx4_wqe_fmr_seg {
	391	__be32 flags;
	392	__be32 mem_key;
	393	__be64 buf_list;
	394	__be64 start_addr;
	395	__be64 reg_len;
	396	__be32 offset;
	397	__be32 page_size;
	398	u32 reserved[2];
	399	};
	400
	401	struct mlx4_wqe_fmr_ext_seg {
	402	u8 flags;
	403	u8 reserved;
	404	__be16 app_mask;
	405	__be16 wire_app_tag;
	406	__be16 mem_app_tag;
	407	__be32 wire_ref_tag_base;
	408	__be32 mem_ref_tag_base;
	409	};
	410
	411	struct mlx4_wqe_local_inval_seg {
aee38fad	412	u64 reserved1;
225c7b1f	413	__be32 mem_key;
aee38fad SM	414	u32 reserved2;
aee38fad SM	415	u64 reserved3[2];
225c7b1f RD	416	};
	417
	418	struct mlx4_wqe_raddr_seg {
	419	__be64 raddr;
	420	__be32 rkey;
	421	u32 reserved;
	422	};
	423
	424	struct mlx4_wqe_atomic_seg {
	425	__be64 swap_add;
	426	__be64 compare;
	427	};
	428
6fa8f719 VS	429	struct mlx4_wqe_masked_atomic_seg {
	430	__be64 swap_add;
	431	__be64 compare;
	432	__be64 swap_add_mask;
	433	__be64 compare_mask;
	434	};
	435
225c7b1f RD	436	struct mlx4_wqe_data_seg {
	437	__be32 byte_count;
	438	__be32 lkey;
	439	__be64 addr;
	440	};
	441
e61ef241 RD	442	enum {
e61ef241 RD	443	MLX4_INLINE_ALIGN = 64,
c1b43dca	444	MLX4_INLINE_SEG = 1 << 31,
e61ef241 RD	445	};
e61ef241 RD	446
225c7b1f RD	447	struct mlx4_wqe_inline_seg {
	448	__be32 byte_count;
	449	};
	450
ce8d9e0d MB	451	enum mlx4_update_qp_attr {
ce8d9e0d MB	452	MLX4_UPDATE_QP_SMAC = 1 << 0,
f5956faf	453	MLX4_UPDATE_QP_VSD = 1 << 1,
fc31e256	454	MLX4_UPDATE_QP_RATE_LIMIT = 1 << 2,
08068cd5	455	MLX4_UPDATE_QP_QOS_VPORT = 1 << 3,
9a892835 MG	456	MLX4_UPDATE_QP_ETH_SRC_CHECK_MC_LB = 1 << 4,
9a892835 MG	457	MLX4_UPDATE_QP_SUPPORTED_ATTRS = (1 << 5) - 1
09e05c3f MB	458	};
	459
	460	enum mlx4_update_qp_params_flags {
9a892835 MG	461	MLX4_UPDATE_QP_PARAMS_FLAGS_ETH_CHECK_MC_LB = 1 << 0,
9a892835 MG	462	MLX4_UPDATE_QP_PARAMS_FLAGS_VSD_ENABLE = 1 << 1,
ce8d9e0d MB	463	};
	464
	465	struct mlx4_update_qp_params {
	466	u8 smac_index;
08068cd5	467	u8 qos_vport;
09e05c3f	468	u32 flags;
fc31e256 OG	469	u16 rate_unit;
fc31e256 OG	470	u16 rate_val;
ce8d9e0d MB	471	};
ce8d9e0d MB	472
6dc06c08	473	struct mlx4_qp mlx4_qp_lookup(struct mlx4_dev dev, u32 qpn);
09e05c3f	474	int mlx4_update_qp(struct mlx4_dev *dev, u32 qpn,
ce8d9e0d MB	475	enum mlx4_update_qp_attr attr,
ce8d9e0d MB	476	struct mlx4_update_qp_params *params);
225c7b1f RD	477	int mlx4_qp_modify(struct mlx4_dev dev, struct mlx4_mtt mtt,
	478	enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state,
	479	struct mlx4_qp_context *context, enum mlx4_qp_optpar optpar,
	480	int sqd_event, struct mlx4_qp *qp);
	481
6a775e2b JM	482	int mlx4_qp_query(struct mlx4_dev dev, struct mlx4_qp qp,
	483	struct mlx4_qp_context *context);
	484
ed4d3c10 YP	485	int mlx4_qp_to_ready(struct mlx4_dev dev, struct mlx4_mtt mtt,
	486	struct mlx4_qp_context *context,
	487	struct mlx4_qp qp, enum mlx4_qp_state qp_state);
	488
225c7b1f RD	489	static inline struct mlx4_qp __mlx4_qp_lookup(struct mlx4_dev dev, u32 qpn)
	490	{
	491	return radix_tree_lookup(&dev->qp_table_tree, qpn & (dev->caps.num_qps - 1));
	492	}
	493
	494	void mlx4_qp_remove(struct mlx4_dev dev, struct mlx4_qp qp);
	495
3f723f42 MS	496	static inline u16 folded_qp(u32 q)
	497	{
	498	u16 res;
	499
	500	res = ((q & 0xff) ^ ((q & 0xff0000) >> 16)) \| (q & 0xff00);
	501	return res;
	502	}
	503
	504	u16 mlx4_qp_roce_entropy(struct mlx4_dev *dev, u32 qpn);
	505
225c7b1f	506	#endif /* MLX4_QP_H */