[mirror_ubuntu-artful-kernel.git] / include / linux / mlx4 / qp.h

/*
 * Copyright (c) 2007 Cisco Systems, Inc.  All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *	- Redistributions of source code must retain the above
 *	  copyright notice, this list of conditions and the following
 *	  disclaimer.
 *
 *	- Redistributions in binary form must reproduce the above
 *	  copyright notice, this list of conditions and the following
 *	  disclaimer in the documentation and/or other materials
 *	  provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#ifndef MLX4_QP_H
#define MLX4_QP_H

#include <linux/types.h>

#include <linux/mlx4/device.h>

#define MLX4_INVALID_LKEY	0x100

enum mlx4_qp_optpar {
	MLX4_QP_OPTPAR_ALT_ADDR_PATH		= 1 << 0,
	MLX4_QP_OPTPAR_RRE			= 1 << 1,
	MLX4_QP_OPTPAR_RAE			= 1 << 2,
	MLX4_QP_OPTPAR_RWE			= 1 << 3,
	MLX4_QP_OPTPAR_PKEY_INDEX		= 1 << 4,
	MLX4_QP_OPTPAR_Q_KEY			= 1 << 5,
	MLX4_QP_OPTPAR_RNR_TIMEOUT		= 1 << 6,
	MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH	= 1 << 7,
	MLX4_QP_OPTPAR_SRA_MAX			= 1 << 8,
	MLX4_QP_OPTPAR_RRA_MAX			= 1 << 9,
	MLX4_QP_OPTPAR_PM_STATE			= 1 << 10,
	MLX4_QP_OPTPAR_RETRY_COUNT		= 1 << 12,
	MLX4_QP_OPTPAR_RNR_RETRY		= 1 << 13,
	MLX4_QP_OPTPAR_ACK_TIMEOUT		= 1 << 14,
	MLX4_QP_OPTPAR_SCHED_QUEUE		= 1 << 16,
	MLX4_QP_OPTPAR_COUNTER_INDEX		= 1 << 20
};

enum mlx4_qp_state {
	MLX4_QP_STATE_RST			= 0,
	MLX4_QP_STATE_INIT			= 1,
	MLX4_QP_STATE_RTR			= 2,
	MLX4_QP_STATE_RTS			= 3,
	MLX4_QP_STATE_SQER			= 4,
	MLX4_QP_STATE_SQD			= 5,
	MLX4_QP_STATE_ERR			= 6,
	MLX4_QP_STATE_SQ_DRAINING		= 7,
	MLX4_QP_NUM_STATE
};

enum {
	MLX4_QP_ST_RC				= 0x0,
	MLX4_QP_ST_UC				= 0x1,
	MLX4_QP_ST_RD				= 0x2,
	MLX4_QP_ST_UD				= 0x3,
	MLX4_QP_ST_XRC				= 0x6,
	MLX4_QP_ST_MLX				= 0x7
};

enum {
	MLX4_QP_PM_MIGRATED			= 0x3,
	MLX4_QP_PM_ARMED			= 0x0,
	MLX4_QP_PM_REARM			= 0x1
};

enum {
	/* params1 */
	MLX4_QP_BIT_SRE				= 1 << 15,
	MLX4_QP_BIT_SWE				= 1 << 14,
	MLX4_QP_BIT_SAE				= 1 << 13,
	/* params2 */
	MLX4_QP_BIT_RRE				= 1 << 15,
	MLX4_QP_BIT_RWE				= 1 << 14,
	MLX4_QP_BIT_RAE				= 1 << 13,
	MLX4_QP_BIT_RIC				= 1 <<	4,
};

enum {
	MLX4_RSS_HASH_XOR			= 0,
	MLX4_RSS_HASH_TOP			= 1,

	MLX4_RSS_UDP_IPV6			= 1 << 0,
	MLX4_RSS_UDP_IPV4			= 1 << 1,
	MLX4_RSS_TCP_IPV6			= 1 << 2,
	MLX4_RSS_IPV6				= 1 << 3,
	MLX4_RSS_TCP_IPV4			= 1 << 4,
	MLX4_RSS_IPV4				= 1 << 5,

	/* offset of mlx4_rss_context within mlx4_qp_context.pri_path */
	MLX4_RSS_OFFSET_IN_QPC_PRI_PATH		= 0x24,
	/* offset of being RSS indirection QP within mlx4_qp_context.flags */
	MLX4_RSS_QPC_FLAG_OFFSET		= 13,
};

struct mlx4_rss_context {
	__be32			base_qpn;
	__be32			default_qpn;
	u16			reserved;
	u8			hash_fn;
	u8			flags;
	__be32			rss_key[10];
	__be32			base_qpn_udp;
};

struct mlx4_qp_path {
	u8			fl;
	u8			vlan_control;
	u8			disable_pkey_check;
	u8			pkey_index;
	u8			counter_index;
	u8			grh_mylmc;
	__be16			rlid;
	u8			ackto;
	u8			mgid_index;
	u8			static_rate;
	u8			hop_limit;
	__be32			tclass_flowlabel;
	u8			rgid[16];
	u8			sched_queue;
	u8			vlan_index;
	u8			feup;
	u8			fvl_rx;
	u8			reserved4[2];
	u8			dmac[6];
};

enum { /* fl */
	MLX4_FL_CV      = 1 << 6,
	MLX4_FL_ETH_HIDE_CQE_VLAN       = 1 << 2
};
enum { /* vlan_control */
	MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED	= 1 << 6,
	MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED	= 1 << 2,
	MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED	= 1 << 1, /* 802.1p priority tag */
	MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED	= 1 << 0
};

enum { /* feup */
	MLX4_FEUP_FORCE_ETH_UP          = 1 << 6, /* force Eth UP */
	MLX4_FSM_FORCE_ETH_SRC_MAC      = 1 << 5, /* force Source MAC */
	MLX4_FVL_FORCE_ETH_VLAN         = 1 << 3  /* force Eth vlan */
};

enum { /* fvl_rx */
	MLX4_FVL_RX_FORCE_ETH_VLAN      = 1 << 0 /* enforce Eth rx vlan */
};

struct mlx4_qp_context {
	__be32			flags;
	__be32			pd;
	u8			mtu_msgmax;
	u8			rq_size_stride;
	u8			sq_size_stride;
	u8			rlkey;
	__be32			usr_page;
	__be32			local_qpn;
	__be32			remote_qpn;
	struct			mlx4_qp_path pri_path;
	struct			mlx4_qp_path alt_path;
	__be32			params1;
	u32			reserved1;
	__be32			next_send_psn;
	__be32			cqn_send;
	u32			reserved2[2];
	__be32			last_acked_psn;
	__be32			ssn;
	__be32			params2;
	__be32			rnr_nextrecvpsn;
	__be32			xrcd;
	__be32			cqn_recv;
	__be64			db_rec_addr;
	__be32			qkey;
	__be32			srqn;
	__be32			msn;
	__be16			rq_wqe_counter;
	__be16			sq_wqe_counter;
	u32			reserved3[2];
	__be32			param3;
	__be32			nummmcpeers_basemkey;
	u8			log_page_size;
	u8			reserved4[2];
	u8			mtt_base_addr_h;
	__be32			mtt_base_addr_l;
	u32			reserved5[10];
};

enum { /* param3 */
	MLX4_STRIP_VLAN = 1 << 30
};

/* Which firmware version adds support for NEC (NoErrorCompletion) bit */
#define MLX4_FW_VER_WQE_CTRL_NEC mlx4_fw_ver(2, 2, 232)

enum {
	MLX4_WQE_CTRL_NEC		= 1 << 29,
	MLX4_WQE_CTRL_FENCE		= 1 << 6,
	MLX4_WQE_CTRL_CQ_UPDATE		= 3 << 2,
	MLX4_WQE_CTRL_SOLICITED		= 1 << 1,
	MLX4_WQE_CTRL_IP_CSUM		= 1 << 4,
	MLX4_WQE_CTRL_TCP_UDP_CSUM	= 1 << 5,
	MLX4_WQE_CTRL_INS_VLAN		= 1 << 6,
	MLX4_WQE_CTRL_STRONG_ORDER	= 1 << 7,
	MLX4_WQE_CTRL_FORCE_LOOPBACK	= 1 << 0,
};

struct mlx4_wqe_ctrl_seg {
	__be32			owner_opcode;
	__be16			vlan_tag;
	u8			ins_vlan;
	u8			fence_size;
	/*
	 * High 24 bits are SRC remote buffer; low 8 bits are flags:
	 * [7]   SO (strong ordering)
	 * [5]   TCP/UDP checksum
	 * [4]   IP checksum
	 * [3:2] C (generate completion queue entry)
	 * [1]   SE (solicited event)
	 * [0]   FL (force loopback)
	 */
	union {
		__be32			srcrb_flags;
		__be16			srcrb_flags16[2];
	};
	/*
	 * imm is immediate data for send/RDMA write w/ immediate;
	 * also invalidation key for send with invalidate; input
	 * modifier for WQEs on CCQs.
	 */
	__be32			imm;
};

enum {
	MLX4_WQE_MLX_VL15	= 1 << 17,
	MLX4_WQE_MLX_SLR	= 1 << 16
};

struct mlx4_wqe_mlx_seg {
	u8			owner;
	u8			reserved1[2];
	u8			opcode;
	__be16			sched_prio;
	u8			reserved2;
	u8			size;
	/*
	 * [17]    VL15
	 * [16]    SLR
	 * [15:12] static rate
	 * [11:8]  SL
	 * [4]     ICRC
	 * [3:2]   C
	 * [0]     FL (force loopback)
	 */
	__be32			flags;
	__be16			rlid;
	u16			reserved3;
};

struct mlx4_wqe_datagram_seg {
	__be32			av[8];
	__be32			dqpn;
	__be32			qkey;
	__be16			vlan;
	u8			mac[6];
};

struct mlx4_wqe_lso_seg {
	__be32			mss_hdr_size;
	__be32			header[0];
};

enum mlx4_wqe_bind_seg_flags2 {
	MLX4_WQE_BIND_ZERO_BASED = (1 << 30),
	MLX4_WQE_BIND_TYPE_2     = (1 << 31),
};

struct mlx4_wqe_bind_seg {
	__be32			flags1;
	__be32			flags2;
	__be32			new_rkey;
	__be32			lkey;
	__be64			addr;
	__be64			length;
};

enum {
	MLX4_WQE_FMR_PERM_LOCAL_READ	= 1 << 27,
	MLX4_WQE_FMR_PERM_LOCAL_WRITE	= 1 << 28,
	MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ	= 1 << 29,
	MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE	= 1 << 30,
	MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC	= 1 << 31
};

struct mlx4_wqe_fmr_seg {
	__be32			flags;
	__be32			mem_key;
	__be64			buf_list;
	__be64			start_addr;
	__be64			reg_len;
	__be32			offset;
	__be32			page_size;
	u32			reserved[2];
};

struct mlx4_wqe_fmr_ext_seg {
	u8			flags;
	u8			reserved;
	__be16			app_mask;
	__be16			wire_app_tag;
	__be16			mem_app_tag;
	__be32			wire_ref_tag_base;
	__be32			mem_ref_tag_base;
};

struct mlx4_wqe_local_inval_seg {
	u64			reserved1;
	__be32			mem_key;
	u32			reserved2;
	u64			reserved3[2];
};

struct mlx4_wqe_raddr_seg {
	__be64			raddr;
	__be32			rkey;
	u32			reserved;
};

struct mlx4_wqe_atomic_seg {
	__be64			swap_add;
	__be64			compare;
};

struct mlx4_wqe_masked_atomic_seg {
	__be64			swap_add;
	__be64			compare;
	__be64			swap_add_mask;
	__be64			compare_mask;
};

struct mlx4_wqe_data_seg {
	__be32			byte_count;
	__be32			lkey;
	__be64			addr;
};

enum {
	MLX4_INLINE_ALIGN	= 64,
	MLX4_INLINE_SEG		= 1 << 31,
};

struct mlx4_wqe_inline_seg {
	__be32			byte_count;
};

int mlx4_qp_modify(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
		   enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state,
		   struct mlx4_qp_context *context, enum mlx4_qp_optpar optpar,
		   int sqd_event, struct mlx4_qp *qp);

int mlx4_qp_query(struct mlx4_dev *dev, struct mlx4_qp *qp,
		  struct mlx4_qp_context *context);

int mlx4_qp_to_ready(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
		     struct mlx4_qp_context *context,
		     struct mlx4_qp *qp, enum mlx4_qp_state *qp_state);

static inline struct mlx4_qp *__mlx4_qp_lookup(struct mlx4_dev *dev, u32 qpn)
{
	return radix_tree_lookup(&dev->qp_table_tree, qpn & (dev->caps.num_qps - 1));
}

void mlx4_qp_remove(struct mlx4_dev *dev, struct mlx4_qp *qp);

#endif /* MLX4_QP_H */
Commit	Line	Data
225c7b1f RD	1	/*
	2	* Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
	3	*
	4	* This software is available to you under a choice of one of two
	5	* licenses. You may choose to be licensed under the terms of the GNU
	6	* General Public License (GPL) Version 2, available from the file
	7	* COPYING in the main directory of this source tree, or the
	8	* OpenIB.org BSD license below:
	9	*
	10	* Redistribution and use in source and binary forms, with or
	11	* without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistributions of source code must retain the above
	15	* copyright notice, this list of conditions and the following
	16	* disclaimer.
	17	*
	18	* - Redistributions in binary form must reproduce the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer in the documentation and/or other materials
	21	* provided with the distribution.
	22	*
	23	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	24	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	25	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	26	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	27	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	28	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	29	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	30	* SOFTWARE.
	31	*/
	32
	33	#ifndef MLX4_QP_H
	34	#define MLX4_QP_H
	35
	36	#include <linux/types.h>
	37
	38	#include <linux/mlx4/device.h>
	39
	40	#define MLX4_INVALID_LKEY 0x100
	41
	42	enum mlx4_qp_optpar {
	43	MLX4_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0,
	44	MLX4_QP_OPTPAR_RRE = 1 << 1,
	45	MLX4_QP_OPTPAR_RAE = 1 << 2,
	46	MLX4_QP_OPTPAR_RWE = 1 << 3,
	47	MLX4_QP_OPTPAR_PKEY_INDEX = 1 << 4,
	48	MLX4_QP_OPTPAR_Q_KEY = 1 << 5,
	49	MLX4_QP_OPTPAR_RNR_TIMEOUT = 1 << 6,
	50	MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
	51	MLX4_QP_OPTPAR_SRA_MAX = 1 << 8,
	52	MLX4_QP_OPTPAR_RRA_MAX = 1 << 9,
	53	MLX4_QP_OPTPAR_PM_STATE = 1 << 10,
	54	MLX4_QP_OPTPAR_RETRY_COUNT = 1 << 12,
	55	MLX4_QP_OPTPAR_RNR_RETRY = 1 << 13,
	56	MLX4_QP_OPTPAR_ACK_TIMEOUT = 1 << 14,
cfcde11c OG	57	MLX4_QP_OPTPAR_SCHED_QUEUE = 1 << 16,
cfcde11c OG	58	MLX4_QP_OPTPAR_COUNTER_INDEX = 1 << 20
225c7b1f RD	59	};
	60
	61	enum mlx4_qp_state {
	62	MLX4_QP_STATE_RST = 0,
	63	MLX4_QP_STATE_INIT = 1,
	64	MLX4_QP_STATE_RTR = 2,
	65	MLX4_QP_STATE_RTS = 3,
	66	MLX4_QP_STATE_SQER = 4,
	67	MLX4_QP_STATE_SQD = 5,
	68	MLX4_QP_STATE_ERR = 6,
	69	MLX4_QP_STATE_SQ_DRAINING = 7,
	70	MLX4_QP_NUM_STATE
	71	};
	72
	73	enum {
	74	MLX4_QP_ST_RC = 0x0,
	75	MLX4_QP_ST_UC = 0x1,
	76	MLX4_QP_ST_RD = 0x2,
	77	MLX4_QP_ST_UD = 0x3,
0a1405da	78	MLX4_QP_ST_XRC = 0x6,
225c7b1f RD	79	MLX4_QP_ST_MLX = 0x7
	80	};
	81
	82	enum {
	83	MLX4_QP_PM_MIGRATED = 0x3,
	84	MLX4_QP_PM_ARMED = 0x0,
	85	MLX4_QP_PM_REARM = 0x1
	86	};
	87
	88	enum {
	89	/* params1 */
	90	MLX4_QP_BIT_SRE = 1 << 15,
	91	MLX4_QP_BIT_SWE = 1 << 14,
	92	MLX4_QP_BIT_SAE = 1 << 13,
	93	/* params2 */
	94	MLX4_QP_BIT_RRE = 1 << 15,
	95	MLX4_QP_BIT_RWE = 1 << 14,
	96	MLX4_QP_BIT_RAE = 1 << 13,
	97	MLX4_QP_BIT_RIC = 1 << 4,
	98	};
	99
876f6e67 OG	100	enum {
	101	MLX4_RSS_HASH_XOR = 0,
	102	MLX4_RSS_HASH_TOP = 1,
	103
	104	MLX4_RSS_UDP_IPV6 = 1 << 0,
	105	MLX4_RSS_UDP_IPV4 = 1 << 1,
	106	MLX4_RSS_TCP_IPV6 = 1 << 2,
	107	MLX4_RSS_IPV6 = 1 << 3,
	108	MLX4_RSS_TCP_IPV4 = 1 << 4,
	109	MLX4_RSS_IPV4 = 1 << 5,
	110
	111	/* offset of mlx4_rss_context within mlx4_qp_context.pri_path */
	112	MLX4_RSS_OFFSET_IN_QPC_PRI_PATH = 0x24,
	113	/* offset of being RSS indirection QP within mlx4_qp_context.flags */
	114	MLX4_RSS_QPC_FLAG_OFFSET = 13,
	115	};
	116
	117	struct mlx4_rss_context {
	118	__be32 base_qpn;
	119	__be32 default_qpn;
	120	u16 reserved;
	121	u8 hash_fn;
	122	u8 flags;
	123	__be32 rss_key[10];
	124	__be32 base_qpn_udp;
	125	};
	126
225c7b1f RD	127	struct mlx4_qp_path {
225c7b1f RD	128	u8 fl;
7677fc96	129	u8 vlan_control;
1ffeb2eb	130	u8 disable_pkey_check;
225c7b1f	131	u8 pkey_index;
98a13e48	132	u8 counter_index;
225c7b1f RD	133	u8 grh_mylmc;
	134	__be16 rlid;
	135	u8 ackto;
	136	u8 mgid_index;
	137	u8 static_rate;
	138	u8 hop_limit;
	139	__be32 tclass_flowlabel;
	140	u8 rgid[16];
	141	u8 sched_queue;
4c3eb3ca	142	u8 vlan_index;
0e98b523	143	u8 feup;
7677fc96	144	u8 fvl_rx;
98a13e48	145	u8 reserved4[2];
96dfa684	146	u8 dmac[6];
225c7b1f RD	147	};
225c7b1f RD	148
7677fc96 RE	149	enum { /* fl */
	150	MLX4_FL_CV = 1 << 6,
	151	MLX4_FL_ETH_HIDE_CQE_VLAN = 1 << 2
	152	};
	153	enum { /* vlan_control */
	154	MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED = 1 << 6,
	155	MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED = 1 << 2,
	156	MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED = 1 << 1, /* 802.1p priority tag */
	157	MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED = 1 << 0
	158	};
	159
	160	enum { /* feup */
	161	MLX4_FEUP_FORCE_ETH_UP = 1 << 6, /* force Eth UP */
	162	MLX4_FSM_FORCE_ETH_SRC_MAC = 1 << 5, /* force Source MAC */
	163	MLX4_FVL_FORCE_ETH_VLAN = 1 << 3 /* force Eth vlan */
	164	};
	165
	166	enum { /* fvl_rx */
	167	MLX4_FVL_RX_FORCE_ETH_VLAN = 1 << 0 /* enforce Eth rx vlan */
	168	};
	169
225c7b1f RD	170	struct mlx4_qp_context {
	171	__be32 flags;
	172	__be32 pd;
	173	u8 mtu_msgmax;
	174	u8 rq_size_stride;
	175	u8 sq_size_stride;
	176	u8 rlkey;
	177	__be32 usr_page;
	178	__be32 local_qpn;
	179	__be32 remote_qpn;
	180	struct mlx4_qp_path pri_path;
	181	struct mlx4_qp_path alt_path;
	182	__be32 params1;
	183	u32 reserved1;
	184	__be32 next_send_psn;
	185	__be32 cqn_send;
	186	u32 reserved2[2];
	187	__be32 last_acked_psn;
	188	__be32 ssn;
	189	__be32 params2;
	190	__be32 rnr_nextrecvpsn;
0a1405da	191	__be32 xrcd;
225c7b1f RD	192	__be32 cqn_recv;
	193	__be64 db_rec_addr;
	194	__be32 qkey;
	195	__be32 srqn;
	196	__be32 msn;
	197	__be16 rq_wqe_counter;
	198	__be16 sq_wqe_counter;
	199	u32 reserved3[2];
	200	__be32 param3;
	201	__be32 nummmcpeers_basemkey;
	202	u8 log_page_size;
	203	u8 reserved4[2];
	204	u8 mtt_base_addr_h;
	205	__be32 mtt_base_addr_l;
	206	u32 reserved5[10];
	207	};
	208
7677fc96 RE	209	enum { /* param3 */
	210	MLX4_STRIP_VLAN = 1 << 30
	211	};
	212
ea54b10c JM	213	/* Which firmware version adds support for NEC (NoErrorCompletion) bit */
	214	#define MLX4_FW_VER_WQE_CTRL_NEC mlx4_fw_ver(2, 2, 232)
	215
225c7b1f	216	enum {
8ff095ec EC	217	MLX4_WQE_CTRL_NEC = 1 << 29,
	218	MLX4_WQE_CTRL_FENCE = 1 << 6,
	219	MLX4_WQE_CTRL_CQ_UPDATE = 3 << 2,
	220	MLX4_WQE_CTRL_SOLICITED = 1 << 1,
	221	MLX4_WQE_CTRL_IP_CSUM = 1 << 4,
	222	MLX4_WQE_CTRL_TCP_UDP_CSUM = 1 << 5,
25c94d01	223	MLX4_WQE_CTRL_INS_VLAN = 1 << 6,
2ac6bf4d	224	MLX4_WQE_CTRL_STRONG_ORDER = 1 << 7,
96dfa684	225	MLX4_WQE_CTRL_FORCE_LOOPBACK = 1 << 0,
225c7b1f RD	226	};
	227
	228	struct mlx4_wqe_ctrl_seg {
	229	__be32 owner_opcode;
25c94d01 YP	230	__be16 vlan_tag;
25c94d01 YP	231	u8 ins_vlan;
225c7b1f RD	232	u8 fence_size;
	233	/*
	234	* High 24 bits are SRC remote buffer; low 8 bits are flags:
	235	* [7] SO (strong ordering)
	236	* [5] TCP/UDP checksum
	237	* [4] IP checksum
	238	* [3:2] C (generate completion queue entry)
	239	* [1] SE (solicited event)
60d6fe99	240	* [0] FL (force loopback)
225c7b1f	241	*/
62212171 ED	242	union {
	243	__be32 srcrb_flags;
	244	__be16 srcrb_flags16[2];
	245	};
225c7b1f RD	246	/*
	247	* imm is immediate data for send/RDMA write w/ immediate;
	248	* also invalidation key for send with invalidate; input
	249	* modifier for WQEs on CCQs.
	250	*/
	251	__be32 imm;
	252	};
	253
	254	enum {
	255	MLX4_WQE_MLX_VL15 = 1 << 17,
	256	MLX4_WQE_MLX_SLR = 1 << 16
	257	};
	258
	259	struct mlx4_wqe_mlx_seg {
	260	u8 owner;
	261	u8 reserved1[2];
	262	u8 opcode;
c0c1d3d7 OD	263	__be16 sched_prio;
c0c1d3d7 OD	264	u8 reserved2;
225c7b1f RD	265	u8 size;
	266	/*
	267	* [17] VL15
	268	* [16] SLR
	269	* [15:12] static rate
	270	* [11:8] SL
	271	* [4] ICRC
	272	* [3:2] C
	273	* [0] FL (force loopback)
	274	*/
	275	__be32 flags;
	276	__be16 rlid;
	277	u16 reserved3;
	278	};
	279
	280	struct mlx4_wqe_datagram_seg {
	281	__be32 av[8];
	282	__be32 dqpn;
	283	__be32 qkey;
96dfa684 EC	284	__be16 vlan;
96dfa684 EC	285	u8 mac[6];
225c7b1f RD	286	};
225c7b1f RD	287
47b37475	288	struct mlx4_wqe_lso_seg {
b832be1e EC	289	__be32 mss_hdr_size;
	290	__be32 header[0];
	291	};
	292
6ff63e19 SM	293	enum mlx4_wqe_bind_seg_flags2 {
	294	MLX4_WQE_BIND_ZERO_BASED = (1 << 30),
	295	MLX4_WQE_BIND_TYPE_2 = (1 << 31),
	296	};
	297
225c7b1f RD	298	struct mlx4_wqe_bind_seg {
	299	__be32 flags1;
	300	__be32 flags2;
	301	__be32 new_rkey;
	302	__be32 lkey;
	303	__be64 addr;
	304	__be64 length;
	305	};
	306
95d04f07 RD	307	enum {
	308	MLX4_WQE_FMR_PERM_LOCAL_READ = 1 << 27,
	309	MLX4_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28,
6ff63e19 SM	310	MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ = 1 << 29,
	311	MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE = 1 << 30,
	312	MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC = 1 << 31
95d04f07 RD	313	};
95d04f07 RD	314
225c7b1f RD	315	struct mlx4_wqe_fmr_seg {
	316	__be32 flags;
	317	__be32 mem_key;
	318	__be64 buf_list;
	319	__be64 start_addr;
	320	__be64 reg_len;
	321	__be32 offset;
	322	__be32 page_size;
	323	u32 reserved[2];
	324	};
	325
	326	struct mlx4_wqe_fmr_ext_seg {
	327	u8 flags;
	328	u8 reserved;
	329	__be16 app_mask;
	330	__be16 wire_app_tag;
	331	__be16 mem_app_tag;
	332	__be32 wire_ref_tag_base;
	333	__be32 mem_ref_tag_base;
	334	};
	335
	336	struct mlx4_wqe_local_inval_seg {
aee38fad	337	u64 reserved1;
225c7b1f	338	__be32 mem_key;
aee38fad SM	339	u32 reserved2;
aee38fad SM	340	u64 reserved3[2];
225c7b1f RD	341	};
	342
	343	struct mlx4_wqe_raddr_seg {
	344	__be64 raddr;
	345	__be32 rkey;
	346	u32 reserved;
	347	};
	348
	349	struct mlx4_wqe_atomic_seg {
	350	__be64 swap_add;
	351	__be64 compare;
	352	};
	353
6fa8f719 VS	354	struct mlx4_wqe_masked_atomic_seg {
	355	__be64 swap_add;
	356	__be64 compare;
	357	__be64 swap_add_mask;
	358	__be64 compare_mask;
	359	};
	360
225c7b1f RD	361	struct mlx4_wqe_data_seg {
	362	__be32 byte_count;
	363	__be32 lkey;
	364	__be64 addr;
	365	};
	366
e61ef241 RD	367	enum {
e61ef241 RD	368	MLX4_INLINE_ALIGN = 64,
c1b43dca	369	MLX4_INLINE_SEG = 1 << 31,
e61ef241 RD	370	};
e61ef241 RD	371
225c7b1f RD	372	struct mlx4_wqe_inline_seg {
	373	__be32 byte_count;
	374	};
	375
	376	int mlx4_qp_modify(struct mlx4_dev dev, struct mlx4_mtt mtt,
	377	enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state,
	378	struct mlx4_qp_context *context, enum mlx4_qp_optpar optpar,
	379	int sqd_event, struct mlx4_qp *qp);
	380
6a775e2b JM	381	int mlx4_qp_query(struct mlx4_dev dev, struct mlx4_qp qp,
	382	struct mlx4_qp_context *context);
	383
ed4d3c10 YP	384	int mlx4_qp_to_ready(struct mlx4_dev dev, struct mlx4_mtt mtt,
	385	struct mlx4_qp_context *context,
	386	struct mlx4_qp qp, enum mlx4_qp_state qp_state);
	387
225c7b1f RD	388	static inline struct mlx4_qp __mlx4_qp_lookup(struct mlx4_dev dev, u32 qpn)
	389	{
	390	return radix_tree_lookup(&dev->qp_table_tree, qpn & (dev->caps.num_qps - 1));
	391	}
	392
	393	void mlx4_qp_remove(struct mlx4_dev dev, struct mlx4_qp qp);
	394
	395	#endif /* MLX4_QP_H */