[mirror_ubuntu-hirsute-kernel.git] / include / linux / mlx5 / cq.h

/*
 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#ifndef MLX5_CORE_CQ_H
#define MLX5_CORE_CQ_H

#include <rdma/ib_verbs.h>
#include <linux/mlx5/driver.h>
#include <linux/refcount.h>

struct mlx5_core_cq {
	u32			cqn;
	int			cqe_sz;
	__be32		       *set_ci_db;
	__be32		       *arm_db;
	struct mlx5_uars_page  *uar;
	refcount_t		refcount;
	struct completion	free;
	unsigned		vector;
	unsigned int		irqn;
	void (*comp)(struct mlx5_core_cq *cq, struct mlx5_eqe *eqe);
	void (*event)		(struct mlx5_core_cq *, enum mlx5_event);
	u32			cons_index;
	unsigned		arm_sn;
	struct mlx5_rsc_debug	*dbg;
	int			pid;
	struct {
		struct list_head list;
		void (*comp)(struct mlx5_core_cq *cq, struct mlx5_eqe *eqe);
		void		*priv;
	} tasklet_ctx;
	int			reset_notify_added;
	struct list_head	reset_notify;
	struct mlx5_eq_comp	*eq;
	u16 uid;
};


enum {
	MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR		= 0x01,
	MLX5_CQE_SYNDROME_LOCAL_QP_OP_ERR		= 0x02,
	MLX5_CQE_SYNDROME_LOCAL_PROT_ERR		= 0x04,
	MLX5_CQE_SYNDROME_WR_FLUSH_ERR			= 0x05,
	MLX5_CQE_SYNDROME_MW_BIND_ERR			= 0x06,
	MLX5_CQE_SYNDROME_BAD_RESP_ERR			= 0x10,
	MLX5_CQE_SYNDROME_LOCAL_ACCESS_ERR		= 0x11,
	MLX5_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR		= 0x12,
	MLX5_CQE_SYNDROME_REMOTE_ACCESS_ERR		= 0x13,
	MLX5_CQE_SYNDROME_REMOTE_OP_ERR			= 0x14,
	MLX5_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR	= 0x15,
	MLX5_CQE_SYNDROME_RNR_RETRY_EXC_ERR		= 0x16,
	MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR		= 0x22,
};

enum {
	MLX5_CQE_OWNER_MASK	= 1,
	MLX5_CQE_REQ		= 0,
	MLX5_CQE_RESP_WR_IMM	= 1,
	MLX5_CQE_RESP_SEND	= 2,
	MLX5_CQE_RESP_SEND_IMM	= 3,
	MLX5_CQE_RESP_SEND_INV	= 4,
	MLX5_CQE_RESIZE_CQ	= 5,
	MLX5_CQE_SIG_ERR	= 12,
	MLX5_CQE_REQ_ERR	= 13,
	MLX5_CQE_RESP_ERR	= 14,
	MLX5_CQE_INVALID	= 15,
};

enum {
	MLX5_CQ_MODIFY_PERIOD	= 1 << 0,
	MLX5_CQ_MODIFY_COUNT	= 1 << 1,
	MLX5_CQ_MODIFY_OVERRUN	= 1 << 2,
};

enum {
	MLX5_CQ_OPMOD_RESIZE		= 1,
	MLX5_MODIFY_CQ_MASK_LOG_SIZE	= 1 << 0,
	MLX5_MODIFY_CQ_MASK_PG_OFFSET	= 1 << 1,
	MLX5_MODIFY_CQ_MASK_PG_SIZE	= 1 << 2,
};

struct mlx5_cq_modify_params {
	int	type;
	union {
		struct {
			u32	page_offset;
			u8	log_cq_size;
		} resize;

		struct {
		} moder;

		struct {
		} mapping;
	} params;
};

enum {
	CQE_STRIDE_64 = 0,
	CQE_STRIDE_128 = 1,
	CQE_STRIDE_128_PAD = 2,
};

#define MLX5_MAX_CQ_PERIOD (BIT(__mlx5_bit_sz(cqc, cq_period)) - 1)
#define MLX5_MAX_CQ_COUNT (BIT(__mlx5_bit_sz(cqc, cq_max_count)) - 1)

static inline int cqe_sz_to_mlx_sz(u8 size, int padding_128_en)
{
	return padding_128_en ? CQE_STRIDE_128_PAD :
				size == 64 ? CQE_STRIDE_64 : CQE_STRIDE_128;
}

static inline void mlx5_cq_set_ci(struct mlx5_core_cq *cq)
{
	*cq->set_ci_db = cpu_to_be32(cq->cons_index & 0xffffff);
}

enum {
	MLX5_CQ_DB_REQ_NOT_SOL		= 1 << 24,
	MLX5_CQ_DB_REQ_NOT		= 0 << 24
};

static inline void mlx5_cq_arm(struct mlx5_core_cq *cq, u32 cmd,
			       void __iomem *uar_page,
			       u32 cons_index)
{
	__be32 doorbell[2];
	u32 sn;
	u32 ci;

	sn = cq->arm_sn & 3;
	ci = cons_index & 0xffffff;

	*cq->arm_db = cpu_to_be32(sn << 28 | cmd | ci);

	/* Make sure that the doorbell record in host memory is
	 * written before ringing the doorbell via PCI MMIO.
	 */
	wmb();

	doorbell[0] = cpu_to_be32(sn << 28 | cmd | ci);
	doorbell[1] = cpu_to_be32(cq->cqn);

	mlx5_write64(doorbell, uar_page + MLX5_CQ_DOORBELL);
}

static inline void mlx5_cq_hold(struct mlx5_core_cq *cq)
{
	refcount_inc(&cq->refcount);
}

static inline void mlx5_cq_put(struct mlx5_core_cq *cq)
{
	if (refcount_dec_and_test(&cq->refcount))
		complete(&cq->free);
}

int mlx5_core_create_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq,
			u32 *in, int inlen, u32 *out, int outlen);
int mlx5_core_destroy_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq);
int mlx5_core_query_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq,
		       u32 *out, int outlen);
int mlx5_core_modify_cq(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq,
			u32 *in, int inlen);
int mlx5_core_modify_cq_moderation(struct mlx5_core_dev *dev,
				   struct mlx5_core_cq *cq, u16 cq_period,
				   u16 cq_max_count);
static inline void mlx5_dump_err_cqe(struct mlx5_core_dev *dev,
				     struct mlx5_err_cqe *err_cqe)
{
	print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET, 16, 1, err_cqe,
		       sizeof(*err_cqe), false);
}
int mlx5_debug_cq_add(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq);
void mlx5_debug_cq_remove(struct mlx5_core_dev *dev, struct mlx5_core_cq *cq);

#endif /* MLX5_CORE_CQ_H */
Commit	Line	Data
e126ba97	1	/*
302bdf68	2	* Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97 EC	3	*
	4	* This software is available to you under a choice of one of two
	5	* licenses. You may choose to be licensed under the terms of the GNU
	6	* General Public License (GPL) Version 2, available from the file
	7	* COPYING in the main directory of this source tree, or the
	8	* OpenIB.org BSD license below:
	9	*
	10	* Redistribution and use in source and binary forms, with or
	11	* without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistributions of source code must retain the above
	15	* copyright notice, this list of conditions and the following
	16	* disclaimer.
	17	*
	18	* - Redistributions in binary form must reproduce the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer in the documentation and/or other materials
	21	* provided with the distribution.
	22	*
	23	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	24	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	25	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	26	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	27	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	28	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	29	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	30	* SOFTWARE.
	31	*/
	32
	33	#ifndef MLX5_CORE_CQ_H
	34	#define MLX5_CORE_CQ_H
	35
	36	#include <rdma/ib_verbs.h>
	37	#include <linux/mlx5/driver.h>
a4b51a9f	38	#include <linux/refcount.h>
e126ba97 EC	39
	40	struct mlx5_core_cq {
	41	u32 cqn;
	42	int cqe_sz;
	43	__be32 *set_ci_db;
	44	__be32 *arm_db;
30aa60b3	45	struct mlx5_uars_page *uar;
a4b51a9f	46	refcount_t refcount;
e126ba97 EC	47	struct completion free;
e126ba97 EC	48	unsigned vector;
0b6e26ce	49	unsigned int irqn;
4e0e2ea1	50	void (comp)(struct mlx5_core_cq cq, struct mlx5_eqe *eqe);
e126ba97	51	void (event) (struct mlx5_core_cq , enum mlx5_event);
e126ba97 EC	52	u32 cons_index;
	53	unsigned arm_sn;
	54	struct mlx5_rsc_debug *dbg;
	55	int pid;
94c6825e MB	56	struct {
94c6825e MB	57	struct list_head list;
4e0e2ea1	58	void (comp)(struct mlx5_core_cq cq, struct mlx5_eqe *eqe);
94c6825e MB	59	void *priv;
94c6825e MB	60	} tasklet_ctx;
89ea94a7 MG	61	int reset_notify_added;
89ea94a7 MG	62	struct list_head reset_notify;
16d76083	63	struct mlx5_eq_comp *eq;
9ba481e2	64	u16 uid;
e126ba97 EC	65	};
	66
	67
	68	enum {
	69	MLX5_CQE_SYNDROME_LOCAL_LENGTH_ERR = 0x01,
	70	MLX5_CQE_SYNDROME_LOCAL_QP_OP_ERR = 0x02,
	71	MLX5_CQE_SYNDROME_LOCAL_PROT_ERR = 0x04,
	72	MLX5_CQE_SYNDROME_WR_FLUSH_ERR = 0x05,
	73	MLX5_CQE_SYNDROME_MW_BIND_ERR = 0x06,
	74	MLX5_CQE_SYNDROME_BAD_RESP_ERR = 0x10,
	75	MLX5_CQE_SYNDROME_LOCAL_ACCESS_ERR = 0x11,
	76	MLX5_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR = 0x12,
	77	MLX5_CQE_SYNDROME_REMOTE_ACCESS_ERR = 0x13,
	78	MLX5_CQE_SYNDROME_REMOTE_OP_ERR = 0x14,
	79	MLX5_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR = 0x15,
	80	MLX5_CQE_SYNDROME_RNR_RETRY_EXC_ERR = 0x16,
	81	MLX5_CQE_SYNDROME_REMOTE_ABORTED_ERR = 0x22,
	82	};
	83
	84	enum {
	85	MLX5_CQE_OWNER_MASK = 1,
	86	MLX5_CQE_REQ = 0,
	87	MLX5_CQE_RESP_WR_IMM = 1,
	88	MLX5_CQE_RESP_SEND = 2,
	89	MLX5_CQE_RESP_SEND_IMM = 3,
	90	MLX5_CQE_RESP_SEND_INV = 4,
bde51583	91	MLX5_CQE_RESIZE_CQ = 5,
d5436ba0	92	MLX5_CQE_SIG_ERR = 12,
e126ba97 EC	93	MLX5_CQE_REQ_ERR = 13,
e126ba97 EC	94	MLX5_CQE_RESP_ERR = 14,
bde51583	95	MLX5_CQE_INVALID = 15,
e126ba97 EC	96	};
	97
	98	enum {
3bdb31f6 EC	99	MLX5_CQ_MODIFY_PERIOD = 1 << 0,
	100	MLX5_CQ_MODIFY_COUNT = 1 << 1,
	101	MLX5_CQ_MODIFY_OVERRUN = 1 << 2,
e126ba97 EC	102	};
e126ba97 EC	103
bde51583 EC	104	enum {
	105	MLX5_CQ_OPMOD_RESIZE = 1,
	106	MLX5_MODIFY_CQ_MASK_LOG_SIZE = 1 << 0,
	107	MLX5_MODIFY_CQ_MASK_PG_OFFSET = 1 << 1,
	108	MLX5_MODIFY_CQ_MASK_PG_SIZE = 1 << 2,
	109	};
	110
e126ba97 EC	111	struct mlx5_cq_modify_params {
	112	int type;
	113	union {
	114	struct {
	115	u32 page_offset;
	116	u8 log_cq_size;
	117	} resize;
	118
	119	struct {
	120	} moder;
	121
	122	struct {
	123	} mapping;
	124	} params;
	125	};
	126
	127	enum {
939de57d DJ	128	CQE_STRIDE_64 = 0,
	129	CQE_STRIDE_128 = 1,
	130	CQE_STRIDE_128_PAD = 2,
e126ba97 EC	131	};
e126ba97 EC	132
b0e9df6d YC	133	#define MLX5_MAX_CQ_PERIOD (BIT(__mlx5_bit_sz(cqc, cq_period)) - 1)
	134	#define MLX5_MAX_CQ_COUNT (BIT(__mlx5_bit_sz(cqc, cq_max_count)) - 1)
	135
7a0c8f42	136	static inline int cqe_sz_to_mlx_sz(u8 size, int padding_128_en)
e126ba97	137	{
939de57d DJ	138	return padding_128_en ? CQE_STRIDE_128_PAD :
939de57d DJ	139	size == 64 ? CQE_STRIDE_64 : CQE_STRIDE_128;
e126ba97 EC	140	}
	141
	142	static inline void mlx5_cq_set_ci(struct mlx5_core_cq *cq)
	143	{
	144	*cq->set_ci_db = cpu_to_be32(cq->cons_index & 0xffffff);
	145	}
	146
	147	enum {
	148	MLX5_CQ_DB_REQ_NOT_SOL = 1 << 24,
	149	MLX5_CQ_DB_REQ_NOT = 0 << 24
	150	};
	151
	152	static inline void mlx5_cq_arm(struct mlx5_core_cq *cq, u32 cmd,
	153	void __iomem *uar_page,
ce0f7509	154	u32 cons_index)
e126ba97 EC	155	{
	156	__be32 doorbell[2];
	157	u32 sn;
	158	u32 ci;
	159
	160	sn = cq->arm_sn & 3;
ce0f7509	161	ci = cons_index & 0xffffff;
e126ba97 EC	162
	163	*cq->arm_db = cpu_to_be32(sn << 28 \| cmd \| ci);
	164
	165	/* Make sure that the doorbell record in host memory is
	166	* written before ringing the doorbell via PCI MMIO.
	167	*/
	168	wmb();
	169
	170	doorbell[0] = cpu_to_be32(sn << 28 \| cmd \| ci);
	171	doorbell[1] = cpu_to_be32(cq->cqn);
	172
bbf29f61	173	mlx5_write64(doorbell, uar_page + MLX5_CQ_DOORBELL);
e126ba97 EC	174	}
e126ba97 EC	175
f105b45b SM	176	static inline void mlx5_cq_hold(struct mlx5_core_cq *cq)
	177	{
	178	refcount_inc(&cq->refcount);
	179	}
	180
	181	static inline void mlx5_cq_put(struct mlx5_core_cq *cq)
	182	{
	183	if (refcount_dec_and_test(&cq->refcount))
	184	complete(&cq->free);
	185	}
	186
e126ba97	187	int mlx5_core_create_cq(struct mlx5_core_dev dev, struct mlx5_core_cq cq,
38164b77	188	u32 in, int inlen, u32 out, int outlen);
e126ba97 EC	189	int mlx5_core_destroy_cq(struct mlx5_core_dev dev, struct mlx5_core_cq cq);
e126ba97 EC	190	int mlx5_core_query_cq(struct mlx5_core_dev dev, struct mlx5_core_cq cq,
27827786	191	u32 *out, int outlen);
e126ba97	192	int mlx5_core_modify_cq(struct mlx5_core_dev dev, struct mlx5_core_cq cq,
27827786	193	u32 *in, int inlen);
90b3e38d RS	194	int mlx5_core_modify_cq_moderation(struct mlx5_core_dev *dev,
	195	struct mlx5_core_cq *cq, u16 cq_period,
	196	u16 cq_max_count);
1acae6b0 EBE	197	static inline void mlx5_dump_err_cqe(struct mlx5_core_dev *dev,
	198	struct mlx5_err_cqe *err_cqe)
	199	{
	200	print_hex_dump(KERN_WARNING, "", DUMP_PREFIX_OFFSET, 16, 1, err_cqe,
	201	sizeof(*err_cqe), false);
	202	}
e126ba97 EC	203	int mlx5_debug_cq_add(struct mlx5_core_dev dev, struct mlx5_core_cq cq);
	204	void mlx5_debug_cq_remove(struct mlx5_core_dev dev, struct mlx5_core_cq cq);
	205
	206	#endif /* MLX5_CORE_CQ_H */