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Merge tag 'acpi-extra-4.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafae...
[mirror_ubuntu-bionic-kernel.git] / include / linux / mlx5 / device.h
CommitLineData
e126ba97 1/*
302bdf68 2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX5_DEVICE_H
34#define MLX5_DEVICE_H
35
36#include <linux/types.h>
37#include <rdma/ib_verbs.h>
e281682b 38#include <linux/mlx5/mlx5_ifc.h>
e126ba97
EC		 39
40#if defined(__LITTLE_ENDIAN)
41#define MLX5_SET_HOST_ENDIANNESS 0
42#elif defined(__BIG_ENDIAN)
43#define MLX5_SET_HOST_ENDIANNESS 0x80
44#else
45#error Host endianness not defined
46#endif
47
d29b796a
EC		 48/* helper macros */
49#define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0)
50#define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld)
51#define __mlx5_bit_off(typ, fld) ((unsigned)(unsigned long)(&(__mlx5_nullp(typ)->fld)))
52#define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32)
53#define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64)
54#define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f))
55#define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1))
56#define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld))
57#define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits)
58
59#define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8)
60#define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8)
61#define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32)
9218b44d 62#define MLX5_ST_SZ_QW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 64)
938fe83c
SM		 63#define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8)
64#define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32)
d29b796a
EC		 65#define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8)
66#define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld))
67
68/* insert a value to a struct */
69#define MLX5_SET(typ, p, fld, v) do { \
70 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
71 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
72 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
73 (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \
74 << __mlx5_dw_bit_off(typ, fld))); \
75} while (0)
76
e281682b
SM		 77#define MLX5_SET_TO_ONES(typ, p, fld) do { \
78 BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \
79 *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \
80 cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \
81 (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \
82 << __mlx5_dw_bit_off(typ, fld))); \
83} while (0)
84
d29b796a
EC		 85#define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\
86__mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \
87__mlx5_mask(typ, fld))
88
89#define MLX5_GET_PR(typ, p, fld) ({ \
90 u32 ___t = MLX5_GET(typ, p, fld); \
91 pr_debug(#fld " = 0x%x\n", ___t); \
92 ___t; \
93})
94
b8a4ddb2 95#define __MLX5_SET64(typ, p, fld, v) do { \
d29b796a 96 BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \
d29b796a
EC		 97 *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \
98} while (0)
99
b8a4ddb2
TH		 100#define MLX5_SET64(typ, p, fld, v) do { \
101 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
102 __MLX5_SET64(typ, p, fld, v); \
103} while (0)
104
105#define MLX5_ARRAY_SET64(typ, p, fld, idx, v) do { \
106 BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \
107 __MLX5_SET64(typ, p, fld[idx], v); \
108} while (0)
109
d29b796a
EC		 110#define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld)))
111
707c4602
MD		 112#define MLX5_GET64_PR(typ, p, fld) ({ \
113 u64 ___t = MLX5_GET64(typ, p, fld); \
114 pr_debug(#fld " = 0x%llx\n", ___t); \
115 ___t; \
116})
117
3efd9a11
MY		 118/* Big endian getters */
119#define MLX5_GET64_BE(typ, p, fld) (*((__be64 *)(p) +\
120 __mlx5_64_off(typ, fld)))
121
122#define MLX5_GET_BE(type_t, typ, p, fld) ({ \
123 type_t tmp; \
124 switch (sizeof(tmp)) { \
125 case sizeof(u8): \
126 tmp = (__force type_t)MLX5_GET(typ, p, fld); \
127 break; \
128 case sizeof(u16): \
129 tmp = (__force type_t)cpu_to_be16(MLX5_GET(typ, p, fld)); \
130 break; \
131 case sizeof(u32): \
132 tmp = (__force type_t)cpu_to_be32(MLX5_GET(typ, p, fld)); \
133 break; \
134 case sizeof(u64): \
135 tmp = (__force type_t)MLX5_GET64_BE(typ, p, fld); \
136 break; \
137 } \
138 tmp; \
139 })
140
ae76715d
HHZ		 141enum mlx5_inline_modes {
142 MLX5_INLINE_MODE_NONE,
143 MLX5_INLINE_MODE_L2,
144 MLX5_INLINE_MODE_IP,
145 MLX5_INLINE_MODE_TCP_UDP,
146};
147
e126ba97
EC		 148enum {
149 MLX5_MAX_COMMANDS = 32,
150 MLX5_CMD_DATA_BLOCK_SIZE = 512,
151 MLX5_PCI_CMD_XPORT = 7,
3121e3c4
SG		 152 MLX5_MKEY_BSF_OCTO_SIZE = 4,
153 MLX5_MAX_PSVS = 4,
e126ba97
EC		 154};
155
156enum {
157 MLX5_EXTENDED_UD_AV = 0x80000000,
158};
159
160enum {
161 MLX5_CQ_STATE_ARMED = 9,
162 MLX5_CQ_STATE_ALWAYS_ARMED = 0xb,
163 MLX5_CQ_STATE_FIRED = 0xa,
164};
165
166enum {
167 MLX5_STAT_RATE_OFFSET = 5,
168};
169
170enum {
171 MLX5_INLINE_SEG = 0x80000000,
172};
173
fc11fbf9
SM		 174enum {
175 MLX5_HW_START_PADDING = MLX5_INLINE_SEG,
176};
177
c7a08ac7
EC		 178enum {
179 MLX5_MIN_PKEY_TABLE_SIZE = 128,
180 MLX5_MAX_LOG_PKEY_TABLE = 5,
181};
182
e420f0c0
HE		 183enum {
184 MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31
185};
186
187enum {
188 MLX5_PFAULT_SUBTYPE_WQE = 0,
189 MLX5_PFAULT_SUBTYPE_RDMA = 1,
190};
191
e126ba97
EC		 192enum {
193 MLX5_PERM_LOCAL_READ = 1 << 2,
194 MLX5_PERM_LOCAL_WRITE = 1 << 3,
195 MLX5_PERM_REMOTE_READ = 1 << 4,
196 MLX5_PERM_REMOTE_WRITE = 1 << 5,
197 MLX5_PERM_ATOMIC = 1 << 6,
198 MLX5_PERM_UMR_EN = 1 << 7,
199};
200
201enum {
202 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0,
203 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
204 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3,
205 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6,
206 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4,
207};
208
e126ba97
EC		 209enum {
210 MLX5_EN_RD = (u64)1,
211 MLX5_EN_WR = (u64)2
212};
213
214enum {
c1be5232
EC		 215 MLX5_BF_REGS_PER_PAGE = 4,
216 MLX5_MAX_UAR_PAGES = 1 << 8,
217 MLX5_NON_FP_BF_REGS_PER_PAGE = 2,
218 MLX5_MAX_UUARS = MLX5_MAX_UAR_PAGES * MLX5_NON_FP_BF_REGS_PER_PAGE,
e126ba97
EC		 219};
220
221enum {
222 MLX5_MKEY_MASK_LEN = 1ull << 0,
223 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1,
224 MLX5_MKEY_MASK_START_ADDR = 1ull << 6,
225 MLX5_MKEY_MASK_PD = 1ull << 7,
226 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8,
d5436ba0 227 MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9,
e126ba97
EC		 228 MLX5_MKEY_MASK_BSF_EN = 1ull << 12,
229 MLX5_MKEY_MASK_KEY = 1ull << 13,
230 MLX5_MKEY_MASK_QPN = 1ull << 14,
231 MLX5_MKEY_MASK_LR = 1ull << 17,
232 MLX5_MKEY_MASK_LW = 1ull << 18,
233 MLX5_MKEY_MASK_RR = 1ull << 19,
234 MLX5_MKEY_MASK_RW = 1ull << 20,
235 MLX5_MKEY_MASK_A = 1ull << 21,
236 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23,
237 MLX5_MKEY_MASK_FREE = 1ull << 29,
238};
239
968e78dd
HE		 240enum {
241 MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4),
242
243 MLX5_UMR_CHECK_NOT_FREE = (1 << 5),
244 MLX5_UMR_CHECK_FREE = (2 << 5),
245
246 MLX5_UMR_INLINE = (1 << 7),
247};
248
cc149f75
HE		 249#define MLX5_UMR_MTT_ALIGNMENT 0x40
250#define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1)
832a6b06 251#define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT
cc149f75 252
e2013b21 253#define MLX5_USER_INDEX_LEN (MLX5_FLD_SZ_BYTES(qpc, user_index) * 8)
254
255enum {
256 MLX5_EVENT_QUEUE_TYPE_QP = 0,
257 MLX5_EVENT_QUEUE_TYPE_RQ = 1,
258 MLX5_EVENT_QUEUE_TYPE_SQ = 2,
259};
260
e126ba97
EC		 261enum mlx5_event {
262 MLX5_EVENT_TYPE_COMP = 0x0,
263
264 MLX5_EVENT_TYPE_PATH_MIG = 0x01,
265 MLX5_EVENT_TYPE_COMM_EST = 0x02,
266 MLX5_EVENT_TYPE_SQ_DRAINED = 0x03,
267 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13,
268 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14,
269
270 MLX5_EVENT_TYPE_CQ_ERROR = 0x04,
271 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
272 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
273 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
274 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
275 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
276
277 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08,
278 MLX5_EVENT_TYPE_PORT_CHANGE = 0x09,
279 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15,
280 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19,
281
282 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a,
283 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b,
284
285 MLX5_EVENT_TYPE_CMD = 0x0a,
286 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb,
e420f0c0
HE		 287
288 MLX5_EVENT_TYPE_PAGE_FAULT = 0xc,
073bb189 289 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE = 0xd,
e126ba97
EC		 290};
291
292enum {
293 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1,
294 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4,
295 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5,
296 MLX5_PORT_CHANGE_SUBTYPE_LID = 6,
297 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7,
298 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8,
299 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9,
300};
301
302enum {
e126ba97 303 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3,
e126ba97
EC		 304 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
305 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
306 MLX5_DEV_CAP_FLAG_APM = 1LL << 17,
307 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
f360d88a 308 MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23,
6cb7ff3d 309 MLX5_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24,
3bdb31f6 310 MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29,
bde51583 311 MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30,
c7a08ac7 312 MLX5_DEV_CAP_FLAG_DCT = 1LL << 37,
e126ba97 313 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40,
c1868b82 314 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46,
e126ba97
EC		 315};
316
3cca2606
AS		 317enum {
318 MLX5_ROCE_VERSION_1 = 0,
319 MLX5_ROCE_VERSION_2 = 2,
320};
321
322enum {
323 MLX5_ROCE_VERSION_1_CAP = 1 << MLX5_ROCE_VERSION_1,
324 MLX5_ROCE_VERSION_2_CAP = 1 << MLX5_ROCE_VERSION_2,
325};
326
327enum {
328 MLX5_ROCE_L3_TYPE_IPV4 = 0,
329 MLX5_ROCE_L3_TYPE_IPV6 = 1,
330};
331
332enum {
333 MLX5_ROCE_L3_TYPE_IPV4_CAP = 1 << 1,
334 MLX5_ROCE_L3_TYPE_IPV6_CAP = 1 << 2,
335};
336
e126ba97
EC		 337enum {
338 MLX5_OPCODE_NOP = 0x00,
339 MLX5_OPCODE_SEND_INVAL = 0x01,
340 MLX5_OPCODE_RDMA_WRITE = 0x08,
341 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09,
342 MLX5_OPCODE_SEND = 0x0a,
343 MLX5_OPCODE_SEND_IMM = 0x0b,
e281682b 344 MLX5_OPCODE_LSO = 0x0e,
e126ba97
EC		 345 MLX5_OPCODE_RDMA_READ = 0x10,
346 MLX5_OPCODE_ATOMIC_CS = 0x11,
347 MLX5_OPCODE_ATOMIC_FA = 0x12,
348 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14,
349 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15,
350 MLX5_OPCODE_BIND_MW = 0x18,
351 MLX5_OPCODE_CONFIG_CMD = 0x1f,
352
353 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
354 MLX5_RECV_OPCODE_SEND = 0x01,
355 MLX5_RECV_OPCODE_SEND_IMM = 0x02,
356 MLX5_RECV_OPCODE_SEND_INVAL = 0x03,
357
358 MLX5_CQE_OPCODE_ERROR = 0x1e,
359 MLX5_CQE_OPCODE_RESIZE = 0x16,
360
361 MLX5_OPCODE_SET_PSV = 0x20,
362 MLX5_OPCODE_GET_PSV = 0x21,
363 MLX5_OPCODE_CHECK_PSV = 0x22,
364 MLX5_OPCODE_RGET_PSV = 0x26,
365 MLX5_OPCODE_RCHECK_PSV = 0x27,
366
367 MLX5_OPCODE_UMR = 0x25,
368
369};
370
371enum {
372 MLX5_SET_PORT_RESET_QKEY = 0,
373 MLX5_SET_PORT_GUID0 = 16,
374 MLX5_SET_PORT_NODE_GUID = 17,
375 MLX5_SET_PORT_SYS_GUID = 18,
376 MLX5_SET_PORT_GID_TABLE = 19,
377 MLX5_SET_PORT_PKEY_TABLE = 20,
378};
379
d8880795
TT		 380enum {
381 MLX5_BW_NO_LIMIT = 0,
382 MLX5_100_MBPS_UNIT = 3,
383 MLX5_GBPS_UNIT = 4,
384};
385
e126ba97
EC		 386enum {
387 MLX5_MAX_PAGE_SHIFT = 31
388};
389
1b77d2bd 390enum {
05bdb2ab
EC		 391 MLX5_ADAPTER_PAGE_SHIFT = 12,
392 MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT,
1b77d2bd
EC		 393};
394
87b8de49 395enum {
87b8de49
EC		 396 MLX5_CAP_OFF_CMDIF_CSUM = 46,
397};
398
986ef95e
SG		 399enum {
400 /*
401 * Max wqe size for rdma read is 512 bytes, so this
402 * limits our max_sge_rd as the wqe needs to fit:
403 * - ctrl segment (16 bytes)
404 * - rdma segment (16 bytes)
405 * - scatter elements (16 bytes each)
406 */
407 MLX5_MAX_SGE_RD = (512 - 16 - 16) / 16
408};
409
e420f0c0
HE		 410enum mlx5_odp_transport_cap_bits {
411 MLX5_ODP_SUPPORT_SEND = 1 << 31,
412 MLX5_ODP_SUPPORT_RECV = 1 << 30,
413 MLX5_ODP_SUPPORT_WRITE = 1 << 29,
414 MLX5_ODP_SUPPORT_READ = 1 << 28,
415};
416
417struct mlx5_odp_caps {
418 char reserved[0x10];
419 struct {
420 __be32 rc_odp_caps;
421 __be32 uc_odp_caps;
422 __be32 ud_odp_caps;
423 } per_transport_caps;
424 char reserved2[0xe4];
425};
426
e126ba97
EC		 427struct mlx5_cmd_layout {
428 u8 type;
429 u8 rsvd0[3];
430 __be32 inlen;
431 __be64 in_ptr;
432 __be32 in[4];
433 __be32 out[4];
434 __be64 out_ptr;
435 __be32 outlen;
436 u8 token;
437 u8 sig;
438 u8 rsvd1;
439 u8 status_own;
440};
441
e126ba97
EC		 442struct health_buffer {
443 __be32 assert_var[5];
444 __be32 rsvd0[3];
445 __be32 assert_exit_ptr;
446 __be32 assert_callra;
447 __be32 rsvd1[2];
448 __be32 fw_ver;
449 __be32 hw_id;
450 __be32 rsvd2;
451 u8 irisc_index;
452 u8 synd;
78ccb258 453 __be16 ext_synd;
e126ba97
EC		 454};
455
456struct mlx5_init_seg {
457 __be32 fw_rev;
458 __be32 cmdif_rev_fw_sub;
459 __be32 rsvd0[2];
460 __be32 cmdq_addr_h;
461 __be32 cmdq_addr_l_sz;
462 __be32 cmd_dbell;
e3297246
EC		 463 __be32 rsvd1[120];
464 __be32 initializing;
e126ba97 465 struct health_buffer health;
b0844444
EBE		 466 __be32 rsvd2[880];
467 __be32 internal_timer_h;
468 __be32 internal_timer_l;
b368d7cb 469 __be32 rsvd3[2];
e126ba97 470 __be32 health_counter;
b0844444 471 __be32 rsvd4[1019];
e126ba97
EC		 472 __be64 ieee1588_clk;
473 __be32 ieee1588_clk_type;
474 __be32 clr_intx;
475};
476
477struct mlx5_eqe_comp {
478 __be32 reserved[6];
479 __be32 cqn;
480};
481
482struct mlx5_eqe_qp_srq {
e2013b21 483 __be32 reserved1[5];
484 u8 type;
485 u8 reserved2[3];
e126ba97
EC		 486 __be32 qp_srq_n;
487};
488
489struct mlx5_eqe_cq_err {
490 __be32 cqn;
491 u8 reserved1[7];
492 u8 syndrome;
493};
494
e126ba97
EC		 495struct mlx5_eqe_port_state {
496 u8 reserved0[8];
497 u8 port;
498};
499
500struct mlx5_eqe_gpio {
501 __be32 reserved0[2];
502 __be64 gpio_event;
503};
504
505struct mlx5_eqe_congestion {
506 u8 type;
507 u8 rsvd0;
508 u8 congestion_level;
509};
510
511struct mlx5_eqe_stall_vl {
512 u8 rsvd0[3];
513 u8 port_vl;
514};
515
516struct mlx5_eqe_cmd {
517 __be32 vector;
518 __be32 rsvd[6];
519};
520
521struct mlx5_eqe_page_req {
522 u8 rsvd0[2];
523 __be16 func_id;
0a324f31
ML		 524 __be32 num_pages;
525 __be32 rsvd1[5];
e126ba97
EC		 526};
527
e420f0c0
HE		 528struct mlx5_eqe_page_fault {
529 __be32 bytes_committed;
530 union {
531 struct {
532 u16 reserved1;
533 __be16 wqe_index;
534 u16 reserved2;
535 __be16 packet_length;
536 u8 reserved3[12];
537 } __packed wqe;
538 struct {
539 __be32 r_key;
540 u16 reserved1;
541 __be16 packet_length;
542 __be32 rdma_op_len;
543 __be64 rdma_va;
544 } __packed rdma;
545 } __packed;
546 __be32 flags_qpn;
547} __packed;
548
073bb189
SM		 549struct mlx5_eqe_vport_change {
550 u8 rsvd0[2];
551 __be16 vport_num;
552 __be32 rsvd1[6];
553} __packed;
554
e126ba97
EC		 555union ev_data {
556 __be32 raw[7];
557 struct mlx5_eqe_cmd cmd;
558 struct mlx5_eqe_comp comp;
559 struct mlx5_eqe_qp_srq qp_srq;
560 struct mlx5_eqe_cq_err cq_err;
e126ba97
EC		 561 struct mlx5_eqe_port_state port;
562 struct mlx5_eqe_gpio gpio;
563 struct mlx5_eqe_congestion cong;
564 struct mlx5_eqe_stall_vl stall_vl;
565 struct mlx5_eqe_page_req req_pages;
e420f0c0 566 struct mlx5_eqe_page_fault page_fault;
073bb189 567 struct mlx5_eqe_vport_change vport_change;
e126ba97
EC		 568} __packed;
569
570struct mlx5_eqe {
571 u8 rsvd0;
572 u8 type;
573 u8 rsvd1;
574 u8 sub_type;
575 __be32 rsvd2[7];
576 union ev_data data;
577 __be16 rsvd3;
578 u8 signature;
579 u8 owner;
580} __packed;
581
582struct mlx5_cmd_prot_block {
583 u8 data[MLX5_CMD_DATA_BLOCK_SIZE];
584 u8 rsvd0[48];
585 __be64 next;
586 __be32 block_num;
587 u8 rsvd1;
588 u8 token;
589 u8 ctrl_sig;
590 u8 sig;
591};
592
e281682b
SM		 593enum {
594 MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5,
595};
596
e126ba97
EC		 597struct mlx5_err_cqe {
598 u8 rsvd0[32];
599 __be32 srqn;
600 u8 rsvd1[18];
601 u8 vendor_err_synd;
602 u8 syndrome;
603 __be32 s_wqe_opcode_qpn;
604 __be16 wqe_counter;
605 u8 signature;
606 u8 op_own;
607};
608
609struct mlx5_cqe64 {
1b223dd3
SM		 610 u8 outer_l3_tunneled;
611 u8 rsvd0;
612 __be16 wqe_id;
e281682b
SM		 613 u8 lro_tcppsh_abort_dupack;
614 u8 lro_min_ttl;
615 __be16 lro_tcp_win;
616 __be32 lro_ack_seq_num;
617 __be32 rss_hash_result;
618 u8 rss_hash_type;
e126ba97 619 u8 ml_path;
e281682b
SM		 620 u8 rsvd20[2];
621 __be16 check_sum;
e126ba97
EC		 622 __be16 slid;
623 __be32 flags_rqpn;
e281682b 624 u8 hds_ip_ext;
1b223dd3 625 u8 l4_l3_hdr_type;
e281682b
SM		 626 __be16 vlan_info;
627 __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */
e126ba97
EC		 628 __be32 imm_inval_pkey;
629 u8 rsvd40[4];
630 __be32 byte_cnt;
b0844444
EBE		 631 __be32 timestamp_h;
632 __be32 timestamp_l;
e126ba97
EC		 633 __be32 sop_drop_qpn;
634 __be16 wqe_counter;
635 u8 signature;
636 u8 op_own;
637};
638
7219ab34
TT		 639struct mlx5_mini_cqe8 {
640 union {
641 __be32 rx_hash_result;
642 struct {
643 __be16 checksum;
644 __be16 rsvd;
645 };
646 struct {
647 __be16 wqe_counter;
648 u8 s_wqe_opcode;
649 u8 reserved;
650 } s_wqe_info;
651 };
652 __be32 byte_cnt;
653};
654
655enum {
656 MLX5_NO_INLINE_DATA,
657 MLX5_INLINE_DATA32_SEG,
658 MLX5_INLINE_DATA64_SEG,
659 MLX5_COMPRESSED,
660};
661
662enum {
663 MLX5_CQE_FORMAT_CSUM = 0x1,
664};
665
666#define MLX5_MINI_CQE_ARRAY_SIZE 8
667
668static inline int mlx5_get_cqe_format(struct mlx5_cqe64 *cqe)
669{
670 return (cqe->op_own >> 2) & 0x3;
671}
672
e281682b
SM		 673static inline int get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe)
674{
675 return (cqe->lro_tcppsh_abort_dupack >> 6) & 1;
676}
677
678static inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe)
679{
1b223dd3
SM		 680 return (cqe->l4_l3_hdr_type >> 4) & 0x7;
681}
682
683static inline u8 get_cqe_l3_hdr_type(struct mlx5_cqe64 *cqe)
684{
685 return (cqe->l4_l3_hdr_type >> 2) & 0x3;
686}
687
688static inline u8 cqe_is_tunneled(struct mlx5_cqe64 *cqe)
689{
690 return cqe->outer_l3_tunneled & 0x1;
e281682b
SM		 691}
692
693static inline int cqe_has_vlan(struct mlx5_cqe64 *cqe)
694{
1b223dd3 695 return !!(cqe->l4_l3_hdr_type & 0x1);
e281682b
SM		 696}
697
b0844444
EBE		 698static inline u64 get_cqe_ts(struct mlx5_cqe64 *cqe)
699{
700 u32 hi, lo;
701
702 hi = be32_to_cpu(cqe->timestamp_h);
703 lo = be32_to_cpu(cqe->timestamp_l);
704
705 return (u64)lo | ((u64)hi << 32);
706}
707
461017cb
TT		 708struct mpwrq_cqe_bc {
709 __be16 filler_consumed_strides;
710 __be16 byte_cnt;
711};
712
713static inline u16 mpwrq_get_cqe_byte_cnt(struct mlx5_cqe64 *cqe)
714{
715 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
716
717 return be16_to_cpu(bc->byte_cnt);
718}
719
720static inline u16 mpwrq_get_cqe_bc_consumed_strides(struct mpwrq_cqe_bc *bc)
721{
722 return 0x7fff & be16_to_cpu(bc->filler_consumed_strides);
723}
724
725static inline u16 mpwrq_get_cqe_consumed_strides(struct mlx5_cqe64 *cqe)
726{
727 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
728
729 return mpwrq_get_cqe_bc_consumed_strides(bc);
730}
731
732static inline bool mpwrq_is_filler_cqe(struct mlx5_cqe64 *cqe)
733{
734 struct mpwrq_cqe_bc *bc = (struct mpwrq_cqe_bc *)&cqe->byte_cnt;
735
736 return 0x8000 & be16_to_cpu(bc->filler_consumed_strides);
737}
738
739static inline u16 mpwrq_get_cqe_stride_index(struct mlx5_cqe64 *cqe)
740{
741 return be16_to_cpu(cqe->wqe_counter);
742}
743
e281682b
SM		 744enum {
745 CQE_L4_HDR_TYPE_NONE = 0x0,
746 CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1,
747 CQE_L4_HDR_TYPE_UDP = 0x2,
748 CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3,
749 CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4,
750};
751
752enum {
753 CQE_RSS_HTYPE_IP = 0x3 << 6,
754 CQE_RSS_HTYPE_L4 = 0x3 << 2,
755};
756
cb34be6d
AS		 757enum {
758 MLX5_CQE_ROCE_L3_HEADER_TYPE_GRH = 0x0,
759 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV6 = 0x1,
760 MLX5_CQE_ROCE_L3_HEADER_TYPE_IPV4 = 0x2,
761};
762
e281682b
SM		 763enum {
764 CQE_L2_OK = 1 << 0,
765 CQE_L3_OK = 1 << 1,
766 CQE_L4_OK = 1 << 2,
767};
768
d5436ba0
SG		 769struct mlx5_sig_err_cqe {
770 u8 rsvd0[16];
771 __be32 expected_trans_sig;
772 __be32 actual_trans_sig;
773 __be32 expected_reftag;
774 __be32 actual_reftag;
775 __be16 syndrome;
776 u8 rsvd22[2];
777 __be32 mkey;
778 __be64 err_offset;
779 u8 rsvd30[8];
780 __be32 qpn;
781 u8 rsvd38[2];
782 u8 signature;
783 u8 op_own;
784};
785
e126ba97
EC		 786struct mlx5_wqe_srq_next_seg {
787 u8 rsvd0[2];
788 __be16 next_wqe_index;
789 u8 signature;
790 u8 rsvd1[11];
791};
792
793union mlx5_ext_cqe {
794 struct ib_grh grh;
795 u8 inl[64];
796};
797
798struct mlx5_cqe128 {
799 union mlx5_ext_cqe inl_grh;
800 struct mlx5_cqe64 cqe64;
801};
802
968e78dd
HE		 803enum {
804 MLX5_MKEY_STATUS_FREE = 1 << 6,
805};
806
ec22eb53
SM		 807enum {
808 MLX5_MKEY_REMOTE_INVAL = 1 << 24,
809 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
810 MLX5_MKEY_BSF_EN = 1 << 30,
811 MLX5_MKEY_LEN64 = 1 << 31,
812};
813
e126ba97
EC		 814struct mlx5_mkey_seg {
815 /* This is a two bit field occupying bits 31-30.
816 * bit 31 is always 0,
817 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
818 */
819 u8 status;
820 u8 pcie_control;
821 u8 flags;
822 u8 version;
823 __be32 qpn_mkey7_0;
824 u8 rsvd1[4];
825 __be32 flags_pd;
826 __be64 start_addr;
827 __be64 len;
828 __be32 bsfs_octo_size;
829 u8 rsvd2[16];
830 __be32 xlt_oct_size;
831 u8 rsvd3[3];
832 u8 log2_page_size;
833 u8 rsvd4[4];
834};
835
e126ba97
EC		 836#define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
837
838enum {
839 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0
840};
841
e281682b
SM		 842enum {
843 VPORT_STATE_DOWN = 0x0,
844 VPORT_STATE_UP = 0x1,
845};
846
81848731
SM		 847enum {
848 MLX5_ESW_VPORT_ADMIN_STATE_DOWN = 0x0,
849 MLX5_ESW_VPORT_ADMIN_STATE_UP = 0x1,
850 MLX5_ESW_VPORT_ADMIN_STATE_AUTO = 0x2,
851};
852
e281682b
SM		 853enum {
854 MLX5_L3_PROT_TYPE_IPV4 = 0,
855 MLX5_L3_PROT_TYPE_IPV6 = 1,
856};
857
858enum {
859 MLX5_L4_PROT_TYPE_TCP = 0,
860 MLX5_L4_PROT_TYPE_UDP = 1,
861};
862
863enum {
864 MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0,
865 MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1,
866 MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2,
867 MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3,
868 MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4,
869};
870
871enum {
872 MLX5_MATCH_OUTER_HEADERS = 1 << 0,
873 MLX5_MATCH_MISC_PARAMETERS = 1 << 1,
874 MLX5_MATCH_INNER_HEADERS = 1 << 2,
875
876};
877
878enum {
879 MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0,
880 MLX5_FLOW_TABLE_TYPE_ESWITCH = 4,
881};
882
883enum {
884 MLX5_FLOW_CONTEXT_DEST_TYPE_VPORT = 0,
885 MLX5_FLOW_CONTEXT_DEST_TYPE_FLOW_TABLE = 1,
886 MLX5_FLOW_CONTEXT_DEST_TYPE_TIR = 2,
887};
888
e16aea27
SM		 889enum mlx5_list_type {
890 MLX5_NVPRT_LIST_TYPE_UC = 0x0,
891 MLX5_NVPRT_LIST_TYPE_MC = 0x1,
892 MLX5_NVPRT_LIST_TYPE_VLAN = 0x2,
893};
894
e281682b
SM		 895enum {
896 MLX5_RQC_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
897 MLX5_RQC_RQ_TYPE_MEMORY_RQ_RPM = 0x1,
898};
899
928cfe87
TT		 900enum mlx5_wol_mode {
901 MLX5_WOL_DISABLE = 0,
902 MLX5_WOL_SECURED_MAGIC = 1 << 1,
903 MLX5_WOL_MAGIC = 1 << 2,
904 MLX5_WOL_ARP = 1 << 3,
905 MLX5_WOL_BROADCAST = 1 << 4,
906 MLX5_WOL_MULTICAST = 1 << 5,
907 MLX5_WOL_UNICAST = 1 << 6,
908 MLX5_WOL_PHY_ACTIVITY = 1 << 7,
909};
910
938fe83c
SM		 911/* MLX5 DEV CAPs */
912
913/* TODO: EAT.ME */
914enum mlx5_cap_mode {
915 HCA_CAP_OPMOD_GET_MAX = 0,
916 HCA_CAP_OPMOD_GET_CUR = 1,
917};
918
919enum mlx5_cap_type {
920 MLX5_CAP_GENERAL = 0,
921 MLX5_CAP_ETHERNET_OFFLOADS,
922 MLX5_CAP_ODP,
923 MLX5_CAP_ATOMIC,
924 MLX5_CAP_ROCE,
925 MLX5_CAP_IPOIB_OFFLOADS,
926 MLX5_CAP_EOIB_OFFLOADS,
927 MLX5_CAP_FLOW_TABLE,
495716b1 928 MLX5_CAP_ESWITCH_FLOW_TABLE,
d6666753 929 MLX5_CAP_ESWITCH,
3f0393a5
SG		 930 MLX5_CAP_RESERVED,
931 MLX5_CAP_VECTOR_CALC,
1466cc5b 932 MLX5_CAP_QOS,
938fe83c
SM		 933 /* NUM OF CAP Types */
934 MLX5_CAP_NUM
935};
936
937/* GET Dev Caps macros */
938#define MLX5_CAP_GEN(mdev, cap) \
939 MLX5_GET(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap)
940
941#define MLX5_CAP_GEN_MAX(mdev, cap) \
942 MLX5_GET(cmd_hca_cap, mdev->hca_caps_max[MLX5_CAP_GENERAL], cap)
943
944#define MLX5_CAP_ETH(mdev, cap) \
945 MLX5_GET(per_protocol_networking_offload_caps,\
946 mdev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap)
947
948#define MLX5_CAP_ETH_MAX(mdev, cap) \
949 MLX5_GET(per_protocol_networking_offload_caps,\
950 mdev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS], cap)
951
952#define MLX5_CAP_ROCE(mdev, cap) \
953 MLX5_GET(roce_cap, mdev->hca_caps_cur[MLX5_CAP_ROCE], cap)
954
955#define MLX5_CAP_ROCE_MAX(mdev, cap) \
956 MLX5_GET(roce_cap, mdev->hca_caps_max[MLX5_CAP_ROCE], cap)
957
958#define MLX5_CAP_ATOMIC(mdev, cap) \
959 MLX5_GET(atomic_caps, mdev->hca_caps_cur[MLX5_CAP_ATOMIC], cap)
960
961#define MLX5_CAP_ATOMIC_MAX(mdev, cap) \
962 MLX5_GET(atomic_caps, mdev->hca_caps_max[MLX5_CAP_ATOMIC], cap)
963
964#define MLX5_CAP_FLOWTABLE(mdev, cap) \
965 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_cur[MLX5_CAP_FLOW_TABLE], cap)
966
967#define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \
968 MLX5_GET(flow_table_nic_cap, mdev->hca_caps_max[MLX5_CAP_FLOW_TABLE], cap)
969
876d634d
MG		 970#define MLX5_CAP_FLOWTABLE_NIC_RX(mdev, cap) \
971 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.cap)
972
973#define MLX5_CAP_FLOWTABLE_NIC_RX_MAX(mdev, cap) \
974 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive.cap)
975
cea824d4
MG		 976#define MLX5_CAP_FLOWTABLE_SNIFFER_RX(mdev, cap) \
977 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive_sniffer.cap)
978
979#define MLX5_CAP_FLOWTABLE_SNIFFER_RX_MAX(mdev, cap) \
980 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_receive_sniffer.cap)
981
982#define MLX5_CAP_FLOWTABLE_SNIFFER_TX(mdev, cap) \
983 MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_transmit_sniffer.cap)
984
985#define MLX5_CAP_FLOWTABLE_SNIFFER_TX_MAX(mdev, cap) \
986 MLX5_CAP_FLOWTABLE_MAX(mdev, flow_table_properties_nic_transmit_sniffer.cap)
987
495716b1
SM		 988#define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \
989 MLX5_GET(flow_table_eswitch_cap, \
990 mdev->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
991
992#define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \
993 MLX5_GET(flow_table_eswitch_cap, \
994 mdev->hca_caps_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap)
995
996#define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \
997 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap)
998
999#define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \
1000 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap)
1001
efdc810b
MHY		 1002#define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \
1003 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap)
1004
1005#define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \
1006 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap)
1007
1008#define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \
1009 MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap)
1010
1011#define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \
1012 MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap)
1013
d6666753
SM		 1014#define MLX5_CAP_ESW(mdev, cap) \
1015 MLX5_GET(e_switch_cap, \
1016 mdev->hca_caps_cur[MLX5_CAP_ESWITCH], cap)
1017
1018#define MLX5_CAP_ESW_MAX(mdev, cap) \
1019 MLX5_GET(e_switch_cap, \
1020 mdev->hca_caps_max[MLX5_CAP_ESWITCH], cap)
1021
938fe83c
SM		 1022#define MLX5_CAP_ODP(mdev, cap)\
1023 MLX5_GET(odp_cap, mdev->hca_caps_cur[MLX5_CAP_ODP], cap)
1024
3f0393a5
SG		 1025#define MLX5_CAP_VECTOR_CALC(mdev, cap) \
1026 MLX5_GET(vector_calc_cap, \
1027 mdev->hca_caps_cur[MLX5_CAP_VECTOR_CALC], cap)
1028
1466cc5b
YP		 1029#define MLX5_CAP_QOS(mdev, cap)\
1030 MLX5_GET(qos_cap, mdev->hca_caps_cur[MLX5_CAP_QOS], cap)
1031
f62b8bb8
AV		 1032enum {
1033 MLX5_CMD_STAT_OK = 0x0,
1034 MLX5_CMD_STAT_INT_ERR = 0x1,
1035 MLX5_CMD_STAT_BAD_OP_ERR = 0x2,
1036 MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3,
1037 MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4,
1038 MLX5_CMD_STAT_BAD_RES_ERR = 0x5,
1039 MLX5_CMD_STAT_RES_BUSY = 0x6,
1040 MLX5_CMD_STAT_LIM_ERR = 0x8,
1041 MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9,
1042 MLX5_CMD_STAT_IX_ERR = 0xa,
1043 MLX5_CMD_STAT_NO_RES_ERR = 0xf,
1044 MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50,
1045 MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51,
1046 MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10,
1047 MLX5_CMD_STAT_BAD_PKT_ERR = 0x30,
1048 MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40,
1049};
1050
efea389d
GP		 1051enum {
1052 MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0,
1053 MLX5_RFC_2863_COUNTERS_GROUP = 0x1,
1054 MLX5_RFC_2819_COUNTERS_GROUP = 0x2,
1055 MLX5_RFC_3635_COUNTERS_GROUP = 0x3,
1056 MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5,
1057 MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10,
1c64bf6f 1058 MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11,
121fcdc8 1059 MLX5_PHYSICAL_LAYER_COUNTERS_GROUP = 0x12,
1c64bf6f 1060 MLX5_INFINIBAND_PORT_COUNTERS_GROUP = 0x20,
efea389d
GP		 1061};
1062
707c4602
MD		 1063static inline u16 mlx5_to_sw_pkey_sz(int pkey_sz)
1064{
1065 if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE)
1066 return 0;
1067 return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz;
1068}
1069
35d19011
MG		 1070#define MLX5_BY_PASS_NUM_REGULAR_PRIOS 8
1071#define MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS 8
1072#define MLX5_BY_PASS_NUM_MULTICAST_PRIOS 1
1073#define MLX5_BY_PASS_NUM_PRIOS (MLX5_BY_PASS_NUM_REGULAR_PRIOS +\
1074 MLX5_BY_PASS_NUM_DONT_TRAP_PRIOS +\
1075 MLX5_BY_PASS_NUM_MULTICAST_PRIOS)
4cbdd30e 1076
e126ba97 1077#endif /* MLX5_DEVICE_H */
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