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IB/mlx5: Update opt param mask for RTS2RTS
[mirror_ubuntu-bionic-kernel.git] / include / linux / mlx5 / device.h
CommitLineData
e126ba97
EC		 1/*
2 * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33#ifndef MLX5_DEVICE_H
34#define MLX5_DEVICE_H
35
36#include <linux/types.h>
37#include <rdma/ib_verbs.h>
38
39#if defined(__LITTLE_ENDIAN)
40#define MLX5_SET_HOST_ENDIANNESS 0
41#elif defined(__BIG_ENDIAN)
42#define MLX5_SET_HOST_ENDIANNESS 0x80
43#else
44#error Host endianness not defined
45#endif
46
47enum {
48 MLX5_MAX_COMMANDS = 32,
49 MLX5_CMD_DATA_BLOCK_SIZE = 512,
50 MLX5_PCI_CMD_XPORT = 7,
51};
52
53enum {
54 MLX5_EXTENDED_UD_AV = 0x80000000,
55};
56
57enum {
58 MLX5_CQ_STATE_ARMED = 9,
59 MLX5_CQ_STATE_ALWAYS_ARMED = 0xb,
60 MLX5_CQ_STATE_FIRED = 0xa,
61};
62
63enum {
64 MLX5_STAT_RATE_OFFSET = 5,
65};
66
67enum {
68 MLX5_INLINE_SEG = 0x80000000,
69};
70
71enum {
72 MLX5_PERM_LOCAL_READ = 1 << 2,
73 MLX5_PERM_LOCAL_WRITE = 1 << 3,
74 MLX5_PERM_REMOTE_READ = 1 << 4,
75 MLX5_PERM_REMOTE_WRITE = 1 << 5,
76 MLX5_PERM_ATOMIC = 1 << 6,
77 MLX5_PERM_UMR_EN = 1 << 7,
78};
79
80enum {
81 MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0,
82 MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2,
83 MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3,
84 MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6,
85 MLX5_PCIE_CTRL_TPH_MASK = 3 << 4,
86};
87
88enum {
89 MLX5_ACCESS_MODE_PA = 0,
90 MLX5_ACCESS_MODE_MTT = 1,
91 MLX5_ACCESS_MODE_KLM = 2
92};
93
94enum {
95 MLX5_MKEY_REMOTE_INVAL = 1 << 24,
96 MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29,
97 MLX5_MKEY_BSF_EN = 1 << 30,
98 MLX5_MKEY_LEN64 = 1 << 31,
99};
100
101enum {
102 MLX5_EN_RD = (u64)1,
103 MLX5_EN_WR = (u64)2
104};
105
106enum {
107 MLX5_BF_REGS_PER_PAGE = 4,
108 MLX5_MAX_UAR_PAGES = 1 << 8,
109 MLX5_MAX_UUARS = MLX5_MAX_UAR_PAGES * MLX5_BF_REGS_PER_PAGE,
110};
111
112enum {
113 MLX5_MKEY_MASK_LEN = 1ull << 0,
114 MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1,
115 MLX5_MKEY_MASK_START_ADDR = 1ull << 6,
116 MLX5_MKEY_MASK_PD = 1ull << 7,
117 MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8,
118 MLX5_MKEY_MASK_BSF_EN = 1ull << 12,
119 MLX5_MKEY_MASK_KEY = 1ull << 13,
120 MLX5_MKEY_MASK_QPN = 1ull << 14,
121 MLX5_MKEY_MASK_LR = 1ull << 17,
122 MLX5_MKEY_MASK_LW = 1ull << 18,
123 MLX5_MKEY_MASK_RR = 1ull << 19,
124 MLX5_MKEY_MASK_RW = 1ull << 20,
125 MLX5_MKEY_MASK_A = 1ull << 21,
126 MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23,
127 MLX5_MKEY_MASK_FREE = 1ull << 29,
128};
129
130enum mlx5_event {
131 MLX5_EVENT_TYPE_COMP = 0x0,
132
133 MLX5_EVENT_TYPE_PATH_MIG = 0x01,
134 MLX5_EVENT_TYPE_COMM_EST = 0x02,
135 MLX5_EVENT_TYPE_SQ_DRAINED = 0x03,
136 MLX5_EVENT_TYPE_SRQ_LAST_WQE = 0x13,
137 MLX5_EVENT_TYPE_SRQ_RQ_LIMIT = 0x14,
138
139 MLX5_EVENT_TYPE_CQ_ERROR = 0x04,
140 MLX5_EVENT_TYPE_WQ_CATAS_ERROR = 0x05,
141 MLX5_EVENT_TYPE_PATH_MIG_FAILED = 0x07,
142 MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
143 MLX5_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11,
144 MLX5_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12,
145
146 MLX5_EVENT_TYPE_INTERNAL_ERROR = 0x08,
147 MLX5_EVENT_TYPE_PORT_CHANGE = 0x09,
148 MLX5_EVENT_TYPE_GPIO_EVENT = 0x15,
149 MLX5_EVENT_TYPE_REMOTE_CONFIG = 0x19,
150
151 MLX5_EVENT_TYPE_DB_BF_CONGESTION = 0x1a,
152 MLX5_EVENT_TYPE_STALL_EVENT = 0x1b,
153
154 MLX5_EVENT_TYPE_CMD = 0x0a,
155 MLX5_EVENT_TYPE_PAGE_REQUEST = 0xb,
156};
157
158enum {
159 MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1,
160 MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4,
161 MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5,
162 MLX5_PORT_CHANGE_SUBTYPE_LID = 6,
163 MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7,
164 MLX5_PORT_CHANGE_SUBTYPE_GUID = 8,
165 MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9,
166};
167
168enum {
169 MLX5_DEV_CAP_FLAG_RC = 1LL << 0,
170 MLX5_DEV_CAP_FLAG_UC = 1LL << 1,
171 MLX5_DEV_CAP_FLAG_UD = 1LL << 2,
172 MLX5_DEV_CAP_FLAG_XRC = 1LL << 3,
173 MLX5_DEV_CAP_FLAG_SRQ = 1LL << 6,
174 MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8,
175 MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9,
176 MLX5_DEV_CAP_FLAG_APM = 1LL << 17,
177 MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 18,
178 MLX5_DEV_CAP_FLAG_ON_DMND_PG = 1LL << 24,
179 MLX5_DEV_CAP_FLAG_RESIZE_SRQ = 1LL << 32,
180 MLX5_DEV_CAP_FLAG_REMOTE_FENCE = 1LL << 38,
181 MLX5_DEV_CAP_FLAG_TLP_HINTS = 1LL << 39,
182 MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40,
183 MLX5_DEV_CAP_FLAG_DCT = 1LL << 41,
c1868b82 184 MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46,
e126ba97
EC		 185};
186
187enum {
188 MLX5_OPCODE_NOP = 0x00,
189 MLX5_OPCODE_SEND_INVAL = 0x01,
190 MLX5_OPCODE_RDMA_WRITE = 0x08,
191 MLX5_OPCODE_RDMA_WRITE_IMM = 0x09,
192 MLX5_OPCODE_SEND = 0x0a,
193 MLX5_OPCODE_SEND_IMM = 0x0b,
194 MLX5_OPCODE_RDMA_READ = 0x10,
195 MLX5_OPCODE_ATOMIC_CS = 0x11,
196 MLX5_OPCODE_ATOMIC_FA = 0x12,
197 MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14,
198 MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15,
199 MLX5_OPCODE_BIND_MW = 0x18,
200 MLX5_OPCODE_CONFIG_CMD = 0x1f,
201
202 MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00,
203 MLX5_RECV_OPCODE_SEND = 0x01,
204 MLX5_RECV_OPCODE_SEND_IMM = 0x02,
205 MLX5_RECV_OPCODE_SEND_INVAL = 0x03,
206
207 MLX5_CQE_OPCODE_ERROR = 0x1e,
208 MLX5_CQE_OPCODE_RESIZE = 0x16,
209
210 MLX5_OPCODE_SET_PSV = 0x20,
211 MLX5_OPCODE_GET_PSV = 0x21,
212 MLX5_OPCODE_CHECK_PSV = 0x22,
213 MLX5_OPCODE_RGET_PSV = 0x26,
214 MLX5_OPCODE_RCHECK_PSV = 0x27,
215
216 MLX5_OPCODE_UMR = 0x25,
217
218};
219
220enum {
221 MLX5_SET_PORT_RESET_QKEY = 0,
222 MLX5_SET_PORT_GUID0 = 16,
223 MLX5_SET_PORT_NODE_GUID = 17,
224 MLX5_SET_PORT_SYS_GUID = 18,
225 MLX5_SET_PORT_GID_TABLE = 19,
226 MLX5_SET_PORT_PKEY_TABLE = 20,
227};
228
229enum {
230 MLX5_MAX_PAGE_SHIFT = 31
231};
232
87b8de49
EC		 233enum {
234 MLX5_CAP_OFF_DCT = 41,
235 MLX5_CAP_OFF_CMDIF_CSUM = 46,
236};
237
e126ba97
EC		 238struct mlx5_inbox_hdr {
239 __be16 opcode;
240 u8 rsvd[4];
241 __be16 opmod;
242};
243
244struct mlx5_outbox_hdr {
245 u8 status;
246 u8 rsvd[3];
247 __be32 syndrome;
248};
249
250struct mlx5_cmd_query_adapter_mbox_in {
251 struct mlx5_inbox_hdr hdr;
252 u8 rsvd[8];
253};
254
255struct mlx5_cmd_query_adapter_mbox_out {
256 struct mlx5_outbox_hdr hdr;
257 u8 rsvd0[24];
258 u8 intapin;
259 u8 rsvd1[13];
260 __be16 vsd_vendor_id;
261 u8 vsd[208];
262 u8 vsd_psid[16];
263};
264
265struct mlx5_hca_cap {
266 u8 rsvd1[16];
267 u8 log_max_srq_sz;
268 u8 log_max_qp_sz;
269 u8 rsvd2;
270 u8 log_max_qp;
271 u8 log_max_strq_sz;
272 u8 log_max_srqs;
273 u8 rsvd4[2];
274 u8 rsvd5;
275 u8 log_max_cq_sz;
276 u8 rsvd6;
277 u8 log_max_cq;
278 u8 log_max_eq_sz;
279 u8 log_max_mkey;
280 u8 rsvd7;
281 u8 log_max_eq;
282 u8 max_indirection;
283 u8 log_max_mrw_sz;
284 u8 log_max_bsf_list_sz;
285 u8 log_max_klm_list_sz;
286 u8 rsvd_8_0;
287 u8 log_max_ra_req_dc;
288 u8 rsvd_8_1;
289 u8 log_max_ra_res_dc;
290 u8 rsvd9;
291 u8 log_max_ra_req_qp;
292 u8 rsvd10;
293 u8 log_max_ra_res_qp;
294 u8 rsvd11[4];
295 __be16 max_qp_count;
296 __be16 rsvd12;
297 u8 rsvd13;
298 u8 local_ca_ack_delay;
299 u8 rsvd14;
300 u8 num_ports;
301 u8 log_max_msg;
302 u8 rsvd15[3];
303 __be16 stat_rate_support;
304 u8 rsvd16[2];
305 __be64 flags;
306 u8 rsvd17;
307 u8 uar_sz;
308 u8 rsvd18;
309 u8 log_pg_sz;
310 __be16 bf_log_bf_reg_size;
311 u8 rsvd19[4];
312 __be16 max_desc_sz_sq;
313 u8 rsvd20[2];
314 __be16 max_desc_sz_rq;
315 u8 rsvd21[2];
316 __be16 max_desc_sz_sq_dc;
0a324f31
ML		 317 __be32 max_qp_mcg;
318 u8 rsvd22[3];
e126ba97 319 u8 log_max_mcg;
0a324f31 320 u8 rsvd23;
e126ba97 321 u8 log_max_pd;
0a324f31 322 u8 rsvd24;
e126ba97 323 u8 log_max_xrcd;
0a324f31 324 u8 rsvd25[42];
288dde9f 325 __be16 log_uar_page_sz;
0a324f31 326 u8 rsvd26[28];
87b8de49 327 u8 log_max_atomic_size_qp;
0a324f31 328 u8 rsvd27[2];
87b8de49 329 u8 log_max_atomic_size_dc;
0a324f31 330 u8 rsvd28[76];
e126ba97
EC		 331};
332
333
334struct mlx5_cmd_query_hca_cap_mbox_in {
335 struct mlx5_inbox_hdr hdr;
336 u8 rsvd[8];
337};
338
339
340struct mlx5_cmd_query_hca_cap_mbox_out {
341 struct mlx5_outbox_hdr hdr;
342 u8 rsvd0[8];
343 struct mlx5_hca_cap hca_cap;
344};
345
346
347struct mlx5_cmd_set_hca_cap_mbox_in {
348 struct mlx5_inbox_hdr hdr;
349 u8 rsvd[8];
350 struct mlx5_hca_cap hca_cap;
351};
352
353
354struct mlx5_cmd_set_hca_cap_mbox_out {
355 struct mlx5_outbox_hdr hdr;
356 u8 rsvd0[8];
357};
358
359
360struct mlx5_cmd_init_hca_mbox_in {
361 struct mlx5_inbox_hdr hdr;
362 u8 rsvd0[2];
363 __be16 profile;
364 u8 rsvd1[4];
365};
366
367struct mlx5_cmd_init_hca_mbox_out {
368 struct mlx5_outbox_hdr hdr;
369 u8 rsvd[8];
370};
371
372struct mlx5_cmd_teardown_hca_mbox_in {
373 struct mlx5_inbox_hdr hdr;
374 u8 rsvd0[2];
375 __be16 profile;
376 u8 rsvd1[4];
377};
378
379struct mlx5_cmd_teardown_hca_mbox_out {
380 struct mlx5_outbox_hdr hdr;
381 u8 rsvd[8];
382};
383
384struct mlx5_cmd_layout {
385 u8 type;
386 u8 rsvd0[3];
387 __be32 inlen;
388 __be64 in_ptr;
389 __be32 in[4];
390 __be32 out[4];
391 __be64 out_ptr;
392 __be32 outlen;
393 u8 token;
394 u8 sig;
395 u8 rsvd1;
396 u8 status_own;
397};
398
399
400struct health_buffer {
401 __be32 assert_var[5];
402 __be32 rsvd0[3];
403 __be32 assert_exit_ptr;
404 __be32 assert_callra;
405 __be32 rsvd1[2];
406 __be32 fw_ver;
407 __be32 hw_id;
408 __be32 rsvd2;
409 u8 irisc_index;
410 u8 synd;
411 __be16 ext_sync;
412};
413
414struct mlx5_init_seg {
415 __be32 fw_rev;
416 __be32 cmdif_rev_fw_sub;
417 __be32 rsvd0[2];
418 __be32 cmdq_addr_h;
419 __be32 cmdq_addr_l_sz;
420 __be32 cmd_dbell;
421 __be32 rsvd1[121];
422 struct health_buffer health;
423 __be32 rsvd2[884];
424 __be32 health_counter;
2f6daec1 425 __be32 rsvd3[1019];
e126ba97
EC		 426 __be64 ieee1588_clk;
427 __be32 ieee1588_clk_type;
428 __be32 clr_intx;
429};
430
431struct mlx5_eqe_comp {
432 __be32 reserved[6];
433 __be32 cqn;
434};
435
436struct mlx5_eqe_qp_srq {
437 __be32 reserved[6];
438 __be32 qp_srq_n;
439};
440
441struct mlx5_eqe_cq_err {
442 __be32 cqn;
443 u8 reserved1[7];
444 u8 syndrome;
445};
446
447struct mlx5_eqe_dropped_packet {
448};
449
450struct mlx5_eqe_port_state {
451 u8 reserved0[8];
452 u8 port;
453};
454
455struct mlx5_eqe_gpio {
456 __be32 reserved0[2];
457 __be64 gpio_event;
458};
459
460struct mlx5_eqe_congestion {
461 u8 type;
462 u8 rsvd0;
463 u8 congestion_level;
464};
465
466struct mlx5_eqe_stall_vl {
467 u8 rsvd0[3];
468 u8 port_vl;
469};
470
471struct mlx5_eqe_cmd {
472 __be32 vector;
473 __be32 rsvd[6];
474};
475
476struct mlx5_eqe_page_req {
477 u8 rsvd0[2];
478 __be16 func_id;
0a324f31
ML		 479 __be32 num_pages;
480 __be32 rsvd1[5];
e126ba97
EC		 481};
482
483union ev_data {
484 __be32 raw[7];
485 struct mlx5_eqe_cmd cmd;
486 struct mlx5_eqe_comp comp;
487 struct mlx5_eqe_qp_srq qp_srq;
488 struct mlx5_eqe_cq_err cq_err;
489 struct mlx5_eqe_dropped_packet dp;
490 struct mlx5_eqe_port_state port;
491 struct mlx5_eqe_gpio gpio;
492 struct mlx5_eqe_congestion cong;
493 struct mlx5_eqe_stall_vl stall_vl;
494 struct mlx5_eqe_page_req req_pages;
495} __packed;
496
497struct mlx5_eqe {
498 u8 rsvd0;
499 u8 type;
500 u8 rsvd1;
501 u8 sub_type;
502 __be32 rsvd2[7];
503 union ev_data data;
504 __be16 rsvd3;
505 u8 signature;
506 u8 owner;
507} __packed;
508
509struct mlx5_cmd_prot_block {
510 u8 data[MLX5_CMD_DATA_BLOCK_SIZE];
511 u8 rsvd0[48];
512 __be64 next;
513 __be32 block_num;
514 u8 rsvd1;
515 u8 token;
516 u8 ctrl_sig;
517 u8 sig;
518};
519
520struct mlx5_err_cqe {
521 u8 rsvd0[32];
522 __be32 srqn;
523 u8 rsvd1[18];
524 u8 vendor_err_synd;
525 u8 syndrome;
526 __be32 s_wqe_opcode_qpn;
527 __be16 wqe_counter;
528 u8 signature;
529 u8 op_own;
530};
531
532struct mlx5_cqe64 {
533 u8 rsvd0[17];
534 u8 ml_path;
535 u8 rsvd20[4];
536 __be16 slid;
537 __be32 flags_rqpn;
538 u8 rsvd28[4];
539 __be32 srqn;
540 __be32 imm_inval_pkey;
541 u8 rsvd40[4];
542 __be32 byte_cnt;
543 __be64 timestamp;
544 __be32 sop_drop_qpn;
545 __be16 wqe_counter;
546 u8 signature;
547 u8 op_own;
548};
549
550struct mlx5_wqe_srq_next_seg {
551 u8 rsvd0[2];
552 __be16 next_wqe_index;
553 u8 signature;
554 u8 rsvd1[11];
555};
556
557union mlx5_ext_cqe {
558 struct ib_grh grh;
559 u8 inl[64];
560};
561
562struct mlx5_cqe128 {
563 union mlx5_ext_cqe inl_grh;
564 struct mlx5_cqe64 cqe64;
565};
566
567struct mlx5_srq_ctx {
568 u8 state_log_sz;
569 u8 rsvd0[3];
570 __be32 flags_xrcd;
571 __be32 pgoff_cqn;
572 u8 rsvd1[4];
573 u8 log_pg_sz;
574 u8 rsvd2[7];
575 __be32 pd;
576 __be16 lwm;
577 __be16 wqe_cnt;
578 u8 rsvd3[8];
579 __be64 db_record;
580};
581
582struct mlx5_create_srq_mbox_in {
583 struct mlx5_inbox_hdr hdr;
584 __be32 input_srqn;
585 u8 rsvd0[4];
586 struct mlx5_srq_ctx ctx;
587 u8 rsvd1[208];
588 __be64 pas[0];
589};
590
591struct mlx5_create_srq_mbox_out {
592 struct mlx5_outbox_hdr hdr;
593 __be32 srqn;
594 u8 rsvd[4];
595};
596
597struct mlx5_destroy_srq_mbox_in {
598 struct mlx5_inbox_hdr hdr;
599 __be32 srqn;
600 u8 rsvd[4];
601};
602
603struct mlx5_destroy_srq_mbox_out {
604 struct mlx5_outbox_hdr hdr;
605 u8 rsvd[8];
606};
607
608struct mlx5_query_srq_mbox_in {
609 struct mlx5_inbox_hdr hdr;
610 __be32 srqn;
611 u8 rsvd0[4];
612};
613
614struct mlx5_query_srq_mbox_out {
615 struct mlx5_outbox_hdr hdr;
616 u8 rsvd0[8];
617 struct mlx5_srq_ctx ctx;
618 u8 rsvd1[32];
619 __be64 pas[0];
620};
621
622struct mlx5_arm_srq_mbox_in {
623 struct mlx5_inbox_hdr hdr;
624 __be32 srqn;
625 __be16 rsvd;
626 __be16 lwm;
627};
628
629struct mlx5_arm_srq_mbox_out {
630 struct mlx5_outbox_hdr hdr;
631 u8 rsvd[8];
632};
633
634struct mlx5_cq_context {
635 u8 status;
636 u8 cqe_sz_flags;
637 u8 st;
638 u8 rsvd3;
639 u8 rsvd4[6];
640 __be16 page_offset;
641 __be32 log_sz_usr_page;
642 __be16 cq_period;
643 __be16 cq_max_count;
644 __be16 rsvd20;
645 __be16 c_eqn;
646 u8 log_pg_sz;
647 u8 rsvd25[7];
648 __be32 last_notified_index;
649 __be32 solicit_producer_index;
650 __be32 consumer_counter;
651 __be32 producer_counter;
652 u8 rsvd48[8];
653 __be64 db_record_addr;
654};
655
656struct mlx5_create_cq_mbox_in {
657 struct mlx5_inbox_hdr hdr;
658 __be32 input_cqn;
659 u8 rsvdx[4];
660 struct mlx5_cq_context ctx;
661 u8 rsvd6[192];
662 __be64 pas[0];
663};
664
665struct mlx5_create_cq_mbox_out {
666 struct mlx5_outbox_hdr hdr;
667 __be32 cqn;
668 u8 rsvd0[4];
669};
670
671struct mlx5_destroy_cq_mbox_in {
672 struct mlx5_inbox_hdr hdr;
673 __be32 cqn;
674 u8 rsvd0[4];
675};
676
677struct mlx5_destroy_cq_mbox_out {
678 struct mlx5_outbox_hdr hdr;
679 u8 rsvd0[8];
680};
681
682struct mlx5_query_cq_mbox_in {
683 struct mlx5_inbox_hdr hdr;
684 __be32 cqn;
685 u8 rsvd0[4];
686};
687
688struct mlx5_query_cq_mbox_out {
689 struct mlx5_outbox_hdr hdr;
690 u8 rsvd0[8];
691 struct mlx5_cq_context ctx;
692 u8 rsvd6[16];
693 __be64 pas[0];
694};
695
cd23b14b
EC		 696struct mlx5_enable_hca_mbox_in {
697 struct mlx5_inbox_hdr hdr;
698 u8 rsvd[8];
699};
700
701struct mlx5_enable_hca_mbox_out {
702 struct mlx5_outbox_hdr hdr;
703 u8 rsvd[8];
704};
705
706struct mlx5_disable_hca_mbox_in {
707 struct mlx5_inbox_hdr hdr;
708 u8 rsvd[8];
709};
710
711struct mlx5_disable_hca_mbox_out {
712 struct mlx5_outbox_hdr hdr;
713 u8 rsvd[8];
714};
715
e126ba97
EC		 716struct mlx5_eq_context {
717 u8 status;
718 u8 ec_oi;
719 u8 st;
720 u8 rsvd2[7];
721 __be16 page_pffset;
722 __be32 log_sz_usr_page;
723 u8 rsvd3[7];
724 u8 intr;
725 u8 log_page_size;
726 u8 rsvd4[15];
727 __be32 consumer_counter;
728 __be32 produser_counter;
729 u8 rsvd5[16];
730};
731
732struct mlx5_create_eq_mbox_in {
733 struct mlx5_inbox_hdr hdr;
734 u8 rsvd0[3];
735 u8 input_eqn;
736 u8 rsvd1[4];
737 struct mlx5_eq_context ctx;
738 u8 rsvd2[8];
739 __be64 events_mask;
740 u8 rsvd3[176];
741 __be64 pas[0];
742};
743
744struct mlx5_create_eq_mbox_out {
745 struct mlx5_outbox_hdr hdr;
746 u8 rsvd0[3];
747 u8 eq_number;
748 u8 rsvd1[4];
749};
750
751struct mlx5_destroy_eq_mbox_in {
752 struct mlx5_inbox_hdr hdr;
753 u8 rsvd0[3];
754 u8 eqn;
755 u8 rsvd1[4];
756};
757
758struct mlx5_destroy_eq_mbox_out {
759 struct mlx5_outbox_hdr hdr;
760 u8 rsvd[8];
761};
762
763struct mlx5_map_eq_mbox_in {
764 struct mlx5_inbox_hdr hdr;
765 __be64 mask;
766 u8 mu;
767 u8 rsvd0[2];
768 u8 eqn;
769 u8 rsvd1[24];
770};
771
772struct mlx5_map_eq_mbox_out {
773 struct mlx5_outbox_hdr hdr;
774 u8 rsvd[8];
775};
776
777struct mlx5_query_eq_mbox_in {
778 struct mlx5_inbox_hdr hdr;
779 u8 rsvd0[3];
780 u8 eqn;
781 u8 rsvd1[4];
782};
783
784struct mlx5_query_eq_mbox_out {
785 struct mlx5_outbox_hdr hdr;
786 u8 rsvd[8];
787 struct mlx5_eq_context ctx;
788};
789
790struct mlx5_mkey_seg {
791 /* This is a two bit field occupying bits 31-30.
792 * bit 31 is always 0,
793 * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation
794 */
795 u8 status;
796 u8 pcie_control;
797 u8 flags;
798 u8 version;
799 __be32 qpn_mkey7_0;
800 u8 rsvd1[4];
801 __be32 flags_pd;
802 __be64 start_addr;
803 __be64 len;
804 __be32 bsfs_octo_size;
805 u8 rsvd2[16];
806 __be32 xlt_oct_size;
807 u8 rsvd3[3];
808 u8 log2_page_size;
809 u8 rsvd4[4];
810};
811
812struct mlx5_query_special_ctxs_mbox_in {
813 struct mlx5_inbox_hdr hdr;
814 u8 rsvd[8];
815};
816
817struct mlx5_query_special_ctxs_mbox_out {
818 struct mlx5_outbox_hdr hdr;
819 __be32 dump_fill_mkey;
820 __be32 reserved_lkey;
821};
822
823struct mlx5_create_mkey_mbox_in {
824 struct mlx5_inbox_hdr hdr;
825 __be32 input_mkey_index;
826 u8 rsvd0[4];
827 struct mlx5_mkey_seg seg;
828 u8 rsvd1[16];
829 __be32 xlat_oct_act_size;
830 __be32 bsf_coto_act_size;
831 u8 rsvd2[168];
832 __be64 pas[0];
833};
834
835struct mlx5_create_mkey_mbox_out {
836 struct mlx5_outbox_hdr hdr;
837 __be32 mkey;
838 u8 rsvd[4];
839};
840
841struct mlx5_destroy_mkey_mbox_in {
842 struct mlx5_inbox_hdr hdr;
843 __be32 mkey;
844 u8 rsvd[4];
845};
846
847struct mlx5_destroy_mkey_mbox_out {
848 struct mlx5_outbox_hdr hdr;
849 u8 rsvd[8];
850};
851
852struct mlx5_query_mkey_mbox_in {
853 struct mlx5_inbox_hdr hdr;
854 __be32 mkey;
855};
856
857struct mlx5_query_mkey_mbox_out {
858 struct mlx5_outbox_hdr hdr;
859 __be64 pas[0];
860};
861
862struct mlx5_modify_mkey_mbox_in {
863 struct mlx5_inbox_hdr hdr;
864 __be32 mkey;
865 __be64 pas[0];
866};
867
868struct mlx5_modify_mkey_mbox_out {
869 struct mlx5_outbox_hdr hdr;
870};
871
872struct mlx5_dump_mkey_mbox_in {
873 struct mlx5_inbox_hdr hdr;
874};
875
876struct mlx5_dump_mkey_mbox_out {
877 struct mlx5_outbox_hdr hdr;
878 __be32 mkey;
879};
880
881struct mlx5_mad_ifc_mbox_in {
882 struct mlx5_inbox_hdr hdr;
883 __be16 remote_lid;
884 u8 rsvd0;
885 u8 port;
886 u8 rsvd1[4];
887 u8 data[256];
888};
889
890struct mlx5_mad_ifc_mbox_out {
891 struct mlx5_outbox_hdr hdr;
892 u8 rsvd[8];
893 u8 data[256];
894};
895
896struct mlx5_access_reg_mbox_in {
897 struct mlx5_inbox_hdr hdr;
898 u8 rsvd0[2];
899 __be16 register_id;
900 __be32 arg;
901 __be32 data[0];
902};
903
904struct mlx5_access_reg_mbox_out {
905 struct mlx5_outbox_hdr hdr;
906 u8 rsvd[8];
907 __be32 data[0];
908};
909
910#define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90)
911
912enum {
913 MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0
914};
915
916#endif /* MLX5_DEVICE_H */
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