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e126ba97 | 1 | /* |
302bdf68 | 2 | * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. |
e126ba97 EC |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef MLX5_DRIVER_H | |
34 | #define MLX5_DRIVER_H | |
35 | ||
36 | #include <linux/kernel.h> | |
37 | #include <linux/completion.h> | |
38 | #include <linux/pci.h> | |
39 | #include <linux/spinlock_types.h> | |
40 | #include <linux/semaphore.h> | |
6ecde51d | 41 | #include <linux/slab.h> |
e126ba97 EC |
42 | #include <linux/vmalloc.h> |
43 | #include <linux/radix-tree.h> | |
6ecde51d | 44 | |
e126ba97 EC |
45 | #include <linux/mlx5/device.h> |
46 | #include <linux/mlx5/doorbell.h> | |
47 | ||
48 | enum { | |
49 | MLX5_BOARD_ID_LEN = 64, | |
50 | MLX5_MAX_NAME_LEN = 16, | |
51 | }; | |
52 | ||
53 | enum { | |
54 | /* one minute for the sake of bringup. Generally, commands must always | |
55 | * complete and we may need to increase this timeout value | |
56 | */ | |
57 | MLX5_CMD_TIMEOUT_MSEC = 7200 * 1000, | |
58 | MLX5_CMD_WQ_MAX_NAME = 32, | |
59 | }; | |
60 | ||
61 | enum { | |
62 | CMD_OWNER_SW = 0x0, | |
63 | CMD_OWNER_HW = 0x1, | |
64 | CMD_STATUS_SUCCESS = 0, | |
65 | }; | |
66 | ||
67 | enum mlx5_sqp_t { | |
68 | MLX5_SQP_SMI = 0, | |
69 | MLX5_SQP_GSI = 1, | |
70 | MLX5_SQP_IEEE_1588 = 2, | |
71 | MLX5_SQP_SNIFFER = 3, | |
72 | MLX5_SQP_SYNC_UMR = 4, | |
73 | }; | |
74 | ||
75 | enum { | |
76 | MLX5_MAX_PORTS = 2, | |
77 | }; | |
78 | ||
79 | enum { | |
80 | MLX5_EQ_VEC_PAGES = 0, | |
81 | MLX5_EQ_VEC_CMD = 1, | |
82 | MLX5_EQ_VEC_ASYNC = 2, | |
83 | MLX5_EQ_VEC_COMP_BASE, | |
84 | }; | |
85 | ||
86 | enum { | |
db058a18 | 87 | MLX5_MAX_IRQ_NAME = 32 |
e126ba97 EC |
88 | }; |
89 | ||
90 | enum { | |
91 | MLX5_ATOMIC_MODE_IB_COMP = 1 << 16, | |
92 | MLX5_ATOMIC_MODE_CX = 2 << 16, | |
93 | MLX5_ATOMIC_MODE_8B = 3 << 16, | |
94 | MLX5_ATOMIC_MODE_16B = 4 << 16, | |
95 | MLX5_ATOMIC_MODE_32B = 5 << 16, | |
96 | MLX5_ATOMIC_MODE_64B = 6 << 16, | |
97 | MLX5_ATOMIC_MODE_128B = 7 << 16, | |
98 | MLX5_ATOMIC_MODE_256B = 8 << 16, | |
99 | }; | |
100 | ||
e126ba97 EC |
101 | enum { |
102 | MLX5_REG_PCAP = 0x5001, | |
103 | MLX5_REG_PMTU = 0x5003, | |
104 | MLX5_REG_PTYS = 0x5004, | |
105 | MLX5_REG_PAOS = 0x5006, | |
3c2d18ef | 106 | MLX5_REG_PFCC = 0x5007, |
efea389d | 107 | MLX5_REG_PPCNT = 0x5008, |
e126ba97 EC |
108 | MLX5_REG_PMAOS = 0x5012, |
109 | MLX5_REG_PUDE = 0x5009, | |
110 | MLX5_REG_PMPE = 0x5010, | |
111 | MLX5_REG_PELC = 0x500e, | |
a124d13e | 112 | MLX5_REG_PVLC = 0x500f, |
e126ba97 EC |
113 | MLX5_REG_PMLP = 0, /* TBD */ |
114 | MLX5_REG_NODE_DESC = 0x6001, | |
115 | MLX5_REG_HOST_ENDIANNESS = 0x7004, | |
116 | }; | |
117 | ||
e420f0c0 HE |
118 | enum mlx5_page_fault_resume_flags { |
119 | MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0, | |
120 | MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1, | |
121 | MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2, | |
122 | MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7, | |
123 | }; | |
124 | ||
e126ba97 EC |
125 | enum dbg_rsc_type { |
126 | MLX5_DBG_RSC_QP, | |
127 | MLX5_DBG_RSC_EQ, | |
128 | MLX5_DBG_RSC_CQ, | |
129 | }; | |
130 | ||
131 | struct mlx5_field_desc { | |
132 | struct dentry *dent; | |
133 | int i; | |
134 | }; | |
135 | ||
136 | struct mlx5_rsc_debug { | |
137 | struct mlx5_core_dev *dev; | |
138 | void *object; | |
139 | enum dbg_rsc_type type; | |
140 | struct dentry *root; | |
141 | struct mlx5_field_desc fields[0]; | |
142 | }; | |
143 | ||
144 | enum mlx5_dev_event { | |
145 | MLX5_DEV_EVENT_SYS_ERROR, | |
146 | MLX5_DEV_EVENT_PORT_UP, | |
147 | MLX5_DEV_EVENT_PORT_DOWN, | |
148 | MLX5_DEV_EVENT_PORT_INITIALIZED, | |
149 | MLX5_DEV_EVENT_LID_CHANGE, | |
150 | MLX5_DEV_EVENT_PKEY_CHANGE, | |
151 | MLX5_DEV_EVENT_GUID_CHANGE, | |
152 | MLX5_DEV_EVENT_CLIENT_REREG, | |
153 | }; | |
154 | ||
4c916a79 | 155 | enum mlx5_port_status { |
6fa1bcab AS |
156 | MLX5_PORT_UP = 1, |
157 | MLX5_PORT_DOWN = 2, | |
4c916a79 RS |
158 | }; |
159 | ||
e126ba97 EC |
160 | struct mlx5_uuar_info { |
161 | struct mlx5_uar *uars; | |
162 | int num_uars; | |
163 | int num_low_latency_uuars; | |
164 | unsigned long *bitmap; | |
165 | unsigned int *count; | |
166 | struct mlx5_bf *bfs; | |
167 | ||
168 | /* | |
169 | * protect uuar allocation data structs | |
170 | */ | |
171 | struct mutex lock; | |
78c0f98c | 172 | u32 ver; |
e126ba97 EC |
173 | }; |
174 | ||
175 | struct mlx5_bf { | |
176 | void __iomem *reg; | |
177 | void __iomem *regreg; | |
178 | int buf_size; | |
179 | struct mlx5_uar *uar; | |
180 | unsigned long offset; | |
181 | int need_lock; | |
182 | /* protect blue flame buffer selection when needed | |
183 | */ | |
184 | spinlock_t lock; | |
185 | ||
186 | /* serialize 64 bit writes when done as two 32 bit accesses | |
187 | */ | |
188 | spinlock_t lock32; | |
189 | int uuarn; | |
190 | }; | |
191 | ||
192 | struct mlx5_cmd_first { | |
193 | __be32 data[4]; | |
194 | }; | |
195 | ||
196 | struct mlx5_cmd_msg { | |
197 | struct list_head list; | |
198 | struct cache_ent *cache; | |
199 | u32 len; | |
200 | struct mlx5_cmd_first first; | |
201 | struct mlx5_cmd_mailbox *next; | |
202 | }; | |
203 | ||
204 | struct mlx5_cmd_debug { | |
205 | struct dentry *dbg_root; | |
206 | struct dentry *dbg_in; | |
207 | struct dentry *dbg_out; | |
208 | struct dentry *dbg_outlen; | |
209 | struct dentry *dbg_status; | |
210 | struct dentry *dbg_run; | |
211 | void *in_msg; | |
212 | void *out_msg; | |
213 | u8 status; | |
214 | u16 inlen; | |
215 | u16 outlen; | |
216 | }; | |
217 | ||
218 | struct cache_ent { | |
219 | /* protect block chain allocations | |
220 | */ | |
221 | spinlock_t lock; | |
222 | struct list_head head; | |
223 | }; | |
224 | ||
225 | struct cmd_msg_cache { | |
226 | struct cache_ent large; | |
227 | struct cache_ent med; | |
228 | ||
229 | }; | |
230 | ||
231 | struct mlx5_cmd_stats { | |
232 | u64 sum; | |
233 | u64 n; | |
234 | struct dentry *root; | |
235 | struct dentry *avg; | |
236 | struct dentry *count; | |
237 | /* protect command average calculations */ | |
238 | spinlock_t lock; | |
239 | }; | |
240 | ||
241 | struct mlx5_cmd { | |
64599cca EC |
242 | void *cmd_alloc_buf; |
243 | dma_addr_t alloc_dma; | |
244 | int alloc_size; | |
e126ba97 EC |
245 | void *cmd_buf; |
246 | dma_addr_t dma; | |
247 | u16 cmdif_rev; | |
248 | u8 log_sz; | |
249 | u8 log_stride; | |
250 | int max_reg_cmds; | |
251 | int events; | |
252 | u32 __iomem *vector; | |
253 | ||
254 | /* protect command queue allocations | |
255 | */ | |
256 | spinlock_t alloc_lock; | |
257 | ||
258 | /* protect token allocations | |
259 | */ | |
260 | spinlock_t token_lock; | |
261 | u8 token; | |
262 | unsigned long bitmask; | |
263 | char wq_name[MLX5_CMD_WQ_MAX_NAME]; | |
264 | struct workqueue_struct *wq; | |
265 | struct semaphore sem; | |
266 | struct semaphore pages_sem; | |
267 | int mode; | |
268 | struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS]; | |
269 | struct pci_pool *pool; | |
270 | struct mlx5_cmd_debug dbg; | |
271 | struct cmd_msg_cache cache; | |
272 | int checksum_disabled; | |
273 | struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX]; | |
274 | }; | |
275 | ||
276 | struct mlx5_port_caps { | |
277 | int gid_table_len; | |
278 | int pkey_table_len; | |
938fe83c | 279 | u8 ext_port_cap; |
e126ba97 EC |
280 | }; |
281 | ||
282 | struct mlx5_cmd_mailbox { | |
283 | void *buf; | |
284 | dma_addr_t dma; | |
285 | struct mlx5_cmd_mailbox *next; | |
286 | }; | |
287 | ||
288 | struct mlx5_buf_list { | |
289 | void *buf; | |
290 | dma_addr_t map; | |
291 | }; | |
292 | ||
293 | struct mlx5_buf { | |
294 | struct mlx5_buf_list direct; | |
e126ba97 | 295 | int npages; |
e126ba97 | 296 | int size; |
f241e749 | 297 | u8 page_shift; |
e126ba97 EC |
298 | }; |
299 | ||
300 | struct mlx5_eq { | |
301 | struct mlx5_core_dev *dev; | |
302 | __be32 __iomem *doorbell; | |
303 | u32 cons_index; | |
304 | struct mlx5_buf buf; | |
305 | int size; | |
0b6e26ce | 306 | unsigned int irqn; |
e126ba97 EC |
307 | u8 eqn; |
308 | int nent; | |
309 | u64 mask; | |
e126ba97 EC |
310 | struct list_head list; |
311 | int index; | |
312 | struct mlx5_rsc_debug *dbg; | |
313 | }; | |
314 | ||
3121e3c4 SG |
315 | struct mlx5_core_psv { |
316 | u32 psv_idx; | |
317 | struct psv_layout { | |
318 | u32 pd; | |
319 | u16 syndrome; | |
320 | u16 reserved; | |
321 | u16 bg; | |
322 | u16 app_tag; | |
323 | u32 ref_tag; | |
324 | } psv; | |
325 | }; | |
326 | ||
327 | struct mlx5_core_sig_ctx { | |
328 | struct mlx5_core_psv psv_memory; | |
329 | struct mlx5_core_psv psv_wire; | |
d5436ba0 SG |
330 | struct ib_sig_err err_item; |
331 | bool sig_status_checked; | |
332 | bool sig_err_exists; | |
333 | u32 sigerr_count; | |
3121e3c4 | 334 | }; |
e126ba97 EC |
335 | |
336 | struct mlx5_core_mr { | |
337 | u64 iova; | |
338 | u64 size; | |
339 | u32 key; | |
340 | u32 pd; | |
e126ba97 EC |
341 | }; |
342 | ||
5903325a EC |
343 | enum mlx5_res_type { |
344 | MLX5_RES_QP, | |
01949d01 HA |
345 | MLX5_RES_SRQ, |
346 | MLX5_RES_XSRQ, | |
5903325a EC |
347 | }; |
348 | ||
349 | struct mlx5_core_rsc_common { | |
350 | enum mlx5_res_type res; | |
351 | atomic_t refcount; | |
352 | struct completion free; | |
353 | }; | |
354 | ||
e126ba97 | 355 | struct mlx5_core_srq { |
01949d01 | 356 | struct mlx5_core_rsc_common common; /* must be first */ |
e126ba97 EC |
357 | u32 srqn; |
358 | int max; | |
359 | int max_gs; | |
360 | int max_avail_gather; | |
361 | int wqe_shift; | |
362 | void (*event) (struct mlx5_core_srq *, enum mlx5_event); | |
363 | ||
364 | atomic_t refcount; | |
365 | struct completion free; | |
366 | }; | |
367 | ||
368 | struct mlx5_eq_table { | |
369 | void __iomem *update_ci; | |
370 | void __iomem *update_arm_ci; | |
233d05d2 | 371 | struct list_head comp_eqs_list; |
e126ba97 EC |
372 | struct mlx5_eq pages_eq; |
373 | struct mlx5_eq async_eq; | |
374 | struct mlx5_eq cmd_eq; | |
e126ba97 EC |
375 | int num_comp_vectors; |
376 | /* protect EQs list | |
377 | */ | |
378 | spinlock_t lock; | |
379 | }; | |
380 | ||
381 | struct mlx5_uar { | |
382 | u32 index; | |
383 | struct list_head bf_list; | |
384 | unsigned free_bf_bmap; | |
88a85f99 | 385 | void __iomem *bf_map; |
e126ba97 EC |
386 | void __iomem *map; |
387 | }; | |
388 | ||
389 | ||
390 | struct mlx5_core_health { | |
391 | struct health_buffer __iomem *health; | |
392 | __be32 __iomem *health_counter; | |
393 | struct timer_list timer; | |
e126ba97 EC |
394 | u32 prev; |
395 | int miss_counter; | |
fd76ee4d | 396 | bool sick; |
ac6ea6e8 EC |
397 | struct workqueue_struct *wq; |
398 | struct work_struct work; | |
e126ba97 EC |
399 | }; |
400 | ||
401 | struct mlx5_cq_table { | |
402 | /* protect radix tree | |
403 | */ | |
404 | spinlock_t lock; | |
405 | struct radix_tree_root tree; | |
406 | }; | |
407 | ||
408 | struct mlx5_qp_table { | |
409 | /* protect radix tree | |
410 | */ | |
411 | spinlock_t lock; | |
412 | struct radix_tree_root tree; | |
413 | }; | |
414 | ||
415 | struct mlx5_srq_table { | |
416 | /* protect radix tree | |
417 | */ | |
418 | spinlock_t lock; | |
419 | struct radix_tree_root tree; | |
420 | }; | |
421 | ||
3bcdb17a SG |
422 | struct mlx5_mr_table { |
423 | /* protect radix tree | |
424 | */ | |
425 | rwlock_t lock; | |
426 | struct radix_tree_root tree; | |
427 | }; | |
428 | ||
fc50db98 EC |
429 | struct mlx5_vf_context { |
430 | int enabled; | |
431 | }; | |
432 | ||
433 | struct mlx5_core_sriov { | |
434 | struct mlx5_vf_context *vfs_ctx; | |
435 | int num_vfs; | |
436 | int enabled_vfs; | |
437 | }; | |
438 | ||
db058a18 SM |
439 | struct mlx5_irq_info { |
440 | cpumask_var_t mask; | |
441 | char name[MLX5_MAX_IRQ_NAME]; | |
442 | }; | |
443 | ||
073bb189 SM |
444 | struct mlx5_eswitch; |
445 | ||
e126ba97 EC |
446 | struct mlx5_priv { |
447 | char name[MLX5_MAX_NAME_LEN]; | |
448 | struct mlx5_eq_table eq_table; | |
db058a18 SM |
449 | struct msix_entry *msix_arr; |
450 | struct mlx5_irq_info *irq_info; | |
e126ba97 EC |
451 | struct mlx5_uuar_info uuari; |
452 | MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock); | |
453 | ||
88a85f99 AS |
454 | struct io_mapping *bf_mapping; |
455 | ||
e126ba97 EC |
456 | /* pages stuff */ |
457 | struct workqueue_struct *pg_wq; | |
458 | struct rb_root page_root; | |
459 | int fw_pages; | |
6aec21f6 | 460 | atomic_t reg_pages; |
bf0bf77f | 461 | struct list_head free_list; |
fc50db98 | 462 | int vfs_pages; |
e126ba97 EC |
463 | |
464 | struct mlx5_core_health health; | |
465 | ||
466 | struct mlx5_srq_table srq_table; | |
467 | ||
468 | /* start: qp staff */ | |
469 | struct mlx5_qp_table qp_table; | |
470 | struct dentry *qp_debugfs; | |
471 | struct dentry *eq_debugfs; | |
472 | struct dentry *cq_debugfs; | |
473 | struct dentry *cmdif_debugfs; | |
474 | /* end: qp staff */ | |
475 | ||
476 | /* start: cq staff */ | |
477 | struct mlx5_cq_table cq_table; | |
478 | /* end: cq staff */ | |
479 | ||
3bcdb17a SG |
480 | /* start: mr staff */ |
481 | struct mlx5_mr_table mr_table; | |
482 | /* end: mr staff */ | |
483 | ||
e126ba97 | 484 | /* start: alloc staff */ |
311c7c71 SM |
485 | /* protect buffer alocation according to numa node */ |
486 | struct mutex alloc_mutex; | |
487 | int numa_node; | |
488 | ||
e126ba97 EC |
489 | struct mutex pgdir_mutex; |
490 | struct list_head pgdir_list; | |
491 | /* end: alloc staff */ | |
492 | struct dentry *dbg_root; | |
493 | ||
494 | /* protect mkey key part */ | |
495 | spinlock_t mkey_lock; | |
496 | u8 mkey_key; | |
9603b61d JM |
497 | |
498 | struct list_head dev_list; | |
499 | struct list_head ctx_list; | |
500 | spinlock_t ctx_lock; | |
073bb189 SM |
501 | |
502 | struct mlx5_eswitch *eswitch; | |
fc50db98 EC |
503 | struct mlx5_core_sriov sriov; |
504 | unsigned long pci_dev_data; | |
25302363 MG |
505 | struct mlx5_flow_root_namespace *root_ns; |
506 | struct mlx5_flow_root_namespace *fdb_root_ns; | |
e126ba97 EC |
507 | }; |
508 | ||
89d44f0a MD |
509 | enum mlx5_device_state { |
510 | MLX5_DEVICE_STATE_UP, | |
511 | MLX5_DEVICE_STATE_INTERNAL_ERROR, | |
512 | }; | |
513 | ||
514 | enum mlx5_interface_state { | |
515 | MLX5_INTERFACE_STATE_DOWN, | |
516 | MLX5_INTERFACE_STATE_UP, | |
517 | }; | |
518 | ||
519 | enum mlx5_pci_status { | |
520 | MLX5_PCI_STATUS_DISABLED, | |
521 | MLX5_PCI_STATUS_ENABLED, | |
522 | }; | |
523 | ||
e126ba97 EC |
524 | struct mlx5_core_dev { |
525 | struct pci_dev *pdev; | |
89d44f0a MD |
526 | /* sync pci state */ |
527 | struct mutex pci_status_mutex; | |
528 | enum mlx5_pci_status pci_status; | |
e126ba97 EC |
529 | u8 rev_id; |
530 | char board_id[MLX5_BOARD_ID_LEN]; | |
531 | struct mlx5_cmd cmd; | |
938fe83c SM |
532 | struct mlx5_port_caps port_caps[MLX5_MAX_PORTS]; |
533 | u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; | |
534 | u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; | |
e126ba97 EC |
535 | phys_addr_t iseg_base; |
536 | struct mlx5_init_seg __iomem *iseg; | |
89d44f0a MD |
537 | enum mlx5_device_state state; |
538 | /* sync interface state */ | |
539 | struct mutex intf_state_mutex; | |
540 | enum mlx5_interface_state interface_state; | |
e126ba97 EC |
541 | void (*event) (struct mlx5_core_dev *dev, |
542 | enum mlx5_dev_event event, | |
4d2f9bbb | 543 | unsigned long param); |
e126ba97 EC |
544 | struct mlx5_priv priv; |
545 | struct mlx5_profile *profile; | |
546 | atomic_t num_qps; | |
f62b8bb8 | 547 | u32 issi; |
e126ba97 EC |
548 | }; |
549 | ||
550 | struct mlx5_db { | |
551 | __be32 *db; | |
552 | union { | |
553 | struct mlx5_db_pgdir *pgdir; | |
554 | struct mlx5_ib_user_db_page *user_page; | |
555 | } u; | |
556 | dma_addr_t dma; | |
557 | int index; | |
558 | }; | |
559 | ||
560 | enum { | |
561 | MLX5_DB_PER_PAGE = PAGE_SIZE / L1_CACHE_BYTES, | |
562 | }; | |
563 | ||
564 | enum { | |
565 | MLX5_COMP_EQ_SIZE = 1024, | |
566 | }; | |
567 | ||
adb0c954 SM |
568 | enum { |
569 | MLX5_PTYS_IB = 1 << 0, | |
570 | MLX5_PTYS_EN = 1 << 2, | |
571 | }; | |
572 | ||
e126ba97 EC |
573 | struct mlx5_db_pgdir { |
574 | struct list_head list; | |
575 | DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE); | |
576 | __be32 *db_page; | |
577 | dma_addr_t db_dma; | |
578 | }; | |
579 | ||
580 | typedef void (*mlx5_cmd_cbk_t)(int status, void *context); | |
581 | ||
582 | struct mlx5_cmd_work_ent { | |
583 | struct mlx5_cmd_msg *in; | |
584 | struct mlx5_cmd_msg *out; | |
746b5583 EC |
585 | void *uout; |
586 | int uout_size; | |
e126ba97 EC |
587 | mlx5_cmd_cbk_t callback; |
588 | void *context; | |
746b5583 | 589 | int idx; |
e126ba97 EC |
590 | struct completion done; |
591 | struct mlx5_cmd *cmd; | |
592 | struct work_struct work; | |
593 | struct mlx5_cmd_layout *lay; | |
594 | int ret; | |
595 | int page_queue; | |
596 | u8 status; | |
597 | u8 token; | |
14a70046 TG |
598 | u64 ts1; |
599 | u64 ts2; | |
746b5583 | 600 | u16 op; |
e126ba97 EC |
601 | }; |
602 | ||
603 | struct mlx5_pas { | |
604 | u64 pa; | |
605 | u8 log_sz; | |
606 | }; | |
607 | ||
707c4602 MD |
608 | enum port_state_policy { |
609 | MLX5_AAA_000 | |
610 | }; | |
611 | ||
612 | enum phy_port_state { | |
613 | MLX5_AAA_111 | |
614 | }; | |
615 | ||
616 | struct mlx5_hca_vport_context { | |
617 | u32 field_select; | |
618 | bool sm_virt_aware; | |
619 | bool has_smi; | |
620 | bool has_raw; | |
621 | enum port_state_policy policy; | |
622 | enum phy_port_state phys_state; | |
623 | enum ib_port_state vport_state; | |
624 | u8 port_physical_state; | |
625 | u64 sys_image_guid; | |
626 | u64 port_guid; | |
627 | u64 node_guid; | |
628 | u32 cap_mask1; | |
629 | u32 cap_mask1_perm; | |
630 | u32 cap_mask2; | |
631 | u32 cap_mask2_perm; | |
632 | u16 lid; | |
633 | u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */ | |
634 | u8 lmc; | |
635 | u8 subnet_timeout; | |
636 | u16 sm_lid; | |
637 | u8 sm_sl; | |
638 | u16 qkey_violation_counter; | |
639 | u16 pkey_violation_counter; | |
640 | bool grh_required; | |
641 | }; | |
642 | ||
e126ba97 EC |
643 | static inline void *mlx5_buf_offset(struct mlx5_buf *buf, int offset) |
644 | { | |
e126ba97 | 645 | return buf->direct.buf + offset; |
e126ba97 EC |
646 | } |
647 | ||
648 | extern struct workqueue_struct *mlx5_core_wq; | |
649 | ||
650 | #define STRUCT_FIELD(header, field) \ | |
651 | .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \ | |
652 | .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field | |
653 | ||
654 | struct ib_field { | |
655 | size_t struct_offset_bytes; | |
656 | size_t struct_size_bytes; | |
657 | int offset_bits; | |
658 | int size_bits; | |
659 | }; | |
660 | ||
661 | static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev) | |
662 | { | |
663 | return pci_get_drvdata(pdev); | |
664 | } | |
665 | ||
666 | extern struct dentry *mlx5_debugfs_root; | |
667 | ||
668 | static inline u16 fw_rev_maj(struct mlx5_core_dev *dev) | |
669 | { | |
670 | return ioread32be(&dev->iseg->fw_rev) & 0xffff; | |
671 | } | |
672 | ||
673 | static inline u16 fw_rev_min(struct mlx5_core_dev *dev) | |
674 | { | |
675 | return ioread32be(&dev->iseg->fw_rev) >> 16; | |
676 | } | |
677 | ||
678 | static inline u16 fw_rev_sub(struct mlx5_core_dev *dev) | |
679 | { | |
680 | return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff; | |
681 | } | |
682 | ||
683 | static inline u16 cmdif_rev(struct mlx5_core_dev *dev) | |
684 | { | |
685 | return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16; | |
686 | } | |
687 | ||
688 | static inline void *mlx5_vzalloc(unsigned long size) | |
689 | { | |
690 | void *rtn; | |
691 | ||
692 | rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN); | |
693 | if (!rtn) | |
694 | rtn = vzalloc(size); | |
695 | return rtn; | |
696 | } | |
697 | ||
3bcdb17a SG |
698 | static inline u32 mlx5_base_mkey(const u32 key) |
699 | { | |
700 | return key & 0xffffff00u; | |
701 | } | |
702 | ||
e126ba97 EC |
703 | int mlx5_cmd_init(struct mlx5_core_dev *dev); |
704 | void mlx5_cmd_cleanup(struct mlx5_core_dev *dev); | |
705 | void mlx5_cmd_use_events(struct mlx5_core_dev *dev); | |
706 | void mlx5_cmd_use_polling(struct mlx5_core_dev *dev); | |
707 | int mlx5_cmd_status_to_err(struct mlx5_outbox_hdr *hdr); | |
b775516b | 708 | int mlx5_cmd_status_to_err_v2(void *ptr); |
938fe83c SM |
709 | int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type, |
710 | enum mlx5_cap_mode cap_mode); | |
e126ba97 EC |
711 | int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out, |
712 | int out_size); | |
746b5583 EC |
713 | int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size, |
714 | void *out, int out_size, mlx5_cmd_cbk_t callback, | |
715 | void *context); | |
e126ba97 EC |
716 | int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn); |
717 | int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn); | |
718 | int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari); | |
719 | int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari); | |
e281682b SM |
720 | int mlx5_alloc_map_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar); |
721 | void mlx5_unmap_free_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar); | |
ac6ea6e8 EC |
722 | void mlx5_health_cleanup(struct mlx5_core_dev *dev); |
723 | int mlx5_health_init(struct mlx5_core_dev *dev); | |
e126ba97 EC |
724 | void mlx5_start_health_poll(struct mlx5_core_dev *dev); |
725 | void mlx5_stop_health_poll(struct mlx5_core_dev *dev); | |
311c7c71 SM |
726 | int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size, |
727 | struct mlx5_buf *buf, int node); | |
64ffaa21 | 728 | int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, struct mlx5_buf *buf); |
e126ba97 EC |
729 | void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf); |
730 | struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev, | |
731 | gfp_t flags, int npages); | |
732 | void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev, | |
733 | struct mlx5_cmd_mailbox *head); | |
734 | int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, | |
01949d01 HA |
735 | struct mlx5_create_srq_mbox_in *in, int inlen, |
736 | int is_xrc); | |
e126ba97 EC |
737 | int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq); |
738 | int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, | |
739 | struct mlx5_query_srq_mbox_out *out); | |
740 | int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, | |
741 | u16 lwm, int is_srq); | |
3bcdb17a SG |
742 | void mlx5_init_mr_table(struct mlx5_core_dev *dev); |
743 | void mlx5_cleanup_mr_table(struct mlx5_core_dev *dev); | |
e126ba97 | 744 | int mlx5_core_create_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr, |
746b5583 EC |
745 | struct mlx5_create_mkey_mbox_in *in, int inlen, |
746 | mlx5_cmd_cbk_t callback, void *context, | |
747 | struct mlx5_create_mkey_mbox_out *out); | |
e126ba97 EC |
748 | int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr); |
749 | int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr, | |
750 | struct mlx5_query_mkey_mbox_out *out, int outlen); | |
751 | int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr, | |
752 | u32 *mkey); | |
753 | int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn); | |
754 | int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn); | |
a97e2d86 | 755 | int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, const void *inb, void *outb, |
f241e749 | 756 | u16 opmod, u8 port); |
e126ba97 EC |
757 | void mlx5_pagealloc_init(struct mlx5_core_dev *dev); |
758 | void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev); | |
759 | int mlx5_pagealloc_start(struct mlx5_core_dev *dev); | |
760 | void mlx5_pagealloc_stop(struct mlx5_core_dev *dev); | |
fc50db98 EC |
761 | int mlx5_sriov_init(struct mlx5_core_dev *dev); |
762 | int mlx5_sriov_cleanup(struct mlx5_core_dev *dev); | |
e126ba97 | 763 | void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id, |
0a324f31 | 764 | s32 npages); |
cd23b14b | 765 | int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot); |
e126ba97 EC |
766 | int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev); |
767 | void mlx5_register_debugfs(void); | |
768 | void mlx5_unregister_debugfs(void); | |
769 | int mlx5_eq_init(struct mlx5_core_dev *dev); | |
770 | void mlx5_eq_cleanup(struct mlx5_core_dev *dev); | |
771 | void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas); | |
772 | void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn); | |
5903325a | 773 | void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type); |
e420f0c0 HE |
774 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
775 | void mlx5_eq_pagefault(struct mlx5_core_dev *dev, struct mlx5_eqe *eqe); | |
776 | #endif | |
e126ba97 EC |
777 | void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type); |
778 | struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn); | |
020446e0 | 779 | void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, u64 vec); |
e126ba97 EC |
780 | void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type); |
781 | int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx, | |
782 | int nent, u64 mask, const char *name, struct mlx5_uar *uar); | |
783 | int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq); | |
784 | int mlx5_start_eqs(struct mlx5_core_dev *dev); | |
785 | int mlx5_stop_eqs(struct mlx5_core_dev *dev); | |
0b6e26ce DT |
786 | int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, |
787 | unsigned int *irqn); | |
e126ba97 EC |
788 | int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); |
789 | int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); | |
790 | ||
791 | int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev); | |
792 | void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev); | |
793 | int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in, | |
794 | int size_in, void *data_out, int size_out, | |
795 | u16 reg_num, int arg, int write); | |
adb0c954 | 796 | |
f241e749 | 797 | int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps); |
adb0c954 | 798 | int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys, |
a05bdefa | 799 | int ptys_size, int proto_mask, u8 local_port); |
adb0c954 SM |
800 | int mlx5_query_port_proto_cap(struct mlx5_core_dev *dev, |
801 | u32 *proto_cap, int proto_mask); | |
802 | int mlx5_query_port_proto_admin(struct mlx5_core_dev *dev, | |
803 | u32 *proto_admin, int proto_mask); | |
a124d13e MD |
804 | int mlx5_query_port_link_width_oper(struct mlx5_core_dev *dev, |
805 | u8 *link_width_oper, u8 local_port); | |
806 | int mlx5_query_port_proto_oper(struct mlx5_core_dev *dev, | |
807 | u8 *proto_oper, int proto_mask, | |
808 | u8 local_port); | |
adb0c954 SM |
809 | int mlx5_set_port_proto(struct mlx5_core_dev *dev, u32 proto_admin, |
810 | int proto_mask); | |
6fa1bcab AS |
811 | int mlx5_set_port_admin_status(struct mlx5_core_dev *dev, |
812 | enum mlx5_port_status status); | |
813 | int mlx5_query_port_admin_status(struct mlx5_core_dev *dev, | |
814 | enum mlx5_port_status *status); | |
e126ba97 | 815 | |
facc9699 SM |
816 | int mlx5_set_port_mtu(struct mlx5_core_dev *dev, int mtu, u8 port); |
817 | void mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, int *max_mtu, u8 port); | |
818 | void mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, int *oper_mtu, | |
819 | u8 port); | |
820 | ||
a124d13e MD |
821 | int mlx5_query_port_vl_hw_cap(struct mlx5_core_dev *dev, |
822 | u8 *vl_hw_cap, u8 local_port); | |
e126ba97 | 823 | |
3c2d18ef AS |
824 | int mlx5_set_port_pause(struct mlx5_core_dev *dev, u32 rx_pause, u32 tx_pause); |
825 | int mlx5_query_port_pause(struct mlx5_core_dev *dev, | |
826 | u32 *rx_pause, u32 *tx_pause); | |
827 | ||
e126ba97 EC |
828 | int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq); |
829 | void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq); | |
830 | int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq, | |
831 | struct mlx5_query_eq_mbox_out *out, int outlen); | |
832 | int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev); | |
833 | void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev); | |
834 | int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev); | |
835 | void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev); | |
836 | int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db); | |
311c7c71 SM |
837 | int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db, |
838 | int node); | |
e126ba97 EC |
839 | void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db); |
840 | ||
e126ba97 EC |
841 | const char *mlx5_command_str(int command); |
842 | int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev); | |
843 | void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev); | |
3121e3c4 SG |
844 | int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn, |
845 | int npsvs, u32 *sig_index); | |
846 | int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num); | |
5903325a | 847 | void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common); |
e420f0c0 HE |
848 | int mlx5_query_odp_caps(struct mlx5_core_dev *dev, |
849 | struct mlx5_odp_caps *odp_caps); | |
e126ba97 | 850 | |
e3297246 EC |
851 | static inline int fw_initializing(struct mlx5_core_dev *dev) |
852 | { | |
853 | return ioread32be(&dev->iseg->initializing) >> 31; | |
854 | } | |
855 | ||
e126ba97 EC |
856 | static inline u32 mlx5_mkey_to_idx(u32 mkey) |
857 | { | |
858 | return mkey >> 8; | |
859 | } | |
860 | ||
861 | static inline u32 mlx5_idx_to_mkey(u32 mkey_idx) | |
862 | { | |
863 | return mkey_idx << 8; | |
864 | } | |
865 | ||
746b5583 EC |
866 | static inline u8 mlx5_mkey_variant(u32 mkey) |
867 | { | |
868 | return mkey & 0xff; | |
869 | } | |
870 | ||
e126ba97 EC |
871 | enum { |
872 | MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0, | |
c1868b82 | 873 | MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1, |
e126ba97 EC |
874 | }; |
875 | ||
876 | enum { | |
877 | MAX_MR_CACHE_ENTRIES = 16, | |
878 | }; | |
879 | ||
64613d94 SM |
880 | enum { |
881 | MLX5_INTERFACE_PROTOCOL_IB = 0, | |
882 | MLX5_INTERFACE_PROTOCOL_ETH = 1, | |
883 | }; | |
884 | ||
9603b61d JM |
885 | struct mlx5_interface { |
886 | void * (*add)(struct mlx5_core_dev *dev); | |
887 | void (*remove)(struct mlx5_core_dev *dev, void *context); | |
888 | void (*event)(struct mlx5_core_dev *dev, void *context, | |
4d2f9bbb | 889 | enum mlx5_dev_event event, unsigned long param); |
64613d94 SM |
890 | void * (*get_dev)(void *context); |
891 | int protocol; | |
9603b61d JM |
892 | struct list_head list; |
893 | }; | |
894 | ||
64613d94 | 895 | void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol); |
9603b61d JM |
896 | int mlx5_register_interface(struct mlx5_interface *intf); |
897 | void mlx5_unregister_interface(struct mlx5_interface *intf); | |
211e6c80 | 898 | int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id); |
9603b61d | 899 | |
e126ba97 EC |
900 | struct mlx5_profile { |
901 | u64 mask; | |
f241e749 | 902 | u8 log_max_qp; |
e126ba97 EC |
903 | struct { |
904 | int size; | |
905 | int limit; | |
906 | } mr_cache[MAX_MR_CACHE_ENTRIES]; | |
907 | }; | |
908 | ||
fc50db98 EC |
909 | enum { |
910 | MLX5_PCI_DEV_IS_VF = 1 << 0, | |
911 | }; | |
912 | ||
913 | static inline int mlx5_core_is_pf(struct mlx5_core_dev *dev) | |
914 | { | |
915 | return !(dev->priv.pci_dev_data & MLX5_PCI_DEV_IS_VF); | |
916 | } | |
917 | ||
707c4602 MD |
918 | static inline int mlx5_get_gid_table_len(u16 param) |
919 | { | |
920 | if (param > 4) { | |
921 | pr_warn("gid table length is zero\n"); | |
922 | return 0; | |
923 | } | |
924 | ||
925 | return 8 * (1 << param); | |
926 | } | |
927 | ||
020446e0 EC |
928 | enum { |
929 | MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32, | |
930 | }; | |
931 | ||
e126ba97 | 932 | #endif /* MLX5_DRIVER_H */ |