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e126ba97 | 1 | /* |
302bdf68 | 2 | * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. |
e126ba97 EC |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef MLX5_DRIVER_H | |
34 | #define MLX5_DRIVER_H | |
35 | ||
36 | #include <linux/kernel.h> | |
37 | #include <linux/completion.h> | |
38 | #include <linux/pci.h> | |
05e0cc84 | 39 | #include <linux/irq.h> |
e126ba97 EC |
40 | #include <linux/spinlock_types.h> |
41 | #include <linux/semaphore.h> | |
6ecde51d | 42 | #include <linux/slab.h> |
e126ba97 | 43 | #include <linux/vmalloc.h> |
792c4e9d | 44 | #include <linux/xarray.h> |
43a335e0 | 45 | #include <linux/workqueue.h> |
d9aaed83 | 46 | #include <linux/mempool.h> |
94c6825e | 47 | #include <linux/interrupt.h> |
52ec462e | 48 | #include <linux/idr.h> |
20902be4 | 49 | #include <linux/notifier.h> |
94f3e14e | 50 | #include <linux/refcount.h> |
6ecde51d | 51 | |
e126ba97 EC |
52 | #include <linux/mlx5/device.h> |
53 | #include <linux/mlx5/doorbell.h> | |
41069256 | 54 | #include <linux/mlx5/eq.h> |
7c39afb3 FD |
55 | #include <linux/timecounter.h> |
56 | #include <linux/ptp_clock_kernel.h> | |
1e34f3ef | 57 | #include <net/devlink.h> |
e126ba97 EC |
58 | |
59 | enum { | |
60 | MLX5_BOARD_ID_LEN = 64, | |
e126ba97 EC |
61 | }; |
62 | ||
63 | enum { | |
64 | /* one minute for the sake of bringup. Generally, commands must always | |
65 | * complete and we may need to increase this timeout value | |
66 | */ | |
6b6c07bd | 67 | MLX5_CMD_TIMEOUT_MSEC = 60 * 1000, |
e126ba97 EC |
68 | MLX5_CMD_WQ_MAX_NAME = 32, |
69 | }; | |
70 | ||
71 | enum { | |
72 | CMD_OWNER_SW = 0x0, | |
73 | CMD_OWNER_HW = 0x1, | |
74 | CMD_STATUS_SUCCESS = 0, | |
75 | }; | |
76 | ||
77 | enum mlx5_sqp_t { | |
78 | MLX5_SQP_SMI = 0, | |
79 | MLX5_SQP_GSI = 1, | |
80 | MLX5_SQP_IEEE_1588 = 2, | |
81 | MLX5_SQP_SNIFFER = 3, | |
82 | MLX5_SQP_SYNC_UMR = 4, | |
83 | }; | |
84 | ||
85 | enum { | |
86 | MLX5_MAX_PORTS = 2, | |
87 | }; | |
88 | ||
e126ba97 | 89 | enum { |
a60109dc YC |
90 | MLX5_ATOMIC_MODE_OFFSET = 16, |
91 | MLX5_ATOMIC_MODE_IB_COMP = 1, | |
92 | MLX5_ATOMIC_MODE_CX = 2, | |
93 | MLX5_ATOMIC_MODE_8B = 3, | |
94 | MLX5_ATOMIC_MODE_16B = 4, | |
95 | MLX5_ATOMIC_MODE_32B = 5, | |
96 | MLX5_ATOMIC_MODE_64B = 6, | |
97 | MLX5_ATOMIC_MODE_128B = 7, | |
98 | MLX5_ATOMIC_MODE_256B = 8, | |
e126ba97 EC |
99 | }; |
100 | ||
e126ba97 | 101 | enum { |
415a64aa | 102 | MLX5_REG_QPTS = 0x4002, |
4f3961ee SM |
103 | MLX5_REG_QETCR = 0x4005, |
104 | MLX5_REG_QTCT = 0x400a, | |
415a64aa | 105 | MLX5_REG_QPDPM = 0x4013, |
c02762eb | 106 | MLX5_REG_QCAM = 0x4019, |
341c5ee2 HN |
107 | MLX5_REG_DCBX_PARAM = 0x4020, |
108 | MLX5_REG_DCBX_APP = 0x4021, | |
e29341fb IT |
109 | MLX5_REG_FPGA_CAP = 0x4022, |
110 | MLX5_REG_FPGA_CTRL = 0x4023, | |
a9956d35 | 111 | MLX5_REG_FPGA_ACCESS_REG = 0x4024, |
0b9055a1 | 112 | MLX5_REG_CORE_DUMP = 0x402e, |
e126ba97 EC |
113 | MLX5_REG_PCAP = 0x5001, |
114 | MLX5_REG_PMTU = 0x5003, | |
115 | MLX5_REG_PTYS = 0x5004, | |
116 | MLX5_REG_PAOS = 0x5006, | |
3c2d18ef | 117 | MLX5_REG_PFCC = 0x5007, |
efea389d | 118 | MLX5_REG_PPCNT = 0x5008, |
50b4a3c2 HN |
119 | MLX5_REG_PPTB = 0x500b, |
120 | MLX5_REG_PBMC = 0x500c, | |
e126ba97 EC |
121 | MLX5_REG_PMAOS = 0x5012, |
122 | MLX5_REG_PUDE = 0x5009, | |
123 | MLX5_REG_PMPE = 0x5010, | |
124 | MLX5_REG_PELC = 0x500e, | |
a124d13e | 125 | MLX5_REG_PVLC = 0x500f, |
94cb1ebb | 126 | MLX5_REG_PCMR = 0x5041, |
bb64143e | 127 | MLX5_REG_PMLP = 0x5002, |
4b5b9c7d | 128 | MLX5_REG_PPLM = 0x5023, |
cfdcbcea | 129 | MLX5_REG_PCAM = 0x507f, |
e126ba97 EC |
130 | MLX5_REG_NODE_DESC = 0x6001, |
131 | MLX5_REG_HOST_ENDIANNESS = 0x7004, | |
bb64143e | 132 | MLX5_REG_MCIA = 0x9014, |
da54d24e | 133 | MLX5_REG_MLCR = 0x902b, |
eff8ea8f FD |
134 | MLX5_REG_MTRC_CAP = 0x9040, |
135 | MLX5_REG_MTRC_CONF = 0x9041, | |
136 | MLX5_REG_MTRC_STDB = 0x9042, | |
137 | MLX5_REG_MTRC_CTRL = 0x9043, | |
4039049b | 138 | MLX5_REG_MPEIN = 0x9050, |
8ed1a630 | 139 | MLX5_REG_MPCNT = 0x9051, |
f9a1ef72 EE |
140 | MLX5_REG_MTPPS = 0x9053, |
141 | MLX5_REG_MTPPSE = 0x9054, | |
5e022dd3 | 142 | MLX5_REG_MPEGC = 0x9056, |
a82e0b5b | 143 | MLX5_REG_MCQS = 0x9060, |
47176289 OG |
144 | MLX5_REG_MCQI = 0x9061, |
145 | MLX5_REG_MCC = 0x9062, | |
146 | MLX5_REG_MCDA = 0x9063, | |
cfdcbcea | 147 | MLX5_REG_MCAM = 0x907f, |
e126ba97 EC |
148 | }; |
149 | ||
415a64aa HN |
150 | enum mlx5_qpts_trust_state { |
151 | MLX5_QPTS_TRUST_PCP = 1, | |
152 | MLX5_QPTS_TRUST_DSCP = 2, | |
153 | }; | |
154 | ||
341c5ee2 HN |
155 | enum mlx5_dcbx_oper_mode { |
156 | MLX5E_DCBX_PARAM_VER_OPER_HOST = 0x0, | |
157 | MLX5E_DCBX_PARAM_VER_OPER_AUTO = 0x3, | |
158 | }; | |
159 | ||
da7525d2 EBE |
160 | enum { |
161 | MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0, | |
162 | MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1, | |
a60109dc YC |
163 | MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP = 1 << 2, |
164 | MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD = 1 << 3, | |
da7525d2 EBE |
165 | }; |
166 | ||
e420f0c0 HE |
167 | enum mlx5_page_fault_resume_flags { |
168 | MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0, | |
169 | MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1, | |
170 | MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2, | |
171 | MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7, | |
172 | }; | |
173 | ||
e126ba97 EC |
174 | enum dbg_rsc_type { |
175 | MLX5_DBG_RSC_QP, | |
176 | MLX5_DBG_RSC_EQ, | |
177 | MLX5_DBG_RSC_CQ, | |
178 | }; | |
179 | ||
7ecf6d8f BW |
180 | enum port_state_policy { |
181 | MLX5_POLICY_DOWN = 0, | |
182 | MLX5_POLICY_UP = 1, | |
183 | MLX5_POLICY_FOLLOW = 2, | |
184 | MLX5_POLICY_INVALID = 0xffffffff | |
185 | }; | |
186 | ||
386e75af HN |
187 | enum mlx5_coredev_type { |
188 | MLX5_COREDEV_PF, | |
189 | MLX5_COREDEV_VF | |
190 | }; | |
191 | ||
e126ba97 | 192 | struct mlx5_field_desc { |
e126ba97 EC |
193 | int i; |
194 | }; | |
195 | ||
196 | struct mlx5_rsc_debug { | |
197 | struct mlx5_core_dev *dev; | |
198 | void *object; | |
199 | enum dbg_rsc_type type; | |
200 | struct dentry *root; | |
201 | struct mlx5_field_desc fields[0]; | |
202 | }; | |
203 | ||
204 | enum mlx5_dev_event { | |
58d180b3 | 205 | MLX5_DEV_EVENT_SYS_ERROR = 128, /* 0 - 127 are FW events */ |
6997b1c9 | 206 | MLX5_DEV_EVENT_PORT_AFFINITY = 129, |
e126ba97 EC |
207 | }; |
208 | ||
4c916a79 | 209 | enum mlx5_port_status { |
6fa1bcab AS |
210 | MLX5_PORT_UP = 1, |
211 | MLX5_PORT_DOWN = 2, | |
4c916a79 RS |
212 | }; |
213 | ||
2f5ff264 | 214 | struct mlx5_bfreg_info { |
b037c29a | 215 | u32 *sys_pages; |
2f5ff264 | 216 | int num_low_latency_bfregs; |
e126ba97 | 217 | unsigned int *count; |
e126ba97 EC |
218 | |
219 | /* | |
2f5ff264 | 220 | * protect bfreg allocation data structs |
e126ba97 EC |
221 | */ |
222 | struct mutex lock; | |
78c0f98c | 223 | u32 ver; |
b037c29a EC |
224 | bool lib_uar_4k; |
225 | u32 num_sys_pages; | |
31a78a5a YH |
226 | u32 num_static_sys_pages; |
227 | u32 total_num_bfregs; | |
228 | u32 num_dyn_bfregs; | |
e126ba97 EC |
229 | }; |
230 | ||
231 | struct mlx5_cmd_first { | |
232 | __be32 data[4]; | |
233 | }; | |
234 | ||
235 | struct mlx5_cmd_msg { | |
236 | struct list_head list; | |
0ac3ea70 | 237 | struct cmd_msg_cache *parent; |
e126ba97 EC |
238 | u32 len; |
239 | struct mlx5_cmd_first first; | |
240 | struct mlx5_cmd_mailbox *next; | |
241 | }; | |
242 | ||
243 | struct mlx5_cmd_debug { | |
244 | struct dentry *dbg_root; | |
e126ba97 EC |
245 | void *in_msg; |
246 | void *out_msg; | |
247 | u8 status; | |
248 | u16 inlen; | |
249 | u16 outlen; | |
250 | }; | |
251 | ||
0ac3ea70 | 252 | struct cmd_msg_cache { |
e126ba97 EC |
253 | /* protect block chain allocations |
254 | */ | |
255 | spinlock_t lock; | |
256 | struct list_head head; | |
0ac3ea70 MHY |
257 | unsigned int max_inbox_size; |
258 | unsigned int num_ent; | |
e126ba97 EC |
259 | }; |
260 | ||
0ac3ea70 MHY |
261 | enum { |
262 | MLX5_NUM_COMMAND_CACHES = 5, | |
e126ba97 EC |
263 | }; |
264 | ||
265 | struct mlx5_cmd_stats { | |
266 | u64 sum; | |
267 | u64 n; | |
268 | struct dentry *root; | |
e126ba97 EC |
269 | /* protect command average calculations */ |
270 | spinlock_t lock; | |
271 | }; | |
272 | ||
273 | struct mlx5_cmd { | |
71edc69c SM |
274 | struct mlx5_nb nb; |
275 | ||
64599cca EC |
276 | void *cmd_alloc_buf; |
277 | dma_addr_t alloc_dma; | |
278 | int alloc_size; | |
e126ba97 EC |
279 | void *cmd_buf; |
280 | dma_addr_t dma; | |
281 | u16 cmdif_rev; | |
282 | u8 log_sz; | |
283 | u8 log_stride; | |
284 | int max_reg_cmds; | |
285 | int events; | |
286 | u32 __iomem *vector; | |
287 | ||
288 | /* protect command queue allocations | |
289 | */ | |
290 | spinlock_t alloc_lock; | |
291 | ||
292 | /* protect token allocations | |
293 | */ | |
294 | spinlock_t token_lock; | |
295 | u8 token; | |
296 | unsigned long bitmask; | |
297 | char wq_name[MLX5_CMD_WQ_MAX_NAME]; | |
298 | struct workqueue_struct *wq; | |
299 | struct semaphore sem; | |
300 | struct semaphore pages_sem; | |
301 | int mode; | |
302 | struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS]; | |
18c90df9 | 303 | struct dma_pool *pool; |
e126ba97 | 304 | struct mlx5_cmd_debug dbg; |
0ac3ea70 | 305 | struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES]; |
e126ba97 EC |
306 | int checksum_disabled; |
307 | struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX]; | |
308 | }; | |
309 | ||
310 | struct mlx5_port_caps { | |
311 | int gid_table_len; | |
312 | int pkey_table_len; | |
938fe83c | 313 | u8 ext_port_cap; |
c43f1112 | 314 | bool has_smi; |
e126ba97 EC |
315 | }; |
316 | ||
317 | struct mlx5_cmd_mailbox { | |
318 | void *buf; | |
319 | dma_addr_t dma; | |
320 | struct mlx5_cmd_mailbox *next; | |
321 | }; | |
322 | ||
323 | struct mlx5_buf_list { | |
324 | void *buf; | |
325 | dma_addr_t map; | |
326 | }; | |
327 | ||
1c1b5228 TT |
328 | struct mlx5_frag_buf { |
329 | struct mlx5_buf_list *frags; | |
330 | int npages; | |
331 | int size; | |
332 | u8 page_shift; | |
333 | }; | |
334 | ||
388ca8be | 335 | struct mlx5_frag_buf_ctrl { |
4972e6fa | 336 | struct mlx5_buf_list *frags; |
388ca8be | 337 | u32 sz_m1; |
8d71e818 | 338 | u16 frag_sz_m1; |
a0903622 | 339 | u16 strides_offset; |
388ca8be YC |
340 | u8 log_sz; |
341 | u8 log_stride; | |
342 | u8 log_frag_strides; | |
343 | }; | |
344 | ||
3121e3c4 SG |
345 | struct mlx5_core_psv { |
346 | u32 psv_idx; | |
347 | struct psv_layout { | |
348 | u32 pd; | |
349 | u16 syndrome; | |
350 | u16 reserved; | |
351 | u16 bg; | |
352 | u16 app_tag; | |
353 | u32 ref_tag; | |
354 | } psv; | |
355 | }; | |
356 | ||
357 | struct mlx5_core_sig_ctx { | |
358 | struct mlx5_core_psv psv_memory; | |
359 | struct mlx5_core_psv psv_wire; | |
d5436ba0 SG |
360 | struct ib_sig_err err_item; |
361 | bool sig_status_checked; | |
362 | bool sig_err_exists; | |
363 | u32 sigerr_count; | |
3121e3c4 | 364 | }; |
e126ba97 | 365 | |
aa8e08d2 AK |
366 | enum { |
367 | MLX5_MKEY_MR = 1, | |
368 | MLX5_MKEY_MW, | |
534fd7aa | 369 | MLX5_MKEY_INDIRECT_DEVX, |
aa8e08d2 AK |
370 | }; |
371 | ||
a606b0f6 | 372 | struct mlx5_core_mkey { |
e126ba97 EC |
373 | u64 iova; |
374 | u64 size; | |
375 | u32 key; | |
376 | u32 pd; | |
aa8e08d2 | 377 | u32 type; |
e126ba97 EC |
378 | }; |
379 | ||
d9aaed83 AK |
380 | #define MLX5_24BIT_MASK ((1 << 24) - 1) |
381 | ||
5903325a | 382 | enum mlx5_res_type { |
e2013b21 | 383 | MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP, |
384 | MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ, | |
385 | MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ, | |
386 | MLX5_RES_SRQ = 3, | |
387 | MLX5_RES_XSRQ = 4, | |
5b3ec3fc | 388 | MLX5_RES_XRQ = 5, |
57cda166 | 389 | MLX5_RES_DCT = MLX5_EVENT_QUEUE_TYPE_DCT, |
5903325a EC |
390 | }; |
391 | ||
392 | struct mlx5_core_rsc_common { | |
393 | enum mlx5_res_type res; | |
94f3e14e | 394 | refcount_t refcount; |
5903325a EC |
395 | struct completion free; |
396 | }; | |
397 | ||
a6d51b68 | 398 | struct mlx5_uars_page { |
e126ba97 | 399 | void __iomem *map; |
a6d51b68 EC |
400 | bool wc; |
401 | u32 index; | |
402 | struct list_head list; | |
403 | unsigned int bfregs; | |
404 | unsigned long *reg_bitmap; /* for non fast path bf regs */ | |
405 | unsigned long *fp_bitmap; | |
406 | unsigned int reg_avail; | |
407 | unsigned int fp_avail; | |
408 | struct kref ref_count; | |
409 | struct mlx5_core_dev *mdev; | |
e126ba97 EC |
410 | }; |
411 | ||
a6d51b68 EC |
412 | struct mlx5_bfreg_head { |
413 | /* protect blue flame registers allocations */ | |
414 | struct mutex lock; | |
415 | struct list_head list; | |
416 | }; | |
417 | ||
418 | struct mlx5_bfreg_data { | |
419 | struct mlx5_bfreg_head reg_head; | |
420 | struct mlx5_bfreg_head wc_head; | |
421 | }; | |
422 | ||
423 | struct mlx5_sq_bfreg { | |
424 | void __iomem *map; | |
425 | struct mlx5_uars_page *up; | |
426 | bool wc; | |
427 | u32 index; | |
428 | unsigned int offset; | |
429 | }; | |
e126ba97 EC |
430 | |
431 | struct mlx5_core_health { | |
432 | struct health_buffer __iomem *health; | |
433 | __be32 __iomem *health_counter; | |
434 | struct timer_list timer; | |
e126ba97 EC |
435 | u32 prev; |
436 | int miss_counter; | |
d1bf0e2c | 437 | u8 synd; |
63cbc552 | 438 | u32 fatal_error; |
8b9d8baa | 439 | u32 crdump_size; |
05ac2c0b MHY |
440 | /* wq spinlock to synchronize draining */ |
441 | spinlock_t wq_lock; | |
ac6ea6e8 | 442 | struct workqueue_struct *wq; |
05ac2c0b | 443 | unsigned long flags; |
b3bd076f | 444 | struct work_struct fatal_report_work; |
d1bf0e2c | 445 | struct work_struct report_work; |
04c0c1ab | 446 | struct delayed_work recover_work; |
1e34f3ef | 447 | struct devlink_health_reporter *fw_reporter; |
96c82cdf | 448 | struct devlink_health_reporter *fw_fatal_reporter; |
e126ba97 EC |
449 | }; |
450 | ||
e126ba97 | 451 | struct mlx5_qp_table { |
451be51c | 452 | struct notifier_block nb; |
221c14f3 | 453 | |
e126ba97 EC |
454 | /* protect radix tree |
455 | */ | |
456 | spinlock_t lock; | |
457 | struct radix_tree_root tree; | |
458 | }; | |
459 | ||
fc50db98 EC |
460 | struct mlx5_vf_context { |
461 | int enabled; | |
7ecf6d8f BW |
462 | u64 port_guid; |
463 | u64 node_guid; | |
464 | enum port_state_policy policy; | |
fc50db98 EC |
465 | }; |
466 | ||
467 | struct mlx5_core_sriov { | |
468 | struct mlx5_vf_context *vfs_ctx; | |
469 | int num_vfs; | |
86eec50b | 470 | u16 max_vfs; |
fc50db98 EC |
471 | }; |
472 | ||
558101f1 GT |
473 | struct mlx5_fc_pool { |
474 | struct mlx5_core_dev *dev; | |
475 | struct mutex pool_lock; /* protects pool lists */ | |
476 | struct list_head fully_used; | |
477 | struct list_head partially_used; | |
478 | struct list_head unused; | |
479 | int available_fcs; | |
480 | int used_fcs; | |
481 | int threshold; | |
482 | }; | |
483 | ||
43a335e0 | 484 | struct mlx5_fc_stats { |
12d6066c VB |
485 | spinlock_t counters_idr_lock; /* protects counters_idr */ |
486 | struct idr counters_idr; | |
9aff93d7 | 487 | struct list_head counters; |
83033688 | 488 | struct llist_head addlist; |
6e5e2283 | 489 | struct llist_head dellist; |
43a335e0 AV |
490 | |
491 | struct workqueue_struct *wq; | |
492 | struct delayed_work work; | |
493 | unsigned long next_query; | |
f6dfb4c3 | 494 | unsigned long sampling_interval; /* jiffies */ |
6f06e04b | 495 | u32 *bulk_query_out; |
558101f1 | 496 | struct mlx5_fc_pool fc_pool; |
43a335e0 AV |
497 | }; |
498 | ||
69c1280b | 499 | struct mlx5_events; |
eeb66cdb | 500 | struct mlx5_mpfs; |
073bb189 | 501 | struct mlx5_eswitch; |
7907f23a | 502 | struct mlx5_lag; |
fadd59fc | 503 | struct mlx5_devcom; |
f2f3df55 | 504 | struct mlx5_eq_table; |
561aa15a | 505 | struct mlx5_irq_table; |
073bb189 | 506 | |
05d3ac97 BW |
507 | struct mlx5_rate_limit { |
508 | u32 rate; | |
509 | u32 max_burst_sz; | |
510 | u16 typical_pkt_sz; | |
511 | }; | |
512 | ||
1466cc5b | 513 | struct mlx5_rl_entry { |
05d3ac97 | 514 | struct mlx5_rate_limit rl; |
1466cc5b YP |
515 | u16 index; |
516 | u16 refcount; | |
517 | }; | |
518 | ||
519 | struct mlx5_rl_table { | |
520 | /* protect rate limit table */ | |
521 | struct mutex rl_lock; | |
522 | u16 max_size; | |
523 | u32 max_rate; | |
524 | u32 min_rate; | |
525 | struct mlx5_rl_entry *rl_entry; | |
526 | }; | |
527 | ||
80f09dfc MG |
528 | struct mlx5_core_roce { |
529 | struct mlx5_flow_table *ft; | |
530 | struct mlx5_flow_group *fg; | |
531 | struct mlx5_flow_handle *allow_rule; | |
532 | }; | |
533 | ||
e126ba97 | 534 | struct mlx5_priv { |
561aa15a YA |
535 | /* IRQ table valid only for real pci devices PF or VF */ |
536 | struct mlx5_irq_table *irq_table; | |
f2f3df55 | 537 | struct mlx5_eq_table *eq_table; |
e126ba97 EC |
538 | |
539 | /* pages stuff */ | |
0cf53c12 | 540 | struct mlx5_nb pg_nb; |
e126ba97 EC |
541 | struct workqueue_struct *pg_wq; |
542 | struct rb_root page_root; | |
543 | int fw_pages; | |
6aec21f6 | 544 | atomic_t reg_pages; |
bf0bf77f | 545 | struct list_head free_list; |
fc50db98 | 546 | int vfs_pages; |
591905ba | 547 | int peer_pf_pages; |
e126ba97 EC |
548 | |
549 | struct mlx5_core_health health; | |
550 | ||
e126ba97 EC |
551 | /* start: qp staff */ |
552 | struct mlx5_qp_table qp_table; | |
553 | struct dentry *qp_debugfs; | |
554 | struct dentry *eq_debugfs; | |
555 | struct dentry *cq_debugfs; | |
556 | struct dentry *cmdif_debugfs; | |
557 | /* end: qp staff */ | |
558 | ||
792c4e9d | 559 | struct xarray mkey_table; |
3bcdb17a | 560 | |
e126ba97 | 561 | /* start: alloc staff */ |
311c7c71 SM |
562 | /* protect buffer alocation according to numa node */ |
563 | struct mutex alloc_mutex; | |
564 | int numa_node; | |
565 | ||
e126ba97 EC |
566 | struct mutex pgdir_mutex; |
567 | struct list_head pgdir_list; | |
568 | /* end: alloc staff */ | |
569 | struct dentry *dbg_root; | |
570 | ||
571 | /* protect mkey key part */ | |
572 | spinlock_t mkey_lock; | |
573 | u8 mkey_key; | |
9603b61d JM |
574 | |
575 | struct list_head dev_list; | |
576 | struct list_head ctx_list; | |
577 | spinlock_t ctx_lock; | |
02039fb6 | 578 | struct mlx5_events *events; |
97834eba | 579 | |
fba53f7b | 580 | struct mlx5_flow_steering *steering; |
eeb66cdb | 581 | struct mlx5_mpfs *mpfs; |
073bb189 | 582 | struct mlx5_eswitch *eswitch; |
fc50db98 | 583 | struct mlx5_core_sriov sriov; |
7907f23a | 584 | struct mlx5_lag *lag; |
fadd59fc | 585 | struct mlx5_devcom *devcom; |
80f09dfc | 586 | struct mlx5_core_roce roce; |
43a335e0 | 587 | struct mlx5_fc_stats fc_stats; |
1466cc5b | 588 | struct mlx5_rl_table rl_table; |
d4eb4cd7 | 589 | |
a6d51b68 | 590 | struct mlx5_bfreg_data bfregs; |
01187175 | 591 | struct mlx5_uars_page *uar; |
e126ba97 EC |
592 | }; |
593 | ||
89d44f0a | 594 | enum mlx5_device_state { |
3e5b72ac | 595 | MLX5_DEVICE_STATE_UNINITIALIZED, |
89d44f0a MD |
596 | MLX5_DEVICE_STATE_UP, |
597 | MLX5_DEVICE_STATE_INTERNAL_ERROR, | |
598 | }; | |
599 | ||
600 | enum mlx5_interface_state { | |
b3cb5388 | 601 | MLX5_INTERFACE_STATE_UP = BIT(0), |
89d44f0a MD |
602 | }; |
603 | ||
604 | enum mlx5_pci_status { | |
605 | MLX5_PCI_STATUS_DISABLED, | |
606 | MLX5_PCI_STATUS_ENABLED, | |
607 | }; | |
608 | ||
d9aaed83 AK |
609 | enum mlx5_pagefault_type_flags { |
610 | MLX5_PFAULT_REQUESTOR = 1 << 0, | |
611 | MLX5_PFAULT_WRITE = 1 << 1, | |
612 | MLX5_PFAULT_RDMA = 1 << 2, | |
613 | }; | |
614 | ||
b50d292b | 615 | struct mlx5_td { |
80a2a902 YA |
616 | /* protects tirs list changes while tirs refresh */ |
617 | struct mutex list_lock; | |
b50d292b HHZ |
618 | struct list_head tirs_list; |
619 | u32 tdn; | |
620 | }; | |
621 | ||
622 | struct mlx5e_resources { | |
b50d292b HHZ |
623 | u32 pdn; |
624 | struct mlx5_td td; | |
625 | struct mlx5_core_mkey mkey; | |
aff26157 | 626 | struct mlx5_sq_bfreg bfreg; |
b50d292b HHZ |
627 | }; |
628 | ||
c9b9dcb4 AL |
629 | enum mlx5_sw_icm_type { |
630 | MLX5_SW_ICM_TYPE_STEERING, | |
631 | MLX5_SW_ICM_TYPE_HEADER_MODIFY, | |
632 | }; | |
633 | ||
52ec462e IT |
634 | #define MLX5_MAX_RESERVED_GIDS 8 |
635 | ||
636 | struct mlx5_rsvd_gids { | |
637 | unsigned int start; | |
638 | unsigned int count; | |
639 | struct ida ida; | |
640 | }; | |
641 | ||
7c39afb3 FD |
642 | #define MAX_PIN_NUM 8 |
643 | struct mlx5_pps { | |
644 | u8 pin_caps[MAX_PIN_NUM]; | |
645 | struct work_struct out_work; | |
646 | u64 start[MAX_PIN_NUM]; | |
647 | u8 enabled; | |
648 | }; | |
649 | ||
650 | struct mlx5_clock { | |
41069256 SM |
651 | struct mlx5_core_dev *mdev; |
652 | struct mlx5_nb pps_nb; | |
64109f1d | 653 | seqlock_t lock; |
7c39afb3 FD |
654 | struct cyclecounter cycles; |
655 | struct timecounter tc; | |
656 | struct hwtstamp_config hwtstamp_config; | |
657 | u32 nominal_c_mult; | |
658 | unsigned long overflow_period; | |
659 | struct delayed_work overflow_work; | |
660 | struct ptp_clock *ptp; | |
661 | struct ptp_clock_info ptp_info; | |
662 | struct mlx5_pps pps_info; | |
663 | }; | |
664 | ||
c9b9dcb4 | 665 | struct mlx5_dm; |
f53aaa31 | 666 | struct mlx5_fw_tracer; |
358aa5ce | 667 | struct mlx5_vxlan; |
0ccc171e | 668 | struct mlx5_geneve; |
87175120 | 669 | struct mlx5_hv_vhca; |
f53aaa31 | 670 | |
c9b9dcb4 AL |
671 | #define MLX5_LOG_SW_ICM_BLOCK_SIZE(dev) (MLX5_CAP_DEV_MEM(dev, log_sw_icm_alloc_granularity)) |
672 | #define MLX5_SW_ICM_BLOCK_SIZE(dev) (1 << MLX5_LOG_SW_ICM_BLOCK_SIZE(dev)) | |
673 | ||
e126ba97 | 674 | struct mlx5_core_dev { |
27b942fb | 675 | struct device *device; |
386e75af | 676 | enum mlx5_coredev_type coredev_type; |
e126ba97 | 677 | struct pci_dev *pdev; |
89d44f0a MD |
678 | /* sync pci state */ |
679 | struct mutex pci_status_mutex; | |
680 | enum mlx5_pci_status pci_status; | |
e126ba97 EC |
681 | u8 rev_id; |
682 | char board_id[MLX5_BOARD_ID_LEN]; | |
683 | struct mlx5_cmd cmd; | |
938fe83c | 684 | struct mlx5_port_caps port_caps[MLX5_MAX_PORTS]; |
71862561 | 685 | struct { |
701052c5 GP |
686 | u32 hca_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; |
687 | u32 hca_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; | |
71862561 GP |
688 | u32 pcam[MLX5_ST_SZ_DW(pcam_reg)]; |
689 | u32 mcam[MLX5_ST_SZ_DW(mcam_reg)]; | |
99d3cd27 | 690 | u32 fpga[MLX5_ST_SZ_DW(fpga_cap)]; |
c02762eb | 691 | u32 qcam[MLX5_ST_SZ_DW(qcam_reg)]; |
591905ba | 692 | u8 embedded_cpu; |
71862561 | 693 | } caps; |
59c9d35e | 694 | u64 sys_image_guid; |
e126ba97 EC |
695 | phys_addr_t iseg_base; |
696 | struct mlx5_init_seg __iomem *iseg; | |
aa8106f1 | 697 | phys_addr_t bar_addr; |
89d44f0a MD |
698 | enum mlx5_device_state state; |
699 | /* sync interface state */ | |
700 | struct mutex intf_state_mutex; | |
5fc7197d | 701 | unsigned long intf_state; |
e126ba97 EC |
702 | struct mlx5_priv priv; |
703 | struct mlx5_profile *profile; | |
704 | atomic_t num_qps; | |
f62b8bb8 | 705 | u32 issi; |
b50d292b | 706 | struct mlx5e_resources mlx5e_res; |
c9b9dcb4 | 707 | struct mlx5_dm *dm; |
358aa5ce | 708 | struct mlx5_vxlan *vxlan; |
0ccc171e | 709 | struct mlx5_geneve *geneve; |
52ec462e IT |
710 | struct { |
711 | struct mlx5_rsvd_gids reserved_gids; | |
734dc065 | 712 | u32 roce_en; |
52ec462e | 713 | } roce; |
e29341fb IT |
714 | #ifdef CONFIG_MLX5_FPGA |
715 | struct mlx5_fpga_device *fpga; | |
5a7b27eb | 716 | #endif |
7c39afb3 | 717 | struct mlx5_clock clock; |
24d33d2c | 718 | struct mlx5_ib_clock_info *clock_info; |
f53aaa31 | 719 | struct mlx5_fw_tracer *tracer; |
b25bbc2f | 720 | u32 vsc_addr; |
87175120 | 721 | struct mlx5_hv_vhca *hv_vhca; |
e126ba97 EC |
722 | }; |
723 | ||
724 | struct mlx5_db { | |
725 | __be32 *db; | |
726 | union { | |
727 | struct mlx5_db_pgdir *pgdir; | |
728 | struct mlx5_ib_user_db_page *user_page; | |
729 | } u; | |
730 | dma_addr_t dma; | |
731 | int index; | |
732 | }; | |
733 | ||
e126ba97 EC |
734 | enum { |
735 | MLX5_COMP_EQ_SIZE = 1024, | |
736 | }; | |
737 | ||
adb0c954 SM |
738 | enum { |
739 | MLX5_PTYS_IB = 1 << 0, | |
740 | MLX5_PTYS_EN = 1 << 2, | |
741 | }; | |
742 | ||
e126ba97 EC |
743 | typedef void (*mlx5_cmd_cbk_t)(int status, void *context); |
744 | ||
73dd3a48 MHY |
745 | enum { |
746 | MLX5_CMD_ENT_STATE_PENDING_COMP, | |
747 | }; | |
748 | ||
e126ba97 | 749 | struct mlx5_cmd_work_ent { |
73dd3a48 | 750 | unsigned long state; |
e126ba97 EC |
751 | struct mlx5_cmd_msg *in; |
752 | struct mlx5_cmd_msg *out; | |
746b5583 EC |
753 | void *uout; |
754 | int uout_size; | |
e126ba97 | 755 | mlx5_cmd_cbk_t callback; |
65ee6708 | 756 | struct delayed_work cb_timeout_work; |
e126ba97 | 757 | void *context; |
746b5583 | 758 | int idx; |
06a8dc40 | 759 | struct completion handling; |
e126ba97 EC |
760 | struct completion done; |
761 | struct mlx5_cmd *cmd; | |
762 | struct work_struct work; | |
763 | struct mlx5_cmd_layout *lay; | |
764 | int ret; | |
765 | int page_queue; | |
766 | u8 status; | |
767 | u8 token; | |
14a70046 TG |
768 | u64 ts1; |
769 | u64 ts2; | |
746b5583 | 770 | u16 op; |
4525abea | 771 | bool polling; |
e126ba97 EC |
772 | }; |
773 | ||
774 | struct mlx5_pas { | |
775 | u64 pa; | |
776 | u8 log_sz; | |
777 | }; | |
778 | ||
707c4602 MD |
779 | enum phy_port_state { |
780 | MLX5_AAA_111 | |
781 | }; | |
782 | ||
783 | struct mlx5_hca_vport_context { | |
784 | u32 field_select; | |
785 | bool sm_virt_aware; | |
786 | bool has_smi; | |
787 | bool has_raw; | |
788 | enum port_state_policy policy; | |
789 | enum phy_port_state phys_state; | |
790 | enum ib_port_state vport_state; | |
791 | u8 port_physical_state; | |
792 | u64 sys_image_guid; | |
793 | u64 port_guid; | |
794 | u64 node_guid; | |
795 | u32 cap_mask1; | |
796 | u32 cap_mask1_perm; | |
4106a758 MG |
797 | u16 cap_mask2; |
798 | u16 cap_mask2_perm; | |
707c4602 MD |
799 | u16 lid; |
800 | u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */ | |
801 | u8 lmc; | |
802 | u8 subnet_timeout; | |
803 | u16 sm_lid; | |
804 | u8 sm_sl; | |
805 | u16 qkey_violation_counter; | |
806 | u16 pkey_violation_counter; | |
807 | bool grh_required; | |
808 | }; | |
809 | ||
388ca8be | 810 | static inline void *mlx5_buf_offset(struct mlx5_frag_buf *buf, int offset) |
e126ba97 | 811 | { |
388ca8be | 812 | return buf->frags->buf + offset; |
e126ba97 EC |
813 | } |
814 | ||
e126ba97 EC |
815 | #define STRUCT_FIELD(header, field) \ |
816 | .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \ | |
817 | .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field | |
818 | ||
e126ba97 EC |
819 | static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev) |
820 | { | |
821 | return pci_get_drvdata(pdev); | |
822 | } | |
823 | ||
824 | extern struct dentry *mlx5_debugfs_root; | |
825 | ||
826 | static inline u16 fw_rev_maj(struct mlx5_core_dev *dev) | |
827 | { | |
828 | return ioread32be(&dev->iseg->fw_rev) & 0xffff; | |
829 | } | |
830 | ||
831 | static inline u16 fw_rev_min(struct mlx5_core_dev *dev) | |
832 | { | |
833 | return ioread32be(&dev->iseg->fw_rev) >> 16; | |
834 | } | |
835 | ||
836 | static inline u16 fw_rev_sub(struct mlx5_core_dev *dev) | |
837 | { | |
838 | return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff; | |
839 | } | |
840 | ||
841 | static inline u16 cmdif_rev(struct mlx5_core_dev *dev) | |
842 | { | |
843 | return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16; | |
844 | } | |
845 | ||
3bcdb17a SG |
846 | static inline u32 mlx5_base_mkey(const u32 key) |
847 | { | |
848 | return key & 0xffffff00u; | |
849 | } | |
850 | ||
4972e6fa TT |
851 | static inline void mlx5_init_fbc_offset(struct mlx5_buf_list *frags, |
852 | u8 log_stride, u8 log_sz, | |
a0903622 | 853 | u16 strides_offset, |
d7037ad7 | 854 | struct mlx5_frag_buf_ctrl *fbc) |
388ca8be | 855 | { |
4972e6fa | 856 | fbc->frags = frags; |
3a2f7033 TT |
857 | fbc->log_stride = log_stride; |
858 | fbc->log_sz = log_sz; | |
388ca8be YC |
859 | fbc->sz_m1 = (1 << fbc->log_sz) - 1; |
860 | fbc->log_frag_strides = PAGE_SHIFT - fbc->log_stride; | |
861 | fbc->frag_sz_m1 = (1 << fbc->log_frag_strides) - 1; | |
d7037ad7 TT |
862 | fbc->strides_offset = strides_offset; |
863 | } | |
864 | ||
4972e6fa TT |
865 | static inline void mlx5_init_fbc(struct mlx5_buf_list *frags, |
866 | u8 log_stride, u8 log_sz, | |
d7037ad7 TT |
867 | struct mlx5_frag_buf_ctrl *fbc) |
868 | { | |
4972e6fa | 869 | mlx5_init_fbc_offset(frags, log_stride, log_sz, 0, fbc); |
3a2f7033 TT |
870 | } |
871 | ||
388ca8be YC |
872 | static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl *fbc, |
873 | u32 ix) | |
874 | { | |
d7037ad7 TT |
875 | unsigned int frag; |
876 | ||
877 | ix += fbc->strides_offset; | |
878 | frag = ix >> fbc->log_frag_strides; | |
388ca8be | 879 | |
4972e6fa | 880 | return fbc->frags[frag].buf + ((fbc->frag_sz_m1 & ix) << fbc->log_stride); |
388ca8be YC |
881 | } |
882 | ||
37fdffb2 TT |
883 | static inline u32 |
884 | mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl *fbc, u32 ix) | |
885 | { | |
886 | u32 last_frag_stride_idx = (ix + fbc->strides_offset) | fbc->frag_sz_m1; | |
887 | ||
888 | return min_t(u32, last_frag_stride_idx - fbc->strides_offset, fbc->sz_m1); | |
889 | } | |
890 | ||
e126ba97 EC |
891 | int mlx5_cmd_init(struct mlx5_core_dev *dev); |
892 | void mlx5_cmd_cleanup(struct mlx5_core_dev *dev); | |
893 | void mlx5_cmd_use_events(struct mlx5_core_dev *dev); | |
894 | void mlx5_cmd_use_polling(struct mlx5_core_dev *dev); | |
c4f287c4 | 895 | |
e355477e JG |
896 | struct mlx5_async_ctx { |
897 | struct mlx5_core_dev *dev; | |
898 | atomic_t num_inflight; | |
899 | struct wait_queue_head wait; | |
900 | }; | |
901 | ||
902 | struct mlx5_async_work; | |
903 | ||
904 | typedef void (*mlx5_async_cbk_t)(int status, struct mlx5_async_work *context); | |
905 | ||
906 | struct mlx5_async_work { | |
907 | struct mlx5_async_ctx *ctx; | |
908 | mlx5_async_cbk_t user_callback; | |
909 | }; | |
910 | ||
911 | void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev, | |
912 | struct mlx5_async_ctx *ctx); | |
913 | void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx); | |
914 | int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size, | |
915 | void *out, int out_size, mlx5_async_cbk_t callback, | |
916 | struct mlx5_async_work *work); | |
917 | ||
e126ba97 EC |
918 | int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out, |
919 | int out_size); | |
4525abea MD |
920 | int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size, |
921 | void *out, int out_size); | |
c4f287c4 SM |
922 | void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome); |
923 | ||
924 | int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type); | |
e126ba97 EC |
925 | int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn); |
926 | int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn); | |
52c368dc | 927 | void mlx5_health_flush(struct mlx5_core_dev *dev); |
ac6ea6e8 EC |
928 | void mlx5_health_cleanup(struct mlx5_core_dev *dev); |
929 | int mlx5_health_init(struct mlx5_core_dev *dev); | |
e126ba97 | 930 | void mlx5_start_health_poll(struct mlx5_core_dev *dev); |
76d5581c | 931 | void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health); |
05ac2c0b | 932 | void mlx5_drain_health_wq(struct mlx5_core_dev *dev); |
0179720d | 933 | void mlx5_trigger_health_work(struct mlx5_core_dev *dev); |
311c7c71 | 934 | int mlx5_buf_alloc_node(struct mlx5_core_dev *dev, int size, |
388ca8be YC |
935 | struct mlx5_frag_buf *buf, int node); |
936 | int mlx5_buf_alloc(struct mlx5_core_dev *dev, | |
937 | int size, struct mlx5_frag_buf *buf); | |
938 | void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf); | |
1c1b5228 TT |
939 | int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size, |
940 | struct mlx5_frag_buf *buf, int node); | |
941 | void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf); | |
e126ba97 EC |
942 | struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev, |
943 | gfp_t flags, int npages); | |
944 | void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev, | |
945 | struct mlx5_cmd_mailbox *head); | |
a606b0f6 MB |
946 | void mlx5_init_mkey_table(struct mlx5_core_dev *dev); |
947 | void mlx5_cleanup_mkey_table(struct mlx5_core_dev *dev); | |
ec22eb53 SM |
948 | int mlx5_core_create_mkey_cb(struct mlx5_core_dev *dev, |
949 | struct mlx5_core_mkey *mkey, | |
e355477e JG |
950 | struct mlx5_async_ctx *async_ctx, u32 *in, |
951 | int inlen, u32 *out, int outlen, | |
952 | mlx5_async_cbk_t callback, | |
953 | struct mlx5_async_work *context); | |
a606b0f6 MB |
954 | int mlx5_core_create_mkey(struct mlx5_core_dev *dev, |
955 | struct mlx5_core_mkey *mkey, | |
ec22eb53 | 956 | u32 *in, int inlen); |
a606b0f6 MB |
957 | int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, |
958 | struct mlx5_core_mkey *mkey); | |
959 | int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey, | |
ec22eb53 | 960 | u32 *out, int outlen); |
e126ba97 EC |
961 | int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn); |
962 | int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn); | |
0cf53c12 | 963 | int mlx5_pagealloc_init(struct mlx5_core_dev *dev); |
e126ba97 | 964 | void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev); |
0cf53c12 | 965 | void mlx5_pagealloc_start(struct mlx5_core_dev *dev); |
e126ba97 EC |
966 | void mlx5_pagealloc_stop(struct mlx5_core_dev *dev); |
967 | void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id, | |
591905ba | 968 | s32 npages, bool ec_function); |
cd23b14b | 969 | int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot); |
e126ba97 EC |
970 | int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev); |
971 | void mlx5_register_debugfs(void); | |
972 | void mlx5_unregister_debugfs(void); | |
388ca8be YC |
973 | |
974 | void mlx5_fill_page_array(struct mlx5_frag_buf *buf, __be64 *pas); | |
1c1b5228 | 975 | void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas); |
0b6e26ce DT |
976 | int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, |
977 | unsigned int *irqn); | |
e126ba97 EC |
978 | int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); |
979 | int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); | |
980 | ||
9f818c8a | 981 | void mlx5_qp_debugfs_init(struct mlx5_core_dev *dev); |
e126ba97 EC |
982 | void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev); |
983 | int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in, | |
984 | int size_in, void *data_out, int size_out, | |
985 | u16 reg_num, int arg, int write); | |
adb0c954 | 986 | |
e126ba97 | 987 | int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db); |
311c7c71 SM |
988 | int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db, |
989 | int node); | |
e126ba97 EC |
990 | void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db); |
991 | ||
e126ba97 | 992 | const char *mlx5_command_str(int command); |
9f818c8a | 993 | void mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev); |
e126ba97 | 994 | void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev); |
3121e3c4 SG |
995 | int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn, |
996 | int npsvs, u32 *sig_index); | |
997 | int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num); | |
5903325a | 998 | void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common); |
e420f0c0 HE |
999 | int mlx5_query_odp_caps(struct mlx5_core_dev *dev, |
1000 | struct mlx5_odp_caps *odp_caps); | |
1c64bf6f MY |
1001 | int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev, |
1002 | u8 port_num, void *out, size_t sz); | |
e126ba97 | 1003 | |
1466cc5b YP |
1004 | int mlx5_init_rl_table(struct mlx5_core_dev *dev); |
1005 | void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev); | |
05d3ac97 BW |
1006 | int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index, |
1007 | struct mlx5_rate_limit *rl); | |
1008 | void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl); | |
1466cc5b | 1009 | bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate); |
05d3ac97 BW |
1010 | bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0, |
1011 | struct mlx5_rate_limit *rl_1); | |
a6d51b68 EC |
1012 | int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg, |
1013 | bool map_wc, bool fast_path); | |
1014 | void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg); | |
1466cc5b | 1015 | |
f2f3df55 SM |
1016 | unsigned int mlx5_comp_vectors_count(struct mlx5_core_dev *dev); |
1017 | struct cpumask * | |
1018 | mlx5_comp_irq_get_affinity_mask(struct mlx5_core_dev *dev, int vector); | |
52ec462e IT |
1019 | unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev); |
1020 | int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index, | |
1021 | u8 roce_version, u8 roce_l3_type, const u8 *gid, | |
cfe4e37f | 1022 | const u8 *mac, bool vlan, u16 vlan_id, u8 port_num); |
52ec462e | 1023 | |
e3297246 EC |
1024 | static inline int fw_initializing(struct mlx5_core_dev *dev) |
1025 | { | |
1026 | return ioread32be(&dev->iseg->initializing) >> 31; | |
1027 | } | |
1028 | ||
e126ba97 EC |
1029 | static inline u32 mlx5_mkey_to_idx(u32 mkey) |
1030 | { | |
1031 | return mkey >> 8; | |
1032 | } | |
1033 | ||
1034 | static inline u32 mlx5_idx_to_mkey(u32 mkey_idx) | |
1035 | { | |
1036 | return mkey_idx << 8; | |
1037 | } | |
1038 | ||
746b5583 EC |
1039 | static inline u8 mlx5_mkey_variant(u32 mkey) |
1040 | { | |
1041 | return mkey & 0xff; | |
1042 | } | |
1043 | ||
e126ba97 EC |
1044 | enum { |
1045 | MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0, | |
c1868b82 | 1046 | MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1, |
e126ba97 EC |
1047 | }; |
1048 | ||
1049 | enum { | |
8b7ff7f3 | 1050 | MR_CACHE_LAST_STD_ENTRY = 20, |
81713d37 AK |
1051 | MLX5_IMR_MTT_CACHE_ENTRY, |
1052 | MLX5_IMR_KSM_CACHE_ENTRY, | |
49780d42 | 1053 | MAX_MR_CACHE_ENTRIES |
e126ba97 EC |
1054 | }; |
1055 | ||
64613d94 SM |
1056 | enum { |
1057 | MLX5_INTERFACE_PROTOCOL_IB = 0, | |
1058 | MLX5_INTERFACE_PROTOCOL_ETH = 1, | |
1059 | }; | |
1060 | ||
9603b61d JM |
1061 | struct mlx5_interface { |
1062 | void * (*add)(struct mlx5_core_dev *dev); | |
1063 | void (*remove)(struct mlx5_core_dev *dev, void *context); | |
737a234b MHY |
1064 | int (*attach)(struct mlx5_core_dev *dev, void *context); |
1065 | void (*detach)(struct mlx5_core_dev *dev, void *context); | |
64613d94 | 1066 | int protocol; |
9603b61d JM |
1067 | struct list_head list; |
1068 | }; | |
1069 | ||
1070 | int mlx5_register_interface(struct mlx5_interface *intf); | |
1071 | void mlx5_unregister_interface(struct mlx5_interface *intf); | |
20902be4 SM |
1072 | int mlx5_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb); |
1073 | int mlx5_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb); | |
c0670781 YH |
1074 | int mlx5_eq_notifier_register(struct mlx5_core_dev *dev, struct mlx5_nb *nb); |
1075 | int mlx5_eq_notifier_unregister(struct mlx5_core_dev *dev, struct mlx5_nb *nb); | |
20902be4 | 1076 | |
211e6c80 | 1077 | int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id); |
9603b61d | 1078 | |
3bc34f3b AH |
1079 | int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev); |
1080 | int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev); | |
7c34ec19 AH |
1081 | bool mlx5_lag_is_roce(struct mlx5_core_dev *dev); |
1082 | bool mlx5_lag_is_sriov(struct mlx5_core_dev *dev); | |
724b509c | 1083 | bool mlx5_lag_is_multipath(struct mlx5_core_dev *dev); |
7907f23a | 1084 | bool mlx5_lag_is_active(struct mlx5_core_dev *dev); |
6a32047a | 1085 | struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev); |
71a0ff65 MD |
1086 | int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev, |
1087 | u64 *values, | |
1088 | int num_counters, | |
1089 | size_t *offsets); | |
01187175 EC |
1090 | struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev); |
1091 | void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up); | |
c9b9dcb4 AL |
1092 | int mlx5_dm_sw_icm_alloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type, |
1093 | u64 length, u16 uid, phys_addr_t *addr, u32 *obj_id); | |
1094 | int mlx5_dm_sw_icm_dealloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type, | |
1095 | u64 length, u16 uid, phys_addr_t addr, u32 obj_id); | |
7907f23a | 1096 | |
f6a8a19b | 1097 | #ifdef CONFIG_MLX5_CORE_IPOIB |
693dfd5a ES |
1098 | struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev, |
1099 | struct ib_device *ibdev, | |
1100 | const char *name, | |
1101 | void (*setup)(struct net_device *)); | |
693dfd5a | 1102 | #endif /* CONFIG_MLX5_CORE_IPOIB */ |
f6a8a19b DD |
1103 | int mlx5_rdma_rn_get_params(struct mlx5_core_dev *mdev, |
1104 | struct ib_device *device, | |
1105 | struct rdma_netdev_alloc_params *params); | |
693dfd5a | 1106 | |
e126ba97 EC |
1107 | struct mlx5_profile { |
1108 | u64 mask; | |
f241e749 | 1109 | u8 log_max_qp; |
e126ba97 EC |
1110 | struct { |
1111 | int size; | |
1112 | int limit; | |
1113 | } mr_cache[MAX_MR_CACHE_ENTRIES]; | |
1114 | }; | |
1115 | ||
fc50db98 EC |
1116 | enum { |
1117 | MLX5_PCI_DEV_IS_VF = 1 << 0, | |
1118 | }; | |
1119 | ||
2752b823 | 1120 | static inline bool mlx5_core_is_pf(const struct mlx5_core_dev *dev) |
fc50db98 | 1121 | { |
386e75af | 1122 | return dev->coredev_type == MLX5_COREDEV_PF; |
fc50db98 EC |
1123 | } |
1124 | ||
591905ba BW |
1125 | static inline bool mlx5_core_is_ecpf(struct mlx5_core_dev *dev) |
1126 | { | |
1127 | return dev->caps.embedded_cpu; | |
1128 | } | |
1129 | ||
2752b823 PP |
1130 | static inline bool |
1131 | mlx5_core_is_ecpf_esw_manager(const struct mlx5_core_dev *dev) | |
7f0d11c7 BW |
1132 | { |
1133 | return dev->caps.embedded_cpu && MLX5_CAP_GEN(dev, eswitch_manager); | |
1134 | } | |
1135 | ||
2752b823 | 1136 | static inline bool mlx5_ecpf_vport_exists(const struct mlx5_core_dev *dev) |
81cd229c BW |
1137 | { |
1138 | return mlx5_core_is_pf(dev) && MLX5_CAP_ESW(dev, ecpf_vport_exists); | |
1139 | } | |
1140 | ||
2752b823 | 1141 | static inline u16 mlx5_core_max_vfs(const struct mlx5_core_dev *dev) |
feb39369 | 1142 | { |
86eec50b | 1143 | return dev->priv.sriov.max_vfs; |
feb39369 BW |
1144 | } |
1145 | ||
707c4602 MD |
1146 | static inline int mlx5_get_gid_table_len(u16 param) |
1147 | { | |
1148 | if (param > 4) { | |
1149 | pr_warn("gid table length is zero\n"); | |
1150 | return 0; | |
1151 | } | |
1152 | ||
1153 | return 8 * (1 << param); | |
1154 | } | |
1155 | ||
1466cc5b YP |
1156 | static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev) |
1157 | { | |
1158 | return !!(dev->priv.rl_table.max_size); | |
1159 | } | |
1160 | ||
32f69e4b DJ |
1161 | static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev) |
1162 | { | |
1163 | return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) && | |
1164 | MLX5_CAP_GEN(dev, num_vhca_ports) <= 1; | |
1165 | } | |
1166 | ||
1167 | static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev) | |
1168 | { | |
1169 | return MLX5_CAP_GEN(dev, num_vhca_ports) > 1; | |
1170 | } | |
1171 | ||
1172 | static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev) | |
1173 | { | |
1174 | return mlx5_core_is_mp_slave(dev) || | |
1175 | mlx5_core_is_mp_master(dev); | |
1176 | } | |
1177 | ||
7fd8aefb DJ |
1178 | static inline int mlx5_core_native_port_num(struct mlx5_core_dev *dev) |
1179 | { | |
32f69e4b DJ |
1180 | if (!mlx5_core_mp_enabled(dev)) |
1181 | return 1; | |
1182 | ||
1183 | return MLX5_CAP_GEN(dev, native_port_num); | |
7fd8aefb DJ |
1184 | } |
1185 | ||
020446e0 EC |
1186 | enum { |
1187 | MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32, | |
1188 | }; | |
1189 | ||
e126ba97 | 1190 | #endif /* MLX5_DRIVER_H */ |