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e126ba97 | 1 | /* |
302bdf68 | 2 | * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. |
e126ba97 EC |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef MLX5_DRIVER_H | |
34 | #define MLX5_DRIVER_H | |
35 | ||
36 | #include <linux/kernel.h> | |
37 | #include <linux/completion.h> | |
38 | #include <linux/pci.h> | |
39 | #include <linux/spinlock_types.h> | |
40 | #include <linux/semaphore.h> | |
6ecde51d | 41 | #include <linux/slab.h> |
e126ba97 EC |
42 | #include <linux/vmalloc.h> |
43 | #include <linux/radix-tree.h> | |
6ecde51d | 44 | |
e126ba97 EC |
45 | #include <linux/mlx5/device.h> |
46 | #include <linux/mlx5/doorbell.h> | |
47 | ||
48 | enum { | |
49 | MLX5_BOARD_ID_LEN = 64, | |
50 | MLX5_MAX_NAME_LEN = 16, | |
51 | }; | |
52 | ||
53 | enum { | |
54 | /* one minute for the sake of bringup. Generally, commands must always | |
55 | * complete and we may need to increase this timeout value | |
56 | */ | |
57 | MLX5_CMD_TIMEOUT_MSEC = 7200 * 1000, | |
58 | MLX5_CMD_WQ_MAX_NAME = 32, | |
59 | }; | |
60 | ||
61 | enum { | |
62 | CMD_OWNER_SW = 0x0, | |
63 | CMD_OWNER_HW = 0x1, | |
64 | CMD_STATUS_SUCCESS = 0, | |
65 | }; | |
66 | ||
67 | enum mlx5_sqp_t { | |
68 | MLX5_SQP_SMI = 0, | |
69 | MLX5_SQP_GSI = 1, | |
70 | MLX5_SQP_IEEE_1588 = 2, | |
71 | MLX5_SQP_SNIFFER = 3, | |
72 | MLX5_SQP_SYNC_UMR = 4, | |
73 | }; | |
74 | ||
75 | enum { | |
76 | MLX5_MAX_PORTS = 2, | |
77 | }; | |
78 | ||
79 | enum { | |
80 | MLX5_EQ_VEC_PAGES = 0, | |
81 | MLX5_EQ_VEC_CMD = 1, | |
82 | MLX5_EQ_VEC_ASYNC = 2, | |
83 | MLX5_EQ_VEC_COMP_BASE, | |
84 | }; | |
85 | ||
86 | enum { | |
db058a18 | 87 | MLX5_MAX_IRQ_NAME = 32 |
e126ba97 EC |
88 | }; |
89 | ||
90 | enum { | |
91 | MLX5_ATOMIC_MODE_IB_COMP = 1 << 16, | |
92 | MLX5_ATOMIC_MODE_CX = 2 << 16, | |
93 | MLX5_ATOMIC_MODE_8B = 3 << 16, | |
94 | MLX5_ATOMIC_MODE_16B = 4 << 16, | |
95 | MLX5_ATOMIC_MODE_32B = 5 << 16, | |
96 | MLX5_ATOMIC_MODE_64B = 6 << 16, | |
97 | MLX5_ATOMIC_MODE_128B = 7 << 16, | |
98 | MLX5_ATOMIC_MODE_256B = 8 << 16, | |
99 | }; | |
100 | ||
e126ba97 EC |
101 | enum { |
102 | MLX5_REG_PCAP = 0x5001, | |
103 | MLX5_REG_PMTU = 0x5003, | |
104 | MLX5_REG_PTYS = 0x5004, | |
105 | MLX5_REG_PAOS = 0x5006, | |
106 | MLX5_REG_PMAOS = 0x5012, | |
107 | MLX5_REG_PUDE = 0x5009, | |
108 | MLX5_REG_PMPE = 0x5010, | |
109 | MLX5_REG_PELC = 0x500e, | |
110 | MLX5_REG_PMLP = 0, /* TBD */ | |
111 | MLX5_REG_NODE_DESC = 0x6001, | |
112 | MLX5_REG_HOST_ENDIANNESS = 0x7004, | |
113 | }; | |
114 | ||
e420f0c0 HE |
115 | enum mlx5_page_fault_resume_flags { |
116 | MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0, | |
117 | MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1, | |
118 | MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2, | |
119 | MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7, | |
120 | }; | |
121 | ||
e126ba97 EC |
122 | enum dbg_rsc_type { |
123 | MLX5_DBG_RSC_QP, | |
124 | MLX5_DBG_RSC_EQ, | |
125 | MLX5_DBG_RSC_CQ, | |
126 | }; | |
127 | ||
128 | struct mlx5_field_desc { | |
129 | struct dentry *dent; | |
130 | int i; | |
131 | }; | |
132 | ||
133 | struct mlx5_rsc_debug { | |
134 | struct mlx5_core_dev *dev; | |
135 | void *object; | |
136 | enum dbg_rsc_type type; | |
137 | struct dentry *root; | |
138 | struct mlx5_field_desc fields[0]; | |
139 | }; | |
140 | ||
141 | enum mlx5_dev_event { | |
142 | MLX5_DEV_EVENT_SYS_ERROR, | |
143 | MLX5_DEV_EVENT_PORT_UP, | |
144 | MLX5_DEV_EVENT_PORT_DOWN, | |
145 | MLX5_DEV_EVENT_PORT_INITIALIZED, | |
146 | MLX5_DEV_EVENT_LID_CHANGE, | |
147 | MLX5_DEV_EVENT_PKEY_CHANGE, | |
148 | MLX5_DEV_EVENT_GUID_CHANGE, | |
149 | MLX5_DEV_EVENT_CLIENT_REREG, | |
150 | }; | |
151 | ||
4c916a79 RS |
152 | enum mlx5_port_status { |
153 | MLX5_PORT_UP = 1 << 1, | |
154 | MLX5_PORT_DOWN = 1 << 2, | |
155 | }; | |
156 | ||
e126ba97 EC |
157 | struct mlx5_uuar_info { |
158 | struct mlx5_uar *uars; | |
159 | int num_uars; | |
160 | int num_low_latency_uuars; | |
161 | unsigned long *bitmap; | |
162 | unsigned int *count; | |
163 | struct mlx5_bf *bfs; | |
164 | ||
165 | /* | |
166 | * protect uuar allocation data structs | |
167 | */ | |
168 | struct mutex lock; | |
78c0f98c | 169 | u32 ver; |
e126ba97 EC |
170 | }; |
171 | ||
172 | struct mlx5_bf { | |
173 | void __iomem *reg; | |
174 | void __iomem *regreg; | |
175 | int buf_size; | |
176 | struct mlx5_uar *uar; | |
177 | unsigned long offset; | |
178 | int need_lock; | |
179 | /* protect blue flame buffer selection when needed | |
180 | */ | |
181 | spinlock_t lock; | |
182 | ||
183 | /* serialize 64 bit writes when done as two 32 bit accesses | |
184 | */ | |
185 | spinlock_t lock32; | |
186 | int uuarn; | |
187 | }; | |
188 | ||
189 | struct mlx5_cmd_first { | |
190 | __be32 data[4]; | |
191 | }; | |
192 | ||
193 | struct mlx5_cmd_msg { | |
194 | struct list_head list; | |
195 | struct cache_ent *cache; | |
196 | u32 len; | |
197 | struct mlx5_cmd_first first; | |
198 | struct mlx5_cmd_mailbox *next; | |
199 | }; | |
200 | ||
201 | struct mlx5_cmd_debug { | |
202 | struct dentry *dbg_root; | |
203 | struct dentry *dbg_in; | |
204 | struct dentry *dbg_out; | |
205 | struct dentry *dbg_outlen; | |
206 | struct dentry *dbg_status; | |
207 | struct dentry *dbg_run; | |
208 | void *in_msg; | |
209 | void *out_msg; | |
210 | u8 status; | |
211 | u16 inlen; | |
212 | u16 outlen; | |
213 | }; | |
214 | ||
215 | struct cache_ent { | |
216 | /* protect block chain allocations | |
217 | */ | |
218 | spinlock_t lock; | |
219 | struct list_head head; | |
220 | }; | |
221 | ||
222 | struct cmd_msg_cache { | |
223 | struct cache_ent large; | |
224 | struct cache_ent med; | |
225 | ||
226 | }; | |
227 | ||
228 | struct mlx5_cmd_stats { | |
229 | u64 sum; | |
230 | u64 n; | |
231 | struct dentry *root; | |
232 | struct dentry *avg; | |
233 | struct dentry *count; | |
234 | /* protect command average calculations */ | |
235 | spinlock_t lock; | |
236 | }; | |
237 | ||
238 | struct mlx5_cmd { | |
64599cca EC |
239 | void *cmd_alloc_buf; |
240 | dma_addr_t alloc_dma; | |
241 | int alloc_size; | |
e126ba97 EC |
242 | void *cmd_buf; |
243 | dma_addr_t dma; | |
244 | u16 cmdif_rev; | |
245 | u8 log_sz; | |
246 | u8 log_stride; | |
247 | int max_reg_cmds; | |
248 | int events; | |
249 | u32 __iomem *vector; | |
250 | ||
251 | /* protect command queue allocations | |
252 | */ | |
253 | spinlock_t alloc_lock; | |
254 | ||
255 | /* protect token allocations | |
256 | */ | |
257 | spinlock_t token_lock; | |
258 | u8 token; | |
259 | unsigned long bitmask; | |
260 | char wq_name[MLX5_CMD_WQ_MAX_NAME]; | |
261 | struct workqueue_struct *wq; | |
262 | struct semaphore sem; | |
263 | struct semaphore pages_sem; | |
264 | int mode; | |
265 | struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS]; | |
266 | struct pci_pool *pool; | |
267 | struct mlx5_cmd_debug dbg; | |
268 | struct cmd_msg_cache cache; | |
269 | int checksum_disabled; | |
270 | struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX]; | |
271 | }; | |
272 | ||
273 | struct mlx5_port_caps { | |
274 | int gid_table_len; | |
275 | int pkey_table_len; | |
938fe83c | 276 | u8 ext_port_cap; |
e126ba97 EC |
277 | }; |
278 | ||
279 | struct mlx5_cmd_mailbox { | |
280 | void *buf; | |
281 | dma_addr_t dma; | |
282 | struct mlx5_cmd_mailbox *next; | |
283 | }; | |
284 | ||
285 | struct mlx5_buf_list { | |
286 | void *buf; | |
287 | dma_addr_t map; | |
288 | }; | |
289 | ||
290 | struct mlx5_buf { | |
291 | struct mlx5_buf_list direct; | |
e126ba97 | 292 | int npages; |
e126ba97 | 293 | int size; |
f241e749 | 294 | u8 page_shift; |
e126ba97 EC |
295 | }; |
296 | ||
297 | struct mlx5_eq { | |
298 | struct mlx5_core_dev *dev; | |
299 | __be32 __iomem *doorbell; | |
300 | u32 cons_index; | |
301 | struct mlx5_buf buf; | |
302 | int size; | |
303 | u8 irqn; | |
304 | u8 eqn; | |
305 | int nent; | |
306 | u64 mask; | |
e126ba97 EC |
307 | struct list_head list; |
308 | int index; | |
309 | struct mlx5_rsc_debug *dbg; | |
310 | }; | |
311 | ||
3121e3c4 SG |
312 | struct mlx5_core_psv { |
313 | u32 psv_idx; | |
314 | struct psv_layout { | |
315 | u32 pd; | |
316 | u16 syndrome; | |
317 | u16 reserved; | |
318 | u16 bg; | |
319 | u16 app_tag; | |
320 | u32 ref_tag; | |
321 | } psv; | |
322 | }; | |
323 | ||
324 | struct mlx5_core_sig_ctx { | |
325 | struct mlx5_core_psv psv_memory; | |
326 | struct mlx5_core_psv psv_wire; | |
d5436ba0 SG |
327 | struct ib_sig_err err_item; |
328 | bool sig_status_checked; | |
329 | bool sig_err_exists; | |
330 | u32 sigerr_count; | |
3121e3c4 | 331 | }; |
e126ba97 EC |
332 | |
333 | struct mlx5_core_mr { | |
334 | u64 iova; | |
335 | u64 size; | |
336 | u32 key; | |
337 | u32 pd; | |
e126ba97 EC |
338 | }; |
339 | ||
5903325a EC |
340 | enum mlx5_res_type { |
341 | MLX5_RES_QP, | |
342 | }; | |
343 | ||
344 | struct mlx5_core_rsc_common { | |
345 | enum mlx5_res_type res; | |
346 | atomic_t refcount; | |
347 | struct completion free; | |
348 | }; | |
349 | ||
e126ba97 EC |
350 | struct mlx5_core_srq { |
351 | u32 srqn; | |
352 | int max; | |
353 | int max_gs; | |
354 | int max_avail_gather; | |
355 | int wqe_shift; | |
356 | void (*event) (struct mlx5_core_srq *, enum mlx5_event); | |
357 | ||
358 | atomic_t refcount; | |
359 | struct completion free; | |
360 | }; | |
361 | ||
362 | struct mlx5_eq_table { | |
363 | void __iomem *update_ci; | |
364 | void __iomem *update_arm_ci; | |
233d05d2 | 365 | struct list_head comp_eqs_list; |
e126ba97 EC |
366 | struct mlx5_eq pages_eq; |
367 | struct mlx5_eq async_eq; | |
368 | struct mlx5_eq cmd_eq; | |
e126ba97 EC |
369 | int num_comp_vectors; |
370 | /* protect EQs list | |
371 | */ | |
372 | spinlock_t lock; | |
373 | }; | |
374 | ||
375 | struct mlx5_uar { | |
376 | u32 index; | |
377 | struct list_head bf_list; | |
378 | unsigned free_bf_bmap; | |
379 | void __iomem *wc_map; | |
380 | void __iomem *map; | |
381 | }; | |
382 | ||
383 | ||
384 | struct mlx5_core_health { | |
385 | struct health_buffer __iomem *health; | |
386 | __be32 __iomem *health_counter; | |
387 | struct timer_list timer; | |
388 | struct list_head list; | |
389 | u32 prev; | |
390 | int miss_counter; | |
391 | }; | |
392 | ||
393 | struct mlx5_cq_table { | |
394 | /* protect radix tree | |
395 | */ | |
396 | spinlock_t lock; | |
397 | struct radix_tree_root tree; | |
398 | }; | |
399 | ||
400 | struct mlx5_qp_table { | |
401 | /* protect radix tree | |
402 | */ | |
403 | spinlock_t lock; | |
404 | struct radix_tree_root tree; | |
405 | }; | |
406 | ||
407 | struct mlx5_srq_table { | |
408 | /* protect radix tree | |
409 | */ | |
410 | spinlock_t lock; | |
411 | struct radix_tree_root tree; | |
412 | }; | |
413 | ||
3bcdb17a SG |
414 | struct mlx5_mr_table { |
415 | /* protect radix tree | |
416 | */ | |
417 | rwlock_t lock; | |
418 | struct radix_tree_root tree; | |
419 | }; | |
420 | ||
db058a18 SM |
421 | struct mlx5_irq_info { |
422 | cpumask_var_t mask; | |
423 | char name[MLX5_MAX_IRQ_NAME]; | |
424 | }; | |
425 | ||
e126ba97 EC |
426 | struct mlx5_priv { |
427 | char name[MLX5_MAX_NAME_LEN]; | |
428 | struct mlx5_eq_table eq_table; | |
db058a18 SM |
429 | struct msix_entry *msix_arr; |
430 | struct mlx5_irq_info *irq_info; | |
e126ba97 EC |
431 | struct mlx5_uuar_info uuari; |
432 | MLX5_DECLARE_DOORBELL_LOCK(cq_uar_lock); | |
433 | ||
434 | /* pages stuff */ | |
435 | struct workqueue_struct *pg_wq; | |
436 | struct rb_root page_root; | |
437 | int fw_pages; | |
6aec21f6 | 438 | atomic_t reg_pages; |
bf0bf77f | 439 | struct list_head free_list; |
e126ba97 EC |
440 | |
441 | struct mlx5_core_health health; | |
442 | ||
443 | struct mlx5_srq_table srq_table; | |
444 | ||
445 | /* start: qp staff */ | |
446 | struct mlx5_qp_table qp_table; | |
447 | struct dentry *qp_debugfs; | |
448 | struct dentry *eq_debugfs; | |
449 | struct dentry *cq_debugfs; | |
450 | struct dentry *cmdif_debugfs; | |
451 | /* end: qp staff */ | |
452 | ||
453 | /* start: cq staff */ | |
454 | struct mlx5_cq_table cq_table; | |
455 | /* end: cq staff */ | |
456 | ||
3bcdb17a SG |
457 | /* start: mr staff */ |
458 | struct mlx5_mr_table mr_table; | |
459 | /* end: mr staff */ | |
460 | ||
e126ba97 EC |
461 | /* start: alloc staff */ |
462 | struct mutex pgdir_mutex; | |
463 | struct list_head pgdir_list; | |
464 | /* end: alloc staff */ | |
465 | struct dentry *dbg_root; | |
466 | ||
467 | /* protect mkey key part */ | |
468 | spinlock_t mkey_lock; | |
469 | u8 mkey_key; | |
9603b61d JM |
470 | |
471 | struct list_head dev_list; | |
472 | struct list_head ctx_list; | |
473 | spinlock_t ctx_lock; | |
e126ba97 EC |
474 | }; |
475 | ||
476 | struct mlx5_core_dev { | |
477 | struct pci_dev *pdev; | |
478 | u8 rev_id; | |
479 | char board_id[MLX5_BOARD_ID_LEN]; | |
480 | struct mlx5_cmd cmd; | |
938fe83c SM |
481 | struct mlx5_port_caps port_caps[MLX5_MAX_PORTS]; |
482 | u32 hca_caps_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; | |
483 | u32 hca_caps_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; | |
e126ba97 EC |
484 | phys_addr_t iseg_base; |
485 | struct mlx5_init_seg __iomem *iseg; | |
486 | void (*event) (struct mlx5_core_dev *dev, | |
487 | enum mlx5_dev_event event, | |
4d2f9bbb | 488 | unsigned long param); |
e126ba97 EC |
489 | struct mlx5_priv priv; |
490 | struct mlx5_profile *profile; | |
491 | atomic_t num_qps; | |
492 | }; | |
493 | ||
494 | struct mlx5_db { | |
495 | __be32 *db; | |
496 | union { | |
497 | struct mlx5_db_pgdir *pgdir; | |
498 | struct mlx5_ib_user_db_page *user_page; | |
499 | } u; | |
500 | dma_addr_t dma; | |
501 | int index; | |
502 | }; | |
503 | ||
504 | enum { | |
505 | MLX5_DB_PER_PAGE = PAGE_SIZE / L1_CACHE_BYTES, | |
506 | }; | |
507 | ||
508 | enum { | |
509 | MLX5_COMP_EQ_SIZE = 1024, | |
510 | }; | |
511 | ||
adb0c954 SM |
512 | enum { |
513 | MLX5_PTYS_IB = 1 << 0, | |
514 | MLX5_PTYS_EN = 1 << 2, | |
515 | }; | |
516 | ||
e126ba97 EC |
517 | struct mlx5_db_pgdir { |
518 | struct list_head list; | |
519 | DECLARE_BITMAP(bitmap, MLX5_DB_PER_PAGE); | |
520 | __be32 *db_page; | |
521 | dma_addr_t db_dma; | |
522 | }; | |
523 | ||
524 | typedef void (*mlx5_cmd_cbk_t)(int status, void *context); | |
525 | ||
526 | struct mlx5_cmd_work_ent { | |
527 | struct mlx5_cmd_msg *in; | |
528 | struct mlx5_cmd_msg *out; | |
746b5583 EC |
529 | void *uout; |
530 | int uout_size; | |
e126ba97 EC |
531 | mlx5_cmd_cbk_t callback; |
532 | void *context; | |
746b5583 | 533 | int idx; |
e126ba97 EC |
534 | struct completion done; |
535 | struct mlx5_cmd *cmd; | |
536 | struct work_struct work; | |
537 | struct mlx5_cmd_layout *lay; | |
538 | int ret; | |
539 | int page_queue; | |
540 | u8 status; | |
541 | u8 token; | |
14a70046 TG |
542 | u64 ts1; |
543 | u64 ts2; | |
746b5583 | 544 | u16 op; |
e126ba97 EC |
545 | }; |
546 | ||
547 | struct mlx5_pas { | |
548 | u64 pa; | |
549 | u8 log_sz; | |
550 | }; | |
551 | ||
552 | static inline void *mlx5_buf_offset(struct mlx5_buf *buf, int offset) | |
553 | { | |
e126ba97 | 554 | return buf->direct.buf + offset; |
e126ba97 EC |
555 | } |
556 | ||
557 | extern struct workqueue_struct *mlx5_core_wq; | |
558 | ||
559 | #define STRUCT_FIELD(header, field) \ | |
560 | .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \ | |
561 | .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field | |
562 | ||
563 | struct ib_field { | |
564 | size_t struct_offset_bytes; | |
565 | size_t struct_size_bytes; | |
566 | int offset_bits; | |
567 | int size_bits; | |
568 | }; | |
569 | ||
570 | static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev) | |
571 | { | |
572 | return pci_get_drvdata(pdev); | |
573 | } | |
574 | ||
575 | extern struct dentry *mlx5_debugfs_root; | |
576 | ||
577 | static inline u16 fw_rev_maj(struct mlx5_core_dev *dev) | |
578 | { | |
579 | return ioread32be(&dev->iseg->fw_rev) & 0xffff; | |
580 | } | |
581 | ||
582 | static inline u16 fw_rev_min(struct mlx5_core_dev *dev) | |
583 | { | |
584 | return ioread32be(&dev->iseg->fw_rev) >> 16; | |
585 | } | |
586 | ||
587 | static inline u16 fw_rev_sub(struct mlx5_core_dev *dev) | |
588 | { | |
589 | return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff; | |
590 | } | |
591 | ||
592 | static inline u16 cmdif_rev(struct mlx5_core_dev *dev) | |
593 | { | |
594 | return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16; | |
595 | } | |
596 | ||
597 | static inline void *mlx5_vzalloc(unsigned long size) | |
598 | { | |
599 | void *rtn; | |
600 | ||
601 | rtn = kzalloc(size, GFP_KERNEL | __GFP_NOWARN); | |
602 | if (!rtn) | |
603 | rtn = vzalloc(size); | |
604 | return rtn; | |
605 | } | |
606 | ||
3bcdb17a SG |
607 | static inline u32 mlx5_base_mkey(const u32 key) |
608 | { | |
609 | return key & 0xffffff00u; | |
610 | } | |
611 | ||
e126ba97 EC |
612 | int mlx5_cmd_init(struct mlx5_core_dev *dev); |
613 | void mlx5_cmd_cleanup(struct mlx5_core_dev *dev); | |
614 | void mlx5_cmd_use_events(struct mlx5_core_dev *dev); | |
615 | void mlx5_cmd_use_polling(struct mlx5_core_dev *dev); | |
616 | int mlx5_cmd_status_to_err(struct mlx5_outbox_hdr *hdr); | |
b775516b | 617 | int mlx5_cmd_status_to_err_v2(void *ptr); |
938fe83c SM |
618 | int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type, |
619 | enum mlx5_cap_mode cap_mode); | |
e126ba97 EC |
620 | int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out, |
621 | int out_size); | |
746b5583 EC |
622 | int mlx5_cmd_exec_cb(struct mlx5_core_dev *dev, void *in, int in_size, |
623 | void *out, int out_size, mlx5_cmd_cbk_t callback, | |
624 | void *context); | |
e126ba97 EC |
625 | int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn); |
626 | int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn); | |
627 | int mlx5_alloc_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari); | |
628 | int mlx5_free_uuars(struct mlx5_core_dev *dev, struct mlx5_uuar_info *uuari); | |
e281682b SM |
629 | int mlx5_alloc_map_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar); |
630 | void mlx5_unmap_free_uar(struct mlx5_core_dev *mdev, struct mlx5_uar *uar); | |
e126ba97 EC |
631 | void mlx5_health_cleanup(void); |
632 | void __init mlx5_health_init(void); | |
633 | void mlx5_start_health_poll(struct mlx5_core_dev *dev); | |
634 | void mlx5_stop_health_poll(struct mlx5_core_dev *dev); | |
64ffaa21 | 635 | int mlx5_buf_alloc(struct mlx5_core_dev *dev, int size, struct mlx5_buf *buf); |
e126ba97 EC |
636 | void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_buf *buf); |
637 | struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev, | |
638 | gfp_t flags, int npages); | |
639 | void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev, | |
640 | struct mlx5_cmd_mailbox *head); | |
641 | int mlx5_core_create_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, | |
642 | struct mlx5_create_srq_mbox_in *in, int inlen); | |
643 | int mlx5_core_destroy_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq); | |
644 | int mlx5_core_query_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, | |
645 | struct mlx5_query_srq_mbox_out *out); | |
646 | int mlx5_core_arm_srq(struct mlx5_core_dev *dev, struct mlx5_core_srq *srq, | |
647 | u16 lwm, int is_srq); | |
3bcdb17a SG |
648 | void mlx5_init_mr_table(struct mlx5_core_dev *dev); |
649 | void mlx5_cleanup_mr_table(struct mlx5_core_dev *dev); | |
e126ba97 | 650 | int mlx5_core_create_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr, |
746b5583 EC |
651 | struct mlx5_create_mkey_mbox_in *in, int inlen, |
652 | mlx5_cmd_cbk_t callback, void *context, | |
653 | struct mlx5_create_mkey_mbox_out *out); | |
e126ba97 EC |
654 | int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr); |
655 | int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr, | |
656 | struct mlx5_query_mkey_mbox_out *out, int outlen); | |
657 | int mlx5_core_dump_fill_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mr *mr, | |
658 | u32 *mkey); | |
659 | int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn); | |
660 | int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn); | |
661 | int mlx5_core_mad_ifc(struct mlx5_core_dev *dev, void *inb, void *outb, | |
f241e749 | 662 | u16 opmod, u8 port); |
e126ba97 EC |
663 | void mlx5_pagealloc_init(struct mlx5_core_dev *dev); |
664 | void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev); | |
665 | int mlx5_pagealloc_start(struct mlx5_core_dev *dev); | |
666 | void mlx5_pagealloc_stop(struct mlx5_core_dev *dev); | |
667 | void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id, | |
0a324f31 | 668 | s32 npages); |
cd23b14b | 669 | int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot); |
e126ba97 EC |
670 | int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev); |
671 | void mlx5_register_debugfs(void); | |
672 | void mlx5_unregister_debugfs(void); | |
673 | int mlx5_eq_init(struct mlx5_core_dev *dev); | |
674 | void mlx5_eq_cleanup(struct mlx5_core_dev *dev); | |
675 | void mlx5_fill_page_array(struct mlx5_buf *buf, __be64 *pas); | |
676 | void mlx5_cq_completion(struct mlx5_core_dev *dev, u32 cqn); | |
5903325a | 677 | void mlx5_rsc_event(struct mlx5_core_dev *dev, u32 rsn, int event_type); |
e420f0c0 HE |
678 | #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING |
679 | void mlx5_eq_pagefault(struct mlx5_core_dev *dev, struct mlx5_eqe *eqe); | |
680 | #endif | |
e126ba97 EC |
681 | void mlx5_srq_event(struct mlx5_core_dev *dev, u32 srqn, int event_type); |
682 | struct mlx5_core_srq *mlx5_core_get_srq(struct mlx5_core_dev *dev, u32 srqn); | |
683 | void mlx5_cmd_comp_handler(struct mlx5_core_dev *dev, unsigned long vector); | |
684 | void mlx5_cq_event(struct mlx5_core_dev *dev, u32 cqn, int event_type); | |
685 | int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx, | |
686 | int nent, u64 mask, const char *name, struct mlx5_uar *uar); | |
687 | int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq); | |
688 | int mlx5_start_eqs(struct mlx5_core_dev *dev); | |
689 | int mlx5_stop_eqs(struct mlx5_core_dev *dev); | |
233d05d2 | 690 | int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, int *irqn); |
e126ba97 EC |
691 | int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); |
692 | int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); | |
693 | ||
694 | int mlx5_qp_debugfs_init(struct mlx5_core_dev *dev); | |
695 | void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev); | |
696 | int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in, | |
697 | int size_in, void *data_out, int size_out, | |
698 | u16 reg_num, int arg, int write); | |
adb0c954 | 699 | |
f241e749 | 700 | int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps); |
adb0c954 SM |
701 | int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys, |
702 | int ptys_size, int proto_mask); | |
703 | int mlx5_query_port_proto_cap(struct mlx5_core_dev *dev, | |
704 | u32 *proto_cap, int proto_mask); | |
705 | int mlx5_query_port_proto_admin(struct mlx5_core_dev *dev, | |
706 | u32 *proto_admin, int proto_mask); | |
707 | int mlx5_set_port_proto(struct mlx5_core_dev *dev, u32 proto_admin, | |
708 | int proto_mask); | |
4c916a79 RS |
709 | int mlx5_set_port_status(struct mlx5_core_dev *dev, |
710 | enum mlx5_port_status status); | |
711 | int mlx5_query_port_status(struct mlx5_core_dev *dev, u8 *status); | |
e126ba97 | 712 | |
e725440e SM |
713 | int mlx5_set_port_mtu(struct mlx5_core_dev *dev, int mtu); |
714 | int mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, int *max_mtu); | |
715 | int mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, int *oper_mtu); | |
716 | ||
e126ba97 EC |
717 | int mlx5_debug_eq_add(struct mlx5_core_dev *dev, struct mlx5_eq *eq); |
718 | void mlx5_debug_eq_remove(struct mlx5_core_dev *dev, struct mlx5_eq *eq); | |
719 | int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq, | |
720 | struct mlx5_query_eq_mbox_out *out, int outlen); | |
721 | int mlx5_eq_debugfs_init(struct mlx5_core_dev *dev); | |
722 | void mlx5_eq_debugfs_cleanup(struct mlx5_core_dev *dev); | |
723 | int mlx5_cq_debugfs_init(struct mlx5_core_dev *dev); | |
724 | void mlx5_cq_debugfs_cleanup(struct mlx5_core_dev *dev); | |
725 | int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db); | |
726 | void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db); | |
727 | ||
e126ba97 EC |
728 | const char *mlx5_command_str(int command); |
729 | int mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev); | |
730 | void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev); | |
3121e3c4 SG |
731 | int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn, |
732 | int npsvs, u32 *sig_index); | |
733 | int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num); | |
5903325a | 734 | void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common); |
e420f0c0 HE |
735 | int mlx5_query_odp_caps(struct mlx5_core_dev *dev, |
736 | struct mlx5_odp_caps *odp_caps); | |
e126ba97 EC |
737 | |
738 | static inline u32 mlx5_mkey_to_idx(u32 mkey) | |
739 | { | |
740 | return mkey >> 8; | |
741 | } | |
742 | ||
743 | static inline u32 mlx5_idx_to_mkey(u32 mkey_idx) | |
744 | { | |
745 | return mkey_idx << 8; | |
746 | } | |
747 | ||
746b5583 EC |
748 | static inline u8 mlx5_mkey_variant(u32 mkey) |
749 | { | |
750 | return mkey & 0xff; | |
751 | } | |
752 | ||
e126ba97 EC |
753 | enum { |
754 | MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0, | |
c1868b82 | 755 | MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1, |
e126ba97 EC |
756 | }; |
757 | ||
758 | enum { | |
759 | MAX_MR_CACHE_ENTRIES = 16, | |
760 | }; | |
761 | ||
64613d94 SM |
762 | enum { |
763 | MLX5_INTERFACE_PROTOCOL_IB = 0, | |
764 | MLX5_INTERFACE_PROTOCOL_ETH = 1, | |
765 | }; | |
766 | ||
9603b61d JM |
767 | struct mlx5_interface { |
768 | void * (*add)(struct mlx5_core_dev *dev); | |
769 | void (*remove)(struct mlx5_core_dev *dev, void *context); | |
770 | void (*event)(struct mlx5_core_dev *dev, void *context, | |
4d2f9bbb | 771 | enum mlx5_dev_event event, unsigned long param); |
64613d94 SM |
772 | void * (*get_dev)(void *context); |
773 | int protocol; | |
9603b61d JM |
774 | struct list_head list; |
775 | }; | |
776 | ||
64613d94 | 777 | void *mlx5_get_protocol_dev(struct mlx5_core_dev *mdev, int protocol); |
9603b61d JM |
778 | int mlx5_register_interface(struct mlx5_interface *intf); |
779 | void mlx5_unregister_interface(struct mlx5_interface *intf); | |
780 | ||
e126ba97 EC |
781 | struct mlx5_profile { |
782 | u64 mask; | |
f241e749 | 783 | u8 log_max_qp; |
e126ba97 EC |
784 | struct { |
785 | int size; | |
786 | int limit; | |
787 | } mr_cache[MAX_MR_CACHE_ENTRIES]; | |
788 | }; | |
789 | ||
790 | #endif /* MLX5_DRIVER_H */ |