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e126ba97 | 1 | /* |
302bdf68 | 2 | * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved. |
e126ba97 EC |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
31 | */ | |
32 | ||
33 | #ifndef MLX5_DRIVER_H | |
34 | #define MLX5_DRIVER_H | |
35 | ||
36 | #include <linux/kernel.h> | |
37 | #include <linux/completion.h> | |
38 | #include <linux/pci.h> | |
05e0cc84 | 39 | #include <linux/irq.h> |
e126ba97 EC |
40 | #include <linux/spinlock_types.h> |
41 | #include <linux/semaphore.h> | |
6ecde51d | 42 | #include <linux/slab.h> |
e126ba97 | 43 | #include <linux/vmalloc.h> |
792c4e9d | 44 | #include <linux/xarray.h> |
43a335e0 | 45 | #include <linux/workqueue.h> |
d9aaed83 | 46 | #include <linux/mempool.h> |
94c6825e | 47 | #include <linux/interrupt.h> |
52ec462e | 48 | #include <linux/idr.h> |
20902be4 | 49 | #include <linux/notifier.h> |
94f3e14e | 50 | #include <linux/refcount.h> |
6ecde51d | 51 | |
e126ba97 EC |
52 | #include <linux/mlx5/device.h> |
53 | #include <linux/mlx5/doorbell.h> | |
41069256 | 54 | #include <linux/mlx5/eq.h> |
7c39afb3 FD |
55 | #include <linux/timecounter.h> |
56 | #include <linux/ptp_clock_kernel.h> | |
1e34f3ef | 57 | #include <net/devlink.h> |
e126ba97 EC |
58 | |
59 | enum { | |
60 | MLX5_BOARD_ID_LEN = 64, | |
e126ba97 EC |
61 | }; |
62 | ||
63 | enum { | |
64 | /* one minute for the sake of bringup. Generally, commands must always | |
65 | * complete and we may need to increase this timeout value | |
66 | */ | |
6b6c07bd | 67 | MLX5_CMD_TIMEOUT_MSEC = 60 * 1000, |
e126ba97 EC |
68 | MLX5_CMD_WQ_MAX_NAME = 32, |
69 | }; | |
70 | ||
71 | enum { | |
72 | CMD_OWNER_SW = 0x0, | |
73 | CMD_OWNER_HW = 0x1, | |
74 | CMD_STATUS_SUCCESS = 0, | |
75 | }; | |
76 | ||
77 | enum mlx5_sqp_t { | |
78 | MLX5_SQP_SMI = 0, | |
79 | MLX5_SQP_GSI = 1, | |
80 | MLX5_SQP_IEEE_1588 = 2, | |
81 | MLX5_SQP_SNIFFER = 3, | |
82 | MLX5_SQP_SYNC_UMR = 4, | |
83 | }; | |
84 | ||
85 | enum { | |
86 | MLX5_MAX_PORTS = 2, | |
87 | }; | |
88 | ||
e126ba97 | 89 | enum { |
a60109dc YC |
90 | MLX5_ATOMIC_MODE_OFFSET = 16, |
91 | MLX5_ATOMIC_MODE_IB_COMP = 1, | |
92 | MLX5_ATOMIC_MODE_CX = 2, | |
93 | MLX5_ATOMIC_MODE_8B = 3, | |
94 | MLX5_ATOMIC_MODE_16B = 4, | |
95 | MLX5_ATOMIC_MODE_32B = 5, | |
96 | MLX5_ATOMIC_MODE_64B = 6, | |
97 | MLX5_ATOMIC_MODE_128B = 7, | |
98 | MLX5_ATOMIC_MODE_256B = 8, | |
e126ba97 EC |
99 | }; |
100 | ||
e126ba97 | 101 | enum { |
415a64aa | 102 | MLX5_REG_QPTS = 0x4002, |
4f3961ee SM |
103 | MLX5_REG_QETCR = 0x4005, |
104 | MLX5_REG_QTCT = 0x400a, | |
415a64aa | 105 | MLX5_REG_QPDPM = 0x4013, |
c02762eb | 106 | MLX5_REG_QCAM = 0x4019, |
341c5ee2 HN |
107 | MLX5_REG_DCBX_PARAM = 0x4020, |
108 | MLX5_REG_DCBX_APP = 0x4021, | |
e29341fb IT |
109 | MLX5_REG_FPGA_CAP = 0x4022, |
110 | MLX5_REG_FPGA_CTRL = 0x4023, | |
a9956d35 | 111 | MLX5_REG_FPGA_ACCESS_REG = 0x4024, |
0b9055a1 | 112 | MLX5_REG_CORE_DUMP = 0x402e, |
e126ba97 EC |
113 | MLX5_REG_PCAP = 0x5001, |
114 | MLX5_REG_PMTU = 0x5003, | |
115 | MLX5_REG_PTYS = 0x5004, | |
116 | MLX5_REG_PAOS = 0x5006, | |
3c2d18ef | 117 | MLX5_REG_PFCC = 0x5007, |
efea389d | 118 | MLX5_REG_PPCNT = 0x5008, |
50b4a3c2 HN |
119 | MLX5_REG_PPTB = 0x500b, |
120 | MLX5_REG_PBMC = 0x500c, | |
e126ba97 EC |
121 | MLX5_REG_PMAOS = 0x5012, |
122 | MLX5_REG_PUDE = 0x5009, | |
123 | MLX5_REG_PMPE = 0x5010, | |
124 | MLX5_REG_PELC = 0x500e, | |
a124d13e | 125 | MLX5_REG_PVLC = 0x500f, |
94cb1ebb | 126 | MLX5_REG_PCMR = 0x5041, |
bb64143e | 127 | MLX5_REG_PMLP = 0x5002, |
4b5b9c7d | 128 | MLX5_REG_PPLM = 0x5023, |
cfdcbcea | 129 | MLX5_REG_PCAM = 0x507f, |
e126ba97 EC |
130 | MLX5_REG_NODE_DESC = 0x6001, |
131 | MLX5_REG_HOST_ENDIANNESS = 0x7004, | |
bb64143e | 132 | MLX5_REG_MCIA = 0x9014, |
da54d24e | 133 | MLX5_REG_MLCR = 0x902b, |
eff8ea8f FD |
134 | MLX5_REG_MTRC_CAP = 0x9040, |
135 | MLX5_REG_MTRC_CONF = 0x9041, | |
136 | MLX5_REG_MTRC_STDB = 0x9042, | |
137 | MLX5_REG_MTRC_CTRL = 0x9043, | |
4039049b | 138 | MLX5_REG_MPEIN = 0x9050, |
8ed1a630 | 139 | MLX5_REG_MPCNT = 0x9051, |
f9a1ef72 EE |
140 | MLX5_REG_MTPPS = 0x9053, |
141 | MLX5_REG_MTPPSE = 0x9054, | |
5e022dd3 | 142 | MLX5_REG_MPEGC = 0x9056, |
a82e0b5b | 143 | MLX5_REG_MCQS = 0x9060, |
47176289 OG |
144 | MLX5_REG_MCQI = 0x9061, |
145 | MLX5_REG_MCC = 0x9062, | |
146 | MLX5_REG_MCDA = 0x9063, | |
cfdcbcea | 147 | MLX5_REG_MCAM = 0x907f, |
bab58ba1 | 148 | MLX5_REG_MIRC = 0x9162, |
609b8272 | 149 | MLX5_REG_RESOURCE_DUMP = 0xC000, |
e126ba97 EC |
150 | }; |
151 | ||
415a64aa HN |
152 | enum mlx5_qpts_trust_state { |
153 | MLX5_QPTS_TRUST_PCP = 1, | |
154 | MLX5_QPTS_TRUST_DSCP = 2, | |
155 | }; | |
156 | ||
341c5ee2 HN |
157 | enum mlx5_dcbx_oper_mode { |
158 | MLX5E_DCBX_PARAM_VER_OPER_HOST = 0x0, | |
159 | MLX5E_DCBX_PARAM_VER_OPER_AUTO = 0x3, | |
160 | }; | |
161 | ||
da7525d2 EBE |
162 | enum { |
163 | MLX5_ATOMIC_OPS_CMP_SWAP = 1 << 0, | |
164 | MLX5_ATOMIC_OPS_FETCH_ADD = 1 << 1, | |
a60109dc YC |
165 | MLX5_ATOMIC_OPS_EXTENDED_CMP_SWAP = 1 << 2, |
166 | MLX5_ATOMIC_OPS_EXTENDED_FETCH_ADD = 1 << 3, | |
da7525d2 EBE |
167 | }; |
168 | ||
e420f0c0 HE |
169 | enum mlx5_page_fault_resume_flags { |
170 | MLX5_PAGE_FAULT_RESUME_REQUESTOR = 1 << 0, | |
171 | MLX5_PAGE_FAULT_RESUME_WRITE = 1 << 1, | |
172 | MLX5_PAGE_FAULT_RESUME_RDMA = 1 << 2, | |
173 | MLX5_PAGE_FAULT_RESUME_ERROR = 1 << 7, | |
174 | }; | |
175 | ||
e126ba97 EC |
176 | enum dbg_rsc_type { |
177 | MLX5_DBG_RSC_QP, | |
178 | MLX5_DBG_RSC_EQ, | |
179 | MLX5_DBG_RSC_CQ, | |
180 | }; | |
181 | ||
7ecf6d8f BW |
182 | enum port_state_policy { |
183 | MLX5_POLICY_DOWN = 0, | |
184 | MLX5_POLICY_UP = 1, | |
185 | MLX5_POLICY_FOLLOW = 2, | |
186 | MLX5_POLICY_INVALID = 0xffffffff | |
187 | }; | |
188 | ||
386e75af HN |
189 | enum mlx5_coredev_type { |
190 | MLX5_COREDEV_PF, | |
191 | MLX5_COREDEV_VF | |
192 | }; | |
193 | ||
e126ba97 | 194 | struct mlx5_field_desc { |
e126ba97 EC |
195 | int i; |
196 | }; | |
197 | ||
198 | struct mlx5_rsc_debug { | |
199 | struct mlx5_core_dev *dev; | |
200 | void *object; | |
201 | enum dbg_rsc_type type; | |
202 | struct dentry *root; | |
203 | struct mlx5_field_desc fields[0]; | |
204 | }; | |
205 | ||
206 | enum mlx5_dev_event { | |
58d180b3 | 207 | MLX5_DEV_EVENT_SYS_ERROR = 128, /* 0 - 127 are FW events */ |
6997b1c9 | 208 | MLX5_DEV_EVENT_PORT_AFFINITY = 129, |
e126ba97 EC |
209 | }; |
210 | ||
4c916a79 | 211 | enum mlx5_port_status { |
6fa1bcab AS |
212 | MLX5_PORT_UP = 1, |
213 | MLX5_PORT_DOWN = 2, | |
4c916a79 RS |
214 | }; |
215 | ||
e126ba97 EC |
216 | struct mlx5_cmd_first { |
217 | __be32 data[4]; | |
218 | }; | |
219 | ||
220 | struct mlx5_cmd_msg { | |
221 | struct list_head list; | |
0ac3ea70 | 222 | struct cmd_msg_cache *parent; |
e126ba97 EC |
223 | u32 len; |
224 | struct mlx5_cmd_first first; | |
225 | struct mlx5_cmd_mailbox *next; | |
226 | }; | |
227 | ||
228 | struct mlx5_cmd_debug { | |
229 | struct dentry *dbg_root; | |
e126ba97 EC |
230 | void *in_msg; |
231 | void *out_msg; | |
232 | u8 status; | |
233 | u16 inlen; | |
234 | u16 outlen; | |
235 | }; | |
236 | ||
0ac3ea70 | 237 | struct cmd_msg_cache { |
e126ba97 EC |
238 | /* protect block chain allocations |
239 | */ | |
240 | spinlock_t lock; | |
241 | struct list_head head; | |
0ac3ea70 MHY |
242 | unsigned int max_inbox_size; |
243 | unsigned int num_ent; | |
e126ba97 EC |
244 | }; |
245 | ||
0ac3ea70 MHY |
246 | enum { |
247 | MLX5_NUM_COMMAND_CACHES = 5, | |
e126ba97 EC |
248 | }; |
249 | ||
250 | struct mlx5_cmd_stats { | |
251 | u64 sum; | |
252 | u64 n; | |
253 | struct dentry *root; | |
e126ba97 EC |
254 | /* protect command average calculations */ |
255 | spinlock_t lock; | |
256 | }; | |
257 | ||
258 | struct mlx5_cmd { | |
71edc69c SM |
259 | struct mlx5_nb nb; |
260 | ||
64599cca EC |
261 | void *cmd_alloc_buf; |
262 | dma_addr_t alloc_dma; | |
263 | int alloc_size; | |
e126ba97 EC |
264 | void *cmd_buf; |
265 | dma_addr_t dma; | |
266 | u16 cmdif_rev; | |
267 | u8 log_sz; | |
268 | u8 log_stride; | |
269 | int max_reg_cmds; | |
270 | int events; | |
271 | u32 __iomem *vector; | |
272 | ||
273 | /* protect command queue allocations | |
274 | */ | |
275 | spinlock_t alloc_lock; | |
276 | ||
277 | /* protect token allocations | |
278 | */ | |
279 | spinlock_t token_lock; | |
280 | u8 token; | |
281 | unsigned long bitmask; | |
282 | char wq_name[MLX5_CMD_WQ_MAX_NAME]; | |
283 | struct workqueue_struct *wq; | |
284 | struct semaphore sem; | |
285 | struct semaphore pages_sem; | |
286 | int mode; | |
d43b7007 | 287 | u16 allowed_opcode; |
e126ba97 | 288 | struct mlx5_cmd_work_ent *ent_arr[MLX5_MAX_COMMANDS]; |
18c90df9 | 289 | struct dma_pool *pool; |
e126ba97 | 290 | struct mlx5_cmd_debug dbg; |
0ac3ea70 | 291 | struct cmd_msg_cache cache[MLX5_NUM_COMMAND_CACHES]; |
e126ba97 EC |
292 | int checksum_disabled; |
293 | struct mlx5_cmd_stats stats[MLX5_CMD_OP_MAX]; | |
294 | }; | |
295 | ||
296 | struct mlx5_port_caps { | |
297 | int gid_table_len; | |
298 | int pkey_table_len; | |
938fe83c | 299 | u8 ext_port_cap; |
c43f1112 | 300 | bool has_smi; |
e126ba97 EC |
301 | }; |
302 | ||
303 | struct mlx5_cmd_mailbox { | |
304 | void *buf; | |
305 | dma_addr_t dma; | |
306 | struct mlx5_cmd_mailbox *next; | |
307 | }; | |
308 | ||
309 | struct mlx5_buf_list { | |
310 | void *buf; | |
311 | dma_addr_t map; | |
312 | }; | |
313 | ||
1c1b5228 TT |
314 | struct mlx5_frag_buf { |
315 | struct mlx5_buf_list *frags; | |
316 | int npages; | |
317 | int size; | |
318 | u8 page_shift; | |
319 | }; | |
320 | ||
388ca8be | 321 | struct mlx5_frag_buf_ctrl { |
4972e6fa | 322 | struct mlx5_buf_list *frags; |
388ca8be | 323 | u32 sz_m1; |
8d71e818 | 324 | u16 frag_sz_m1; |
a0903622 | 325 | u16 strides_offset; |
388ca8be YC |
326 | u8 log_sz; |
327 | u8 log_stride; | |
328 | u8 log_frag_strides; | |
329 | }; | |
330 | ||
3121e3c4 SG |
331 | struct mlx5_core_psv { |
332 | u32 psv_idx; | |
333 | struct psv_layout { | |
334 | u32 pd; | |
335 | u16 syndrome; | |
336 | u16 reserved; | |
337 | u16 bg; | |
338 | u16 app_tag; | |
339 | u32 ref_tag; | |
340 | } psv; | |
341 | }; | |
342 | ||
343 | struct mlx5_core_sig_ctx { | |
344 | struct mlx5_core_psv psv_memory; | |
345 | struct mlx5_core_psv psv_wire; | |
d5436ba0 SG |
346 | struct ib_sig_err err_item; |
347 | bool sig_status_checked; | |
348 | bool sig_err_exists; | |
349 | u32 sigerr_count; | |
3121e3c4 | 350 | }; |
e126ba97 | 351 | |
aa8e08d2 AK |
352 | enum { |
353 | MLX5_MKEY_MR = 1, | |
354 | MLX5_MKEY_MW, | |
534fd7aa | 355 | MLX5_MKEY_INDIRECT_DEVX, |
aa8e08d2 AK |
356 | }; |
357 | ||
a606b0f6 | 358 | struct mlx5_core_mkey { |
e126ba97 EC |
359 | u64 iova; |
360 | u64 size; | |
361 | u32 key; | |
362 | u32 pd; | |
aa8e08d2 | 363 | u32 type; |
e126ba97 EC |
364 | }; |
365 | ||
d9aaed83 AK |
366 | #define MLX5_24BIT_MASK ((1 << 24) - 1) |
367 | ||
5903325a | 368 | enum mlx5_res_type { |
e2013b21 | 369 | MLX5_RES_QP = MLX5_EVENT_QUEUE_TYPE_QP, |
370 | MLX5_RES_RQ = MLX5_EVENT_QUEUE_TYPE_RQ, | |
371 | MLX5_RES_SQ = MLX5_EVENT_QUEUE_TYPE_SQ, | |
372 | MLX5_RES_SRQ = 3, | |
373 | MLX5_RES_XSRQ = 4, | |
5b3ec3fc | 374 | MLX5_RES_XRQ = 5, |
57cda166 | 375 | MLX5_RES_DCT = MLX5_EVENT_QUEUE_TYPE_DCT, |
5903325a EC |
376 | }; |
377 | ||
378 | struct mlx5_core_rsc_common { | |
379 | enum mlx5_res_type res; | |
94f3e14e | 380 | refcount_t refcount; |
5903325a EC |
381 | struct completion free; |
382 | }; | |
383 | ||
a6d51b68 | 384 | struct mlx5_uars_page { |
e126ba97 | 385 | void __iomem *map; |
a6d51b68 EC |
386 | bool wc; |
387 | u32 index; | |
388 | struct list_head list; | |
389 | unsigned int bfregs; | |
390 | unsigned long *reg_bitmap; /* for non fast path bf regs */ | |
391 | unsigned long *fp_bitmap; | |
392 | unsigned int reg_avail; | |
393 | unsigned int fp_avail; | |
394 | struct kref ref_count; | |
395 | struct mlx5_core_dev *mdev; | |
e126ba97 EC |
396 | }; |
397 | ||
a6d51b68 EC |
398 | struct mlx5_bfreg_head { |
399 | /* protect blue flame registers allocations */ | |
400 | struct mutex lock; | |
401 | struct list_head list; | |
402 | }; | |
403 | ||
404 | struct mlx5_bfreg_data { | |
405 | struct mlx5_bfreg_head reg_head; | |
406 | struct mlx5_bfreg_head wc_head; | |
407 | }; | |
408 | ||
409 | struct mlx5_sq_bfreg { | |
410 | void __iomem *map; | |
411 | struct mlx5_uars_page *up; | |
412 | bool wc; | |
413 | u32 index; | |
414 | unsigned int offset; | |
415 | }; | |
e126ba97 EC |
416 | |
417 | struct mlx5_core_health { | |
418 | struct health_buffer __iomem *health; | |
419 | __be32 __iomem *health_counter; | |
420 | struct timer_list timer; | |
e126ba97 EC |
421 | u32 prev; |
422 | int miss_counter; | |
d1bf0e2c | 423 | u8 synd; |
63cbc552 | 424 | u32 fatal_error; |
8b9d8baa | 425 | u32 crdump_size; |
05ac2c0b MHY |
426 | /* wq spinlock to synchronize draining */ |
427 | spinlock_t wq_lock; | |
ac6ea6e8 | 428 | struct workqueue_struct *wq; |
05ac2c0b | 429 | unsigned long flags; |
b3bd076f | 430 | struct work_struct fatal_report_work; |
d1bf0e2c | 431 | struct work_struct report_work; |
04c0c1ab | 432 | struct delayed_work recover_work; |
1e34f3ef | 433 | struct devlink_health_reporter *fw_reporter; |
96c82cdf | 434 | struct devlink_health_reporter *fw_fatal_reporter; |
e126ba97 EC |
435 | }; |
436 | ||
e126ba97 | 437 | struct mlx5_qp_table { |
451be51c | 438 | struct notifier_block nb; |
221c14f3 | 439 | |
e126ba97 EC |
440 | /* protect radix tree |
441 | */ | |
442 | spinlock_t lock; | |
443 | struct radix_tree_root tree; | |
444 | }; | |
445 | ||
fc50db98 EC |
446 | struct mlx5_vf_context { |
447 | int enabled; | |
7ecf6d8f BW |
448 | u64 port_guid; |
449 | u64 node_guid; | |
4bbd4923 DG |
450 | /* Valid bits are used to validate administrative guid only. |
451 | * Enabled after ndo_set_vf_guid | |
452 | */ | |
453 | u8 port_guid_valid:1; | |
454 | u8 node_guid_valid:1; | |
7ecf6d8f | 455 | enum port_state_policy policy; |
fc50db98 EC |
456 | }; |
457 | ||
458 | struct mlx5_core_sriov { | |
459 | struct mlx5_vf_context *vfs_ctx; | |
460 | int num_vfs; | |
86eec50b | 461 | u16 max_vfs; |
fc50db98 EC |
462 | }; |
463 | ||
558101f1 GT |
464 | struct mlx5_fc_pool { |
465 | struct mlx5_core_dev *dev; | |
466 | struct mutex pool_lock; /* protects pool lists */ | |
467 | struct list_head fully_used; | |
468 | struct list_head partially_used; | |
469 | struct list_head unused; | |
470 | int available_fcs; | |
471 | int used_fcs; | |
472 | int threshold; | |
473 | }; | |
474 | ||
43a335e0 | 475 | struct mlx5_fc_stats { |
12d6066c VB |
476 | spinlock_t counters_idr_lock; /* protects counters_idr */ |
477 | struct idr counters_idr; | |
9aff93d7 | 478 | struct list_head counters; |
83033688 | 479 | struct llist_head addlist; |
6e5e2283 | 480 | struct llist_head dellist; |
43a335e0 AV |
481 | |
482 | struct workqueue_struct *wq; | |
483 | struct delayed_work work; | |
484 | unsigned long next_query; | |
f6dfb4c3 | 485 | unsigned long sampling_interval; /* jiffies */ |
6f06e04b | 486 | u32 *bulk_query_out; |
558101f1 | 487 | struct mlx5_fc_pool fc_pool; |
43a335e0 AV |
488 | }; |
489 | ||
69c1280b | 490 | struct mlx5_events; |
eeb66cdb | 491 | struct mlx5_mpfs; |
073bb189 | 492 | struct mlx5_eswitch; |
7907f23a | 493 | struct mlx5_lag; |
fadd59fc | 494 | struct mlx5_devcom; |
f2f3df55 | 495 | struct mlx5_eq_table; |
561aa15a | 496 | struct mlx5_irq_table; |
073bb189 | 497 | |
05d3ac97 BW |
498 | struct mlx5_rate_limit { |
499 | u32 rate; | |
500 | u32 max_burst_sz; | |
501 | u16 typical_pkt_sz; | |
502 | }; | |
503 | ||
1466cc5b | 504 | struct mlx5_rl_entry { |
1326034b YH |
505 | u8 rl_raw[MLX5_ST_SZ_BYTES(set_pp_rate_limit_context)]; |
506 | u16 index; | |
507 | u64 refcount; | |
508 | u16 uid; | |
509 | u8 dedicated : 1; | |
1466cc5b YP |
510 | }; |
511 | ||
512 | struct mlx5_rl_table { | |
513 | /* protect rate limit table */ | |
514 | struct mutex rl_lock; | |
515 | u16 max_size; | |
516 | u32 max_rate; | |
517 | u32 min_rate; | |
518 | struct mlx5_rl_entry *rl_entry; | |
519 | }; | |
520 | ||
80f09dfc MG |
521 | struct mlx5_core_roce { |
522 | struct mlx5_flow_table *ft; | |
523 | struct mlx5_flow_group *fg; | |
524 | struct mlx5_flow_handle *allow_rule; | |
525 | }; | |
526 | ||
e126ba97 | 527 | struct mlx5_priv { |
561aa15a YA |
528 | /* IRQ table valid only for real pci devices PF or VF */ |
529 | struct mlx5_irq_table *irq_table; | |
f2f3df55 | 530 | struct mlx5_eq_table *eq_table; |
e126ba97 EC |
531 | |
532 | /* pages stuff */ | |
0cf53c12 | 533 | struct mlx5_nb pg_nb; |
e126ba97 EC |
534 | struct workqueue_struct *pg_wq; |
535 | struct rb_root page_root; | |
536 | int fw_pages; | |
6aec21f6 | 537 | atomic_t reg_pages; |
bf0bf77f | 538 | struct list_head free_list; |
fc50db98 | 539 | int vfs_pages; |
591905ba | 540 | int peer_pf_pages; |
e126ba97 EC |
541 | |
542 | struct mlx5_core_health health; | |
543 | ||
e126ba97 EC |
544 | /* start: qp staff */ |
545 | struct mlx5_qp_table qp_table; | |
546 | struct dentry *qp_debugfs; | |
547 | struct dentry *eq_debugfs; | |
548 | struct dentry *cq_debugfs; | |
549 | struct dentry *cmdif_debugfs; | |
550 | /* end: qp staff */ | |
551 | ||
e126ba97 | 552 | /* start: alloc staff */ |
311c7c71 SM |
553 | /* protect buffer alocation according to numa node */ |
554 | struct mutex alloc_mutex; | |
555 | int numa_node; | |
556 | ||
e126ba97 EC |
557 | struct mutex pgdir_mutex; |
558 | struct list_head pgdir_list; | |
559 | /* end: alloc staff */ | |
560 | struct dentry *dbg_root; | |
561 | ||
9603b61d JM |
562 | struct list_head dev_list; |
563 | struct list_head ctx_list; | |
564 | spinlock_t ctx_lock; | |
02039fb6 | 565 | struct mlx5_events *events; |
97834eba | 566 | |
fba53f7b | 567 | struct mlx5_flow_steering *steering; |
eeb66cdb | 568 | struct mlx5_mpfs *mpfs; |
073bb189 | 569 | struct mlx5_eswitch *eswitch; |
fc50db98 | 570 | struct mlx5_core_sriov sriov; |
7907f23a | 571 | struct mlx5_lag *lag; |
fadd59fc | 572 | struct mlx5_devcom *devcom; |
80f09dfc | 573 | struct mlx5_core_roce roce; |
43a335e0 | 574 | struct mlx5_fc_stats fc_stats; |
1466cc5b | 575 | struct mlx5_rl_table rl_table; |
d4eb4cd7 | 576 | |
a6d51b68 | 577 | struct mlx5_bfreg_data bfregs; |
01187175 | 578 | struct mlx5_uars_page *uar; |
e126ba97 EC |
579 | }; |
580 | ||
89d44f0a | 581 | enum mlx5_device_state { |
3e5b72ac | 582 | MLX5_DEVICE_STATE_UNINITIALIZED, |
89d44f0a MD |
583 | MLX5_DEVICE_STATE_UP, |
584 | MLX5_DEVICE_STATE_INTERNAL_ERROR, | |
585 | }; | |
586 | ||
587 | enum mlx5_interface_state { | |
b3cb5388 | 588 | MLX5_INTERFACE_STATE_UP = BIT(0), |
89d44f0a MD |
589 | }; |
590 | ||
591 | enum mlx5_pci_status { | |
592 | MLX5_PCI_STATUS_DISABLED, | |
593 | MLX5_PCI_STATUS_ENABLED, | |
594 | }; | |
595 | ||
d9aaed83 AK |
596 | enum mlx5_pagefault_type_flags { |
597 | MLX5_PFAULT_REQUESTOR = 1 << 0, | |
598 | MLX5_PFAULT_WRITE = 1 << 1, | |
599 | MLX5_PFAULT_RDMA = 1 << 2, | |
600 | }; | |
601 | ||
b50d292b | 602 | struct mlx5_td { |
80a2a902 YA |
603 | /* protects tirs list changes while tirs refresh */ |
604 | struct mutex list_lock; | |
b50d292b HHZ |
605 | struct list_head tirs_list; |
606 | u32 tdn; | |
607 | }; | |
608 | ||
609 | struct mlx5e_resources { | |
b50d292b HHZ |
610 | u32 pdn; |
611 | struct mlx5_td td; | |
612 | struct mlx5_core_mkey mkey; | |
aff26157 | 613 | struct mlx5_sq_bfreg bfreg; |
b50d292b HHZ |
614 | }; |
615 | ||
c9b9dcb4 AL |
616 | enum mlx5_sw_icm_type { |
617 | MLX5_SW_ICM_TYPE_STEERING, | |
618 | MLX5_SW_ICM_TYPE_HEADER_MODIFY, | |
619 | }; | |
620 | ||
52ec462e IT |
621 | #define MLX5_MAX_RESERVED_GIDS 8 |
622 | ||
623 | struct mlx5_rsvd_gids { | |
624 | unsigned int start; | |
625 | unsigned int count; | |
626 | struct ida ida; | |
627 | }; | |
628 | ||
7c39afb3 FD |
629 | #define MAX_PIN_NUM 8 |
630 | struct mlx5_pps { | |
631 | u8 pin_caps[MAX_PIN_NUM]; | |
632 | struct work_struct out_work; | |
633 | u64 start[MAX_PIN_NUM]; | |
634 | u8 enabled; | |
635 | }; | |
636 | ||
637 | struct mlx5_clock { | |
41069256 SM |
638 | struct mlx5_core_dev *mdev; |
639 | struct mlx5_nb pps_nb; | |
64109f1d | 640 | seqlock_t lock; |
7c39afb3 FD |
641 | struct cyclecounter cycles; |
642 | struct timecounter tc; | |
643 | struct hwtstamp_config hwtstamp_config; | |
644 | u32 nominal_c_mult; | |
645 | unsigned long overflow_period; | |
646 | struct delayed_work overflow_work; | |
647 | struct ptp_clock *ptp; | |
648 | struct ptp_clock_info ptp_info; | |
649 | struct mlx5_pps pps_info; | |
650 | }; | |
651 | ||
c9b9dcb4 | 652 | struct mlx5_dm; |
f53aaa31 | 653 | struct mlx5_fw_tracer; |
358aa5ce | 654 | struct mlx5_vxlan; |
0ccc171e | 655 | struct mlx5_geneve; |
87175120 | 656 | struct mlx5_hv_vhca; |
f53aaa31 | 657 | |
c9b9dcb4 AL |
658 | #define MLX5_LOG_SW_ICM_BLOCK_SIZE(dev) (MLX5_CAP_DEV_MEM(dev, log_sw_icm_alloc_granularity)) |
659 | #define MLX5_SW_ICM_BLOCK_SIZE(dev) (1 << MLX5_LOG_SW_ICM_BLOCK_SIZE(dev)) | |
660 | ||
e126ba97 | 661 | struct mlx5_core_dev { |
27b942fb | 662 | struct device *device; |
386e75af | 663 | enum mlx5_coredev_type coredev_type; |
e126ba97 | 664 | struct pci_dev *pdev; |
89d44f0a MD |
665 | /* sync pci state */ |
666 | struct mutex pci_status_mutex; | |
667 | enum mlx5_pci_status pci_status; | |
e126ba97 EC |
668 | u8 rev_id; |
669 | char board_id[MLX5_BOARD_ID_LEN]; | |
670 | struct mlx5_cmd cmd; | |
938fe83c | 671 | struct mlx5_port_caps port_caps[MLX5_MAX_PORTS]; |
71862561 | 672 | struct { |
701052c5 GP |
673 | u32 hca_cur[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; |
674 | u32 hca_max[MLX5_CAP_NUM][MLX5_UN_SZ_DW(hca_cap_union)]; | |
71862561 | 675 | u32 pcam[MLX5_ST_SZ_DW(pcam_reg)]; |
932ef155 | 676 | u32 mcam[MLX5_MCAM_REGS_NUM][MLX5_ST_SZ_DW(mcam_reg)]; |
99d3cd27 | 677 | u32 fpga[MLX5_ST_SZ_DW(fpga_cap)]; |
c02762eb | 678 | u32 qcam[MLX5_ST_SZ_DW(qcam_reg)]; |
591905ba | 679 | u8 embedded_cpu; |
71862561 | 680 | } caps; |
59c9d35e | 681 | u64 sys_image_guid; |
e126ba97 EC |
682 | phys_addr_t iseg_base; |
683 | struct mlx5_init_seg __iomem *iseg; | |
aa8106f1 | 684 | phys_addr_t bar_addr; |
89d44f0a MD |
685 | enum mlx5_device_state state; |
686 | /* sync interface state */ | |
687 | struct mutex intf_state_mutex; | |
5fc7197d | 688 | unsigned long intf_state; |
e126ba97 EC |
689 | struct mlx5_priv priv; |
690 | struct mlx5_profile *profile; | |
691 | atomic_t num_qps; | |
f62b8bb8 | 692 | u32 issi; |
b50d292b | 693 | struct mlx5e_resources mlx5e_res; |
c9b9dcb4 | 694 | struct mlx5_dm *dm; |
358aa5ce | 695 | struct mlx5_vxlan *vxlan; |
0ccc171e | 696 | struct mlx5_geneve *geneve; |
52ec462e IT |
697 | struct { |
698 | struct mlx5_rsvd_gids reserved_gids; | |
734dc065 | 699 | u32 roce_en; |
52ec462e | 700 | } roce; |
e29341fb IT |
701 | #ifdef CONFIG_MLX5_FPGA |
702 | struct mlx5_fpga_device *fpga; | |
5a7b27eb | 703 | #endif |
7c39afb3 | 704 | struct mlx5_clock clock; |
24d33d2c | 705 | struct mlx5_ib_clock_info *clock_info; |
f53aaa31 | 706 | struct mlx5_fw_tracer *tracer; |
12206b17 | 707 | struct mlx5_rsc_dump *rsc_dump; |
b25bbc2f | 708 | u32 vsc_addr; |
87175120 | 709 | struct mlx5_hv_vhca *hv_vhca; |
e126ba97 EC |
710 | }; |
711 | ||
712 | struct mlx5_db { | |
713 | __be32 *db; | |
714 | union { | |
715 | struct mlx5_db_pgdir *pgdir; | |
716 | struct mlx5_ib_user_db_page *user_page; | |
717 | } u; | |
718 | dma_addr_t dma; | |
719 | int index; | |
720 | }; | |
721 | ||
e126ba97 EC |
722 | enum { |
723 | MLX5_COMP_EQ_SIZE = 1024, | |
724 | }; | |
725 | ||
adb0c954 SM |
726 | enum { |
727 | MLX5_PTYS_IB = 1 << 0, | |
728 | MLX5_PTYS_EN = 1 << 2, | |
729 | }; | |
730 | ||
e126ba97 EC |
731 | typedef void (*mlx5_cmd_cbk_t)(int status, void *context); |
732 | ||
73dd3a48 MHY |
733 | enum { |
734 | MLX5_CMD_ENT_STATE_PENDING_COMP, | |
735 | }; | |
736 | ||
e126ba97 | 737 | struct mlx5_cmd_work_ent { |
73dd3a48 | 738 | unsigned long state; |
e126ba97 EC |
739 | struct mlx5_cmd_msg *in; |
740 | struct mlx5_cmd_msg *out; | |
746b5583 EC |
741 | void *uout; |
742 | int uout_size; | |
e126ba97 | 743 | mlx5_cmd_cbk_t callback; |
65ee6708 | 744 | struct delayed_work cb_timeout_work; |
e126ba97 | 745 | void *context; |
746b5583 | 746 | int idx; |
17d00e83 | 747 | struct completion handling; |
e126ba97 EC |
748 | struct completion done; |
749 | struct mlx5_cmd *cmd; | |
750 | struct work_struct work; | |
751 | struct mlx5_cmd_layout *lay; | |
752 | int ret; | |
753 | int page_queue; | |
754 | u8 status; | |
755 | u8 token; | |
14a70046 TG |
756 | u64 ts1; |
757 | u64 ts2; | |
746b5583 | 758 | u16 op; |
4525abea | 759 | bool polling; |
e126ba97 EC |
760 | }; |
761 | ||
762 | struct mlx5_pas { | |
763 | u64 pa; | |
764 | u8 log_sz; | |
765 | }; | |
766 | ||
707c4602 MD |
767 | enum phy_port_state { |
768 | MLX5_AAA_111 | |
769 | }; | |
770 | ||
771 | struct mlx5_hca_vport_context { | |
772 | u32 field_select; | |
773 | bool sm_virt_aware; | |
774 | bool has_smi; | |
775 | bool has_raw; | |
776 | enum port_state_policy policy; | |
777 | enum phy_port_state phys_state; | |
778 | enum ib_port_state vport_state; | |
779 | u8 port_physical_state; | |
780 | u64 sys_image_guid; | |
781 | u64 port_guid; | |
782 | u64 node_guid; | |
783 | u32 cap_mask1; | |
784 | u32 cap_mask1_perm; | |
4106a758 MG |
785 | u16 cap_mask2; |
786 | u16 cap_mask2_perm; | |
707c4602 MD |
787 | u16 lid; |
788 | u8 init_type_reply; /* bitmask: see ib spec 14.2.5.6 InitTypeReply */ | |
789 | u8 lmc; | |
790 | u8 subnet_timeout; | |
791 | u16 sm_lid; | |
792 | u8 sm_sl; | |
793 | u16 qkey_violation_counter; | |
794 | u16 pkey_violation_counter; | |
795 | bool grh_required; | |
796 | }; | |
797 | ||
388ca8be | 798 | static inline void *mlx5_buf_offset(struct mlx5_frag_buf *buf, int offset) |
e126ba97 | 799 | { |
388ca8be | 800 | return buf->frags->buf + offset; |
e126ba97 EC |
801 | } |
802 | ||
e126ba97 EC |
803 | #define STRUCT_FIELD(header, field) \ |
804 | .struct_offset_bytes = offsetof(struct ib_unpacked_ ## header, field), \ | |
805 | .struct_size_bytes = sizeof((struct ib_unpacked_ ## header *)0)->field | |
806 | ||
e126ba97 EC |
807 | static inline struct mlx5_core_dev *pci2mlx5_core_dev(struct pci_dev *pdev) |
808 | { | |
809 | return pci_get_drvdata(pdev); | |
810 | } | |
811 | ||
812 | extern struct dentry *mlx5_debugfs_root; | |
813 | ||
814 | static inline u16 fw_rev_maj(struct mlx5_core_dev *dev) | |
815 | { | |
816 | return ioread32be(&dev->iseg->fw_rev) & 0xffff; | |
817 | } | |
818 | ||
819 | static inline u16 fw_rev_min(struct mlx5_core_dev *dev) | |
820 | { | |
821 | return ioread32be(&dev->iseg->fw_rev) >> 16; | |
822 | } | |
823 | ||
824 | static inline u16 fw_rev_sub(struct mlx5_core_dev *dev) | |
825 | { | |
826 | return ioread32be(&dev->iseg->cmdif_rev_fw_sub) & 0xffff; | |
827 | } | |
828 | ||
829 | static inline u16 cmdif_rev(struct mlx5_core_dev *dev) | |
830 | { | |
831 | return ioread32be(&dev->iseg->cmdif_rev_fw_sub) >> 16; | |
832 | } | |
833 | ||
3bcdb17a SG |
834 | static inline u32 mlx5_base_mkey(const u32 key) |
835 | { | |
836 | return key & 0xffffff00u; | |
837 | } | |
838 | ||
4972e6fa TT |
839 | static inline void mlx5_init_fbc_offset(struct mlx5_buf_list *frags, |
840 | u8 log_stride, u8 log_sz, | |
a0903622 | 841 | u16 strides_offset, |
d7037ad7 | 842 | struct mlx5_frag_buf_ctrl *fbc) |
388ca8be | 843 | { |
4972e6fa | 844 | fbc->frags = frags; |
3a2f7033 TT |
845 | fbc->log_stride = log_stride; |
846 | fbc->log_sz = log_sz; | |
388ca8be YC |
847 | fbc->sz_m1 = (1 << fbc->log_sz) - 1; |
848 | fbc->log_frag_strides = PAGE_SHIFT - fbc->log_stride; | |
849 | fbc->frag_sz_m1 = (1 << fbc->log_frag_strides) - 1; | |
d7037ad7 TT |
850 | fbc->strides_offset = strides_offset; |
851 | } | |
852 | ||
4972e6fa TT |
853 | static inline void mlx5_init_fbc(struct mlx5_buf_list *frags, |
854 | u8 log_stride, u8 log_sz, | |
d7037ad7 TT |
855 | struct mlx5_frag_buf_ctrl *fbc) |
856 | { | |
4972e6fa | 857 | mlx5_init_fbc_offset(frags, log_stride, log_sz, 0, fbc); |
3a2f7033 TT |
858 | } |
859 | ||
388ca8be YC |
860 | static inline void *mlx5_frag_buf_get_wqe(struct mlx5_frag_buf_ctrl *fbc, |
861 | u32 ix) | |
862 | { | |
d7037ad7 TT |
863 | unsigned int frag; |
864 | ||
865 | ix += fbc->strides_offset; | |
866 | frag = ix >> fbc->log_frag_strides; | |
388ca8be | 867 | |
4972e6fa | 868 | return fbc->frags[frag].buf + ((fbc->frag_sz_m1 & ix) << fbc->log_stride); |
388ca8be YC |
869 | } |
870 | ||
37fdffb2 TT |
871 | static inline u32 |
872 | mlx5_frag_buf_get_idx_last_contig_stride(struct mlx5_frag_buf_ctrl *fbc, u32 ix) | |
873 | { | |
874 | u32 last_frag_stride_idx = (ix + fbc->strides_offset) | fbc->frag_sz_m1; | |
875 | ||
876 | return min_t(u32, last_frag_stride_idx - fbc->strides_offset, fbc->sz_m1); | |
877 | } | |
878 | ||
d43b7007 EBE |
879 | enum { |
880 | CMD_ALLOWED_OPCODE_ALL, | |
881 | }; | |
882 | ||
e126ba97 EC |
883 | int mlx5_cmd_init(struct mlx5_core_dev *dev); |
884 | void mlx5_cmd_cleanup(struct mlx5_core_dev *dev); | |
885 | void mlx5_cmd_use_events(struct mlx5_core_dev *dev); | |
886 | void mlx5_cmd_use_polling(struct mlx5_core_dev *dev); | |
d43b7007 | 887 | void mlx5_cmd_allowed_opcode(struct mlx5_core_dev *dev, u16 opcode); |
c4f287c4 | 888 | |
e355477e JG |
889 | struct mlx5_async_ctx { |
890 | struct mlx5_core_dev *dev; | |
891 | atomic_t num_inflight; | |
892 | struct wait_queue_head wait; | |
893 | }; | |
894 | ||
895 | struct mlx5_async_work; | |
896 | ||
897 | typedef void (*mlx5_async_cbk_t)(int status, struct mlx5_async_work *context); | |
898 | ||
899 | struct mlx5_async_work { | |
900 | struct mlx5_async_ctx *ctx; | |
901 | mlx5_async_cbk_t user_callback; | |
902 | }; | |
903 | ||
904 | void mlx5_cmd_init_async_ctx(struct mlx5_core_dev *dev, | |
905 | struct mlx5_async_ctx *ctx); | |
906 | void mlx5_cmd_cleanup_async_ctx(struct mlx5_async_ctx *ctx); | |
907 | int mlx5_cmd_exec_cb(struct mlx5_async_ctx *ctx, void *in, int in_size, | |
908 | void *out, int out_size, mlx5_async_cbk_t callback, | |
909 | struct mlx5_async_work *work); | |
910 | ||
e126ba97 EC |
911 | int mlx5_cmd_exec(struct mlx5_core_dev *dev, void *in, int in_size, void *out, |
912 | int out_size); | |
4525abea MD |
913 | int mlx5_cmd_exec_polling(struct mlx5_core_dev *dev, void *in, int in_size, |
914 | void *out, int out_size); | |
c4f287c4 SM |
915 | void mlx5_cmd_mbox_status(void *out, u8 *status, u32 *syndrome); |
916 | ||
917 | int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type); | |
e126ba97 EC |
918 | int mlx5_cmd_alloc_uar(struct mlx5_core_dev *dev, u32 *uarn); |
919 | int mlx5_cmd_free_uar(struct mlx5_core_dev *dev, u32 uarn); | |
52c368dc | 920 | void mlx5_health_flush(struct mlx5_core_dev *dev); |
ac6ea6e8 EC |
921 | void mlx5_health_cleanup(struct mlx5_core_dev *dev); |
922 | int mlx5_health_init(struct mlx5_core_dev *dev); | |
e126ba97 | 923 | void mlx5_start_health_poll(struct mlx5_core_dev *dev); |
76d5581c | 924 | void mlx5_stop_health_poll(struct mlx5_core_dev *dev, bool disable_health); |
05ac2c0b | 925 | void mlx5_drain_health_wq(struct mlx5_core_dev *dev); |
0179720d | 926 | void mlx5_trigger_health_work(struct mlx5_core_dev *dev); |
388ca8be YC |
927 | int mlx5_buf_alloc(struct mlx5_core_dev *dev, |
928 | int size, struct mlx5_frag_buf *buf); | |
929 | void mlx5_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf); | |
1c1b5228 TT |
930 | int mlx5_frag_buf_alloc_node(struct mlx5_core_dev *dev, int size, |
931 | struct mlx5_frag_buf *buf, int node); | |
932 | void mlx5_frag_buf_free(struct mlx5_core_dev *dev, struct mlx5_frag_buf *buf); | |
e126ba97 EC |
933 | struct mlx5_cmd_mailbox *mlx5_alloc_cmd_mailbox_chain(struct mlx5_core_dev *dev, |
934 | gfp_t flags, int npages); | |
935 | void mlx5_free_cmd_mailbox_chain(struct mlx5_core_dev *dev, | |
936 | struct mlx5_cmd_mailbox *head); | |
a606b0f6 MB |
937 | int mlx5_core_create_mkey(struct mlx5_core_dev *dev, |
938 | struct mlx5_core_mkey *mkey, | |
ec22eb53 | 939 | u32 *in, int inlen); |
a606b0f6 MB |
940 | int mlx5_core_destroy_mkey(struct mlx5_core_dev *dev, |
941 | struct mlx5_core_mkey *mkey); | |
942 | int mlx5_core_query_mkey(struct mlx5_core_dev *dev, struct mlx5_core_mkey *mkey, | |
ec22eb53 | 943 | u32 *out, int outlen); |
e126ba97 EC |
944 | int mlx5_core_alloc_pd(struct mlx5_core_dev *dev, u32 *pdn); |
945 | int mlx5_core_dealloc_pd(struct mlx5_core_dev *dev, u32 pdn); | |
0cf53c12 | 946 | int mlx5_pagealloc_init(struct mlx5_core_dev *dev); |
e126ba97 | 947 | void mlx5_pagealloc_cleanup(struct mlx5_core_dev *dev); |
0cf53c12 | 948 | void mlx5_pagealloc_start(struct mlx5_core_dev *dev); |
e126ba97 EC |
949 | void mlx5_pagealloc_stop(struct mlx5_core_dev *dev); |
950 | void mlx5_core_req_pages_handler(struct mlx5_core_dev *dev, u16 func_id, | |
591905ba | 951 | s32 npages, bool ec_function); |
cd23b14b | 952 | int mlx5_satisfy_startup_pages(struct mlx5_core_dev *dev, int boot); |
e126ba97 EC |
953 | int mlx5_reclaim_startup_pages(struct mlx5_core_dev *dev); |
954 | void mlx5_register_debugfs(void); | |
955 | void mlx5_unregister_debugfs(void); | |
388ca8be YC |
956 | |
957 | void mlx5_fill_page_array(struct mlx5_frag_buf *buf, __be64 *pas); | |
1c1b5228 | 958 | void mlx5_fill_page_frag_array(struct mlx5_frag_buf *frag_buf, __be64 *pas); |
0b6e26ce DT |
959 | int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn, |
960 | unsigned int *irqn); | |
e126ba97 EC |
961 | int mlx5_core_attach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); |
962 | int mlx5_core_detach_mcg(struct mlx5_core_dev *dev, union ib_gid *mgid, u32 qpn); | |
963 | ||
9f818c8a | 964 | void mlx5_qp_debugfs_init(struct mlx5_core_dev *dev); |
e126ba97 EC |
965 | void mlx5_qp_debugfs_cleanup(struct mlx5_core_dev *dev); |
966 | int mlx5_core_access_reg(struct mlx5_core_dev *dev, void *data_in, | |
967 | int size_in, void *data_out, int size_out, | |
968 | u16 reg_num, int arg, int write); | |
adb0c954 | 969 | |
e126ba97 | 970 | int mlx5_db_alloc(struct mlx5_core_dev *dev, struct mlx5_db *db); |
311c7c71 SM |
971 | int mlx5_db_alloc_node(struct mlx5_core_dev *dev, struct mlx5_db *db, |
972 | int node); | |
e126ba97 EC |
973 | void mlx5_db_free(struct mlx5_core_dev *dev, struct mlx5_db *db); |
974 | ||
e126ba97 | 975 | const char *mlx5_command_str(int command); |
9f818c8a | 976 | void mlx5_cmdif_debugfs_init(struct mlx5_core_dev *dev); |
e126ba97 | 977 | void mlx5_cmdif_debugfs_cleanup(struct mlx5_core_dev *dev); |
3121e3c4 SG |
978 | int mlx5_core_create_psv(struct mlx5_core_dev *dev, u32 pdn, |
979 | int npsvs, u32 *sig_index); | |
980 | int mlx5_core_destroy_psv(struct mlx5_core_dev *dev, int psv_num); | |
5903325a | 981 | void mlx5_core_put_rsc(struct mlx5_core_rsc_common *common); |
e420f0c0 HE |
982 | int mlx5_query_odp_caps(struct mlx5_core_dev *dev, |
983 | struct mlx5_odp_caps *odp_caps); | |
1c64bf6f MY |
984 | int mlx5_core_query_ib_ppcnt(struct mlx5_core_dev *dev, |
985 | u8 port_num, void *out, size_t sz); | |
e126ba97 | 986 | |
1466cc5b YP |
987 | int mlx5_init_rl_table(struct mlx5_core_dev *dev); |
988 | void mlx5_cleanup_rl_table(struct mlx5_core_dev *dev); | |
05d3ac97 BW |
989 | int mlx5_rl_add_rate(struct mlx5_core_dev *dev, u16 *index, |
990 | struct mlx5_rate_limit *rl); | |
991 | void mlx5_rl_remove_rate(struct mlx5_core_dev *dev, struct mlx5_rate_limit *rl); | |
1466cc5b | 992 | bool mlx5_rl_is_in_range(struct mlx5_core_dev *dev, u32 rate); |
1326034b YH |
993 | int mlx5_rl_add_rate_raw(struct mlx5_core_dev *dev, void *rl_in, u16 uid, |
994 | bool dedicated_entry, u16 *index); | |
995 | void mlx5_rl_remove_rate_raw(struct mlx5_core_dev *dev, u16 index); | |
05d3ac97 BW |
996 | bool mlx5_rl_are_equal(struct mlx5_rate_limit *rl_0, |
997 | struct mlx5_rate_limit *rl_1); | |
a6d51b68 EC |
998 | int mlx5_alloc_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg, |
999 | bool map_wc, bool fast_path); | |
1000 | void mlx5_free_bfreg(struct mlx5_core_dev *mdev, struct mlx5_sq_bfreg *bfreg); | |
1466cc5b | 1001 | |
f2f3df55 SM |
1002 | unsigned int mlx5_comp_vectors_count(struct mlx5_core_dev *dev); |
1003 | struct cpumask * | |
1004 | mlx5_comp_irq_get_affinity_mask(struct mlx5_core_dev *dev, int vector); | |
52ec462e IT |
1005 | unsigned int mlx5_core_reserved_gids_count(struct mlx5_core_dev *dev); |
1006 | int mlx5_core_roce_gid_set(struct mlx5_core_dev *dev, unsigned int index, | |
1007 | u8 roce_version, u8 roce_l3_type, const u8 *gid, | |
cfe4e37f | 1008 | const u8 *mac, bool vlan, u16 vlan_id, u8 port_num); |
52ec462e | 1009 | |
e3297246 EC |
1010 | static inline int fw_initializing(struct mlx5_core_dev *dev) |
1011 | { | |
1012 | return ioread32be(&dev->iseg->initializing) >> 31; | |
1013 | } | |
1014 | ||
e126ba97 EC |
1015 | static inline u32 mlx5_mkey_to_idx(u32 mkey) |
1016 | { | |
1017 | return mkey >> 8; | |
1018 | } | |
1019 | ||
1020 | static inline u32 mlx5_idx_to_mkey(u32 mkey_idx) | |
1021 | { | |
1022 | return mkey_idx << 8; | |
1023 | } | |
1024 | ||
746b5583 EC |
1025 | static inline u8 mlx5_mkey_variant(u32 mkey) |
1026 | { | |
1027 | return mkey & 0xff; | |
1028 | } | |
1029 | ||
e126ba97 EC |
1030 | enum { |
1031 | MLX5_PROF_MASK_QP_SIZE = (u64)1 << 0, | |
c1868b82 | 1032 | MLX5_PROF_MASK_MR_CACHE = (u64)1 << 1, |
e126ba97 EC |
1033 | }; |
1034 | ||
1035 | enum { | |
8b7ff7f3 | 1036 | MR_CACHE_LAST_STD_ENTRY = 20, |
81713d37 AK |
1037 | MLX5_IMR_MTT_CACHE_ENTRY, |
1038 | MLX5_IMR_KSM_CACHE_ENTRY, | |
49780d42 | 1039 | MAX_MR_CACHE_ENTRIES |
e126ba97 EC |
1040 | }; |
1041 | ||
64613d94 SM |
1042 | enum { |
1043 | MLX5_INTERFACE_PROTOCOL_IB = 0, | |
1044 | MLX5_INTERFACE_PROTOCOL_ETH = 1, | |
1045 | }; | |
1046 | ||
9603b61d JM |
1047 | struct mlx5_interface { |
1048 | void * (*add)(struct mlx5_core_dev *dev); | |
1049 | void (*remove)(struct mlx5_core_dev *dev, void *context); | |
737a234b MHY |
1050 | int (*attach)(struct mlx5_core_dev *dev, void *context); |
1051 | void (*detach)(struct mlx5_core_dev *dev, void *context); | |
64613d94 | 1052 | int protocol; |
9603b61d JM |
1053 | struct list_head list; |
1054 | }; | |
1055 | ||
1056 | int mlx5_register_interface(struct mlx5_interface *intf); | |
1057 | void mlx5_unregister_interface(struct mlx5_interface *intf); | |
20902be4 SM |
1058 | int mlx5_notifier_register(struct mlx5_core_dev *dev, struct notifier_block *nb); |
1059 | int mlx5_notifier_unregister(struct mlx5_core_dev *dev, struct notifier_block *nb); | |
c0670781 YH |
1060 | int mlx5_eq_notifier_register(struct mlx5_core_dev *dev, struct mlx5_nb *nb); |
1061 | int mlx5_eq_notifier_unregister(struct mlx5_core_dev *dev, struct mlx5_nb *nb); | |
20902be4 | 1062 | |
211e6c80 | 1063 | int mlx5_core_query_vendor_id(struct mlx5_core_dev *mdev, u32 *vendor_id); |
9603b61d | 1064 | |
3bc34f3b AH |
1065 | int mlx5_cmd_create_vport_lag(struct mlx5_core_dev *dev); |
1066 | int mlx5_cmd_destroy_vport_lag(struct mlx5_core_dev *dev); | |
7c34ec19 AH |
1067 | bool mlx5_lag_is_roce(struct mlx5_core_dev *dev); |
1068 | bool mlx5_lag_is_sriov(struct mlx5_core_dev *dev); | |
724b509c | 1069 | bool mlx5_lag_is_multipath(struct mlx5_core_dev *dev); |
7907f23a | 1070 | bool mlx5_lag_is_active(struct mlx5_core_dev *dev); |
6a32047a | 1071 | struct net_device *mlx5_lag_get_roce_netdev(struct mlx5_core_dev *dev); |
71a0ff65 MD |
1072 | int mlx5_lag_query_cong_counters(struct mlx5_core_dev *dev, |
1073 | u64 *values, | |
1074 | int num_counters, | |
1075 | size_t *offsets); | |
01187175 EC |
1076 | struct mlx5_uars_page *mlx5_get_uars_page(struct mlx5_core_dev *mdev); |
1077 | void mlx5_put_uars_page(struct mlx5_core_dev *mdev, struct mlx5_uars_page *up); | |
c9b9dcb4 AL |
1078 | int mlx5_dm_sw_icm_alloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type, |
1079 | u64 length, u16 uid, phys_addr_t *addr, u32 *obj_id); | |
1080 | int mlx5_dm_sw_icm_dealloc(struct mlx5_core_dev *dev, enum mlx5_sw_icm_type type, | |
1081 | u64 length, u16 uid, phys_addr_t addr, u32 obj_id); | |
7907f23a | 1082 | |
f6a8a19b | 1083 | #ifdef CONFIG_MLX5_CORE_IPOIB |
693dfd5a ES |
1084 | struct net_device *mlx5_rdma_netdev_alloc(struct mlx5_core_dev *mdev, |
1085 | struct ib_device *ibdev, | |
1086 | const char *name, | |
1087 | void (*setup)(struct net_device *)); | |
693dfd5a | 1088 | #endif /* CONFIG_MLX5_CORE_IPOIB */ |
f6a8a19b DD |
1089 | int mlx5_rdma_rn_get_params(struct mlx5_core_dev *mdev, |
1090 | struct ib_device *device, | |
1091 | struct rdma_netdev_alloc_params *params); | |
693dfd5a | 1092 | |
e126ba97 EC |
1093 | struct mlx5_profile { |
1094 | u64 mask; | |
f241e749 | 1095 | u8 log_max_qp; |
e126ba97 EC |
1096 | struct { |
1097 | int size; | |
1098 | int limit; | |
1099 | } mr_cache[MAX_MR_CACHE_ENTRIES]; | |
1100 | }; | |
1101 | ||
fc50db98 EC |
1102 | enum { |
1103 | MLX5_PCI_DEV_IS_VF = 1 << 0, | |
1104 | }; | |
1105 | ||
2752b823 | 1106 | static inline bool mlx5_core_is_pf(const struct mlx5_core_dev *dev) |
fc50db98 | 1107 | { |
386e75af | 1108 | return dev->coredev_type == MLX5_COREDEV_PF; |
fc50db98 EC |
1109 | } |
1110 | ||
e53a9d26 PP |
1111 | static inline bool mlx5_core_is_vf(const struct mlx5_core_dev *dev) |
1112 | { | |
1113 | return dev->coredev_type == MLX5_COREDEV_VF; | |
1114 | } | |
1115 | ||
591905ba BW |
1116 | static inline bool mlx5_core_is_ecpf(struct mlx5_core_dev *dev) |
1117 | { | |
1118 | return dev->caps.embedded_cpu; | |
1119 | } | |
1120 | ||
2752b823 PP |
1121 | static inline bool |
1122 | mlx5_core_is_ecpf_esw_manager(const struct mlx5_core_dev *dev) | |
7f0d11c7 BW |
1123 | { |
1124 | return dev->caps.embedded_cpu && MLX5_CAP_GEN(dev, eswitch_manager); | |
1125 | } | |
1126 | ||
2752b823 | 1127 | static inline bool mlx5_ecpf_vport_exists(const struct mlx5_core_dev *dev) |
81cd229c BW |
1128 | { |
1129 | return mlx5_core_is_pf(dev) && MLX5_CAP_ESW(dev, ecpf_vport_exists); | |
1130 | } | |
1131 | ||
2752b823 | 1132 | static inline u16 mlx5_core_max_vfs(const struct mlx5_core_dev *dev) |
feb39369 | 1133 | { |
86eec50b | 1134 | return dev->priv.sriov.max_vfs; |
feb39369 BW |
1135 | } |
1136 | ||
707c4602 MD |
1137 | static inline int mlx5_get_gid_table_len(u16 param) |
1138 | { | |
1139 | if (param > 4) { | |
1140 | pr_warn("gid table length is zero\n"); | |
1141 | return 0; | |
1142 | } | |
1143 | ||
1144 | return 8 * (1 << param); | |
1145 | } | |
1146 | ||
1466cc5b YP |
1147 | static inline bool mlx5_rl_is_supported(struct mlx5_core_dev *dev) |
1148 | { | |
1149 | return !!(dev->priv.rl_table.max_size); | |
1150 | } | |
1151 | ||
32f69e4b DJ |
1152 | static inline int mlx5_core_is_mp_slave(struct mlx5_core_dev *dev) |
1153 | { | |
1154 | return MLX5_CAP_GEN(dev, affiliate_nic_vport_criteria) && | |
1155 | MLX5_CAP_GEN(dev, num_vhca_ports) <= 1; | |
1156 | } | |
1157 | ||
1158 | static inline int mlx5_core_is_mp_master(struct mlx5_core_dev *dev) | |
1159 | { | |
1160 | return MLX5_CAP_GEN(dev, num_vhca_ports) > 1; | |
1161 | } | |
1162 | ||
1163 | static inline int mlx5_core_mp_enabled(struct mlx5_core_dev *dev) | |
1164 | { | |
1165 | return mlx5_core_is_mp_slave(dev) || | |
1166 | mlx5_core_is_mp_master(dev); | |
1167 | } | |
1168 | ||
7fd8aefb DJ |
1169 | static inline int mlx5_core_native_port_num(struct mlx5_core_dev *dev) |
1170 | { | |
32f69e4b DJ |
1171 | if (!mlx5_core_mp_enabled(dev)) |
1172 | return 1; | |
1173 | ||
1174 | return MLX5_CAP_GEN(dev, native_port_num); | |
7fd8aefb DJ |
1175 | } |
1176 | ||
020446e0 EC |
1177 | enum { |
1178 | MLX5_TRIGGERED_CMD_COMP = (u64)1 << 32, | |
1179 | }; | |
1180 | ||
cc9defcb MG |
1181 | static inline bool mlx5_is_roce_enabled(struct mlx5_core_dev *dev) |
1182 | { | |
1183 | struct devlink *devlink = priv_to_devlink(dev); | |
1184 | union devlink_param_value val; | |
1185 | ||
1186 | devlink_param_driverinit_value_get(devlink, | |
1187 | DEVLINK_PARAM_GENERIC_ID_ENABLE_ROCE, | |
1188 | &val); | |
1189 | return val.vbool; | |
1190 | } | |
1191 | ||
e126ba97 | 1192 | #endif /* MLX5_DRIVER_H */ |