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net/mlx5: Introducing E-Switch and l2 table
[mirror_ubuntu-artful-kernel.git] / include / linux / mlx5 / mlx5_ifc.h
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d29b796a 1/*
e281682b 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
d29b796a
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
e281682b 31*/
d29b796a
EC		 32#ifndef MLX5_IFC_H
33#define MLX5_IFC_H
34
e281682b
SM		 35enum {
36 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
37 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
38 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
39 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
40 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
41 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
42 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
43 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
44 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
45 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
46 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
47 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
48 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
49 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
50 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
51 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
52 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
53 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
54 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
55 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
56 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
57 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
58 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
59 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb
60};
61
62enum {
63 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
64 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
65 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
66 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
67};
68
d29b796a
EC		 69enum {
70 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
71 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
72 MLX5_CMD_OP_INIT_HCA = 0x102,
73 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
74 MLX5_CMD_OP_ENABLE_HCA = 0x104,
75 MLX5_CMD_OP_DISABLE_HCA = 0x105,
76 MLX5_CMD_OP_QUERY_PAGES = 0x107,
77 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
78 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
e281682b
SM		 79 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
80 MLX5_CMD_OP_SET_ISSI = 0x10b,
d29b796a
EC		 81 MLX5_CMD_OP_CREATE_MKEY = 0x200,
82 MLX5_CMD_OP_QUERY_MKEY = 0x201,
83 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
84 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
85 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
86 MLX5_CMD_OP_CREATE_EQ = 0x301,
87 MLX5_CMD_OP_DESTROY_EQ = 0x302,
88 MLX5_CMD_OP_QUERY_EQ = 0x303,
89 MLX5_CMD_OP_GEN_EQE = 0x304,
90 MLX5_CMD_OP_CREATE_CQ = 0x400,
91 MLX5_CMD_OP_DESTROY_CQ = 0x401,
92 MLX5_CMD_OP_QUERY_CQ = 0x402,
93 MLX5_CMD_OP_MODIFY_CQ = 0x403,
94 MLX5_CMD_OP_CREATE_QP = 0x500,
95 MLX5_CMD_OP_DESTROY_QP = 0x501,
96 MLX5_CMD_OP_RST2INIT_QP = 0x502,
97 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
98 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
99 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
100 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
101 MLX5_CMD_OP_2ERR_QP = 0x507,
102 MLX5_CMD_OP_2RST_QP = 0x50a,
103 MLX5_CMD_OP_QUERY_QP = 0x50b,
e281682b 104 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
d29b796a
EC		 105 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
106 MLX5_CMD_OP_CREATE_PSV = 0x600,
107 MLX5_CMD_OP_DESTROY_PSV = 0x601,
108 MLX5_CMD_OP_CREATE_SRQ = 0x700,
109 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
110 MLX5_CMD_OP_QUERY_SRQ = 0x702,
111 MLX5_CMD_OP_ARM_RQ = 0x703,
e281682b
SM		 112 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
113 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
114 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
115 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
d29b796a
EC		 116 MLX5_CMD_OP_CREATE_DCT = 0x710,
117 MLX5_CMD_OP_DESTROY_DCT = 0x711,
118 MLX5_CMD_OP_DRAIN_DCT = 0x712,
119 MLX5_CMD_OP_QUERY_DCT = 0x713,
120 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
121 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
122 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
123 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
124 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
125 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
126 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
e281682b 127 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
d29b796a 128 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
e281682b
SM		 129 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
130 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
131 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
132 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
d29b796a
EC		 133 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
134 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
135 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
136 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
137 MLX5_CMD_OP_ALLOC_PD = 0x800,
138 MLX5_CMD_OP_DEALLOC_PD = 0x801,
139 MLX5_CMD_OP_ALLOC_UAR = 0x802,
140 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
141 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
142 MLX5_CMD_OP_ACCESS_REG = 0x805,
143 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
e281682b 144 MLX5_CMD_OP_DETTACH_FROM_MCG = 0x807,
d29b796a
EC		 145 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
146 MLX5_CMD_OP_MAD_IFC = 0x50d,
147 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
148 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
149 MLX5_CMD_OP_NOP = 0x80d,
150 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
151 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
e281682b
SM		 152 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
153 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
154 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
155 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
156 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
157 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
158 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
159 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
160 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
161 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
162 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
163 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
d29b796a
EC		 164 MLX5_CMD_OP_CREATE_TIR = 0x900,
165 MLX5_CMD_OP_MODIFY_TIR = 0x901,
166 MLX5_CMD_OP_DESTROY_TIR = 0x902,
167 MLX5_CMD_OP_QUERY_TIR = 0x903,
d29b796a
EC		 168 MLX5_CMD_OP_CREATE_SQ = 0x904,
169 MLX5_CMD_OP_MODIFY_SQ = 0x905,
170 MLX5_CMD_OP_DESTROY_SQ = 0x906,
171 MLX5_CMD_OP_QUERY_SQ = 0x907,
172 MLX5_CMD_OP_CREATE_RQ = 0x908,
173 MLX5_CMD_OP_MODIFY_RQ = 0x909,
174 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
175 MLX5_CMD_OP_QUERY_RQ = 0x90b,
176 MLX5_CMD_OP_CREATE_RMP = 0x90c,
177 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
178 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
179 MLX5_CMD_OP_QUERY_RMP = 0x90f,
e281682b
SM		 180 MLX5_CMD_OP_CREATE_TIS = 0x912,
181 MLX5_CMD_OP_MODIFY_TIS = 0x913,
182 MLX5_CMD_OP_DESTROY_TIS = 0x914,
183 MLX5_CMD_OP_QUERY_TIS = 0x915,
184 MLX5_CMD_OP_CREATE_RQT = 0x916,
185 MLX5_CMD_OP_MODIFY_RQT = 0x917,
186 MLX5_CMD_OP_DESTROY_RQT = 0x918,
187 MLX5_CMD_OP_QUERY_RQT = 0x919,
188 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
189 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
190 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
191 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
192 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
193 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
194 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
195 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
196 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938
197};
198
199struct mlx5_ifc_flow_table_fields_supported_bits {
200 u8 outer_dmac[0x1];
201 u8 outer_smac[0x1];
202 u8 outer_ether_type[0x1];
203 u8 reserved_0[0x1];
204 u8 outer_first_prio[0x1];
205 u8 outer_first_cfi[0x1];
206 u8 outer_first_vid[0x1];
207 u8 reserved_1[0x1];
208 u8 outer_second_prio[0x1];
209 u8 outer_second_cfi[0x1];
210 u8 outer_second_vid[0x1];
211 u8 reserved_2[0x1];
212 u8 outer_sip[0x1];
213 u8 outer_dip[0x1];
214 u8 outer_frag[0x1];
215 u8 outer_ip_protocol[0x1];
216 u8 outer_ip_ecn[0x1];
217 u8 outer_ip_dscp[0x1];
218 u8 outer_udp_sport[0x1];
219 u8 outer_udp_dport[0x1];
220 u8 outer_tcp_sport[0x1];
221 u8 outer_tcp_dport[0x1];
222 u8 outer_tcp_flags[0x1];
223 u8 outer_gre_protocol[0x1];
224 u8 outer_gre_key[0x1];
225 u8 outer_vxlan_vni[0x1];
226 u8 reserved_3[0x5];
227 u8 source_eswitch_port[0x1];
228
229 u8 inner_dmac[0x1];
230 u8 inner_smac[0x1];
231 u8 inner_ether_type[0x1];
232 u8 reserved_4[0x1];
233 u8 inner_first_prio[0x1];
234 u8 inner_first_cfi[0x1];
235 u8 inner_first_vid[0x1];
236 u8 reserved_5[0x1];
237 u8 inner_second_prio[0x1];
238 u8 inner_second_cfi[0x1];
239 u8 inner_second_vid[0x1];
240 u8 reserved_6[0x1];
241 u8 inner_sip[0x1];
242 u8 inner_dip[0x1];
243 u8 inner_frag[0x1];
244 u8 inner_ip_protocol[0x1];
245 u8 inner_ip_ecn[0x1];
246 u8 inner_ip_dscp[0x1];
247 u8 inner_udp_sport[0x1];
248 u8 inner_udp_dport[0x1];
249 u8 inner_tcp_sport[0x1];
250 u8 inner_tcp_dport[0x1];
251 u8 inner_tcp_flags[0x1];
252 u8 reserved_7[0x9];
253
254 u8 reserved_8[0x40];
255};
256
257struct mlx5_ifc_flow_table_prop_layout_bits {
258 u8 ft_support[0x1];
259 u8 reserved_0[0x1f];
260
261 u8 reserved_1[0x2];
262 u8 log_max_ft_size[0x6];
263 u8 reserved_2[0x10];
264 u8 max_ft_level[0x8];
265
266 u8 reserved_3[0x20];
267
268 u8 reserved_4[0x18];
269 u8 log_max_ft_num[0x8];
270
271 u8 reserved_5[0x18];
272 u8 log_max_destination[0x8];
273
274 u8 reserved_6[0x18];
275 u8 log_max_flow[0x8];
276
277 u8 reserved_7[0x40];
278
279 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
280
281 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
282};
283
284struct mlx5_ifc_odp_per_transport_service_cap_bits {
285 u8 send[0x1];
286 u8 receive[0x1];
287 u8 write[0x1];
288 u8 read[0x1];
289 u8 reserved_0[0x1];
290 u8 srq_receive[0x1];
291 u8 reserved_1[0x1a];
292};
293
294struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
295 u8 smac_47_16[0x20];
296
297 u8 smac_15_0[0x10];
298 u8 ethertype[0x10];
299
300 u8 dmac_47_16[0x20];
301
302 u8 dmac_15_0[0x10];
303 u8 first_prio[0x3];
304 u8 first_cfi[0x1];
305 u8 first_vid[0xc];
306
307 u8 ip_protocol[0x8];
308 u8 ip_dscp[0x6];
309 u8 ip_ecn[0x2];
310 u8 vlan_tag[0x1];
311 u8 reserved_0[0x1];
312 u8 frag[0x1];
313 u8 reserved_1[0x4];
314 u8 tcp_flags[0x9];
315
316 u8 tcp_sport[0x10];
317 u8 tcp_dport[0x10];
318
319 u8 reserved_2[0x20];
320
321 u8 udp_sport[0x10];
322 u8 udp_dport[0x10];
323
324 u8 src_ip[4][0x20];
325
326 u8 dst_ip[4][0x20];
327};
328
329struct mlx5_ifc_fte_match_set_misc_bits {
330 u8 reserved_0[0x20];
331
332 u8 reserved_1[0x10];
333 u8 source_port[0x10];
334
335 u8 outer_second_prio[0x3];
336 u8 outer_second_cfi[0x1];
337 u8 outer_second_vid[0xc];
338 u8 inner_second_prio[0x3];
339 u8 inner_second_cfi[0x1];
340 u8 inner_second_vid[0xc];
341
342 u8 outer_second_vlan_tag[0x1];
343 u8 inner_second_vlan_tag[0x1];
344 u8 reserved_2[0xe];
345 u8 gre_protocol[0x10];
346
347 u8 gre_key_h[0x18];
348 u8 gre_key_l[0x8];
349
350 u8 vxlan_vni[0x18];
351 u8 reserved_3[0x8];
352
353 u8 reserved_4[0x20];
354
355 u8 reserved_5[0xc];
356 u8 outer_ipv6_flow_label[0x14];
357
358 u8 reserved_6[0xc];
359 u8 inner_ipv6_flow_label[0x14];
360
361 u8 reserved_7[0xe0];
362};
363
364struct mlx5_ifc_cmd_pas_bits {
365 u8 pa_h[0x20];
366
367 u8 pa_l[0x14];
368 u8 reserved_0[0xc];
369};
370
371struct mlx5_ifc_uint64_bits {
372 u8 hi[0x20];
373
374 u8 lo[0x20];
375};
376
377enum {
378 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
379 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
380 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
381 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
382 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
383 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
384 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
385 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
386 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
387 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
388};
389
390struct mlx5_ifc_ads_bits {
391 u8 fl[0x1];
392 u8 free_ar[0x1];
393 u8 reserved_0[0xe];
394 u8 pkey_index[0x10];
395
396 u8 reserved_1[0x8];
397 u8 grh[0x1];
398 u8 mlid[0x7];
399 u8 rlid[0x10];
400
401 u8 ack_timeout[0x5];
402 u8 reserved_2[0x3];
403 u8 src_addr_index[0x8];
404 u8 reserved_3[0x4];
405 u8 stat_rate[0x4];
406 u8 hop_limit[0x8];
407
408 u8 reserved_4[0x4];
409 u8 tclass[0x8];
410 u8 flow_label[0x14];
411
412 u8 rgid_rip[16][0x8];
413
414 u8 reserved_5[0x4];
415 u8 f_dscp[0x1];
416 u8 f_ecn[0x1];
417 u8 reserved_6[0x1];
418 u8 f_eth_prio[0x1];
419 u8 ecn[0x2];
420 u8 dscp[0x6];
421 u8 udp_sport[0x10];
422
423 u8 dei_cfi[0x1];
424 u8 eth_prio[0x3];
425 u8 sl[0x4];
426 u8 port[0x8];
427 u8 rmac_47_32[0x10];
428
429 u8 rmac_31_0[0x20];
430};
431
432struct mlx5_ifc_flow_table_nic_cap_bits {
433 u8 reserved_0[0x200];
434
435 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
436
437 u8 reserved_1[0x200];
438
439 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
440
441 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
442
443 u8 reserved_2[0x200];
444
445 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
446
447 u8 reserved_3[0x7200];
448};
449
450struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
451 u8 csum_cap[0x1];
452 u8 vlan_cap[0x1];
453 u8 lro_cap[0x1];
454 u8 lro_psh_flag[0x1];
455 u8 lro_time_stamp[0x1];
66189961
TT		 456 u8 reserved_0[0x3];
457 u8 self_lb_en_modifiable[0x1];
458 u8 reserved_1[0x2];
e281682b 459 u8 max_lso_cap[0x5];
66189961 460 u8 reserved_2[0x4];
e281682b 461 u8 rss_ind_tbl_cap[0x4];
66189961 462 u8 reserved_3[0x3];
e281682b 463 u8 tunnel_lso_const_out_ip_id[0x1];
66189961 464 u8 reserved_4[0x2];
e281682b
SM		 465 u8 tunnel_statless_gre[0x1];
466 u8 tunnel_stateless_vxlan[0x1];
467
66189961 468 u8 reserved_5[0x20];
e281682b 469
66189961 470 u8 reserved_6[0x10];
e281682b
SM		 471 u8 lro_min_mss_size[0x10];
472
66189961 473 u8 reserved_7[0x120];
e281682b
SM		 474
475 u8 lro_timer_supported_periods[4][0x20];
476
66189961 477 u8 reserved_8[0x600];
e281682b
SM		 478};
479
480struct mlx5_ifc_roce_cap_bits {
481 u8 roce_apm[0x1];
482 u8 reserved_0[0x1f];
483
484 u8 reserved_1[0x60];
485
486 u8 reserved_2[0xc];
487 u8 l3_type[0x4];
488 u8 reserved_3[0x8];
489 u8 roce_version[0x8];
490
491 u8 reserved_4[0x10];
492 u8 r_roce_dest_udp_port[0x10];
493
494 u8 r_roce_max_src_udp_port[0x10];
495 u8 r_roce_min_src_udp_port[0x10];
496
497 u8 reserved_5[0x10];
498 u8 roce_address_table_size[0x10];
499
500 u8 reserved_6[0x700];
501};
502
503enum {
504 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
505 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
506 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
507 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
508 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
509 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
510 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
511 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
512 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
513};
514
515enum {
516 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
517 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
518 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
519 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
520 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
521 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
522 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
523 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
524 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
525};
526
527struct mlx5_ifc_atomic_caps_bits {
528 u8 reserved_0[0x40];
529
530 u8 atomic_req_endianness[0x1];
531 u8 reserved_1[0x1f];
532
533 u8 reserved_2[0x20];
534
535 u8 reserved_3[0x10];
536 u8 atomic_operations[0x10];
537
538 u8 reserved_4[0x10];
539 u8 atomic_size_qp[0x10];
540
541 u8 reserved_5[0x10];
542 u8 atomic_size_dc[0x10];
543
544 u8 reserved_6[0x720];
545};
546
547struct mlx5_ifc_odp_cap_bits {
548 u8 reserved_0[0x40];
549
550 u8 sig[0x1];
551 u8 reserved_1[0x1f];
552
553 u8 reserved_2[0x20];
554
555 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
556
557 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
558
559 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
560
561 u8 reserved_3[0x720];
562};
563
564enum {
565 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
566 MLX5_WQ_TYPE_CYCLIC = 0x1,
567 MLX5_WQ_TYPE_STRQ = 0x2,
568};
569
570enum {
571 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
572 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
573};
574
575enum {
576 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
577 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
578 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
579 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
580 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
581};
582
583enum {
584 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
585 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
586 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
587 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
588 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
589 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
590};
591
592enum {
593 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
594 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
595};
596
597enum {
598 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
599 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
600 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
601};
602
603enum {
604 MLX5_CAP_PORT_TYPE_IB = 0x0,
605 MLX5_CAP_PORT_TYPE_ETH = 0x1,
d29b796a
EC		 606};
607
b775516b
EC		 608struct mlx5_ifc_cmd_hca_cap_bits {
609 u8 reserved_0[0x80];
610
611 u8 log_max_srq_sz[0x8];
612 u8 log_max_qp_sz[0x8];
613 u8 reserved_1[0xb];
614 u8 log_max_qp[0x5];
615
e281682b
SM		 616 u8 reserved_2[0xb];
617 u8 log_max_srq[0x5];
b775516b
EC		 618 u8 reserved_3[0x10];
619
620 u8 reserved_4[0x8];
621 u8 log_max_cq_sz[0x8];
622 u8 reserved_5[0xb];
623 u8 log_max_cq[0x5];
624
625 u8 log_max_eq_sz[0x8];
626 u8 reserved_6[0x2];
627 u8 log_max_mkey[0x6];
628 u8 reserved_7[0xc];
629 u8 log_max_eq[0x4];
630
631 u8 max_indirection[0x8];
632 u8 reserved_8[0x1];
633 u8 log_max_mrw_sz[0x7];
634 u8 reserved_9[0x2];
635 u8 log_max_bsf_list_size[0x6];
636 u8 reserved_10[0x2];
637 u8 log_max_klm_list_size[0x6];
638
639 u8 reserved_11[0xa];
640 u8 log_max_ra_req_dc[0x6];
641 u8 reserved_12[0xa];
642 u8 log_max_ra_res_dc[0x6];
643
644 u8 reserved_13[0xa];
645 u8 log_max_ra_req_qp[0x6];
646 u8 reserved_14[0xa];
647 u8 log_max_ra_res_qp[0x6];
648
649 u8 pad_cap[0x1];
650 u8 cc_query_allowed[0x1];
651 u8 cc_modify_allowed[0x1];
e281682b
SM		 652 u8 reserved_15[0xd];
653 u8 gid_table_size[0x10];
b775516b 654
e281682b
SM		 655 u8 out_of_seq_cnt[0x1];
656 u8 vport_counters[0x1];
657 u8 reserved_16[0x4];
b775516b
EC		 658 u8 max_qp_cnt[0xa];
659 u8 pkey_table_size[0x10];
660
e281682b
SM		 661 u8 vport_group_manager[0x1];
662 u8 vhca_group_manager[0x1];
663 u8 ib_virt[0x1];
664 u8 eth_virt[0x1];
665 u8 reserved_17[0x1];
666 u8 ets[0x1];
667 u8 nic_flow_table[0x1];
54f0a411 668 u8 eswitch_flow_table[0x1];
fc50db98
EC		 669 u8 early_vf_enable;
670 u8 reserved_18[0x2];
b775516b 671 u8 local_ca_ack_delay[0x5];
e281682b
SM		 672 u8 reserved_19[0x6];
673 u8 port_type[0x2];
b775516b
EC		 674 u8 num_ports[0x8];
675
e281682b 676 u8 reserved_20[0x3];
b775516b 677 u8 log_max_msg[0x5];
e281682b 678 u8 reserved_21[0x18];
b775516b
EC		 679
680 u8 stat_rate_support[0x10];
e281682b
SM		 681 u8 reserved_22[0xc];
682 u8 cqe_version[0x4];
b775516b 683
e281682b
SM		 684 u8 compact_address_vector[0x1];
685 u8 reserved_23[0xe];
686 u8 drain_sigerr[0x1];
b775516b
EC		 687 u8 cmdif_checksum[0x2];
688 u8 sigerr_cqe[0x1];
e281682b 689 u8 reserved_24[0x1];
b775516b
EC		 690 u8 wq_signature[0x1];
691 u8 sctr_data_cqe[0x1];
e281682b 692 u8 reserved_25[0x1];
b775516b
EC		 693 u8 sho[0x1];
694 u8 tph[0x1];
695 u8 rf[0x1];
e281682b
SM		 696 u8 dct[0x1];
697 u8 reserved_26[0x1];
698 u8 eth_net_offloads[0x1];
b775516b
EC		 699 u8 roce[0x1];
700 u8 atomic[0x1];
e281682b 701 u8 reserved_27[0x1];
b775516b
EC		 702
703 u8 cq_oi[0x1];
704 u8 cq_resize[0x1];
705 u8 cq_moderation[0x1];
e281682b
SM		 706 u8 reserved_28[0x3];
707 u8 cq_eq_remap[0x1];
b775516b
EC		 708 u8 pg[0x1];
709 u8 block_lb_mc[0x1];
e281682b
SM		 710 u8 reserved_29[0x1];
711 u8 scqe_break_moderation[0x1];
712 u8 reserved_30[0x1];
b775516b 713 u8 cd[0x1];
e281682b 714 u8 reserved_31[0x1];
b775516b 715 u8 apm[0x1];
e281682b 716 u8 reserved_32[0x7];
b775516b
EC		 717 u8 qkv[0x1];
718 u8 pkv[0x1];
e281682b 719 u8 reserved_33[0x4];
b775516b
EC		 720 u8 xrc[0x1];
721 u8 ud[0x1];
722 u8 uc[0x1];
723 u8 rc[0x1];
724
e281682b 725 u8 reserved_34[0xa];
b775516b 726 u8 uar_sz[0x6];
e281682b 727 u8 reserved_35[0x8];
b775516b
EC		 728 u8 log_pg_sz[0x8];
729
730 u8 bf[0x1];
e281682b
SM		 731 u8 reserved_36[0x1];
732 u8 pad_tx_eth_packet[0x1];
733 u8 reserved_37[0x8];
b775516b 734 u8 log_bf_reg_size[0x5];
e281682b 735 u8 reserved_38[0x10];
b775516b 736
e281682b 737 u8 reserved_39[0x10];
b775516b
EC		 738 u8 max_wqe_sz_sq[0x10];
739
e281682b 740 u8 reserved_40[0x10];
b775516b
EC		 741 u8 max_wqe_sz_rq[0x10];
742
e281682b 743 u8 reserved_41[0x10];
b775516b
EC		 744 u8 max_wqe_sz_sq_dc[0x10];
745
e281682b 746 u8 reserved_42[0x7];
b775516b
EC		 747 u8 max_qp_mcg[0x19];
748
e281682b 749 u8 reserved_43[0x18];
b775516b
EC		 750 u8 log_max_mcg[0x8];
751
e281682b
SM		 752 u8 reserved_44[0x3];
753 u8 log_max_transport_domain[0x5];
754 u8 reserved_45[0x3];
b775516b 755 u8 log_max_pd[0x5];
e281682b 756 u8 reserved_46[0xb];
b775516b
EC		 757 u8 log_max_xrcd[0x5];
758
e281682b 759 u8 reserved_47[0x20];
b775516b 760
e281682b 761 u8 reserved_48[0x3];
b775516b 762 u8 log_max_rq[0x5];
e281682b 763 u8 reserved_49[0x3];
b775516b 764 u8 log_max_sq[0x5];
e281682b 765 u8 reserved_50[0x3];
b775516b 766 u8 log_max_tir[0x5];
e281682b 767 u8 reserved_51[0x3];
b775516b
EC		 768 u8 log_max_tis[0x5];
769
e281682b
SM		 770 u8 basic_cyclic_rcv_wqe[0x1];
771 u8 reserved_52[0x2];
772 u8 log_max_rmp[0x5];
773 u8 reserved_53[0x3];
774 u8 log_max_rqt[0x5];
775 u8 reserved_54[0x3];
776 u8 log_max_rqt_size[0x5];
777 u8 reserved_55[0x3];
b775516b
EC		 778 u8 log_max_tis_per_sq[0x5];
779
e281682b
SM		 780 u8 reserved_56[0x3];
781 u8 log_max_stride_sz_rq[0x5];
782 u8 reserved_57[0x3];
783 u8 log_min_stride_sz_rq[0x5];
784 u8 reserved_58[0x3];
785 u8 log_max_stride_sz_sq[0x5];
786 u8 reserved_59[0x3];
787 u8 log_min_stride_sz_sq[0x5];
788
789 u8 reserved_60[0x1b];
790 u8 log_max_wq_sz[0x5];
791
54f0a411
SM		 792 u8 nic_vport_change_event[0x1];
793 u8 reserved_61[0xa];
794 u8 log_max_vlan_list[0x5];
e281682b 795 u8 reserved_62[0x3];
54f0a411
SM		 796 u8 log_max_current_mc_list[0x5];
797 u8 reserved_63[0x3];
798 u8 log_max_current_uc_list[0x5];
799
800 u8 reserved_64[0x80];
801
802 u8 reserved_65[0x3];
e281682b 803 u8 log_max_l2_table[0x5];
54f0a411 804 u8 reserved_66[0x8];
b775516b
EC		 805 u8 log_uar_page_sz[0x10];
806
54f0a411 807 u8 reserved_67[0xe0];
b775516b 808
54f0a411 809 u8 reserved_68[0x1f];
b775516b
EC		 810 u8 cqe_zip[0x1];
811
812 u8 cqe_zip_timeout[0x10];
813 u8 cqe_zip_max_num[0x10];
814
54f0a411 815 u8 reserved_69[0x220];
b775516b
EC		 816};
817
e281682b
SM		 818enum {
819 MLX5_DEST_FORMAT_STRUCT_DESTINATION_TYPE_FLOW_TABLE_ = 0x1,
820 MLX5_DEST_FORMAT_STRUCT_DESTINATION_TYPE_TIR = 0x2,
821};
b775516b 822
e281682b
SM		 823struct mlx5_ifc_dest_format_struct_bits {
824 u8 destination_type[0x8];
825 u8 destination_id[0x18];
b775516b 826
e281682b
SM		 827 u8 reserved_0[0x20];
828};
829
830struct mlx5_ifc_fte_match_param_bits {
831 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
832
833 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
834
835 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
b775516b 836
e281682b 837 u8 reserved_0[0xa00];
b775516b
EC		 838};
839
e281682b
SM		 840enum {
841 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
842 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
843 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
844 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
845 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
846};
b775516b 847
e281682b
SM		 848struct mlx5_ifc_rx_hash_field_select_bits {
849 u8 l3_prot_type[0x1];
850 u8 l4_prot_type[0x1];
851 u8 selected_fields[0x1e];
852};
b775516b 853
e281682b
SM		 854enum {
855 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
856 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
b775516b
EC		 857};
858
e281682b
SM		 859enum {
860 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
861 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
862};
863
864struct mlx5_ifc_wq_bits {
865 u8 wq_type[0x4];
866 u8 wq_signature[0x1];
867 u8 end_padding_mode[0x2];
868 u8 cd_slave[0x1];
b775516b
EC		 869 u8 reserved_0[0x18];
870
e281682b
SM		 871 u8 hds_skip_first_sge[0x1];
872 u8 log2_hds_buf_size[0x3];
873 u8 reserved_1[0x7];
874 u8 page_offset[0x5];
875 u8 lwm[0x10];
b775516b 876
e281682b
SM		 877 u8 reserved_2[0x8];
878 u8 pd[0x18];
879
880 u8 reserved_3[0x8];
881 u8 uar_page[0x18];
882
883 u8 dbr_addr[0x40];
884
885 u8 hw_counter[0x20];
886
887 u8 sw_counter[0x20];
888
889 u8 reserved_4[0xc];
890 u8 log_wq_stride[0x4];
891 u8 reserved_5[0x3];
892 u8 log_wq_pg_sz[0x5];
893 u8 reserved_6[0x3];
894 u8 log_wq_sz[0x5];
895
896 u8 reserved_7[0x4e0];
b775516b 897
e281682b 898 struct mlx5_ifc_cmd_pas_bits pas[0];
b775516b
EC		 899};
900
e281682b
SM		 901struct mlx5_ifc_rq_num_bits {
902 u8 reserved_0[0x8];
903 u8 rq_num[0x18];
904};
b775516b 905
e281682b
SM		 906struct mlx5_ifc_mac_address_layout_bits {
907 u8 reserved_0[0x10];
908 u8 mac_addr_47_32[0x10];
b775516b 909
e281682b
SM		 910 u8 mac_addr_31_0[0x20];
911};
912
c0046cf7
SM		 913struct mlx5_ifc_vlan_layout_bits {
914 u8 reserved_0[0x14];
915 u8 vlan[0x0c];
916
917 u8 reserved_1[0x20];
918};
919
e281682b
SM		 920struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
921 u8 reserved_0[0xa0];
922
923 u8 min_time_between_cnps[0x20];
924
925 u8 reserved_1[0x12];
926 u8 cnp_dscp[0x6];
927 u8 reserved_2[0x5];
928 u8 cnp_802p_prio[0x3];
929
930 u8 reserved_3[0x720];
931};
932
933struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
934 u8 reserved_0[0x60];
935
936 u8 reserved_1[0x4];
937 u8 clamp_tgt_rate[0x1];
938 u8 reserved_2[0x3];
939 u8 clamp_tgt_rate_after_time_inc[0x1];
940 u8 reserved_3[0x17];
941
942 u8 reserved_4[0x20];
943
944 u8 rpg_time_reset[0x20];
945
946 u8 rpg_byte_reset[0x20];
947
948 u8 rpg_threshold[0x20];
949
950 u8 rpg_max_rate[0x20];
951
952 u8 rpg_ai_rate[0x20];
953
954 u8 rpg_hai_rate[0x20];
955
956 u8 rpg_gd[0x20];
957
958 u8 rpg_min_dec_fac[0x20];
959
960 u8 rpg_min_rate[0x20];
961
962 u8 reserved_5[0xe0];
963
964 u8 rate_to_set_on_first_cnp[0x20];
965
966 u8 dce_tcp_g[0x20];
967
968 u8 dce_tcp_rtt[0x20];
969
970 u8 rate_reduce_monitor_period[0x20];
971
972 u8 reserved_6[0x20];
973
974 u8 initial_alpha_value[0x20];
975
976 u8 reserved_7[0x4a0];
977};
978
979struct mlx5_ifc_cong_control_802_1qau_rp_bits {
980 u8 reserved_0[0x80];
981
982 u8 rppp_max_rps[0x20];
983
984 u8 rpg_time_reset[0x20];
985
986 u8 rpg_byte_reset[0x20];
987
988 u8 rpg_threshold[0x20];
989
990 u8 rpg_max_rate[0x20];
991
992 u8 rpg_ai_rate[0x20];
993
994 u8 rpg_hai_rate[0x20];
995
996 u8 rpg_gd[0x20];
997
998 u8 rpg_min_dec_fac[0x20];
999
1000 u8 rpg_min_rate[0x20];
1001
1002 u8 reserved_1[0x640];
1003};
1004
1005enum {
1006 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1007 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1008 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1009};
1010
1011struct mlx5_ifc_resize_field_select_bits {
1012 u8 resize_field_select[0x20];
1013};
1014
1015enum {
1016 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1017 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1018 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1019 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1020};
1021
1022struct mlx5_ifc_modify_field_select_bits {
1023 u8 modify_field_select[0x20];
1024};
1025
1026struct mlx5_ifc_field_select_r_roce_np_bits {
1027 u8 field_select_r_roce_np[0x20];
1028};
1029
1030struct mlx5_ifc_field_select_r_roce_rp_bits {
1031 u8 field_select_r_roce_rp[0x20];
1032};
1033
1034enum {
1035 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1036 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1037 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1038 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1039 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1040 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1041 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1042 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1043 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1044 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1045};
1046
1047struct mlx5_ifc_field_select_802_1qau_rp_bits {
1048 u8 field_select_8021qaurp[0x20];
1049};
1050
1051struct mlx5_ifc_phys_layer_cntrs_bits {
1052 u8 time_since_last_clear_high[0x20];
1053
1054 u8 time_since_last_clear_low[0x20];
1055
1056 u8 symbol_errors_high[0x20];
1057
1058 u8 symbol_errors_low[0x20];
1059
1060 u8 sync_headers_errors_high[0x20];
1061
1062 u8 sync_headers_errors_low[0x20];
1063
1064 u8 edpl_bip_errors_lane0_high[0x20];
1065
1066 u8 edpl_bip_errors_lane0_low[0x20];
1067
1068 u8 edpl_bip_errors_lane1_high[0x20];
1069
1070 u8 edpl_bip_errors_lane1_low[0x20];
1071
1072 u8 edpl_bip_errors_lane2_high[0x20];
1073
1074 u8 edpl_bip_errors_lane2_low[0x20];
1075
1076 u8 edpl_bip_errors_lane3_high[0x20];
1077
1078 u8 edpl_bip_errors_lane3_low[0x20];
1079
1080 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1081
1082 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1083
1084 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1085
1086 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1087
1088 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1089
1090 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1091
1092 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1093
1094 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1095
1096 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1097
1098 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1099
1100 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1101
1102 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1103
1104 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1105
1106 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1107
1108 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1109
1110 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1111
1112 u8 rs_fec_corrected_blocks_high[0x20];
1113
1114 u8 rs_fec_corrected_blocks_low[0x20];
1115
1116 u8 rs_fec_uncorrectable_blocks_high[0x20];
1117
1118 u8 rs_fec_uncorrectable_blocks_low[0x20];
1119
1120 u8 rs_fec_no_errors_blocks_high[0x20];
1121
1122 u8 rs_fec_no_errors_blocks_low[0x20];
1123
1124 u8 rs_fec_single_error_blocks_high[0x20];
1125
1126 u8 rs_fec_single_error_blocks_low[0x20];
1127
1128 u8 rs_fec_corrected_symbols_total_high[0x20];
1129
1130 u8 rs_fec_corrected_symbols_total_low[0x20];
1131
1132 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1133
1134 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1135
1136 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1137
1138 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1139
1140 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1141
1142 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1143
1144 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1145
1146 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1147
1148 u8 link_down_events[0x20];
1149
1150 u8 successful_recovery_events[0x20];
1151
1152 u8 reserved_0[0x180];
1153};
1154
1155struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1156 u8 transmit_queue_high[0x20];
1157
1158 u8 transmit_queue_low[0x20];
1159
1160 u8 reserved_0[0x780];
1161};
1162
1163struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1164 u8 rx_octets_high[0x20];
1165
1166 u8 rx_octets_low[0x20];
1167
1168 u8 reserved_0[0xc0];
1169
1170 u8 rx_frames_high[0x20];
1171
1172 u8 rx_frames_low[0x20];
1173
1174 u8 tx_octets_high[0x20];
1175
1176 u8 tx_octets_low[0x20];
1177
1178 u8 reserved_1[0xc0];
1179
1180 u8 tx_frames_high[0x20];
1181
1182 u8 tx_frames_low[0x20];
1183
1184 u8 rx_pause_high[0x20];
1185
1186 u8 rx_pause_low[0x20];
1187
1188 u8 rx_pause_duration_high[0x20];
1189
1190 u8 rx_pause_duration_low[0x20];
1191
1192 u8 tx_pause_high[0x20];
1193
1194 u8 tx_pause_low[0x20];
1195
1196 u8 tx_pause_duration_high[0x20];
1197
1198 u8 tx_pause_duration_low[0x20];
1199
1200 u8 rx_pause_transition_high[0x20];
1201
1202 u8 rx_pause_transition_low[0x20];
1203
1204 u8 reserved_2[0x400];
1205};
1206
1207struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1208 u8 port_transmit_wait_high[0x20];
1209
1210 u8 port_transmit_wait_low[0x20];
1211
1212 u8 reserved_0[0x780];
1213};
1214
1215struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1216 u8 dot3stats_alignment_errors_high[0x20];
1217
1218 u8 dot3stats_alignment_errors_low[0x20];
1219
1220 u8 dot3stats_fcs_errors_high[0x20];
1221
1222 u8 dot3stats_fcs_errors_low[0x20];
1223
1224 u8 dot3stats_single_collision_frames_high[0x20];
1225
1226 u8 dot3stats_single_collision_frames_low[0x20];
1227
1228 u8 dot3stats_multiple_collision_frames_high[0x20];
1229
1230 u8 dot3stats_multiple_collision_frames_low[0x20];
1231
1232 u8 dot3stats_sqe_test_errors_high[0x20];
1233
1234 u8 dot3stats_sqe_test_errors_low[0x20];
1235
1236 u8 dot3stats_deferred_transmissions_high[0x20];
1237
1238 u8 dot3stats_deferred_transmissions_low[0x20];
1239
1240 u8 dot3stats_late_collisions_high[0x20];
1241
1242 u8 dot3stats_late_collisions_low[0x20];
1243
1244 u8 dot3stats_excessive_collisions_high[0x20];
1245
1246 u8 dot3stats_excessive_collisions_low[0x20];
1247
1248 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1249
1250 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1251
1252 u8 dot3stats_carrier_sense_errors_high[0x20];
1253
1254 u8 dot3stats_carrier_sense_errors_low[0x20];
1255
1256 u8 dot3stats_frame_too_longs_high[0x20];
1257
1258 u8 dot3stats_frame_too_longs_low[0x20];
1259
1260 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1261
1262 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1263
1264 u8 dot3stats_symbol_errors_high[0x20];
1265
1266 u8 dot3stats_symbol_errors_low[0x20];
1267
1268 u8 dot3control_in_unknown_opcodes_high[0x20];
1269
1270 u8 dot3control_in_unknown_opcodes_low[0x20];
1271
1272 u8 dot3in_pause_frames_high[0x20];
1273
1274 u8 dot3in_pause_frames_low[0x20];
1275
1276 u8 dot3out_pause_frames_high[0x20];
1277
1278 u8 dot3out_pause_frames_low[0x20];
1279
1280 u8 reserved_0[0x3c0];
1281};
1282
1283struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1284 u8 ether_stats_drop_events_high[0x20];
1285
1286 u8 ether_stats_drop_events_low[0x20];
1287
1288 u8 ether_stats_octets_high[0x20];
1289
1290 u8 ether_stats_octets_low[0x20];
1291
1292 u8 ether_stats_pkts_high[0x20];
1293
1294 u8 ether_stats_pkts_low[0x20];
1295
1296 u8 ether_stats_broadcast_pkts_high[0x20];
1297
1298 u8 ether_stats_broadcast_pkts_low[0x20];
1299
1300 u8 ether_stats_multicast_pkts_high[0x20];
1301
1302 u8 ether_stats_multicast_pkts_low[0x20];
1303
1304 u8 ether_stats_crc_align_errors_high[0x20];
1305
1306 u8 ether_stats_crc_align_errors_low[0x20];
1307
1308 u8 ether_stats_undersize_pkts_high[0x20];
1309
1310 u8 ether_stats_undersize_pkts_low[0x20];
1311
1312 u8 ether_stats_oversize_pkts_high[0x20];
1313
1314 u8 ether_stats_oversize_pkts_low[0x20];
1315
1316 u8 ether_stats_fragments_high[0x20];
1317
1318 u8 ether_stats_fragments_low[0x20];
1319
1320 u8 ether_stats_jabbers_high[0x20];
1321
1322 u8 ether_stats_jabbers_low[0x20];
1323
1324 u8 ether_stats_collisions_high[0x20];
1325
1326 u8 ether_stats_collisions_low[0x20];
1327
1328 u8 ether_stats_pkts64octets_high[0x20];
1329
1330 u8 ether_stats_pkts64octets_low[0x20];
1331
1332 u8 ether_stats_pkts65to127octets_high[0x20];
1333
1334 u8 ether_stats_pkts65to127octets_low[0x20];
1335
1336 u8 ether_stats_pkts128to255octets_high[0x20];
1337
1338 u8 ether_stats_pkts128to255octets_low[0x20];
1339
1340 u8 ether_stats_pkts256to511octets_high[0x20];
1341
1342 u8 ether_stats_pkts256to511octets_low[0x20];
1343
1344 u8 ether_stats_pkts512to1023octets_high[0x20];
1345
1346 u8 ether_stats_pkts512to1023octets_low[0x20];
1347
1348 u8 ether_stats_pkts1024to1518octets_high[0x20];
1349
1350 u8 ether_stats_pkts1024to1518octets_low[0x20];
1351
1352 u8 ether_stats_pkts1519to2047octets_high[0x20];
1353
1354 u8 ether_stats_pkts1519to2047octets_low[0x20];
1355
1356 u8 ether_stats_pkts2048to4095octets_high[0x20];
1357
1358 u8 ether_stats_pkts2048to4095octets_low[0x20];
1359
1360 u8 ether_stats_pkts4096to8191octets_high[0x20];
1361
1362 u8 ether_stats_pkts4096to8191octets_low[0x20];
1363
1364 u8 ether_stats_pkts8192to10239octets_high[0x20];
1365
1366 u8 ether_stats_pkts8192to10239octets_low[0x20];
1367
1368 u8 reserved_0[0x280];
1369};
1370
1371struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1372 u8 if_in_octets_high[0x20];
1373
1374 u8 if_in_octets_low[0x20];
1375
1376 u8 if_in_ucast_pkts_high[0x20];
1377
1378 u8 if_in_ucast_pkts_low[0x20];
1379
1380 u8 if_in_discards_high[0x20];
1381
1382 u8 if_in_discards_low[0x20];
1383
1384 u8 if_in_errors_high[0x20];
1385
1386 u8 if_in_errors_low[0x20];
1387
1388 u8 if_in_unknown_protos_high[0x20];
1389
1390 u8 if_in_unknown_protos_low[0x20];
1391
1392 u8 if_out_octets_high[0x20];
1393
1394 u8 if_out_octets_low[0x20];
1395
1396 u8 if_out_ucast_pkts_high[0x20];
1397
1398 u8 if_out_ucast_pkts_low[0x20];
1399
1400 u8 if_out_discards_high[0x20];
1401
1402 u8 if_out_discards_low[0x20];
1403
1404 u8 if_out_errors_high[0x20];
1405
1406 u8 if_out_errors_low[0x20];
1407
1408 u8 if_in_multicast_pkts_high[0x20];
1409
1410 u8 if_in_multicast_pkts_low[0x20];
1411
1412 u8 if_in_broadcast_pkts_high[0x20];
1413
1414 u8 if_in_broadcast_pkts_low[0x20];
1415
1416 u8 if_out_multicast_pkts_high[0x20];
1417
1418 u8 if_out_multicast_pkts_low[0x20];
1419
1420 u8 if_out_broadcast_pkts_high[0x20];
1421
1422 u8 if_out_broadcast_pkts_low[0x20];
1423
1424 u8 reserved_0[0x480];
1425};
1426
1427struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1428 u8 a_frames_transmitted_ok_high[0x20];
1429
1430 u8 a_frames_transmitted_ok_low[0x20];
1431
1432 u8 a_frames_received_ok_high[0x20];
1433
1434 u8 a_frames_received_ok_low[0x20];
1435
1436 u8 a_frame_check_sequence_errors_high[0x20];
1437
1438 u8 a_frame_check_sequence_errors_low[0x20];
1439
1440 u8 a_alignment_errors_high[0x20];
1441
1442 u8 a_alignment_errors_low[0x20];
1443
1444 u8 a_octets_transmitted_ok_high[0x20];
1445
1446 u8 a_octets_transmitted_ok_low[0x20];
1447
1448 u8 a_octets_received_ok_high[0x20];
1449
1450 u8 a_octets_received_ok_low[0x20];
1451
1452 u8 a_multicast_frames_xmitted_ok_high[0x20];
1453
1454 u8 a_multicast_frames_xmitted_ok_low[0x20];
1455
1456 u8 a_broadcast_frames_xmitted_ok_high[0x20];
1457
1458 u8 a_broadcast_frames_xmitted_ok_low[0x20];
1459
1460 u8 a_multicast_frames_received_ok_high[0x20];
1461
1462 u8 a_multicast_frames_received_ok_low[0x20];
1463
1464 u8 a_broadcast_frames_received_ok_high[0x20];
1465
1466 u8 a_broadcast_frames_received_ok_low[0x20];
1467
1468 u8 a_in_range_length_errors_high[0x20];
1469
1470 u8 a_in_range_length_errors_low[0x20];
1471
1472 u8 a_out_of_range_length_field_high[0x20];
1473
1474 u8 a_out_of_range_length_field_low[0x20];
1475
1476 u8 a_frame_too_long_errors_high[0x20];
1477
1478 u8 a_frame_too_long_errors_low[0x20];
1479
1480 u8 a_symbol_error_during_carrier_high[0x20];
1481
1482 u8 a_symbol_error_during_carrier_low[0x20];
1483
1484 u8 a_mac_control_frames_transmitted_high[0x20];
1485
1486 u8 a_mac_control_frames_transmitted_low[0x20];
1487
1488 u8 a_mac_control_frames_received_high[0x20];
1489
1490 u8 a_mac_control_frames_received_low[0x20];
1491
1492 u8 a_unsupported_opcodes_received_high[0x20];
1493
1494 u8 a_unsupported_opcodes_received_low[0x20];
1495
1496 u8 a_pause_mac_ctrl_frames_received_high[0x20];
1497
1498 u8 a_pause_mac_ctrl_frames_received_low[0x20];
1499
1500 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
1501
1502 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
1503
1504 u8 reserved_0[0x300];
1505};
1506
1507struct mlx5_ifc_cmd_inter_comp_event_bits {
1508 u8 command_completion_vector[0x20];
1509
1510 u8 reserved_0[0xc0];
1511};
1512
1513struct mlx5_ifc_stall_vl_event_bits {
1514 u8 reserved_0[0x18];
1515 u8 port_num[0x1];
1516 u8 reserved_1[0x3];
1517 u8 vl[0x4];
1518
1519 u8 reserved_2[0xa0];
1520};
1521
1522struct mlx5_ifc_db_bf_congestion_event_bits {
1523 u8 event_subtype[0x8];
1524 u8 reserved_0[0x8];
1525 u8 congestion_level[0x8];
1526 u8 reserved_1[0x8];
1527
1528 u8 reserved_2[0xa0];
1529};
1530
1531struct mlx5_ifc_gpio_event_bits {
1532 u8 reserved_0[0x60];
1533
1534 u8 gpio_event_hi[0x20];
1535
1536 u8 gpio_event_lo[0x20];
1537
1538 u8 reserved_1[0x40];
1539};
1540
1541struct mlx5_ifc_port_state_change_event_bits {
1542 u8 reserved_0[0x40];
1543
1544 u8 port_num[0x4];
1545 u8 reserved_1[0x1c];
1546
1547 u8 reserved_2[0x80];
1548};
1549
1550struct mlx5_ifc_dropped_packet_logged_bits {
1551 u8 reserved_0[0xe0];
1552};
1553
1554enum {
1555 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
1556 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
1557};
1558
1559struct mlx5_ifc_cq_error_bits {
1560 u8 reserved_0[0x8];
1561 u8 cqn[0x18];
1562
1563 u8 reserved_1[0x20];
1564
1565 u8 reserved_2[0x18];
1566 u8 syndrome[0x8];
1567
1568 u8 reserved_3[0x80];
1569};
1570
1571struct mlx5_ifc_rdma_page_fault_event_bits {
1572 u8 bytes_committed[0x20];
1573
1574 u8 r_key[0x20];
1575
1576 u8 reserved_0[0x10];
1577 u8 packet_len[0x10];
1578
1579 u8 rdma_op_len[0x20];
1580
1581 u8 rdma_va[0x40];
1582
1583 u8 reserved_1[0x5];
1584 u8 rdma[0x1];
1585 u8 write[0x1];
1586 u8 requestor[0x1];
1587 u8 qp_number[0x18];
1588};
1589
1590struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1591 u8 bytes_committed[0x20];
1592
1593 u8 reserved_0[0x10];
1594 u8 wqe_index[0x10];
1595
1596 u8 reserved_1[0x10];
1597 u8 len[0x10];
1598
1599 u8 reserved_2[0x60];
1600
1601 u8 reserved_3[0x5];
1602 u8 rdma[0x1];
1603 u8 write_read[0x1];
1604 u8 requestor[0x1];
1605 u8 qpn[0x18];
1606};
1607
1608struct mlx5_ifc_qp_events_bits {
1609 u8 reserved_0[0xa0];
1610
1611 u8 type[0x8];
1612 u8 reserved_1[0x18];
1613
1614 u8 reserved_2[0x8];
1615 u8 qpn_rqn_sqn[0x18];
1616};
1617
1618struct mlx5_ifc_dct_events_bits {
1619 u8 reserved_0[0xc0];
1620
1621 u8 reserved_1[0x8];
1622 u8 dct_number[0x18];
1623};
1624
1625struct mlx5_ifc_comp_event_bits {
1626 u8 reserved_0[0xc0];
1627
1628 u8 reserved_1[0x8];
1629 u8 cq_number[0x18];
1630};
1631
1632enum {
1633 MLX5_QPC_STATE_RST = 0x0,
1634 MLX5_QPC_STATE_INIT = 0x1,
1635 MLX5_QPC_STATE_RTR = 0x2,
1636 MLX5_QPC_STATE_RTS = 0x3,
1637 MLX5_QPC_STATE_SQER = 0x4,
1638 MLX5_QPC_STATE_ERR = 0x6,
1639 MLX5_QPC_STATE_SQD = 0x7,
1640 MLX5_QPC_STATE_SUSPENDED = 0x9,
1641};
1642
1643enum {
1644 MLX5_QPC_ST_RC = 0x0,
1645 MLX5_QPC_ST_UC = 0x1,
1646 MLX5_QPC_ST_UD = 0x2,
1647 MLX5_QPC_ST_XRC = 0x3,
1648 MLX5_QPC_ST_DCI = 0x5,
1649 MLX5_QPC_ST_QP0 = 0x7,
1650 MLX5_QPC_ST_QP1 = 0x8,
1651 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
1652 MLX5_QPC_ST_REG_UMR = 0xc,
1653};
1654
1655enum {
1656 MLX5_QPC_PM_STATE_ARMED = 0x0,
1657 MLX5_QPC_PM_STATE_REARM = 0x1,
1658 MLX5_QPC_PM_STATE_RESERVED = 0x2,
1659 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
1660};
1661
1662enum {
1663 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
1664 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
1665};
1666
1667enum {
1668 MLX5_QPC_MTU_256_BYTES = 0x1,
1669 MLX5_QPC_MTU_512_BYTES = 0x2,
1670 MLX5_QPC_MTU_1K_BYTES = 0x3,
1671 MLX5_QPC_MTU_2K_BYTES = 0x4,
1672 MLX5_QPC_MTU_4K_BYTES = 0x5,
1673 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
1674};
1675
1676enum {
1677 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
1678 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
1679 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
1680 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
1681 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
1682 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
1683 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
1684 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
1685};
1686
1687enum {
1688 MLX5_QPC_CS_REQ_DISABLE = 0x0,
1689 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
1690 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
1691};
1692
1693enum {
1694 MLX5_QPC_CS_RES_DISABLE = 0x0,
1695 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
1696 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
1697};
1698
1699struct mlx5_ifc_qpc_bits {
1700 u8 state[0x4];
1701 u8 reserved_0[0x4];
1702 u8 st[0x8];
1703 u8 reserved_1[0x3];
1704 u8 pm_state[0x2];
1705 u8 reserved_2[0x7];
1706 u8 end_padding_mode[0x2];
1707 u8 reserved_3[0x2];
1708
1709 u8 wq_signature[0x1];
1710 u8 block_lb_mc[0x1];
1711 u8 atomic_like_write_en[0x1];
1712 u8 latency_sensitive[0x1];
1713 u8 reserved_4[0x1];
1714 u8 drain_sigerr[0x1];
1715 u8 reserved_5[0x2];
1716 u8 pd[0x18];
1717
1718 u8 mtu[0x3];
1719 u8 log_msg_max[0x5];
1720 u8 reserved_6[0x1];
1721 u8 log_rq_size[0x4];
1722 u8 log_rq_stride[0x3];
1723 u8 no_sq[0x1];
1724 u8 log_sq_size[0x4];
1725 u8 reserved_7[0x6];
1726 u8 rlky[0x1];
1727 u8 reserved_8[0x4];
1728
1729 u8 counter_set_id[0x8];
1730 u8 uar_page[0x18];
1731
1732 u8 reserved_9[0x8];
1733 u8 user_index[0x18];
1734
1735 u8 reserved_10[0x3];
1736 u8 log_page_size[0x5];
1737 u8 remote_qpn[0x18];
1738
1739 struct mlx5_ifc_ads_bits primary_address_path;
1740
1741 struct mlx5_ifc_ads_bits secondary_address_path;
1742
1743 u8 log_ack_req_freq[0x4];
1744 u8 reserved_11[0x4];
1745 u8 log_sra_max[0x3];
1746 u8 reserved_12[0x2];
1747 u8 retry_count[0x3];
1748 u8 rnr_retry[0x3];
1749 u8 reserved_13[0x1];
1750 u8 fre[0x1];
1751 u8 cur_rnr_retry[0x3];
1752 u8 cur_retry_count[0x3];
1753 u8 reserved_14[0x5];
1754
1755 u8 reserved_15[0x20];
1756
1757 u8 reserved_16[0x8];
1758 u8 next_send_psn[0x18];
1759
1760 u8 reserved_17[0x8];
1761 u8 cqn_snd[0x18];
1762
1763 u8 reserved_18[0x40];
1764
1765 u8 reserved_19[0x8];
1766 u8 last_acked_psn[0x18];
1767
1768 u8 reserved_20[0x8];
1769 u8 ssn[0x18];
1770
1771 u8 reserved_21[0x8];
1772 u8 log_rra_max[0x3];
1773 u8 reserved_22[0x1];
1774 u8 atomic_mode[0x4];
1775 u8 rre[0x1];
1776 u8 rwe[0x1];
1777 u8 rae[0x1];
1778 u8 reserved_23[0x1];
1779 u8 page_offset[0x6];
1780 u8 reserved_24[0x3];
1781 u8 cd_slave_receive[0x1];
1782 u8 cd_slave_send[0x1];
1783 u8 cd_master[0x1];
1784
1785 u8 reserved_25[0x3];
1786 u8 min_rnr_nak[0x5];
1787 u8 next_rcv_psn[0x18];
1788
1789 u8 reserved_26[0x8];
1790 u8 xrcd[0x18];
1791
1792 u8 reserved_27[0x8];
1793 u8 cqn_rcv[0x18];
1794
1795 u8 dbr_addr[0x40];
1796
1797 u8 q_key[0x20];
1798
1799 u8 reserved_28[0x5];
1800 u8 rq_type[0x3];
1801 u8 srqn_rmpn[0x18];
1802
1803 u8 reserved_29[0x8];
1804 u8 rmsn[0x18];
1805
1806 u8 hw_sq_wqebb_counter[0x10];
1807 u8 sw_sq_wqebb_counter[0x10];
1808
1809 u8 hw_rq_counter[0x20];
1810
1811 u8 sw_rq_counter[0x20];
1812
1813 u8 reserved_30[0x20];
1814
1815 u8 reserved_31[0xf];
1816 u8 cgs[0x1];
1817 u8 cs_req[0x8];
1818 u8 cs_res[0x8];
1819
1820 u8 dc_access_key[0x40];
1821
1822 u8 reserved_32[0xc0];
1823};
1824
1825struct mlx5_ifc_roce_addr_layout_bits {
1826 u8 source_l3_address[16][0x8];
1827
1828 u8 reserved_0[0x3];
1829 u8 vlan_valid[0x1];
1830 u8 vlan_id[0xc];
1831 u8 source_mac_47_32[0x10];
1832
1833 u8 source_mac_31_0[0x20];
1834
1835 u8 reserved_1[0x14];
1836 u8 roce_l3_type[0x4];
1837 u8 roce_version[0x8];
1838
1839 u8 reserved_2[0x20];
1840};
1841
1842union mlx5_ifc_hca_cap_union_bits {
1843 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
1844 struct mlx5_ifc_odp_cap_bits odp_cap;
1845 struct mlx5_ifc_atomic_caps_bits atomic_caps;
1846 struct mlx5_ifc_roce_cap_bits roce_cap;
1847 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
1848 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
1849 u8 reserved_0[0x8000];
1850};
1851
1852enum {
1853 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
1854 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
1855 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
1856};
1857
1858struct mlx5_ifc_flow_context_bits {
1859 u8 reserved_0[0x20];
1860
1861 u8 group_id[0x20];
1862
1863 u8 reserved_1[0x8];
1864 u8 flow_tag[0x18];
1865
1866 u8 reserved_2[0x10];
1867 u8 action[0x10];
1868
1869 u8 reserved_3[0x8];
1870 u8 destination_list_size[0x18];
1871
1872 u8 reserved_4[0x160];
1873
1874 struct mlx5_ifc_fte_match_param_bits match_value;
1875
1876 u8 reserved_5[0x600];
1877
1878 struct mlx5_ifc_dest_format_struct_bits destination[0];
1879};
1880
1881enum {
1882 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
1883 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
1884};
1885
1886struct mlx5_ifc_xrc_srqc_bits {
1887 u8 state[0x4];
1888 u8 log_xrc_srq_size[0x4];
1889 u8 reserved_0[0x18];
1890
1891 u8 wq_signature[0x1];
1892 u8 cont_srq[0x1];
1893 u8 reserved_1[0x1];
1894 u8 rlky[0x1];
1895 u8 basic_cyclic_rcv_wqe[0x1];
1896 u8 log_rq_stride[0x3];
1897 u8 xrcd[0x18];
1898
1899 u8 page_offset[0x6];
1900 u8 reserved_2[0x2];
1901 u8 cqn[0x18];
1902
1903 u8 reserved_3[0x20];
1904
1905 u8 user_index_equal_xrc_srqn[0x1];
1906 u8 reserved_4[0x1];
1907 u8 log_page_size[0x6];
1908 u8 user_index[0x18];
1909
1910 u8 reserved_5[0x20];
1911
1912 u8 reserved_6[0x8];
1913 u8 pd[0x18];
1914
1915 u8 lwm[0x10];
1916 u8 wqe_cnt[0x10];
1917
1918 u8 reserved_7[0x40];
1919
1920 u8 db_record_addr_h[0x20];
1921
1922 u8 db_record_addr_l[0x1e];
1923 u8 reserved_8[0x2];
1924
1925 u8 reserved_9[0x80];
1926};
1927
1928struct mlx5_ifc_traffic_counter_bits {
1929 u8 packets[0x40];
1930
1931 u8 octets[0x40];
1932};
1933
1934struct mlx5_ifc_tisc_bits {
1935 u8 reserved_0[0xc];
1936 u8 prio[0x4];
1937 u8 reserved_1[0x10];
1938
1939 u8 reserved_2[0x100];
1940
1941 u8 reserved_3[0x8];
1942 u8 transport_domain[0x18];
1943
1944 u8 reserved_4[0x3c0];
1945};
1946
1947enum {
1948 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
1949 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
1950};
1951
1952enum {
1953 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
1954 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
1955};
1956
1957enum {
2be6967c
SM		 1958 MLX5_RX_HASH_FN_NONE = 0x0,
1959 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
1960 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
e281682b
SM		 1961};
1962
1963enum {
1964 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1,
1965 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2,
1966};
1967
1968struct mlx5_ifc_tirc_bits {
1969 u8 reserved_0[0x20];
1970
1971 u8 disp_type[0x4];
1972 u8 reserved_1[0x1c];
1973
1974 u8 reserved_2[0x40];
1975
1976 u8 reserved_3[0x4];
1977 u8 lro_timeout_period_usecs[0x10];
1978 u8 lro_enable_mask[0x4];
1979 u8 lro_max_ip_payload_size[0x8];
1980
1981 u8 reserved_4[0x40];
1982
1983 u8 reserved_5[0x8];
1984 u8 inline_rqn[0x18];
1985
1986 u8 rx_hash_symmetric[0x1];
1987 u8 reserved_6[0x1];
1988 u8 tunneled_offload_en[0x1];
1989 u8 reserved_7[0x5];
1990 u8 indirect_table[0x18];
1991
1992 u8 rx_hash_fn[0x4];
1993 u8 reserved_8[0x2];
1994 u8 self_lb_block[0x2];
1995 u8 transport_domain[0x18];
1996
1997 u8 rx_hash_toeplitz_key[10][0x20];
1998
1999 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2000
2001 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2002
2003 u8 reserved_9[0x4c0];
2004};
2005
2006enum {
2007 MLX5_SRQC_STATE_GOOD = 0x0,
2008 MLX5_SRQC_STATE_ERROR = 0x1,
2009};
2010
2011struct mlx5_ifc_srqc_bits {
2012 u8 state[0x4];
2013 u8 log_srq_size[0x4];
2014 u8 reserved_0[0x18];
2015
2016 u8 wq_signature[0x1];
2017 u8 cont_srq[0x1];
2018 u8 reserved_1[0x1];
2019 u8 rlky[0x1];
2020 u8 reserved_2[0x1];
2021 u8 log_rq_stride[0x3];
2022 u8 xrcd[0x18];
2023
2024 u8 page_offset[0x6];
2025 u8 reserved_3[0x2];
2026 u8 cqn[0x18];
2027
2028 u8 reserved_4[0x20];
2029
2030 u8 reserved_5[0x2];
2031 u8 log_page_size[0x6];
2032 u8 reserved_6[0x18];
2033
2034 u8 reserved_7[0x20];
2035
2036 u8 reserved_8[0x8];
2037 u8 pd[0x18];
2038
2039 u8 lwm[0x10];
2040 u8 wqe_cnt[0x10];
2041
2042 u8 reserved_9[0x40];
2043
01949d01 2044 u8 dbr_addr[0x40];
e281682b 2045
01949d01 2046 u8 reserved_10[0x80];
e281682b
SM		 2047};
2048
2049enum {
2050 MLX5_SQC_STATE_RST = 0x0,
2051 MLX5_SQC_STATE_RDY = 0x1,
2052 MLX5_SQC_STATE_ERR = 0x3,
2053};
2054
2055struct mlx5_ifc_sqc_bits {
2056 u8 rlky[0x1];
2057 u8 cd_master[0x1];
2058 u8 fre[0x1];
2059 u8 flush_in_error_en[0x1];
2060 u8 reserved_0[0x4];
2061 u8 state[0x4];
2062 u8 reserved_1[0x14];
2063
2064 u8 reserved_2[0x8];
2065 u8 user_index[0x18];
2066
2067 u8 reserved_3[0x8];
2068 u8 cqn[0x18];
2069
2070 u8 reserved_4[0xa0];
2071
2072 u8 tis_lst_sz[0x10];
2073 u8 reserved_5[0x10];
2074
2075 u8 reserved_6[0x40];
2076
2077 u8 reserved_7[0x8];
2078 u8 tis_num_0[0x18];
2079
2080 struct mlx5_ifc_wq_bits wq;
2081};
2082
2083struct mlx5_ifc_rqtc_bits {
2084 u8 reserved_0[0xa0];
2085
2086 u8 reserved_1[0x10];
2087 u8 rqt_max_size[0x10];
2088
2089 u8 reserved_2[0x10];
2090 u8 rqt_actual_size[0x10];
2091
2092 u8 reserved_3[0x6a0];
2093
2094 struct mlx5_ifc_rq_num_bits rq_num[0];
2095};
2096
2097enum {
2098 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2099 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2100};
2101
2102enum {
2103 MLX5_RQC_STATE_RST = 0x0,
2104 MLX5_RQC_STATE_RDY = 0x1,
2105 MLX5_RQC_STATE_ERR = 0x3,
2106};
2107
2108struct mlx5_ifc_rqc_bits {
2109 u8 rlky[0x1];
2110 u8 reserved_0[0x2];
2111 u8 vsd[0x1];
2112 u8 mem_rq_type[0x4];
2113 u8 state[0x4];
2114 u8 reserved_1[0x1];
2115 u8 flush_in_error_en[0x1];
2116 u8 reserved_2[0x12];
2117
2118 u8 reserved_3[0x8];
2119 u8 user_index[0x18];
2120
2121 u8 reserved_4[0x8];
2122 u8 cqn[0x18];
2123
2124 u8 counter_set_id[0x8];
2125 u8 reserved_5[0x18];
2126
2127 u8 reserved_6[0x8];
2128 u8 rmpn[0x18];
2129
2130 u8 reserved_7[0xe0];
2131
2132 struct mlx5_ifc_wq_bits wq;
2133};
2134
2135enum {
2136 MLX5_RMPC_STATE_RDY = 0x1,
2137 MLX5_RMPC_STATE_ERR = 0x3,
2138};
2139
2140struct mlx5_ifc_rmpc_bits {
2141 u8 reserved_0[0x8];
2142 u8 state[0x4];
2143 u8 reserved_1[0x14];
2144
2145 u8 basic_cyclic_rcv_wqe[0x1];
2146 u8 reserved_2[0x1f];
2147
2148 u8 reserved_3[0x140];
2149
2150 struct mlx5_ifc_wq_bits wq;
2151};
2152
e281682b
SM		 2153struct mlx5_ifc_nic_vport_context_bits {
2154 u8 reserved_0[0x1f];
2155 u8 roce_en[0x1];
2156
d82b7318
SM		 2157 u8 arm_change_event[0x1];
2158 u8 reserved_1[0x1a];
2159 u8 event_on_mtu[0x1];
2160 u8 event_on_promisc_change[0x1];
2161 u8 event_on_vlan_change[0x1];
2162 u8 event_on_mc_address_change[0x1];
2163 u8 event_on_uc_address_change[0x1];
e281682b 2164
d82b7318
SM		 2165 u8 reserved_2[0xf0];
2166
2167 u8 mtu[0x10];
2168
2169 u8 reserved_3[0x640];
2170
2171 u8 promisc_uc[0x1];
2172 u8 promisc_mc[0x1];
2173 u8 promisc_all[0x1];
2174 u8 reserved_4[0x2];
e281682b 2175 u8 allowed_list_type[0x3];
d82b7318 2176 u8 reserved_5[0xc];
e281682b
SM		 2177 u8 allowed_list_size[0xc];
2178
2179 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2180
d82b7318 2181 u8 reserved_6[0x20];
e281682b
SM		 2182
2183 u8 current_uc_mac_address[0][0x40];
2184};
2185
2186enum {
2187 MLX5_MKC_ACCESS_MODE_PA = 0x0,
2188 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
2189 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
2190};
2191
2192struct mlx5_ifc_mkc_bits {
2193 u8 reserved_0[0x1];
2194 u8 free[0x1];
2195 u8 reserved_1[0xd];
2196 u8 small_fence_on_rdma_read_response[0x1];
2197 u8 umr_en[0x1];
2198 u8 a[0x1];
2199 u8 rw[0x1];
2200 u8 rr[0x1];
2201 u8 lw[0x1];
2202 u8 lr[0x1];
2203 u8 access_mode[0x2];
2204 u8 reserved_2[0x8];
2205
2206 u8 qpn[0x18];
2207 u8 mkey_7_0[0x8];
2208
2209 u8 reserved_3[0x20];
2210
2211 u8 length64[0x1];
2212 u8 bsf_en[0x1];
2213 u8 sync_umr[0x1];
2214 u8 reserved_4[0x2];
2215 u8 expected_sigerr_count[0x1];
2216 u8 reserved_5[0x1];
2217 u8 en_rinval[0x1];
2218 u8 pd[0x18];
2219
2220 u8 start_addr[0x40];
2221
2222 u8 len[0x40];
2223
2224 u8 bsf_octword_size[0x20];
2225
2226 u8 reserved_6[0x80];
2227
2228 u8 translations_octword_size[0x20];
2229
2230 u8 reserved_7[0x1b];
2231 u8 log_page_size[0x5];
2232
2233 u8 reserved_8[0x20];
2234};
2235
2236struct mlx5_ifc_pkey_bits {
2237 u8 reserved_0[0x10];
2238 u8 pkey[0x10];
2239};
2240
2241struct mlx5_ifc_array128_auto_bits {
2242 u8 array128_auto[16][0x8];
2243};
2244
2245struct mlx5_ifc_hca_vport_context_bits {
2246 u8 field_select[0x20];
2247
2248 u8 reserved_0[0xe0];
2249
2250 u8 sm_virt_aware[0x1];
2251 u8 has_smi[0x1];
2252 u8 has_raw[0x1];
2253 u8 grh_required[0x1];
707c4602
MD		 2254 u8 reserved_1[0xc];
2255 u8 port_physical_state[0x4];
2256 u8 vport_state_policy[0x4];
2257 u8 port_state[0x4];
e281682b
SM		 2258 u8 vport_state[0x4];
2259
707c4602
MD		 2260 u8 reserved_2[0x20];
2261
2262 u8 system_image_guid[0x40];
e281682b
SM		 2263
2264 u8 port_guid[0x40];
2265
2266 u8 node_guid[0x40];
2267
2268 u8 cap_mask1[0x20];
2269
2270 u8 cap_mask1_field_select[0x20];
2271
2272 u8 cap_mask2[0x20];
2273
2274 u8 cap_mask2_field_select[0x20];
2275
2276 u8 reserved_3[0x80];
2277
2278 u8 lid[0x10];
2279 u8 reserved_4[0x4];
2280 u8 init_type_reply[0x4];
2281 u8 lmc[0x3];
2282 u8 subnet_timeout[0x5];
2283
2284 u8 sm_lid[0x10];
2285 u8 sm_sl[0x4];
2286 u8 reserved_5[0xc];
2287
2288 u8 qkey_violation_counter[0x10];
2289 u8 pkey_violation_counter[0x10];
2290
2291 u8 reserved_6[0xca0];
2292};
2293
2294enum {
2295 MLX5_EQC_STATUS_OK = 0x0,
2296 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
2297};
2298
2299enum {
2300 MLX5_EQC_ST_ARMED = 0x9,
2301 MLX5_EQC_ST_FIRED = 0xa,
2302};
2303
2304struct mlx5_ifc_eqc_bits {
2305 u8 status[0x4];
2306 u8 reserved_0[0x9];
2307 u8 ec[0x1];
2308 u8 oi[0x1];
2309 u8 reserved_1[0x5];
2310 u8 st[0x4];
2311 u8 reserved_2[0x8];
2312
2313 u8 reserved_3[0x20];
2314
2315 u8 reserved_4[0x14];
2316 u8 page_offset[0x6];
2317 u8 reserved_5[0x6];
2318
2319 u8 reserved_6[0x3];
2320 u8 log_eq_size[0x5];
2321 u8 uar_page[0x18];
2322
2323 u8 reserved_7[0x20];
2324
2325 u8 reserved_8[0x18];
2326 u8 intr[0x8];
2327
2328 u8 reserved_9[0x3];
2329 u8 log_page_size[0x5];
2330 u8 reserved_10[0x18];
2331
2332 u8 reserved_11[0x60];
2333
2334 u8 reserved_12[0x8];
2335 u8 consumer_counter[0x18];
2336
2337 u8 reserved_13[0x8];
2338 u8 producer_counter[0x18];
2339
2340 u8 reserved_14[0x80];
2341};
2342
2343enum {
2344 MLX5_DCTC_STATE_ACTIVE = 0x0,
2345 MLX5_DCTC_STATE_DRAINING = 0x1,
2346 MLX5_DCTC_STATE_DRAINED = 0x2,
2347};
2348
2349enum {
2350 MLX5_DCTC_CS_RES_DISABLE = 0x0,
2351 MLX5_DCTC_CS_RES_NA = 0x1,
2352 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
2353};
2354
2355enum {
2356 MLX5_DCTC_MTU_256_BYTES = 0x1,
2357 MLX5_DCTC_MTU_512_BYTES = 0x2,
2358 MLX5_DCTC_MTU_1K_BYTES = 0x3,
2359 MLX5_DCTC_MTU_2K_BYTES = 0x4,
2360 MLX5_DCTC_MTU_4K_BYTES = 0x5,
2361};
2362
2363struct mlx5_ifc_dctc_bits {
2364 u8 reserved_0[0x4];
2365 u8 state[0x4];
2366 u8 reserved_1[0x18];
2367
2368 u8 reserved_2[0x8];
2369 u8 user_index[0x18];
2370
2371 u8 reserved_3[0x8];
2372 u8 cqn[0x18];
2373
2374 u8 counter_set_id[0x8];
2375 u8 atomic_mode[0x4];
2376 u8 rre[0x1];
2377 u8 rwe[0x1];
2378 u8 rae[0x1];
2379 u8 atomic_like_write_en[0x1];
2380 u8 latency_sensitive[0x1];
2381 u8 rlky[0x1];
2382 u8 free_ar[0x1];
2383 u8 reserved_4[0xd];
2384
2385 u8 reserved_5[0x8];
2386 u8 cs_res[0x8];
2387 u8 reserved_6[0x3];
2388 u8 min_rnr_nak[0x5];
2389 u8 reserved_7[0x8];
2390
2391 u8 reserved_8[0x8];
2392 u8 srqn[0x18];
2393
2394 u8 reserved_9[0x8];
2395 u8 pd[0x18];
2396
2397 u8 tclass[0x8];
2398 u8 reserved_10[0x4];
2399 u8 flow_label[0x14];
2400
2401 u8 dc_access_key[0x40];
2402
2403 u8 reserved_11[0x5];
2404 u8 mtu[0x3];
2405 u8 port[0x8];
2406 u8 pkey_index[0x10];
2407
2408 u8 reserved_12[0x8];
2409 u8 my_addr_index[0x8];
2410 u8 reserved_13[0x8];
2411 u8 hop_limit[0x8];
2412
2413 u8 dc_access_key_violation_count[0x20];
2414
2415 u8 reserved_14[0x14];
2416 u8 dei_cfi[0x1];
2417 u8 eth_prio[0x3];
2418 u8 ecn[0x2];
2419 u8 dscp[0x6];
2420
2421 u8 reserved_15[0x40];
2422};
2423
2424enum {
2425 MLX5_CQC_STATUS_OK = 0x0,
2426 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
2427 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
2428};
2429
2430enum {
2431 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
2432 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
2433};
2434
2435enum {
2436 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
2437 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
2438 MLX5_CQC_ST_FIRED = 0xa,
2439};
2440
2441struct mlx5_ifc_cqc_bits {
2442 u8 status[0x4];
2443 u8 reserved_0[0x4];
2444 u8 cqe_sz[0x3];
2445 u8 cc[0x1];
2446 u8 reserved_1[0x1];
2447 u8 scqe_break_moderation_en[0x1];
2448 u8 oi[0x1];
2449 u8 reserved_2[0x2];
2450 u8 cqe_zip_en[0x1];
2451 u8 mini_cqe_res_format[0x2];
2452 u8 st[0x4];
2453 u8 reserved_3[0x8];
2454
2455 u8 reserved_4[0x20];
2456
2457 u8 reserved_5[0x14];
2458 u8 page_offset[0x6];
2459 u8 reserved_6[0x6];
2460
2461 u8 reserved_7[0x3];
2462 u8 log_cq_size[0x5];
2463 u8 uar_page[0x18];
2464
2465 u8 reserved_8[0x4];
2466 u8 cq_period[0xc];
2467 u8 cq_max_count[0x10];
2468
2469 u8 reserved_9[0x18];
2470 u8 c_eqn[0x8];
2471
2472 u8 reserved_10[0x3];
2473 u8 log_page_size[0x5];
2474 u8 reserved_11[0x18];
2475
2476 u8 reserved_12[0x20];
2477
2478 u8 reserved_13[0x8];
2479 u8 last_notified_index[0x18];
2480
2481 u8 reserved_14[0x8];
2482 u8 last_solicit_index[0x18];
2483
2484 u8 reserved_15[0x8];
2485 u8 consumer_counter[0x18];
2486
2487 u8 reserved_16[0x8];
2488 u8 producer_counter[0x18];
2489
2490 u8 reserved_17[0x40];
2491
2492 u8 dbr_addr[0x40];
2493};
2494
2495union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2496 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2497 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2498 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2499 u8 reserved_0[0x800];
2500};
2501
2502struct mlx5_ifc_query_adapter_param_block_bits {
211e6c80 2503 u8 reserved_0[0xc0];
e281682b 2504
211e6c80
MD		 2505 u8 reserved_1[0x8];
2506 u8 ieee_vendor_id[0x18];
2507
2508 u8 reserved_2[0x10];
e281682b
SM		 2509 u8 vsd_vendor_id[0x10];
2510
2511 u8 vsd[208][0x8];
2512
2513 u8 vsd_contd_psid[16][0x8];
2514};
2515
2516union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2517 struct mlx5_ifc_modify_field_select_bits modify_field_select;
2518 struct mlx5_ifc_resize_field_select_bits resize_field_select;
2519 u8 reserved_0[0x20];
2520};
2521
2522union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2523 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2524 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2525 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
2526 u8 reserved_0[0x20];
2527};
2528
2529union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
2530 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
2531 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
2532 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
2533 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
2534 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
2535 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
2536 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
2537 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
2538 u8 reserved_0[0x7c0];
2539};
2540
2541union mlx5_ifc_event_auto_bits {
2542 struct mlx5_ifc_comp_event_bits comp_event;
2543 struct mlx5_ifc_dct_events_bits dct_events;
2544 struct mlx5_ifc_qp_events_bits qp_events;
2545 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
2546 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
2547 struct mlx5_ifc_cq_error_bits cq_error;
2548 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
2549 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
2550 struct mlx5_ifc_gpio_event_bits gpio_event;
2551 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
2552 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
2553 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
2554 u8 reserved_0[0xe0];
2555};
2556
2557struct mlx5_ifc_health_buffer_bits {
2558 u8 reserved_0[0x100];
2559
2560 u8 assert_existptr[0x20];
2561
2562 u8 assert_callra[0x20];
2563
2564 u8 reserved_1[0x40];
2565
2566 u8 fw_version[0x20];
2567
2568 u8 hw_id[0x20];
2569
2570 u8 reserved_2[0x20];
2571
2572 u8 irisc_index[0x8];
2573 u8 synd[0x8];
2574 u8 ext_synd[0x10];
2575};
2576
2577struct mlx5_ifc_register_loopback_control_bits {
2578 u8 no_lb[0x1];
2579 u8 reserved_0[0x7];
2580 u8 port[0x8];
2581 u8 reserved_1[0x10];
2582
2583 u8 reserved_2[0x60];
2584};
2585
2586struct mlx5_ifc_teardown_hca_out_bits {
2587 u8 status[0x8];
2588 u8 reserved_0[0x18];
2589
2590 u8 syndrome[0x20];
2591
2592 u8 reserved_1[0x40];
2593};
2594
2595enum {
2596 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
2597 MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE = 0x1,
2598};
2599
2600struct mlx5_ifc_teardown_hca_in_bits {
2601 u8 opcode[0x10];
2602 u8 reserved_0[0x10];
2603
2604 u8 reserved_1[0x10];
2605 u8 op_mod[0x10];
2606
2607 u8 reserved_2[0x10];
2608 u8 profile[0x10];
2609
2610 u8 reserved_3[0x20];
2611};
2612
2613struct mlx5_ifc_sqerr2rts_qp_out_bits {
2614 u8 status[0x8];
2615 u8 reserved_0[0x18];
2616
2617 u8 syndrome[0x20];
2618
2619 u8 reserved_1[0x40];
2620};
2621
2622struct mlx5_ifc_sqerr2rts_qp_in_bits {
2623 u8 opcode[0x10];
2624 u8 reserved_0[0x10];
2625
2626 u8 reserved_1[0x10];
2627 u8 op_mod[0x10];
2628
2629 u8 reserved_2[0x8];
2630 u8 qpn[0x18];
2631
2632 u8 reserved_3[0x20];
2633
2634 u8 opt_param_mask[0x20];
2635
2636 u8 reserved_4[0x20];
2637
2638 struct mlx5_ifc_qpc_bits qpc;
2639
2640 u8 reserved_5[0x80];
2641};
2642
2643struct mlx5_ifc_sqd2rts_qp_out_bits {
2644 u8 status[0x8];
2645 u8 reserved_0[0x18];
2646
2647 u8 syndrome[0x20];
2648
2649 u8 reserved_1[0x40];
2650};
2651
2652struct mlx5_ifc_sqd2rts_qp_in_bits {
2653 u8 opcode[0x10];
2654 u8 reserved_0[0x10];
2655
2656 u8 reserved_1[0x10];
2657 u8 op_mod[0x10];
2658
2659 u8 reserved_2[0x8];
2660 u8 qpn[0x18];
2661
2662 u8 reserved_3[0x20];
2663
2664 u8 opt_param_mask[0x20];
2665
2666 u8 reserved_4[0x20];
2667
2668 struct mlx5_ifc_qpc_bits qpc;
2669
2670 u8 reserved_5[0x80];
2671};
2672
2673struct mlx5_ifc_set_roce_address_out_bits {
2674 u8 status[0x8];
2675 u8 reserved_0[0x18];
2676
2677 u8 syndrome[0x20];
2678
2679 u8 reserved_1[0x40];
2680};
2681
2682struct mlx5_ifc_set_roce_address_in_bits {
2683 u8 opcode[0x10];
2684 u8 reserved_0[0x10];
2685
2686 u8 reserved_1[0x10];
2687 u8 op_mod[0x10];
2688
2689 u8 roce_address_index[0x10];
2690 u8 reserved_2[0x10];
2691
2692 u8 reserved_3[0x20];
2693
2694 struct mlx5_ifc_roce_addr_layout_bits roce_address;
2695};
2696
2697struct mlx5_ifc_set_mad_demux_out_bits {
2698 u8 status[0x8];
2699 u8 reserved_0[0x18];
2700
2701 u8 syndrome[0x20];
2702
2703 u8 reserved_1[0x40];
2704};
2705
2706enum {
2707 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
2708 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
2709};
2710
2711struct mlx5_ifc_set_mad_demux_in_bits {
2712 u8 opcode[0x10];
2713 u8 reserved_0[0x10];
2714
2715 u8 reserved_1[0x10];
2716 u8 op_mod[0x10];
2717
2718 u8 reserved_2[0x20];
2719
2720 u8 reserved_3[0x6];
2721 u8 demux_mode[0x2];
2722 u8 reserved_4[0x18];
2723};
2724
2725struct mlx5_ifc_set_l2_table_entry_out_bits {
2726 u8 status[0x8];
2727 u8 reserved_0[0x18];
2728
2729 u8 syndrome[0x20];
2730
2731 u8 reserved_1[0x40];
2732};
2733
2734struct mlx5_ifc_set_l2_table_entry_in_bits {
2735 u8 opcode[0x10];
2736 u8 reserved_0[0x10];
2737
2738 u8 reserved_1[0x10];
2739 u8 op_mod[0x10];
2740
2741 u8 reserved_2[0x60];
2742
2743 u8 reserved_3[0x8];
2744 u8 table_index[0x18];
2745
2746 u8 reserved_4[0x20];
2747
2748 u8 reserved_5[0x13];
2749 u8 vlan_valid[0x1];
2750 u8 vlan[0xc];
2751
2752 struct mlx5_ifc_mac_address_layout_bits mac_address;
2753
2754 u8 reserved_6[0xc0];
2755};
2756
2757struct mlx5_ifc_set_issi_out_bits {
2758 u8 status[0x8];
2759 u8 reserved_0[0x18];
2760
2761 u8 syndrome[0x20];
2762
2763 u8 reserved_1[0x40];
2764};
2765
2766struct mlx5_ifc_set_issi_in_bits {
2767 u8 opcode[0x10];
2768 u8 reserved_0[0x10];
2769
2770 u8 reserved_1[0x10];
2771 u8 op_mod[0x10];
2772
2773 u8 reserved_2[0x10];
2774 u8 current_issi[0x10];
2775
2776 u8 reserved_3[0x20];
2777};
2778
2779struct mlx5_ifc_set_hca_cap_out_bits {
2780 u8 status[0x8];
2781 u8 reserved_0[0x18];
2782
2783 u8 syndrome[0x20];
2784
2785 u8 reserved_1[0x40];
2786};
2787
2788struct mlx5_ifc_set_hca_cap_in_bits {
2789 u8 opcode[0x10];
2790 u8 reserved_0[0x10];
2791
2792 u8 reserved_1[0x10];
2793 u8 op_mod[0x10];
2794
2795 u8 reserved_2[0x40];
2796
2797 union mlx5_ifc_hca_cap_union_bits capability;
2798};
2799
2800struct mlx5_ifc_set_fte_out_bits {
2801 u8 status[0x8];
2802 u8 reserved_0[0x18];
2803
2804 u8 syndrome[0x20];
2805
2806 u8 reserved_1[0x40];
2807};
2808
2809struct mlx5_ifc_set_fte_in_bits {
2810 u8 opcode[0x10];
2811 u8 reserved_0[0x10];
2812
2813 u8 reserved_1[0x10];
2814 u8 op_mod[0x10];
2815
2816 u8 reserved_2[0x40];
2817
2818 u8 table_type[0x8];
2819 u8 reserved_3[0x18];
2820
2821 u8 reserved_4[0x8];
2822 u8 table_id[0x18];
2823
2824 u8 reserved_5[0x40];
2825
2826 u8 flow_index[0x20];
2827
2828 u8 reserved_6[0xe0];
2829
2830 struct mlx5_ifc_flow_context_bits flow_context;
2831};
2832
2833struct mlx5_ifc_rts2rts_qp_out_bits {
2834 u8 status[0x8];
2835 u8 reserved_0[0x18];
2836
2837 u8 syndrome[0x20];
2838
2839 u8 reserved_1[0x40];
2840};
2841
2842struct mlx5_ifc_rts2rts_qp_in_bits {
2843 u8 opcode[0x10];
2844 u8 reserved_0[0x10];
2845
2846 u8 reserved_1[0x10];
2847 u8 op_mod[0x10];
2848
2849 u8 reserved_2[0x8];
2850 u8 qpn[0x18];
2851
2852 u8 reserved_3[0x20];
2853
2854 u8 opt_param_mask[0x20];
2855
2856 u8 reserved_4[0x20];
2857
2858 struct mlx5_ifc_qpc_bits qpc;
2859
2860 u8 reserved_5[0x80];
2861};
2862
2863struct mlx5_ifc_rtr2rts_qp_out_bits {
2864 u8 status[0x8];
2865 u8 reserved_0[0x18];
2866
2867 u8 syndrome[0x20];
2868
2869 u8 reserved_1[0x40];
2870};
2871
2872struct mlx5_ifc_rtr2rts_qp_in_bits {
2873 u8 opcode[0x10];
2874 u8 reserved_0[0x10];
2875
2876 u8 reserved_1[0x10];
2877 u8 op_mod[0x10];
2878
2879 u8 reserved_2[0x8];
2880 u8 qpn[0x18];
2881
2882 u8 reserved_3[0x20];
2883
2884 u8 opt_param_mask[0x20];
2885
2886 u8 reserved_4[0x20];
2887
2888 struct mlx5_ifc_qpc_bits qpc;
2889
2890 u8 reserved_5[0x80];
2891};
2892
2893struct mlx5_ifc_rst2init_qp_out_bits {
2894 u8 status[0x8];
2895 u8 reserved_0[0x18];
2896
2897 u8 syndrome[0x20];
2898
2899 u8 reserved_1[0x40];
2900};
2901
2902struct mlx5_ifc_rst2init_qp_in_bits {
2903 u8 opcode[0x10];
2904 u8 reserved_0[0x10];
2905
2906 u8 reserved_1[0x10];
2907 u8 op_mod[0x10];
2908
2909 u8 reserved_2[0x8];
2910 u8 qpn[0x18];
2911
2912 u8 reserved_3[0x20];
2913
2914 u8 opt_param_mask[0x20];
2915
2916 u8 reserved_4[0x20];
2917
2918 struct mlx5_ifc_qpc_bits qpc;
2919
2920 u8 reserved_5[0x80];
2921};
2922
2923struct mlx5_ifc_query_xrc_srq_out_bits {
2924 u8 status[0x8];
2925 u8 reserved_0[0x18];
2926
2927 u8 syndrome[0x20];
2928
2929 u8 reserved_1[0x40];
2930
2931 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
2932
2933 u8 reserved_2[0x600];
2934
2935 u8 pas[0][0x40];
2936};
2937
2938struct mlx5_ifc_query_xrc_srq_in_bits {
2939 u8 opcode[0x10];
2940 u8 reserved_0[0x10];
2941
2942 u8 reserved_1[0x10];
2943 u8 op_mod[0x10];
2944
2945 u8 reserved_2[0x8];
2946 u8 xrc_srqn[0x18];
2947
2948 u8 reserved_3[0x20];
2949};
2950
2951enum {
2952 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
2953 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
2954};
2955
2956struct mlx5_ifc_query_vport_state_out_bits {
2957 u8 status[0x8];
2958 u8 reserved_0[0x18];
2959
2960 u8 syndrome[0x20];
2961
2962 u8 reserved_1[0x20];
2963
2964 u8 reserved_2[0x18];
2965 u8 admin_state[0x4];
2966 u8 state[0x4];
2967};
2968
2969enum {
2970 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0,
e7546514 2971 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1,
e281682b
SM		 2972};
2973
2974struct mlx5_ifc_query_vport_state_in_bits {
2975 u8 opcode[0x10];
2976 u8 reserved_0[0x10];
2977
2978 u8 reserved_1[0x10];
2979 u8 op_mod[0x10];
2980
2981 u8 other_vport[0x1];
2982 u8 reserved_2[0xf];
2983 u8 vport_number[0x10];
2984
2985 u8 reserved_3[0x20];
2986};
2987
2988struct mlx5_ifc_query_vport_counter_out_bits {
2989 u8 status[0x8];
2990 u8 reserved_0[0x18];
2991
2992 u8 syndrome[0x20];
2993
2994 u8 reserved_1[0x40];
2995
2996 struct mlx5_ifc_traffic_counter_bits received_errors;
2997
2998 struct mlx5_ifc_traffic_counter_bits transmit_errors;
2999
3000 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3001
3002 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3003
3004 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3005
3006 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3007
3008 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3009
3010 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3011
3012 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3013
3014 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3015
3016 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3017
3018 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3019
3020 u8 reserved_2[0xa00];
3021};
3022
3023enum {
3024 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
3025};
3026
3027struct mlx5_ifc_query_vport_counter_in_bits {
3028 u8 opcode[0x10];
3029 u8 reserved_0[0x10];
3030
3031 u8 reserved_1[0x10];
3032 u8 op_mod[0x10];
3033
3034 u8 other_vport[0x1];
3035 u8 reserved_2[0xf];
3036 u8 vport_number[0x10];
3037
3038 u8 reserved_3[0x60];
3039
3040 u8 clear[0x1];
3041 u8 reserved_4[0x1f];
3042
3043 u8 reserved_5[0x20];
3044};
3045
3046struct mlx5_ifc_query_tis_out_bits {
3047 u8 status[0x8];
3048 u8 reserved_0[0x18];
3049
3050 u8 syndrome[0x20];
3051
3052 u8 reserved_1[0x40];
3053
3054 struct mlx5_ifc_tisc_bits tis_context;
3055};
3056
3057struct mlx5_ifc_query_tis_in_bits {
3058 u8 opcode[0x10];
3059 u8 reserved_0[0x10];
3060
3061 u8 reserved_1[0x10];
3062 u8 op_mod[0x10];
3063
3064 u8 reserved_2[0x8];
3065 u8 tisn[0x18];
3066
3067 u8 reserved_3[0x20];
3068};
3069
3070struct mlx5_ifc_query_tir_out_bits {
3071 u8 status[0x8];
3072 u8 reserved_0[0x18];
3073
3074 u8 syndrome[0x20];
3075
3076 u8 reserved_1[0xc0];
3077
3078 struct mlx5_ifc_tirc_bits tir_context;
3079};
3080
3081struct mlx5_ifc_query_tir_in_bits {
3082 u8 opcode[0x10];
3083 u8 reserved_0[0x10];
3084
3085 u8 reserved_1[0x10];
3086 u8 op_mod[0x10];
3087
3088 u8 reserved_2[0x8];
3089 u8 tirn[0x18];
3090
3091 u8 reserved_3[0x20];
3092};
3093
3094struct mlx5_ifc_query_srq_out_bits {
3095 u8 status[0x8];
3096 u8 reserved_0[0x18];
3097
3098 u8 syndrome[0x20];
3099
3100 u8 reserved_1[0x40];
3101
3102 struct mlx5_ifc_srqc_bits srq_context_entry;
3103
3104 u8 reserved_2[0x600];
3105
3106 u8 pas[0][0x40];
3107};
3108
3109struct mlx5_ifc_query_srq_in_bits {
3110 u8 opcode[0x10];
3111 u8 reserved_0[0x10];
3112
3113 u8 reserved_1[0x10];
3114 u8 op_mod[0x10];
3115
3116 u8 reserved_2[0x8];
3117 u8 srqn[0x18];
3118
3119 u8 reserved_3[0x20];
3120};
3121
3122struct mlx5_ifc_query_sq_out_bits {
3123 u8 status[0x8];
3124 u8 reserved_0[0x18];
3125
3126 u8 syndrome[0x20];
3127
3128 u8 reserved_1[0xc0];
3129
3130 struct mlx5_ifc_sqc_bits sq_context;
3131};
3132
3133struct mlx5_ifc_query_sq_in_bits {
3134 u8 opcode[0x10];
3135 u8 reserved_0[0x10];
3136
3137 u8 reserved_1[0x10];
3138 u8 op_mod[0x10];
3139
3140 u8 reserved_2[0x8];
3141 u8 sqn[0x18];
3142
3143 u8 reserved_3[0x20];
3144};
3145
3146struct mlx5_ifc_query_special_contexts_out_bits {
3147 u8 status[0x8];
3148 u8 reserved_0[0x18];
3149
3150 u8 syndrome[0x20];
3151
3152 u8 reserved_1[0x20];
3153
3154 u8 resd_lkey[0x20];
3155};
3156
3157struct mlx5_ifc_query_special_contexts_in_bits {
3158 u8 opcode[0x10];
3159 u8 reserved_0[0x10];
3160
3161 u8 reserved_1[0x10];
3162 u8 op_mod[0x10];
3163
3164 u8 reserved_2[0x40];
3165};
3166
3167struct mlx5_ifc_query_rqt_out_bits {
3168 u8 status[0x8];
3169 u8 reserved_0[0x18];
3170
3171 u8 syndrome[0x20];
3172
3173 u8 reserved_1[0xc0];
3174
3175 struct mlx5_ifc_rqtc_bits rqt_context;
3176};
3177
3178struct mlx5_ifc_query_rqt_in_bits {
3179 u8 opcode[0x10];
3180 u8 reserved_0[0x10];
3181
3182 u8 reserved_1[0x10];
3183 u8 op_mod[0x10];
3184
3185 u8 reserved_2[0x8];
3186 u8 rqtn[0x18];
3187
3188 u8 reserved_3[0x20];
3189};
3190
3191struct mlx5_ifc_query_rq_out_bits {
3192 u8 status[0x8];
3193 u8 reserved_0[0x18];
3194
3195 u8 syndrome[0x20];
3196
3197 u8 reserved_1[0xc0];
3198
3199 struct mlx5_ifc_rqc_bits rq_context;
3200};
3201
3202struct mlx5_ifc_query_rq_in_bits {
3203 u8 opcode[0x10];
3204 u8 reserved_0[0x10];
3205
3206 u8 reserved_1[0x10];
3207 u8 op_mod[0x10];
3208
3209 u8 reserved_2[0x8];
3210 u8 rqn[0x18];
3211
3212 u8 reserved_3[0x20];
3213};
3214
3215struct mlx5_ifc_query_roce_address_out_bits {
3216 u8 status[0x8];
3217 u8 reserved_0[0x18];
3218
3219 u8 syndrome[0x20];
3220
3221 u8 reserved_1[0x40];
3222
3223 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3224};
3225
3226struct mlx5_ifc_query_roce_address_in_bits {
3227 u8 opcode[0x10];
3228 u8 reserved_0[0x10];
3229
3230 u8 reserved_1[0x10];
3231 u8 op_mod[0x10];
3232
3233 u8 roce_address_index[0x10];
3234 u8 reserved_2[0x10];
3235
3236 u8 reserved_3[0x20];
3237};
3238
3239struct mlx5_ifc_query_rmp_out_bits {
3240 u8 status[0x8];
3241 u8 reserved_0[0x18];
3242
3243 u8 syndrome[0x20];
3244
3245 u8 reserved_1[0xc0];
3246
3247 struct mlx5_ifc_rmpc_bits rmp_context;
3248};
3249
3250struct mlx5_ifc_query_rmp_in_bits {
3251 u8 opcode[0x10];
3252 u8 reserved_0[0x10];
3253
3254 u8 reserved_1[0x10];
3255 u8 op_mod[0x10];
3256
3257 u8 reserved_2[0x8];
3258 u8 rmpn[0x18];
3259
3260 u8 reserved_3[0x20];
3261};
3262
3263struct mlx5_ifc_query_qp_out_bits {
3264 u8 status[0x8];
3265 u8 reserved_0[0x18];
3266
3267 u8 syndrome[0x20];
3268
3269 u8 reserved_1[0x40];
3270
3271 u8 opt_param_mask[0x20];
3272
3273 u8 reserved_2[0x20];
3274
3275 struct mlx5_ifc_qpc_bits qpc;
3276
3277 u8 reserved_3[0x80];
3278
3279 u8 pas[0][0x40];
3280};
3281
3282struct mlx5_ifc_query_qp_in_bits {
3283 u8 opcode[0x10];
3284 u8 reserved_0[0x10];
3285
3286 u8 reserved_1[0x10];
3287 u8 op_mod[0x10];
3288
3289 u8 reserved_2[0x8];
3290 u8 qpn[0x18];
3291
3292 u8 reserved_3[0x20];
3293};
3294
3295struct mlx5_ifc_query_q_counter_out_bits {
3296 u8 status[0x8];
3297 u8 reserved_0[0x18];
3298
3299 u8 syndrome[0x20];
3300
3301 u8 reserved_1[0x40];
3302
3303 u8 rx_write_requests[0x20];
3304
3305 u8 reserved_2[0x20];
3306
3307 u8 rx_read_requests[0x20];
3308
3309 u8 reserved_3[0x20];
3310
3311 u8 rx_atomic_requests[0x20];
3312
3313 u8 reserved_4[0x20];
3314
3315 u8 rx_dct_connect[0x20];
3316
3317 u8 reserved_5[0x20];
3318
3319 u8 out_of_buffer[0x20];
3320
3321 u8 reserved_6[0x20];
3322
3323 u8 out_of_sequence[0x20];
3324
3325 u8 reserved_7[0x620];
3326};
3327
3328struct mlx5_ifc_query_q_counter_in_bits {
3329 u8 opcode[0x10];
3330 u8 reserved_0[0x10];
3331
3332 u8 reserved_1[0x10];
3333 u8 op_mod[0x10];
3334
3335 u8 reserved_2[0x80];
3336
3337 u8 clear[0x1];
3338 u8 reserved_3[0x1f];
3339
3340 u8 reserved_4[0x18];
3341 u8 counter_set_id[0x8];
3342};
3343
3344struct mlx5_ifc_query_pages_out_bits {
3345 u8 status[0x8];
3346 u8 reserved_0[0x18];
3347
3348 u8 syndrome[0x20];
3349
3350 u8 reserved_1[0x10];
3351 u8 function_id[0x10];
3352
3353 u8 num_pages[0x20];
3354};
3355
3356enum {
3357 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
3358 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
3359 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
3360};
3361
3362struct mlx5_ifc_query_pages_in_bits {
3363 u8 opcode[0x10];
3364 u8 reserved_0[0x10];
3365
3366 u8 reserved_1[0x10];
3367 u8 op_mod[0x10];
3368
3369 u8 reserved_2[0x10];
3370 u8 function_id[0x10];
3371
3372 u8 reserved_3[0x20];
3373};
3374
3375struct mlx5_ifc_query_nic_vport_context_out_bits {
3376 u8 status[0x8];
3377 u8 reserved_0[0x18];
3378
3379 u8 syndrome[0x20];
3380
3381 u8 reserved_1[0x40];
3382
3383 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
3384};
3385
3386struct mlx5_ifc_query_nic_vport_context_in_bits {
3387 u8 opcode[0x10];
3388 u8 reserved_0[0x10];
3389
3390 u8 reserved_1[0x10];
3391 u8 op_mod[0x10];
3392
3393 u8 other_vport[0x1];
3394 u8 reserved_2[0xf];
3395 u8 vport_number[0x10];
3396
3397 u8 reserved_3[0x5];
3398 u8 allowed_list_type[0x3];
3399 u8 reserved_4[0x18];
3400};
3401
3402struct mlx5_ifc_query_mkey_out_bits {
3403 u8 status[0x8];
3404 u8 reserved_0[0x18];
3405
3406 u8 syndrome[0x20];
3407
3408 u8 reserved_1[0x40];
3409
3410 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
3411
3412 u8 reserved_2[0x600];
3413
3414 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
3415
3416 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
3417};
3418
3419struct mlx5_ifc_query_mkey_in_bits {
3420 u8 opcode[0x10];
3421 u8 reserved_0[0x10];
3422
3423 u8 reserved_1[0x10];
3424 u8 op_mod[0x10];
3425
3426 u8 reserved_2[0x8];
3427 u8 mkey_index[0x18];
3428
3429 u8 pg_access[0x1];
3430 u8 reserved_3[0x1f];
3431};
3432
3433struct mlx5_ifc_query_mad_demux_out_bits {
3434 u8 status[0x8];
3435 u8 reserved_0[0x18];
3436
3437 u8 syndrome[0x20];
3438
3439 u8 reserved_1[0x40];
3440
3441 u8 mad_dumux_parameters_block[0x20];
3442};
3443
3444struct mlx5_ifc_query_mad_demux_in_bits {
3445 u8 opcode[0x10];
3446 u8 reserved_0[0x10];
3447
3448 u8 reserved_1[0x10];
3449 u8 op_mod[0x10];
3450
3451 u8 reserved_2[0x40];
3452};
3453
3454struct mlx5_ifc_query_l2_table_entry_out_bits {
3455 u8 status[0x8];
3456 u8 reserved_0[0x18];
3457
3458 u8 syndrome[0x20];
3459
3460 u8 reserved_1[0xa0];
3461
3462 u8 reserved_2[0x13];
3463 u8 vlan_valid[0x1];
3464 u8 vlan[0xc];
3465
3466 struct mlx5_ifc_mac_address_layout_bits mac_address;
3467
3468 u8 reserved_3[0xc0];
3469};
3470
3471struct mlx5_ifc_query_l2_table_entry_in_bits {
3472 u8 opcode[0x10];
3473 u8 reserved_0[0x10];
3474
3475 u8 reserved_1[0x10];
3476 u8 op_mod[0x10];
3477
3478 u8 reserved_2[0x60];
3479
3480 u8 reserved_3[0x8];
3481 u8 table_index[0x18];
3482
3483 u8 reserved_4[0x140];
3484};
3485
3486struct mlx5_ifc_query_issi_out_bits {
3487 u8 status[0x8];
3488 u8 reserved_0[0x18];
3489
3490 u8 syndrome[0x20];
3491
3492 u8 reserved_1[0x10];
3493 u8 current_issi[0x10];
3494
3495 u8 reserved_2[0xa0];
3496
3497 u8 supported_issi_reserved[76][0x8];
3498 u8 supported_issi_dw0[0x20];
3499};
3500
3501struct mlx5_ifc_query_issi_in_bits {
3502 u8 opcode[0x10];
3503 u8 reserved_0[0x10];
3504
3505 u8 reserved_1[0x10];
3506 u8 op_mod[0x10];
3507
3508 u8 reserved_2[0x40];
3509};
3510
3511struct mlx5_ifc_query_hca_vport_pkey_out_bits {
3512 u8 status[0x8];
3513 u8 reserved_0[0x18];
3514
3515 u8 syndrome[0x20];
3516
3517 u8 reserved_1[0x40];
3518
3519 struct mlx5_ifc_pkey_bits pkey[0];
3520};
3521
3522struct mlx5_ifc_query_hca_vport_pkey_in_bits {
3523 u8 opcode[0x10];
3524 u8 reserved_0[0x10];
3525
3526 u8 reserved_1[0x10];
3527 u8 op_mod[0x10];
3528
3529 u8 other_vport[0x1];
707c4602
MD		 3530 u8 reserved_2[0xb];
3531 u8 port_num[0x4];
e281682b
SM		 3532 u8 vport_number[0x10];
3533
3534 u8 reserved_3[0x10];
3535 u8 pkey_index[0x10];
3536};
3537
3538struct mlx5_ifc_query_hca_vport_gid_out_bits {
3539 u8 status[0x8];
3540 u8 reserved_0[0x18];
3541
3542 u8 syndrome[0x20];
3543
3544 u8 reserved_1[0x20];
3545
3546 u8 gids_num[0x10];
3547 u8 reserved_2[0x10];
3548
3549 struct mlx5_ifc_array128_auto_bits gid[0];
3550};
3551
3552struct mlx5_ifc_query_hca_vport_gid_in_bits {
3553 u8 opcode[0x10];
3554 u8 reserved_0[0x10];
3555
3556 u8 reserved_1[0x10];
3557 u8 op_mod[0x10];
3558
3559 u8 other_vport[0x1];
707c4602
MD		 3560 u8 reserved_2[0xb];
3561 u8 port_num[0x4];
e281682b
SM		 3562 u8 vport_number[0x10];
3563
3564 u8 reserved_3[0x10];
3565 u8 gid_index[0x10];
3566};
3567
3568struct mlx5_ifc_query_hca_vport_context_out_bits {
3569 u8 status[0x8];
3570 u8 reserved_0[0x18];
3571
3572 u8 syndrome[0x20];
3573
3574 u8 reserved_1[0x40];
3575
3576 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
3577};
3578
3579struct mlx5_ifc_query_hca_vport_context_in_bits {
3580 u8 opcode[0x10];
3581 u8 reserved_0[0x10];
3582
3583 u8 reserved_1[0x10];
3584 u8 op_mod[0x10];
3585
3586 u8 other_vport[0x1];
707c4602
MD		 3587 u8 reserved_2[0xb];
3588 u8 port_num[0x4];
e281682b
SM		 3589 u8 vport_number[0x10];
3590
3591 u8 reserved_3[0x20];
3592};
3593
3594struct mlx5_ifc_query_hca_cap_out_bits {
3595 u8 status[0x8];
3596 u8 reserved_0[0x18];
3597
3598 u8 syndrome[0x20];
3599
3600 u8 reserved_1[0x40];
3601
3602 union mlx5_ifc_hca_cap_union_bits capability;
3603};
3604
3605struct mlx5_ifc_query_hca_cap_in_bits {
3606 u8 opcode[0x10];
3607 u8 reserved_0[0x10];
3608
3609 u8 reserved_1[0x10];
3610 u8 op_mod[0x10];
3611
3612 u8 reserved_2[0x40];
3613};
3614
3615struct mlx5_ifc_query_flow_table_out_bits {
3616 u8 status[0x8];
3617 u8 reserved_0[0x18];
3618
3619 u8 syndrome[0x20];
3620
3621 u8 reserved_1[0x80];
3622
3623 u8 reserved_2[0x8];
3624 u8 level[0x8];
3625 u8 reserved_3[0x8];
3626 u8 log_size[0x8];
3627
3628 u8 reserved_4[0x120];
3629};
3630
3631struct mlx5_ifc_query_flow_table_in_bits {
3632 u8 opcode[0x10];
3633 u8 reserved_0[0x10];
3634
3635 u8 reserved_1[0x10];
3636 u8 op_mod[0x10];
3637
3638 u8 reserved_2[0x40];
3639
3640 u8 table_type[0x8];
3641 u8 reserved_3[0x18];
3642
3643 u8 reserved_4[0x8];
3644 u8 table_id[0x18];
3645
3646 u8 reserved_5[0x140];
3647};
3648
3649struct mlx5_ifc_query_fte_out_bits {
3650 u8 status[0x8];
3651 u8 reserved_0[0x18];
3652
3653 u8 syndrome[0x20];
3654
3655 u8 reserved_1[0x1c0];
3656
3657 struct mlx5_ifc_flow_context_bits flow_context;
3658};
3659
3660struct mlx5_ifc_query_fte_in_bits {
3661 u8 opcode[0x10];
3662 u8 reserved_0[0x10];
3663
3664 u8 reserved_1[0x10];
3665 u8 op_mod[0x10];
3666
3667 u8 reserved_2[0x40];
3668
3669 u8 table_type[0x8];
3670 u8 reserved_3[0x18];
3671
3672 u8 reserved_4[0x8];
3673 u8 table_id[0x18];
3674
3675 u8 reserved_5[0x40];
3676
3677 u8 flow_index[0x20];
3678
3679 u8 reserved_6[0xe0];
3680};
3681
3682enum {
3683 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
3684 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
3685 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
3686};
3687
3688struct mlx5_ifc_query_flow_group_out_bits {
3689 u8 status[0x8];
3690 u8 reserved_0[0x18];
3691
3692 u8 syndrome[0x20];
3693
3694 u8 reserved_1[0xa0];
3695
3696 u8 start_flow_index[0x20];
3697
3698 u8 reserved_2[0x20];
3699
3700 u8 end_flow_index[0x20];
3701
3702 u8 reserved_3[0xa0];
3703
3704 u8 reserved_4[0x18];
3705 u8 match_criteria_enable[0x8];
3706
3707 struct mlx5_ifc_fte_match_param_bits match_criteria;
3708
3709 u8 reserved_5[0xe00];
3710};
3711
3712struct mlx5_ifc_query_flow_group_in_bits {
3713 u8 opcode[0x10];
3714 u8 reserved_0[0x10];
3715
3716 u8 reserved_1[0x10];
3717 u8 op_mod[0x10];
3718
3719 u8 reserved_2[0x40];
3720
3721 u8 table_type[0x8];
3722 u8 reserved_3[0x18];
3723
3724 u8 reserved_4[0x8];
3725 u8 table_id[0x18];
3726
3727 u8 group_id[0x20];
3728
3729 u8 reserved_5[0x120];
3730};
3731
3732struct mlx5_ifc_query_eq_out_bits {
3733 u8 status[0x8];
3734 u8 reserved_0[0x18];
3735
3736 u8 syndrome[0x20];
3737
3738 u8 reserved_1[0x40];
3739
3740 struct mlx5_ifc_eqc_bits eq_context_entry;
3741
3742 u8 reserved_2[0x40];
3743
3744 u8 event_bitmask[0x40];
3745
3746 u8 reserved_3[0x580];
3747
3748 u8 pas[0][0x40];
3749};
3750
3751struct mlx5_ifc_query_eq_in_bits {
3752 u8 opcode[0x10];
3753 u8 reserved_0[0x10];
3754
3755 u8 reserved_1[0x10];
3756 u8 op_mod[0x10];
3757
3758 u8 reserved_2[0x18];
3759 u8 eq_number[0x8];
3760
3761 u8 reserved_3[0x20];
3762};
3763
3764struct mlx5_ifc_query_dct_out_bits {
3765 u8 status[0x8];
3766 u8 reserved_0[0x18];
3767
3768 u8 syndrome[0x20];
3769
3770 u8 reserved_1[0x40];
3771
3772 struct mlx5_ifc_dctc_bits dct_context_entry;
3773
3774 u8 reserved_2[0x180];
3775};
3776
3777struct mlx5_ifc_query_dct_in_bits {
3778 u8 opcode[0x10];
3779 u8 reserved_0[0x10];
3780
3781 u8 reserved_1[0x10];
3782 u8 op_mod[0x10];
3783
3784 u8 reserved_2[0x8];
3785 u8 dctn[0x18];
3786
3787 u8 reserved_3[0x20];
3788};
3789
3790struct mlx5_ifc_query_cq_out_bits {
3791 u8 status[0x8];
3792 u8 reserved_0[0x18];
3793
3794 u8 syndrome[0x20];
3795
3796 u8 reserved_1[0x40];
3797
3798 struct mlx5_ifc_cqc_bits cq_context;
3799
3800 u8 reserved_2[0x600];
3801
3802 u8 pas[0][0x40];
3803};
3804
3805struct mlx5_ifc_query_cq_in_bits {
3806 u8 opcode[0x10];
3807 u8 reserved_0[0x10];
3808
3809 u8 reserved_1[0x10];
3810 u8 op_mod[0x10];
3811
3812 u8 reserved_2[0x8];
3813 u8 cqn[0x18];
3814
3815 u8 reserved_3[0x20];
3816};
3817
3818struct mlx5_ifc_query_cong_status_out_bits {
3819 u8 status[0x8];
3820 u8 reserved_0[0x18];
3821
3822 u8 syndrome[0x20];
3823
3824 u8 reserved_1[0x20];
3825
3826 u8 enable[0x1];
3827 u8 tag_enable[0x1];
3828 u8 reserved_2[0x1e];
3829};
3830
3831struct mlx5_ifc_query_cong_status_in_bits {
3832 u8 opcode[0x10];
3833 u8 reserved_0[0x10];
3834
3835 u8 reserved_1[0x10];
3836 u8 op_mod[0x10];
3837
3838 u8 reserved_2[0x18];
3839 u8 priority[0x4];
3840 u8 cong_protocol[0x4];
3841
3842 u8 reserved_3[0x20];
3843};
3844
3845struct mlx5_ifc_query_cong_statistics_out_bits {
3846 u8 status[0x8];
3847 u8 reserved_0[0x18];
3848
3849 u8 syndrome[0x20];
3850
3851 u8 reserved_1[0x40];
3852
3853 u8 cur_flows[0x20];
3854
3855 u8 sum_flows[0x20];
3856
3857 u8 cnp_ignored_high[0x20];
3858
3859 u8 cnp_ignored_low[0x20];
3860
3861 u8 cnp_handled_high[0x20];
3862
3863 u8 cnp_handled_low[0x20];
3864
3865 u8 reserved_2[0x100];
3866
3867 u8 time_stamp_high[0x20];
3868
3869 u8 time_stamp_low[0x20];
3870
3871 u8 accumulators_period[0x20];
3872
3873 u8 ecn_marked_roce_packets_high[0x20];
3874
3875 u8 ecn_marked_roce_packets_low[0x20];
3876
3877 u8 cnps_sent_high[0x20];
3878
3879 u8 cnps_sent_low[0x20];
3880
3881 u8 reserved_3[0x560];
3882};
3883
3884struct mlx5_ifc_query_cong_statistics_in_bits {
3885 u8 opcode[0x10];
3886 u8 reserved_0[0x10];
3887
3888 u8 reserved_1[0x10];
3889 u8 op_mod[0x10];
3890
3891 u8 clear[0x1];
3892 u8 reserved_2[0x1f];
3893
3894 u8 reserved_3[0x20];
3895};
3896
3897struct mlx5_ifc_query_cong_params_out_bits {
3898 u8 status[0x8];
3899 u8 reserved_0[0x18];
3900
3901 u8 syndrome[0x20];
3902
3903 u8 reserved_1[0x40];
3904
3905 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
3906};
3907
3908struct mlx5_ifc_query_cong_params_in_bits {
3909 u8 opcode[0x10];
3910 u8 reserved_0[0x10];
3911
3912 u8 reserved_1[0x10];
3913 u8 op_mod[0x10];
3914
3915 u8 reserved_2[0x1c];
3916 u8 cong_protocol[0x4];
3917
3918 u8 reserved_3[0x20];
3919};
3920
3921struct mlx5_ifc_query_adapter_out_bits {
3922 u8 status[0x8];
3923 u8 reserved_0[0x18];
3924
3925 u8 syndrome[0x20];
3926
3927 u8 reserved_1[0x40];
3928
3929 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
3930};
3931
3932struct mlx5_ifc_query_adapter_in_bits {
3933 u8 opcode[0x10];
3934 u8 reserved_0[0x10];
3935
3936 u8 reserved_1[0x10];
3937 u8 op_mod[0x10];
3938
3939 u8 reserved_2[0x40];
3940};
3941
3942struct mlx5_ifc_qp_2rst_out_bits {
3943 u8 status[0x8];
3944 u8 reserved_0[0x18];
3945
3946 u8 syndrome[0x20];
3947
3948 u8 reserved_1[0x40];
3949};
3950
3951struct mlx5_ifc_qp_2rst_in_bits {
3952 u8 opcode[0x10];
3953 u8 reserved_0[0x10];
3954
3955 u8 reserved_1[0x10];
3956 u8 op_mod[0x10];
3957
3958 u8 reserved_2[0x8];
3959 u8 qpn[0x18];
3960
3961 u8 reserved_3[0x20];
3962};
3963
3964struct mlx5_ifc_qp_2err_out_bits {
3965 u8 status[0x8];
3966 u8 reserved_0[0x18];
3967
3968 u8 syndrome[0x20];
3969
3970 u8 reserved_1[0x40];
3971};
3972
3973struct mlx5_ifc_qp_2err_in_bits {
3974 u8 opcode[0x10];
3975 u8 reserved_0[0x10];
3976
3977 u8 reserved_1[0x10];
3978 u8 op_mod[0x10];
3979
3980 u8 reserved_2[0x8];
3981 u8 qpn[0x18];
3982
3983 u8 reserved_3[0x20];
3984};
3985
3986struct mlx5_ifc_page_fault_resume_out_bits {
3987 u8 status[0x8];
3988 u8 reserved_0[0x18];
3989
3990 u8 syndrome[0x20];
3991
3992 u8 reserved_1[0x40];
3993};
3994
3995struct mlx5_ifc_page_fault_resume_in_bits {
3996 u8 opcode[0x10];
3997 u8 reserved_0[0x10];
3998
3999 u8 reserved_1[0x10];
4000 u8 op_mod[0x10];
4001
4002 u8 error[0x1];
4003 u8 reserved_2[0x4];
4004 u8 rdma[0x1];
4005 u8 read_write[0x1];
4006 u8 req_res[0x1];
4007 u8 qpn[0x18];
4008
4009 u8 reserved_3[0x20];
4010};
4011
4012struct mlx5_ifc_nop_out_bits {
4013 u8 status[0x8];
4014 u8 reserved_0[0x18];
4015
4016 u8 syndrome[0x20];
4017
4018 u8 reserved_1[0x40];
4019};
4020
4021struct mlx5_ifc_nop_in_bits {
4022 u8 opcode[0x10];
4023 u8 reserved_0[0x10];
4024
4025 u8 reserved_1[0x10];
4026 u8 op_mod[0x10];
4027
4028 u8 reserved_2[0x40];
4029};
4030
4031struct mlx5_ifc_modify_vport_state_out_bits {
4032 u8 status[0x8];
4033 u8 reserved_0[0x18];
4034
4035 u8 syndrome[0x20];
4036
4037 u8 reserved_1[0x40];
4038};
4039
4040struct mlx5_ifc_modify_vport_state_in_bits {
4041 u8 opcode[0x10];
4042 u8 reserved_0[0x10];
4043
4044 u8 reserved_1[0x10];
4045 u8 op_mod[0x10];
4046
4047 u8 other_vport[0x1];
4048 u8 reserved_2[0xf];
4049 u8 vport_number[0x10];
4050
4051 u8 reserved_3[0x18];
4052 u8 admin_state[0x4];
4053 u8 reserved_4[0x4];
4054};
4055
4056struct mlx5_ifc_modify_tis_out_bits {
4057 u8 status[0x8];
4058 u8 reserved_0[0x18];
4059
4060 u8 syndrome[0x20];
4061
4062 u8 reserved_1[0x40];
4063};
4064
4065struct mlx5_ifc_modify_tis_in_bits {
4066 u8 opcode[0x10];
4067 u8 reserved_0[0x10];
4068
4069 u8 reserved_1[0x10];
4070 u8 op_mod[0x10];
4071
4072 u8 reserved_2[0x8];
4073 u8 tisn[0x18];
4074
4075 u8 reserved_3[0x20];
4076
4077 u8 modify_bitmask[0x40];
4078
4079 u8 reserved_4[0x40];
4080
4081 struct mlx5_ifc_tisc_bits ctx;
4082};
4083
d9eea403 4084struct mlx5_ifc_modify_tir_bitmask_bits {
66189961 4085 u8 reserved_0[0x20];
d9eea403 4086
66189961
TT		 4087 u8 reserved_1[0x1b];
4088 u8 self_lb_en[0x1];
4089 u8 reserved_2[0x3];
d9eea403
AS		 4090 u8 lro[0x1];
4091};
4092
e281682b
SM		 4093struct mlx5_ifc_modify_tir_out_bits {
4094 u8 status[0x8];
4095 u8 reserved_0[0x18];
4096
4097 u8 syndrome[0x20];
4098
4099 u8 reserved_1[0x40];
4100};
4101
4102struct mlx5_ifc_modify_tir_in_bits {
4103 u8 opcode[0x10];
4104 u8 reserved_0[0x10];
4105
4106 u8 reserved_1[0x10];
4107 u8 op_mod[0x10];
4108
4109 u8 reserved_2[0x8];
4110 u8 tirn[0x18];
4111
4112 u8 reserved_3[0x20];
4113
d9eea403 4114 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
e281682b
SM		 4115
4116 u8 reserved_4[0x40];
4117
4118 struct mlx5_ifc_tirc_bits ctx;
4119};
4120
4121struct mlx5_ifc_modify_sq_out_bits {
4122 u8 status[0x8];
4123 u8 reserved_0[0x18];
4124
4125 u8 syndrome[0x20];
4126
4127 u8 reserved_1[0x40];
4128};
4129
4130struct mlx5_ifc_modify_sq_in_bits {
4131 u8 opcode[0x10];
4132 u8 reserved_0[0x10];
4133
4134 u8 reserved_1[0x10];
4135 u8 op_mod[0x10];
4136
4137 u8 sq_state[0x4];
4138 u8 reserved_2[0x4];
4139 u8 sqn[0x18];
4140
4141 u8 reserved_3[0x20];
4142
4143 u8 modify_bitmask[0x40];
4144
4145 u8 reserved_4[0x40];
4146
4147 struct mlx5_ifc_sqc_bits ctx;
4148};
4149
4150struct mlx5_ifc_modify_rqt_out_bits {
4151 u8 status[0x8];
4152 u8 reserved_0[0x18];
4153
4154 u8 syndrome[0x20];
4155
4156 u8 reserved_1[0x40];
4157};
4158
5c50368f
AS		 4159struct mlx5_ifc_rqt_bitmask_bits {
4160 u8 reserved[0x20];
4161
4162 u8 reserved1[0x1f];
4163 u8 rqn_list[0x1];
4164};
4165
e281682b
SM		 4166struct mlx5_ifc_modify_rqt_in_bits {
4167 u8 opcode[0x10];
4168 u8 reserved_0[0x10];
4169
4170 u8 reserved_1[0x10];
4171 u8 op_mod[0x10];
4172
4173 u8 reserved_2[0x8];
4174 u8 rqtn[0x18];
4175
4176 u8 reserved_3[0x20];
4177
5c50368f 4178 struct mlx5_ifc_rqt_bitmask_bits bitmask;
e281682b
SM		 4179
4180 u8 reserved_4[0x40];
4181
4182 struct mlx5_ifc_rqtc_bits ctx;
4183};
4184
4185struct mlx5_ifc_modify_rq_out_bits {
4186 u8 status[0x8];
4187 u8 reserved_0[0x18];
4188
4189 u8 syndrome[0x20];
4190
4191 u8 reserved_1[0x40];
4192};
4193
4194struct mlx5_ifc_modify_rq_in_bits {
4195 u8 opcode[0x10];
4196 u8 reserved_0[0x10];
4197
4198 u8 reserved_1[0x10];
4199 u8 op_mod[0x10];
4200
4201 u8 rq_state[0x4];
4202 u8 reserved_2[0x4];
4203 u8 rqn[0x18];
4204
4205 u8 reserved_3[0x20];
4206
4207 u8 modify_bitmask[0x40];
4208
4209 u8 reserved_4[0x40];
4210
4211 struct mlx5_ifc_rqc_bits ctx;
4212};
4213
4214struct mlx5_ifc_modify_rmp_out_bits {
4215 u8 status[0x8];
4216 u8 reserved_0[0x18];
4217
4218 u8 syndrome[0x20];
4219
4220 u8 reserved_1[0x40];
4221};
4222
01949d01
HA		 4223struct mlx5_ifc_rmp_bitmask_bits {
4224 u8 reserved[0x20];
4225
4226 u8 reserved1[0x1f];
4227 u8 lwm[0x1];
4228};
4229
e281682b
SM		 4230struct mlx5_ifc_modify_rmp_in_bits {
4231 u8 opcode[0x10];
4232 u8 reserved_0[0x10];
4233
4234 u8 reserved_1[0x10];
4235 u8 op_mod[0x10];
4236
4237 u8 rmp_state[0x4];
4238 u8 reserved_2[0x4];
4239 u8 rmpn[0x18];
4240
4241 u8 reserved_3[0x20];
4242
01949d01 4243 struct mlx5_ifc_rmp_bitmask_bits bitmask;
e281682b
SM		 4244
4245 u8 reserved_4[0x40];
4246
4247 struct mlx5_ifc_rmpc_bits ctx;
4248};
4249
4250struct mlx5_ifc_modify_nic_vport_context_out_bits {
4251 u8 status[0x8];
4252 u8 reserved_0[0x18];
4253
4254 u8 syndrome[0x20];
4255
4256 u8 reserved_1[0x40];
4257};
4258
4259struct mlx5_ifc_modify_nic_vport_field_select_bits {
d82b7318
SM		 4260 u8 reserved_0[0x19];
4261 u8 mtu[0x1];
4262 u8 change_event[0x1];
4263 u8 promisc[0x1];
e281682b
SM		 4264 u8 permanent_address[0x1];
4265 u8 addresses_list[0x1];
4266 u8 roce_en[0x1];
4267 u8 reserved_1[0x1];
4268};
4269
4270struct mlx5_ifc_modify_nic_vport_context_in_bits {
4271 u8 opcode[0x10];
4272 u8 reserved_0[0x10];
4273
4274 u8 reserved_1[0x10];
4275 u8 op_mod[0x10];
4276
4277 u8 other_vport[0x1];
4278 u8 reserved_2[0xf];
4279 u8 vport_number[0x10];
4280
4281 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
4282
4283 u8 reserved_3[0x780];
4284
4285 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4286};
4287
4288struct mlx5_ifc_modify_hca_vport_context_out_bits {
4289 u8 status[0x8];
4290 u8 reserved_0[0x18];
4291
4292 u8 syndrome[0x20];
4293
4294 u8 reserved_1[0x40];
4295};
4296
4297struct mlx5_ifc_modify_hca_vport_context_in_bits {
4298 u8 opcode[0x10];
4299 u8 reserved_0[0x10];
4300
4301 u8 reserved_1[0x10];
4302 u8 op_mod[0x10];
4303
4304 u8 other_vport[0x1];
707c4602
MD		 4305 u8 reserved_2[0xb];
4306 u8 port_num[0x4];
e281682b
SM		 4307 u8 vport_number[0x10];
4308
4309 u8 reserved_3[0x20];
4310
4311 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4312};
4313
4314struct mlx5_ifc_modify_cq_out_bits {
4315 u8 status[0x8];
4316 u8 reserved_0[0x18];
4317
4318 u8 syndrome[0x20];
4319
4320 u8 reserved_1[0x40];
4321};
4322
4323enum {
4324 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
4325 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
4326};
4327
4328struct mlx5_ifc_modify_cq_in_bits {
4329 u8 opcode[0x10];
4330 u8 reserved_0[0x10];
4331
4332 u8 reserved_1[0x10];
4333 u8 op_mod[0x10];
4334
4335 u8 reserved_2[0x8];
4336 u8 cqn[0x18];
4337
4338 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
4339
4340 struct mlx5_ifc_cqc_bits cq_context;
4341
4342 u8 reserved_3[0x600];
4343
4344 u8 pas[0][0x40];
4345};
4346
4347struct mlx5_ifc_modify_cong_status_out_bits {
4348 u8 status[0x8];
4349 u8 reserved_0[0x18];
4350
4351 u8 syndrome[0x20];
4352
4353 u8 reserved_1[0x40];
4354};
4355
4356struct mlx5_ifc_modify_cong_status_in_bits {
4357 u8 opcode[0x10];
4358 u8 reserved_0[0x10];
4359
4360 u8 reserved_1[0x10];
4361 u8 op_mod[0x10];
4362
4363 u8 reserved_2[0x18];
4364 u8 priority[0x4];
4365 u8 cong_protocol[0x4];
4366
4367 u8 enable[0x1];
4368 u8 tag_enable[0x1];
4369 u8 reserved_3[0x1e];
4370};
4371
4372struct mlx5_ifc_modify_cong_params_out_bits {
4373 u8 status[0x8];
4374 u8 reserved_0[0x18];
4375
4376 u8 syndrome[0x20];
4377
4378 u8 reserved_1[0x40];
4379};
4380
4381struct mlx5_ifc_modify_cong_params_in_bits {
4382 u8 opcode[0x10];
4383 u8 reserved_0[0x10];
4384
4385 u8 reserved_1[0x10];
4386 u8 op_mod[0x10];
4387
4388 u8 reserved_2[0x1c];
4389 u8 cong_protocol[0x4];
4390
4391 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
4392
4393 u8 reserved_3[0x80];
4394
4395 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4396};
4397
4398struct mlx5_ifc_manage_pages_out_bits {
4399 u8 status[0x8];
4400 u8 reserved_0[0x18];
4401
4402 u8 syndrome[0x20];
4403
4404 u8 output_num_entries[0x20];
4405
4406 u8 reserved_1[0x20];
4407
4408 u8 pas[0][0x40];
4409};
4410
4411enum {
4412 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
4413 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
4414 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
4415};
4416
4417struct mlx5_ifc_manage_pages_in_bits {
4418 u8 opcode[0x10];
4419 u8 reserved_0[0x10];
4420
4421 u8 reserved_1[0x10];
4422 u8 op_mod[0x10];
4423
4424 u8 reserved_2[0x10];
4425 u8 function_id[0x10];
4426
4427 u8 input_num_entries[0x20];
4428
4429 u8 pas[0][0x40];
4430};
4431
4432struct mlx5_ifc_mad_ifc_out_bits {
4433 u8 status[0x8];
4434 u8 reserved_0[0x18];
4435
4436 u8 syndrome[0x20];
4437
4438 u8 reserved_1[0x40];
4439
4440 u8 response_mad_packet[256][0x8];
4441};
4442
4443struct mlx5_ifc_mad_ifc_in_bits {
4444 u8 opcode[0x10];
4445 u8 reserved_0[0x10];
4446
4447 u8 reserved_1[0x10];
4448 u8 op_mod[0x10];
4449
4450 u8 remote_lid[0x10];
4451 u8 reserved_2[0x8];
4452 u8 port[0x8];
4453
4454 u8 reserved_3[0x20];
4455
4456 u8 mad[256][0x8];
4457};
4458
4459struct mlx5_ifc_init_hca_out_bits {
4460 u8 status[0x8];
4461 u8 reserved_0[0x18];
4462
4463 u8 syndrome[0x20];
4464
4465 u8 reserved_1[0x40];
4466};
4467
4468struct mlx5_ifc_init_hca_in_bits {
4469 u8 opcode[0x10];
4470 u8 reserved_0[0x10];
4471
4472 u8 reserved_1[0x10];
4473 u8 op_mod[0x10];
4474
4475 u8 reserved_2[0x40];
4476};
4477
4478struct mlx5_ifc_init2rtr_qp_out_bits {
4479 u8 status[0x8];
4480 u8 reserved_0[0x18];
4481
4482 u8 syndrome[0x20];
4483
4484 u8 reserved_1[0x40];
4485};
4486
4487struct mlx5_ifc_init2rtr_qp_in_bits {
4488 u8 opcode[0x10];
4489 u8 reserved_0[0x10];
4490
4491 u8 reserved_1[0x10];
4492 u8 op_mod[0x10];
4493
4494 u8 reserved_2[0x8];
4495 u8 qpn[0x18];
4496
4497 u8 reserved_3[0x20];
4498
4499 u8 opt_param_mask[0x20];
4500
4501 u8 reserved_4[0x20];
4502
4503 struct mlx5_ifc_qpc_bits qpc;
4504
4505 u8 reserved_5[0x80];
4506};
4507
4508struct mlx5_ifc_init2init_qp_out_bits {
4509 u8 status[0x8];
4510 u8 reserved_0[0x18];
4511
4512 u8 syndrome[0x20];
4513
4514 u8 reserved_1[0x40];
4515};
4516
4517struct mlx5_ifc_init2init_qp_in_bits {
4518 u8 opcode[0x10];
4519 u8 reserved_0[0x10];
4520
4521 u8 reserved_1[0x10];
4522 u8 op_mod[0x10];
4523
4524 u8 reserved_2[0x8];
4525 u8 qpn[0x18];
4526
4527 u8 reserved_3[0x20];
4528
4529 u8 opt_param_mask[0x20];
4530
4531 u8 reserved_4[0x20];
4532
4533 struct mlx5_ifc_qpc_bits qpc;
4534
4535 u8 reserved_5[0x80];
4536};
4537
4538struct mlx5_ifc_get_dropped_packet_log_out_bits {
4539 u8 status[0x8];
4540 u8 reserved_0[0x18];
4541
4542 u8 syndrome[0x20];
4543
4544 u8 reserved_1[0x40];
4545
4546 u8 packet_headers_log[128][0x8];
4547
4548 u8 packet_syndrome[64][0x8];
4549};
4550
4551struct mlx5_ifc_get_dropped_packet_log_in_bits {
4552 u8 opcode[0x10];
4553 u8 reserved_0[0x10];
4554
4555 u8 reserved_1[0x10];
4556 u8 op_mod[0x10];
4557
4558 u8 reserved_2[0x40];
4559};
4560
4561struct mlx5_ifc_gen_eqe_in_bits {
4562 u8 opcode[0x10];
4563 u8 reserved_0[0x10];
4564
4565 u8 reserved_1[0x10];
4566 u8 op_mod[0x10];
4567
4568 u8 reserved_2[0x18];
4569 u8 eq_number[0x8];
4570
4571 u8 reserved_3[0x20];
4572
4573 u8 eqe[64][0x8];
4574};
4575
4576struct mlx5_ifc_gen_eq_out_bits {
4577 u8 status[0x8];
4578 u8 reserved_0[0x18];
4579
4580 u8 syndrome[0x20];
4581
4582 u8 reserved_1[0x40];
4583};
4584
4585struct mlx5_ifc_enable_hca_out_bits {
4586 u8 status[0x8];
4587 u8 reserved_0[0x18];
4588
4589 u8 syndrome[0x20];
4590
4591 u8 reserved_1[0x20];
4592};
4593
4594struct mlx5_ifc_enable_hca_in_bits {
4595 u8 opcode[0x10];
4596 u8 reserved_0[0x10];
4597
4598 u8 reserved_1[0x10];
4599 u8 op_mod[0x10];
4600
4601 u8 reserved_2[0x10];
4602 u8 function_id[0x10];
4603
4604 u8 reserved_3[0x20];
4605};
4606
4607struct mlx5_ifc_drain_dct_out_bits {
4608 u8 status[0x8];
4609 u8 reserved_0[0x18];
4610
4611 u8 syndrome[0x20];
4612
4613 u8 reserved_1[0x40];
4614};
4615
4616struct mlx5_ifc_drain_dct_in_bits {
4617 u8 opcode[0x10];
4618 u8 reserved_0[0x10];
4619
4620 u8 reserved_1[0x10];
4621 u8 op_mod[0x10];
4622
4623 u8 reserved_2[0x8];
4624 u8 dctn[0x18];
4625
4626 u8 reserved_3[0x20];
4627};
4628
4629struct mlx5_ifc_disable_hca_out_bits {
4630 u8 status[0x8];
4631 u8 reserved_0[0x18];
4632
4633 u8 syndrome[0x20];
4634
4635 u8 reserved_1[0x20];
4636};
4637
4638struct mlx5_ifc_disable_hca_in_bits {
4639 u8 opcode[0x10];
4640 u8 reserved_0[0x10];
4641
4642 u8 reserved_1[0x10];
4643 u8 op_mod[0x10];
4644
4645 u8 reserved_2[0x10];
4646 u8 function_id[0x10];
4647
4648 u8 reserved_3[0x20];
4649};
4650
4651struct mlx5_ifc_detach_from_mcg_out_bits {
4652 u8 status[0x8];
4653 u8 reserved_0[0x18];
4654
4655 u8 syndrome[0x20];
4656
4657 u8 reserved_1[0x40];
4658};
4659
4660struct mlx5_ifc_detach_from_mcg_in_bits {
4661 u8 opcode[0x10];
4662 u8 reserved_0[0x10];
4663
4664 u8 reserved_1[0x10];
4665 u8 op_mod[0x10];
4666
4667 u8 reserved_2[0x8];
4668 u8 qpn[0x18];
4669
4670 u8 reserved_3[0x20];
4671
4672 u8 multicast_gid[16][0x8];
4673};
4674
4675struct mlx5_ifc_destroy_xrc_srq_out_bits {
4676 u8 status[0x8];
4677 u8 reserved_0[0x18];
4678
4679 u8 syndrome[0x20];
4680
4681 u8 reserved_1[0x40];
4682};
4683
4684struct mlx5_ifc_destroy_xrc_srq_in_bits {
4685 u8 opcode[0x10];
4686 u8 reserved_0[0x10];
4687
4688 u8 reserved_1[0x10];
4689 u8 op_mod[0x10];
4690
4691 u8 reserved_2[0x8];
4692 u8 xrc_srqn[0x18];
4693
4694 u8 reserved_3[0x20];
4695};
4696
4697struct mlx5_ifc_destroy_tis_out_bits {
4698 u8 status[0x8];
4699 u8 reserved_0[0x18];
4700
4701 u8 syndrome[0x20];
4702
4703 u8 reserved_1[0x40];
4704};
4705
4706struct mlx5_ifc_destroy_tis_in_bits {
4707 u8 opcode[0x10];
4708 u8 reserved_0[0x10];
4709
4710 u8 reserved_1[0x10];
4711 u8 op_mod[0x10];
4712
4713 u8 reserved_2[0x8];
4714 u8 tisn[0x18];
4715
4716 u8 reserved_3[0x20];
4717};
4718
4719struct mlx5_ifc_destroy_tir_out_bits {
4720 u8 status[0x8];
4721 u8 reserved_0[0x18];
4722
4723 u8 syndrome[0x20];
4724
4725 u8 reserved_1[0x40];
4726};
4727
4728struct mlx5_ifc_destroy_tir_in_bits {
4729 u8 opcode[0x10];
4730 u8 reserved_0[0x10];
4731
4732 u8 reserved_1[0x10];
4733 u8 op_mod[0x10];
4734
4735 u8 reserved_2[0x8];
4736 u8 tirn[0x18];
4737
4738 u8 reserved_3[0x20];
4739};
4740
4741struct mlx5_ifc_destroy_srq_out_bits {
4742 u8 status[0x8];
4743 u8 reserved_0[0x18];
4744
4745 u8 syndrome[0x20];
4746
4747 u8 reserved_1[0x40];
4748};
4749
4750struct mlx5_ifc_destroy_srq_in_bits {
4751 u8 opcode[0x10];
4752 u8 reserved_0[0x10];
4753
4754 u8 reserved_1[0x10];
4755 u8 op_mod[0x10];
4756
4757 u8 reserved_2[0x8];
4758 u8 srqn[0x18];
4759
4760 u8 reserved_3[0x20];
4761};
4762
4763struct mlx5_ifc_destroy_sq_out_bits {
4764 u8 status[0x8];
4765 u8 reserved_0[0x18];
4766
4767 u8 syndrome[0x20];
4768
4769 u8 reserved_1[0x40];
4770};
4771
4772struct mlx5_ifc_destroy_sq_in_bits {
4773 u8 opcode[0x10];
4774 u8 reserved_0[0x10];
4775
4776 u8 reserved_1[0x10];
4777 u8 op_mod[0x10];
4778
4779 u8 reserved_2[0x8];
4780 u8 sqn[0x18];
4781
4782 u8 reserved_3[0x20];
4783};
4784
4785struct mlx5_ifc_destroy_rqt_out_bits {
4786 u8 status[0x8];
4787 u8 reserved_0[0x18];
4788
4789 u8 syndrome[0x20];
4790
4791 u8 reserved_1[0x40];
4792};
4793
4794struct mlx5_ifc_destroy_rqt_in_bits {
4795 u8 opcode[0x10];
4796 u8 reserved_0[0x10];
4797
4798 u8 reserved_1[0x10];
4799 u8 op_mod[0x10];
4800
4801 u8 reserved_2[0x8];
4802 u8 rqtn[0x18];
4803
4804 u8 reserved_3[0x20];
4805};
4806
4807struct mlx5_ifc_destroy_rq_out_bits {
4808 u8 status[0x8];
4809 u8 reserved_0[0x18];
4810
4811 u8 syndrome[0x20];
4812
4813 u8 reserved_1[0x40];
4814};
4815
4816struct mlx5_ifc_destroy_rq_in_bits {
4817 u8 opcode[0x10];
4818 u8 reserved_0[0x10];
4819
4820 u8 reserved_1[0x10];
4821 u8 op_mod[0x10];
4822
4823 u8 reserved_2[0x8];
4824 u8 rqn[0x18];
4825
4826 u8 reserved_3[0x20];
4827};
4828
4829struct mlx5_ifc_destroy_rmp_out_bits {
4830 u8 status[0x8];
4831 u8 reserved_0[0x18];
4832
4833 u8 syndrome[0x20];
4834
4835 u8 reserved_1[0x40];
4836};
4837
4838struct mlx5_ifc_destroy_rmp_in_bits {
4839 u8 opcode[0x10];
4840 u8 reserved_0[0x10];
4841
4842 u8 reserved_1[0x10];
4843 u8 op_mod[0x10];
4844
4845 u8 reserved_2[0x8];
4846 u8 rmpn[0x18];
4847
4848 u8 reserved_3[0x20];
4849};
4850
4851struct mlx5_ifc_destroy_qp_out_bits {
4852 u8 status[0x8];
4853 u8 reserved_0[0x18];
4854
4855 u8 syndrome[0x20];
4856
4857 u8 reserved_1[0x40];
4858};
4859
4860struct mlx5_ifc_destroy_qp_in_bits {
4861 u8 opcode[0x10];
4862 u8 reserved_0[0x10];
4863
4864 u8 reserved_1[0x10];
4865 u8 op_mod[0x10];
4866
4867 u8 reserved_2[0x8];
4868 u8 qpn[0x18];
4869
4870 u8 reserved_3[0x20];
4871};
4872
4873struct mlx5_ifc_destroy_psv_out_bits {
4874 u8 status[0x8];
4875 u8 reserved_0[0x18];
4876
4877 u8 syndrome[0x20];
4878
4879 u8 reserved_1[0x40];
4880};
4881
4882struct mlx5_ifc_destroy_psv_in_bits {
4883 u8 opcode[0x10];
4884 u8 reserved_0[0x10];
4885
4886 u8 reserved_1[0x10];
4887 u8 op_mod[0x10];
4888
4889 u8 reserved_2[0x8];
4890 u8 psvn[0x18];
4891
4892 u8 reserved_3[0x20];
4893};
4894
4895struct mlx5_ifc_destroy_mkey_out_bits {
4896 u8 status[0x8];
4897 u8 reserved_0[0x18];
4898
4899 u8 syndrome[0x20];
4900
4901 u8 reserved_1[0x40];
4902};
4903
4904struct mlx5_ifc_destroy_mkey_in_bits {
4905 u8 opcode[0x10];
4906 u8 reserved_0[0x10];
4907
4908 u8 reserved_1[0x10];
4909 u8 op_mod[0x10];
4910
4911 u8 reserved_2[0x8];
4912 u8 mkey_index[0x18];
4913
4914 u8 reserved_3[0x20];
4915};
4916
4917struct mlx5_ifc_destroy_flow_table_out_bits {
4918 u8 status[0x8];
4919 u8 reserved_0[0x18];
4920
4921 u8 syndrome[0x20];
4922
4923 u8 reserved_1[0x40];
4924};
4925
4926struct mlx5_ifc_destroy_flow_table_in_bits {
4927 u8 opcode[0x10];
4928 u8 reserved_0[0x10];
4929
4930 u8 reserved_1[0x10];
4931 u8 op_mod[0x10];
4932
4933 u8 reserved_2[0x40];
4934
4935 u8 table_type[0x8];
4936 u8 reserved_3[0x18];
4937
4938 u8 reserved_4[0x8];
4939 u8 table_id[0x18];
4940
4941 u8 reserved_5[0x140];
4942};
4943
4944struct mlx5_ifc_destroy_flow_group_out_bits {
4945 u8 status[0x8];
4946 u8 reserved_0[0x18];
4947
4948 u8 syndrome[0x20];
4949
4950 u8 reserved_1[0x40];
4951};
4952
4953struct mlx5_ifc_destroy_flow_group_in_bits {
4954 u8 opcode[0x10];
4955 u8 reserved_0[0x10];
4956
4957 u8 reserved_1[0x10];
4958 u8 op_mod[0x10];
4959
4960 u8 reserved_2[0x40];
4961
4962 u8 table_type[0x8];
4963 u8 reserved_3[0x18];
4964
4965 u8 reserved_4[0x8];
4966 u8 table_id[0x18];
4967
4968 u8 group_id[0x20];
4969
4970 u8 reserved_5[0x120];
4971};
4972
4973struct mlx5_ifc_destroy_eq_out_bits {
4974 u8 status[0x8];
4975 u8 reserved_0[0x18];
4976
4977 u8 syndrome[0x20];
4978
4979 u8 reserved_1[0x40];
4980};
4981
4982struct mlx5_ifc_destroy_eq_in_bits {
4983 u8 opcode[0x10];
4984 u8 reserved_0[0x10];
4985
4986 u8 reserved_1[0x10];
4987 u8 op_mod[0x10];
4988
4989 u8 reserved_2[0x18];
4990 u8 eq_number[0x8];
4991
4992 u8 reserved_3[0x20];
4993};
4994
4995struct mlx5_ifc_destroy_dct_out_bits {
4996 u8 status[0x8];
4997 u8 reserved_0[0x18];
4998
4999 u8 syndrome[0x20];
5000
5001 u8 reserved_1[0x40];
5002};
5003
5004struct mlx5_ifc_destroy_dct_in_bits {
5005 u8 opcode[0x10];
5006 u8 reserved_0[0x10];
5007
5008 u8 reserved_1[0x10];
5009 u8 op_mod[0x10];
5010
5011 u8 reserved_2[0x8];
5012 u8 dctn[0x18];
5013
5014 u8 reserved_3[0x20];
5015};
5016
5017struct mlx5_ifc_destroy_cq_out_bits {
5018 u8 status[0x8];
5019 u8 reserved_0[0x18];
5020
5021 u8 syndrome[0x20];
5022
5023 u8 reserved_1[0x40];
5024};
5025
5026struct mlx5_ifc_destroy_cq_in_bits {
5027 u8 opcode[0x10];
5028 u8 reserved_0[0x10];
5029
5030 u8 reserved_1[0x10];
5031 u8 op_mod[0x10];
5032
5033 u8 reserved_2[0x8];
5034 u8 cqn[0x18];
5035
5036 u8 reserved_3[0x20];
5037};
5038
5039struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
5040 u8 status[0x8];
5041 u8 reserved_0[0x18];
5042
5043 u8 syndrome[0x20];
5044
5045 u8 reserved_1[0x40];
5046};
5047
5048struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
5049 u8 opcode[0x10];
5050 u8 reserved_0[0x10];
5051
5052 u8 reserved_1[0x10];
5053 u8 op_mod[0x10];
5054
5055 u8 reserved_2[0x20];
5056
5057 u8 reserved_3[0x10];
5058 u8 vxlan_udp_port[0x10];
5059};
5060
5061struct mlx5_ifc_delete_l2_table_entry_out_bits {
5062 u8 status[0x8];
5063 u8 reserved_0[0x18];
5064
5065 u8 syndrome[0x20];
5066
5067 u8 reserved_1[0x40];
5068};
5069
5070struct mlx5_ifc_delete_l2_table_entry_in_bits {
5071 u8 opcode[0x10];
5072 u8 reserved_0[0x10];
5073
5074 u8 reserved_1[0x10];
5075 u8 op_mod[0x10];
5076
5077 u8 reserved_2[0x60];
5078
5079 u8 reserved_3[0x8];
5080 u8 table_index[0x18];
5081
5082 u8 reserved_4[0x140];
5083};
5084
5085struct mlx5_ifc_delete_fte_out_bits {
5086 u8 status[0x8];
5087 u8 reserved_0[0x18];
5088
5089 u8 syndrome[0x20];
5090
5091 u8 reserved_1[0x40];
5092};
5093
5094struct mlx5_ifc_delete_fte_in_bits {
5095 u8 opcode[0x10];
5096 u8 reserved_0[0x10];
5097
5098 u8 reserved_1[0x10];
5099 u8 op_mod[0x10];
5100
5101 u8 reserved_2[0x40];
5102
5103 u8 table_type[0x8];
5104 u8 reserved_3[0x18];
5105
5106 u8 reserved_4[0x8];
5107 u8 table_id[0x18];
5108
5109 u8 reserved_5[0x40];
5110
5111 u8 flow_index[0x20];
5112
5113 u8 reserved_6[0xe0];
5114};
5115
5116struct mlx5_ifc_dealloc_xrcd_out_bits {
5117 u8 status[0x8];
5118 u8 reserved_0[0x18];
5119
5120 u8 syndrome[0x20];
5121
5122 u8 reserved_1[0x40];
5123};
5124
5125struct mlx5_ifc_dealloc_xrcd_in_bits {
5126 u8 opcode[0x10];
5127 u8 reserved_0[0x10];
5128
5129 u8 reserved_1[0x10];
5130 u8 op_mod[0x10];
5131
5132 u8 reserved_2[0x8];
5133 u8 xrcd[0x18];
5134
5135 u8 reserved_3[0x20];
5136};
5137
5138struct mlx5_ifc_dealloc_uar_out_bits {
5139 u8 status[0x8];
5140 u8 reserved_0[0x18];
5141
5142 u8 syndrome[0x20];
5143
5144 u8 reserved_1[0x40];
5145};
5146
5147struct mlx5_ifc_dealloc_uar_in_bits {
5148 u8 opcode[0x10];
5149 u8 reserved_0[0x10];
5150
5151 u8 reserved_1[0x10];
5152 u8 op_mod[0x10];
5153
5154 u8 reserved_2[0x8];
5155 u8 uar[0x18];
5156
5157 u8 reserved_3[0x20];
5158};
5159
5160struct mlx5_ifc_dealloc_transport_domain_out_bits {
5161 u8 status[0x8];
5162 u8 reserved_0[0x18];
5163
5164 u8 syndrome[0x20];
5165
5166 u8 reserved_1[0x40];
5167};
5168
5169struct mlx5_ifc_dealloc_transport_domain_in_bits {
5170 u8 opcode[0x10];
5171 u8 reserved_0[0x10];
5172
5173 u8 reserved_1[0x10];
5174 u8 op_mod[0x10];
5175
5176 u8 reserved_2[0x8];
5177 u8 transport_domain[0x18];
5178
5179 u8 reserved_3[0x20];
5180};
5181
5182struct mlx5_ifc_dealloc_q_counter_out_bits {
5183 u8 status[0x8];
5184 u8 reserved_0[0x18];
5185
5186 u8 syndrome[0x20];
5187
5188 u8 reserved_1[0x40];
5189};
5190
5191struct mlx5_ifc_dealloc_q_counter_in_bits {
5192 u8 opcode[0x10];
5193 u8 reserved_0[0x10];
5194
5195 u8 reserved_1[0x10];
5196 u8 op_mod[0x10];
5197
5198 u8 reserved_2[0x18];
5199 u8 counter_set_id[0x8];
5200
5201 u8 reserved_3[0x20];
5202};
5203
5204struct mlx5_ifc_dealloc_pd_out_bits {
5205 u8 status[0x8];
5206 u8 reserved_0[0x18];
5207
5208 u8 syndrome[0x20];
5209
5210 u8 reserved_1[0x40];
5211};
5212
5213struct mlx5_ifc_dealloc_pd_in_bits {
5214 u8 opcode[0x10];
5215 u8 reserved_0[0x10];
5216
5217 u8 reserved_1[0x10];
5218 u8 op_mod[0x10];
5219
5220 u8 reserved_2[0x8];
5221 u8 pd[0x18];
5222
5223 u8 reserved_3[0x20];
5224};
5225
5226struct mlx5_ifc_create_xrc_srq_out_bits {
5227 u8 status[0x8];
5228 u8 reserved_0[0x18];
5229
5230 u8 syndrome[0x20];
5231
5232 u8 reserved_1[0x8];
5233 u8 xrc_srqn[0x18];
5234
5235 u8 reserved_2[0x20];
5236};
5237
5238struct mlx5_ifc_create_xrc_srq_in_bits {
5239 u8 opcode[0x10];
5240 u8 reserved_0[0x10];
5241
5242 u8 reserved_1[0x10];
5243 u8 op_mod[0x10];
5244
5245 u8 reserved_2[0x40];
5246
5247 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
5248
5249 u8 reserved_3[0x600];
5250
5251 u8 pas[0][0x40];
5252};
5253
5254struct mlx5_ifc_create_tis_out_bits {
5255 u8 status[0x8];
5256 u8 reserved_0[0x18];
5257
5258 u8 syndrome[0x20];
5259
5260 u8 reserved_1[0x8];
5261 u8 tisn[0x18];
5262
5263 u8 reserved_2[0x20];
5264};
5265
5266struct mlx5_ifc_create_tis_in_bits {
5267 u8 opcode[0x10];
5268 u8 reserved_0[0x10];
5269
5270 u8 reserved_1[0x10];
5271 u8 op_mod[0x10];
5272
5273 u8 reserved_2[0xc0];
5274
5275 struct mlx5_ifc_tisc_bits ctx;
5276};
5277
5278struct mlx5_ifc_create_tir_out_bits {
5279 u8 status[0x8];
5280 u8 reserved_0[0x18];
5281
5282 u8 syndrome[0x20];
5283
5284 u8 reserved_1[0x8];
5285 u8 tirn[0x18];
5286
5287 u8 reserved_2[0x20];
5288};
5289
5290struct mlx5_ifc_create_tir_in_bits {
5291 u8 opcode[0x10];
5292 u8 reserved_0[0x10];
5293
5294 u8 reserved_1[0x10];
5295 u8 op_mod[0x10];
5296
5297 u8 reserved_2[0xc0];
5298
5299 struct mlx5_ifc_tirc_bits ctx;
5300};
5301
5302struct mlx5_ifc_create_srq_out_bits {
5303 u8 status[0x8];
5304 u8 reserved_0[0x18];
5305
5306 u8 syndrome[0x20];
5307
5308 u8 reserved_1[0x8];
5309 u8 srqn[0x18];
5310
5311 u8 reserved_2[0x20];
5312};
5313
5314struct mlx5_ifc_create_srq_in_bits {
5315 u8 opcode[0x10];
5316 u8 reserved_0[0x10];
5317
5318 u8 reserved_1[0x10];
5319 u8 op_mod[0x10];
5320
5321 u8 reserved_2[0x40];
5322
5323 struct mlx5_ifc_srqc_bits srq_context_entry;
5324
5325 u8 reserved_3[0x600];
5326
5327 u8 pas[0][0x40];
5328};
5329
5330struct mlx5_ifc_create_sq_out_bits {
5331 u8 status[0x8];
5332 u8 reserved_0[0x18];
5333
5334 u8 syndrome[0x20];
5335
5336 u8 reserved_1[0x8];
5337 u8 sqn[0x18];
5338
5339 u8 reserved_2[0x20];
5340};
5341
5342struct mlx5_ifc_create_sq_in_bits {
5343 u8 opcode[0x10];
5344 u8 reserved_0[0x10];
5345
5346 u8 reserved_1[0x10];
5347 u8 op_mod[0x10];
5348
5349 u8 reserved_2[0xc0];
5350
5351 struct mlx5_ifc_sqc_bits ctx;
5352};
5353
5354struct mlx5_ifc_create_rqt_out_bits {
5355 u8 status[0x8];
5356 u8 reserved_0[0x18];
5357
5358 u8 syndrome[0x20];
5359
5360 u8 reserved_1[0x8];
5361 u8 rqtn[0x18];
5362
5363 u8 reserved_2[0x20];
5364};
5365
5366struct mlx5_ifc_create_rqt_in_bits {
5367 u8 opcode[0x10];
5368 u8 reserved_0[0x10];
5369
5370 u8 reserved_1[0x10];
5371 u8 op_mod[0x10];
5372
5373 u8 reserved_2[0xc0];
5374
5375 struct mlx5_ifc_rqtc_bits rqt_context;
5376};
5377
5378struct mlx5_ifc_create_rq_out_bits {
5379 u8 status[0x8];
5380 u8 reserved_0[0x18];
5381
5382 u8 syndrome[0x20];
5383
5384 u8 reserved_1[0x8];
5385 u8 rqn[0x18];
5386
5387 u8 reserved_2[0x20];
5388};
5389
5390struct mlx5_ifc_create_rq_in_bits {
5391 u8 opcode[0x10];
5392 u8 reserved_0[0x10];
5393
5394 u8 reserved_1[0x10];
5395 u8 op_mod[0x10];
5396
5397 u8 reserved_2[0xc0];
5398
5399 struct mlx5_ifc_rqc_bits ctx;
5400};
5401
5402struct mlx5_ifc_create_rmp_out_bits {
5403 u8 status[0x8];
5404 u8 reserved_0[0x18];
5405
5406 u8 syndrome[0x20];
5407
5408 u8 reserved_1[0x8];
5409 u8 rmpn[0x18];
5410
5411 u8 reserved_2[0x20];
5412};
5413
5414struct mlx5_ifc_create_rmp_in_bits {
5415 u8 opcode[0x10];
5416 u8 reserved_0[0x10];
5417
5418 u8 reserved_1[0x10];
5419 u8 op_mod[0x10];
5420
5421 u8 reserved_2[0xc0];
5422
5423 struct mlx5_ifc_rmpc_bits ctx;
5424};
5425
5426struct mlx5_ifc_create_qp_out_bits {
5427 u8 status[0x8];
5428 u8 reserved_0[0x18];
5429
5430 u8 syndrome[0x20];
5431
5432 u8 reserved_1[0x8];
5433 u8 qpn[0x18];
5434
5435 u8 reserved_2[0x20];
5436};
5437
5438struct mlx5_ifc_create_qp_in_bits {
5439 u8 opcode[0x10];
5440 u8 reserved_0[0x10];
5441
5442 u8 reserved_1[0x10];
5443 u8 op_mod[0x10];
5444
5445 u8 reserved_2[0x40];
5446
5447 u8 opt_param_mask[0x20];
5448
5449 u8 reserved_3[0x20];
5450
5451 struct mlx5_ifc_qpc_bits qpc;
5452
5453 u8 reserved_4[0x80];
5454
5455 u8 pas[0][0x40];
5456};
5457
5458struct mlx5_ifc_create_psv_out_bits {
5459 u8 status[0x8];
5460 u8 reserved_0[0x18];
5461
5462 u8 syndrome[0x20];
5463
5464 u8 reserved_1[0x40];
5465
5466 u8 reserved_2[0x8];
5467 u8 psv0_index[0x18];
5468
5469 u8 reserved_3[0x8];
5470 u8 psv1_index[0x18];
5471
5472 u8 reserved_4[0x8];
5473 u8 psv2_index[0x18];
5474
5475 u8 reserved_5[0x8];
5476 u8 psv3_index[0x18];
5477};
5478
5479struct mlx5_ifc_create_psv_in_bits {
5480 u8 opcode[0x10];
5481 u8 reserved_0[0x10];
5482
5483 u8 reserved_1[0x10];
5484 u8 op_mod[0x10];
5485
5486 u8 num_psv[0x4];
5487 u8 reserved_2[0x4];
5488 u8 pd[0x18];
5489
5490 u8 reserved_3[0x20];
5491};
5492
5493struct mlx5_ifc_create_mkey_out_bits {
5494 u8 status[0x8];
5495 u8 reserved_0[0x18];
5496
5497 u8 syndrome[0x20];
5498
5499 u8 reserved_1[0x8];
5500 u8 mkey_index[0x18];
5501
5502 u8 reserved_2[0x20];
5503};
5504
5505struct mlx5_ifc_create_mkey_in_bits {
5506 u8 opcode[0x10];
5507 u8 reserved_0[0x10];
5508
5509 u8 reserved_1[0x10];
5510 u8 op_mod[0x10];
5511
5512 u8 reserved_2[0x20];
5513
5514 u8 pg_access[0x1];
5515 u8 reserved_3[0x1f];
5516
5517 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5518
5519 u8 reserved_4[0x80];
5520
5521 u8 translations_octword_actual_size[0x20];
5522
5523 u8 reserved_5[0x560];
5524
5525 u8 klm_pas_mtt[0][0x20];
5526};
5527
5528struct mlx5_ifc_create_flow_table_out_bits {
5529 u8 status[0x8];
5530 u8 reserved_0[0x18];
5531
5532 u8 syndrome[0x20];
5533
5534 u8 reserved_1[0x8];
5535 u8 table_id[0x18];
5536
5537 u8 reserved_2[0x20];
5538};
5539
5540struct mlx5_ifc_create_flow_table_in_bits {
5541 u8 opcode[0x10];
5542 u8 reserved_0[0x10];
5543
5544 u8 reserved_1[0x10];
5545 u8 op_mod[0x10];
5546
5547 u8 reserved_2[0x40];
5548
5549 u8 table_type[0x8];
5550 u8 reserved_3[0x18];
5551
5552 u8 reserved_4[0x20];
5553
5554 u8 reserved_5[0x8];
5555 u8 level[0x8];
5556 u8 reserved_6[0x8];
5557 u8 log_size[0x8];
5558
5559 u8 reserved_7[0x120];
5560};
5561
5562struct mlx5_ifc_create_flow_group_out_bits {
5563 u8 status[0x8];
5564 u8 reserved_0[0x18];
5565
5566 u8 syndrome[0x20];
5567
5568 u8 reserved_1[0x8];
5569 u8 group_id[0x18];
5570
5571 u8 reserved_2[0x20];
5572};
5573
5574enum {
5575 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
5576 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
5577 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
5578};
5579
5580struct mlx5_ifc_create_flow_group_in_bits {
5581 u8 opcode[0x10];
5582 u8 reserved_0[0x10];
5583
5584 u8 reserved_1[0x10];
5585 u8 op_mod[0x10];
5586
5587 u8 reserved_2[0x40];
5588
5589 u8 table_type[0x8];
5590 u8 reserved_3[0x18];
5591
5592 u8 reserved_4[0x8];
5593 u8 table_id[0x18];
5594
5595 u8 reserved_5[0x20];
5596
5597 u8 start_flow_index[0x20];
5598
5599 u8 reserved_6[0x20];
5600
5601 u8 end_flow_index[0x20];
5602
5603 u8 reserved_7[0xa0];
5604
5605 u8 reserved_8[0x18];
5606 u8 match_criteria_enable[0x8];
5607
5608 struct mlx5_ifc_fte_match_param_bits match_criteria;
5609
5610 u8 reserved_9[0xe00];
5611};
5612
5613struct mlx5_ifc_create_eq_out_bits {
5614 u8 status[0x8];
5615 u8 reserved_0[0x18];
5616
5617 u8 syndrome[0x20];
5618
5619 u8 reserved_1[0x18];
5620 u8 eq_number[0x8];
5621
5622 u8 reserved_2[0x20];
5623};
5624
5625struct mlx5_ifc_create_eq_in_bits {
5626 u8 opcode[0x10];
5627 u8 reserved_0[0x10];
5628
5629 u8 reserved_1[0x10];
5630 u8 op_mod[0x10];
5631
5632 u8 reserved_2[0x40];
5633
5634 struct mlx5_ifc_eqc_bits eq_context_entry;
5635
5636 u8 reserved_3[0x40];
5637
5638 u8 event_bitmask[0x40];
5639
5640 u8 reserved_4[0x580];
5641
5642 u8 pas[0][0x40];
5643};
5644
5645struct mlx5_ifc_create_dct_out_bits {
5646 u8 status[0x8];
5647 u8 reserved_0[0x18];
5648
5649 u8 syndrome[0x20];
5650
5651 u8 reserved_1[0x8];
5652 u8 dctn[0x18];
5653
5654 u8 reserved_2[0x20];
5655};
5656
5657struct mlx5_ifc_create_dct_in_bits {
5658 u8 opcode[0x10];
5659 u8 reserved_0[0x10];
5660
5661 u8 reserved_1[0x10];
5662 u8 op_mod[0x10];
5663
5664 u8 reserved_2[0x40];
5665
5666 struct mlx5_ifc_dctc_bits dct_context_entry;
5667
5668 u8 reserved_3[0x180];
5669};
5670
5671struct mlx5_ifc_create_cq_out_bits {
5672 u8 status[0x8];
5673 u8 reserved_0[0x18];
5674
5675 u8 syndrome[0x20];
5676
5677 u8 reserved_1[0x8];
5678 u8 cqn[0x18];
5679
5680 u8 reserved_2[0x20];
5681};
5682
5683struct mlx5_ifc_create_cq_in_bits {
5684 u8 opcode[0x10];
5685 u8 reserved_0[0x10];
5686
5687 u8 reserved_1[0x10];
5688 u8 op_mod[0x10];
5689
5690 u8 reserved_2[0x40];
5691
5692 struct mlx5_ifc_cqc_bits cq_context;
5693
5694 u8 reserved_3[0x600];
5695
5696 u8 pas[0][0x40];
5697};
5698
5699struct mlx5_ifc_config_int_moderation_out_bits {
5700 u8 status[0x8];
5701 u8 reserved_0[0x18];
5702
5703 u8 syndrome[0x20];
5704
5705 u8 reserved_1[0x4];
5706 u8 min_delay[0xc];
5707 u8 int_vector[0x10];
5708
5709 u8 reserved_2[0x20];
5710};
5711
5712enum {
5713 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
5714 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
5715};
5716
5717struct mlx5_ifc_config_int_moderation_in_bits {
5718 u8 opcode[0x10];
5719 u8 reserved_0[0x10];
5720
5721 u8 reserved_1[0x10];
5722 u8 op_mod[0x10];
5723
5724 u8 reserved_2[0x4];
5725 u8 min_delay[0xc];
5726 u8 int_vector[0x10];
5727
5728 u8 reserved_3[0x20];
5729};
5730
5731struct mlx5_ifc_attach_to_mcg_out_bits {
5732 u8 status[0x8];
5733 u8 reserved_0[0x18];
5734
5735 u8 syndrome[0x20];
5736
5737 u8 reserved_1[0x40];
5738};
5739
5740struct mlx5_ifc_attach_to_mcg_in_bits {
5741 u8 opcode[0x10];
5742 u8 reserved_0[0x10];
5743
5744 u8 reserved_1[0x10];
5745 u8 op_mod[0x10];
5746
5747 u8 reserved_2[0x8];
5748 u8 qpn[0x18];
5749
5750 u8 reserved_3[0x20];
5751
5752 u8 multicast_gid[16][0x8];
5753};
5754
5755struct mlx5_ifc_arm_xrc_srq_out_bits {
5756 u8 status[0x8];
5757 u8 reserved_0[0x18];
5758
5759 u8 syndrome[0x20];
5760
5761 u8 reserved_1[0x40];
5762};
5763
5764enum {
5765 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
5766};
5767
5768struct mlx5_ifc_arm_xrc_srq_in_bits {
5769 u8 opcode[0x10];
5770 u8 reserved_0[0x10];
5771
5772 u8 reserved_1[0x10];
5773 u8 op_mod[0x10];
5774
5775 u8 reserved_2[0x8];
5776 u8 xrc_srqn[0x18];
5777
5778 u8 reserved_3[0x10];
5779 u8 lwm[0x10];
5780};
5781
5782struct mlx5_ifc_arm_rq_out_bits {
5783 u8 status[0x8];
5784 u8 reserved_0[0x18];
5785
5786 u8 syndrome[0x20];
5787
5788 u8 reserved_1[0x40];
5789};
5790
5791enum {
5792 MLX5_ARM_RQ_IN_OP_MOD_SRQ_ = 0x1,
5793};
5794
5795struct mlx5_ifc_arm_rq_in_bits {
5796 u8 opcode[0x10];
5797 u8 reserved_0[0x10];
5798
5799 u8 reserved_1[0x10];
5800 u8 op_mod[0x10];
5801
5802 u8 reserved_2[0x8];
5803 u8 srq_number[0x18];
5804
5805 u8 reserved_3[0x10];
5806 u8 lwm[0x10];
5807};
5808
5809struct mlx5_ifc_arm_dct_out_bits {
5810 u8 status[0x8];
5811 u8 reserved_0[0x18];
5812
5813 u8 syndrome[0x20];
5814
5815 u8 reserved_1[0x40];
5816};
5817
5818struct mlx5_ifc_arm_dct_in_bits {
5819 u8 opcode[0x10];
5820 u8 reserved_0[0x10];
5821
5822 u8 reserved_1[0x10];
5823 u8 op_mod[0x10];
5824
5825 u8 reserved_2[0x8];
5826 u8 dct_number[0x18];
5827
5828 u8 reserved_3[0x20];
5829};
5830
5831struct mlx5_ifc_alloc_xrcd_out_bits {
5832 u8 status[0x8];
5833 u8 reserved_0[0x18];
5834
5835 u8 syndrome[0x20];
5836
5837 u8 reserved_1[0x8];
5838 u8 xrcd[0x18];
5839
5840 u8 reserved_2[0x20];
5841};
5842
5843struct mlx5_ifc_alloc_xrcd_in_bits {
5844 u8 opcode[0x10];
5845 u8 reserved_0[0x10];
5846
5847 u8 reserved_1[0x10];
5848 u8 op_mod[0x10];
5849
5850 u8 reserved_2[0x40];
5851};
5852
5853struct mlx5_ifc_alloc_uar_out_bits {
5854 u8 status[0x8];
5855 u8 reserved_0[0x18];
5856
5857 u8 syndrome[0x20];
5858
5859 u8 reserved_1[0x8];
5860 u8 uar[0x18];
5861
5862 u8 reserved_2[0x20];
5863};
5864
5865struct mlx5_ifc_alloc_uar_in_bits {
5866 u8 opcode[0x10];
5867 u8 reserved_0[0x10];
5868
5869 u8 reserved_1[0x10];
5870 u8 op_mod[0x10];
5871
5872 u8 reserved_2[0x40];
5873};
5874
5875struct mlx5_ifc_alloc_transport_domain_out_bits {
5876 u8 status[0x8];
5877 u8 reserved_0[0x18];
5878
5879 u8 syndrome[0x20];
5880
5881 u8 reserved_1[0x8];
5882 u8 transport_domain[0x18];
5883
5884 u8 reserved_2[0x20];
5885};
5886
5887struct mlx5_ifc_alloc_transport_domain_in_bits {
5888 u8 opcode[0x10];
5889 u8 reserved_0[0x10];
5890
5891 u8 reserved_1[0x10];
5892 u8 op_mod[0x10];
5893
5894 u8 reserved_2[0x40];
5895};
5896
5897struct mlx5_ifc_alloc_q_counter_out_bits {
5898 u8 status[0x8];
5899 u8 reserved_0[0x18];
5900
5901 u8 syndrome[0x20];
5902
5903 u8 reserved_1[0x18];
5904 u8 counter_set_id[0x8];
5905
5906 u8 reserved_2[0x20];
5907};
5908
5909struct mlx5_ifc_alloc_q_counter_in_bits {
5910 u8 opcode[0x10];
5911 u8 reserved_0[0x10];
5912
5913 u8 reserved_1[0x10];
5914 u8 op_mod[0x10];
5915
5916 u8 reserved_2[0x40];
5917};
5918
5919struct mlx5_ifc_alloc_pd_out_bits {
5920 u8 status[0x8];
5921 u8 reserved_0[0x18];
5922
5923 u8 syndrome[0x20];
5924
5925 u8 reserved_1[0x8];
5926 u8 pd[0x18];
5927
5928 u8 reserved_2[0x20];
5929};
5930
5931struct mlx5_ifc_alloc_pd_in_bits {
5932 u8 opcode[0x10];
5933 u8 reserved_0[0x10];
5934
5935 u8 reserved_1[0x10];
5936 u8 op_mod[0x10];
5937
5938 u8 reserved_2[0x40];
5939};
5940
5941struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
5942 u8 status[0x8];
5943 u8 reserved_0[0x18];
5944
5945 u8 syndrome[0x20];
5946
5947 u8 reserved_1[0x40];
5948};
5949
5950struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
5951 u8 opcode[0x10];
5952 u8 reserved_0[0x10];
5953
5954 u8 reserved_1[0x10];
5955 u8 op_mod[0x10];
5956
5957 u8 reserved_2[0x20];
5958
5959 u8 reserved_3[0x10];
5960 u8 vxlan_udp_port[0x10];
5961};
5962
5963struct mlx5_ifc_access_register_out_bits {
5964 u8 status[0x8];
5965 u8 reserved_0[0x18];
5966
5967 u8 syndrome[0x20];
5968
5969 u8 reserved_1[0x40];
5970
5971 u8 register_data[0][0x20];
5972};
5973
5974enum {
5975 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
5976 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
5977};
5978
5979struct mlx5_ifc_access_register_in_bits {
5980 u8 opcode[0x10];
5981 u8 reserved_0[0x10];
5982
5983 u8 reserved_1[0x10];
5984 u8 op_mod[0x10];
5985
5986 u8 reserved_2[0x10];
5987 u8 register_id[0x10];
5988
5989 u8 argument[0x20];
5990
5991 u8 register_data[0][0x20];
5992};
5993
5994struct mlx5_ifc_sltp_reg_bits {
5995 u8 status[0x4];
5996 u8 version[0x4];
5997 u8 local_port[0x8];
5998 u8 pnat[0x2];
5999 u8 reserved_0[0x2];
6000 u8 lane[0x4];
6001 u8 reserved_1[0x8];
6002
6003 u8 reserved_2[0x20];
6004
6005 u8 reserved_3[0x7];
6006 u8 polarity[0x1];
6007 u8 ob_tap0[0x8];
6008 u8 ob_tap1[0x8];
6009 u8 ob_tap2[0x8];
6010
6011 u8 reserved_4[0xc];
6012 u8 ob_preemp_mode[0x4];
6013 u8 ob_reg[0x8];
6014 u8 ob_bias[0x8];
6015
6016 u8 reserved_5[0x20];
6017};
6018
6019struct mlx5_ifc_slrg_reg_bits {
6020 u8 status[0x4];
6021 u8 version[0x4];
6022 u8 local_port[0x8];
6023 u8 pnat[0x2];
6024 u8 reserved_0[0x2];
6025 u8 lane[0x4];
6026 u8 reserved_1[0x8];
6027
6028 u8 time_to_link_up[0x10];
6029 u8 reserved_2[0xc];
6030 u8 grade_lane_speed[0x4];
6031
6032 u8 grade_version[0x8];
6033 u8 grade[0x18];
6034
6035 u8 reserved_3[0x4];
6036 u8 height_grade_type[0x4];
6037 u8 height_grade[0x18];
6038
6039 u8 height_dz[0x10];
6040 u8 height_dv[0x10];
6041
6042 u8 reserved_4[0x10];
6043 u8 height_sigma[0x10];
6044
6045 u8 reserved_5[0x20];
6046
6047 u8 reserved_6[0x4];
6048 u8 phase_grade_type[0x4];
6049 u8 phase_grade[0x18];
6050
6051 u8 reserved_7[0x8];
6052 u8 phase_eo_pos[0x8];
6053 u8 reserved_8[0x8];
6054 u8 phase_eo_neg[0x8];
6055
6056 u8 ffe_set_tested[0x10];
6057 u8 test_errors_per_lane[0x10];
6058};
6059
6060struct mlx5_ifc_pvlc_reg_bits {
6061 u8 reserved_0[0x8];
6062 u8 local_port[0x8];
6063 u8 reserved_1[0x10];
6064
6065 u8 reserved_2[0x1c];
6066 u8 vl_hw_cap[0x4];
6067
6068 u8 reserved_3[0x1c];
6069 u8 vl_admin[0x4];
6070
6071 u8 reserved_4[0x1c];
6072 u8 vl_operational[0x4];
6073};
6074
6075struct mlx5_ifc_pude_reg_bits {
6076 u8 swid[0x8];
6077 u8 local_port[0x8];
6078 u8 reserved_0[0x4];
6079 u8 admin_status[0x4];
6080 u8 reserved_1[0x4];
6081 u8 oper_status[0x4];
6082
6083 u8 reserved_2[0x60];
6084};
6085
6086struct mlx5_ifc_ptys_reg_bits {
6087 u8 reserved_0[0x8];
6088 u8 local_port[0x8];
6089 u8 reserved_1[0xd];
6090 u8 proto_mask[0x3];
6091
6092 u8 reserved_2[0x40];
6093
6094 u8 eth_proto_capability[0x20];
6095
6096 u8 ib_link_width_capability[0x10];
6097 u8 ib_proto_capability[0x10];
6098
6099 u8 reserved_3[0x20];
6100
6101 u8 eth_proto_admin[0x20];
6102
6103 u8 ib_link_width_admin[0x10];
6104 u8 ib_proto_admin[0x10];
6105
6106 u8 reserved_4[0x20];
6107
6108 u8 eth_proto_oper[0x20];
6109
6110 u8 ib_link_width_oper[0x10];
6111 u8 ib_proto_oper[0x10];
6112
6113 u8 reserved_5[0x20];
6114
6115 u8 eth_proto_lp_advertise[0x20];
6116
6117 u8 reserved_6[0x60];
6118};
6119
6120struct mlx5_ifc_ptas_reg_bits {
6121 u8 reserved_0[0x20];
6122
6123 u8 algorithm_options[0x10];
6124 u8 reserved_1[0x4];
6125 u8 repetitions_mode[0x4];
6126 u8 num_of_repetitions[0x8];
6127
6128 u8 grade_version[0x8];
6129 u8 height_grade_type[0x4];
6130 u8 phase_grade_type[0x4];
6131 u8 height_grade_weight[0x8];
6132 u8 phase_grade_weight[0x8];
6133
6134 u8 gisim_measure_bits[0x10];
6135 u8 adaptive_tap_measure_bits[0x10];
6136
6137 u8 ber_bath_high_error_threshold[0x10];
6138 u8 ber_bath_mid_error_threshold[0x10];
6139
6140 u8 ber_bath_low_error_threshold[0x10];
6141 u8 one_ratio_high_threshold[0x10];
6142
6143 u8 one_ratio_high_mid_threshold[0x10];
6144 u8 one_ratio_low_mid_threshold[0x10];
6145
6146 u8 one_ratio_low_threshold[0x10];
6147 u8 ndeo_error_threshold[0x10];
6148
6149 u8 mixer_offset_step_size[0x10];
6150 u8 reserved_2[0x8];
6151 u8 mix90_phase_for_voltage_bath[0x8];
6152
6153 u8 mixer_offset_start[0x10];
6154 u8 mixer_offset_end[0x10];
6155
6156 u8 reserved_3[0x15];
6157 u8 ber_test_time[0xb];
6158};
6159
6160struct mlx5_ifc_pspa_reg_bits {
6161 u8 swid[0x8];
6162 u8 local_port[0x8];
6163 u8 sub_port[0x8];
6164 u8 reserved_0[0x8];
6165
6166 u8 reserved_1[0x20];
6167};
6168
6169struct mlx5_ifc_pqdr_reg_bits {
6170 u8 reserved_0[0x8];
6171 u8 local_port[0x8];
6172 u8 reserved_1[0x5];
6173 u8 prio[0x3];
6174 u8 reserved_2[0x6];
6175 u8 mode[0x2];
6176
6177 u8 reserved_3[0x20];
6178
6179 u8 reserved_4[0x10];
6180 u8 min_threshold[0x10];
6181
6182 u8 reserved_5[0x10];
6183 u8 max_threshold[0x10];
6184
6185 u8 reserved_6[0x10];
6186 u8 mark_probability_denominator[0x10];
6187
6188 u8 reserved_7[0x60];
6189};
6190
6191struct mlx5_ifc_ppsc_reg_bits {
6192 u8 reserved_0[0x8];
6193 u8 local_port[0x8];
6194 u8 reserved_1[0x10];
6195
6196 u8 reserved_2[0x60];
6197
6198 u8 reserved_3[0x1c];
6199 u8 wrps_admin[0x4];
6200
6201 u8 reserved_4[0x1c];
6202 u8 wrps_status[0x4];
6203
6204 u8 reserved_5[0x8];
6205 u8 up_threshold[0x8];
6206 u8 reserved_6[0x8];
6207 u8 down_threshold[0x8];
6208
6209 u8 reserved_7[0x20];
6210
6211 u8 reserved_8[0x1c];
6212 u8 srps_admin[0x4];
6213
6214 u8 reserved_9[0x1c];
6215 u8 srps_status[0x4];
6216
6217 u8 reserved_10[0x40];
6218};
6219
6220struct mlx5_ifc_pplr_reg_bits {
6221 u8 reserved_0[0x8];
6222 u8 local_port[0x8];
6223 u8 reserved_1[0x10];
6224
6225 u8 reserved_2[0x8];
6226 u8 lb_cap[0x8];
6227 u8 reserved_3[0x8];
6228 u8 lb_en[0x8];
6229};
6230
6231struct mlx5_ifc_pplm_reg_bits {
6232 u8 reserved_0[0x8];
6233 u8 local_port[0x8];
6234 u8 reserved_1[0x10];
6235
6236 u8 reserved_2[0x20];
6237
6238 u8 port_profile_mode[0x8];
6239 u8 static_port_profile[0x8];
6240 u8 active_port_profile[0x8];
6241 u8 reserved_3[0x8];
6242
6243 u8 retransmission_active[0x8];
6244 u8 fec_mode_active[0x18];
6245
6246 u8 reserved_4[0x20];
6247};
6248
6249struct mlx5_ifc_ppcnt_reg_bits {
6250 u8 swid[0x8];
6251 u8 local_port[0x8];
6252 u8 pnat[0x2];
6253 u8 reserved_0[0x8];
6254 u8 grp[0x6];
6255
6256 u8 clr[0x1];
6257 u8 reserved_1[0x1c];
6258 u8 prio_tc[0x3];
6259
6260 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
6261};
6262
6263struct mlx5_ifc_ppad_reg_bits {
6264 u8 reserved_0[0x3];
6265 u8 single_mac[0x1];
6266 u8 reserved_1[0x4];
6267 u8 local_port[0x8];
6268 u8 mac_47_32[0x10];
6269
6270 u8 mac_31_0[0x20];
6271
6272 u8 reserved_2[0x40];
6273};
6274
6275struct mlx5_ifc_pmtu_reg_bits {
6276 u8 reserved_0[0x8];
6277 u8 local_port[0x8];
6278 u8 reserved_1[0x10];
6279
6280 u8 max_mtu[0x10];
6281 u8 reserved_2[0x10];
6282
6283 u8 admin_mtu[0x10];
6284 u8 reserved_3[0x10];
6285
6286 u8 oper_mtu[0x10];
6287 u8 reserved_4[0x10];
6288};
6289
6290struct mlx5_ifc_pmpr_reg_bits {
6291 u8 reserved_0[0x8];
6292 u8 module[0x8];
6293 u8 reserved_1[0x10];
6294
6295 u8 reserved_2[0x18];
6296 u8 attenuation_5g[0x8];
6297
6298 u8 reserved_3[0x18];
6299 u8 attenuation_7g[0x8];
6300
6301 u8 reserved_4[0x18];
6302 u8 attenuation_12g[0x8];
6303};
6304
6305struct mlx5_ifc_pmpe_reg_bits {
6306 u8 reserved_0[0x8];
6307 u8 module[0x8];
6308 u8 reserved_1[0xc];
6309 u8 module_status[0x4];
6310
6311 u8 reserved_2[0x60];
6312};
6313
6314struct mlx5_ifc_pmpc_reg_bits {
6315 u8 module_state_updated[32][0x8];
6316};
6317
6318struct mlx5_ifc_pmlpn_reg_bits {
6319 u8 reserved_0[0x4];
6320 u8 mlpn_status[0x4];
6321 u8 local_port[0x8];
6322 u8 reserved_1[0x10];
6323
6324 u8 e[0x1];
6325 u8 reserved_2[0x1f];
6326};
6327
6328struct mlx5_ifc_pmlp_reg_bits {
6329 u8 rxtx[0x1];
6330 u8 reserved_0[0x7];
6331 u8 local_port[0x8];
6332 u8 reserved_1[0x8];
6333 u8 width[0x8];
6334
6335 u8 lane0_module_mapping[0x20];
6336
6337 u8 lane1_module_mapping[0x20];
6338
6339 u8 lane2_module_mapping[0x20];
6340
6341 u8 lane3_module_mapping[0x20];
6342
6343 u8 reserved_2[0x160];
6344};
6345
6346struct mlx5_ifc_pmaos_reg_bits {
6347 u8 reserved_0[0x8];
6348 u8 module[0x8];
6349 u8 reserved_1[0x4];
6350 u8 admin_status[0x4];
6351 u8 reserved_2[0x4];
6352 u8 oper_status[0x4];
6353
6354 u8 ase[0x1];
6355 u8 ee[0x1];
6356 u8 reserved_3[0x1c];
6357 u8 e[0x2];
6358
6359 u8 reserved_4[0x40];
6360};
6361
6362struct mlx5_ifc_plpc_reg_bits {
6363 u8 reserved_0[0x4];
6364 u8 profile_id[0xc];
6365 u8 reserved_1[0x4];
6366 u8 proto_mask[0x4];
6367 u8 reserved_2[0x8];
6368
6369 u8 reserved_3[0x10];
6370 u8 lane_speed[0x10];
6371
6372 u8 reserved_4[0x17];
6373 u8 lpbf[0x1];
6374 u8 fec_mode_policy[0x8];
6375
6376 u8 retransmission_capability[0x8];
6377 u8 fec_mode_capability[0x18];
6378
6379 u8 retransmission_support_admin[0x8];
6380 u8 fec_mode_support_admin[0x18];
6381
6382 u8 retransmission_request_admin[0x8];
6383 u8 fec_mode_request_admin[0x18];
6384
6385 u8 reserved_5[0x80];
6386};
6387
6388struct mlx5_ifc_plib_reg_bits {
6389 u8 reserved_0[0x8];
6390 u8 local_port[0x8];
6391 u8 reserved_1[0x8];
6392 u8 ib_port[0x8];
6393
6394 u8 reserved_2[0x60];
6395};
6396
6397struct mlx5_ifc_plbf_reg_bits {
6398 u8 reserved_0[0x8];
6399 u8 local_port[0x8];
6400 u8 reserved_1[0xd];
6401 u8 lbf_mode[0x3];
6402
6403 u8 reserved_2[0x20];
6404};
6405
6406struct mlx5_ifc_pipg_reg_bits {
6407 u8 reserved_0[0x8];
6408 u8 local_port[0x8];
6409 u8 reserved_1[0x10];
6410
6411 u8 dic[0x1];
6412 u8 reserved_2[0x19];
6413 u8 ipg[0x4];
6414 u8 reserved_3[0x2];
6415};
6416
6417struct mlx5_ifc_pifr_reg_bits {
6418 u8 reserved_0[0x8];
6419 u8 local_port[0x8];
6420 u8 reserved_1[0x10];
6421
6422 u8 reserved_2[0xe0];
6423
6424 u8 port_filter[8][0x20];
6425
6426 u8 port_filter_update_en[8][0x20];
6427};
6428
6429struct mlx5_ifc_pfcc_reg_bits {
6430 u8 reserved_0[0x8];
6431 u8 local_port[0x8];
6432 u8 reserved_1[0x10];
6433
6434 u8 ppan[0x4];
6435 u8 reserved_2[0x4];
6436 u8 prio_mask_tx[0x8];
6437 u8 reserved_3[0x8];
6438 u8 prio_mask_rx[0x8];
6439
6440 u8 pptx[0x1];
6441 u8 aptx[0x1];
6442 u8 reserved_4[0x6];
6443 u8 pfctx[0x8];
6444 u8 reserved_5[0x10];
6445
6446 u8 pprx[0x1];
6447 u8 aprx[0x1];
6448 u8 reserved_6[0x6];
6449 u8 pfcrx[0x8];
6450 u8 reserved_7[0x10];
6451
6452 u8 reserved_8[0x80];
6453};
6454
6455struct mlx5_ifc_pelc_reg_bits {
6456 u8 op[0x4];
6457 u8 reserved_0[0x4];
6458 u8 local_port[0x8];
6459 u8 reserved_1[0x10];
6460
6461 u8 op_admin[0x8];
6462 u8 op_capability[0x8];
6463 u8 op_request[0x8];
6464 u8 op_active[0x8];
6465
6466 u8 admin[0x40];
6467
6468 u8 capability[0x40];
6469
6470 u8 request[0x40];
6471
6472 u8 active[0x40];
6473
6474 u8 reserved_2[0x80];
6475};
6476
6477struct mlx5_ifc_peir_reg_bits {
6478 u8 reserved_0[0x8];
6479 u8 local_port[0x8];
6480 u8 reserved_1[0x10];
6481
6482 u8 reserved_2[0xc];
6483 u8 error_count[0x4];
6484 u8 reserved_3[0x10];
6485
6486 u8 reserved_4[0xc];
6487 u8 lane[0x4];
6488 u8 reserved_5[0x8];
6489 u8 error_type[0x8];
6490};
6491
6492struct mlx5_ifc_pcap_reg_bits {
6493 u8 reserved_0[0x8];
6494 u8 local_port[0x8];
6495 u8 reserved_1[0x10];
6496
6497 u8 port_capability_mask[4][0x20];
6498};
6499
6500struct mlx5_ifc_paos_reg_bits {
6501 u8 swid[0x8];
6502 u8 local_port[0x8];
6503 u8 reserved_0[0x4];
6504 u8 admin_status[0x4];
6505 u8 reserved_1[0x4];
6506 u8 oper_status[0x4];
6507
6508 u8 ase[0x1];
6509 u8 ee[0x1];
6510 u8 reserved_2[0x1c];
6511 u8 e[0x2];
6512
6513 u8 reserved_3[0x40];
6514};
6515
6516struct mlx5_ifc_pamp_reg_bits {
6517 u8 reserved_0[0x8];
6518 u8 opamp_group[0x8];
6519 u8 reserved_1[0xc];
6520 u8 opamp_group_type[0x4];
6521
6522 u8 start_index[0x10];
6523 u8 reserved_2[0x4];
6524 u8 num_of_indices[0xc];
6525
6526 u8 index_data[18][0x10];
6527};
6528
6529struct mlx5_ifc_lane_2_module_mapping_bits {
6530 u8 reserved_0[0x6];
6531 u8 rx_lane[0x2];
6532 u8 reserved_1[0x6];
6533 u8 tx_lane[0x2];
6534 u8 reserved_2[0x8];
6535 u8 module[0x8];
6536};
6537
6538struct mlx5_ifc_bufferx_reg_bits {
6539 u8 reserved_0[0x6];
6540 u8 lossy[0x1];
6541 u8 epsb[0x1];
6542 u8 reserved_1[0xc];
6543 u8 size[0xc];
6544
6545 u8 xoff_threshold[0x10];
6546 u8 xon_threshold[0x10];
6547};
6548
6549struct mlx5_ifc_set_node_in_bits {
6550 u8 node_description[64][0x8];
6551};
6552
6553struct mlx5_ifc_register_power_settings_bits {
6554 u8 reserved_0[0x18];
6555 u8 power_settings_level[0x8];
6556
6557 u8 reserved_1[0x60];
6558};
6559
6560struct mlx5_ifc_register_host_endianness_bits {
6561 u8 he[0x1];
6562 u8 reserved_0[0x1f];
6563
6564 u8 reserved_1[0x60];
6565};
6566
6567struct mlx5_ifc_umr_pointer_desc_argument_bits {
6568 u8 reserved_0[0x20];
6569
6570 u8 mkey[0x20];
6571
6572 u8 addressh_63_32[0x20];
6573
6574 u8 addressl_31_0[0x20];
6575};
6576
6577struct mlx5_ifc_ud_adrs_vector_bits {
6578 u8 dc_key[0x40];
6579
6580 u8 ext[0x1];
6581 u8 reserved_0[0x7];
6582 u8 destination_qp_dct[0x18];
6583
6584 u8 static_rate[0x4];
6585 u8 sl_eth_prio[0x4];
6586 u8 fl[0x1];
6587 u8 mlid[0x7];
6588 u8 rlid_udp_sport[0x10];
6589
6590 u8 reserved_1[0x20];
6591
6592 u8 rmac_47_16[0x20];
6593
6594 u8 rmac_15_0[0x10];
6595 u8 tclass[0x8];
6596 u8 hop_limit[0x8];
6597
6598 u8 reserved_2[0x1];
6599 u8 grh[0x1];
6600 u8 reserved_3[0x2];
6601 u8 src_addr_index[0x8];
6602 u8 flow_label[0x14];
6603
6604 u8 rgid_rip[16][0x8];
6605};
6606
6607struct mlx5_ifc_pages_req_event_bits {
6608 u8 reserved_0[0x10];
6609 u8 function_id[0x10];
6610
6611 u8 num_pages[0x20];
6612
6613 u8 reserved_1[0xa0];
6614};
6615
6616struct mlx5_ifc_eqe_bits {
6617 u8 reserved_0[0x8];
6618 u8 event_type[0x8];
6619 u8 reserved_1[0x8];
6620 u8 event_sub_type[0x8];
6621
6622 u8 reserved_2[0xe0];
6623
6624 union mlx5_ifc_event_auto_bits event_data;
6625
6626 u8 reserved_3[0x10];
6627 u8 signature[0x8];
6628 u8 reserved_4[0x7];
6629 u8 owner[0x1];
6630};
6631
6632enum {
6633 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
6634};
6635
6636struct mlx5_ifc_cmd_queue_entry_bits {
6637 u8 type[0x8];
6638 u8 reserved_0[0x18];
6639
6640 u8 input_length[0x20];
6641
6642 u8 input_mailbox_pointer_63_32[0x20];
6643
6644 u8 input_mailbox_pointer_31_9[0x17];
6645 u8 reserved_1[0x9];
6646
6647 u8 command_input_inline_data[16][0x8];
6648
6649 u8 command_output_inline_data[16][0x8];
6650
6651 u8 output_mailbox_pointer_63_32[0x20];
6652
6653 u8 output_mailbox_pointer_31_9[0x17];
6654 u8 reserved_2[0x9];
6655
6656 u8 output_length[0x20];
6657
6658 u8 token[0x8];
6659 u8 signature[0x8];
6660 u8 reserved_3[0x8];
6661 u8 status[0x7];
6662 u8 ownership[0x1];
6663};
6664
6665struct mlx5_ifc_cmd_out_bits {
6666 u8 status[0x8];
6667 u8 reserved_0[0x18];
6668
6669 u8 syndrome[0x20];
6670
6671 u8 command_output[0x20];
6672};
6673
6674struct mlx5_ifc_cmd_in_bits {
6675 u8 opcode[0x10];
6676 u8 reserved_0[0x10];
6677
6678 u8 reserved_1[0x10];
6679 u8 op_mod[0x10];
6680
6681 u8 command[0][0x20];
6682};
6683
6684struct mlx5_ifc_cmd_if_box_bits {
6685 u8 mailbox_data[512][0x8];
6686
6687 u8 reserved_0[0x180];
6688
6689 u8 next_pointer_63_32[0x20];
6690
6691 u8 next_pointer_31_10[0x16];
6692 u8 reserved_1[0xa];
6693
6694 u8 block_number[0x20];
6695
6696 u8 reserved_2[0x8];
6697 u8 token[0x8];
6698 u8 ctrl_signature[0x8];
6699 u8 signature[0x8];
6700};
6701
6702struct mlx5_ifc_mtt_bits {
6703 u8 ptag_63_32[0x20];
6704
6705 u8 ptag_31_8[0x18];
6706 u8 reserved_0[0x6];
6707 u8 wr_en[0x1];
6708 u8 rd_en[0x1];
6709};
6710
6711enum {
6712 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
6713 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
6714 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
6715};
6716
6717enum {
6718 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
6719 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
6720 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
6721};
6722
6723enum {
6724 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
6725 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
6726 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
6727 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
6728 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
6729 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
6730 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
6731 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
6732 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
6733 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
6734 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
6735};
6736
6737struct mlx5_ifc_initial_seg_bits {
6738 u8 fw_rev_minor[0x10];
6739 u8 fw_rev_major[0x10];
6740
6741 u8 cmd_interface_rev[0x10];
6742 u8 fw_rev_subminor[0x10];
6743
6744 u8 reserved_0[0x40];
6745
6746 u8 cmdq_phy_addr_63_32[0x20];
6747
6748 u8 cmdq_phy_addr_31_12[0x14];
6749 u8 reserved_1[0x2];
6750 u8 nic_interface[0x2];
6751 u8 log_cmdq_size[0x4];
6752 u8 log_cmdq_stride[0x4];
6753
6754 u8 command_doorbell_vector[0x20];
6755
6756 u8 reserved_2[0xf00];
6757
6758 u8 initializing[0x1];
6759 u8 reserved_3[0x4];
6760 u8 nic_interface_supported[0x3];
6761 u8 reserved_4[0x18];
6762
6763 struct mlx5_ifc_health_buffer_bits health_buffer;
6764
6765 u8 no_dram_nic_offset[0x20];
6766
6767 u8 reserved_5[0x6e40];
6768
6769 u8 reserved_6[0x1f];
6770 u8 clear_int[0x1];
6771
6772 u8 health_syndrome[0x8];
6773 u8 health_counter[0x18];
6774
6775 u8 reserved_7[0x17fc0];
6776};
6777
6778union mlx5_ifc_ports_control_registers_document_bits {
6779 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
6780 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
6781 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
6782 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
6783 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
6784 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
6785 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
6786 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
6787 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
6788 struct mlx5_ifc_pamp_reg_bits pamp_reg;
6789 struct mlx5_ifc_paos_reg_bits paos_reg;
6790 struct mlx5_ifc_pcap_reg_bits pcap_reg;
6791 struct mlx5_ifc_peir_reg_bits peir_reg;
6792 struct mlx5_ifc_pelc_reg_bits pelc_reg;
6793 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
6794 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
6795 struct mlx5_ifc_pifr_reg_bits pifr_reg;
6796 struct mlx5_ifc_pipg_reg_bits pipg_reg;
6797 struct mlx5_ifc_plbf_reg_bits plbf_reg;
6798 struct mlx5_ifc_plib_reg_bits plib_reg;
6799 struct mlx5_ifc_plpc_reg_bits plpc_reg;
6800 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
6801 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
6802 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
6803 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
6804 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
6805 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
6806 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
6807 struct mlx5_ifc_ppad_reg_bits ppad_reg;
6808 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
6809 struct mlx5_ifc_pplm_reg_bits pplm_reg;
6810 struct mlx5_ifc_pplr_reg_bits pplr_reg;
6811 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
6812 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
6813 struct mlx5_ifc_pspa_reg_bits pspa_reg;
6814 struct mlx5_ifc_ptas_reg_bits ptas_reg;
6815 struct mlx5_ifc_ptys_reg_bits ptys_reg;
6816 struct mlx5_ifc_pude_reg_bits pude_reg;
6817 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
6818 struct mlx5_ifc_slrg_reg_bits slrg_reg;
6819 struct mlx5_ifc_sltp_reg_bits sltp_reg;
6820 u8 reserved_0[0x60e0];
6821};
6822
6823union mlx5_ifc_debug_enhancements_document_bits {
6824 struct mlx5_ifc_health_buffer_bits health_buffer;
6825 u8 reserved_0[0x200];
6826};
6827
6828union mlx5_ifc_uplink_pci_interface_document_bits {
6829 struct mlx5_ifc_initial_seg_bits initial_seg;
6830 u8 reserved_0[0x20060];
b775516b
EC		 6831};
6832
d29b796a 6833#endif /* MLX5_IFC_H */
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