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net/mlx5: Make the command interface cache more flexible
[mirror_ubuntu-artful-kernel.git] / include / linux / mlx5 / mlx5_ifc.h
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d29b796a 1/*
e281682b 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
d29b796a
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
e281682b 31*/
d29b796a
EC		 32#ifndef MLX5_IFC_H
33#define MLX5_IFC_H
34
e281682b
SM		 35enum {
36 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
37 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
38 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
39 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
40 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
41 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
42 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
43 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
44 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
45 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
46 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
47 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
48 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
49 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
50 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
51 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
52 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
53 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
54 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
55 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
56 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
57 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
58 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
59 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb
60};
61
62enum {
63 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
64 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
65 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
66 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
67};
68
f91e6d89
EBE		 69enum {
70 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
71 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
72};
73
d29b796a
EC		 74enum {
75 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
76 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
77 MLX5_CMD_OP_INIT_HCA = 0x102,
78 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
79 MLX5_CMD_OP_ENABLE_HCA = 0x104,
80 MLX5_CMD_OP_DISABLE_HCA = 0x105,
81 MLX5_CMD_OP_QUERY_PAGES = 0x107,
82 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
83 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
e281682b
SM		 84 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
85 MLX5_CMD_OP_SET_ISSI = 0x10b,
d29b796a
EC		 86 MLX5_CMD_OP_CREATE_MKEY = 0x200,
87 MLX5_CMD_OP_QUERY_MKEY = 0x201,
88 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
89 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
90 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
91 MLX5_CMD_OP_CREATE_EQ = 0x301,
92 MLX5_CMD_OP_DESTROY_EQ = 0x302,
93 MLX5_CMD_OP_QUERY_EQ = 0x303,
94 MLX5_CMD_OP_GEN_EQE = 0x304,
95 MLX5_CMD_OP_CREATE_CQ = 0x400,
96 MLX5_CMD_OP_DESTROY_CQ = 0x401,
97 MLX5_CMD_OP_QUERY_CQ = 0x402,
98 MLX5_CMD_OP_MODIFY_CQ = 0x403,
99 MLX5_CMD_OP_CREATE_QP = 0x500,
100 MLX5_CMD_OP_DESTROY_QP = 0x501,
101 MLX5_CMD_OP_RST2INIT_QP = 0x502,
102 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
103 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
104 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
105 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
106 MLX5_CMD_OP_2ERR_QP = 0x507,
107 MLX5_CMD_OP_2RST_QP = 0x50a,
108 MLX5_CMD_OP_QUERY_QP = 0x50b,
e281682b 109 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
d29b796a
EC		 110 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
111 MLX5_CMD_OP_CREATE_PSV = 0x600,
112 MLX5_CMD_OP_DESTROY_PSV = 0x601,
113 MLX5_CMD_OP_CREATE_SRQ = 0x700,
114 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
115 MLX5_CMD_OP_QUERY_SRQ = 0x702,
116 MLX5_CMD_OP_ARM_RQ = 0x703,
e281682b
SM		 117 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
118 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
119 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
120 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
d29b796a
EC		 121 MLX5_CMD_OP_CREATE_DCT = 0x710,
122 MLX5_CMD_OP_DESTROY_DCT = 0x711,
123 MLX5_CMD_OP_DRAIN_DCT = 0x712,
124 MLX5_CMD_OP_QUERY_DCT = 0x713,
125 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
7486216b
SM		 126 MLX5_CMD_OP_CREATE_XRQ = 0x717,
127 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
128 MLX5_CMD_OP_QUERY_XRQ = 0x719,
129 MLX5_CMD_OP_ARM_XRQ = 0x71a,
d29b796a
EC		 130 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
131 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
132 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
133 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
134 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
135 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
e281682b 136 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
d29b796a 137 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
e281682b
SM		 138 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
139 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
140 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
141 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
d29b796a
EC		 142 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
143 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
144 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
145 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
7486216b
SM		 146 MLX5_CMD_OP_SET_RATE_LIMIT = 0x780,
147 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
813f8540
MHY		 148 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
149 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
150 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
151 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
152 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
153 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
d29b796a
EC		 154 MLX5_CMD_OP_ALLOC_PD = 0x800,
155 MLX5_CMD_OP_DEALLOC_PD = 0x801,
156 MLX5_CMD_OP_ALLOC_UAR = 0x802,
157 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
158 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
159 MLX5_CMD_OP_ACCESS_REG = 0x805,
160 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
20bb566b 161 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
d29b796a
EC		 162 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
163 MLX5_CMD_OP_MAD_IFC = 0x50d,
164 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
165 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
166 MLX5_CMD_OP_NOP = 0x80d,
167 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
168 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
e281682b
SM		 169 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
170 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
171 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
172 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
173 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
174 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
175 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
176 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
177 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
178 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
179 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
180 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
928cfe87
TT		 181 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
182 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
84df61eb
AH		 183 MLX5_CMD_OP_CREATE_LAG = 0x840,
184 MLX5_CMD_OP_MODIFY_LAG = 0x841,
185 MLX5_CMD_OP_QUERY_LAG = 0x842,
186 MLX5_CMD_OP_DESTROY_LAG = 0x843,
187 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
188 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
d29b796a
EC		 189 MLX5_CMD_OP_CREATE_TIR = 0x900,
190 MLX5_CMD_OP_MODIFY_TIR = 0x901,
191 MLX5_CMD_OP_DESTROY_TIR = 0x902,
192 MLX5_CMD_OP_QUERY_TIR = 0x903,
d29b796a
EC		 193 MLX5_CMD_OP_CREATE_SQ = 0x904,
194 MLX5_CMD_OP_MODIFY_SQ = 0x905,
195 MLX5_CMD_OP_DESTROY_SQ = 0x906,
196 MLX5_CMD_OP_QUERY_SQ = 0x907,
197 MLX5_CMD_OP_CREATE_RQ = 0x908,
198 MLX5_CMD_OP_MODIFY_RQ = 0x909,
199 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
200 MLX5_CMD_OP_QUERY_RQ = 0x90b,
201 MLX5_CMD_OP_CREATE_RMP = 0x90c,
202 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
203 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
204 MLX5_CMD_OP_QUERY_RMP = 0x90f,
e281682b
SM		 205 MLX5_CMD_OP_CREATE_TIS = 0x912,
206 MLX5_CMD_OP_MODIFY_TIS = 0x913,
207 MLX5_CMD_OP_DESTROY_TIS = 0x914,
208 MLX5_CMD_OP_QUERY_TIS = 0x915,
209 MLX5_CMD_OP_CREATE_RQT = 0x916,
210 MLX5_CMD_OP_MODIFY_RQT = 0x917,
211 MLX5_CMD_OP_DESTROY_RQT = 0x918,
212 MLX5_CMD_OP_QUERY_RQT = 0x919,
2cc43b49 213 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
e281682b
SM		 214 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
215 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
216 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
217 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
218 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
219 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
220 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
221 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
34a40e68 222 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
9dc0b289
AV		 223 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
224 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
225 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
86d56a1a 226 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
7adbde20
HHZ		 227 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d,
228 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e,
86d56a1a 229 MLX5_CMD_OP_MAX
e281682b
SM		 230};
231
232struct mlx5_ifc_flow_table_fields_supported_bits {
233 u8 outer_dmac[0x1];
234 u8 outer_smac[0x1];
235 u8 outer_ether_type[0x1];
b4ff3a36 236 u8 reserved_at_3[0x1];
e281682b
SM		 237 u8 outer_first_prio[0x1];
238 u8 outer_first_cfi[0x1];
239 u8 outer_first_vid[0x1];
b4ff3a36 240 u8 reserved_at_7[0x1];
e281682b
SM		 241 u8 outer_second_prio[0x1];
242 u8 outer_second_cfi[0x1];
243 u8 outer_second_vid[0x1];
b4ff3a36 244 u8 reserved_at_b[0x1];
e281682b
SM		 245 u8 outer_sip[0x1];
246 u8 outer_dip[0x1];
247 u8 outer_frag[0x1];
248 u8 outer_ip_protocol[0x1];
249 u8 outer_ip_ecn[0x1];
250 u8 outer_ip_dscp[0x1];
251 u8 outer_udp_sport[0x1];
252 u8 outer_udp_dport[0x1];
253 u8 outer_tcp_sport[0x1];
254 u8 outer_tcp_dport[0x1];
255 u8 outer_tcp_flags[0x1];
256 u8 outer_gre_protocol[0x1];
257 u8 outer_gre_key[0x1];
258 u8 outer_vxlan_vni[0x1];
b4ff3a36 259 u8 reserved_at_1a[0x5];
e281682b
SM		 260 u8 source_eswitch_port[0x1];
261
262 u8 inner_dmac[0x1];
263 u8 inner_smac[0x1];
264 u8 inner_ether_type[0x1];
b4ff3a36 265 u8 reserved_at_23[0x1];
e281682b
SM		 266 u8 inner_first_prio[0x1];
267 u8 inner_first_cfi[0x1];
268 u8 inner_first_vid[0x1];
b4ff3a36 269 u8 reserved_at_27[0x1];
e281682b
SM		 270 u8 inner_second_prio[0x1];
271 u8 inner_second_cfi[0x1];
272 u8 inner_second_vid[0x1];
b4ff3a36 273 u8 reserved_at_2b[0x1];
e281682b
SM		 274 u8 inner_sip[0x1];
275 u8 inner_dip[0x1];
276 u8 inner_frag[0x1];
277 u8 inner_ip_protocol[0x1];
278 u8 inner_ip_ecn[0x1];
279 u8 inner_ip_dscp[0x1];
280 u8 inner_udp_sport[0x1];
281 u8 inner_udp_dport[0x1];
282 u8 inner_tcp_sport[0x1];
283 u8 inner_tcp_dport[0x1];
284 u8 inner_tcp_flags[0x1];
b4ff3a36 285 u8 reserved_at_37[0x9];
e281682b 286
b4ff3a36 287 u8 reserved_at_40[0x40];
e281682b
SM		 288};
289
290struct mlx5_ifc_flow_table_prop_layout_bits {
291 u8 ft_support[0x1];
9dc0b289
AV		 292 u8 reserved_at_1[0x1];
293 u8 flow_counter[0x1];
26a81453 294 u8 flow_modify_en[0x1];
2cc43b49 295 u8 modify_root[0x1];
34a40e68
MG		 296 u8 identified_miss_table_mode[0x1];
297 u8 flow_table_modify[0x1];
7adbde20
HHZ		 298 u8 encap[0x1];
299 u8 decap[0x1];
300 u8 reserved_at_9[0x17];
e281682b 301
b4ff3a36 302 u8 reserved_at_20[0x2];
e281682b 303 u8 log_max_ft_size[0x6];
b4ff3a36 304 u8 reserved_at_28[0x10];
e281682b
SM		 305 u8 max_ft_level[0x8];
306
b4ff3a36 307 u8 reserved_at_40[0x20];
e281682b 308
b4ff3a36 309 u8 reserved_at_60[0x18];
e281682b
SM		 310 u8 log_max_ft_num[0x8];
311
b4ff3a36 312 u8 reserved_at_80[0x18];
e281682b
SM		 313 u8 log_max_destination[0x8];
314
b4ff3a36 315 u8 reserved_at_a0[0x18];
e281682b
SM		 316 u8 log_max_flow[0x8];
317
b4ff3a36 318 u8 reserved_at_c0[0x40];
e281682b
SM		 319
320 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
321
322 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
323};
324
325struct mlx5_ifc_odp_per_transport_service_cap_bits {
326 u8 send[0x1];
327 u8 receive[0x1];
328 u8 write[0x1];
329 u8 read[0x1];
b4ff3a36 330 u8 reserved_at_4[0x1];
e281682b 331 u8 srq_receive[0x1];
b4ff3a36 332 u8 reserved_at_6[0x1a];
e281682b
SM		 333};
334
b4d1f032 335struct mlx5_ifc_ipv4_layout_bits {
b4ff3a36 336 u8 reserved_at_0[0x60];
b4d1f032
MG		 337
338 u8 ipv4[0x20];
339};
340
341struct mlx5_ifc_ipv6_layout_bits {
342 u8 ipv6[16][0x8];
343};
344
345union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
346 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
347 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
b4ff3a36 348 u8 reserved_at_0[0x80];
b4d1f032
MG		 349};
350
e281682b
SM		 351struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
352 u8 smac_47_16[0x20];
353
354 u8 smac_15_0[0x10];
355 u8 ethertype[0x10];
356
357 u8 dmac_47_16[0x20];
358
359 u8 dmac_15_0[0x10];
360 u8 first_prio[0x3];
361 u8 first_cfi[0x1];
362 u8 first_vid[0xc];
363
364 u8 ip_protocol[0x8];
365 u8 ip_dscp[0x6];
366 u8 ip_ecn[0x2];
367 u8 vlan_tag[0x1];
b4ff3a36 368 u8 reserved_at_91[0x1];
e281682b 369 u8 frag[0x1];
b4ff3a36 370 u8 reserved_at_93[0x4];
e281682b
SM		 371 u8 tcp_flags[0x9];
372
373 u8 tcp_sport[0x10];
374 u8 tcp_dport[0x10];
375
b4ff3a36 376 u8 reserved_at_c0[0x20];
e281682b
SM		 377
378 u8 udp_sport[0x10];
379 u8 udp_dport[0x10];
380
b4d1f032 381 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
e281682b 382
b4d1f032 383 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
e281682b
SM		 384};
385
386struct mlx5_ifc_fte_match_set_misc_bits {
7486216b
SM		 387 u8 reserved_at_0[0x8];
388 u8 source_sqn[0x18];
e281682b 389
b4ff3a36 390 u8 reserved_at_20[0x10];
e281682b
SM		 391 u8 source_port[0x10];
392
393 u8 outer_second_prio[0x3];
394 u8 outer_second_cfi[0x1];
395 u8 outer_second_vid[0xc];
396 u8 inner_second_prio[0x3];
397 u8 inner_second_cfi[0x1];
398 u8 inner_second_vid[0xc];
399
400 u8 outer_second_vlan_tag[0x1];
401 u8 inner_second_vlan_tag[0x1];
b4ff3a36 402 u8 reserved_at_62[0xe];
e281682b
SM		 403 u8 gre_protocol[0x10];
404
405 u8 gre_key_h[0x18];
406 u8 gre_key_l[0x8];
407
408 u8 vxlan_vni[0x18];
b4ff3a36 409 u8 reserved_at_b8[0x8];
e281682b 410
b4ff3a36 411 u8 reserved_at_c0[0x20];
e281682b 412
b4ff3a36 413 u8 reserved_at_e0[0xc];
e281682b
SM		 414 u8 outer_ipv6_flow_label[0x14];
415
b4ff3a36 416 u8 reserved_at_100[0xc];
e281682b
SM		 417 u8 inner_ipv6_flow_label[0x14];
418
b4ff3a36 419 u8 reserved_at_120[0xe0];
e281682b
SM		 420};
421
422struct mlx5_ifc_cmd_pas_bits {
423 u8 pa_h[0x20];
424
425 u8 pa_l[0x14];
b4ff3a36 426 u8 reserved_at_34[0xc];
e281682b
SM		 427};
428
429struct mlx5_ifc_uint64_bits {
430 u8 hi[0x20];
431
432 u8 lo[0x20];
433};
434
435enum {
436 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
437 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
438 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
439 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
440 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
441 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
442 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
443 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
444 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
445 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
446};
447
448struct mlx5_ifc_ads_bits {
449 u8 fl[0x1];
450 u8 free_ar[0x1];
b4ff3a36 451 u8 reserved_at_2[0xe];
e281682b
SM		 452 u8 pkey_index[0x10];
453
b4ff3a36 454 u8 reserved_at_20[0x8];
e281682b
SM		 455 u8 grh[0x1];
456 u8 mlid[0x7];
457 u8 rlid[0x10];
458
459 u8 ack_timeout[0x5];
b4ff3a36 460 u8 reserved_at_45[0x3];
e281682b 461 u8 src_addr_index[0x8];
b4ff3a36 462 u8 reserved_at_50[0x4];
e281682b
SM		 463 u8 stat_rate[0x4];
464 u8 hop_limit[0x8];
465
b4ff3a36 466 u8 reserved_at_60[0x4];
e281682b
SM		 467 u8 tclass[0x8];
468 u8 flow_label[0x14];
469
470 u8 rgid_rip[16][0x8];
471
b4ff3a36 472 u8 reserved_at_100[0x4];
e281682b
SM		 473 u8 f_dscp[0x1];
474 u8 f_ecn[0x1];
b4ff3a36 475 u8 reserved_at_106[0x1];
e281682b
SM		 476 u8 f_eth_prio[0x1];
477 u8 ecn[0x2];
478 u8 dscp[0x6];
479 u8 udp_sport[0x10];
480
481 u8 dei_cfi[0x1];
482 u8 eth_prio[0x3];
483 u8 sl[0x4];
484 u8 port[0x8];
485 u8 rmac_47_32[0x10];
486
487 u8 rmac_31_0[0x20];
488};
489
490struct mlx5_ifc_flow_table_nic_cap_bits {
b3638e1a 491 u8 nic_rx_multi_path_tirs[0x1];
cea824d4
MG		 492 u8 nic_rx_multi_path_tirs_fts[0x1];
493 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
494 u8 reserved_at_3[0x1fd];
e281682b
SM		 495
496 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
497
b4ff3a36 498 u8 reserved_at_400[0x200];
e281682b
SM		 499
500 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
501
502 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
503
b4ff3a36 504 u8 reserved_at_a00[0x200];
e281682b
SM		 505
506 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
507
b4ff3a36 508 u8 reserved_at_e00[0x7200];
e281682b
SM		 509};
510
495716b1 511struct mlx5_ifc_flow_table_eswitch_cap_bits {
b4ff3a36 512 u8 reserved_at_0[0x200];
495716b1
SM		 513
514 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
515
516 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
517
518 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
519
b4ff3a36 520 u8 reserved_at_800[0x7800];
495716b1
SM		 521};
522
d6666753
SM		 523struct mlx5_ifc_e_switch_cap_bits {
524 u8 vport_svlan_strip[0x1];
525 u8 vport_cvlan_strip[0x1];
526 u8 vport_svlan_insert[0x1];
527 u8 vport_cvlan_insert_if_not_exist[0x1];
528 u8 vport_cvlan_insert_overwrite[0x1];
23898c76
NO		 529 u8 reserved_at_5[0x19];
530 u8 nic_vport_node_guid_modify[0x1];
531 u8 nic_vport_port_guid_modify[0x1];
d6666753 532
7adbde20
HHZ		 533 u8 vxlan_encap_decap[0x1];
534 u8 nvgre_encap_decap[0x1];
535 u8 reserved_at_22[0x9];
536 u8 log_max_encap_headers[0x5];
537 u8 reserved_2b[0x6];
538 u8 max_encap_header_size[0xa];
539
540 u8 reserved_40[0x7c0];
541
d6666753
SM		 542};
543
7486216b
SM		 544struct mlx5_ifc_qos_cap_bits {
545 u8 packet_pacing[0x1];
813f8540
MHY		 546 u8 esw_scheduling[0x1];
547 u8 reserved_at_2[0x1e];
548
549 u8 reserved_at_20[0x20];
550
7486216b 551 u8 packet_pacing_max_rate[0x20];
813f8540 552
7486216b 553 u8 packet_pacing_min_rate[0x20];
813f8540
MHY		 554
555 u8 reserved_at_80[0x10];
7486216b 556 u8 packet_pacing_rate_table_size[0x10];
813f8540
MHY		 557
558 u8 esw_element_type[0x10];
559 u8 esw_tsar_type[0x10];
560
561 u8 reserved_at_c0[0x10];
562 u8 max_qos_para_vport[0x10];
563
564 u8 max_tsar_bw_share[0x20];
565
566 u8 reserved_at_100[0x700];
7486216b
SM		 567};
568
e281682b
SM		 569struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
570 u8 csum_cap[0x1];
571 u8 vlan_cap[0x1];
572 u8 lro_cap[0x1];
573 u8 lro_psh_flag[0x1];
574 u8 lro_time_stamp[0x1];
b4ff3a36 575 u8 reserved_at_5[0x3];
66189961 576 u8 self_lb_en_modifiable[0x1];
b4ff3a36 577 u8 reserved_at_9[0x2];
e281682b 578 u8 max_lso_cap[0x5];
cff92d7c
HHZ		 579 u8 reserved_at_10[0x2];
580 u8 wqe_inline_mode[0x2];
e281682b 581 u8 rss_ind_tbl_cap[0x4];
7d5e1423
SM		 582 u8 reg_umr_sq[0x1];
583 u8 scatter_fcs[0x1];
584 u8 reserved_at_1a[0x1];
e281682b 585 u8 tunnel_lso_const_out_ip_id[0x1];
b4ff3a36 586 u8 reserved_at_1c[0x2];
e281682b
SM		 587 u8 tunnel_statless_gre[0x1];
588 u8 tunnel_stateless_vxlan[0x1];
589
b4ff3a36 590 u8 reserved_at_20[0x20];
e281682b 591
b4ff3a36 592 u8 reserved_at_40[0x10];
e281682b
SM		 593 u8 lro_min_mss_size[0x10];
594
b4ff3a36 595 u8 reserved_at_60[0x120];
e281682b
SM		 596
597 u8 lro_timer_supported_periods[4][0x20];
598
b4ff3a36 599 u8 reserved_at_200[0x600];
e281682b
SM		 600};
601
602struct mlx5_ifc_roce_cap_bits {
603 u8 roce_apm[0x1];
b4ff3a36 604 u8 reserved_at_1[0x1f];
e281682b 605
b4ff3a36 606 u8 reserved_at_20[0x60];
e281682b 607
b4ff3a36 608 u8 reserved_at_80[0xc];
e281682b 609 u8 l3_type[0x4];
b4ff3a36 610 u8 reserved_at_90[0x8];
e281682b
SM		 611 u8 roce_version[0x8];
612
b4ff3a36 613 u8 reserved_at_a0[0x10];
e281682b
SM		 614 u8 r_roce_dest_udp_port[0x10];
615
616 u8 r_roce_max_src_udp_port[0x10];
617 u8 r_roce_min_src_udp_port[0x10];
618
b4ff3a36 619 u8 reserved_at_e0[0x10];
e281682b
SM		 620 u8 roce_address_table_size[0x10];
621
b4ff3a36 622 u8 reserved_at_100[0x700];
e281682b
SM		 623};
624
625enum {
626 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
627 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
628 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
629 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
630 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
631 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
632 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
633 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
634 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
635};
636
637enum {
638 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
639 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
640 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
641 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
642 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
643 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
644 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
645 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
646 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
647};
648
649struct mlx5_ifc_atomic_caps_bits {
b4ff3a36 650 u8 reserved_at_0[0x40];
e281682b 651
f91e6d89 652 u8 atomic_req_8B_endianess_mode[0x2];
b4ff3a36 653 u8 reserved_at_42[0x4];
f91e6d89 654 u8 supported_atomic_req_8B_endianess_mode_1[0x1];
e281682b 655
b4ff3a36 656 u8 reserved_at_47[0x19];
e281682b 657
b4ff3a36 658 u8 reserved_at_60[0x20];
e281682b 659
b4ff3a36 660 u8 reserved_at_80[0x10];
f91e6d89 661 u8 atomic_operations[0x10];
e281682b 662
b4ff3a36 663 u8 reserved_at_a0[0x10];
f91e6d89
EBE		 664 u8 atomic_size_qp[0x10];
665
b4ff3a36 666 u8 reserved_at_c0[0x10];
e281682b
SM		 667 u8 atomic_size_dc[0x10];
668
b4ff3a36 669 u8 reserved_at_e0[0x720];
e281682b
SM		 670};
671
672struct mlx5_ifc_odp_cap_bits {
b4ff3a36 673 u8 reserved_at_0[0x40];
e281682b
SM		 674
675 u8 sig[0x1];
b4ff3a36 676 u8 reserved_at_41[0x1f];
e281682b 677
b4ff3a36 678 u8 reserved_at_60[0x20];
e281682b
SM		 679
680 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
681
682 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
683
684 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
685
b4ff3a36 686 u8 reserved_at_e0[0x720];
e281682b
SM		 687};
688
3f0393a5
SG		 689struct mlx5_ifc_calc_op {
690 u8 reserved_at_0[0x10];
691 u8 reserved_at_10[0x9];
692 u8 op_swap_endianness[0x1];
693 u8 op_min[0x1];
694 u8 op_xor[0x1];
695 u8 op_or[0x1];
696 u8 op_and[0x1];
697 u8 op_max[0x1];
698 u8 op_add[0x1];
699};
700
701struct mlx5_ifc_vector_calc_cap_bits {
702 u8 calc_matrix[0x1];
703 u8 reserved_at_1[0x1f];
704 u8 reserved_at_20[0x8];
705 u8 max_vec_count[0x8];
706 u8 reserved_at_30[0xd];
707 u8 max_chunk_size[0x3];
708 struct mlx5_ifc_calc_op calc0;
709 struct mlx5_ifc_calc_op calc1;
710 struct mlx5_ifc_calc_op calc2;
711 struct mlx5_ifc_calc_op calc3;
712
713 u8 reserved_at_e0[0x720];
714};
715
e281682b
SM		 716enum {
717 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
718 MLX5_WQ_TYPE_CYCLIC = 0x1,
7d5e1423 719 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
e281682b
SM		 720};
721
722enum {
723 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
724 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
725};
726
727enum {
728 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
729 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
730 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
731 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
732 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
733};
734
735enum {
736 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
737 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
738 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
739 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
740 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
741 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
742};
743
744enum {
745 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
746 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
747};
748
749enum {
750 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
751 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
752 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
753};
754
755enum {
756 MLX5_CAP_PORT_TYPE_IB = 0x0,
757 MLX5_CAP_PORT_TYPE_ETH = 0x1,
d29b796a
EC		 758};
759
b775516b 760struct mlx5_ifc_cmd_hca_cap_bits {
b4ff3a36 761 u8 reserved_at_0[0x80];
b775516b
EC		 762
763 u8 log_max_srq_sz[0x8];
764 u8 log_max_qp_sz[0x8];
b4ff3a36 765 u8 reserved_at_90[0xb];
b775516b
EC		 766 u8 log_max_qp[0x5];
767
b4ff3a36 768 u8 reserved_at_a0[0xb];
e281682b 769 u8 log_max_srq[0x5];
b4ff3a36 770 u8 reserved_at_b0[0x10];
b775516b 771
b4ff3a36 772 u8 reserved_at_c0[0x8];
b775516b 773 u8 log_max_cq_sz[0x8];
b4ff3a36 774 u8 reserved_at_d0[0xb];
b775516b
EC		 775 u8 log_max_cq[0x5];
776
777 u8 log_max_eq_sz[0x8];
b4ff3a36 778 u8 reserved_at_e8[0x2];
b775516b 779 u8 log_max_mkey[0x6];
b4ff3a36 780 u8 reserved_at_f0[0xc];
b775516b
EC		 781 u8 log_max_eq[0x4];
782
783 u8 max_indirection[0x8];
b4ff3a36 784 u8 reserved_at_108[0x1];
b775516b 785 u8 log_max_mrw_sz[0x7];
b4ff3a36 786 u8 reserved_at_110[0x2];
b775516b 787 u8 log_max_bsf_list_size[0x6];
b4ff3a36 788 u8 reserved_at_118[0x2];
b775516b
EC		 789 u8 log_max_klm_list_size[0x6];
790
b4ff3a36 791 u8 reserved_at_120[0xa];
b775516b 792 u8 log_max_ra_req_dc[0x6];
b4ff3a36 793 u8 reserved_at_130[0xa];
b775516b
EC		 794 u8 log_max_ra_res_dc[0x6];
795
b4ff3a36 796 u8 reserved_at_140[0xa];
b775516b 797 u8 log_max_ra_req_qp[0x6];
b4ff3a36 798 u8 reserved_at_150[0xa];
b775516b
EC		 799 u8 log_max_ra_res_qp[0x6];
800
801 u8 pad_cap[0x1];
802 u8 cc_query_allowed[0x1];
803 u8 cc_modify_allowed[0x1];
b4ff3a36 804 u8 reserved_at_163[0xd];
e281682b 805 u8 gid_table_size[0x10];
b775516b 806
e281682b
SM		 807 u8 out_of_seq_cnt[0x1];
808 u8 vport_counters[0x1];
7486216b 809 u8 retransmission_q_counters[0x1];
83b502a1
AV		 810 u8 reserved_at_183[0x1];
811 u8 modify_rq_counter_set_id[0x1];
812 u8 reserved_at_185[0x1];
b775516b
EC		 813 u8 max_qp_cnt[0xa];
814 u8 pkey_table_size[0x10];
815
e281682b
SM		 816 u8 vport_group_manager[0x1];
817 u8 vhca_group_manager[0x1];
818 u8 ib_virt[0x1];
819 u8 eth_virt[0x1];
b4ff3a36 820 u8 reserved_at_1a4[0x1];
e281682b
SM		 821 u8 ets[0x1];
822 u8 nic_flow_table[0x1];
54f0a411 823 u8 eswitch_flow_table[0x1];
e1c9c62b
TT		 824 u8 early_vf_enable[0x1];
825 u8 reserved_at_1a9[0x2];
b775516b 826 u8 local_ca_ack_delay[0x5];
7d5e1423
SM		 827 u8 reserved_at_1af[0x2];
828 u8 ports_check[0x1];
829 u8 reserved_at_1b2[0x1];
830 u8 disable_link_up[0x1];
831 u8 beacon_led[0x1];
e281682b 832 u8 port_type[0x2];
b775516b
EC		 833 u8 num_ports[0x8];
834
e1c9c62b 835 u8 reserved_at_1c0[0x3];
b775516b 836 u8 log_max_msg[0x5];
e1c9c62b 837 u8 reserved_at_1c8[0x4];
4f3961ee 838 u8 max_tc[0x4];
7486216b
SM		 839 u8 reserved_at_1d0[0x1];
840 u8 dcbx[0x1];
841 u8 reserved_at_1d2[0x4];
928cfe87
TT		 842 u8 rol_s[0x1];
843 u8 rol_g[0x1];
e1c9c62b 844 u8 reserved_at_1d8[0x1];
928cfe87
TT		 845 u8 wol_s[0x1];
846 u8 wol_g[0x1];
847 u8 wol_a[0x1];
848 u8 wol_b[0x1];
849 u8 wol_m[0x1];
850 u8 wol_u[0x1];
851 u8 wol_p[0x1];
b775516b
EC		 852
853 u8 stat_rate_support[0x10];
e1c9c62b 854 u8 reserved_at_1f0[0xc];
e281682b 855 u8 cqe_version[0x4];
b775516b 856
e281682b 857 u8 compact_address_vector[0x1];
7d5e1423
SM		 858 u8 striding_rq[0x1];
859 u8 reserved_at_201[0x2];
1015c2e8 860 u8 ipoib_basic_offloads[0x1];
e1c9c62b 861 u8 reserved_at_205[0xa];
e281682b 862 u8 drain_sigerr[0x1];
b775516b
EC		 863 u8 cmdif_checksum[0x2];
864 u8 sigerr_cqe[0x1];
e1c9c62b 865 u8 reserved_at_213[0x1];
b775516b
EC		 866 u8 wq_signature[0x1];
867 u8 sctr_data_cqe[0x1];
e1c9c62b 868 u8 reserved_at_216[0x1];
b775516b
EC		 869 u8 sho[0x1];
870 u8 tph[0x1];
871 u8 rf[0x1];
e281682b 872 u8 dct[0x1];
7486216b 873 u8 qos[0x1];
e281682b 874 u8 eth_net_offloads[0x1];
b775516b
EC		 875 u8 roce[0x1];
876 u8 atomic[0x1];
e1c9c62b 877 u8 reserved_at_21f[0x1];
b775516b
EC		 878
879 u8 cq_oi[0x1];
880 u8 cq_resize[0x1];
881 u8 cq_moderation[0x1];
e1c9c62b 882 u8 reserved_at_223[0x3];
e281682b 883 u8 cq_eq_remap[0x1];
b775516b
EC		 884 u8 pg[0x1];
885 u8 block_lb_mc[0x1];
e1c9c62b 886 u8 reserved_at_229[0x1];
e281682b 887 u8 scqe_break_moderation[0x1];
7d5e1423 888 u8 cq_period_start_from_cqe[0x1];
b775516b 889 u8 cd[0x1];
e1c9c62b 890 u8 reserved_at_22d[0x1];
b775516b 891 u8 apm[0x1];
3f0393a5 892 u8 vector_calc[0x1];
7d5e1423 893 u8 umr_ptr_rlky[0x1];
d2370e0a 894 u8 imaicl[0x1];
e1c9c62b 895 u8 reserved_at_232[0x4];
b775516b
EC		 896 u8 qkv[0x1];
897 u8 pkv[0x1];
b11a4f9c
HE		 898 u8 set_deth_sqpn[0x1];
899 u8 reserved_at_239[0x3];
b775516b
EC		 900 u8 xrc[0x1];
901 u8 ud[0x1];
902 u8 uc[0x1];
903 u8 rc[0x1];
904
e1c9c62b 905 u8 reserved_at_240[0xa];
b775516b 906 u8 uar_sz[0x6];
e1c9c62b 907 u8 reserved_at_250[0x8];
b775516b
EC		 908 u8 log_pg_sz[0x8];
909
910 u8 bf[0x1];
e1c9c62b 911 u8 reserved_at_261[0x1];
e281682b 912 u8 pad_tx_eth_packet[0x1];
e1c9c62b 913 u8 reserved_at_263[0x8];
b775516b 914 u8 log_bf_reg_size[0x5];
84df61eb
AH		 915
916 u8 reserved_at_270[0xb];
917 u8 lag_master[0x1];
918 u8 num_lag_ports[0x4];
b775516b 919
e1c9c62b 920 u8 reserved_at_280[0x10];
b775516b
EC		 921 u8 max_wqe_sz_sq[0x10];
922
e1c9c62b 923 u8 reserved_at_2a0[0x10];
b775516b
EC		 924 u8 max_wqe_sz_rq[0x10];
925
e1c9c62b 926 u8 reserved_at_2c0[0x10];
b775516b
EC		 927 u8 max_wqe_sz_sq_dc[0x10];
928
e1c9c62b 929 u8 reserved_at_2e0[0x7];
b775516b
EC		 930 u8 max_qp_mcg[0x19];
931
e1c9c62b 932 u8 reserved_at_300[0x18];
b775516b
EC		 933 u8 log_max_mcg[0x8];
934
e1c9c62b 935 u8 reserved_at_320[0x3];
e281682b 936 u8 log_max_transport_domain[0x5];
e1c9c62b 937 u8 reserved_at_328[0x3];
b775516b 938 u8 log_max_pd[0x5];
e1c9c62b 939 u8 reserved_at_330[0xb];
b775516b
EC		 940 u8 log_max_xrcd[0x5];
941
a351a1b0
AV		 942 u8 reserved_at_340[0x8];
943 u8 log_max_flow_counter_bulk[0x8];
944 u8 max_flow_counter[0x10];
945
b775516b 946
e1c9c62b 947 u8 reserved_at_360[0x3];
b775516b 948 u8 log_max_rq[0x5];
e1c9c62b 949 u8 reserved_at_368[0x3];
b775516b 950 u8 log_max_sq[0x5];
e1c9c62b 951 u8 reserved_at_370[0x3];
b775516b 952 u8 log_max_tir[0x5];
e1c9c62b 953 u8 reserved_at_378[0x3];
b775516b
EC		 954 u8 log_max_tis[0x5];
955
e281682b 956 u8 basic_cyclic_rcv_wqe[0x1];
e1c9c62b 957 u8 reserved_at_381[0x2];
e281682b 958 u8 log_max_rmp[0x5];
e1c9c62b 959 u8 reserved_at_388[0x3];
e281682b 960 u8 log_max_rqt[0x5];
e1c9c62b 961 u8 reserved_at_390[0x3];
e281682b 962 u8 log_max_rqt_size[0x5];
e1c9c62b 963 u8 reserved_at_398[0x3];
b775516b
EC		 964 u8 log_max_tis_per_sq[0x5];
965
e1c9c62b 966 u8 reserved_at_3a0[0x3];
e281682b 967 u8 log_max_stride_sz_rq[0x5];
e1c9c62b 968 u8 reserved_at_3a8[0x3];
e281682b 969 u8 log_min_stride_sz_rq[0x5];
e1c9c62b 970 u8 reserved_at_3b0[0x3];
e281682b 971 u8 log_max_stride_sz_sq[0x5];
e1c9c62b 972 u8 reserved_at_3b8[0x3];
e281682b
SM		 973 u8 log_min_stride_sz_sq[0x5];
974
e1c9c62b 975 u8 reserved_at_3c0[0x1b];
e281682b
SM		 976 u8 log_max_wq_sz[0x5];
977
54f0a411 978 u8 nic_vport_change_event[0x1];
e1c9c62b 979 u8 reserved_at_3e1[0xa];
54f0a411 980 u8 log_max_vlan_list[0x5];
e1c9c62b 981 u8 reserved_at_3f0[0x3];
54f0a411 982 u8 log_max_current_mc_list[0x5];
e1c9c62b 983 u8 reserved_at_3f8[0x3];
54f0a411
SM		 984 u8 log_max_current_uc_list[0x5];
985
e1c9c62b 986 u8 reserved_at_400[0x80];
54f0a411 987
e1c9c62b 988 u8 reserved_at_480[0x3];
e281682b 989 u8 log_max_l2_table[0x5];
e1c9c62b 990 u8 reserved_at_488[0x8];
b775516b
EC		 991 u8 log_uar_page_sz[0x10];
992
e1c9c62b 993 u8 reserved_at_4a0[0x20];
048ccca8 994 u8 device_frequency_mhz[0x20];
b0844444 995 u8 device_frequency_khz[0x20];
e1c9c62b
TT		 996
997 u8 reserved_at_500[0x80];
998
999 u8 reserved_at_580[0x3f];
7d5e1423 1000 u8 cqe_compression[0x1];
b775516b 1001
7d5e1423
SM		 1002 u8 cqe_compression_timeout[0x10];
1003 u8 cqe_compression_max_num[0x10];
b775516b 1004
7486216b
SM		 1005 u8 reserved_at_5e0[0x10];
1006 u8 tag_matching[0x1];
1007 u8 rndv_offload_rc[0x1];
1008 u8 rndv_offload_dc[0x1];
1009 u8 log_tag_matching_list_sz[0x5];
1010 u8 reserved_at_5e8[0x3];
1011 u8 log_max_xrq[0x5];
1012
1013 u8 reserved_at_5f0[0x200];
b775516b
EC		 1014};
1015
81848731
SM		 1016enum mlx5_flow_destination_type {
1017 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1018 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1019 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
bd5251db
AV		 1020
1021 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
e281682b 1022};
b775516b 1023
e281682b
SM		 1024struct mlx5_ifc_dest_format_struct_bits {
1025 u8 destination_type[0x8];
1026 u8 destination_id[0x18];
b775516b 1027
b4ff3a36 1028 u8 reserved_at_20[0x20];
e281682b
SM		 1029};
1030
9dc0b289 1031struct mlx5_ifc_flow_counter_list_bits {
a351a1b0
AV		 1032 u8 clear[0x1];
1033 u8 num_of_counters[0xf];
9dc0b289
AV		 1034 u8 flow_counter_id[0x10];
1035
1036 u8 reserved_at_20[0x20];
1037};
1038
1039union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1040 struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1041 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1042 u8 reserved_at_0[0x40];
1043};
1044
e281682b
SM		 1045struct mlx5_ifc_fte_match_param_bits {
1046 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1047
1048 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1049
1050 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
b775516b 1051
b4ff3a36 1052 u8 reserved_at_600[0xa00];
b775516b
EC		 1053};
1054
e281682b
SM		 1055enum {
1056 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1057 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1058 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1059 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1060 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1061};
b775516b 1062
e281682b
SM		 1063struct mlx5_ifc_rx_hash_field_select_bits {
1064 u8 l3_prot_type[0x1];
1065 u8 l4_prot_type[0x1];
1066 u8 selected_fields[0x1e];
1067};
b775516b 1068
e281682b
SM		 1069enum {
1070 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
1071 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
b775516b
EC		 1072};
1073
e281682b
SM		 1074enum {
1075 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
1076 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
1077};
1078
1079struct mlx5_ifc_wq_bits {
1080 u8 wq_type[0x4];
1081 u8 wq_signature[0x1];
1082 u8 end_padding_mode[0x2];
1083 u8 cd_slave[0x1];
b4ff3a36 1084 u8 reserved_at_8[0x18];
b775516b 1085
e281682b
SM		 1086 u8 hds_skip_first_sge[0x1];
1087 u8 log2_hds_buf_size[0x3];
b4ff3a36 1088 u8 reserved_at_24[0x7];
e281682b
SM		 1089 u8 page_offset[0x5];
1090 u8 lwm[0x10];
b775516b 1091
b4ff3a36 1092 u8 reserved_at_40[0x8];
e281682b
SM		 1093 u8 pd[0x18];
1094
b4ff3a36 1095 u8 reserved_at_60[0x8];
e281682b
SM		 1096 u8 uar_page[0x18];
1097
1098 u8 dbr_addr[0x40];
1099
1100 u8 hw_counter[0x20];
1101
1102 u8 sw_counter[0x20];
1103
b4ff3a36 1104 u8 reserved_at_100[0xc];
e281682b 1105 u8 log_wq_stride[0x4];
b4ff3a36 1106 u8 reserved_at_110[0x3];
e281682b 1107 u8 log_wq_pg_sz[0x5];
b4ff3a36 1108 u8 reserved_at_118[0x3];
e281682b
SM		 1109 u8 log_wq_sz[0x5];
1110
7d5e1423
SM		 1111 u8 reserved_at_120[0x15];
1112 u8 log_wqe_num_of_strides[0x3];
1113 u8 two_byte_shift_en[0x1];
1114 u8 reserved_at_139[0x4];
1115 u8 log_wqe_stride_size[0x3];
1116
1117 u8 reserved_at_140[0x4c0];
b775516b 1118
e281682b 1119 struct mlx5_ifc_cmd_pas_bits pas[0];
b775516b
EC		 1120};
1121
e281682b 1122struct mlx5_ifc_rq_num_bits {
b4ff3a36 1123 u8 reserved_at_0[0x8];
e281682b
SM		 1124 u8 rq_num[0x18];
1125};
b775516b 1126
e281682b 1127struct mlx5_ifc_mac_address_layout_bits {
b4ff3a36 1128 u8 reserved_at_0[0x10];
e281682b 1129 u8 mac_addr_47_32[0x10];
b775516b 1130
e281682b
SM		 1131 u8 mac_addr_31_0[0x20];
1132};
1133
c0046cf7 1134struct mlx5_ifc_vlan_layout_bits {
b4ff3a36 1135 u8 reserved_at_0[0x14];
c0046cf7
SM		 1136 u8 vlan[0x0c];
1137
b4ff3a36 1138 u8 reserved_at_20[0x20];
c0046cf7
SM		 1139};
1140
e281682b 1141struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
b4ff3a36 1142 u8 reserved_at_0[0xa0];
e281682b
SM		 1143
1144 u8 min_time_between_cnps[0x20];
1145
b4ff3a36 1146 u8 reserved_at_c0[0x12];
e281682b 1147 u8 cnp_dscp[0x6];
b4ff3a36 1148 u8 reserved_at_d8[0x5];
e281682b
SM		 1149 u8 cnp_802p_prio[0x3];
1150
b4ff3a36 1151 u8 reserved_at_e0[0x720];
e281682b
SM		 1152};
1153
1154struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
b4ff3a36 1155 u8 reserved_at_0[0x60];
e281682b 1156
b4ff3a36 1157 u8 reserved_at_60[0x4];
e281682b 1158 u8 clamp_tgt_rate[0x1];
b4ff3a36 1159 u8 reserved_at_65[0x3];
e281682b 1160 u8 clamp_tgt_rate_after_time_inc[0x1];
b4ff3a36 1161 u8 reserved_at_69[0x17];
e281682b 1162
b4ff3a36 1163 u8 reserved_at_80[0x20];
e281682b
SM		 1164
1165 u8 rpg_time_reset[0x20];
1166
1167 u8 rpg_byte_reset[0x20];
1168
1169 u8 rpg_threshold[0x20];
1170
1171 u8 rpg_max_rate[0x20];
1172
1173 u8 rpg_ai_rate[0x20];
1174
1175 u8 rpg_hai_rate[0x20];
1176
1177 u8 rpg_gd[0x20];
1178
1179 u8 rpg_min_dec_fac[0x20];
1180
1181 u8 rpg_min_rate[0x20];
1182
b4ff3a36 1183 u8 reserved_at_1c0[0xe0];
e281682b
SM		 1184
1185 u8 rate_to_set_on_first_cnp[0x20];
1186
1187 u8 dce_tcp_g[0x20];
1188
1189 u8 dce_tcp_rtt[0x20];
1190
1191 u8 rate_reduce_monitor_period[0x20];
1192
b4ff3a36 1193 u8 reserved_at_320[0x20];
e281682b
SM		 1194
1195 u8 initial_alpha_value[0x20];
1196
b4ff3a36 1197 u8 reserved_at_360[0x4a0];
e281682b
SM		 1198};
1199
1200struct mlx5_ifc_cong_control_802_1qau_rp_bits {
b4ff3a36 1201 u8 reserved_at_0[0x80];
e281682b
SM		 1202
1203 u8 rppp_max_rps[0x20];
1204
1205 u8 rpg_time_reset[0x20];
1206
1207 u8 rpg_byte_reset[0x20];
1208
1209 u8 rpg_threshold[0x20];
1210
1211 u8 rpg_max_rate[0x20];
1212
1213 u8 rpg_ai_rate[0x20];
1214
1215 u8 rpg_hai_rate[0x20];
1216
1217 u8 rpg_gd[0x20];
1218
1219 u8 rpg_min_dec_fac[0x20];
1220
1221 u8 rpg_min_rate[0x20];
1222
b4ff3a36 1223 u8 reserved_at_1c0[0x640];
e281682b
SM		 1224};
1225
1226enum {
1227 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1228 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1229 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1230};
1231
1232struct mlx5_ifc_resize_field_select_bits {
1233 u8 resize_field_select[0x20];
1234};
1235
1236enum {
1237 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1238 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1239 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1240 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1241};
1242
1243struct mlx5_ifc_modify_field_select_bits {
1244 u8 modify_field_select[0x20];
1245};
1246
1247struct mlx5_ifc_field_select_r_roce_np_bits {
1248 u8 field_select_r_roce_np[0x20];
1249};
1250
1251struct mlx5_ifc_field_select_r_roce_rp_bits {
1252 u8 field_select_r_roce_rp[0x20];
1253};
1254
1255enum {
1256 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1257 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1258 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1259 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1260 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1261 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1262 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1263 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1264 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1265 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1266};
1267
1268struct mlx5_ifc_field_select_802_1qau_rp_bits {
1269 u8 field_select_8021qaurp[0x20];
1270};
1271
1272struct mlx5_ifc_phys_layer_cntrs_bits {
1273 u8 time_since_last_clear_high[0x20];
1274
1275 u8 time_since_last_clear_low[0x20];
1276
1277 u8 symbol_errors_high[0x20];
1278
1279 u8 symbol_errors_low[0x20];
1280
1281 u8 sync_headers_errors_high[0x20];
1282
1283 u8 sync_headers_errors_low[0x20];
1284
1285 u8 edpl_bip_errors_lane0_high[0x20];
1286
1287 u8 edpl_bip_errors_lane0_low[0x20];
1288
1289 u8 edpl_bip_errors_lane1_high[0x20];
1290
1291 u8 edpl_bip_errors_lane1_low[0x20];
1292
1293 u8 edpl_bip_errors_lane2_high[0x20];
1294
1295 u8 edpl_bip_errors_lane2_low[0x20];
1296
1297 u8 edpl_bip_errors_lane3_high[0x20];
1298
1299 u8 edpl_bip_errors_lane3_low[0x20];
1300
1301 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1302
1303 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1304
1305 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1306
1307 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1308
1309 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1310
1311 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1312
1313 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1314
1315 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1316
1317 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1318
1319 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1320
1321 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1322
1323 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1324
1325 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1326
1327 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1328
1329 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1330
1331 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1332
1333 u8 rs_fec_corrected_blocks_high[0x20];
1334
1335 u8 rs_fec_corrected_blocks_low[0x20];
1336
1337 u8 rs_fec_uncorrectable_blocks_high[0x20];
1338
1339 u8 rs_fec_uncorrectable_blocks_low[0x20];
1340
1341 u8 rs_fec_no_errors_blocks_high[0x20];
1342
1343 u8 rs_fec_no_errors_blocks_low[0x20];
1344
1345 u8 rs_fec_single_error_blocks_high[0x20];
1346
1347 u8 rs_fec_single_error_blocks_low[0x20];
1348
1349 u8 rs_fec_corrected_symbols_total_high[0x20];
1350
1351 u8 rs_fec_corrected_symbols_total_low[0x20];
1352
1353 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1354
1355 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1356
1357 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1358
1359 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1360
1361 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1362
1363 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1364
1365 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1366
1367 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1368
1369 u8 link_down_events[0x20];
1370
1371 u8 successful_recovery_events[0x20];
1372
b4ff3a36 1373 u8 reserved_at_640[0x180];
e281682b
SM		 1374};
1375
1c64bf6f
MY		 1376struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1377 u8 symbol_error_counter[0x10];
1378
1379 u8 link_error_recovery_counter[0x8];
1380
1381 u8 link_downed_counter[0x8];
1382
1383 u8 port_rcv_errors[0x10];
1384
1385 u8 port_rcv_remote_physical_errors[0x10];
1386
1387 u8 port_rcv_switch_relay_errors[0x10];
1388
1389 u8 port_xmit_discards[0x10];
1390
1391 u8 port_xmit_constraint_errors[0x8];
1392
1393 u8 port_rcv_constraint_errors[0x8];
1394
1395 u8 reserved_at_70[0x8];
1396
1397 u8 link_overrun_errors[0x8];
1398
1399 u8 reserved_at_80[0x10];
1400
1401 u8 vl_15_dropped[0x10];
1402
1403 u8 reserved_at_a0[0xa0];
1404};
1405
e281682b
SM		 1406struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1407 u8 transmit_queue_high[0x20];
1408
1409 u8 transmit_queue_low[0x20];
1410
b4ff3a36 1411 u8 reserved_at_40[0x780];
e281682b
SM		 1412};
1413
1414struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1415 u8 rx_octets_high[0x20];
1416
1417 u8 rx_octets_low[0x20];
1418
b4ff3a36 1419 u8 reserved_at_40[0xc0];
e281682b
SM		 1420
1421 u8 rx_frames_high[0x20];
1422
1423 u8 rx_frames_low[0x20];
1424
1425 u8 tx_octets_high[0x20];
1426
1427 u8 tx_octets_low[0x20];
1428
b4ff3a36 1429 u8 reserved_at_180[0xc0];
e281682b
SM		 1430
1431 u8 tx_frames_high[0x20];
1432
1433 u8 tx_frames_low[0x20];
1434
1435 u8 rx_pause_high[0x20];
1436
1437 u8 rx_pause_low[0x20];
1438
1439 u8 rx_pause_duration_high[0x20];
1440
1441 u8 rx_pause_duration_low[0x20];
1442
1443 u8 tx_pause_high[0x20];
1444
1445 u8 tx_pause_low[0x20];
1446
1447 u8 tx_pause_duration_high[0x20];
1448
1449 u8 tx_pause_duration_low[0x20];
1450
1451 u8 rx_pause_transition_high[0x20];
1452
1453 u8 rx_pause_transition_low[0x20];
1454
b4ff3a36 1455 u8 reserved_at_3c0[0x400];
e281682b
SM		 1456};
1457
1458struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1459 u8 port_transmit_wait_high[0x20];
1460
1461 u8 port_transmit_wait_low[0x20];
1462
b4ff3a36 1463 u8 reserved_at_40[0x780];
e281682b
SM		 1464};
1465
1466struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1467 u8 dot3stats_alignment_errors_high[0x20];
1468
1469 u8 dot3stats_alignment_errors_low[0x20];
1470
1471 u8 dot3stats_fcs_errors_high[0x20];
1472
1473 u8 dot3stats_fcs_errors_low[0x20];
1474
1475 u8 dot3stats_single_collision_frames_high[0x20];
1476
1477 u8 dot3stats_single_collision_frames_low[0x20];
1478
1479 u8 dot3stats_multiple_collision_frames_high[0x20];
1480
1481 u8 dot3stats_multiple_collision_frames_low[0x20];
1482
1483 u8 dot3stats_sqe_test_errors_high[0x20];
1484
1485 u8 dot3stats_sqe_test_errors_low[0x20];
1486
1487 u8 dot3stats_deferred_transmissions_high[0x20];
1488
1489 u8 dot3stats_deferred_transmissions_low[0x20];
1490
1491 u8 dot3stats_late_collisions_high[0x20];
1492
1493 u8 dot3stats_late_collisions_low[0x20];
1494
1495 u8 dot3stats_excessive_collisions_high[0x20];
1496
1497 u8 dot3stats_excessive_collisions_low[0x20];
1498
1499 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1500
1501 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1502
1503 u8 dot3stats_carrier_sense_errors_high[0x20];
1504
1505 u8 dot3stats_carrier_sense_errors_low[0x20];
1506
1507 u8 dot3stats_frame_too_longs_high[0x20];
1508
1509 u8 dot3stats_frame_too_longs_low[0x20];
1510
1511 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1512
1513 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1514
1515 u8 dot3stats_symbol_errors_high[0x20];
1516
1517 u8 dot3stats_symbol_errors_low[0x20];
1518
1519 u8 dot3control_in_unknown_opcodes_high[0x20];
1520
1521 u8 dot3control_in_unknown_opcodes_low[0x20];
1522
1523 u8 dot3in_pause_frames_high[0x20];
1524
1525 u8 dot3in_pause_frames_low[0x20];
1526
1527 u8 dot3out_pause_frames_high[0x20];
1528
1529 u8 dot3out_pause_frames_low[0x20];
1530
b4ff3a36 1531 u8 reserved_at_400[0x3c0];
e281682b
SM		 1532};
1533
1534struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1535 u8 ether_stats_drop_events_high[0x20];
1536
1537 u8 ether_stats_drop_events_low[0x20];
1538
1539 u8 ether_stats_octets_high[0x20];
1540
1541 u8 ether_stats_octets_low[0x20];
1542
1543 u8 ether_stats_pkts_high[0x20];
1544
1545 u8 ether_stats_pkts_low[0x20];
1546
1547 u8 ether_stats_broadcast_pkts_high[0x20];
1548
1549 u8 ether_stats_broadcast_pkts_low[0x20];
1550
1551 u8 ether_stats_multicast_pkts_high[0x20];
1552
1553 u8 ether_stats_multicast_pkts_low[0x20];
1554
1555 u8 ether_stats_crc_align_errors_high[0x20];
1556
1557 u8 ether_stats_crc_align_errors_low[0x20];
1558
1559 u8 ether_stats_undersize_pkts_high[0x20];
1560
1561 u8 ether_stats_undersize_pkts_low[0x20];
1562
1563 u8 ether_stats_oversize_pkts_high[0x20];
1564
1565 u8 ether_stats_oversize_pkts_low[0x20];
1566
1567 u8 ether_stats_fragments_high[0x20];
1568
1569 u8 ether_stats_fragments_low[0x20];
1570
1571 u8 ether_stats_jabbers_high[0x20];
1572
1573 u8 ether_stats_jabbers_low[0x20];
1574
1575 u8 ether_stats_collisions_high[0x20];
1576
1577 u8 ether_stats_collisions_low[0x20];
1578
1579 u8 ether_stats_pkts64octets_high[0x20];
1580
1581 u8 ether_stats_pkts64octets_low[0x20];
1582
1583 u8 ether_stats_pkts65to127octets_high[0x20];
1584
1585 u8 ether_stats_pkts65to127octets_low[0x20];
1586
1587 u8 ether_stats_pkts128to255octets_high[0x20];
1588
1589 u8 ether_stats_pkts128to255octets_low[0x20];
1590
1591 u8 ether_stats_pkts256to511octets_high[0x20];
1592
1593 u8 ether_stats_pkts256to511octets_low[0x20];
1594
1595 u8 ether_stats_pkts512to1023octets_high[0x20];
1596
1597 u8 ether_stats_pkts512to1023octets_low[0x20];
1598
1599 u8 ether_stats_pkts1024to1518octets_high[0x20];
1600
1601 u8 ether_stats_pkts1024to1518octets_low[0x20];
1602
1603 u8 ether_stats_pkts1519to2047octets_high[0x20];
1604
1605 u8 ether_stats_pkts1519to2047octets_low[0x20];
1606
1607 u8 ether_stats_pkts2048to4095octets_high[0x20];
1608
1609 u8 ether_stats_pkts2048to4095octets_low[0x20];
1610
1611 u8 ether_stats_pkts4096to8191octets_high[0x20];
1612
1613 u8 ether_stats_pkts4096to8191octets_low[0x20];
1614
1615 u8 ether_stats_pkts8192to10239octets_high[0x20];
1616
1617 u8 ether_stats_pkts8192to10239octets_low[0x20];
1618
b4ff3a36 1619 u8 reserved_at_540[0x280];
e281682b
SM		 1620};
1621
1622struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1623 u8 if_in_octets_high[0x20];
1624
1625 u8 if_in_octets_low[0x20];
1626
1627 u8 if_in_ucast_pkts_high[0x20];
1628
1629 u8 if_in_ucast_pkts_low[0x20];
1630
1631 u8 if_in_discards_high[0x20];
1632
1633 u8 if_in_discards_low[0x20];
1634
1635 u8 if_in_errors_high[0x20];
1636
1637 u8 if_in_errors_low[0x20];
1638
1639 u8 if_in_unknown_protos_high[0x20];
1640
1641 u8 if_in_unknown_protos_low[0x20];
1642
1643 u8 if_out_octets_high[0x20];
1644
1645 u8 if_out_octets_low[0x20];
1646
1647 u8 if_out_ucast_pkts_high[0x20];
1648
1649 u8 if_out_ucast_pkts_low[0x20];
1650
1651 u8 if_out_discards_high[0x20];
1652
1653 u8 if_out_discards_low[0x20];
1654
1655 u8 if_out_errors_high[0x20];
1656
1657 u8 if_out_errors_low[0x20];
1658
1659 u8 if_in_multicast_pkts_high[0x20];
1660
1661 u8 if_in_multicast_pkts_low[0x20];
1662
1663 u8 if_in_broadcast_pkts_high[0x20];
1664
1665 u8 if_in_broadcast_pkts_low[0x20];
1666
1667 u8 if_out_multicast_pkts_high[0x20];
1668
1669 u8 if_out_multicast_pkts_low[0x20];
1670
1671 u8 if_out_broadcast_pkts_high[0x20];
1672
1673 u8 if_out_broadcast_pkts_low[0x20];
1674
b4ff3a36 1675 u8 reserved_at_340[0x480];
e281682b
SM		 1676};
1677
1678struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1679 u8 a_frames_transmitted_ok_high[0x20];
1680
1681 u8 a_frames_transmitted_ok_low[0x20];
1682
1683 u8 a_frames_received_ok_high[0x20];
1684
1685 u8 a_frames_received_ok_low[0x20];
1686
1687 u8 a_frame_check_sequence_errors_high[0x20];
1688
1689 u8 a_frame_check_sequence_errors_low[0x20];
1690
1691 u8 a_alignment_errors_high[0x20];
1692
1693 u8 a_alignment_errors_low[0x20];
1694
1695 u8 a_octets_transmitted_ok_high[0x20];
1696
1697 u8 a_octets_transmitted_ok_low[0x20];
1698
1699 u8 a_octets_received_ok_high[0x20];
1700
1701 u8 a_octets_received_ok_low[0x20];
1702
1703 u8 a_multicast_frames_xmitted_ok_high[0x20];
1704
1705 u8 a_multicast_frames_xmitted_ok_low[0x20];
1706
1707 u8 a_broadcast_frames_xmitted_ok_high[0x20];
1708
1709 u8 a_broadcast_frames_xmitted_ok_low[0x20];
1710
1711 u8 a_multicast_frames_received_ok_high[0x20];
1712
1713 u8 a_multicast_frames_received_ok_low[0x20];
1714
1715 u8 a_broadcast_frames_received_ok_high[0x20];
1716
1717 u8 a_broadcast_frames_received_ok_low[0x20];
1718
1719 u8 a_in_range_length_errors_high[0x20];
1720
1721 u8 a_in_range_length_errors_low[0x20];
1722
1723 u8 a_out_of_range_length_field_high[0x20];
1724
1725 u8 a_out_of_range_length_field_low[0x20];
1726
1727 u8 a_frame_too_long_errors_high[0x20];
1728
1729 u8 a_frame_too_long_errors_low[0x20];
1730
1731 u8 a_symbol_error_during_carrier_high[0x20];
1732
1733 u8 a_symbol_error_during_carrier_low[0x20];
1734
1735 u8 a_mac_control_frames_transmitted_high[0x20];
1736
1737 u8 a_mac_control_frames_transmitted_low[0x20];
1738
1739 u8 a_mac_control_frames_received_high[0x20];
1740
1741 u8 a_mac_control_frames_received_low[0x20];
1742
1743 u8 a_unsupported_opcodes_received_high[0x20];
1744
1745 u8 a_unsupported_opcodes_received_low[0x20];
1746
1747 u8 a_pause_mac_ctrl_frames_received_high[0x20];
1748
1749 u8 a_pause_mac_ctrl_frames_received_low[0x20];
1750
1751 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
1752
1753 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
1754
b4ff3a36 1755 u8 reserved_at_4c0[0x300];
e281682b
SM		 1756};
1757
1758struct mlx5_ifc_cmd_inter_comp_event_bits {
1759 u8 command_completion_vector[0x20];
1760
b4ff3a36 1761 u8 reserved_at_20[0xc0];
e281682b
SM		 1762};
1763
1764struct mlx5_ifc_stall_vl_event_bits {
b4ff3a36 1765 u8 reserved_at_0[0x18];
e281682b 1766 u8 port_num[0x1];
b4ff3a36 1767 u8 reserved_at_19[0x3];
e281682b
SM		 1768 u8 vl[0x4];
1769
b4ff3a36 1770 u8 reserved_at_20[0xa0];
e281682b
SM		 1771};
1772
1773struct mlx5_ifc_db_bf_congestion_event_bits {
1774 u8 event_subtype[0x8];
b4ff3a36 1775 u8 reserved_at_8[0x8];
e281682b 1776 u8 congestion_level[0x8];
b4ff3a36 1777 u8 reserved_at_18[0x8];
e281682b 1778
b4ff3a36 1779 u8 reserved_at_20[0xa0];
e281682b
SM		 1780};
1781
1782struct mlx5_ifc_gpio_event_bits {
b4ff3a36 1783 u8 reserved_at_0[0x60];
e281682b
SM		 1784
1785 u8 gpio_event_hi[0x20];
1786
1787 u8 gpio_event_lo[0x20];
1788
b4ff3a36 1789 u8 reserved_at_a0[0x40];
e281682b
SM		 1790};
1791
1792struct mlx5_ifc_port_state_change_event_bits {
b4ff3a36 1793 u8 reserved_at_0[0x40];
e281682b
SM		 1794
1795 u8 port_num[0x4];
b4ff3a36 1796 u8 reserved_at_44[0x1c];
e281682b 1797
b4ff3a36 1798 u8 reserved_at_60[0x80];
e281682b
SM		 1799};
1800
1801struct mlx5_ifc_dropped_packet_logged_bits {
b4ff3a36 1802 u8 reserved_at_0[0xe0];
e281682b
SM		 1803};
1804
1805enum {
1806 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
1807 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
1808};
1809
1810struct mlx5_ifc_cq_error_bits {
b4ff3a36 1811 u8 reserved_at_0[0x8];
e281682b
SM		 1812 u8 cqn[0x18];
1813
b4ff3a36 1814 u8 reserved_at_20[0x20];
e281682b 1815
b4ff3a36 1816 u8 reserved_at_40[0x18];
e281682b
SM		 1817 u8 syndrome[0x8];
1818
b4ff3a36 1819 u8 reserved_at_60[0x80];
e281682b
SM		 1820};
1821
1822struct mlx5_ifc_rdma_page_fault_event_bits {
1823 u8 bytes_committed[0x20];
1824
1825 u8 r_key[0x20];
1826
b4ff3a36 1827 u8 reserved_at_40[0x10];
e281682b
SM		 1828 u8 packet_len[0x10];
1829
1830 u8 rdma_op_len[0x20];
1831
1832 u8 rdma_va[0x40];
1833
b4ff3a36 1834 u8 reserved_at_c0[0x5];
e281682b
SM		 1835 u8 rdma[0x1];
1836 u8 write[0x1];
1837 u8 requestor[0x1];
1838 u8 qp_number[0x18];
1839};
1840
1841struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1842 u8 bytes_committed[0x20];
1843
b4ff3a36 1844 u8 reserved_at_20[0x10];
e281682b
SM		 1845 u8 wqe_index[0x10];
1846
b4ff3a36 1847 u8 reserved_at_40[0x10];
e281682b
SM		 1848 u8 len[0x10];
1849
b4ff3a36 1850 u8 reserved_at_60[0x60];
e281682b 1851
b4ff3a36 1852 u8 reserved_at_c0[0x5];
e281682b
SM		 1853 u8 rdma[0x1];
1854 u8 write_read[0x1];
1855 u8 requestor[0x1];
1856 u8 qpn[0x18];
1857};
1858
1859struct mlx5_ifc_qp_events_bits {
b4ff3a36 1860 u8 reserved_at_0[0xa0];
e281682b
SM		 1861
1862 u8 type[0x8];
b4ff3a36 1863 u8 reserved_at_a8[0x18];
e281682b 1864
b4ff3a36 1865 u8 reserved_at_c0[0x8];
e281682b
SM		 1866 u8 qpn_rqn_sqn[0x18];
1867};
1868
1869struct mlx5_ifc_dct_events_bits {
b4ff3a36 1870 u8 reserved_at_0[0xc0];
e281682b 1871
b4ff3a36 1872 u8 reserved_at_c0[0x8];
e281682b
SM		 1873 u8 dct_number[0x18];
1874};
1875
1876struct mlx5_ifc_comp_event_bits {
b4ff3a36 1877 u8 reserved_at_0[0xc0];
e281682b 1878
b4ff3a36 1879 u8 reserved_at_c0[0x8];
e281682b
SM		 1880 u8 cq_number[0x18];
1881};
1882
1883enum {
1884 MLX5_QPC_STATE_RST = 0x0,
1885 MLX5_QPC_STATE_INIT = 0x1,
1886 MLX5_QPC_STATE_RTR = 0x2,
1887 MLX5_QPC_STATE_RTS = 0x3,
1888 MLX5_QPC_STATE_SQER = 0x4,
1889 MLX5_QPC_STATE_ERR = 0x6,
1890 MLX5_QPC_STATE_SQD = 0x7,
1891 MLX5_QPC_STATE_SUSPENDED = 0x9,
1892};
1893
1894enum {
1895 MLX5_QPC_ST_RC = 0x0,
1896 MLX5_QPC_ST_UC = 0x1,
1897 MLX5_QPC_ST_UD = 0x2,
1898 MLX5_QPC_ST_XRC = 0x3,
1899 MLX5_QPC_ST_DCI = 0x5,
1900 MLX5_QPC_ST_QP0 = 0x7,
1901 MLX5_QPC_ST_QP1 = 0x8,
1902 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
1903 MLX5_QPC_ST_REG_UMR = 0xc,
1904};
1905
1906enum {
1907 MLX5_QPC_PM_STATE_ARMED = 0x0,
1908 MLX5_QPC_PM_STATE_REARM = 0x1,
1909 MLX5_QPC_PM_STATE_RESERVED = 0x2,
1910 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
1911};
1912
1913enum {
1914 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
1915 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
1916};
1917
1918enum {
1919 MLX5_QPC_MTU_256_BYTES = 0x1,
1920 MLX5_QPC_MTU_512_BYTES = 0x2,
1921 MLX5_QPC_MTU_1K_BYTES = 0x3,
1922 MLX5_QPC_MTU_2K_BYTES = 0x4,
1923 MLX5_QPC_MTU_4K_BYTES = 0x5,
1924 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
1925};
1926
1927enum {
1928 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
1929 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
1930 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
1931 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
1932 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
1933 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
1934 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
1935 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
1936};
1937
1938enum {
1939 MLX5_QPC_CS_REQ_DISABLE = 0x0,
1940 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
1941 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
1942};
1943
1944enum {
1945 MLX5_QPC_CS_RES_DISABLE = 0x0,
1946 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
1947 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
1948};
1949
1950struct mlx5_ifc_qpc_bits {
1951 u8 state[0x4];
84df61eb 1952 u8 lag_tx_port_affinity[0x4];
e281682b 1953 u8 st[0x8];
b4ff3a36 1954 u8 reserved_at_10[0x3];
e281682b 1955 u8 pm_state[0x2];
b4ff3a36 1956 u8 reserved_at_15[0x7];
e281682b 1957 u8 end_padding_mode[0x2];
b4ff3a36 1958 u8 reserved_at_1e[0x2];
e281682b
SM		 1959
1960 u8 wq_signature[0x1];
1961 u8 block_lb_mc[0x1];
1962 u8 atomic_like_write_en[0x1];
1963 u8 latency_sensitive[0x1];
b4ff3a36 1964 u8 reserved_at_24[0x1];
e281682b 1965 u8 drain_sigerr[0x1];
b4ff3a36 1966 u8 reserved_at_26[0x2];
e281682b
SM		 1967 u8 pd[0x18];
1968
1969 u8 mtu[0x3];
1970 u8 log_msg_max[0x5];
b4ff3a36 1971 u8 reserved_at_48[0x1];
e281682b
SM		 1972 u8 log_rq_size[0x4];
1973 u8 log_rq_stride[0x3];
1974 u8 no_sq[0x1];
1975 u8 log_sq_size[0x4];
b4ff3a36 1976 u8 reserved_at_55[0x6];
e281682b 1977 u8 rlky[0x1];
1015c2e8 1978 u8 ulp_stateless_offload_mode[0x4];
e281682b
SM		 1979
1980 u8 counter_set_id[0x8];
1981 u8 uar_page[0x18];
1982
b4ff3a36 1983 u8 reserved_at_80[0x8];
e281682b
SM		 1984 u8 user_index[0x18];
1985
b4ff3a36 1986 u8 reserved_at_a0[0x3];
e281682b
SM		 1987 u8 log_page_size[0x5];
1988 u8 remote_qpn[0x18];
1989
1990 struct mlx5_ifc_ads_bits primary_address_path;
1991
1992 struct mlx5_ifc_ads_bits secondary_address_path;
1993
1994 u8 log_ack_req_freq[0x4];
b4ff3a36 1995 u8 reserved_at_384[0x4];
e281682b 1996 u8 log_sra_max[0x3];
b4ff3a36 1997 u8 reserved_at_38b[0x2];
e281682b
SM		 1998 u8 retry_count[0x3];
1999 u8 rnr_retry[0x3];
b4ff3a36 2000 u8 reserved_at_393[0x1];
e281682b
SM		 2001 u8 fre[0x1];
2002 u8 cur_rnr_retry[0x3];
2003 u8 cur_retry_count[0x3];
b4ff3a36 2004 u8 reserved_at_39b[0x5];
e281682b 2005
b4ff3a36 2006 u8 reserved_at_3a0[0x20];
e281682b 2007
b4ff3a36 2008 u8 reserved_at_3c0[0x8];
e281682b
SM		 2009 u8 next_send_psn[0x18];
2010
b4ff3a36 2011 u8 reserved_at_3e0[0x8];
e281682b
SM		 2012 u8 cqn_snd[0x18];
2013
09a7d9ec
SM		 2014 u8 reserved_at_400[0x8];
2015 u8 deth_sqpn[0x18];
2016
2017 u8 reserved_at_420[0x20];
e281682b 2018
b4ff3a36 2019 u8 reserved_at_440[0x8];
e281682b
SM		 2020 u8 last_acked_psn[0x18];
2021
b4ff3a36 2022 u8 reserved_at_460[0x8];
e281682b
SM		 2023 u8 ssn[0x18];
2024
b4ff3a36 2025 u8 reserved_at_480[0x8];
e281682b 2026 u8 log_rra_max[0x3];
b4ff3a36 2027 u8 reserved_at_48b[0x1];
e281682b
SM		 2028 u8 atomic_mode[0x4];
2029 u8 rre[0x1];
2030 u8 rwe[0x1];
2031 u8 rae[0x1];
b4ff3a36 2032 u8 reserved_at_493[0x1];
e281682b 2033 u8 page_offset[0x6];
b4ff3a36 2034 u8 reserved_at_49a[0x3];
e281682b
SM		 2035 u8 cd_slave_receive[0x1];
2036 u8 cd_slave_send[0x1];
2037 u8 cd_master[0x1];
2038
b4ff3a36 2039 u8 reserved_at_4a0[0x3];
e281682b
SM		 2040 u8 min_rnr_nak[0x5];
2041 u8 next_rcv_psn[0x18];
2042
b4ff3a36 2043 u8 reserved_at_4c0[0x8];
e281682b
SM		 2044 u8 xrcd[0x18];
2045
b4ff3a36 2046 u8 reserved_at_4e0[0x8];
e281682b
SM		 2047 u8 cqn_rcv[0x18];
2048
2049 u8 dbr_addr[0x40];
2050
2051 u8 q_key[0x20];
2052
b4ff3a36 2053 u8 reserved_at_560[0x5];
e281682b 2054 u8 rq_type[0x3];
7486216b 2055 u8 srqn_rmpn_xrqn[0x18];
e281682b 2056
b4ff3a36 2057 u8 reserved_at_580[0x8];
e281682b
SM		 2058 u8 rmsn[0x18];
2059
2060 u8 hw_sq_wqebb_counter[0x10];
2061 u8 sw_sq_wqebb_counter[0x10];
2062
2063 u8 hw_rq_counter[0x20];
2064
2065 u8 sw_rq_counter[0x20];
2066
b4ff3a36 2067 u8 reserved_at_600[0x20];
e281682b 2068
b4ff3a36 2069 u8 reserved_at_620[0xf];
e281682b
SM		 2070 u8 cgs[0x1];
2071 u8 cs_req[0x8];
2072 u8 cs_res[0x8];
2073
2074 u8 dc_access_key[0x40];
2075
b4ff3a36 2076 u8 reserved_at_680[0xc0];
e281682b
SM		 2077};
2078
2079struct mlx5_ifc_roce_addr_layout_bits {
2080 u8 source_l3_address[16][0x8];
2081
b4ff3a36 2082 u8 reserved_at_80[0x3];
e281682b
SM		 2083 u8 vlan_valid[0x1];
2084 u8 vlan_id[0xc];
2085 u8 source_mac_47_32[0x10];
2086
2087 u8 source_mac_31_0[0x20];
2088
b4ff3a36 2089 u8 reserved_at_c0[0x14];
e281682b
SM		 2090 u8 roce_l3_type[0x4];
2091 u8 roce_version[0x8];
2092
b4ff3a36 2093 u8 reserved_at_e0[0x20];
e281682b
SM		 2094};
2095
2096union mlx5_ifc_hca_cap_union_bits {
2097 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2098 struct mlx5_ifc_odp_cap_bits odp_cap;
2099 struct mlx5_ifc_atomic_caps_bits atomic_caps;
2100 struct mlx5_ifc_roce_cap_bits roce_cap;
2101 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2102 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
495716b1 2103 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
d6666753 2104 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
3f0393a5 2105 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
7486216b 2106 struct mlx5_ifc_qos_cap_bits qos_cap;
b4ff3a36 2107 u8 reserved_at_0[0x8000];
e281682b
SM		 2108};
2109
2110enum {
2111 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
2112 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
2113 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
9dc0b289 2114 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
7adbde20
HHZ		 2115 MLX5_FLOW_CONTEXT_ACTION_ENCAP = 0x10,
2116 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
e281682b
SM		 2117};
2118
2119struct mlx5_ifc_flow_context_bits {
b4ff3a36 2120 u8 reserved_at_0[0x20];
e281682b
SM		 2121
2122 u8 group_id[0x20];
2123
b4ff3a36 2124 u8 reserved_at_40[0x8];
e281682b
SM		 2125 u8 flow_tag[0x18];
2126
b4ff3a36 2127 u8 reserved_at_60[0x10];
e281682b
SM		 2128 u8 action[0x10];
2129
b4ff3a36 2130 u8 reserved_at_80[0x8];
e281682b
SM		 2131 u8 destination_list_size[0x18];
2132
9dc0b289
AV		 2133 u8 reserved_at_a0[0x8];
2134 u8 flow_counter_list_size[0x18];
2135
7adbde20
HHZ		 2136 u8 encap_id[0x20];
2137
2138 u8 reserved_at_e0[0x120];
e281682b
SM		 2139
2140 struct mlx5_ifc_fte_match_param_bits match_value;
2141
b4ff3a36 2142 u8 reserved_at_1200[0x600];
e281682b 2143
9dc0b289 2144 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
e281682b
SM		 2145};
2146
2147enum {
2148 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
2149 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
2150};
2151
2152struct mlx5_ifc_xrc_srqc_bits {
2153 u8 state[0x4];
2154 u8 log_xrc_srq_size[0x4];
b4ff3a36 2155 u8 reserved_at_8[0x18];
e281682b
SM		 2156
2157 u8 wq_signature[0x1];
2158 u8 cont_srq[0x1];
b4ff3a36 2159 u8 reserved_at_22[0x1];
e281682b
SM		 2160 u8 rlky[0x1];
2161 u8 basic_cyclic_rcv_wqe[0x1];
2162 u8 log_rq_stride[0x3];
2163 u8 xrcd[0x18];
2164
2165 u8 page_offset[0x6];
b4ff3a36 2166 u8 reserved_at_46[0x2];
e281682b
SM		 2167 u8 cqn[0x18];
2168
b4ff3a36 2169 u8 reserved_at_60[0x20];
e281682b
SM		 2170
2171 u8 user_index_equal_xrc_srqn[0x1];
b4ff3a36 2172 u8 reserved_at_81[0x1];
e281682b
SM		 2173 u8 log_page_size[0x6];
2174 u8 user_index[0x18];
2175
b4ff3a36 2176 u8 reserved_at_a0[0x20];
e281682b 2177
b4ff3a36 2178 u8 reserved_at_c0[0x8];
e281682b
SM		 2179 u8 pd[0x18];
2180
2181 u8 lwm[0x10];
2182 u8 wqe_cnt[0x10];
2183
b4ff3a36 2184 u8 reserved_at_100[0x40];
e281682b
SM		 2185
2186 u8 db_record_addr_h[0x20];
2187
2188 u8 db_record_addr_l[0x1e];
b4ff3a36 2189 u8 reserved_at_17e[0x2];
e281682b 2190
b4ff3a36 2191 u8 reserved_at_180[0x80];
e281682b
SM		 2192};
2193
2194struct mlx5_ifc_traffic_counter_bits {
2195 u8 packets[0x40];
2196
2197 u8 octets[0x40];
2198};
2199
2200struct mlx5_ifc_tisc_bits {
84df61eb
AH		 2201 u8 strict_lag_tx_port_affinity[0x1];
2202 u8 reserved_at_1[0x3];
2203 u8 lag_tx_port_affinity[0x04];
2204
2205 u8 reserved_at_8[0x4];
e281682b 2206 u8 prio[0x4];
b4ff3a36 2207 u8 reserved_at_10[0x10];
e281682b 2208
b4ff3a36 2209 u8 reserved_at_20[0x100];
e281682b 2210
b4ff3a36 2211 u8 reserved_at_120[0x8];
e281682b
SM		 2212 u8 transport_domain[0x18];
2213
b4ff3a36 2214 u8 reserved_at_140[0x3c0];
e281682b
SM		 2215};
2216
2217enum {
2218 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2219 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2220};
2221
2222enum {
2223 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2224 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2225};
2226
2227enum {
2be6967c
SM		 2228 MLX5_RX_HASH_FN_NONE = 0x0,
2229 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
2230 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
e281682b
SM		 2231};
2232
2233enum {
2234 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1,
2235 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2,
2236};
2237
2238struct mlx5_ifc_tirc_bits {
b4ff3a36 2239 u8 reserved_at_0[0x20];
e281682b
SM		 2240
2241 u8 disp_type[0x4];
b4ff3a36 2242 u8 reserved_at_24[0x1c];
e281682b 2243
b4ff3a36 2244 u8 reserved_at_40[0x40];
e281682b 2245
b4ff3a36 2246 u8 reserved_at_80[0x4];
e281682b
SM		 2247 u8 lro_timeout_period_usecs[0x10];
2248 u8 lro_enable_mask[0x4];
2249 u8 lro_max_ip_payload_size[0x8];
2250
b4ff3a36 2251 u8 reserved_at_a0[0x40];
e281682b 2252
b4ff3a36 2253 u8 reserved_at_e0[0x8];
e281682b
SM		 2254 u8 inline_rqn[0x18];
2255
2256 u8 rx_hash_symmetric[0x1];
b4ff3a36 2257 u8 reserved_at_101[0x1];
e281682b 2258 u8 tunneled_offload_en[0x1];
b4ff3a36 2259 u8 reserved_at_103[0x5];
e281682b
SM		 2260 u8 indirect_table[0x18];
2261
2262 u8 rx_hash_fn[0x4];
b4ff3a36 2263 u8 reserved_at_124[0x2];
e281682b
SM		 2264 u8 self_lb_block[0x2];
2265 u8 transport_domain[0x18];
2266
2267 u8 rx_hash_toeplitz_key[10][0x20];
2268
2269 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2270
2271 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2272
b4ff3a36 2273 u8 reserved_at_2c0[0x4c0];
e281682b
SM		 2274};
2275
2276enum {
2277 MLX5_SRQC_STATE_GOOD = 0x0,
2278 MLX5_SRQC_STATE_ERROR = 0x1,
2279};
2280
2281struct mlx5_ifc_srqc_bits {
2282 u8 state[0x4];
2283 u8 log_srq_size[0x4];
b4ff3a36 2284 u8 reserved_at_8[0x18];
e281682b
SM		 2285
2286 u8 wq_signature[0x1];
2287 u8 cont_srq[0x1];
b4ff3a36 2288 u8 reserved_at_22[0x1];
e281682b 2289 u8 rlky[0x1];
b4ff3a36 2290 u8 reserved_at_24[0x1];
e281682b
SM		 2291 u8 log_rq_stride[0x3];
2292 u8 xrcd[0x18];
2293
2294 u8 page_offset[0x6];
b4ff3a36 2295 u8 reserved_at_46[0x2];
e281682b
SM		 2296 u8 cqn[0x18];
2297
b4ff3a36 2298 u8 reserved_at_60[0x20];
e281682b 2299
b4ff3a36 2300 u8 reserved_at_80[0x2];
e281682b 2301 u8 log_page_size[0x6];
b4ff3a36 2302 u8 reserved_at_88[0x18];
e281682b 2303
b4ff3a36 2304 u8 reserved_at_a0[0x20];
e281682b 2305
b4ff3a36 2306 u8 reserved_at_c0[0x8];
e281682b
SM		 2307 u8 pd[0x18];
2308
2309 u8 lwm[0x10];
2310 u8 wqe_cnt[0x10];
2311
b4ff3a36 2312 u8 reserved_at_100[0x40];
e281682b 2313
01949d01 2314 u8 dbr_addr[0x40];
e281682b 2315
b4ff3a36 2316 u8 reserved_at_180[0x80];
e281682b
SM		 2317};
2318
2319enum {
2320 MLX5_SQC_STATE_RST = 0x0,
2321 MLX5_SQC_STATE_RDY = 0x1,
2322 MLX5_SQC_STATE_ERR = 0x3,
2323};
2324
2325struct mlx5_ifc_sqc_bits {
2326 u8 rlky[0x1];
2327 u8 cd_master[0x1];
2328 u8 fre[0x1];
2329 u8 flush_in_error_en[0x1];
cff92d7c
HHZ		 2330 u8 reserved_at_4[0x1];
2331 u8 min_wqe_inline_mode[0x3];
e281682b 2332 u8 state[0x4];
7d5e1423
SM		 2333 u8 reg_umr[0x1];
2334 u8 reserved_at_d[0x13];
e281682b 2335
b4ff3a36 2336 u8 reserved_at_20[0x8];
e281682b
SM		 2337 u8 user_index[0x18];
2338
b4ff3a36 2339 u8 reserved_at_40[0x8];
e281682b
SM		 2340 u8 cqn[0x18];
2341
7486216b 2342 u8 reserved_at_60[0x90];
e281682b 2343
7486216b 2344 u8 packet_pacing_rate_limit_index[0x10];
e281682b 2345 u8 tis_lst_sz[0x10];
b4ff3a36 2346 u8 reserved_at_110[0x10];
e281682b 2347
b4ff3a36 2348 u8 reserved_at_120[0x40];
e281682b 2349
b4ff3a36 2350 u8 reserved_at_160[0x8];
e281682b
SM		 2351 u8 tis_num_0[0x18];
2352
2353 struct mlx5_ifc_wq_bits wq;
2354};
2355
813f8540
MHY		 2356enum {
2357 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2358 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2359 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2360 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2361};
2362
2363struct mlx5_ifc_scheduling_context_bits {
2364 u8 element_type[0x8];
2365 u8 reserved_at_8[0x18];
2366
2367 u8 element_attributes[0x20];
2368
2369 u8 parent_element_id[0x20];
2370
2371 u8 reserved_at_60[0x40];
2372
2373 u8 bw_share[0x20];
2374
2375 u8 max_average_bw[0x20];
2376
2377 u8 reserved_at_e0[0x120];
2378};
2379
e281682b 2380struct mlx5_ifc_rqtc_bits {
b4ff3a36 2381 u8 reserved_at_0[0xa0];
e281682b 2382
b4ff3a36 2383 u8 reserved_at_a0[0x10];
e281682b
SM		 2384 u8 rqt_max_size[0x10];
2385
b4ff3a36 2386 u8 reserved_at_c0[0x10];
e281682b
SM		 2387 u8 rqt_actual_size[0x10];
2388
b4ff3a36 2389 u8 reserved_at_e0[0x6a0];
e281682b
SM		 2390
2391 struct mlx5_ifc_rq_num_bits rq_num[0];
2392};
2393
2394enum {
2395 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2396 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2397};
2398
2399enum {
2400 MLX5_RQC_STATE_RST = 0x0,
2401 MLX5_RQC_STATE_RDY = 0x1,
2402 MLX5_RQC_STATE_ERR = 0x3,
2403};
2404
2405struct mlx5_ifc_rqc_bits {
2406 u8 rlky[0x1];
7d5e1423
SM		 2407 u8 reserved_at_1[0x1];
2408 u8 scatter_fcs[0x1];
e281682b
SM		 2409 u8 vsd[0x1];
2410 u8 mem_rq_type[0x4];
2411 u8 state[0x4];
b4ff3a36 2412 u8 reserved_at_c[0x1];
e281682b 2413 u8 flush_in_error_en[0x1];
b4ff3a36 2414 u8 reserved_at_e[0x12];
e281682b 2415
b4ff3a36 2416 u8 reserved_at_20[0x8];
e281682b
SM		 2417 u8 user_index[0x18];
2418
b4ff3a36 2419 u8 reserved_at_40[0x8];
e281682b
SM		 2420 u8 cqn[0x18];
2421
2422 u8 counter_set_id[0x8];
b4ff3a36 2423 u8 reserved_at_68[0x18];
e281682b 2424
b4ff3a36 2425 u8 reserved_at_80[0x8];
e281682b
SM		 2426 u8 rmpn[0x18];
2427
b4ff3a36 2428 u8 reserved_at_a0[0xe0];
e281682b
SM		 2429
2430 struct mlx5_ifc_wq_bits wq;
2431};
2432
2433enum {
2434 MLX5_RMPC_STATE_RDY = 0x1,
2435 MLX5_RMPC_STATE_ERR = 0x3,
2436};
2437
2438struct mlx5_ifc_rmpc_bits {
b4ff3a36 2439 u8 reserved_at_0[0x8];
e281682b 2440 u8 state[0x4];
b4ff3a36 2441 u8 reserved_at_c[0x14];
e281682b
SM		 2442
2443 u8 basic_cyclic_rcv_wqe[0x1];
b4ff3a36 2444 u8 reserved_at_21[0x1f];
e281682b 2445
b4ff3a36 2446 u8 reserved_at_40[0x140];
e281682b
SM		 2447
2448 struct mlx5_ifc_wq_bits wq;
2449};
2450
e281682b 2451struct mlx5_ifc_nic_vport_context_bits {
cff92d7c
HHZ		 2452 u8 reserved_at_0[0x5];
2453 u8 min_wqe_inline_mode[0x3];
2454 u8 reserved_at_8[0x17];
e281682b
SM		 2455 u8 roce_en[0x1];
2456
d82b7318 2457 u8 arm_change_event[0x1];
b4ff3a36 2458 u8 reserved_at_21[0x1a];
d82b7318
SM		 2459 u8 event_on_mtu[0x1];
2460 u8 event_on_promisc_change[0x1];
2461 u8 event_on_vlan_change[0x1];
2462 u8 event_on_mc_address_change[0x1];
2463 u8 event_on_uc_address_change[0x1];
e281682b 2464
b4ff3a36 2465 u8 reserved_at_40[0xf0];
d82b7318
SM		 2466
2467 u8 mtu[0x10];
2468
9efa7525
AS		 2469 u8 system_image_guid[0x40];
2470 u8 port_guid[0x40];
2471 u8 node_guid[0x40];
2472
b4ff3a36 2473 u8 reserved_at_200[0x140];
9efa7525 2474 u8 qkey_violation_counter[0x10];
b4ff3a36 2475 u8 reserved_at_350[0x430];
d82b7318
SM		 2476
2477 u8 promisc_uc[0x1];
2478 u8 promisc_mc[0x1];
2479 u8 promisc_all[0x1];
b4ff3a36 2480 u8 reserved_at_783[0x2];
e281682b 2481 u8 allowed_list_type[0x3];
b4ff3a36 2482 u8 reserved_at_788[0xc];
e281682b
SM		 2483 u8 allowed_list_size[0xc];
2484
2485 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2486
b4ff3a36 2487 u8 reserved_at_7e0[0x20];
e281682b
SM		 2488
2489 u8 current_uc_mac_address[0][0x40];
2490};
2491
2492enum {
2493 MLX5_MKC_ACCESS_MODE_PA = 0x0,
2494 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
2495 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
2496};
2497
2498struct mlx5_ifc_mkc_bits {
b4ff3a36 2499 u8 reserved_at_0[0x1];
e281682b 2500 u8 free[0x1];
b4ff3a36 2501 u8 reserved_at_2[0xd];
e281682b
SM		 2502 u8 small_fence_on_rdma_read_response[0x1];
2503 u8 umr_en[0x1];
2504 u8 a[0x1];
2505 u8 rw[0x1];
2506 u8 rr[0x1];
2507 u8 lw[0x1];
2508 u8 lr[0x1];
2509 u8 access_mode[0x2];
b4ff3a36 2510 u8 reserved_at_18[0x8];
e281682b
SM		 2511
2512 u8 qpn[0x18];
2513 u8 mkey_7_0[0x8];
2514
b4ff3a36 2515 u8 reserved_at_40[0x20];
e281682b
SM		 2516
2517 u8 length64[0x1];
2518 u8 bsf_en[0x1];
2519 u8 sync_umr[0x1];
b4ff3a36 2520 u8 reserved_at_63[0x2];
e281682b 2521 u8 expected_sigerr_count[0x1];
b4ff3a36 2522 u8 reserved_at_66[0x1];
e281682b
SM		 2523 u8 en_rinval[0x1];
2524 u8 pd[0x18];
2525
2526 u8 start_addr[0x40];
2527
2528 u8 len[0x40];
2529
2530 u8 bsf_octword_size[0x20];
2531
b4ff3a36 2532 u8 reserved_at_120[0x80];
e281682b
SM		 2533
2534 u8 translations_octword_size[0x20];
2535
b4ff3a36 2536 u8 reserved_at_1c0[0x1b];
e281682b
SM		 2537 u8 log_page_size[0x5];
2538
b4ff3a36 2539 u8 reserved_at_1e0[0x20];
e281682b
SM		 2540};
2541
2542struct mlx5_ifc_pkey_bits {
b4ff3a36 2543 u8 reserved_at_0[0x10];
e281682b
SM		 2544 u8 pkey[0x10];
2545};
2546
2547struct mlx5_ifc_array128_auto_bits {
2548 u8 array128_auto[16][0x8];
2549};
2550
2551struct mlx5_ifc_hca_vport_context_bits {
2552 u8 field_select[0x20];
2553
b4ff3a36 2554 u8 reserved_at_20[0xe0];
e281682b
SM		 2555
2556 u8 sm_virt_aware[0x1];
2557 u8 has_smi[0x1];
2558 u8 has_raw[0x1];
2559 u8 grh_required[0x1];
b4ff3a36 2560 u8 reserved_at_104[0xc];
707c4602
MD		 2561 u8 port_physical_state[0x4];
2562 u8 vport_state_policy[0x4];
2563 u8 port_state[0x4];
e281682b
SM		 2564 u8 vport_state[0x4];
2565
b4ff3a36 2566 u8 reserved_at_120[0x20];
707c4602
MD		 2567
2568 u8 system_image_guid[0x40];
e281682b
SM		 2569
2570 u8 port_guid[0x40];
2571
2572 u8 node_guid[0x40];
2573
2574 u8 cap_mask1[0x20];
2575
2576 u8 cap_mask1_field_select[0x20];
2577
2578 u8 cap_mask2[0x20];
2579
2580 u8 cap_mask2_field_select[0x20];
2581
b4ff3a36 2582 u8 reserved_at_280[0x80];
e281682b
SM		 2583
2584 u8 lid[0x10];
b4ff3a36 2585 u8 reserved_at_310[0x4];
e281682b
SM		 2586 u8 init_type_reply[0x4];
2587 u8 lmc[0x3];
2588 u8 subnet_timeout[0x5];
2589
2590 u8 sm_lid[0x10];
2591 u8 sm_sl[0x4];
b4ff3a36 2592 u8 reserved_at_334[0xc];
e281682b
SM		 2593
2594 u8 qkey_violation_counter[0x10];
2595 u8 pkey_violation_counter[0x10];
2596
b4ff3a36 2597 u8 reserved_at_360[0xca0];
e281682b
SM		 2598};
2599
d6666753 2600struct mlx5_ifc_esw_vport_context_bits {
b4ff3a36 2601 u8 reserved_at_0[0x3];
d6666753
SM		 2602 u8 vport_svlan_strip[0x1];
2603 u8 vport_cvlan_strip[0x1];
2604 u8 vport_svlan_insert[0x1];
2605 u8 vport_cvlan_insert[0x2];
b4ff3a36 2606 u8 reserved_at_8[0x18];
d6666753 2607
b4ff3a36 2608 u8 reserved_at_20[0x20];
d6666753
SM		 2609
2610 u8 svlan_cfi[0x1];
2611 u8 svlan_pcp[0x3];
2612 u8 svlan_id[0xc];
2613 u8 cvlan_cfi[0x1];
2614 u8 cvlan_pcp[0x3];
2615 u8 cvlan_id[0xc];
2616
b4ff3a36 2617 u8 reserved_at_60[0x7a0];
d6666753
SM		 2618};
2619
e281682b
SM		 2620enum {
2621 MLX5_EQC_STATUS_OK = 0x0,
2622 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
2623};
2624
2625enum {
2626 MLX5_EQC_ST_ARMED = 0x9,
2627 MLX5_EQC_ST_FIRED = 0xa,
2628};
2629
2630struct mlx5_ifc_eqc_bits {
2631 u8 status[0x4];
b4ff3a36 2632 u8 reserved_at_4[0x9];
e281682b
SM		 2633 u8 ec[0x1];
2634 u8 oi[0x1];
b4ff3a36 2635 u8 reserved_at_f[0x5];
e281682b 2636 u8 st[0x4];
b4ff3a36 2637 u8 reserved_at_18[0x8];
e281682b 2638
b4ff3a36 2639 u8 reserved_at_20[0x20];
e281682b 2640
b4ff3a36 2641 u8 reserved_at_40[0x14];
e281682b 2642 u8 page_offset[0x6];
b4ff3a36 2643 u8 reserved_at_5a[0x6];
e281682b 2644
b4ff3a36 2645 u8 reserved_at_60[0x3];
e281682b
SM		 2646 u8 log_eq_size[0x5];
2647 u8 uar_page[0x18];
2648
b4ff3a36 2649 u8 reserved_at_80[0x20];
e281682b 2650
b4ff3a36 2651 u8 reserved_at_a0[0x18];
e281682b
SM		 2652 u8 intr[0x8];
2653
b4ff3a36 2654 u8 reserved_at_c0[0x3];
e281682b 2655 u8 log_page_size[0x5];
b4ff3a36 2656 u8 reserved_at_c8[0x18];
e281682b 2657
b4ff3a36 2658 u8 reserved_at_e0[0x60];
e281682b 2659
b4ff3a36 2660 u8 reserved_at_140[0x8];
e281682b
SM		 2661 u8 consumer_counter[0x18];
2662
b4ff3a36 2663 u8 reserved_at_160[0x8];
e281682b
SM		 2664 u8 producer_counter[0x18];
2665
b4ff3a36 2666 u8 reserved_at_180[0x80];
e281682b
SM		 2667};
2668
2669enum {
2670 MLX5_DCTC_STATE_ACTIVE = 0x0,
2671 MLX5_DCTC_STATE_DRAINING = 0x1,
2672 MLX5_DCTC_STATE_DRAINED = 0x2,
2673};
2674
2675enum {
2676 MLX5_DCTC_CS_RES_DISABLE = 0x0,
2677 MLX5_DCTC_CS_RES_NA = 0x1,
2678 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
2679};
2680
2681enum {
2682 MLX5_DCTC_MTU_256_BYTES = 0x1,
2683 MLX5_DCTC_MTU_512_BYTES = 0x2,
2684 MLX5_DCTC_MTU_1K_BYTES = 0x3,
2685 MLX5_DCTC_MTU_2K_BYTES = 0x4,
2686 MLX5_DCTC_MTU_4K_BYTES = 0x5,
2687};
2688
2689struct mlx5_ifc_dctc_bits {
b4ff3a36 2690 u8 reserved_at_0[0x4];
e281682b 2691 u8 state[0x4];
b4ff3a36 2692 u8 reserved_at_8[0x18];
e281682b 2693
b4ff3a36 2694 u8 reserved_at_20[0x8];
e281682b
SM		 2695 u8 user_index[0x18];
2696
b4ff3a36 2697 u8 reserved_at_40[0x8];
e281682b
SM		 2698 u8 cqn[0x18];
2699
2700 u8 counter_set_id[0x8];
2701 u8 atomic_mode[0x4];
2702 u8 rre[0x1];
2703 u8 rwe[0x1];
2704 u8 rae[0x1];
2705 u8 atomic_like_write_en[0x1];
2706 u8 latency_sensitive[0x1];
2707 u8 rlky[0x1];
2708 u8 free_ar[0x1];
b4ff3a36 2709 u8 reserved_at_73[0xd];
e281682b 2710
b4ff3a36 2711 u8 reserved_at_80[0x8];
e281682b 2712 u8 cs_res[0x8];
b4ff3a36 2713 u8 reserved_at_90[0x3];
e281682b 2714 u8 min_rnr_nak[0x5];
b4ff3a36 2715 u8 reserved_at_98[0x8];
e281682b 2716
b4ff3a36 2717 u8 reserved_at_a0[0x8];
7486216b 2718 u8 srqn_xrqn[0x18];
e281682b 2719
b4ff3a36 2720 u8 reserved_at_c0[0x8];
e281682b
SM		 2721 u8 pd[0x18];
2722
2723 u8 tclass[0x8];
b4ff3a36 2724 u8 reserved_at_e8[0x4];
e281682b
SM		 2725 u8 flow_label[0x14];
2726
2727 u8 dc_access_key[0x40];
2728
b4ff3a36 2729 u8 reserved_at_140[0x5];
e281682b
SM		 2730 u8 mtu[0x3];
2731 u8 port[0x8];
2732 u8 pkey_index[0x10];
2733
b4ff3a36 2734 u8 reserved_at_160[0x8];
e281682b 2735 u8 my_addr_index[0x8];
b4ff3a36 2736 u8 reserved_at_170[0x8];
e281682b
SM		 2737 u8 hop_limit[0x8];
2738
2739 u8 dc_access_key_violation_count[0x20];
2740
b4ff3a36 2741 u8 reserved_at_1a0[0x14];
e281682b
SM		 2742 u8 dei_cfi[0x1];
2743 u8 eth_prio[0x3];
2744 u8 ecn[0x2];
2745 u8 dscp[0x6];
2746
b4ff3a36 2747 u8 reserved_at_1c0[0x40];
e281682b
SM		 2748};
2749
2750enum {
2751 MLX5_CQC_STATUS_OK = 0x0,
2752 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
2753 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
2754};
2755
2756enum {
2757 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
2758 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
2759};
2760
2761enum {
2762 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
2763 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
2764 MLX5_CQC_ST_FIRED = 0xa,
2765};
2766
7d5e1423
SM		 2767enum {
2768 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
2769 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
7486216b 2770 MLX5_CQ_PERIOD_NUM_MODES
7d5e1423
SM		 2771};
2772
e281682b
SM		 2773struct mlx5_ifc_cqc_bits {
2774 u8 status[0x4];
b4ff3a36 2775 u8 reserved_at_4[0x4];
e281682b
SM		 2776 u8 cqe_sz[0x3];
2777 u8 cc[0x1];
b4ff3a36 2778 u8 reserved_at_c[0x1];
e281682b
SM		 2779 u8 scqe_break_moderation_en[0x1];
2780 u8 oi[0x1];
7d5e1423
SM		 2781 u8 cq_period_mode[0x2];
2782 u8 cqe_comp_en[0x1];
e281682b
SM		 2783 u8 mini_cqe_res_format[0x2];
2784 u8 st[0x4];
b4ff3a36 2785 u8 reserved_at_18[0x8];
e281682b 2786
b4ff3a36 2787 u8 reserved_at_20[0x20];
e281682b 2788
b4ff3a36 2789 u8 reserved_at_40[0x14];
e281682b 2790 u8 page_offset[0x6];
b4ff3a36 2791 u8 reserved_at_5a[0x6];
e281682b 2792
b4ff3a36 2793 u8 reserved_at_60[0x3];
e281682b
SM		 2794 u8 log_cq_size[0x5];
2795 u8 uar_page[0x18];
2796
b4ff3a36 2797 u8 reserved_at_80[0x4];
e281682b
SM		 2798 u8 cq_period[0xc];
2799 u8 cq_max_count[0x10];
2800
b4ff3a36 2801 u8 reserved_at_a0[0x18];
e281682b
SM		 2802 u8 c_eqn[0x8];
2803
b4ff3a36 2804 u8 reserved_at_c0[0x3];
e281682b 2805 u8 log_page_size[0x5];
b4ff3a36 2806 u8 reserved_at_c8[0x18];
e281682b 2807
b4ff3a36 2808 u8 reserved_at_e0[0x20];
e281682b 2809
b4ff3a36 2810 u8 reserved_at_100[0x8];
e281682b
SM		 2811 u8 last_notified_index[0x18];
2812
b4ff3a36 2813 u8 reserved_at_120[0x8];
e281682b
SM		 2814 u8 last_solicit_index[0x18];
2815
b4ff3a36 2816 u8 reserved_at_140[0x8];
e281682b
SM		 2817 u8 consumer_counter[0x18];
2818
b4ff3a36 2819 u8 reserved_at_160[0x8];
e281682b
SM		 2820 u8 producer_counter[0x18];
2821
b4ff3a36 2822 u8 reserved_at_180[0x40];
e281682b
SM		 2823
2824 u8 dbr_addr[0x40];
2825};
2826
2827union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2828 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2829 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2830 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
b4ff3a36 2831 u8 reserved_at_0[0x800];
e281682b
SM		 2832};
2833
2834struct mlx5_ifc_query_adapter_param_block_bits {
b4ff3a36 2835 u8 reserved_at_0[0xc0];
e281682b 2836
b4ff3a36 2837 u8 reserved_at_c0[0x8];
211e6c80
MD		 2838 u8 ieee_vendor_id[0x18];
2839
b4ff3a36 2840 u8 reserved_at_e0[0x10];
e281682b
SM		 2841 u8 vsd_vendor_id[0x10];
2842
2843 u8 vsd[208][0x8];
2844
2845 u8 vsd_contd_psid[16][0x8];
2846};
2847
7486216b
SM		 2848enum {
2849 MLX5_XRQC_STATE_GOOD = 0x0,
2850 MLX5_XRQC_STATE_ERROR = 0x1,
2851};
2852
2853enum {
2854 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
2855 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
2856};
2857
2858enum {
2859 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
2860};
2861
2862struct mlx5_ifc_tag_matching_topology_context_bits {
2863 u8 log_matching_list_sz[0x4];
2864 u8 reserved_at_4[0xc];
2865 u8 append_next_index[0x10];
2866
2867 u8 sw_phase_cnt[0x10];
2868 u8 hw_phase_cnt[0x10];
2869
2870 u8 reserved_at_40[0x40];
2871};
2872
2873struct mlx5_ifc_xrqc_bits {
2874 u8 state[0x4];
2875 u8 rlkey[0x1];
2876 u8 reserved_at_5[0xf];
2877 u8 topology[0x4];
2878 u8 reserved_at_18[0x4];
2879 u8 offload[0x4];
2880
2881 u8 reserved_at_20[0x8];
2882 u8 user_index[0x18];
2883
2884 u8 reserved_at_40[0x8];
2885 u8 cqn[0x18];
2886
2887 u8 reserved_at_60[0xa0];
2888
2889 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
2890
5579e151 2891 u8 reserved_at_180[0x880];
7486216b
SM		 2892
2893 struct mlx5_ifc_wq_bits wq;
2894};
2895
e281682b
SM		 2896union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2897 struct mlx5_ifc_modify_field_select_bits modify_field_select;
2898 struct mlx5_ifc_resize_field_select_bits resize_field_select;
b4ff3a36 2899 u8 reserved_at_0[0x20];
e281682b
SM		 2900};
2901
2902union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2903 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2904 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2905 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
b4ff3a36 2906 u8 reserved_at_0[0x20];
e281682b
SM		 2907};
2908
2909union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
2910 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
2911 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
2912 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
2913 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
2914 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
2915 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
2916 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
1c64bf6f 2917 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b 2918 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
b4ff3a36 2919 u8 reserved_at_0[0x7c0];
e281682b
SM		 2920};
2921
2922union mlx5_ifc_event_auto_bits {
2923 struct mlx5_ifc_comp_event_bits comp_event;
2924 struct mlx5_ifc_dct_events_bits dct_events;
2925 struct mlx5_ifc_qp_events_bits qp_events;
2926 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
2927 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
2928 struct mlx5_ifc_cq_error_bits cq_error;
2929 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
2930 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
2931 struct mlx5_ifc_gpio_event_bits gpio_event;
2932 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
2933 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
2934 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
b4ff3a36 2935 u8 reserved_at_0[0xe0];
e281682b
SM		 2936};
2937
2938struct mlx5_ifc_health_buffer_bits {
b4ff3a36 2939 u8 reserved_at_0[0x100];
e281682b
SM		 2940
2941 u8 assert_existptr[0x20];
2942
2943 u8 assert_callra[0x20];
2944
b4ff3a36 2945 u8 reserved_at_140[0x40];
e281682b
SM		 2946
2947 u8 fw_version[0x20];
2948
2949 u8 hw_id[0x20];
2950
b4ff3a36 2951 u8 reserved_at_1c0[0x20];
e281682b
SM		 2952
2953 u8 irisc_index[0x8];
2954 u8 synd[0x8];
2955 u8 ext_synd[0x10];
2956};
2957
2958struct mlx5_ifc_register_loopback_control_bits {
2959 u8 no_lb[0x1];
b4ff3a36 2960 u8 reserved_at_1[0x7];
e281682b 2961 u8 port[0x8];
b4ff3a36 2962 u8 reserved_at_10[0x10];
e281682b 2963
b4ff3a36 2964 u8 reserved_at_20[0x60];
e281682b
SM		 2965};
2966
813f8540
MHY		 2967struct mlx5_ifc_vport_tc_element_bits {
2968 u8 traffic_class[0x4];
2969 u8 reserved_at_4[0xc];
2970 u8 vport_number[0x10];
2971};
2972
2973struct mlx5_ifc_vport_element_bits {
2974 u8 reserved_at_0[0x10];
2975 u8 vport_number[0x10];
2976};
2977
2978enum {
2979 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
2980 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
2981 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
2982};
2983
2984struct mlx5_ifc_tsar_element_bits {
2985 u8 reserved_at_0[0x8];
2986 u8 tsar_type[0x8];
2987 u8 reserved_at_10[0x10];
2988};
2989
e281682b
SM		 2990struct mlx5_ifc_teardown_hca_out_bits {
2991 u8 status[0x8];
b4ff3a36 2992 u8 reserved_at_8[0x18];
e281682b
SM		 2993
2994 u8 syndrome[0x20];
2995
b4ff3a36 2996 u8 reserved_at_40[0x40];
e281682b
SM		 2997};
2998
2999enum {
3000 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
3001 MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE = 0x1,
3002};
3003
3004struct mlx5_ifc_teardown_hca_in_bits {
3005 u8 opcode[0x10];
b4ff3a36 3006 u8 reserved_at_10[0x10];
e281682b 3007
b4ff3a36 3008 u8 reserved_at_20[0x10];
e281682b
SM		 3009 u8 op_mod[0x10];
3010
b4ff3a36 3011 u8 reserved_at_40[0x10];
e281682b
SM		 3012 u8 profile[0x10];
3013
b4ff3a36 3014 u8 reserved_at_60[0x20];
e281682b
SM		 3015};
3016
3017struct mlx5_ifc_sqerr2rts_qp_out_bits {
3018 u8 status[0x8];
b4ff3a36 3019 u8 reserved_at_8[0x18];
e281682b
SM		 3020
3021 u8 syndrome[0x20];
3022
b4ff3a36 3023 u8 reserved_at_40[0x40];
e281682b
SM		 3024};
3025
3026struct mlx5_ifc_sqerr2rts_qp_in_bits {
3027 u8 opcode[0x10];
b4ff3a36 3028 u8 reserved_at_10[0x10];
e281682b 3029
b4ff3a36 3030 u8 reserved_at_20[0x10];
e281682b
SM		 3031 u8 op_mod[0x10];
3032
b4ff3a36 3033 u8 reserved_at_40[0x8];
e281682b
SM		 3034 u8 qpn[0x18];
3035
b4ff3a36 3036 u8 reserved_at_60[0x20];
e281682b
SM		 3037
3038 u8 opt_param_mask[0x20];
3039
b4ff3a36 3040 u8 reserved_at_a0[0x20];
e281682b
SM		 3041
3042 struct mlx5_ifc_qpc_bits qpc;
3043
b4ff3a36 3044 u8 reserved_at_800[0x80];
e281682b
SM		 3045};
3046
3047struct mlx5_ifc_sqd2rts_qp_out_bits {
3048 u8 status[0x8];
b4ff3a36 3049 u8 reserved_at_8[0x18];
e281682b
SM		 3050
3051 u8 syndrome[0x20];
3052
b4ff3a36 3053 u8 reserved_at_40[0x40];
e281682b
SM		 3054};
3055
3056struct mlx5_ifc_sqd2rts_qp_in_bits {
3057 u8 opcode[0x10];
b4ff3a36 3058 u8 reserved_at_10[0x10];
e281682b 3059
b4ff3a36 3060 u8 reserved_at_20[0x10];
e281682b
SM		 3061 u8 op_mod[0x10];
3062
b4ff3a36 3063 u8 reserved_at_40[0x8];
e281682b
SM		 3064 u8 qpn[0x18];
3065
b4ff3a36 3066 u8 reserved_at_60[0x20];
e281682b
SM		 3067
3068 u8 opt_param_mask[0x20];
3069
b4ff3a36 3070 u8 reserved_at_a0[0x20];
e281682b
SM		 3071
3072 struct mlx5_ifc_qpc_bits qpc;
3073
b4ff3a36 3074 u8 reserved_at_800[0x80];
e281682b
SM		 3075};
3076
3077struct mlx5_ifc_set_roce_address_out_bits {
3078 u8 status[0x8];
b4ff3a36 3079 u8 reserved_at_8[0x18];
e281682b
SM		 3080
3081 u8 syndrome[0x20];
3082
b4ff3a36 3083 u8 reserved_at_40[0x40];
e281682b
SM		 3084};
3085
3086struct mlx5_ifc_set_roce_address_in_bits {
3087 u8 opcode[0x10];
b4ff3a36 3088 u8 reserved_at_10[0x10];
e281682b 3089
b4ff3a36 3090 u8 reserved_at_20[0x10];
e281682b
SM		 3091 u8 op_mod[0x10];
3092
3093 u8 roce_address_index[0x10];
b4ff3a36 3094 u8 reserved_at_50[0x10];
e281682b 3095
b4ff3a36 3096 u8 reserved_at_60[0x20];
e281682b
SM		 3097
3098 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3099};
3100
3101struct mlx5_ifc_set_mad_demux_out_bits {
3102 u8 status[0x8];
b4ff3a36 3103 u8 reserved_at_8[0x18];
e281682b
SM		 3104
3105 u8 syndrome[0x20];
3106
b4ff3a36 3107 u8 reserved_at_40[0x40];
e281682b
SM		 3108};
3109
3110enum {
3111 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
3112 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
3113};
3114
3115struct mlx5_ifc_set_mad_demux_in_bits {
3116 u8 opcode[0x10];
b4ff3a36 3117 u8 reserved_at_10[0x10];
e281682b 3118
b4ff3a36 3119 u8 reserved_at_20[0x10];
e281682b
SM		 3120 u8 op_mod[0x10];
3121
b4ff3a36 3122 u8 reserved_at_40[0x20];
e281682b 3123
b4ff3a36 3124 u8 reserved_at_60[0x6];
e281682b 3125 u8 demux_mode[0x2];
b4ff3a36 3126 u8 reserved_at_68[0x18];
e281682b
SM		 3127};
3128
3129struct mlx5_ifc_set_l2_table_entry_out_bits {
3130 u8 status[0x8];
b4ff3a36 3131 u8 reserved_at_8[0x18];
e281682b
SM		 3132
3133 u8 syndrome[0x20];
3134
b4ff3a36 3135 u8 reserved_at_40[0x40];
e281682b
SM		 3136};
3137
3138struct mlx5_ifc_set_l2_table_entry_in_bits {
3139 u8 opcode[0x10];
b4ff3a36 3140 u8 reserved_at_10[0x10];
e281682b 3141
b4ff3a36 3142 u8 reserved_at_20[0x10];
e281682b
SM		 3143 u8 op_mod[0x10];
3144
b4ff3a36 3145 u8 reserved_at_40[0x60];
e281682b 3146
b4ff3a36 3147 u8 reserved_at_a0[0x8];
e281682b
SM		 3148 u8 table_index[0x18];
3149
b4ff3a36 3150 u8 reserved_at_c0[0x20];
e281682b 3151
b4ff3a36 3152 u8 reserved_at_e0[0x13];
e281682b
SM		 3153 u8 vlan_valid[0x1];
3154 u8 vlan[0xc];
3155
3156 struct mlx5_ifc_mac_address_layout_bits mac_address;
3157
b4ff3a36 3158 u8 reserved_at_140[0xc0];
e281682b
SM		 3159};
3160
3161struct mlx5_ifc_set_issi_out_bits {
3162 u8 status[0x8];
b4ff3a36 3163 u8 reserved_at_8[0x18];
e281682b
SM		 3164
3165 u8 syndrome[0x20];
3166
b4ff3a36 3167 u8 reserved_at_40[0x40];
e281682b
SM		 3168};
3169
3170struct mlx5_ifc_set_issi_in_bits {
3171 u8 opcode[0x10];
b4ff3a36 3172 u8 reserved_at_10[0x10];
e281682b 3173
b4ff3a36 3174 u8 reserved_at_20[0x10];
e281682b
SM		 3175 u8 op_mod[0x10];
3176
b4ff3a36 3177 u8 reserved_at_40[0x10];
e281682b
SM		 3178 u8 current_issi[0x10];
3179
b4ff3a36 3180 u8 reserved_at_60[0x20];
e281682b
SM		 3181};
3182
3183struct mlx5_ifc_set_hca_cap_out_bits {
3184 u8 status[0x8];
b4ff3a36 3185 u8 reserved_at_8[0x18];
e281682b
SM		 3186
3187 u8 syndrome[0x20];
3188
b4ff3a36 3189 u8 reserved_at_40[0x40];
e281682b
SM		 3190};
3191
3192struct mlx5_ifc_set_hca_cap_in_bits {
3193 u8 opcode[0x10];
b4ff3a36 3194 u8 reserved_at_10[0x10];
e281682b 3195
b4ff3a36 3196 u8 reserved_at_20[0x10];
e281682b
SM		 3197 u8 op_mod[0x10];
3198
b4ff3a36 3199 u8 reserved_at_40[0x40];
e281682b
SM		 3200
3201 union mlx5_ifc_hca_cap_union_bits capability;
3202};
3203
26a81453
MG		 3204enum {
3205 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
3206 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
3207 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
3208 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
3209};
3210
e281682b
SM		 3211struct mlx5_ifc_set_fte_out_bits {
3212 u8 status[0x8];
b4ff3a36 3213 u8 reserved_at_8[0x18];
e281682b
SM		 3214
3215 u8 syndrome[0x20];
3216
b4ff3a36 3217 u8 reserved_at_40[0x40];
e281682b
SM		 3218};
3219
3220struct mlx5_ifc_set_fte_in_bits {
3221 u8 opcode[0x10];
b4ff3a36 3222 u8 reserved_at_10[0x10];
e281682b 3223
b4ff3a36 3224 u8 reserved_at_20[0x10];
e281682b
SM		 3225 u8 op_mod[0x10];
3226
7d5e1423
SM		 3227 u8 other_vport[0x1];
3228 u8 reserved_at_41[0xf];
3229 u8 vport_number[0x10];
3230
3231 u8 reserved_at_60[0x20];
e281682b
SM		 3232
3233 u8 table_type[0x8];
b4ff3a36 3234 u8 reserved_at_88[0x18];
e281682b 3235
b4ff3a36 3236 u8 reserved_at_a0[0x8];
e281682b
SM		 3237 u8 table_id[0x18];
3238
b4ff3a36 3239 u8 reserved_at_c0[0x18];
26a81453
MG		 3240 u8 modify_enable_mask[0x8];
3241
b4ff3a36 3242 u8 reserved_at_e0[0x20];
e281682b
SM		 3243
3244 u8 flow_index[0x20];
3245
b4ff3a36 3246 u8 reserved_at_120[0xe0];
e281682b
SM		 3247
3248 struct mlx5_ifc_flow_context_bits flow_context;
3249};
3250
3251struct mlx5_ifc_rts2rts_qp_out_bits {
3252 u8 status[0x8];
b4ff3a36 3253 u8 reserved_at_8[0x18];
e281682b
SM		 3254
3255 u8 syndrome[0x20];
3256
b4ff3a36 3257 u8 reserved_at_40[0x40];
e281682b
SM		 3258};
3259
3260struct mlx5_ifc_rts2rts_qp_in_bits {
3261 u8 opcode[0x10];
b4ff3a36 3262 u8 reserved_at_10[0x10];
e281682b 3263
b4ff3a36 3264 u8 reserved_at_20[0x10];
e281682b
SM		 3265 u8 op_mod[0x10];
3266
b4ff3a36 3267 u8 reserved_at_40[0x8];
e281682b
SM		 3268 u8 qpn[0x18];
3269
b4ff3a36 3270 u8 reserved_at_60[0x20];
e281682b
SM		 3271
3272 u8 opt_param_mask[0x20];
3273
b4ff3a36 3274 u8 reserved_at_a0[0x20];
e281682b
SM		 3275
3276 struct mlx5_ifc_qpc_bits qpc;
3277
b4ff3a36 3278 u8 reserved_at_800[0x80];
e281682b
SM		 3279};
3280
3281struct mlx5_ifc_rtr2rts_qp_out_bits {
3282 u8 status[0x8];
b4ff3a36 3283 u8 reserved_at_8[0x18];
e281682b
SM		 3284
3285 u8 syndrome[0x20];
3286
b4ff3a36 3287 u8 reserved_at_40[0x40];
e281682b
SM		 3288};
3289
3290struct mlx5_ifc_rtr2rts_qp_in_bits {
3291 u8 opcode[0x10];
b4ff3a36 3292 u8 reserved_at_10[0x10];
e281682b 3293
b4ff3a36 3294 u8 reserved_at_20[0x10];
e281682b
SM		 3295 u8 op_mod[0x10];
3296
b4ff3a36 3297 u8 reserved_at_40[0x8];
e281682b
SM		 3298 u8 qpn[0x18];
3299
b4ff3a36 3300 u8 reserved_at_60[0x20];
e281682b
SM		 3301
3302 u8 opt_param_mask[0x20];
3303
b4ff3a36 3304 u8 reserved_at_a0[0x20];
e281682b
SM		 3305
3306 struct mlx5_ifc_qpc_bits qpc;
3307
b4ff3a36 3308 u8 reserved_at_800[0x80];
e281682b
SM		 3309};
3310
3311struct mlx5_ifc_rst2init_qp_out_bits {
3312 u8 status[0x8];
b4ff3a36 3313 u8 reserved_at_8[0x18];
e281682b
SM		 3314
3315 u8 syndrome[0x20];
3316
b4ff3a36 3317 u8 reserved_at_40[0x40];
e281682b
SM		 3318};
3319
3320struct mlx5_ifc_rst2init_qp_in_bits {
3321 u8 opcode[0x10];
b4ff3a36 3322 u8 reserved_at_10[0x10];
e281682b 3323
b4ff3a36 3324 u8 reserved_at_20[0x10];
e281682b
SM		 3325 u8 op_mod[0x10];
3326
b4ff3a36 3327 u8 reserved_at_40[0x8];
e281682b
SM		 3328 u8 qpn[0x18];
3329
b4ff3a36 3330 u8 reserved_at_60[0x20];
e281682b
SM		 3331
3332 u8 opt_param_mask[0x20];
3333
b4ff3a36 3334 u8 reserved_at_a0[0x20];
e281682b
SM		 3335
3336 struct mlx5_ifc_qpc_bits qpc;
3337
b4ff3a36 3338 u8 reserved_at_800[0x80];
e281682b
SM		 3339};
3340
7486216b
SM		 3341struct mlx5_ifc_query_xrq_out_bits {
3342 u8 status[0x8];
3343 u8 reserved_at_8[0x18];
3344
3345 u8 syndrome[0x20];
3346
3347 u8 reserved_at_40[0x40];
3348
3349 struct mlx5_ifc_xrqc_bits xrq_context;
3350};
3351
3352struct mlx5_ifc_query_xrq_in_bits {
3353 u8 opcode[0x10];
3354 u8 reserved_at_10[0x10];
3355
3356 u8 reserved_at_20[0x10];
3357 u8 op_mod[0x10];
3358
3359 u8 reserved_at_40[0x8];
3360 u8 xrqn[0x18];
3361
3362 u8 reserved_at_60[0x20];
3363};
3364
e281682b
SM		 3365struct mlx5_ifc_query_xrc_srq_out_bits {
3366 u8 status[0x8];
b4ff3a36 3367 u8 reserved_at_8[0x18];
e281682b
SM		 3368
3369 u8 syndrome[0x20];
3370
b4ff3a36 3371 u8 reserved_at_40[0x40];
e281682b
SM		 3372
3373 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3374
b4ff3a36 3375 u8 reserved_at_280[0x600];
e281682b
SM		 3376
3377 u8 pas[0][0x40];
3378};
3379
3380struct mlx5_ifc_query_xrc_srq_in_bits {
3381 u8 opcode[0x10];
b4ff3a36 3382 u8 reserved_at_10[0x10];
e281682b 3383
b4ff3a36 3384 u8 reserved_at_20[0x10];
e281682b
SM		 3385 u8 op_mod[0x10];
3386
b4ff3a36 3387 u8 reserved_at_40[0x8];
e281682b
SM		 3388 u8 xrc_srqn[0x18];
3389
b4ff3a36 3390 u8 reserved_at_60[0x20];
e281682b
SM		 3391};
3392
3393enum {
3394 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
3395 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
3396};
3397
3398struct mlx5_ifc_query_vport_state_out_bits {
3399 u8 status[0x8];
b4ff3a36 3400 u8 reserved_at_8[0x18];
e281682b
SM		 3401
3402 u8 syndrome[0x20];
3403
b4ff3a36 3404 u8 reserved_at_40[0x20];
e281682b 3405
b4ff3a36 3406 u8 reserved_at_60[0x18];
e281682b
SM		 3407 u8 admin_state[0x4];
3408 u8 state[0x4];
3409};
3410
3411enum {
3412 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0,
e7546514 3413 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1,
e281682b
SM		 3414};
3415
3416struct mlx5_ifc_query_vport_state_in_bits {
3417 u8 opcode[0x10];
b4ff3a36 3418 u8 reserved_at_10[0x10];
e281682b 3419
b4ff3a36 3420 u8 reserved_at_20[0x10];
e281682b
SM		 3421 u8 op_mod[0x10];
3422
3423 u8 other_vport[0x1];
b4ff3a36 3424 u8 reserved_at_41[0xf];
e281682b
SM		 3425 u8 vport_number[0x10];
3426
b4ff3a36 3427 u8 reserved_at_60[0x20];
e281682b
SM		 3428};
3429
3430struct mlx5_ifc_query_vport_counter_out_bits {
3431 u8 status[0x8];
b4ff3a36 3432 u8 reserved_at_8[0x18];
e281682b
SM		 3433
3434 u8 syndrome[0x20];
3435
b4ff3a36 3436 u8 reserved_at_40[0x40];
e281682b
SM		 3437
3438 struct mlx5_ifc_traffic_counter_bits received_errors;
3439
3440 struct mlx5_ifc_traffic_counter_bits transmit_errors;
3441
3442 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3443
3444 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3445
3446 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3447
3448 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3449
3450 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3451
3452 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3453
3454 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3455
3456 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3457
3458 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3459
3460 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3461
b4ff3a36 3462 u8 reserved_at_680[0xa00];
e281682b
SM		 3463};
3464
3465enum {
3466 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
3467};
3468
3469struct mlx5_ifc_query_vport_counter_in_bits {
3470 u8 opcode[0x10];
b4ff3a36 3471 u8 reserved_at_10[0x10];
e281682b 3472
b4ff3a36 3473 u8 reserved_at_20[0x10];
e281682b
SM		 3474 u8 op_mod[0x10];
3475
3476 u8 other_vport[0x1];
b54ba277
MY		 3477 u8 reserved_at_41[0xb];
3478 u8 port_num[0x4];
e281682b
SM		 3479 u8 vport_number[0x10];
3480
b4ff3a36 3481 u8 reserved_at_60[0x60];
e281682b
SM		 3482
3483 u8 clear[0x1];
b4ff3a36 3484 u8 reserved_at_c1[0x1f];
e281682b 3485
b4ff3a36 3486 u8 reserved_at_e0[0x20];
e281682b
SM		 3487};
3488
3489struct mlx5_ifc_query_tis_out_bits {
3490 u8 status[0x8];
b4ff3a36 3491 u8 reserved_at_8[0x18];
e281682b
SM		 3492
3493 u8 syndrome[0x20];
3494
b4ff3a36 3495 u8 reserved_at_40[0x40];
e281682b
SM		 3496
3497 struct mlx5_ifc_tisc_bits tis_context;
3498};
3499
3500struct mlx5_ifc_query_tis_in_bits {
3501 u8 opcode[0x10];
b4ff3a36 3502 u8 reserved_at_10[0x10];
e281682b 3503
b4ff3a36 3504 u8 reserved_at_20[0x10];
e281682b
SM		 3505 u8 op_mod[0x10];
3506
b4ff3a36 3507 u8 reserved_at_40[0x8];
e281682b
SM		 3508 u8 tisn[0x18];
3509
b4ff3a36 3510 u8 reserved_at_60[0x20];
e281682b
SM		 3511};
3512
3513struct mlx5_ifc_query_tir_out_bits {
3514 u8 status[0x8];
b4ff3a36 3515 u8 reserved_at_8[0x18];
e281682b
SM		 3516
3517 u8 syndrome[0x20];
3518
b4ff3a36 3519 u8 reserved_at_40[0xc0];
e281682b
SM		 3520
3521 struct mlx5_ifc_tirc_bits tir_context;
3522};
3523
3524struct mlx5_ifc_query_tir_in_bits {
3525 u8 opcode[0x10];
b4ff3a36 3526 u8 reserved_at_10[0x10];
e281682b 3527
b4ff3a36 3528 u8 reserved_at_20[0x10];
e281682b
SM		 3529 u8 op_mod[0x10];
3530
b4ff3a36 3531 u8 reserved_at_40[0x8];
e281682b
SM		 3532 u8 tirn[0x18];
3533
b4ff3a36 3534 u8 reserved_at_60[0x20];
e281682b
SM		 3535};
3536
3537struct mlx5_ifc_query_srq_out_bits {
3538 u8 status[0x8];
b4ff3a36 3539 u8 reserved_at_8[0x18];
e281682b
SM		 3540
3541 u8 syndrome[0x20];
3542
b4ff3a36 3543 u8 reserved_at_40[0x40];
e281682b
SM		 3544
3545 struct mlx5_ifc_srqc_bits srq_context_entry;
3546
b4ff3a36 3547 u8 reserved_at_280[0x600];
e281682b
SM		 3548
3549 u8 pas[0][0x40];
3550};
3551
3552struct mlx5_ifc_query_srq_in_bits {
3553 u8 opcode[0x10];
b4ff3a36 3554 u8 reserved_at_10[0x10];
e281682b 3555
b4ff3a36 3556 u8 reserved_at_20[0x10];
e281682b
SM		 3557 u8 op_mod[0x10];
3558
b4ff3a36 3559 u8 reserved_at_40[0x8];
e281682b
SM		 3560 u8 srqn[0x18];
3561
b4ff3a36 3562 u8 reserved_at_60[0x20];
e281682b
SM		 3563};
3564
3565struct mlx5_ifc_query_sq_out_bits {
3566 u8 status[0x8];
b4ff3a36 3567 u8 reserved_at_8[0x18];
e281682b
SM		 3568
3569 u8 syndrome[0x20];
3570
b4ff3a36 3571 u8 reserved_at_40[0xc0];
e281682b
SM		 3572
3573 struct mlx5_ifc_sqc_bits sq_context;
3574};
3575
3576struct mlx5_ifc_query_sq_in_bits {
3577 u8 opcode[0x10];
b4ff3a36 3578 u8 reserved_at_10[0x10];
e281682b 3579
b4ff3a36 3580 u8 reserved_at_20[0x10];
e281682b
SM		 3581 u8 op_mod[0x10];
3582
b4ff3a36 3583 u8 reserved_at_40[0x8];
e281682b
SM		 3584 u8 sqn[0x18];
3585
b4ff3a36 3586 u8 reserved_at_60[0x20];
e281682b
SM		 3587};
3588
3589struct mlx5_ifc_query_special_contexts_out_bits {
3590 u8 status[0x8];
b4ff3a36 3591 u8 reserved_at_8[0x18];
e281682b
SM		 3592
3593 u8 syndrome[0x20];
3594
ec22eb53 3595 u8 dump_fill_mkey[0x20];
e281682b
SM		 3596
3597 u8 resd_lkey[0x20];
3598};
3599
3600struct mlx5_ifc_query_special_contexts_in_bits {
3601 u8 opcode[0x10];
b4ff3a36 3602 u8 reserved_at_10[0x10];
e281682b 3603
b4ff3a36 3604 u8 reserved_at_20[0x10];
e281682b
SM		 3605 u8 op_mod[0x10];
3606
b4ff3a36 3607 u8 reserved_at_40[0x40];
e281682b
SM		 3608};
3609
813f8540
MHY		 3610struct mlx5_ifc_query_scheduling_element_out_bits {
3611 u8 opcode[0x10];
3612 u8 reserved_at_10[0x10];
3613
3614 u8 reserved_at_20[0x10];
3615 u8 op_mod[0x10];
3616
3617 u8 reserved_at_40[0xc0];
3618
3619 struct mlx5_ifc_scheduling_context_bits scheduling_context;
3620
3621 u8 reserved_at_300[0x100];
3622};
3623
3624enum {
3625 SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
3626};
3627
3628struct mlx5_ifc_query_scheduling_element_in_bits {
3629 u8 opcode[0x10];
3630 u8 reserved_at_10[0x10];
3631
3632 u8 reserved_at_20[0x10];
3633 u8 op_mod[0x10];
3634
3635 u8 scheduling_hierarchy[0x8];
3636 u8 reserved_at_48[0x18];
3637
3638 u8 scheduling_element_id[0x20];
3639
3640 u8 reserved_at_80[0x180];
3641};
3642
e281682b
SM		 3643struct mlx5_ifc_query_rqt_out_bits {
3644 u8 status[0x8];
b4ff3a36 3645 u8 reserved_at_8[0x18];
e281682b
SM		 3646
3647 u8 syndrome[0x20];
3648
b4ff3a36 3649 u8 reserved_at_40[0xc0];
e281682b
SM		 3650
3651 struct mlx5_ifc_rqtc_bits rqt_context;
3652};
3653
3654struct mlx5_ifc_query_rqt_in_bits {
3655 u8 opcode[0x10];
b4ff3a36 3656 u8 reserved_at_10[0x10];
e281682b 3657
b4ff3a36 3658 u8 reserved_at_20[0x10];
e281682b
SM		 3659 u8 op_mod[0x10];
3660
b4ff3a36 3661 u8 reserved_at_40[0x8];
e281682b
SM		 3662 u8 rqtn[0x18];
3663
b4ff3a36 3664 u8 reserved_at_60[0x20];
e281682b
SM		 3665};
3666
3667struct mlx5_ifc_query_rq_out_bits {
3668 u8 status[0x8];
b4ff3a36 3669 u8 reserved_at_8[0x18];
e281682b
SM		 3670
3671 u8 syndrome[0x20];
3672
b4ff3a36 3673 u8 reserved_at_40[0xc0];
e281682b
SM		 3674
3675 struct mlx5_ifc_rqc_bits rq_context;
3676};
3677
3678struct mlx5_ifc_query_rq_in_bits {
3679 u8 opcode[0x10];
b4ff3a36 3680 u8 reserved_at_10[0x10];
e281682b 3681
b4ff3a36 3682 u8 reserved_at_20[0x10];
e281682b
SM		 3683 u8 op_mod[0x10];
3684
b4ff3a36 3685 u8 reserved_at_40[0x8];
e281682b
SM		 3686 u8 rqn[0x18];
3687
b4ff3a36 3688 u8 reserved_at_60[0x20];
e281682b
SM		 3689};
3690
3691struct mlx5_ifc_query_roce_address_out_bits {
3692 u8 status[0x8];
b4ff3a36 3693 u8 reserved_at_8[0x18];
e281682b
SM		 3694
3695 u8 syndrome[0x20];
3696
b4ff3a36 3697 u8 reserved_at_40[0x40];
e281682b
SM		 3698
3699 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3700};
3701
3702struct mlx5_ifc_query_roce_address_in_bits {
3703 u8 opcode[0x10];
b4ff3a36 3704 u8 reserved_at_10[0x10];
e281682b 3705
b4ff3a36 3706 u8 reserved_at_20[0x10];
e281682b
SM		 3707 u8 op_mod[0x10];
3708
3709 u8 roce_address_index[0x10];
b4ff3a36 3710 u8 reserved_at_50[0x10];
e281682b 3711
b4ff3a36 3712 u8 reserved_at_60[0x20];
e281682b
SM		 3713};
3714
3715struct mlx5_ifc_query_rmp_out_bits {
3716 u8 status[0x8];
b4ff3a36 3717 u8 reserved_at_8[0x18];
e281682b
SM		 3718
3719 u8 syndrome[0x20];
3720
b4ff3a36 3721 u8 reserved_at_40[0xc0];
e281682b
SM		 3722
3723 struct mlx5_ifc_rmpc_bits rmp_context;
3724};
3725
3726struct mlx5_ifc_query_rmp_in_bits {
3727 u8 opcode[0x10];
b4ff3a36 3728 u8 reserved_at_10[0x10];
e281682b 3729
b4ff3a36 3730 u8 reserved_at_20[0x10];
e281682b
SM		 3731 u8 op_mod[0x10];
3732
b4ff3a36 3733 u8 reserved_at_40[0x8];
e281682b
SM		 3734 u8 rmpn[0x18];
3735
b4ff3a36 3736 u8 reserved_at_60[0x20];
e281682b
SM		 3737};
3738
3739struct mlx5_ifc_query_qp_out_bits {
3740 u8 status[0x8];
b4ff3a36 3741 u8 reserved_at_8[0x18];
e281682b
SM		 3742
3743 u8 syndrome[0x20];
3744
b4ff3a36 3745 u8 reserved_at_40[0x40];
e281682b
SM		 3746
3747 u8 opt_param_mask[0x20];
3748
b4ff3a36 3749 u8 reserved_at_a0[0x20];
e281682b
SM		 3750
3751 struct mlx5_ifc_qpc_bits qpc;
3752
b4ff3a36 3753 u8 reserved_at_800[0x80];
e281682b
SM		 3754
3755 u8 pas[0][0x40];
3756};
3757
3758struct mlx5_ifc_query_qp_in_bits {
3759 u8 opcode[0x10];
b4ff3a36 3760 u8 reserved_at_10[0x10];
e281682b 3761
b4ff3a36 3762 u8 reserved_at_20[0x10];
e281682b
SM		 3763 u8 op_mod[0x10];
3764
b4ff3a36 3765 u8 reserved_at_40[0x8];
e281682b
SM		 3766 u8 qpn[0x18];
3767
b4ff3a36 3768 u8 reserved_at_60[0x20];
e281682b
SM		 3769};
3770
3771struct mlx5_ifc_query_q_counter_out_bits {
3772 u8 status[0x8];
b4ff3a36 3773 u8 reserved_at_8[0x18];
e281682b
SM		 3774
3775 u8 syndrome[0x20];
3776
b4ff3a36 3777 u8 reserved_at_40[0x40];
e281682b
SM		 3778
3779 u8 rx_write_requests[0x20];
3780
b4ff3a36 3781 u8 reserved_at_a0[0x20];
e281682b
SM		 3782
3783 u8 rx_read_requests[0x20];
3784
b4ff3a36 3785 u8 reserved_at_e0[0x20];
e281682b
SM		 3786
3787 u8 rx_atomic_requests[0x20];
3788
b4ff3a36 3789 u8 reserved_at_120[0x20];
e281682b
SM		 3790
3791 u8 rx_dct_connect[0x20];
3792
b4ff3a36 3793 u8 reserved_at_160[0x20];
e281682b
SM		 3794
3795 u8 out_of_buffer[0x20];
3796
b4ff3a36 3797 u8 reserved_at_1a0[0x20];
e281682b
SM		 3798
3799 u8 out_of_sequence[0x20];
3800
7486216b
SM		 3801 u8 reserved_at_1e0[0x20];
3802
3803 u8 duplicate_request[0x20];
3804
3805 u8 reserved_at_220[0x20];
3806
3807 u8 rnr_nak_retry_err[0x20];
3808
3809 u8 reserved_at_260[0x20];
3810
3811 u8 packet_seq_err[0x20];
3812
3813 u8 reserved_at_2a0[0x20];
3814
3815 u8 implied_nak_seq_err[0x20];
3816
3817 u8 reserved_at_2e0[0x20];
3818
3819 u8 local_ack_timeout_err[0x20];
3820
3821 u8 reserved_at_320[0x4e0];
e281682b
SM		 3822};
3823
3824struct mlx5_ifc_query_q_counter_in_bits {
3825 u8 opcode[0x10];
b4ff3a36 3826 u8 reserved_at_10[0x10];
e281682b 3827
b4ff3a36 3828 u8 reserved_at_20[0x10];
e281682b
SM		 3829 u8 op_mod[0x10];
3830
b4ff3a36 3831 u8 reserved_at_40[0x80];
e281682b
SM		 3832
3833 u8 clear[0x1];
b4ff3a36 3834 u8 reserved_at_c1[0x1f];
e281682b 3835
b4ff3a36 3836 u8 reserved_at_e0[0x18];
e281682b
SM		 3837 u8 counter_set_id[0x8];
3838};
3839
3840struct mlx5_ifc_query_pages_out_bits {
3841 u8 status[0x8];
b4ff3a36 3842 u8 reserved_at_8[0x18];
e281682b
SM		 3843
3844 u8 syndrome[0x20];
3845
b4ff3a36 3846 u8 reserved_at_40[0x10];
e281682b
SM		 3847 u8 function_id[0x10];
3848
3849 u8 num_pages[0x20];
3850};
3851
3852enum {
3853 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
3854 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
3855 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
3856};
3857
3858struct mlx5_ifc_query_pages_in_bits {
3859 u8 opcode[0x10];
b4ff3a36 3860 u8 reserved_at_10[0x10];
e281682b 3861
b4ff3a36 3862 u8 reserved_at_20[0x10];
e281682b
SM		 3863 u8 op_mod[0x10];
3864
b4ff3a36 3865 u8 reserved_at_40[0x10];
e281682b
SM		 3866 u8 function_id[0x10];
3867
b4ff3a36 3868 u8 reserved_at_60[0x20];
e281682b
SM		 3869};
3870
3871struct mlx5_ifc_query_nic_vport_context_out_bits {
3872 u8 status[0x8];
b4ff3a36 3873 u8 reserved_at_8[0x18];
e281682b
SM		 3874
3875 u8 syndrome[0x20];
3876
b4ff3a36 3877 u8 reserved_at_40[0x40];
e281682b
SM		 3878
3879 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
3880};
3881
3882struct mlx5_ifc_query_nic_vport_context_in_bits {
3883 u8 opcode[0x10];
b4ff3a36 3884 u8 reserved_at_10[0x10];
e281682b 3885
b4ff3a36 3886 u8 reserved_at_20[0x10];
e281682b
SM		 3887 u8 op_mod[0x10];
3888
3889 u8 other_vport[0x1];
b4ff3a36 3890 u8 reserved_at_41[0xf];
e281682b
SM		 3891 u8 vport_number[0x10];
3892
b4ff3a36 3893 u8 reserved_at_60[0x5];
e281682b 3894 u8 allowed_list_type[0x3];
b4ff3a36 3895 u8 reserved_at_68[0x18];
e281682b
SM		 3896};
3897
3898struct mlx5_ifc_query_mkey_out_bits {
3899 u8 status[0x8];
b4ff3a36 3900 u8 reserved_at_8[0x18];
e281682b
SM		 3901
3902 u8 syndrome[0x20];
3903
b4ff3a36 3904 u8 reserved_at_40[0x40];
e281682b
SM		 3905
3906 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
3907
b4ff3a36 3908 u8 reserved_at_280[0x600];
e281682b
SM		 3909
3910 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
3911
3912 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
3913};
3914
3915struct mlx5_ifc_query_mkey_in_bits {
3916 u8 opcode[0x10];
b4ff3a36 3917 u8 reserved_at_10[0x10];
e281682b 3918
b4ff3a36 3919 u8 reserved_at_20[0x10];
e281682b
SM		 3920 u8 op_mod[0x10];
3921
b4ff3a36 3922 u8 reserved_at_40[0x8];
e281682b
SM		 3923 u8 mkey_index[0x18];
3924
3925 u8 pg_access[0x1];
b4ff3a36 3926 u8 reserved_at_61[0x1f];
e281682b
SM		 3927};
3928
3929struct mlx5_ifc_query_mad_demux_out_bits {
3930 u8 status[0x8];
b4ff3a36 3931 u8 reserved_at_8[0x18];
e281682b
SM		 3932
3933 u8 syndrome[0x20];
3934
b4ff3a36 3935 u8 reserved_at_40[0x40];
e281682b
SM		 3936
3937 u8 mad_dumux_parameters_block[0x20];
3938};
3939
3940struct mlx5_ifc_query_mad_demux_in_bits {
3941 u8 opcode[0x10];
b4ff3a36 3942 u8 reserved_at_10[0x10];
e281682b 3943
b4ff3a36 3944 u8 reserved_at_20[0x10];
e281682b
SM		 3945 u8 op_mod[0x10];
3946
b4ff3a36 3947 u8 reserved_at_40[0x40];
e281682b
SM		 3948};
3949
3950struct mlx5_ifc_query_l2_table_entry_out_bits {
3951 u8 status[0x8];
b4ff3a36 3952 u8 reserved_at_8[0x18];
e281682b
SM		 3953
3954 u8 syndrome[0x20];
3955
b4ff3a36 3956 u8 reserved_at_40[0xa0];
e281682b 3957
b4ff3a36 3958 u8 reserved_at_e0[0x13];
e281682b
SM		 3959 u8 vlan_valid[0x1];
3960 u8 vlan[0xc];
3961
3962 struct mlx5_ifc_mac_address_layout_bits mac_address;
3963
b4ff3a36 3964 u8 reserved_at_140[0xc0];
e281682b
SM		 3965};
3966
3967struct mlx5_ifc_query_l2_table_entry_in_bits {
3968 u8 opcode[0x10];
b4ff3a36 3969 u8 reserved_at_10[0x10];
e281682b 3970
b4ff3a36 3971 u8 reserved_at_20[0x10];
e281682b
SM		 3972 u8 op_mod[0x10];
3973
b4ff3a36 3974 u8 reserved_at_40[0x60];
e281682b 3975
b4ff3a36 3976 u8 reserved_at_a0[0x8];
e281682b
SM		 3977 u8 table_index[0x18];
3978
b4ff3a36 3979 u8 reserved_at_c0[0x140];
e281682b
SM		 3980};
3981
3982struct mlx5_ifc_query_issi_out_bits {
3983 u8 status[0x8];
b4ff3a36 3984 u8 reserved_at_8[0x18];
e281682b
SM		 3985
3986 u8 syndrome[0x20];
3987
b4ff3a36 3988 u8 reserved_at_40[0x10];
e281682b
SM		 3989 u8 current_issi[0x10];
3990
b4ff3a36 3991 u8 reserved_at_60[0xa0];
e281682b 3992
b4ff3a36 3993 u8 reserved_at_100[76][0x8];
e281682b
SM		 3994 u8 supported_issi_dw0[0x20];
3995};
3996
3997struct mlx5_ifc_query_issi_in_bits {
3998 u8 opcode[0x10];
b4ff3a36 3999 u8 reserved_at_10[0x10];
e281682b 4000
b4ff3a36 4001 u8 reserved_at_20[0x10];
e281682b
SM		 4002 u8 op_mod[0x10];
4003
b4ff3a36 4004 u8 reserved_at_40[0x40];
e281682b
SM		 4005};
4006
4007struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4008 u8 status[0x8];
b4ff3a36 4009 u8 reserved_at_8[0x18];
e281682b
SM		 4010
4011 u8 syndrome[0x20];
4012
b4ff3a36 4013 u8 reserved_at_40[0x40];
e281682b
SM		 4014
4015 struct mlx5_ifc_pkey_bits pkey[0];
4016};
4017
4018struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4019 u8 opcode[0x10];
b4ff3a36 4020 u8 reserved_at_10[0x10];
e281682b 4021
b4ff3a36 4022 u8 reserved_at_20[0x10];
e281682b
SM		 4023 u8 op_mod[0x10];
4024
4025 u8 other_vport[0x1];
b4ff3a36 4026 u8 reserved_at_41[0xb];
707c4602 4027 u8 port_num[0x4];
e281682b
SM		 4028 u8 vport_number[0x10];
4029
b4ff3a36 4030 u8 reserved_at_60[0x10];
e281682b
SM		 4031 u8 pkey_index[0x10];
4032};
4033
eff901d3
EC		 4034enum {
4035 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
4036 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
4037 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4038};
4039
e281682b
SM		 4040struct mlx5_ifc_query_hca_vport_gid_out_bits {
4041 u8 status[0x8];
b4ff3a36 4042 u8 reserved_at_8[0x18];
e281682b
SM		 4043
4044 u8 syndrome[0x20];
4045
b4ff3a36 4046 u8 reserved_at_40[0x20];
e281682b
SM		 4047
4048 u8 gids_num[0x10];
b4ff3a36 4049 u8 reserved_at_70[0x10];
e281682b
SM		 4050
4051 struct mlx5_ifc_array128_auto_bits gid[0];
4052};
4053
4054struct mlx5_ifc_query_hca_vport_gid_in_bits {
4055 u8 opcode[0x10];
b4ff3a36 4056 u8 reserved_at_10[0x10];
e281682b 4057
b4ff3a36 4058 u8 reserved_at_20[0x10];
e281682b
SM		 4059 u8 op_mod[0x10];
4060
4061 u8 other_vport[0x1];
b4ff3a36 4062 u8 reserved_at_41[0xb];
707c4602 4063 u8 port_num[0x4];
e281682b
SM		 4064 u8 vport_number[0x10];
4065
b4ff3a36 4066 u8 reserved_at_60[0x10];
e281682b
SM		 4067 u8 gid_index[0x10];
4068};
4069
4070struct mlx5_ifc_query_hca_vport_context_out_bits {
4071 u8 status[0x8];
b4ff3a36 4072 u8 reserved_at_8[0x18];
e281682b
SM		 4073
4074 u8 syndrome[0x20];
4075
b4ff3a36 4076 u8 reserved_at_40[0x40];
e281682b
SM		 4077
4078 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4079};
4080
4081struct mlx5_ifc_query_hca_vport_context_in_bits {
4082 u8 opcode[0x10];
b4ff3a36 4083 u8 reserved_at_10[0x10];
e281682b 4084
b4ff3a36 4085 u8 reserved_at_20[0x10];
e281682b
SM		 4086 u8 op_mod[0x10];
4087
4088 u8 other_vport[0x1];
b4ff3a36 4089 u8 reserved_at_41[0xb];
707c4602 4090 u8 port_num[0x4];
e281682b
SM		 4091 u8 vport_number[0x10];
4092
b4ff3a36 4093 u8 reserved_at_60[0x20];
e281682b
SM		 4094};
4095
4096struct mlx5_ifc_query_hca_cap_out_bits {
4097 u8 status[0x8];
b4ff3a36 4098 u8 reserved_at_8[0x18];
e281682b
SM		 4099
4100 u8 syndrome[0x20];
4101
b4ff3a36 4102 u8 reserved_at_40[0x40];
e281682b
SM		 4103
4104 union mlx5_ifc_hca_cap_union_bits capability;
4105};
4106
4107struct mlx5_ifc_query_hca_cap_in_bits {
4108 u8 opcode[0x10];
b4ff3a36 4109 u8 reserved_at_10[0x10];
e281682b 4110
b4ff3a36 4111 u8 reserved_at_20[0x10];
e281682b
SM		 4112 u8 op_mod[0x10];
4113
b4ff3a36 4114 u8 reserved_at_40[0x40];
e281682b
SM		 4115};
4116
4117struct mlx5_ifc_query_flow_table_out_bits {
4118 u8 status[0x8];
b4ff3a36 4119 u8 reserved_at_8[0x18];
e281682b
SM		 4120
4121 u8 syndrome[0x20];
4122
b4ff3a36 4123 u8 reserved_at_40[0x80];
e281682b 4124
b4ff3a36 4125 u8 reserved_at_c0[0x8];
e281682b 4126 u8 level[0x8];
b4ff3a36 4127 u8 reserved_at_d0[0x8];
e281682b
SM		 4128 u8 log_size[0x8];
4129
b4ff3a36 4130 u8 reserved_at_e0[0x120];
e281682b
SM		 4131};
4132
4133struct mlx5_ifc_query_flow_table_in_bits {
4134 u8 opcode[0x10];
b4ff3a36 4135 u8 reserved_at_10[0x10];
e281682b 4136
b4ff3a36 4137 u8 reserved_at_20[0x10];
e281682b
SM		 4138 u8 op_mod[0x10];
4139
b4ff3a36 4140 u8 reserved_at_40[0x40];
e281682b
SM		 4141
4142 u8 table_type[0x8];
b4ff3a36 4143 u8 reserved_at_88[0x18];
e281682b 4144
b4ff3a36 4145 u8 reserved_at_a0[0x8];
e281682b
SM		 4146 u8 table_id[0x18];
4147
b4ff3a36 4148 u8 reserved_at_c0[0x140];
e281682b
SM		 4149};
4150
4151struct mlx5_ifc_query_fte_out_bits {
4152 u8 status[0x8];
b4ff3a36 4153 u8 reserved_at_8[0x18];
e281682b
SM		 4154
4155 u8 syndrome[0x20];
4156
b4ff3a36 4157 u8 reserved_at_40[0x1c0];
e281682b
SM		 4158
4159 struct mlx5_ifc_flow_context_bits flow_context;
4160};
4161
4162struct mlx5_ifc_query_fte_in_bits {
4163 u8 opcode[0x10];
b4ff3a36 4164 u8 reserved_at_10[0x10];
e281682b 4165
b4ff3a36 4166 u8 reserved_at_20[0x10];
e281682b
SM		 4167 u8 op_mod[0x10];
4168
b4ff3a36 4169 u8 reserved_at_40[0x40];
e281682b
SM		 4170
4171 u8 table_type[0x8];
b4ff3a36 4172 u8 reserved_at_88[0x18];
e281682b 4173
b4ff3a36 4174 u8 reserved_at_a0[0x8];
e281682b
SM		 4175 u8 table_id[0x18];
4176
b4ff3a36 4177 u8 reserved_at_c0[0x40];
e281682b
SM		 4178
4179 u8 flow_index[0x20];
4180
b4ff3a36 4181 u8 reserved_at_120[0xe0];
e281682b
SM		 4182};
4183
4184enum {
4185 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
4186 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
4187 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
4188};
4189
4190struct mlx5_ifc_query_flow_group_out_bits {
4191 u8 status[0x8];
b4ff3a36 4192 u8 reserved_at_8[0x18];
e281682b
SM		 4193
4194 u8 syndrome[0x20];
4195
b4ff3a36 4196 u8 reserved_at_40[0xa0];
e281682b
SM		 4197
4198 u8 start_flow_index[0x20];
4199
b4ff3a36 4200 u8 reserved_at_100[0x20];
e281682b
SM		 4201
4202 u8 end_flow_index[0x20];
4203
b4ff3a36 4204 u8 reserved_at_140[0xa0];
e281682b 4205
b4ff3a36 4206 u8 reserved_at_1e0[0x18];
e281682b
SM		 4207 u8 match_criteria_enable[0x8];
4208
4209 struct mlx5_ifc_fte_match_param_bits match_criteria;
4210
b4ff3a36 4211 u8 reserved_at_1200[0xe00];
e281682b
SM		 4212};
4213
4214struct mlx5_ifc_query_flow_group_in_bits {
4215 u8 opcode[0x10];
b4ff3a36 4216 u8 reserved_at_10[0x10];
e281682b 4217
b4ff3a36 4218 u8 reserved_at_20[0x10];
e281682b
SM		 4219 u8 op_mod[0x10];
4220
b4ff3a36 4221 u8 reserved_at_40[0x40];
e281682b
SM		 4222
4223 u8 table_type[0x8];
b4ff3a36 4224 u8 reserved_at_88[0x18];
e281682b 4225
b4ff3a36 4226 u8 reserved_at_a0[0x8];
e281682b
SM		 4227 u8 table_id[0x18];
4228
4229 u8 group_id[0x20];
4230
b4ff3a36 4231 u8 reserved_at_e0[0x120];
e281682b
SM		 4232};
4233
9dc0b289
AV		 4234struct mlx5_ifc_query_flow_counter_out_bits {
4235 u8 status[0x8];
4236 u8 reserved_at_8[0x18];
4237
4238 u8 syndrome[0x20];
4239
4240 u8 reserved_at_40[0x40];
4241
4242 struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4243};
4244
4245struct mlx5_ifc_query_flow_counter_in_bits {
4246 u8 opcode[0x10];
4247 u8 reserved_at_10[0x10];
4248
4249 u8 reserved_at_20[0x10];
4250 u8 op_mod[0x10];
4251
4252 u8 reserved_at_40[0x80];
4253
4254 u8 clear[0x1];
4255 u8 reserved_at_c1[0xf];
4256 u8 num_of_counters[0x10];
4257
4258 u8 reserved_at_e0[0x10];
4259 u8 flow_counter_id[0x10];
4260};
4261
d6666753
SM		 4262struct mlx5_ifc_query_esw_vport_context_out_bits {
4263 u8 status[0x8];
b4ff3a36 4264 u8 reserved_at_8[0x18];
d6666753
SM		 4265
4266 u8 syndrome[0x20];
4267
b4ff3a36 4268 u8 reserved_at_40[0x40];
d6666753
SM		 4269
4270 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4271};
4272
4273struct mlx5_ifc_query_esw_vport_context_in_bits {
4274 u8 opcode[0x10];
b4ff3a36 4275 u8 reserved_at_10[0x10];
d6666753 4276
b4ff3a36 4277 u8 reserved_at_20[0x10];
d6666753
SM		 4278 u8 op_mod[0x10];
4279
4280 u8 other_vport[0x1];
b4ff3a36 4281 u8 reserved_at_41[0xf];
d6666753
SM		 4282 u8 vport_number[0x10];
4283
b4ff3a36 4284 u8 reserved_at_60[0x20];
d6666753
SM		 4285};
4286
4287struct mlx5_ifc_modify_esw_vport_context_out_bits {
4288 u8 status[0x8];
b4ff3a36 4289 u8 reserved_at_8[0x18];
d6666753
SM		 4290
4291 u8 syndrome[0x20];
4292
b4ff3a36 4293 u8 reserved_at_40[0x40];
d6666753
SM		 4294};
4295
4296struct mlx5_ifc_esw_vport_context_fields_select_bits {
b4ff3a36 4297 u8 reserved_at_0[0x1c];
d6666753
SM		 4298 u8 vport_cvlan_insert[0x1];
4299 u8 vport_svlan_insert[0x1];
4300 u8 vport_cvlan_strip[0x1];
4301 u8 vport_svlan_strip[0x1];
4302};
4303
4304struct mlx5_ifc_modify_esw_vport_context_in_bits {
4305 u8 opcode[0x10];
b4ff3a36 4306 u8 reserved_at_10[0x10];
d6666753 4307
b4ff3a36 4308 u8 reserved_at_20[0x10];
d6666753
SM		 4309 u8 op_mod[0x10];
4310
4311 u8 other_vport[0x1];
b4ff3a36 4312 u8 reserved_at_41[0xf];
d6666753
SM		 4313 u8 vport_number[0x10];
4314
4315 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4316
4317 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4318};
4319
e281682b
SM		 4320struct mlx5_ifc_query_eq_out_bits {
4321 u8 status[0x8];
b4ff3a36 4322 u8 reserved_at_8[0x18];
e281682b
SM		 4323
4324 u8 syndrome[0x20];
4325
b4ff3a36 4326 u8 reserved_at_40[0x40];
e281682b
SM		 4327
4328 struct mlx5_ifc_eqc_bits eq_context_entry;
4329
b4ff3a36 4330 u8 reserved_at_280[0x40];
e281682b
SM		 4331
4332 u8 event_bitmask[0x40];
4333
b4ff3a36 4334 u8 reserved_at_300[0x580];
e281682b
SM		 4335
4336 u8 pas[0][0x40];
4337};
4338
4339struct mlx5_ifc_query_eq_in_bits {
4340 u8 opcode[0x10];
b4ff3a36 4341 u8 reserved_at_10[0x10];
e281682b 4342
b4ff3a36 4343 u8 reserved_at_20[0x10];
e281682b
SM		 4344 u8 op_mod[0x10];
4345
b4ff3a36 4346 u8 reserved_at_40[0x18];
e281682b
SM		 4347 u8 eq_number[0x8];
4348
b4ff3a36 4349 u8 reserved_at_60[0x20];
e281682b
SM		 4350};
4351
7adbde20
HHZ		 4352struct mlx5_ifc_encap_header_in_bits {
4353 u8 reserved_at_0[0x5];
4354 u8 header_type[0x3];
4355 u8 reserved_at_8[0xe];
4356 u8 encap_header_size[0xa];
4357
4358 u8 reserved_at_20[0x10];
4359 u8 encap_header[2][0x8];
4360
4361 u8 more_encap_header[0][0x8];
4362};
4363
4364struct mlx5_ifc_query_encap_header_out_bits {
4365 u8 status[0x8];
4366 u8 reserved_at_8[0x18];
4367
4368 u8 syndrome[0x20];
4369
4370 u8 reserved_at_40[0xa0];
4371
4372 struct mlx5_ifc_encap_header_in_bits encap_header[0];
4373};
4374
4375struct mlx5_ifc_query_encap_header_in_bits {
4376 u8 opcode[0x10];
4377 u8 reserved_at_10[0x10];
4378
4379 u8 reserved_at_20[0x10];
4380 u8 op_mod[0x10];
4381
4382 u8 encap_id[0x20];
4383
4384 u8 reserved_at_60[0xa0];
4385};
4386
4387struct mlx5_ifc_alloc_encap_header_out_bits {
4388 u8 status[0x8];
4389 u8 reserved_at_8[0x18];
4390
4391 u8 syndrome[0x20];
4392
4393 u8 encap_id[0x20];
4394
4395 u8 reserved_at_60[0x20];
4396};
4397
4398struct mlx5_ifc_alloc_encap_header_in_bits {
4399 u8 opcode[0x10];
4400 u8 reserved_at_10[0x10];
4401
4402 u8 reserved_at_20[0x10];
4403 u8 op_mod[0x10];
4404
4405 u8 reserved_at_40[0xa0];
4406
4407 struct mlx5_ifc_encap_header_in_bits encap_header;
4408};
4409
4410struct mlx5_ifc_dealloc_encap_header_out_bits {
4411 u8 status[0x8];
4412 u8 reserved_at_8[0x18];
4413
4414 u8 syndrome[0x20];
4415
4416 u8 reserved_at_40[0x40];
4417};
4418
4419struct mlx5_ifc_dealloc_encap_header_in_bits {
4420 u8 opcode[0x10];
4421 u8 reserved_at_10[0x10];
4422
4423 u8 reserved_20[0x10];
4424 u8 op_mod[0x10];
4425
4426 u8 encap_id[0x20];
4427
4428 u8 reserved_60[0x20];
4429};
4430
e281682b
SM		 4431struct mlx5_ifc_query_dct_out_bits {
4432 u8 status[0x8];
b4ff3a36 4433 u8 reserved_at_8[0x18];
e281682b
SM		 4434
4435 u8 syndrome[0x20];
4436
b4ff3a36 4437 u8 reserved_at_40[0x40];
e281682b
SM		 4438
4439 struct mlx5_ifc_dctc_bits dct_context_entry;
4440
b4ff3a36 4441 u8 reserved_at_280[0x180];
e281682b
SM		 4442};
4443
4444struct mlx5_ifc_query_dct_in_bits {
4445 u8 opcode[0x10];
b4ff3a36 4446 u8 reserved_at_10[0x10];
e281682b 4447
b4ff3a36 4448 u8 reserved_at_20[0x10];
e281682b
SM		 4449 u8 op_mod[0x10];
4450
b4ff3a36 4451 u8 reserved_at_40[0x8];
e281682b
SM		 4452 u8 dctn[0x18];
4453
b4ff3a36 4454 u8 reserved_at_60[0x20];
e281682b
SM		 4455};
4456
4457struct mlx5_ifc_query_cq_out_bits {
4458 u8 status[0x8];
b4ff3a36 4459 u8 reserved_at_8[0x18];
e281682b
SM		 4460
4461 u8 syndrome[0x20];
4462
b4ff3a36 4463 u8 reserved_at_40[0x40];
e281682b
SM		 4464
4465 struct mlx5_ifc_cqc_bits cq_context;
4466
b4ff3a36 4467 u8 reserved_at_280[0x600];
e281682b
SM		 4468
4469 u8 pas[0][0x40];
4470};
4471
4472struct mlx5_ifc_query_cq_in_bits {
4473 u8 opcode[0x10];
b4ff3a36 4474 u8 reserved_at_10[0x10];
e281682b 4475
b4ff3a36 4476 u8 reserved_at_20[0x10];
e281682b
SM		 4477 u8 op_mod[0x10];
4478
b4ff3a36 4479 u8 reserved_at_40[0x8];
e281682b
SM		 4480 u8 cqn[0x18];
4481
b4ff3a36 4482 u8 reserved_at_60[0x20];
e281682b
SM		 4483};
4484
4485struct mlx5_ifc_query_cong_status_out_bits {
4486 u8 status[0x8];
b4ff3a36 4487 u8 reserved_at_8[0x18];
e281682b
SM		 4488
4489 u8 syndrome[0x20];
4490
b4ff3a36 4491 u8 reserved_at_40[0x20];
e281682b
SM		 4492
4493 u8 enable[0x1];
4494 u8 tag_enable[0x1];
b4ff3a36 4495 u8 reserved_at_62[0x1e];
e281682b
SM		 4496};
4497
4498struct mlx5_ifc_query_cong_status_in_bits {
4499 u8 opcode[0x10];
b4ff3a36 4500 u8 reserved_at_10[0x10];
e281682b 4501
b4ff3a36 4502 u8 reserved_at_20[0x10];
e281682b
SM		 4503 u8 op_mod[0x10];
4504
b4ff3a36 4505 u8 reserved_at_40[0x18];
e281682b
SM		 4506 u8 priority[0x4];
4507 u8 cong_protocol[0x4];
4508
b4ff3a36 4509 u8 reserved_at_60[0x20];
e281682b
SM		 4510};
4511
4512struct mlx5_ifc_query_cong_statistics_out_bits {
4513 u8 status[0x8];
b4ff3a36 4514 u8 reserved_at_8[0x18];
e281682b
SM		 4515
4516 u8 syndrome[0x20];
4517
b4ff3a36 4518 u8 reserved_at_40[0x40];
e281682b
SM		 4519
4520 u8 cur_flows[0x20];
4521
4522 u8 sum_flows[0x20];
4523
4524 u8 cnp_ignored_high[0x20];
4525
4526 u8 cnp_ignored_low[0x20];
4527
4528 u8 cnp_handled_high[0x20];
4529
4530 u8 cnp_handled_low[0x20];
4531
b4ff3a36 4532 u8 reserved_at_140[0x100];
e281682b
SM		 4533
4534 u8 time_stamp_high[0x20];
4535
4536 u8 time_stamp_low[0x20];
4537
4538 u8 accumulators_period[0x20];
4539
4540 u8 ecn_marked_roce_packets_high[0x20];
4541
4542 u8 ecn_marked_roce_packets_low[0x20];
4543
4544 u8 cnps_sent_high[0x20];
4545
4546 u8 cnps_sent_low[0x20];
4547
b4ff3a36 4548 u8 reserved_at_320[0x560];
e281682b
SM		 4549};
4550
4551struct mlx5_ifc_query_cong_statistics_in_bits {
4552 u8 opcode[0x10];
b4ff3a36 4553 u8 reserved_at_10[0x10];
e281682b 4554
b4ff3a36 4555 u8 reserved_at_20[0x10];
e281682b
SM		 4556 u8 op_mod[0x10];
4557
4558 u8 clear[0x1];
b4ff3a36 4559 u8 reserved_at_41[0x1f];
e281682b 4560
b4ff3a36 4561 u8 reserved_at_60[0x20];
e281682b
SM		 4562};
4563
4564struct mlx5_ifc_query_cong_params_out_bits {
4565 u8 status[0x8];
b4ff3a36 4566 u8 reserved_at_8[0x18];
e281682b
SM		 4567
4568 u8 syndrome[0x20];
4569
b4ff3a36 4570 u8 reserved_at_40[0x40];
e281682b
SM		 4571
4572 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4573};
4574
4575struct mlx5_ifc_query_cong_params_in_bits {
4576 u8 opcode[0x10];
b4ff3a36 4577 u8 reserved_at_10[0x10];
e281682b 4578
b4ff3a36 4579 u8 reserved_at_20[0x10];
e281682b
SM		 4580 u8 op_mod[0x10];
4581
b4ff3a36 4582 u8 reserved_at_40[0x1c];
e281682b
SM		 4583 u8 cong_protocol[0x4];
4584
b4ff3a36 4585 u8 reserved_at_60[0x20];
e281682b
SM		 4586};
4587
4588struct mlx5_ifc_query_adapter_out_bits {
4589 u8 status[0x8];
b4ff3a36 4590 u8 reserved_at_8[0x18];
e281682b
SM		 4591
4592 u8 syndrome[0x20];
4593
b4ff3a36 4594 u8 reserved_at_40[0x40];
e281682b
SM		 4595
4596 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4597};
4598
4599struct mlx5_ifc_query_adapter_in_bits {
4600 u8 opcode[0x10];
b4ff3a36 4601 u8 reserved_at_10[0x10];
e281682b 4602
b4ff3a36 4603 u8 reserved_at_20[0x10];
e281682b
SM		 4604 u8 op_mod[0x10];
4605
b4ff3a36 4606 u8 reserved_at_40[0x40];
e281682b
SM		 4607};
4608
4609struct mlx5_ifc_qp_2rst_out_bits {
4610 u8 status[0x8];
b4ff3a36 4611 u8 reserved_at_8[0x18];
e281682b
SM		 4612
4613 u8 syndrome[0x20];
4614
b4ff3a36 4615 u8 reserved_at_40[0x40];
e281682b
SM		 4616};
4617
4618struct mlx5_ifc_qp_2rst_in_bits {
4619 u8 opcode[0x10];
b4ff3a36 4620 u8 reserved_at_10[0x10];
e281682b 4621
b4ff3a36 4622 u8 reserved_at_20[0x10];
e281682b
SM		 4623 u8 op_mod[0x10];
4624
b4ff3a36 4625 u8 reserved_at_40[0x8];
e281682b
SM		 4626 u8 qpn[0x18];
4627
b4ff3a36 4628 u8 reserved_at_60[0x20];
e281682b
SM		 4629};
4630
4631struct mlx5_ifc_qp_2err_out_bits {
4632 u8 status[0x8];
b4ff3a36 4633 u8 reserved_at_8[0x18];
e281682b
SM		 4634
4635 u8 syndrome[0x20];
4636
b4ff3a36 4637 u8 reserved_at_40[0x40];
e281682b
SM		 4638};
4639
4640struct mlx5_ifc_qp_2err_in_bits {
4641 u8 opcode[0x10];
b4ff3a36 4642 u8 reserved_at_10[0x10];
e281682b 4643
b4ff3a36 4644 u8 reserved_at_20[0x10];
e281682b
SM		 4645 u8 op_mod[0x10];
4646
b4ff3a36 4647 u8 reserved_at_40[0x8];
e281682b
SM		 4648 u8 qpn[0x18];
4649
b4ff3a36 4650 u8 reserved_at_60[0x20];
e281682b
SM		 4651};
4652
4653struct mlx5_ifc_page_fault_resume_out_bits {
4654 u8 status[0x8];
b4ff3a36 4655 u8 reserved_at_8[0x18];
e281682b
SM		 4656
4657 u8 syndrome[0x20];
4658
b4ff3a36 4659 u8 reserved_at_40[0x40];
e281682b
SM		 4660};
4661
4662struct mlx5_ifc_page_fault_resume_in_bits {
4663 u8 opcode[0x10];
b4ff3a36 4664 u8 reserved_at_10[0x10];
e281682b 4665
b4ff3a36 4666 u8 reserved_at_20[0x10];
e281682b
SM		 4667 u8 op_mod[0x10];
4668
4669 u8 error[0x1];
b4ff3a36 4670 u8 reserved_at_41[0x4];
e281682b
SM		 4671 u8 rdma[0x1];
4672 u8 read_write[0x1];
4673 u8 req_res[0x1];
4674 u8 qpn[0x18];
4675
b4ff3a36 4676 u8 reserved_at_60[0x20];
e281682b
SM		 4677};
4678
4679struct mlx5_ifc_nop_out_bits {
4680 u8 status[0x8];
b4ff3a36 4681 u8 reserved_at_8[0x18];
e281682b
SM		 4682
4683 u8 syndrome[0x20];
4684
b4ff3a36 4685 u8 reserved_at_40[0x40];
e281682b
SM		 4686};
4687
4688struct mlx5_ifc_nop_in_bits {
4689 u8 opcode[0x10];
b4ff3a36 4690 u8 reserved_at_10[0x10];
e281682b 4691
b4ff3a36 4692 u8 reserved_at_20[0x10];
e281682b
SM		 4693 u8 op_mod[0x10];
4694
b4ff3a36 4695 u8 reserved_at_40[0x40];
e281682b
SM		 4696};
4697
4698struct mlx5_ifc_modify_vport_state_out_bits {
4699 u8 status[0x8];
b4ff3a36 4700 u8 reserved_at_8[0x18];
e281682b
SM		 4701
4702 u8 syndrome[0x20];
4703
b4ff3a36 4704 u8 reserved_at_40[0x40];
e281682b
SM		 4705};
4706
4707struct mlx5_ifc_modify_vport_state_in_bits {
4708 u8 opcode[0x10];
b4ff3a36 4709 u8 reserved_at_10[0x10];
e281682b 4710
b4ff3a36 4711 u8 reserved_at_20[0x10];
e281682b
SM		 4712 u8 op_mod[0x10];
4713
4714 u8 other_vport[0x1];
b4ff3a36 4715 u8 reserved_at_41[0xf];
e281682b
SM		 4716 u8 vport_number[0x10];
4717
b4ff3a36 4718 u8 reserved_at_60[0x18];
e281682b 4719 u8 admin_state[0x4];
b4ff3a36 4720 u8 reserved_at_7c[0x4];
e281682b
SM		 4721};
4722
4723struct mlx5_ifc_modify_tis_out_bits {
4724 u8 status[0x8];
b4ff3a36 4725 u8 reserved_at_8[0x18];
e281682b
SM		 4726
4727 u8 syndrome[0x20];
4728
b4ff3a36 4729 u8 reserved_at_40[0x40];
e281682b
SM		 4730};
4731
75850d0b 4732struct mlx5_ifc_modify_tis_bitmask_bits {
b4ff3a36 4733 u8 reserved_at_0[0x20];
75850d0b 4734
84df61eb
AH		 4735 u8 reserved_at_20[0x1d];
4736 u8 lag_tx_port_affinity[0x1];
4737 u8 strict_lag_tx_port_affinity[0x1];
75850d0b 4738 u8 prio[0x1];
4739};
4740
e281682b
SM		 4741struct mlx5_ifc_modify_tis_in_bits {
4742 u8 opcode[0x10];
b4ff3a36 4743 u8 reserved_at_10[0x10];
e281682b 4744
b4ff3a36 4745 u8 reserved_at_20[0x10];
e281682b
SM		 4746 u8 op_mod[0x10];
4747
b4ff3a36 4748 u8 reserved_at_40[0x8];
e281682b
SM		 4749 u8 tisn[0x18];
4750
b4ff3a36 4751 u8 reserved_at_60[0x20];
e281682b 4752
75850d0b 4753 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
e281682b 4754
b4ff3a36 4755 u8 reserved_at_c0[0x40];
e281682b
SM		 4756
4757 struct mlx5_ifc_tisc_bits ctx;
4758};
4759
d9eea403 4760struct mlx5_ifc_modify_tir_bitmask_bits {
b4ff3a36 4761 u8 reserved_at_0[0x20];
d9eea403 4762
b4ff3a36 4763 u8 reserved_at_20[0x1b];
66189961 4764 u8 self_lb_en[0x1];
bdfc028d
TT		 4765 u8 reserved_at_3c[0x1];
4766 u8 hash[0x1];
4767 u8 reserved_at_3e[0x1];
d9eea403
AS		 4768 u8 lro[0x1];
4769};
4770
e281682b
SM		 4771struct mlx5_ifc_modify_tir_out_bits {
4772 u8 status[0x8];
b4ff3a36 4773 u8 reserved_at_8[0x18];
e281682b
SM		 4774
4775 u8 syndrome[0x20];
4776
b4ff3a36 4777 u8 reserved_at_40[0x40];
e281682b
SM		 4778};
4779
4780struct mlx5_ifc_modify_tir_in_bits {
4781 u8 opcode[0x10];
b4ff3a36 4782 u8 reserved_at_10[0x10];
e281682b 4783
b4ff3a36 4784 u8 reserved_at_20[0x10];
e281682b
SM		 4785 u8 op_mod[0x10];
4786
b4ff3a36 4787 u8 reserved_at_40[0x8];
e281682b
SM		 4788 u8 tirn[0x18];
4789
b4ff3a36 4790 u8 reserved_at_60[0x20];
e281682b 4791
d9eea403 4792 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
e281682b 4793
b4ff3a36 4794 u8 reserved_at_c0[0x40];
e281682b
SM		 4795
4796 struct mlx5_ifc_tirc_bits ctx;
4797};
4798
4799struct mlx5_ifc_modify_sq_out_bits {
4800 u8 status[0x8];
b4ff3a36 4801 u8 reserved_at_8[0x18];
e281682b
SM		 4802
4803 u8 syndrome[0x20];
4804
b4ff3a36 4805 u8 reserved_at_40[0x40];
e281682b
SM		 4806};
4807
4808struct mlx5_ifc_modify_sq_in_bits {
4809 u8 opcode[0x10];
b4ff3a36 4810 u8 reserved_at_10[0x10];
e281682b 4811
b4ff3a36 4812 u8 reserved_at_20[0x10];
e281682b
SM		 4813 u8 op_mod[0x10];
4814
4815 u8 sq_state[0x4];
b4ff3a36 4816 u8 reserved_at_44[0x4];
e281682b
SM		 4817 u8 sqn[0x18];
4818
b4ff3a36 4819 u8 reserved_at_60[0x20];
e281682b
SM		 4820
4821 u8 modify_bitmask[0x40];
4822
b4ff3a36 4823 u8 reserved_at_c0[0x40];
e281682b
SM		 4824
4825 struct mlx5_ifc_sqc_bits ctx;
4826};
4827
813f8540
MHY		 4828struct mlx5_ifc_modify_scheduling_element_out_bits {
4829 u8 status[0x8];
4830 u8 reserved_at_8[0x18];
4831
4832 u8 syndrome[0x20];
4833
4834 u8 reserved_at_40[0x1c0];
4835};
4836
4837enum {
4838 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
4839 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
4840};
4841
4842struct mlx5_ifc_modify_scheduling_element_in_bits {
4843 u8 opcode[0x10];
4844 u8 reserved_at_10[0x10];
4845
4846 u8 reserved_at_20[0x10];
4847 u8 op_mod[0x10];
4848
4849 u8 scheduling_hierarchy[0x8];
4850 u8 reserved_at_48[0x18];
4851
4852 u8 scheduling_element_id[0x20];
4853
4854 u8 reserved_at_80[0x20];
4855
4856 u8 modify_bitmask[0x20];
4857
4858 u8 reserved_at_c0[0x40];
4859
4860 struct mlx5_ifc_scheduling_context_bits scheduling_context;
4861
4862 u8 reserved_at_300[0x100];
4863};
4864
e281682b
SM		 4865struct mlx5_ifc_modify_rqt_out_bits {
4866 u8 status[0x8];
b4ff3a36 4867 u8 reserved_at_8[0x18];
e281682b
SM		 4868
4869 u8 syndrome[0x20];
4870
b4ff3a36 4871 u8 reserved_at_40[0x40];
e281682b
SM		 4872};
4873
5c50368f 4874struct mlx5_ifc_rqt_bitmask_bits {
b4ff3a36 4875 u8 reserved_at_0[0x20];
5c50368f 4876
b4ff3a36 4877 u8 reserved_at_20[0x1f];
5c50368f
AS		 4878 u8 rqn_list[0x1];
4879};
4880
e281682b
SM		 4881struct mlx5_ifc_modify_rqt_in_bits {
4882 u8 opcode[0x10];
b4ff3a36 4883 u8 reserved_at_10[0x10];
e281682b 4884
b4ff3a36 4885 u8 reserved_at_20[0x10];
e281682b
SM		 4886 u8 op_mod[0x10];
4887
b4ff3a36 4888 u8 reserved_at_40[0x8];
e281682b
SM		 4889 u8 rqtn[0x18];
4890
b4ff3a36 4891 u8 reserved_at_60[0x20];
e281682b 4892
5c50368f 4893 struct mlx5_ifc_rqt_bitmask_bits bitmask;
e281682b 4894
b4ff3a36 4895 u8 reserved_at_c0[0x40];
e281682b
SM		 4896
4897 struct mlx5_ifc_rqtc_bits ctx;
4898};
4899
4900struct mlx5_ifc_modify_rq_out_bits {
4901 u8 status[0x8];
b4ff3a36 4902 u8 reserved_at_8[0x18];
e281682b
SM		 4903
4904 u8 syndrome[0x20];
4905
b4ff3a36 4906 u8 reserved_at_40[0x40];
e281682b
SM		 4907};
4908
83b502a1
AV		 4909enum {
4910 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
4911 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID = 1ULL << 3,
4912};
4913
e281682b
SM		 4914struct mlx5_ifc_modify_rq_in_bits {
4915 u8 opcode[0x10];
b4ff3a36 4916 u8 reserved_at_10[0x10];
e281682b 4917
b4ff3a36 4918 u8 reserved_at_20[0x10];
e281682b
SM		 4919 u8 op_mod[0x10];
4920
4921 u8 rq_state[0x4];
b4ff3a36 4922 u8 reserved_at_44[0x4];
e281682b
SM		 4923 u8 rqn[0x18];
4924
b4ff3a36 4925 u8 reserved_at_60[0x20];
e281682b
SM		 4926
4927 u8 modify_bitmask[0x40];
4928
b4ff3a36 4929 u8 reserved_at_c0[0x40];
e281682b
SM		 4930
4931 struct mlx5_ifc_rqc_bits ctx;
4932};
4933
4934struct mlx5_ifc_modify_rmp_out_bits {
4935 u8 status[0x8];
b4ff3a36 4936 u8 reserved_at_8[0x18];
e281682b
SM		 4937
4938 u8 syndrome[0x20];
4939
b4ff3a36 4940 u8 reserved_at_40[0x40];
e281682b
SM		 4941};
4942
01949d01 4943struct mlx5_ifc_rmp_bitmask_bits {
b4ff3a36 4944 u8 reserved_at_0[0x20];
01949d01 4945
b4ff3a36 4946 u8 reserved_at_20[0x1f];
01949d01
HA		 4947 u8 lwm[0x1];
4948};
4949
e281682b
SM		 4950struct mlx5_ifc_modify_rmp_in_bits {
4951 u8 opcode[0x10];
b4ff3a36 4952 u8 reserved_at_10[0x10];
e281682b 4953
b4ff3a36 4954 u8 reserved_at_20[0x10];
e281682b
SM		 4955 u8 op_mod[0x10];
4956
4957 u8 rmp_state[0x4];
b4ff3a36 4958 u8 reserved_at_44[0x4];
e281682b
SM		 4959 u8 rmpn[0x18];
4960
b4ff3a36 4961 u8 reserved_at_60[0x20];
e281682b 4962
01949d01 4963 struct mlx5_ifc_rmp_bitmask_bits bitmask;
e281682b 4964
b4ff3a36 4965 u8 reserved_at_c0[0x40];
e281682b
SM		 4966
4967 struct mlx5_ifc_rmpc_bits ctx;
4968};
4969
4970struct mlx5_ifc_modify_nic_vport_context_out_bits {
4971 u8 status[0x8];
b4ff3a36 4972 u8 reserved_at_8[0x18];
e281682b
SM		 4973
4974 u8 syndrome[0x20];
4975
b4ff3a36 4976 u8 reserved_at_40[0x40];
e281682b
SM		 4977};
4978
4979struct mlx5_ifc_modify_nic_vport_field_select_bits {
23898c76
NO		 4980 u8 reserved_at_0[0x16];
4981 u8 node_guid[0x1];
4982 u8 port_guid[0x1];
9def7121 4983 u8 min_inline[0x1];
d82b7318
SM		 4984 u8 mtu[0x1];
4985 u8 change_event[0x1];
4986 u8 promisc[0x1];
e281682b
SM		 4987 u8 permanent_address[0x1];
4988 u8 addresses_list[0x1];
4989 u8 roce_en[0x1];
b4ff3a36 4990 u8 reserved_at_1f[0x1];
e281682b
SM		 4991};
4992
4993struct mlx5_ifc_modify_nic_vport_context_in_bits {
4994 u8 opcode[0x10];
b4ff3a36 4995 u8 reserved_at_10[0x10];
e281682b 4996
b4ff3a36 4997 u8 reserved_at_20[0x10];
e281682b
SM		 4998 u8 op_mod[0x10];
4999
5000 u8 other_vport[0x1];
b4ff3a36 5001 u8 reserved_at_41[0xf];
e281682b
SM		 5002 u8 vport_number[0x10];
5003
5004 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5005
b4ff3a36 5006 u8 reserved_at_80[0x780];
e281682b
SM		 5007
5008 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5009};
5010
5011struct mlx5_ifc_modify_hca_vport_context_out_bits {
5012 u8 status[0x8];
b4ff3a36 5013 u8 reserved_at_8[0x18];
e281682b
SM		 5014
5015 u8 syndrome[0x20];
5016
b4ff3a36 5017 u8 reserved_at_40[0x40];
e281682b
SM		 5018};
5019
5020struct mlx5_ifc_modify_hca_vport_context_in_bits {
5021 u8 opcode[0x10];
b4ff3a36 5022 u8 reserved_at_10[0x10];
e281682b 5023
b4ff3a36 5024 u8 reserved_at_20[0x10];
e281682b
SM		 5025 u8 op_mod[0x10];
5026
5027 u8 other_vport[0x1];
b4ff3a36 5028 u8 reserved_at_41[0xb];
707c4602 5029 u8 port_num[0x4];
e281682b
SM		 5030 u8 vport_number[0x10];
5031
b4ff3a36 5032 u8 reserved_at_60[0x20];
e281682b
SM		 5033
5034 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5035};
5036
5037struct mlx5_ifc_modify_cq_out_bits {
5038 u8 status[0x8];
b4ff3a36 5039 u8 reserved_at_8[0x18];
e281682b
SM		 5040
5041 u8 syndrome[0x20];
5042
b4ff3a36 5043 u8 reserved_at_40[0x40];
e281682b
SM		 5044};
5045
5046enum {
5047 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
5048 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
5049};
5050
5051struct mlx5_ifc_modify_cq_in_bits {
5052 u8 opcode[0x10];
b4ff3a36 5053 u8 reserved_at_10[0x10];
e281682b 5054
b4ff3a36 5055 u8 reserved_at_20[0x10];
e281682b
SM		 5056 u8 op_mod[0x10];
5057
b4ff3a36 5058 u8 reserved_at_40[0x8];
e281682b
SM		 5059 u8 cqn[0x18];
5060
5061 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5062
5063 struct mlx5_ifc_cqc_bits cq_context;
5064
b4ff3a36 5065 u8 reserved_at_280[0x600];
e281682b
SM		 5066
5067 u8 pas[0][0x40];
5068};
5069
5070struct mlx5_ifc_modify_cong_status_out_bits {
5071 u8 status[0x8];
b4ff3a36 5072 u8 reserved_at_8[0x18];
e281682b
SM		 5073
5074 u8 syndrome[0x20];
5075
b4ff3a36 5076 u8 reserved_at_40[0x40];
e281682b
SM		 5077};
5078
5079struct mlx5_ifc_modify_cong_status_in_bits {
5080 u8 opcode[0x10];
b4ff3a36 5081 u8 reserved_at_10[0x10];
e281682b 5082
b4ff3a36 5083 u8 reserved_at_20[0x10];
e281682b
SM		 5084 u8 op_mod[0x10];
5085
b4ff3a36 5086 u8 reserved_at_40[0x18];
e281682b
SM		 5087 u8 priority[0x4];
5088 u8 cong_protocol[0x4];
5089
5090 u8 enable[0x1];
5091 u8 tag_enable[0x1];
b4ff3a36 5092 u8 reserved_at_62[0x1e];
e281682b
SM		 5093};
5094
5095struct mlx5_ifc_modify_cong_params_out_bits {
5096 u8 status[0x8];
b4ff3a36 5097 u8 reserved_at_8[0x18];
e281682b
SM		 5098
5099 u8 syndrome[0x20];
5100
b4ff3a36 5101 u8 reserved_at_40[0x40];
e281682b
SM		 5102};
5103
5104struct mlx5_ifc_modify_cong_params_in_bits {
5105 u8 opcode[0x10];
b4ff3a36 5106 u8 reserved_at_10[0x10];
e281682b 5107
b4ff3a36 5108 u8 reserved_at_20[0x10];
e281682b
SM		 5109 u8 op_mod[0x10];
5110
b4ff3a36 5111 u8 reserved_at_40[0x1c];
e281682b
SM		 5112 u8 cong_protocol[0x4];
5113
5114 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5115
b4ff3a36 5116 u8 reserved_at_80[0x80];
e281682b
SM		 5117
5118 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5119};
5120
5121struct mlx5_ifc_manage_pages_out_bits {
5122 u8 status[0x8];
b4ff3a36 5123 u8 reserved_at_8[0x18];
e281682b
SM		 5124
5125 u8 syndrome[0x20];
5126
5127 u8 output_num_entries[0x20];
5128
b4ff3a36 5129 u8 reserved_at_60[0x20];
e281682b
SM		 5130
5131 u8 pas[0][0x40];
5132};
5133
5134enum {
5135 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
5136 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
5137 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
5138};
5139
5140struct mlx5_ifc_manage_pages_in_bits {
5141 u8 opcode[0x10];
b4ff3a36 5142 u8 reserved_at_10[0x10];
e281682b 5143
b4ff3a36 5144 u8 reserved_at_20[0x10];
e281682b
SM		 5145 u8 op_mod[0x10];
5146
b4ff3a36 5147 u8 reserved_at_40[0x10];
e281682b
SM		 5148 u8 function_id[0x10];
5149
5150 u8 input_num_entries[0x20];
5151
5152 u8 pas[0][0x40];
5153};
5154
5155struct mlx5_ifc_mad_ifc_out_bits {
5156 u8 status[0x8];
b4ff3a36 5157 u8 reserved_at_8[0x18];
e281682b
SM		 5158
5159 u8 syndrome[0x20];
5160
b4ff3a36 5161 u8 reserved_at_40[0x40];
e281682b
SM		 5162
5163 u8 response_mad_packet[256][0x8];
5164};
5165
5166struct mlx5_ifc_mad_ifc_in_bits {
5167 u8 opcode[0x10];
b4ff3a36 5168 u8 reserved_at_10[0x10];
e281682b 5169
b4ff3a36 5170 u8 reserved_at_20[0x10];
e281682b
SM		 5171 u8 op_mod[0x10];
5172
5173 u8 remote_lid[0x10];
b4ff3a36 5174 u8 reserved_at_50[0x8];
e281682b
SM		 5175 u8 port[0x8];
5176
b4ff3a36 5177 u8 reserved_at_60[0x20];
e281682b
SM		 5178
5179 u8 mad[256][0x8];
5180};
5181
5182struct mlx5_ifc_init_hca_out_bits {
5183 u8 status[0x8];
b4ff3a36 5184 u8 reserved_at_8[0x18];
e281682b
SM		 5185
5186 u8 syndrome[0x20];
5187
b4ff3a36 5188 u8 reserved_at_40[0x40];
e281682b
SM		 5189};
5190
5191struct mlx5_ifc_init_hca_in_bits {
5192 u8 opcode[0x10];
b4ff3a36 5193 u8 reserved_at_10[0x10];
e281682b 5194
b4ff3a36 5195 u8 reserved_at_20[0x10];
e281682b
SM		 5196 u8 op_mod[0x10];
5197
b4ff3a36 5198 u8 reserved_at_40[0x40];
e281682b
SM		 5199};
5200
5201struct mlx5_ifc_init2rtr_qp_out_bits {
5202 u8 status[0x8];
b4ff3a36 5203 u8 reserved_at_8[0x18];
e281682b
SM		 5204
5205 u8 syndrome[0x20];
5206
b4ff3a36 5207 u8 reserved_at_40[0x40];
e281682b
SM		 5208};
5209
5210struct mlx5_ifc_init2rtr_qp_in_bits {
5211 u8 opcode[0x10];
b4ff3a36 5212 u8 reserved_at_10[0x10];
e281682b 5213
b4ff3a36 5214 u8 reserved_at_20[0x10];
e281682b
SM		 5215 u8 op_mod[0x10];
5216
b4ff3a36 5217 u8 reserved_at_40[0x8];
e281682b
SM		 5218 u8 qpn[0x18];
5219
b4ff3a36 5220 u8 reserved_at_60[0x20];
e281682b
SM		 5221
5222 u8 opt_param_mask[0x20];
5223
b4ff3a36 5224 u8 reserved_at_a0[0x20];
e281682b
SM		 5225
5226 struct mlx5_ifc_qpc_bits qpc;
5227
b4ff3a36 5228 u8 reserved_at_800[0x80];
e281682b
SM		 5229};
5230
5231struct mlx5_ifc_init2init_qp_out_bits {
5232 u8 status[0x8];
b4ff3a36 5233 u8 reserved_at_8[0x18];
e281682b
SM		 5234
5235 u8 syndrome[0x20];
5236
b4ff3a36 5237 u8 reserved_at_40[0x40];
e281682b
SM		 5238};
5239
5240struct mlx5_ifc_init2init_qp_in_bits {
5241 u8 opcode[0x10];
b4ff3a36 5242 u8 reserved_at_10[0x10];
e281682b 5243
b4ff3a36 5244 u8 reserved_at_20[0x10];
e281682b
SM		 5245 u8 op_mod[0x10];
5246
b4ff3a36 5247 u8 reserved_at_40[0x8];
e281682b
SM		 5248 u8 qpn[0x18];
5249
b4ff3a36 5250 u8 reserved_at_60[0x20];
e281682b
SM		 5251
5252 u8 opt_param_mask[0x20];
5253
b4ff3a36 5254 u8 reserved_at_a0[0x20];
e281682b
SM		 5255
5256 struct mlx5_ifc_qpc_bits qpc;
5257
b4ff3a36 5258 u8 reserved_at_800[0x80];
e281682b
SM		 5259};
5260
5261struct mlx5_ifc_get_dropped_packet_log_out_bits {
5262 u8 status[0x8];
b4ff3a36 5263 u8 reserved_at_8[0x18];
e281682b
SM		 5264
5265 u8 syndrome[0x20];
5266
b4ff3a36 5267 u8 reserved_at_40[0x40];
e281682b
SM		 5268
5269 u8 packet_headers_log[128][0x8];
5270
5271 u8 packet_syndrome[64][0x8];
5272};
5273
5274struct mlx5_ifc_get_dropped_packet_log_in_bits {
5275 u8 opcode[0x10];
b4ff3a36 5276 u8 reserved_at_10[0x10];
e281682b 5277
b4ff3a36 5278 u8 reserved_at_20[0x10];
e281682b
SM		 5279 u8 op_mod[0x10];
5280
b4ff3a36 5281 u8 reserved_at_40[0x40];
e281682b
SM		 5282};
5283
5284struct mlx5_ifc_gen_eqe_in_bits {
5285 u8 opcode[0x10];
b4ff3a36 5286 u8 reserved_at_10[0x10];
e281682b 5287
b4ff3a36 5288 u8 reserved_at_20[0x10];
e281682b
SM		 5289 u8 op_mod[0x10];
5290
b4ff3a36 5291 u8 reserved_at_40[0x18];
e281682b
SM		 5292 u8 eq_number[0x8];
5293
b4ff3a36 5294 u8 reserved_at_60[0x20];
e281682b
SM		 5295
5296 u8 eqe[64][0x8];
5297};
5298
5299struct mlx5_ifc_gen_eq_out_bits {
5300 u8 status[0x8];
b4ff3a36 5301 u8 reserved_at_8[0x18];
e281682b
SM		 5302
5303 u8 syndrome[0x20];
5304
b4ff3a36 5305 u8 reserved_at_40[0x40];
e281682b
SM		 5306};
5307
5308struct mlx5_ifc_enable_hca_out_bits {
5309 u8 status[0x8];
b4ff3a36 5310 u8 reserved_at_8[0x18];
e281682b
SM		 5311
5312 u8 syndrome[0x20];
5313
b4ff3a36 5314 u8 reserved_at_40[0x20];
e281682b
SM		 5315};
5316
5317struct mlx5_ifc_enable_hca_in_bits {
5318 u8 opcode[0x10];
b4ff3a36 5319 u8 reserved_at_10[0x10];
e281682b 5320
b4ff3a36 5321 u8 reserved_at_20[0x10];
e281682b
SM		 5322 u8 op_mod[0x10];
5323
b4ff3a36 5324 u8 reserved_at_40[0x10];
e281682b
SM		 5325 u8 function_id[0x10];
5326
b4ff3a36 5327 u8 reserved_at_60[0x20];
e281682b
SM		 5328};
5329
5330struct mlx5_ifc_drain_dct_out_bits {
5331 u8 status[0x8];
b4ff3a36 5332 u8 reserved_at_8[0x18];
e281682b
SM		 5333
5334 u8 syndrome[0x20];
5335
b4ff3a36 5336 u8 reserved_at_40[0x40];
e281682b
SM		 5337};
5338
5339struct mlx5_ifc_drain_dct_in_bits {
5340 u8 opcode[0x10];
b4ff3a36 5341 u8 reserved_at_10[0x10];
e281682b 5342
b4ff3a36 5343 u8 reserved_at_20[0x10];
e281682b
SM		 5344 u8 op_mod[0x10];
5345
b4ff3a36 5346 u8 reserved_at_40[0x8];
e281682b
SM		 5347 u8 dctn[0x18];
5348
b4ff3a36 5349 u8 reserved_at_60[0x20];
e281682b
SM		 5350};
5351
5352struct mlx5_ifc_disable_hca_out_bits {
5353 u8 status[0x8];
b4ff3a36 5354 u8 reserved_at_8[0x18];
e281682b
SM		 5355
5356 u8 syndrome[0x20];
5357
b4ff3a36 5358 u8 reserved_at_40[0x20];
e281682b
SM		 5359};
5360
5361struct mlx5_ifc_disable_hca_in_bits {
5362 u8 opcode[0x10];
b4ff3a36 5363 u8 reserved_at_10[0x10];
e281682b 5364
b4ff3a36 5365 u8 reserved_at_20[0x10];
e281682b
SM		 5366 u8 op_mod[0x10];
5367
b4ff3a36 5368 u8 reserved_at_40[0x10];
e281682b
SM		 5369 u8 function_id[0x10];
5370
b4ff3a36 5371 u8 reserved_at_60[0x20];
e281682b
SM		 5372};
5373
5374struct mlx5_ifc_detach_from_mcg_out_bits {
5375 u8 status[0x8];
b4ff3a36 5376 u8 reserved_at_8[0x18];
e281682b
SM		 5377
5378 u8 syndrome[0x20];
5379
b4ff3a36 5380 u8 reserved_at_40[0x40];
e281682b
SM		 5381};
5382
5383struct mlx5_ifc_detach_from_mcg_in_bits {
5384 u8 opcode[0x10];
b4ff3a36 5385 u8 reserved_at_10[0x10];
e281682b 5386
b4ff3a36 5387 u8 reserved_at_20[0x10];
e281682b
SM		 5388 u8 op_mod[0x10];
5389
b4ff3a36 5390 u8 reserved_at_40[0x8];
e281682b
SM		 5391 u8 qpn[0x18];
5392
b4ff3a36 5393 u8 reserved_at_60[0x20];
e281682b
SM		 5394
5395 u8 multicast_gid[16][0x8];
5396};
5397
7486216b
SM		 5398struct mlx5_ifc_destroy_xrq_out_bits {
5399 u8 status[0x8];
5400 u8 reserved_at_8[0x18];
5401
5402 u8 syndrome[0x20];
5403
5404 u8 reserved_at_40[0x40];
5405};
5406
5407struct mlx5_ifc_destroy_xrq_in_bits {
5408 u8 opcode[0x10];
5409 u8 reserved_at_10[0x10];
5410
5411 u8 reserved_at_20[0x10];
5412 u8 op_mod[0x10];
5413
5414 u8 reserved_at_40[0x8];
5415 u8 xrqn[0x18];
5416
5417 u8 reserved_at_60[0x20];
5418};
5419
e281682b
SM		 5420struct mlx5_ifc_destroy_xrc_srq_out_bits {
5421 u8 status[0x8];
b4ff3a36 5422 u8 reserved_at_8[0x18];
e281682b
SM		 5423
5424 u8 syndrome[0x20];
5425
b4ff3a36 5426 u8 reserved_at_40[0x40];
e281682b
SM		 5427};
5428
5429struct mlx5_ifc_destroy_xrc_srq_in_bits {
5430 u8 opcode[0x10];
b4ff3a36 5431 u8 reserved_at_10[0x10];
e281682b 5432
b4ff3a36 5433 u8 reserved_at_20[0x10];
e281682b
SM		 5434 u8 op_mod[0x10];
5435
b4ff3a36 5436 u8 reserved_at_40[0x8];
e281682b
SM		 5437 u8 xrc_srqn[0x18];
5438
b4ff3a36 5439 u8 reserved_at_60[0x20];
e281682b
SM		 5440};
5441
5442struct mlx5_ifc_destroy_tis_out_bits {
5443 u8 status[0x8];
b4ff3a36 5444 u8 reserved_at_8[0x18];
e281682b
SM		 5445
5446 u8 syndrome[0x20];
5447
b4ff3a36 5448 u8 reserved_at_40[0x40];
e281682b
SM		 5449};
5450
5451struct mlx5_ifc_destroy_tis_in_bits {
5452 u8 opcode[0x10];
b4ff3a36 5453 u8 reserved_at_10[0x10];
e281682b 5454
b4ff3a36 5455 u8 reserved_at_20[0x10];
e281682b
SM		 5456 u8 op_mod[0x10];
5457
b4ff3a36 5458 u8 reserved_at_40[0x8];
e281682b
SM		 5459 u8 tisn[0x18];
5460
b4ff3a36 5461 u8 reserved_at_60[0x20];
e281682b
SM		 5462};
5463
5464struct mlx5_ifc_destroy_tir_out_bits {
5465 u8 status[0x8];
b4ff3a36 5466 u8 reserved_at_8[0x18];
e281682b
SM		 5467
5468 u8 syndrome[0x20];
5469
b4ff3a36 5470 u8 reserved_at_40[0x40];
e281682b
SM		 5471};
5472
5473struct mlx5_ifc_destroy_tir_in_bits {
5474 u8 opcode[0x10];
b4ff3a36 5475 u8 reserved_at_10[0x10];
e281682b 5476
b4ff3a36 5477 u8 reserved_at_20[0x10];
e281682b
SM		 5478 u8 op_mod[0x10];
5479
b4ff3a36 5480 u8 reserved_at_40[0x8];
e281682b
SM		 5481 u8 tirn[0x18];
5482
b4ff3a36 5483 u8 reserved_at_60[0x20];
e281682b
SM		 5484};
5485
5486struct mlx5_ifc_destroy_srq_out_bits {
5487 u8 status[0x8];
b4ff3a36 5488 u8 reserved_at_8[0x18];
e281682b
SM		 5489
5490 u8 syndrome[0x20];
5491
b4ff3a36 5492 u8 reserved_at_40[0x40];
e281682b
SM		 5493};
5494
5495struct mlx5_ifc_destroy_srq_in_bits {
5496 u8 opcode[0x10];
b4ff3a36 5497 u8 reserved_at_10[0x10];
e281682b 5498
b4ff3a36 5499 u8 reserved_at_20[0x10];
e281682b
SM		 5500 u8 op_mod[0x10];
5501
b4ff3a36 5502 u8 reserved_at_40[0x8];
e281682b
SM		 5503 u8 srqn[0x18];
5504
b4ff3a36 5505 u8 reserved_at_60[0x20];
e281682b
SM		 5506};
5507
5508struct mlx5_ifc_destroy_sq_out_bits {
5509 u8 status[0x8];
b4ff3a36 5510 u8 reserved_at_8[0x18];
e281682b
SM		 5511
5512 u8 syndrome[0x20];
5513
b4ff3a36 5514 u8 reserved_at_40[0x40];
e281682b
SM		 5515};
5516
5517struct mlx5_ifc_destroy_sq_in_bits {
5518 u8 opcode[0x10];
b4ff3a36 5519 u8 reserved_at_10[0x10];
e281682b 5520
b4ff3a36 5521 u8 reserved_at_20[0x10];
e281682b
SM		 5522 u8 op_mod[0x10];
5523
b4ff3a36 5524 u8 reserved_at_40[0x8];
e281682b
SM		 5525 u8 sqn[0x18];
5526
b4ff3a36 5527 u8 reserved_at_60[0x20];
e281682b
SM		 5528};
5529
813f8540
MHY		 5530struct mlx5_ifc_destroy_scheduling_element_out_bits {
5531 u8 status[0x8];
5532 u8 reserved_at_8[0x18];
5533
5534 u8 syndrome[0x20];
5535
5536 u8 reserved_at_40[0x1c0];
5537};
5538
5539struct mlx5_ifc_destroy_scheduling_element_in_bits {
5540 u8 opcode[0x10];
5541 u8 reserved_at_10[0x10];
5542
5543 u8 reserved_at_20[0x10];
5544 u8 op_mod[0x10];
5545
5546 u8 scheduling_hierarchy[0x8];
5547 u8 reserved_at_48[0x18];
5548
5549 u8 scheduling_element_id[0x20];
5550
5551 u8 reserved_at_80[0x180];
5552};
5553
e281682b
SM		 5554struct mlx5_ifc_destroy_rqt_out_bits {
5555 u8 status[0x8];
b4ff3a36 5556 u8 reserved_at_8[0x18];
e281682b
SM		 5557
5558 u8 syndrome[0x20];
5559
b4ff3a36 5560 u8 reserved_at_40[0x40];
e281682b
SM		 5561};
5562
5563struct mlx5_ifc_destroy_rqt_in_bits {
5564 u8 opcode[0x10];
b4ff3a36 5565 u8 reserved_at_10[0x10];
e281682b 5566
b4ff3a36 5567 u8 reserved_at_20[0x10];
e281682b
SM		 5568 u8 op_mod[0x10];
5569
b4ff3a36 5570 u8 reserved_at_40[0x8];
e281682b
SM		 5571 u8 rqtn[0x18];
5572
b4ff3a36 5573 u8 reserved_at_60[0x20];
e281682b
SM		 5574};
5575
5576struct mlx5_ifc_destroy_rq_out_bits {
5577 u8 status[0x8];
b4ff3a36 5578 u8 reserved_at_8[0x18];
e281682b
SM		 5579
5580 u8 syndrome[0x20];
5581
b4ff3a36 5582 u8 reserved_at_40[0x40];
e281682b
SM		 5583};
5584
5585struct mlx5_ifc_destroy_rq_in_bits {
5586 u8 opcode[0x10];
b4ff3a36 5587 u8 reserved_at_10[0x10];
e281682b 5588
b4ff3a36 5589 u8 reserved_at_20[0x10];
e281682b
SM		 5590 u8 op_mod[0x10];
5591
b4ff3a36 5592 u8 reserved_at_40[0x8];
e281682b
SM		 5593 u8 rqn[0x18];
5594
b4ff3a36 5595 u8 reserved_at_60[0x20];
e281682b
SM		 5596};
5597
5598struct mlx5_ifc_destroy_rmp_out_bits {
5599 u8 status[0x8];
b4ff3a36 5600 u8 reserved_at_8[0x18];
e281682b
SM		 5601
5602 u8 syndrome[0x20];
5603
b4ff3a36 5604 u8 reserved_at_40[0x40];
e281682b
SM		 5605};
5606
5607struct mlx5_ifc_destroy_rmp_in_bits {
5608 u8 opcode[0x10];
b4ff3a36 5609 u8 reserved_at_10[0x10];
e281682b 5610
b4ff3a36 5611 u8 reserved_at_20[0x10];
e281682b
SM		 5612 u8 op_mod[0x10];
5613
b4ff3a36 5614 u8 reserved_at_40[0x8];
e281682b
SM		 5615 u8 rmpn[0x18];
5616
b4ff3a36 5617 u8 reserved_at_60[0x20];
e281682b
SM		 5618};
5619
5620struct mlx5_ifc_destroy_qp_out_bits {
5621 u8 status[0x8];
b4ff3a36 5622 u8 reserved_at_8[0x18];
e281682b
SM		 5623
5624 u8 syndrome[0x20];
5625
b4ff3a36 5626 u8 reserved_at_40[0x40];
e281682b
SM		 5627};
5628
5629struct mlx5_ifc_destroy_qp_in_bits {
5630 u8 opcode[0x10];
b4ff3a36 5631 u8 reserved_at_10[0x10];
e281682b 5632
b4ff3a36 5633 u8 reserved_at_20[0x10];
e281682b
SM		 5634 u8 op_mod[0x10];
5635
b4ff3a36 5636 u8 reserved_at_40[0x8];
e281682b
SM		 5637 u8 qpn[0x18];
5638
b4ff3a36 5639 u8 reserved_at_60[0x20];
e281682b
SM		 5640};
5641
5642struct mlx5_ifc_destroy_psv_out_bits {
5643 u8 status[0x8];
b4ff3a36 5644 u8 reserved_at_8[0x18];
e281682b
SM		 5645
5646 u8 syndrome[0x20];
5647
b4ff3a36 5648 u8 reserved_at_40[0x40];
e281682b
SM		 5649};
5650
5651struct mlx5_ifc_destroy_psv_in_bits {
5652 u8 opcode[0x10];
b4ff3a36 5653 u8 reserved_at_10[0x10];
e281682b 5654
b4ff3a36 5655 u8 reserved_at_20[0x10];
e281682b
SM		 5656 u8 op_mod[0x10];
5657
b4ff3a36 5658 u8 reserved_at_40[0x8];
e281682b
SM		 5659 u8 psvn[0x18];
5660
b4ff3a36 5661 u8 reserved_at_60[0x20];
e281682b
SM		 5662};
5663
5664struct mlx5_ifc_destroy_mkey_out_bits {
5665 u8 status[0x8];
b4ff3a36 5666 u8 reserved_at_8[0x18];
e281682b
SM		 5667
5668 u8 syndrome[0x20];
5669
b4ff3a36 5670 u8 reserved_at_40[0x40];
e281682b
SM		 5671};
5672
5673struct mlx5_ifc_destroy_mkey_in_bits {
5674 u8 opcode[0x10];
b4ff3a36 5675 u8 reserved_at_10[0x10];
e281682b 5676
b4ff3a36 5677 u8 reserved_at_20[0x10];
e281682b
SM		 5678 u8 op_mod[0x10];
5679
b4ff3a36 5680 u8 reserved_at_40[0x8];
e281682b
SM		 5681 u8 mkey_index[0x18];
5682
b4ff3a36 5683 u8 reserved_at_60[0x20];
e281682b
SM		 5684};
5685
5686struct mlx5_ifc_destroy_flow_table_out_bits {
5687 u8 status[0x8];
b4ff3a36 5688 u8 reserved_at_8[0x18];
e281682b
SM		 5689
5690 u8 syndrome[0x20];
5691
b4ff3a36 5692 u8 reserved_at_40[0x40];
e281682b
SM		 5693};
5694
5695struct mlx5_ifc_destroy_flow_table_in_bits {
5696 u8 opcode[0x10];
b4ff3a36 5697 u8 reserved_at_10[0x10];
e281682b 5698
b4ff3a36 5699 u8 reserved_at_20[0x10];
e281682b
SM		 5700 u8 op_mod[0x10];
5701
7d5e1423
SM		 5702 u8 other_vport[0x1];
5703 u8 reserved_at_41[0xf];
5704 u8 vport_number[0x10];
5705
5706 u8 reserved_at_60[0x20];
e281682b
SM		 5707
5708 u8 table_type[0x8];
b4ff3a36 5709 u8 reserved_at_88[0x18];
e281682b 5710
b4ff3a36 5711 u8 reserved_at_a0[0x8];
e281682b
SM		 5712 u8 table_id[0x18];
5713
b4ff3a36 5714 u8 reserved_at_c0[0x140];
e281682b
SM		 5715};
5716
5717struct mlx5_ifc_destroy_flow_group_out_bits {
5718 u8 status[0x8];
b4ff3a36 5719 u8 reserved_at_8[0x18];
e281682b
SM		 5720
5721 u8 syndrome[0x20];
5722
b4ff3a36 5723 u8 reserved_at_40[0x40];
e281682b
SM		 5724};
5725
5726struct mlx5_ifc_destroy_flow_group_in_bits {
5727 u8 opcode[0x10];
b4ff3a36 5728 u8 reserved_at_10[0x10];
e281682b 5729
b4ff3a36 5730 u8 reserved_at_20[0x10];
e281682b
SM		 5731 u8 op_mod[0x10];
5732
7d5e1423
SM		 5733 u8 other_vport[0x1];
5734 u8 reserved_at_41[0xf];
5735 u8 vport_number[0x10];
5736
5737 u8 reserved_at_60[0x20];
e281682b
SM		 5738
5739 u8 table_type[0x8];
b4ff3a36 5740 u8 reserved_at_88[0x18];
e281682b 5741
b4ff3a36 5742 u8 reserved_at_a0[0x8];
e281682b
SM		 5743 u8 table_id[0x18];
5744
5745 u8 group_id[0x20];
5746
b4ff3a36 5747 u8 reserved_at_e0[0x120];
e281682b
SM		 5748};
5749
5750struct mlx5_ifc_destroy_eq_out_bits {
5751 u8 status[0x8];
b4ff3a36 5752 u8 reserved_at_8[0x18];
e281682b
SM		 5753
5754 u8 syndrome[0x20];
5755
b4ff3a36 5756 u8 reserved_at_40[0x40];
e281682b
SM		 5757};
5758
5759struct mlx5_ifc_destroy_eq_in_bits {
5760 u8 opcode[0x10];
b4ff3a36 5761 u8 reserved_at_10[0x10];
e281682b 5762
b4ff3a36 5763 u8 reserved_at_20[0x10];
e281682b
SM		 5764 u8 op_mod[0x10];
5765
b4ff3a36 5766 u8 reserved_at_40[0x18];
e281682b
SM		 5767 u8 eq_number[0x8];
5768
b4ff3a36 5769 u8 reserved_at_60[0x20];
e281682b
SM		 5770};
5771
5772struct mlx5_ifc_destroy_dct_out_bits {
5773 u8 status[0x8];
b4ff3a36 5774 u8 reserved_at_8[0x18];
e281682b
SM		 5775
5776 u8 syndrome[0x20];
5777
b4ff3a36 5778 u8 reserved_at_40[0x40];
e281682b
SM		 5779};
5780
5781struct mlx5_ifc_destroy_dct_in_bits {
5782 u8 opcode[0x10];
b4ff3a36 5783 u8 reserved_at_10[0x10];
e281682b 5784
b4ff3a36 5785 u8 reserved_at_20[0x10];
e281682b
SM		 5786 u8 op_mod[0x10];
5787
b4ff3a36 5788 u8 reserved_at_40[0x8];
e281682b
SM		 5789 u8 dctn[0x18];
5790
b4ff3a36 5791 u8 reserved_at_60[0x20];
e281682b
SM		 5792};
5793
5794struct mlx5_ifc_destroy_cq_out_bits {
5795 u8 status[0x8];
b4ff3a36 5796 u8 reserved_at_8[0x18];
e281682b
SM		 5797
5798 u8 syndrome[0x20];
5799
b4ff3a36 5800 u8 reserved_at_40[0x40];
e281682b
SM		 5801};
5802
5803struct mlx5_ifc_destroy_cq_in_bits {
5804 u8 opcode[0x10];
b4ff3a36 5805 u8 reserved_at_10[0x10];
e281682b 5806
b4ff3a36 5807 u8 reserved_at_20[0x10];
e281682b
SM		 5808 u8 op_mod[0x10];
5809
b4ff3a36 5810 u8 reserved_at_40[0x8];
e281682b
SM		 5811 u8 cqn[0x18];
5812
b4ff3a36 5813 u8 reserved_at_60[0x20];
e281682b
SM		 5814};
5815
5816struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
5817 u8 status[0x8];
b4ff3a36 5818 u8 reserved_at_8[0x18];
e281682b
SM		 5819
5820 u8 syndrome[0x20];
5821
b4ff3a36 5822 u8 reserved_at_40[0x40];
e281682b
SM		 5823};
5824
5825struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
5826 u8 opcode[0x10];
b4ff3a36 5827 u8 reserved_at_10[0x10];
e281682b 5828
b4ff3a36 5829 u8 reserved_at_20[0x10];
e281682b
SM		 5830 u8 op_mod[0x10];
5831
b4ff3a36 5832 u8 reserved_at_40[0x20];
e281682b 5833
b4ff3a36 5834 u8 reserved_at_60[0x10];
e281682b
SM		 5835 u8 vxlan_udp_port[0x10];
5836};
5837
5838struct mlx5_ifc_delete_l2_table_entry_out_bits {
5839 u8 status[0x8];
b4ff3a36 5840 u8 reserved_at_8[0x18];
e281682b
SM		 5841
5842 u8 syndrome[0x20];
5843
b4ff3a36 5844 u8 reserved_at_40[0x40];
e281682b
SM		 5845};
5846
5847struct mlx5_ifc_delete_l2_table_entry_in_bits {
5848 u8 opcode[0x10];
b4ff3a36 5849 u8 reserved_at_10[0x10];
e281682b 5850
b4ff3a36 5851 u8 reserved_at_20[0x10];
e281682b
SM		 5852 u8 op_mod[0x10];
5853
b4ff3a36 5854 u8 reserved_at_40[0x60];
e281682b 5855
b4ff3a36 5856 u8 reserved_at_a0[0x8];
e281682b
SM		 5857 u8 table_index[0x18];
5858
b4ff3a36 5859 u8 reserved_at_c0[0x140];
e281682b
SM		 5860};
5861
5862struct mlx5_ifc_delete_fte_out_bits {
5863 u8 status[0x8];
b4ff3a36 5864 u8 reserved_at_8[0x18];
e281682b
SM		 5865
5866 u8 syndrome[0x20];
5867
b4ff3a36 5868 u8 reserved_at_40[0x40];
e281682b
SM		 5869};
5870
5871struct mlx5_ifc_delete_fte_in_bits {
5872 u8 opcode[0x10];
b4ff3a36 5873 u8 reserved_at_10[0x10];
e281682b 5874
b4ff3a36 5875 u8 reserved_at_20[0x10];
e281682b
SM		 5876 u8 op_mod[0x10];
5877
7d5e1423
SM		 5878 u8 other_vport[0x1];
5879 u8 reserved_at_41[0xf];
5880 u8 vport_number[0x10];
5881
5882 u8 reserved_at_60[0x20];
e281682b
SM		 5883
5884 u8 table_type[0x8];
b4ff3a36 5885 u8 reserved_at_88[0x18];
e281682b 5886
b4ff3a36 5887 u8 reserved_at_a0[0x8];
e281682b
SM		 5888 u8 table_id[0x18];
5889
b4ff3a36 5890 u8 reserved_at_c0[0x40];
e281682b
SM		 5891
5892 u8 flow_index[0x20];
5893
b4ff3a36 5894 u8 reserved_at_120[0xe0];
e281682b
SM		 5895};
5896
5897struct mlx5_ifc_dealloc_xrcd_out_bits {
5898 u8 status[0x8];
b4ff3a36 5899 u8 reserved_at_8[0x18];
e281682b
SM		 5900
5901 u8 syndrome[0x20];
5902
b4ff3a36 5903 u8 reserved_at_40[0x40];
e281682b
SM		 5904};
5905
5906struct mlx5_ifc_dealloc_xrcd_in_bits {
5907 u8 opcode[0x10];
b4ff3a36 5908 u8 reserved_at_10[0x10];
e281682b 5909
b4ff3a36 5910 u8 reserved_at_20[0x10];
e281682b
SM		 5911 u8 op_mod[0x10];
5912
b4ff3a36 5913 u8 reserved_at_40[0x8];
e281682b
SM		 5914 u8 xrcd[0x18];
5915
b4ff3a36 5916 u8 reserved_at_60[0x20];
e281682b
SM		 5917};
5918
5919struct mlx5_ifc_dealloc_uar_out_bits {
5920 u8 status[0x8];
b4ff3a36 5921 u8 reserved_at_8[0x18];
e281682b
SM		 5922
5923 u8 syndrome[0x20];
5924
b4ff3a36 5925 u8 reserved_at_40[0x40];
e281682b
SM		 5926};
5927
5928struct mlx5_ifc_dealloc_uar_in_bits {
5929 u8 opcode[0x10];
b4ff3a36 5930 u8 reserved_at_10[0x10];
e281682b 5931
b4ff3a36 5932 u8 reserved_at_20[0x10];
e281682b
SM		 5933 u8 op_mod[0x10];
5934
b4ff3a36 5935 u8 reserved_at_40[0x8];
e281682b
SM		 5936 u8 uar[0x18];
5937
b4ff3a36 5938 u8 reserved_at_60[0x20];
e281682b
SM		 5939};
5940
5941struct mlx5_ifc_dealloc_transport_domain_out_bits {
5942 u8 status[0x8];
b4ff3a36 5943 u8 reserved_at_8[0x18];
e281682b
SM		 5944
5945 u8 syndrome[0x20];
5946
b4ff3a36 5947 u8 reserved_at_40[0x40];
e281682b
SM		 5948};
5949
5950struct mlx5_ifc_dealloc_transport_domain_in_bits {
5951 u8 opcode[0x10];
b4ff3a36 5952 u8 reserved_at_10[0x10];
e281682b 5953
b4ff3a36 5954 u8 reserved_at_20[0x10];
e281682b
SM		 5955 u8 op_mod[0x10];
5956
b4ff3a36 5957 u8 reserved_at_40[0x8];
e281682b
SM		 5958 u8 transport_domain[0x18];
5959
b4ff3a36 5960 u8 reserved_at_60[0x20];
e281682b
SM		 5961};
5962
5963struct mlx5_ifc_dealloc_q_counter_out_bits {
5964 u8 status[0x8];
b4ff3a36 5965 u8 reserved_at_8[0x18];
e281682b
SM		 5966
5967 u8 syndrome[0x20];
5968
b4ff3a36 5969 u8 reserved_at_40[0x40];
e281682b
SM		 5970};
5971
5972struct mlx5_ifc_dealloc_q_counter_in_bits {
5973 u8 opcode[0x10];
b4ff3a36 5974 u8 reserved_at_10[0x10];
e281682b 5975
b4ff3a36 5976 u8 reserved_at_20[0x10];
e281682b
SM		 5977 u8 op_mod[0x10];
5978
b4ff3a36 5979 u8 reserved_at_40[0x18];
e281682b
SM		 5980 u8 counter_set_id[0x8];
5981
b4ff3a36 5982 u8 reserved_at_60[0x20];
e281682b
SM		 5983};
5984
5985struct mlx5_ifc_dealloc_pd_out_bits {
5986 u8 status[0x8];
b4ff3a36 5987 u8 reserved_at_8[0x18];
e281682b
SM		 5988
5989 u8 syndrome[0x20];
5990
b4ff3a36 5991 u8 reserved_at_40[0x40];
e281682b
SM		 5992};
5993
5994struct mlx5_ifc_dealloc_pd_in_bits {
5995 u8 opcode[0x10];
b4ff3a36 5996 u8 reserved_at_10[0x10];
e281682b 5997
b4ff3a36 5998 u8 reserved_at_20[0x10];
e281682b
SM		 5999 u8 op_mod[0x10];
6000
b4ff3a36 6001 u8 reserved_at_40[0x8];
e281682b
SM		 6002 u8 pd[0x18];
6003
b4ff3a36 6004 u8 reserved_at_60[0x20];
e281682b
SM		 6005};
6006
9dc0b289
AV		 6007struct mlx5_ifc_dealloc_flow_counter_out_bits {
6008 u8 status[0x8];
6009 u8 reserved_at_8[0x18];
6010
6011 u8 syndrome[0x20];
6012
6013 u8 reserved_at_40[0x40];
6014};
6015
6016struct mlx5_ifc_dealloc_flow_counter_in_bits {
6017 u8 opcode[0x10];
6018 u8 reserved_at_10[0x10];
6019
6020 u8 reserved_at_20[0x10];
6021 u8 op_mod[0x10];
6022
6023 u8 reserved_at_40[0x10];
6024 u8 flow_counter_id[0x10];
6025
6026 u8 reserved_at_60[0x20];
6027};
6028
7486216b
SM		 6029struct mlx5_ifc_create_xrq_out_bits {
6030 u8 status[0x8];
6031 u8 reserved_at_8[0x18];
6032
6033 u8 syndrome[0x20];
6034
6035 u8 reserved_at_40[0x8];
6036 u8 xrqn[0x18];
6037
6038 u8 reserved_at_60[0x20];
6039};
6040
6041struct mlx5_ifc_create_xrq_in_bits {
6042 u8 opcode[0x10];
6043 u8 reserved_at_10[0x10];
6044
6045 u8 reserved_at_20[0x10];
6046 u8 op_mod[0x10];
6047
6048 u8 reserved_at_40[0x40];
6049
6050 struct mlx5_ifc_xrqc_bits xrq_context;
6051};
6052
e281682b
SM		 6053struct mlx5_ifc_create_xrc_srq_out_bits {
6054 u8 status[0x8];
b4ff3a36 6055 u8 reserved_at_8[0x18];
e281682b
SM		 6056
6057 u8 syndrome[0x20];
6058
b4ff3a36 6059 u8 reserved_at_40[0x8];
e281682b
SM		 6060 u8 xrc_srqn[0x18];
6061
b4ff3a36 6062 u8 reserved_at_60[0x20];
e281682b
SM		 6063};
6064
6065struct mlx5_ifc_create_xrc_srq_in_bits {
6066 u8 opcode[0x10];
b4ff3a36 6067 u8 reserved_at_10[0x10];
e281682b 6068
b4ff3a36 6069 u8 reserved_at_20[0x10];
e281682b
SM		 6070 u8 op_mod[0x10];
6071
b4ff3a36 6072 u8 reserved_at_40[0x40];
e281682b
SM		 6073
6074 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6075
b4ff3a36 6076 u8 reserved_at_280[0x600];
e281682b
SM		 6077
6078 u8 pas[0][0x40];
6079};
6080
6081struct mlx5_ifc_create_tis_out_bits {
6082 u8 status[0x8];
b4ff3a36 6083 u8 reserved_at_8[0x18];
e281682b
SM		 6084
6085 u8 syndrome[0x20];
6086
b4ff3a36 6087 u8 reserved_at_40[0x8];
e281682b
SM		 6088 u8 tisn[0x18];
6089
b4ff3a36 6090 u8 reserved_at_60[0x20];
e281682b
SM		 6091};
6092
6093struct mlx5_ifc_create_tis_in_bits {
6094 u8 opcode[0x10];
b4ff3a36 6095 u8 reserved_at_10[0x10];
e281682b 6096
b4ff3a36 6097 u8 reserved_at_20[0x10];
e281682b
SM		 6098 u8 op_mod[0x10];
6099
b4ff3a36 6100 u8 reserved_at_40[0xc0];
e281682b
SM		 6101
6102 struct mlx5_ifc_tisc_bits ctx;
6103};
6104
6105struct mlx5_ifc_create_tir_out_bits {
6106 u8 status[0x8];
b4ff3a36 6107 u8 reserved_at_8[0x18];
e281682b
SM		 6108
6109 u8 syndrome[0x20];
6110
b4ff3a36 6111 u8 reserved_at_40[0x8];
e281682b
SM		 6112 u8 tirn[0x18];
6113
b4ff3a36 6114 u8 reserved_at_60[0x20];
e281682b
SM		 6115};
6116
6117struct mlx5_ifc_create_tir_in_bits {
6118 u8 opcode[0x10];
b4ff3a36 6119 u8 reserved_at_10[0x10];
e281682b 6120
b4ff3a36 6121 u8 reserved_at_20[0x10];
e281682b
SM		 6122 u8 op_mod[0x10];
6123
b4ff3a36 6124 u8 reserved_at_40[0xc0];
e281682b
SM		 6125
6126 struct mlx5_ifc_tirc_bits ctx;
6127};
6128
6129struct mlx5_ifc_create_srq_out_bits {
6130 u8 status[0x8];
b4ff3a36 6131 u8 reserved_at_8[0x18];
e281682b
SM		 6132
6133 u8 syndrome[0x20];
6134
b4ff3a36 6135 u8 reserved_at_40[0x8];
e281682b
SM		 6136 u8 srqn[0x18];
6137
b4ff3a36 6138 u8 reserved_at_60[0x20];
e281682b
SM		 6139};
6140
6141struct mlx5_ifc_create_srq_in_bits {
6142 u8 opcode[0x10];
b4ff3a36 6143 u8 reserved_at_10[0x10];
e281682b 6144
b4ff3a36 6145 u8 reserved_at_20[0x10];
e281682b
SM		 6146 u8 op_mod[0x10];
6147
b4ff3a36 6148 u8 reserved_at_40[0x40];
e281682b
SM		 6149
6150 struct mlx5_ifc_srqc_bits srq_context_entry;
6151
b4ff3a36 6152 u8 reserved_at_280[0x600];
e281682b
SM		 6153
6154 u8 pas[0][0x40];
6155};
6156
6157struct mlx5_ifc_create_sq_out_bits {
6158 u8 status[0x8];
b4ff3a36 6159 u8 reserved_at_8[0x18];
e281682b
SM		 6160
6161 u8 syndrome[0x20];
6162
b4ff3a36 6163 u8 reserved_at_40[0x8];
e281682b
SM		 6164 u8 sqn[0x18];
6165
b4ff3a36 6166 u8 reserved_at_60[0x20];
e281682b
SM		 6167};
6168
6169struct mlx5_ifc_create_sq_in_bits {
6170 u8 opcode[0x10];
b4ff3a36 6171 u8 reserved_at_10[0x10];
e281682b 6172
b4ff3a36 6173 u8 reserved_at_20[0x10];
e281682b
SM		 6174 u8 op_mod[0x10];
6175
b4ff3a36 6176 u8 reserved_at_40[0xc0];
e281682b
SM		 6177
6178 struct mlx5_ifc_sqc_bits ctx;
6179};
6180
813f8540
MHY		 6181struct mlx5_ifc_create_scheduling_element_out_bits {
6182 u8 status[0x8];
6183 u8 reserved_at_8[0x18];
6184
6185 u8 syndrome[0x20];
6186
6187 u8 reserved_at_40[0x40];
6188
6189 u8 scheduling_element_id[0x20];
6190
6191 u8 reserved_at_a0[0x160];
6192};
6193
6194struct mlx5_ifc_create_scheduling_element_in_bits {
6195 u8 opcode[0x10];
6196 u8 reserved_at_10[0x10];
6197
6198 u8 reserved_at_20[0x10];
6199 u8 op_mod[0x10];
6200
6201 u8 scheduling_hierarchy[0x8];
6202 u8 reserved_at_48[0x18];
6203
6204 u8 reserved_at_60[0xa0];
6205
6206 struct mlx5_ifc_scheduling_context_bits scheduling_context;
6207
6208 u8 reserved_at_300[0x100];
6209};
6210
e281682b
SM		 6211struct mlx5_ifc_create_rqt_out_bits {
6212 u8 status[0x8];
b4ff3a36 6213 u8 reserved_at_8[0x18];
e281682b
SM		 6214
6215 u8 syndrome[0x20];
6216
b4ff3a36 6217 u8 reserved_at_40[0x8];
e281682b
SM		 6218 u8 rqtn[0x18];
6219
b4ff3a36 6220 u8 reserved_at_60[0x20];
e281682b
SM		 6221};
6222
6223struct mlx5_ifc_create_rqt_in_bits {
6224 u8 opcode[0x10];
b4ff3a36 6225 u8 reserved_at_10[0x10];
e281682b 6226
b4ff3a36 6227 u8 reserved_at_20[0x10];
e281682b
SM		 6228 u8 op_mod[0x10];
6229
b4ff3a36 6230 u8 reserved_at_40[0xc0];
e281682b
SM		 6231
6232 struct mlx5_ifc_rqtc_bits rqt_context;
6233};
6234
6235struct mlx5_ifc_create_rq_out_bits {
6236 u8 status[0x8];
b4ff3a36 6237 u8 reserved_at_8[0x18];
e281682b
SM		 6238
6239 u8 syndrome[0x20];
6240
b4ff3a36 6241 u8 reserved_at_40[0x8];
e281682b
SM		 6242 u8 rqn[0x18];
6243
b4ff3a36 6244 u8 reserved_at_60[0x20];
e281682b
SM		 6245};
6246
6247struct mlx5_ifc_create_rq_in_bits {
6248 u8 opcode[0x10];
b4ff3a36 6249 u8 reserved_at_10[0x10];
e281682b 6250
b4ff3a36 6251 u8 reserved_at_20[0x10];
e281682b
SM		 6252 u8 op_mod[0x10];
6253
b4ff3a36 6254 u8 reserved_at_40[0xc0];
e281682b
SM		 6255
6256 struct mlx5_ifc_rqc_bits ctx;
6257};
6258
6259struct mlx5_ifc_create_rmp_out_bits {
6260 u8 status[0x8];
b4ff3a36 6261 u8 reserved_at_8[0x18];
e281682b
SM		 6262
6263 u8 syndrome[0x20];
6264
b4ff3a36 6265 u8 reserved_at_40[0x8];
e281682b
SM		 6266 u8 rmpn[0x18];
6267
b4ff3a36 6268 u8 reserved_at_60[0x20];
e281682b
SM		 6269};
6270
6271struct mlx5_ifc_create_rmp_in_bits {
6272 u8 opcode[0x10];
b4ff3a36 6273 u8 reserved_at_10[0x10];
e281682b 6274
b4ff3a36 6275 u8 reserved_at_20[0x10];
e281682b
SM		 6276 u8 op_mod[0x10];
6277
b4ff3a36 6278 u8 reserved_at_40[0xc0];
e281682b
SM		 6279
6280 struct mlx5_ifc_rmpc_bits ctx;
6281};
6282
6283struct mlx5_ifc_create_qp_out_bits {
6284 u8 status[0x8];
b4ff3a36 6285 u8 reserved_at_8[0x18];
e281682b
SM		 6286
6287 u8 syndrome[0x20];
6288
b4ff3a36 6289 u8 reserved_at_40[0x8];
e281682b
SM		 6290 u8 qpn[0x18];
6291
b4ff3a36 6292 u8 reserved_at_60[0x20];
e281682b
SM		 6293};
6294
6295struct mlx5_ifc_create_qp_in_bits {
6296 u8 opcode[0x10];
b4ff3a36 6297 u8 reserved_at_10[0x10];
e281682b 6298
b4ff3a36 6299 u8 reserved_at_20[0x10];
e281682b
SM		 6300 u8 op_mod[0x10];
6301
b4ff3a36 6302 u8 reserved_at_40[0x40];
e281682b
SM		 6303
6304 u8 opt_param_mask[0x20];
6305
b4ff3a36 6306 u8 reserved_at_a0[0x20];
e281682b
SM		 6307
6308 struct mlx5_ifc_qpc_bits qpc;
6309
b4ff3a36 6310 u8 reserved_at_800[0x80];
e281682b
SM		 6311
6312 u8 pas[0][0x40];
6313};
6314
6315struct mlx5_ifc_create_psv_out_bits {
6316 u8 status[0x8];
b4ff3a36 6317 u8 reserved_at_8[0x18];
e281682b
SM		 6318
6319 u8 syndrome[0x20];
6320
b4ff3a36 6321 u8 reserved_at_40[0x40];
e281682b 6322
b4ff3a36 6323 u8 reserved_at_80[0x8];
e281682b
SM		 6324 u8 psv0_index[0x18];
6325
b4ff3a36 6326 u8 reserved_at_a0[0x8];
e281682b
SM		 6327 u8 psv1_index[0x18];
6328
b4ff3a36 6329 u8 reserved_at_c0[0x8];
e281682b
SM		 6330 u8 psv2_index[0x18];
6331
b4ff3a36 6332 u8 reserved_at_e0[0x8];
e281682b
SM		 6333 u8 psv3_index[0x18];
6334};
6335
6336struct mlx5_ifc_create_psv_in_bits {
6337 u8 opcode[0x10];
b4ff3a36 6338 u8 reserved_at_10[0x10];
e281682b 6339
b4ff3a36 6340 u8 reserved_at_20[0x10];
e281682b
SM		 6341 u8 op_mod[0x10];
6342
6343 u8 num_psv[0x4];
b4ff3a36 6344 u8 reserved_at_44[0x4];
e281682b
SM		 6345 u8 pd[0x18];
6346
b4ff3a36 6347 u8 reserved_at_60[0x20];
e281682b
SM		 6348};
6349
6350struct mlx5_ifc_create_mkey_out_bits {
6351 u8 status[0x8];
b4ff3a36 6352 u8 reserved_at_8[0x18];
e281682b
SM		 6353
6354 u8 syndrome[0x20];
6355
b4ff3a36 6356 u8 reserved_at_40[0x8];
e281682b
SM		 6357 u8 mkey_index[0x18];
6358
b4ff3a36 6359 u8 reserved_at_60[0x20];
e281682b
SM		 6360};
6361
6362struct mlx5_ifc_create_mkey_in_bits {
6363 u8 opcode[0x10];
b4ff3a36 6364 u8 reserved_at_10[0x10];
e281682b 6365
b4ff3a36 6366 u8 reserved_at_20[0x10];
e281682b
SM		 6367 u8 op_mod[0x10];
6368
b4ff3a36 6369 u8 reserved_at_40[0x20];
e281682b
SM		 6370
6371 u8 pg_access[0x1];
b4ff3a36 6372 u8 reserved_at_61[0x1f];
e281682b
SM		 6373
6374 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6375
b4ff3a36 6376 u8 reserved_at_280[0x80];
e281682b
SM		 6377
6378 u8 translations_octword_actual_size[0x20];
6379
b4ff3a36 6380 u8 reserved_at_320[0x560];
e281682b
SM		 6381
6382 u8 klm_pas_mtt[0][0x20];
6383};
6384
6385struct mlx5_ifc_create_flow_table_out_bits {
6386 u8 status[0x8];
b4ff3a36 6387 u8 reserved_at_8[0x18];
e281682b
SM		 6388
6389 u8 syndrome[0x20];
6390
b4ff3a36 6391 u8 reserved_at_40[0x8];
e281682b
SM		 6392 u8 table_id[0x18];
6393
b4ff3a36 6394 u8 reserved_at_60[0x20];
e281682b
SM		 6395};
6396
6397struct mlx5_ifc_create_flow_table_in_bits {
6398 u8 opcode[0x10];
b4ff3a36 6399 u8 reserved_at_10[0x10];
e281682b 6400
b4ff3a36 6401 u8 reserved_at_20[0x10];
e281682b
SM		 6402 u8 op_mod[0x10];
6403
7d5e1423
SM		 6404 u8 other_vport[0x1];
6405 u8 reserved_at_41[0xf];
6406 u8 vport_number[0x10];
6407
6408 u8 reserved_at_60[0x20];
e281682b
SM		 6409
6410 u8 table_type[0x8];
b4ff3a36 6411 u8 reserved_at_88[0x18];
e281682b 6412
b4ff3a36 6413 u8 reserved_at_a0[0x20];
e281682b 6414
7adbde20
HHZ		 6415 u8 encap_en[0x1];
6416 u8 decap_en[0x1];
6417 u8 reserved_at_c2[0x2];
34a40e68 6418 u8 table_miss_mode[0x4];
e281682b 6419 u8 level[0x8];
b4ff3a36 6420 u8 reserved_at_d0[0x8];
e281682b
SM		 6421 u8 log_size[0x8];
6422
b4ff3a36 6423 u8 reserved_at_e0[0x8];
34a40e68
MG		 6424 u8 table_miss_id[0x18];
6425
84df61eb
AH		 6426 u8 reserved_at_100[0x8];
6427 u8 lag_master_next_table_id[0x18];
6428
6429 u8 reserved_at_120[0x80];
e281682b
SM		 6430};
6431
6432struct mlx5_ifc_create_flow_group_out_bits {
6433 u8 status[0x8];
b4ff3a36 6434 u8 reserved_at_8[0x18];
e281682b
SM		 6435
6436 u8 syndrome[0x20];
6437
b4ff3a36 6438 u8 reserved_at_40[0x8];
e281682b
SM		 6439 u8 group_id[0x18];
6440
b4ff3a36 6441 u8 reserved_at_60[0x20];
e281682b
SM		 6442};
6443
6444enum {
6445 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
6446 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
6447 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
6448};
6449
6450struct mlx5_ifc_create_flow_group_in_bits {
6451 u8 opcode[0x10];
b4ff3a36 6452 u8 reserved_at_10[0x10];
e281682b 6453
b4ff3a36 6454 u8 reserved_at_20[0x10];
e281682b
SM		 6455 u8 op_mod[0x10];
6456
7d5e1423
SM		 6457 u8 other_vport[0x1];
6458 u8 reserved_at_41[0xf];
6459 u8 vport_number[0x10];
6460
6461 u8 reserved_at_60[0x20];
e281682b
SM		 6462
6463 u8 table_type[0x8];
b4ff3a36 6464 u8 reserved_at_88[0x18];
e281682b 6465
b4ff3a36 6466 u8 reserved_at_a0[0x8];
e281682b
SM		 6467 u8 table_id[0x18];
6468
b4ff3a36 6469 u8 reserved_at_c0[0x20];
e281682b
SM		 6470
6471 u8 start_flow_index[0x20];
6472
b4ff3a36 6473 u8 reserved_at_100[0x20];
e281682b
SM		 6474
6475 u8 end_flow_index[0x20];
6476
b4ff3a36 6477 u8 reserved_at_140[0xa0];
e281682b 6478
b4ff3a36 6479 u8 reserved_at_1e0[0x18];
e281682b
SM		 6480 u8 match_criteria_enable[0x8];
6481
6482 struct mlx5_ifc_fte_match_param_bits match_criteria;
6483
b4ff3a36 6484 u8 reserved_at_1200[0xe00];
e281682b
SM		 6485};
6486
6487struct mlx5_ifc_create_eq_out_bits {
6488 u8 status[0x8];
b4ff3a36 6489 u8 reserved_at_8[0x18];
e281682b
SM		 6490
6491 u8 syndrome[0x20];
6492
b4ff3a36 6493 u8 reserved_at_40[0x18];
e281682b
SM		 6494 u8 eq_number[0x8];
6495
b4ff3a36 6496 u8 reserved_at_60[0x20];
e281682b
SM		 6497};
6498
6499struct mlx5_ifc_create_eq_in_bits {
6500 u8 opcode[0x10];
b4ff3a36 6501 u8 reserved_at_10[0x10];
e281682b 6502
b4ff3a36 6503 u8 reserved_at_20[0x10];
e281682b
SM		 6504 u8 op_mod[0x10];
6505
b4ff3a36 6506 u8 reserved_at_40[0x40];
e281682b
SM		 6507
6508 struct mlx5_ifc_eqc_bits eq_context_entry;
6509
b4ff3a36 6510 u8 reserved_at_280[0x40];
e281682b
SM		 6511
6512 u8 event_bitmask[0x40];
6513
b4ff3a36 6514 u8 reserved_at_300[0x580];
e281682b
SM		 6515
6516 u8 pas[0][0x40];
6517};
6518
6519struct mlx5_ifc_create_dct_out_bits {
6520 u8 status[0x8];
b4ff3a36 6521 u8 reserved_at_8[0x18];
e281682b
SM		 6522
6523 u8 syndrome[0x20];
6524
b4ff3a36 6525 u8 reserved_at_40[0x8];
e281682b
SM		 6526 u8 dctn[0x18];
6527
b4ff3a36 6528 u8 reserved_at_60[0x20];
e281682b
SM		 6529};
6530
6531struct mlx5_ifc_create_dct_in_bits {
6532 u8 opcode[0x10];
b4ff3a36 6533 u8 reserved_at_10[0x10];
e281682b 6534
b4ff3a36 6535 u8 reserved_at_20[0x10];
e281682b
SM		 6536 u8 op_mod[0x10];
6537
b4ff3a36 6538 u8 reserved_at_40[0x40];
e281682b
SM		 6539
6540 struct mlx5_ifc_dctc_bits dct_context_entry;
6541
b4ff3a36 6542 u8 reserved_at_280[0x180];
e281682b
SM		 6543};
6544
6545struct mlx5_ifc_create_cq_out_bits {
6546 u8 status[0x8];
b4ff3a36 6547 u8 reserved_at_8[0x18];
e281682b
SM		 6548
6549 u8 syndrome[0x20];
6550
b4ff3a36 6551 u8 reserved_at_40[0x8];
e281682b
SM		 6552 u8 cqn[0x18];
6553
b4ff3a36 6554 u8 reserved_at_60[0x20];
e281682b
SM		 6555};
6556
6557struct mlx5_ifc_create_cq_in_bits {
6558 u8 opcode[0x10];
b4ff3a36 6559 u8 reserved_at_10[0x10];
e281682b 6560
b4ff3a36 6561 u8 reserved_at_20[0x10];
e281682b
SM		 6562 u8 op_mod[0x10];
6563
b4ff3a36 6564 u8 reserved_at_40[0x40];
e281682b
SM		 6565
6566 struct mlx5_ifc_cqc_bits cq_context;
6567
b4ff3a36 6568 u8 reserved_at_280[0x600];
e281682b
SM		 6569
6570 u8 pas[0][0x40];
6571};
6572
6573struct mlx5_ifc_config_int_moderation_out_bits {
6574 u8 status[0x8];
b4ff3a36 6575 u8 reserved_at_8[0x18];
e281682b
SM		 6576
6577 u8 syndrome[0x20];
6578
b4ff3a36 6579 u8 reserved_at_40[0x4];
e281682b
SM		 6580 u8 min_delay[0xc];
6581 u8 int_vector[0x10];
6582
b4ff3a36 6583 u8 reserved_at_60[0x20];
e281682b
SM		 6584};
6585
6586enum {
6587 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
6588 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
6589};
6590
6591struct mlx5_ifc_config_int_moderation_in_bits {
6592 u8 opcode[0x10];
b4ff3a36 6593 u8 reserved_at_10[0x10];
e281682b 6594
b4ff3a36 6595 u8 reserved_at_20[0x10];
e281682b
SM		 6596 u8 op_mod[0x10];
6597
b4ff3a36 6598 u8 reserved_at_40[0x4];
e281682b
SM		 6599 u8 min_delay[0xc];
6600 u8 int_vector[0x10];
6601
b4ff3a36 6602 u8 reserved_at_60[0x20];
e281682b
SM		 6603};
6604
6605struct mlx5_ifc_attach_to_mcg_out_bits {
6606 u8 status[0x8];
b4ff3a36 6607 u8 reserved_at_8[0x18];
e281682b
SM		 6608
6609 u8 syndrome[0x20];
6610
b4ff3a36 6611 u8 reserved_at_40[0x40];
e281682b
SM		 6612};
6613
6614struct mlx5_ifc_attach_to_mcg_in_bits {
6615 u8 opcode[0x10];
b4ff3a36 6616 u8 reserved_at_10[0x10];
e281682b 6617
b4ff3a36 6618 u8 reserved_at_20[0x10];
e281682b
SM		 6619 u8 op_mod[0x10];
6620
b4ff3a36 6621 u8 reserved_at_40[0x8];
e281682b
SM		 6622 u8 qpn[0x18];
6623
b4ff3a36 6624 u8 reserved_at_60[0x20];
e281682b
SM		 6625
6626 u8 multicast_gid[16][0x8];
6627};
6628
7486216b
SM		 6629struct mlx5_ifc_arm_xrq_out_bits {
6630 u8 status[0x8];
6631 u8 reserved_at_8[0x18];
6632
6633 u8 syndrome[0x20];
6634
6635 u8 reserved_at_40[0x40];
6636};
6637
6638struct mlx5_ifc_arm_xrq_in_bits {
6639 u8 opcode[0x10];
6640 u8 reserved_at_10[0x10];
6641
6642 u8 reserved_at_20[0x10];
6643 u8 op_mod[0x10];
6644
6645 u8 reserved_at_40[0x8];
6646 u8 xrqn[0x18];
6647
6648 u8 reserved_at_60[0x10];
6649 u8 lwm[0x10];
6650};
6651
e281682b
SM		 6652struct mlx5_ifc_arm_xrc_srq_out_bits {
6653 u8 status[0x8];
b4ff3a36 6654 u8 reserved_at_8[0x18];
e281682b
SM		 6655
6656 u8 syndrome[0x20];
6657
b4ff3a36 6658 u8 reserved_at_40[0x40];
e281682b
SM		 6659};
6660
6661enum {
6662 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
6663};
6664
6665struct mlx5_ifc_arm_xrc_srq_in_bits {
6666 u8 opcode[0x10];
b4ff3a36 6667 u8 reserved_at_10[0x10];
e281682b 6668
b4ff3a36 6669 u8 reserved_at_20[0x10];
e281682b
SM		 6670 u8 op_mod[0x10];
6671
b4ff3a36 6672 u8 reserved_at_40[0x8];
e281682b
SM		 6673 u8 xrc_srqn[0x18];
6674
b4ff3a36 6675 u8 reserved_at_60[0x10];
e281682b
SM		 6676 u8 lwm[0x10];
6677};
6678
6679struct mlx5_ifc_arm_rq_out_bits {
6680 u8 status[0x8];
b4ff3a36 6681 u8 reserved_at_8[0x18];
e281682b
SM		 6682
6683 u8 syndrome[0x20];
6684
b4ff3a36 6685 u8 reserved_at_40[0x40];
e281682b
SM		 6686};
6687
6688enum {
7486216b
SM		 6689 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
6690 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
e281682b
SM		 6691};
6692
6693struct mlx5_ifc_arm_rq_in_bits {
6694 u8 opcode[0x10];
b4ff3a36 6695 u8 reserved_at_10[0x10];
e281682b 6696
b4ff3a36 6697 u8 reserved_at_20[0x10];
e281682b
SM		 6698 u8 op_mod[0x10];
6699
b4ff3a36 6700 u8 reserved_at_40[0x8];
e281682b
SM		 6701 u8 srq_number[0x18];
6702
b4ff3a36 6703 u8 reserved_at_60[0x10];
e281682b
SM		 6704 u8 lwm[0x10];
6705};
6706
6707struct mlx5_ifc_arm_dct_out_bits {
6708 u8 status[0x8];
b4ff3a36 6709 u8 reserved_at_8[0x18];
e281682b
SM		 6710
6711 u8 syndrome[0x20];
6712
b4ff3a36 6713 u8 reserved_at_40[0x40];
e281682b
SM		 6714};
6715
6716struct mlx5_ifc_arm_dct_in_bits {
6717 u8 opcode[0x10];
b4ff3a36 6718 u8 reserved_at_10[0x10];
e281682b 6719
b4ff3a36 6720 u8 reserved_at_20[0x10];
e281682b
SM		 6721 u8 op_mod[0x10];
6722
b4ff3a36 6723 u8 reserved_at_40[0x8];
e281682b
SM		 6724 u8 dct_number[0x18];
6725
b4ff3a36 6726 u8 reserved_at_60[0x20];
e281682b
SM		 6727};
6728
6729struct mlx5_ifc_alloc_xrcd_out_bits {
6730 u8 status[0x8];
b4ff3a36 6731 u8 reserved_at_8[0x18];
e281682b
SM		 6732
6733 u8 syndrome[0x20];
6734
b4ff3a36 6735 u8 reserved_at_40[0x8];
e281682b
SM		 6736 u8 xrcd[0x18];
6737
b4ff3a36 6738 u8 reserved_at_60[0x20];
e281682b
SM		 6739};
6740
6741struct mlx5_ifc_alloc_xrcd_in_bits {
6742 u8 opcode[0x10];
b4ff3a36 6743 u8 reserved_at_10[0x10];
e281682b 6744
b4ff3a36 6745 u8 reserved_at_20[0x10];
e281682b
SM		 6746 u8 op_mod[0x10];
6747
b4ff3a36 6748 u8 reserved_at_40[0x40];
e281682b
SM		 6749};
6750
6751struct mlx5_ifc_alloc_uar_out_bits {
6752 u8 status[0x8];
b4ff3a36 6753 u8 reserved_at_8[0x18];
e281682b
SM		 6754
6755 u8 syndrome[0x20];
6756
b4ff3a36 6757 u8 reserved_at_40[0x8];
e281682b
SM		 6758 u8 uar[0x18];
6759
b4ff3a36 6760 u8 reserved_at_60[0x20];
e281682b
SM		 6761};
6762
6763struct mlx5_ifc_alloc_uar_in_bits {
6764 u8 opcode[0x10];
b4ff3a36 6765 u8 reserved_at_10[0x10];
e281682b 6766
b4ff3a36 6767 u8 reserved_at_20[0x10];
e281682b
SM		 6768 u8 op_mod[0x10];
6769
b4ff3a36 6770 u8 reserved_at_40[0x40];
e281682b
SM		 6771};
6772
6773struct mlx5_ifc_alloc_transport_domain_out_bits {
6774 u8 status[0x8];
b4ff3a36 6775 u8 reserved_at_8[0x18];
e281682b
SM		 6776
6777 u8 syndrome[0x20];
6778
b4ff3a36 6779 u8 reserved_at_40[0x8];
e281682b
SM		 6780 u8 transport_domain[0x18];
6781
b4ff3a36 6782 u8 reserved_at_60[0x20];
e281682b
SM		 6783};
6784
6785struct mlx5_ifc_alloc_transport_domain_in_bits {
6786 u8 opcode[0x10];
b4ff3a36 6787 u8 reserved_at_10[0x10];
e281682b 6788
b4ff3a36 6789 u8 reserved_at_20[0x10];
e281682b
SM		 6790 u8 op_mod[0x10];
6791
b4ff3a36 6792 u8 reserved_at_40[0x40];
e281682b
SM		 6793};
6794
6795struct mlx5_ifc_alloc_q_counter_out_bits {
6796 u8 status[0x8];
b4ff3a36 6797 u8 reserved_at_8[0x18];
e281682b
SM		 6798
6799 u8 syndrome[0x20];
6800
b4ff3a36 6801 u8 reserved_at_40[0x18];
e281682b
SM		 6802 u8 counter_set_id[0x8];
6803
b4ff3a36 6804 u8 reserved_at_60[0x20];
e281682b
SM		 6805};
6806
6807struct mlx5_ifc_alloc_q_counter_in_bits {
6808 u8 opcode[0x10];
b4ff3a36 6809 u8 reserved_at_10[0x10];
e281682b 6810
b4ff3a36 6811 u8 reserved_at_20[0x10];
e281682b
SM		 6812 u8 op_mod[0x10];
6813
b4ff3a36 6814 u8 reserved_at_40[0x40];
e281682b
SM		 6815};
6816
6817struct mlx5_ifc_alloc_pd_out_bits {
6818 u8 status[0x8];
b4ff3a36 6819 u8 reserved_at_8[0x18];
e281682b
SM		 6820
6821 u8 syndrome[0x20];
6822
b4ff3a36 6823 u8 reserved_at_40[0x8];
e281682b
SM		 6824 u8 pd[0x18];
6825
b4ff3a36 6826 u8 reserved_at_60[0x20];
e281682b
SM		 6827};
6828
6829struct mlx5_ifc_alloc_pd_in_bits {
9dc0b289
AV		 6830 u8 opcode[0x10];
6831 u8 reserved_at_10[0x10];
6832
6833 u8 reserved_at_20[0x10];
6834 u8 op_mod[0x10];
6835
6836 u8 reserved_at_40[0x40];
6837};
6838
6839struct mlx5_ifc_alloc_flow_counter_out_bits {
6840 u8 status[0x8];
6841 u8 reserved_at_8[0x18];
6842
6843 u8 syndrome[0x20];
6844
6845 u8 reserved_at_40[0x10];
6846 u8 flow_counter_id[0x10];
6847
6848 u8 reserved_at_60[0x20];
6849};
6850
6851struct mlx5_ifc_alloc_flow_counter_in_bits {
e281682b 6852 u8 opcode[0x10];
b4ff3a36 6853 u8 reserved_at_10[0x10];
e281682b 6854
b4ff3a36 6855 u8 reserved_at_20[0x10];
e281682b
SM		 6856 u8 op_mod[0x10];
6857
b4ff3a36 6858 u8 reserved_at_40[0x40];
e281682b
SM		 6859};
6860
6861struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
6862 u8 status[0x8];
b4ff3a36 6863 u8 reserved_at_8[0x18];
e281682b
SM		 6864
6865 u8 syndrome[0x20];
6866
b4ff3a36 6867 u8 reserved_at_40[0x40];
e281682b
SM		 6868};
6869
6870struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
6871 u8 opcode[0x10];
b4ff3a36 6872 u8 reserved_at_10[0x10];
e281682b 6873
b4ff3a36 6874 u8 reserved_at_20[0x10];
e281682b
SM		 6875 u8 op_mod[0x10];
6876
b4ff3a36 6877 u8 reserved_at_40[0x20];
e281682b 6878
b4ff3a36 6879 u8 reserved_at_60[0x10];
e281682b
SM		 6880 u8 vxlan_udp_port[0x10];
6881};
6882
7486216b
SM		 6883struct mlx5_ifc_set_rate_limit_out_bits {
6884 u8 status[0x8];
6885 u8 reserved_at_8[0x18];
6886
6887 u8 syndrome[0x20];
6888
6889 u8 reserved_at_40[0x40];
6890};
6891
6892struct mlx5_ifc_set_rate_limit_in_bits {
6893 u8 opcode[0x10];
6894 u8 reserved_at_10[0x10];
6895
6896 u8 reserved_at_20[0x10];
6897 u8 op_mod[0x10];
6898
6899 u8 reserved_at_40[0x10];
6900 u8 rate_limit_index[0x10];
6901
6902 u8 reserved_at_60[0x20];
6903
6904 u8 rate_limit[0x20];
6905};
6906
e281682b
SM		 6907struct mlx5_ifc_access_register_out_bits {
6908 u8 status[0x8];
b4ff3a36 6909 u8 reserved_at_8[0x18];
e281682b
SM		 6910
6911 u8 syndrome[0x20];
6912
b4ff3a36 6913 u8 reserved_at_40[0x40];
e281682b
SM		 6914
6915 u8 register_data[0][0x20];
6916};
6917
6918enum {
6919 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
6920 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
6921};
6922
6923struct mlx5_ifc_access_register_in_bits {
6924 u8 opcode[0x10];
b4ff3a36 6925 u8 reserved_at_10[0x10];
e281682b 6926
b4ff3a36 6927 u8 reserved_at_20[0x10];
e281682b
SM		 6928 u8 op_mod[0x10];
6929
b4ff3a36 6930 u8 reserved_at_40[0x10];
e281682b
SM		 6931 u8 register_id[0x10];
6932
6933 u8 argument[0x20];
6934
6935 u8 register_data[0][0x20];
6936};
6937
6938struct mlx5_ifc_sltp_reg_bits {
6939 u8 status[0x4];
6940 u8 version[0x4];
6941 u8 local_port[0x8];
6942 u8 pnat[0x2];
b4ff3a36 6943 u8 reserved_at_12[0x2];
e281682b 6944 u8 lane[0x4];
b4ff3a36 6945 u8 reserved_at_18[0x8];
e281682b 6946
b4ff3a36 6947 u8 reserved_at_20[0x20];
e281682b 6948
b4ff3a36 6949 u8 reserved_at_40[0x7];
e281682b
SM		 6950 u8 polarity[0x1];
6951 u8 ob_tap0[0x8];
6952 u8 ob_tap1[0x8];
6953 u8 ob_tap2[0x8];
6954
b4ff3a36 6955 u8 reserved_at_60[0xc];
e281682b
SM		 6956 u8 ob_preemp_mode[0x4];
6957 u8 ob_reg[0x8];
6958 u8 ob_bias[0x8];
6959
b4ff3a36 6960 u8 reserved_at_80[0x20];
e281682b
SM		 6961};
6962
6963struct mlx5_ifc_slrg_reg_bits {
6964 u8 status[0x4];
6965 u8 version[0x4];
6966 u8 local_port[0x8];
6967 u8 pnat[0x2];
b4ff3a36 6968 u8 reserved_at_12[0x2];
e281682b 6969 u8 lane[0x4];
b4ff3a36 6970 u8 reserved_at_18[0x8];
e281682b
SM		 6971
6972 u8 time_to_link_up[0x10];
b4ff3a36 6973 u8 reserved_at_30[0xc];
e281682b
SM		 6974 u8 grade_lane_speed[0x4];
6975
6976 u8 grade_version[0x8];
6977 u8 grade[0x18];
6978
b4ff3a36 6979 u8 reserved_at_60[0x4];
e281682b
SM		 6980 u8 height_grade_type[0x4];
6981 u8 height_grade[0x18];
6982
6983 u8 height_dz[0x10];
6984 u8 height_dv[0x10];
6985
b4ff3a36 6986 u8 reserved_at_a0[0x10];
e281682b
SM		 6987 u8 height_sigma[0x10];
6988
b4ff3a36 6989 u8 reserved_at_c0[0x20];
e281682b 6990
b4ff3a36 6991 u8 reserved_at_e0[0x4];
e281682b
SM		 6992 u8 phase_grade_type[0x4];
6993 u8 phase_grade[0x18];
6994
b4ff3a36 6995 u8 reserved_at_100[0x8];
e281682b 6996 u8 phase_eo_pos[0x8];
b4ff3a36 6997 u8 reserved_at_110[0x8];
e281682b
SM		 6998 u8 phase_eo_neg[0x8];
6999
7000 u8 ffe_set_tested[0x10];
7001 u8 test_errors_per_lane[0x10];
7002};
7003
7004struct mlx5_ifc_pvlc_reg_bits {
b4ff3a36 7005 u8 reserved_at_0[0x8];
e281682b 7006 u8 local_port[0x8];
b4ff3a36 7007 u8 reserved_at_10[0x10];
e281682b 7008
b4ff3a36 7009 u8 reserved_at_20[0x1c];
e281682b
SM		 7010 u8 vl_hw_cap[0x4];
7011
b4ff3a36 7012 u8 reserved_at_40[0x1c];
e281682b
SM		 7013 u8 vl_admin[0x4];
7014
b4ff3a36 7015 u8 reserved_at_60[0x1c];
e281682b
SM		 7016 u8 vl_operational[0x4];
7017};
7018
7019struct mlx5_ifc_pude_reg_bits {
7020 u8 swid[0x8];
7021 u8 local_port[0x8];
b4ff3a36 7022 u8 reserved_at_10[0x4];
e281682b 7023 u8 admin_status[0x4];
b4ff3a36 7024 u8 reserved_at_18[0x4];
e281682b
SM		 7025 u8 oper_status[0x4];
7026
b4ff3a36 7027 u8 reserved_at_20[0x60];
e281682b
SM		 7028};
7029
7030struct mlx5_ifc_ptys_reg_bits {
e7e31ca4 7031 u8 reserved_at_0[0x1];
7486216b 7032 u8 an_disable_admin[0x1];
e7e31ca4
BW		 7033 u8 an_disable_cap[0x1];
7034 u8 reserved_at_3[0x5];
e281682b 7035 u8 local_port[0x8];
b4ff3a36 7036 u8 reserved_at_10[0xd];
e281682b
SM		 7037 u8 proto_mask[0x3];
7038
7486216b
SM		 7039 u8 an_status[0x4];
7040 u8 reserved_at_24[0x3c];
e281682b
SM		 7041
7042 u8 eth_proto_capability[0x20];
7043
7044 u8 ib_link_width_capability[0x10];
7045 u8 ib_proto_capability[0x10];
7046
b4ff3a36 7047 u8 reserved_at_a0[0x20];
e281682b
SM		 7048
7049 u8 eth_proto_admin[0x20];
7050
7051 u8 ib_link_width_admin[0x10];
7052 u8 ib_proto_admin[0x10];
7053
b4ff3a36 7054 u8 reserved_at_100[0x20];
e281682b
SM		 7055
7056 u8 eth_proto_oper[0x20];
7057
7058 u8 ib_link_width_oper[0x10];
7059 u8 ib_proto_oper[0x10];
7060
b4ff3a36 7061 u8 reserved_at_160[0x20];
e281682b
SM		 7062
7063 u8 eth_proto_lp_advertise[0x20];
7064
b4ff3a36 7065 u8 reserved_at_1a0[0x60];
e281682b
SM		 7066};
7067
7d5e1423
SM		 7068struct mlx5_ifc_mlcr_reg_bits {
7069 u8 reserved_at_0[0x8];
7070 u8 local_port[0x8];
7071 u8 reserved_at_10[0x20];
7072
7073 u8 beacon_duration[0x10];
7074 u8 reserved_at_40[0x10];
7075
7076 u8 beacon_remain[0x10];
7077};
7078
e281682b 7079struct mlx5_ifc_ptas_reg_bits {
b4ff3a36 7080 u8 reserved_at_0[0x20];
e281682b
SM		 7081
7082 u8 algorithm_options[0x10];
b4ff3a36 7083 u8 reserved_at_30[0x4];
e281682b
SM		 7084 u8 repetitions_mode[0x4];
7085 u8 num_of_repetitions[0x8];
7086
7087 u8 grade_version[0x8];
7088 u8 height_grade_type[0x4];
7089 u8 phase_grade_type[0x4];
7090 u8 height_grade_weight[0x8];
7091 u8 phase_grade_weight[0x8];
7092
7093 u8 gisim_measure_bits[0x10];
7094 u8 adaptive_tap_measure_bits[0x10];
7095
7096 u8 ber_bath_high_error_threshold[0x10];
7097 u8 ber_bath_mid_error_threshold[0x10];
7098
7099 u8 ber_bath_low_error_threshold[0x10];
7100 u8 one_ratio_high_threshold[0x10];
7101
7102 u8 one_ratio_high_mid_threshold[0x10];
7103 u8 one_ratio_low_mid_threshold[0x10];
7104
7105 u8 one_ratio_low_threshold[0x10];
7106 u8 ndeo_error_threshold[0x10];
7107
7108 u8 mixer_offset_step_size[0x10];
b4ff3a36 7109 u8 reserved_at_110[0x8];
e281682b
SM		 7110 u8 mix90_phase_for_voltage_bath[0x8];
7111
7112 u8 mixer_offset_start[0x10];
7113 u8 mixer_offset_end[0x10];
7114
b4ff3a36 7115 u8 reserved_at_140[0x15];
e281682b
SM		 7116 u8 ber_test_time[0xb];
7117};
7118
7119struct mlx5_ifc_pspa_reg_bits {
7120 u8 swid[0x8];
7121 u8 local_port[0x8];
7122 u8 sub_port[0x8];
b4ff3a36 7123 u8 reserved_at_18[0x8];
e281682b 7124
b4ff3a36 7125 u8 reserved_at_20[0x20];
e281682b
SM		 7126};
7127
7128struct mlx5_ifc_pqdr_reg_bits {
b4ff3a36 7129 u8 reserved_at_0[0x8];
e281682b 7130 u8 local_port[0x8];
b4ff3a36 7131 u8 reserved_at_10[0x5];
e281682b 7132 u8 prio[0x3];
b4ff3a36 7133 u8 reserved_at_18[0x6];
e281682b
SM		 7134 u8 mode[0x2];
7135
b4ff3a36 7136 u8 reserved_at_20[0x20];
e281682b 7137
b4ff3a36 7138 u8 reserved_at_40[0x10];
e281682b
SM		 7139 u8 min_threshold[0x10];
7140
b4ff3a36 7141 u8 reserved_at_60[0x10];
e281682b
SM		 7142 u8 max_threshold[0x10];
7143
b4ff3a36 7144 u8 reserved_at_80[0x10];
e281682b
SM		 7145 u8 mark_probability_denominator[0x10];
7146
b4ff3a36 7147 u8 reserved_at_a0[0x60];
e281682b
SM		 7148};
7149
7150struct mlx5_ifc_ppsc_reg_bits {
b4ff3a36 7151 u8 reserved_at_0[0x8];
e281682b 7152 u8 local_port[0x8];
b4ff3a36 7153 u8 reserved_at_10[0x10];
e281682b 7154
b4ff3a36 7155 u8 reserved_at_20[0x60];
e281682b 7156
b4ff3a36 7157 u8 reserved_at_80[0x1c];
e281682b
SM		 7158 u8 wrps_admin[0x4];
7159
b4ff3a36 7160 u8 reserved_at_a0[0x1c];
e281682b
SM		 7161 u8 wrps_status[0x4];
7162
b4ff3a36 7163 u8 reserved_at_c0[0x8];
e281682b 7164 u8 up_threshold[0x8];
b4ff3a36 7165 u8 reserved_at_d0[0x8];
e281682b
SM		 7166 u8 down_threshold[0x8];
7167
b4ff3a36 7168 u8 reserved_at_e0[0x20];
e281682b 7169
b4ff3a36 7170 u8 reserved_at_100[0x1c];
e281682b
SM		 7171 u8 srps_admin[0x4];
7172
b4ff3a36 7173 u8 reserved_at_120[0x1c];
e281682b
SM		 7174 u8 srps_status[0x4];
7175
b4ff3a36 7176 u8 reserved_at_140[0x40];
e281682b
SM		 7177};
7178
7179struct mlx5_ifc_pplr_reg_bits {
b4ff3a36 7180 u8 reserved_at_0[0x8];
e281682b 7181 u8 local_port[0x8];
b4ff3a36 7182 u8 reserved_at_10[0x10];
e281682b 7183
b4ff3a36 7184 u8 reserved_at_20[0x8];
e281682b 7185 u8 lb_cap[0x8];
b4ff3a36 7186 u8 reserved_at_30[0x8];
e281682b
SM		 7187 u8 lb_en[0x8];
7188};
7189
7190struct mlx5_ifc_pplm_reg_bits {
b4ff3a36 7191 u8 reserved_at_0[0x8];
e281682b 7192 u8 local_port[0x8];
b4ff3a36 7193 u8 reserved_at_10[0x10];
e281682b 7194
b4ff3a36 7195 u8 reserved_at_20[0x20];
e281682b
SM		 7196
7197 u8 port_profile_mode[0x8];
7198 u8 static_port_profile[0x8];
7199 u8 active_port_profile[0x8];
b4ff3a36 7200 u8 reserved_at_58[0x8];
e281682b
SM		 7201
7202 u8 retransmission_active[0x8];
7203 u8 fec_mode_active[0x18];
7204
b4ff3a36 7205 u8 reserved_at_80[0x20];
e281682b
SM		 7206};
7207
7208struct mlx5_ifc_ppcnt_reg_bits {
7209 u8 swid[0x8];
7210 u8 local_port[0x8];
7211 u8 pnat[0x2];
b4ff3a36 7212 u8 reserved_at_12[0x8];
e281682b
SM		 7213 u8 grp[0x6];
7214
7215 u8 clr[0x1];
b4ff3a36 7216 u8 reserved_at_21[0x1c];
e281682b
SM		 7217 u8 prio_tc[0x3];
7218
7219 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
7220};
7221
7222struct mlx5_ifc_ppad_reg_bits {
b4ff3a36 7223 u8 reserved_at_0[0x3];
e281682b 7224 u8 single_mac[0x1];
b4ff3a36 7225 u8 reserved_at_4[0x4];
e281682b
SM		 7226 u8 local_port[0x8];
7227 u8 mac_47_32[0x10];
7228
7229 u8 mac_31_0[0x20];
7230
b4ff3a36 7231 u8 reserved_at_40[0x40];
e281682b
SM		 7232};
7233
7234struct mlx5_ifc_pmtu_reg_bits {
b4ff3a36 7235 u8 reserved_at_0[0x8];
e281682b 7236 u8 local_port[0x8];
b4ff3a36 7237 u8 reserved_at_10[0x10];
e281682b
SM		 7238
7239 u8 max_mtu[0x10];
b4ff3a36 7240 u8 reserved_at_30[0x10];
e281682b
SM		 7241
7242 u8 admin_mtu[0x10];
b4ff3a36 7243 u8 reserved_at_50[0x10];
e281682b
SM		 7244
7245 u8 oper_mtu[0x10];
b4ff3a36 7246 u8 reserved_at_70[0x10];
e281682b
SM		 7247};
7248
7249struct mlx5_ifc_pmpr_reg_bits {
b4ff3a36 7250 u8 reserved_at_0[0x8];
e281682b 7251 u8 module[0x8];
b4ff3a36 7252 u8 reserved_at_10[0x10];
e281682b 7253
b4ff3a36 7254 u8 reserved_at_20[0x18];
e281682b
SM		 7255 u8 attenuation_5g[0x8];
7256
b4ff3a36 7257 u8 reserved_at_40[0x18];
e281682b
SM		 7258 u8 attenuation_7g[0x8];
7259
b4ff3a36 7260 u8 reserved_at_60[0x18];
e281682b
SM		 7261 u8 attenuation_12g[0x8];
7262};
7263
7264struct mlx5_ifc_pmpe_reg_bits {
b4ff3a36 7265 u8 reserved_at_0[0x8];
e281682b 7266 u8 module[0x8];
b4ff3a36 7267 u8 reserved_at_10[0xc];
e281682b
SM		 7268 u8 module_status[0x4];
7269
b4ff3a36 7270 u8 reserved_at_20[0x60];
e281682b
SM		 7271};
7272
7273struct mlx5_ifc_pmpc_reg_bits {
7274 u8 module_state_updated[32][0x8];
7275};
7276
7277struct mlx5_ifc_pmlpn_reg_bits {
b4ff3a36 7278 u8 reserved_at_0[0x4];
e281682b
SM		 7279 u8 mlpn_status[0x4];
7280 u8 local_port[0x8];
b4ff3a36 7281 u8 reserved_at_10[0x10];
e281682b
SM		 7282
7283 u8 e[0x1];
b4ff3a36 7284 u8 reserved_at_21[0x1f];
e281682b
SM		 7285};
7286
7287struct mlx5_ifc_pmlp_reg_bits {
7288 u8 rxtx[0x1];
b4ff3a36 7289 u8 reserved_at_1[0x7];
e281682b 7290 u8 local_port[0x8];
b4ff3a36 7291 u8 reserved_at_10[0x8];
e281682b
SM		 7292 u8 width[0x8];
7293
7294 u8 lane0_module_mapping[0x20];
7295
7296 u8 lane1_module_mapping[0x20];
7297
7298 u8 lane2_module_mapping[0x20];
7299
7300 u8 lane3_module_mapping[0x20];
7301
b4ff3a36 7302 u8 reserved_at_a0[0x160];
e281682b
SM		 7303};
7304
7305struct mlx5_ifc_pmaos_reg_bits {
b4ff3a36 7306 u8 reserved_at_0[0x8];
e281682b 7307 u8 module[0x8];
b4ff3a36 7308 u8 reserved_at_10[0x4];
e281682b 7309 u8 admin_status[0x4];
b4ff3a36 7310 u8 reserved_at_18[0x4];
e281682b
SM		 7311 u8 oper_status[0x4];
7312
7313 u8 ase[0x1];
7314 u8 ee[0x1];
b4ff3a36 7315 u8 reserved_at_22[0x1c];
e281682b
SM		 7316 u8 e[0x2];
7317
b4ff3a36 7318 u8 reserved_at_40[0x40];
e281682b
SM		 7319};
7320
7321struct mlx5_ifc_plpc_reg_bits {
b4ff3a36 7322 u8 reserved_at_0[0x4];
e281682b 7323 u8 profile_id[0xc];
b4ff3a36 7324 u8 reserved_at_10[0x4];
e281682b 7325 u8 proto_mask[0x4];
b4ff3a36 7326 u8 reserved_at_18[0x8];
e281682b 7327
b4ff3a36 7328 u8 reserved_at_20[0x10];
e281682b
SM		 7329 u8 lane_speed[0x10];
7330
b4ff3a36 7331 u8 reserved_at_40[0x17];
e281682b
SM		 7332 u8 lpbf[0x1];
7333 u8 fec_mode_policy[0x8];
7334
7335 u8 retransmission_capability[0x8];
7336 u8 fec_mode_capability[0x18];
7337
7338 u8 retransmission_support_admin[0x8];
7339 u8 fec_mode_support_admin[0x18];
7340
7341 u8 retransmission_request_admin[0x8];
7342 u8 fec_mode_request_admin[0x18];
7343
b4ff3a36 7344 u8 reserved_at_c0[0x80];
e281682b
SM		 7345};
7346
7347struct mlx5_ifc_plib_reg_bits {
b4ff3a36 7348 u8 reserved_at_0[0x8];
e281682b 7349 u8 local_port[0x8];
b4ff3a36 7350 u8 reserved_at_10[0x8];
e281682b
SM		 7351 u8 ib_port[0x8];
7352
b4ff3a36 7353 u8 reserved_at_20[0x60];
e281682b
SM		 7354};
7355
7356struct mlx5_ifc_plbf_reg_bits {
b4ff3a36 7357 u8 reserved_at_0[0x8];
e281682b 7358 u8 local_port[0x8];
b4ff3a36 7359 u8 reserved_at_10[0xd];
e281682b
SM		 7360 u8 lbf_mode[0x3];
7361
b4ff3a36 7362 u8 reserved_at_20[0x20];
e281682b
SM		 7363};
7364
7365struct mlx5_ifc_pipg_reg_bits {
b4ff3a36 7366 u8 reserved_at_0[0x8];
e281682b 7367 u8 local_port[0x8];
b4ff3a36 7368 u8 reserved_at_10[0x10];
e281682b
SM		 7369
7370 u8 dic[0x1];
b4ff3a36 7371 u8 reserved_at_21[0x19];
e281682b 7372 u8 ipg[0x4];
b4ff3a36 7373 u8 reserved_at_3e[0x2];
e281682b
SM		 7374};
7375
7376struct mlx5_ifc_pifr_reg_bits {
b4ff3a36 7377 u8 reserved_at_0[0x8];
e281682b 7378 u8 local_port[0x8];
b4ff3a36 7379 u8 reserved_at_10[0x10];
e281682b 7380
b4ff3a36 7381 u8 reserved_at_20[0xe0];
e281682b
SM		 7382
7383 u8 port_filter[8][0x20];
7384
7385 u8 port_filter_update_en[8][0x20];
7386};
7387
7388struct mlx5_ifc_pfcc_reg_bits {
b4ff3a36 7389 u8 reserved_at_0[0x8];
e281682b 7390 u8 local_port[0x8];
b4ff3a36 7391 u8 reserved_at_10[0x10];
e281682b
SM		 7392
7393 u8 ppan[0x4];
b4ff3a36 7394 u8 reserved_at_24[0x4];
e281682b 7395 u8 prio_mask_tx[0x8];
b4ff3a36 7396 u8 reserved_at_30[0x8];
e281682b
SM		 7397 u8 prio_mask_rx[0x8];
7398
7399 u8 pptx[0x1];
7400 u8 aptx[0x1];
b4ff3a36 7401 u8 reserved_at_42[0x6];
e281682b 7402 u8 pfctx[0x8];
b4ff3a36 7403 u8 reserved_at_50[0x10];
e281682b
SM		 7404
7405 u8 pprx[0x1];
7406 u8 aprx[0x1];
b4ff3a36 7407 u8 reserved_at_62[0x6];
e281682b 7408 u8 pfcrx[0x8];
b4ff3a36 7409 u8 reserved_at_70[0x10];
e281682b 7410
b4ff3a36 7411 u8 reserved_at_80[0x80];
e281682b
SM		 7412};
7413
7414struct mlx5_ifc_pelc_reg_bits {
7415 u8 op[0x4];
b4ff3a36 7416 u8 reserved_at_4[0x4];
e281682b 7417 u8 local_port[0x8];
b4ff3a36 7418 u8 reserved_at_10[0x10];
e281682b
SM		 7419
7420 u8 op_admin[0x8];
7421 u8 op_capability[0x8];
7422 u8 op_request[0x8];
7423 u8 op_active[0x8];
7424
7425 u8 admin[0x40];
7426
7427 u8 capability[0x40];
7428
7429 u8 request[0x40];
7430
7431 u8 active[0x40];
7432
b4ff3a36 7433 u8 reserved_at_140[0x80];
e281682b
SM		 7434};
7435
7436struct mlx5_ifc_peir_reg_bits {
b4ff3a36 7437 u8 reserved_at_0[0x8];
e281682b 7438 u8 local_port[0x8];
b4ff3a36 7439 u8 reserved_at_10[0x10];
e281682b 7440
b4ff3a36 7441 u8 reserved_at_20[0xc];
e281682b 7442 u8 error_count[0x4];
b4ff3a36 7443 u8 reserved_at_30[0x10];
e281682b 7444
b4ff3a36 7445 u8 reserved_at_40[0xc];
e281682b 7446 u8 lane[0x4];
b4ff3a36 7447 u8 reserved_at_50[0x8];
e281682b
SM		 7448 u8 error_type[0x8];
7449};
7450
7451struct mlx5_ifc_pcap_reg_bits {
b4ff3a36 7452 u8 reserved_at_0[0x8];
e281682b 7453 u8 local_port[0x8];
b4ff3a36 7454 u8 reserved_at_10[0x10];
e281682b
SM		 7455
7456 u8 port_capability_mask[4][0x20];
7457};
7458
7459struct mlx5_ifc_paos_reg_bits {
7460 u8 swid[0x8];
7461 u8 local_port[0x8];
b4ff3a36 7462 u8 reserved_at_10[0x4];
e281682b 7463 u8 admin_status[0x4];
b4ff3a36 7464 u8 reserved_at_18[0x4];
e281682b
SM		 7465 u8 oper_status[0x4];
7466
7467 u8 ase[0x1];
7468 u8 ee[0x1];
b4ff3a36 7469 u8 reserved_at_22[0x1c];
e281682b
SM		 7470 u8 e[0x2];
7471
b4ff3a36 7472 u8 reserved_at_40[0x40];
e281682b
SM		 7473};
7474
7475struct mlx5_ifc_pamp_reg_bits {
b4ff3a36 7476 u8 reserved_at_0[0x8];
e281682b 7477 u8 opamp_group[0x8];
b4ff3a36 7478 u8 reserved_at_10[0xc];
e281682b
SM		 7479 u8 opamp_group_type[0x4];
7480
7481 u8 start_index[0x10];
b4ff3a36 7482 u8 reserved_at_30[0x4];
e281682b
SM		 7483 u8 num_of_indices[0xc];
7484
7485 u8 index_data[18][0x10];
7486};
7487
7d5e1423
SM		 7488struct mlx5_ifc_pcmr_reg_bits {
7489 u8 reserved_at_0[0x8];
7490 u8 local_port[0x8];
7491 u8 reserved_at_10[0x2e];
7492 u8 fcs_cap[0x1];
7493 u8 reserved_at_3f[0x1f];
7494 u8 fcs_chk[0x1];
7495 u8 reserved_at_5f[0x1];
7496};
7497
e281682b 7498struct mlx5_ifc_lane_2_module_mapping_bits {
b4ff3a36 7499 u8 reserved_at_0[0x6];
e281682b 7500 u8 rx_lane[0x2];
b4ff3a36 7501 u8 reserved_at_8[0x6];
e281682b 7502 u8 tx_lane[0x2];
b4ff3a36 7503 u8 reserved_at_10[0x8];
e281682b
SM		 7504 u8 module[0x8];
7505};
7506
7507struct mlx5_ifc_bufferx_reg_bits {
b4ff3a36 7508 u8 reserved_at_0[0x6];
e281682b
SM		 7509 u8 lossy[0x1];
7510 u8 epsb[0x1];
b4ff3a36 7511 u8 reserved_at_8[0xc];
e281682b
SM		 7512 u8 size[0xc];
7513
7514 u8 xoff_threshold[0x10];
7515 u8 xon_threshold[0x10];
7516};
7517
7518struct mlx5_ifc_set_node_in_bits {
7519 u8 node_description[64][0x8];
7520};
7521
7522struct mlx5_ifc_register_power_settings_bits {
b4ff3a36 7523 u8 reserved_at_0[0x18];
e281682b
SM		 7524 u8 power_settings_level[0x8];
7525
b4ff3a36 7526 u8 reserved_at_20[0x60];
e281682b
SM		 7527};
7528
7529struct mlx5_ifc_register_host_endianness_bits {
7530 u8 he[0x1];
b4ff3a36 7531 u8 reserved_at_1[0x1f];
e281682b 7532
b4ff3a36 7533 u8 reserved_at_20[0x60];
e281682b
SM		 7534};
7535
7536struct mlx5_ifc_umr_pointer_desc_argument_bits {
b4ff3a36 7537 u8 reserved_at_0[0x20];
e281682b
SM		 7538
7539 u8 mkey[0x20];
7540
7541 u8 addressh_63_32[0x20];
7542
7543 u8 addressl_31_0[0x20];
7544};
7545
7546struct mlx5_ifc_ud_adrs_vector_bits {
7547 u8 dc_key[0x40];
7548
7549 u8 ext[0x1];
b4ff3a36 7550 u8 reserved_at_41[0x7];
e281682b
SM		 7551 u8 destination_qp_dct[0x18];
7552
7553 u8 static_rate[0x4];
7554 u8 sl_eth_prio[0x4];
7555 u8 fl[0x1];
7556 u8 mlid[0x7];
7557 u8 rlid_udp_sport[0x10];
7558
b4ff3a36 7559 u8 reserved_at_80[0x20];
e281682b
SM		 7560
7561 u8 rmac_47_16[0x20];
7562
7563 u8 rmac_15_0[0x10];
7564 u8 tclass[0x8];
7565 u8 hop_limit[0x8];
7566
b4ff3a36 7567 u8 reserved_at_e0[0x1];
e281682b 7568 u8 grh[0x1];
b4ff3a36 7569 u8 reserved_at_e2[0x2];
e281682b
SM		 7570 u8 src_addr_index[0x8];
7571 u8 flow_label[0x14];
7572
7573 u8 rgid_rip[16][0x8];
7574};
7575
7576struct mlx5_ifc_pages_req_event_bits {
b4ff3a36 7577 u8 reserved_at_0[0x10];
e281682b
SM		 7578 u8 function_id[0x10];
7579
7580 u8 num_pages[0x20];
7581
b4ff3a36 7582 u8 reserved_at_40[0xa0];
e281682b
SM		 7583};
7584
7585struct mlx5_ifc_eqe_bits {
b4ff3a36 7586 u8 reserved_at_0[0x8];
e281682b 7587 u8 event_type[0x8];
b4ff3a36 7588 u8 reserved_at_10[0x8];
e281682b
SM		 7589 u8 event_sub_type[0x8];
7590
b4ff3a36 7591 u8 reserved_at_20[0xe0];
e281682b
SM		 7592
7593 union mlx5_ifc_event_auto_bits event_data;
7594
b4ff3a36 7595 u8 reserved_at_1e0[0x10];
e281682b 7596 u8 signature[0x8];
b4ff3a36 7597 u8 reserved_at_1f8[0x7];
e281682b
SM		 7598 u8 owner[0x1];
7599};
7600
7601enum {
7602 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
7603};
7604
7605struct mlx5_ifc_cmd_queue_entry_bits {
7606 u8 type[0x8];
b4ff3a36 7607 u8 reserved_at_8[0x18];
e281682b
SM		 7608
7609 u8 input_length[0x20];
7610
7611 u8 input_mailbox_pointer_63_32[0x20];
7612
7613 u8 input_mailbox_pointer_31_9[0x17];
b4ff3a36 7614 u8 reserved_at_77[0x9];
e281682b
SM		 7615
7616 u8 command_input_inline_data[16][0x8];
7617
7618 u8 command_output_inline_data[16][0x8];
7619
7620 u8 output_mailbox_pointer_63_32[0x20];
7621
7622 u8 output_mailbox_pointer_31_9[0x17];
b4ff3a36 7623 u8 reserved_at_1b7[0x9];
e281682b
SM		 7624
7625 u8 output_length[0x20];
7626
7627 u8 token[0x8];
7628 u8 signature[0x8];
b4ff3a36 7629 u8 reserved_at_1f0[0x8];
e281682b
SM		 7630 u8 status[0x7];
7631 u8 ownership[0x1];
7632};
7633
7634struct mlx5_ifc_cmd_out_bits {
7635 u8 status[0x8];
b4ff3a36 7636 u8 reserved_at_8[0x18];
e281682b
SM		 7637
7638 u8 syndrome[0x20];
7639
7640 u8 command_output[0x20];
7641};
7642
7643struct mlx5_ifc_cmd_in_bits {
7644 u8 opcode[0x10];
b4ff3a36 7645 u8 reserved_at_10[0x10];
e281682b 7646
b4ff3a36 7647 u8 reserved_at_20[0x10];
e281682b
SM		 7648 u8 op_mod[0x10];
7649
7650 u8 command[0][0x20];
7651};
7652
7653struct mlx5_ifc_cmd_if_box_bits {
7654 u8 mailbox_data[512][0x8];
7655
b4ff3a36 7656 u8 reserved_at_1000[0x180];
e281682b
SM		 7657
7658 u8 next_pointer_63_32[0x20];
7659
7660 u8 next_pointer_31_10[0x16];
b4ff3a36 7661 u8 reserved_at_11b6[0xa];
e281682b
SM		 7662
7663 u8 block_number[0x20];
7664
b4ff3a36 7665 u8 reserved_at_11e0[0x8];
e281682b
SM		 7666 u8 token[0x8];
7667 u8 ctrl_signature[0x8];
7668 u8 signature[0x8];
7669};
7670
7671struct mlx5_ifc_mtt_bits {
7672 u8 ptag_63_32[0x20];
7673
7674 u8 ptag_31_8[0x18];
b4ff3a36 7675 u8 reserved_at_38[0x6];
e281682b
SM		 7676 u8 wr_en[0x1];
7677 u8 rd_en[0x1];
7678};
7679
928cfe87
TT		 7680struct mlx5_ifc_query_wol_rol_out_bits {
7681 u8 status[0x8];
7682 u8 reserved_at_8[0x18];
7683
7684 u8 syndrome[0x20];
7685
7686 u8 reserved_at_40[0x10];
7687 u8 rol_mode[0x8];
7688 u8 wol_mode[0x8];
7689
7690 u8 reserved_at_60[0x20];
7691};
7692
7693struct mlx5_ifc_query_wol_rol_in_bits {
7694 u8 opcode[0x10];
7695 u8 reserved_at_10[0x10];
7696
7697 u8 reserved_at_20[0x10];
7698 u8 op_mod[0x10];
7699
7700 u8 reserved_at_40[0x40];
7701};
7702
7703struct mlx5_ifc_set_wol_rol_out_bits {
7704 u8 status[0x8];
7705 u8 reserved_at_8[0x18];
7706
7707 u8 syndrome[0x20];
7708
7709 u8 reserved_at_40[0x40];
7710};
7711
7712struct mlx5_ifc_set_wol_rol_in_bits {
7713 u8 opcode[0x10];
7714 u8 reserved_at_10[0x10];
7715
7716 u8 reserved_at_20[0x10];
7717 u8 op_mod[0x10];
7718
7719 u8 rol_mode_valid[0x1];
7720 u8 wol_mode_valid[0x1];
7721 u8 reserved_at_42[0xe];
7722 u8 rol_mode[0x8];
7723 u8 wol_mode[0x8];
7724
7725 u8 reserved_at_60[0x20];
7726};
7727
e281682b
SM		 7728enum {
7729 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
7730 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
7731 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
7732};
7733
7734enum {
7735 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
7736 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
7737 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
7738};
7739
7740enum {
7741 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
7742 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
7743 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
7744 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
7745 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
7746 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
7747 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
7748 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
7749 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
7750 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
7751 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
7752};
7753
7754struct mlx5_ifc_initial_seg_bits {
7755 u8 fw_rev_minor[0x10];
7756 u8 fw_rev_major[0x10];
7757
7758 u8 cmd_interface_rev[0x10];
7759 u8 fw_rev_subminor[0x10];
7760
b4ff3a36 7761 u8 reserved_at_40[0x40];
e281682b
SM		 7762
7763 u8 cmdq_phy_addr_63_32[0x20];
7764
7765 u8 cmdq_phy_addr_31_12[0x14];
b4ff3a36 7766 u8 reserved_at_b4[0x2];
e281682b
SM		 7767 u8 nic_interface[0x2];
7768 u8 log_cmdq_size[0x4];
7769 u8 log_cmdq_stride[0x4];
7770
7771 u8 command_doorbell_vector[0x20];
7772
b4ff3a36 7773 u8 reserved_at_e0[0xf00];
e281682b
SM		 7774
7775 u8 initializing[0x1];
b4ff3a36 7776 u8 reserved_at_fe1[0x4];
e281682b 7777 u8 nic_interface_supported[0x3];
b4ff3a36 7778 u8 reserved_at_fe8[0x18];
e281682b
SM		 7779
7780 struct mlx5_ifc_health_buffer_bits health_buffer;
7781
7782 u8 no_dram_nic_offset[0x20];
7783
b4ff3a36 7784 u8 reserved_at_1220[0x6e40];
e281682b 7785
b4ff3a36 7786 u8 reserved_at_8060[0x1f];
e281682b
SM		 7787 u8 clear_int[0x1];
7788
7789 u8 health_syndrome[0x8];
7790 u8 health_counter[0x18];
7791
b4ff3a36 7792 u8 reserved_at_80a0[0x17fc0];
e281682b
SM		 7793};
7794
7795union mlx5_ifc_ports_control_registers_document_bits {
7796 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
7797 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
7798 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
7799 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
7800 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
7801 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
7802 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
7803 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
7804 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
7805 struct mlx5_ifc_pamp_reg_bits pamp_reg;
7806 struct mlx5_ifc_paos_reg_bits paos_reg;
7807 struct mlx5_ifc_pcap_reg_bits pcap_reg;
7808 struct mlx5_ifc_peir_reg_bits peir_reg;
7809 struct mlx5_ifc_pelc_reg_bits pelc_reg;
7810 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
1c64bf6f 7811 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b
SM		 7812 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
7813 struct mlx5_ifc_pifr_reg_bits pifr_reg;
7814 struct mlx5_ifc_pipg_reg_bits pipg_reg;
7815 struct mlx5_ifc_plbf_reg_bits plbf_reg;
7816 struct mlx5_ifc_plib_reg_bits plib_reg;
7817 struct mlx5_ifc_plpc_reg_bits plpc_reg;
7818 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
7819 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
7820 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
7821 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
7822 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
7823 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
7824 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
7825 struct mlx5_ifc_ppad_reg_bits ppad_reg;
7826 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
7827 struct mlx5_ifc_pplm_reg_bits pplm_reg;
7828 struct mlx5_ifc_pplr_reg_bits pplr_reg;
7829 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
7830 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
7831 struct mlx5_ifc_pspa_reg_bits pspa_reg;
7832 struct mlx5_ifc_ptas_reg_bits ptas_reg;
7833 struct mlx5_ifc_ptys_reg_bits ptys_reg;
7d5e1423 7834 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
e281682b
SM		 7835 struct mlx5_ifc_pude_reg_bits pude_reg;
7836 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
7837 struct mlx5_ifc_slrg_reg_bits slrg_reg;
7838 struct mlx5_ifc_sltp_reg_bits sltp_reg;
b4ff3a36 7839 u8 reserved_at_0[0x60e0];
e281682b
SM		 7840};
7841
7842union mlx5_ifc_debug_enhancements_document_bits {
7843 struct mlx5_ifc_health_buffer_bits health_buffer;
b4ff3a36 7844 u8 reserved_at_0[0x200];
e281682b
SM		 7845};
7846
7847union mlx5_ifc_uplink_pci_interface_document_bits {
7848 struct mlx5_ifc_initial_seg_bits initial_seg;
b4ff3a36 7849 u8 reserved_at_0[0x20060];
b775516b
EC		 7850};
7851
2cc43b49
MG		 7852struct mlx5_ifc_set_flow_table_root_out_bits {
7853 u8 status[0x8];
b4ff3a36 7854 u8 reserved_at_8[0x18];
2cc43b49
MG		 7855
7856 u8 syndrome[0x20];
7857
b4ff3a36 7858 u8 reserved_at_40[0x40];
2cc43b49
MG		 7859};
7860
7861struct mlx5_ifc_set_flow_table_root_in_bits {
7862 u8 opcode[0x10];
b4ff3a36 7863 u8 reserved_at_10[0x10];
2cc43b49 7864
b4ff3a36 7865 u8 reserved_at_20[0x10];
2cc43b49
MG		 7866 u8 op_mod[0x10];
7867
7d5e1423
SM		 7868 u8 other_vport[0x1];
7869 u8 reserved_at_41[0xf];
7870 u8 vport_number[0x10];
7871
7872 u8 reserved_at_60[0x20];
2cc43b49
MG		 7873
7874 u8 table_type[0x8];
b4ff3a36 7875 u8 reserved_at_88[0x18];
2cc43b49 7876
b4ff3a36 7877 u8 reserved_at_a0[0x8];
2cc43b49
MG		 7878 u8 table_id[0x18];
7879
b4ff3a36 7880 u8 reserved_at_c0[0x140];
2cc43b49
MG		 7881};
7882
34a40e68 7883enum {
84df61eb
AH		 7884 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
7885 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
34a40e68
MG		 7886};
7887
7888struct mlx5_ifc_modify_flow_table_out_bits {
7889 u8 status[0x8];
b4ff3a36 7890 u8 reserved_at_8[0x18];
34a40e68
MG		 7891
7892 u8 syndrome[0x20];
7893
b4ff3a36 7894 u8 reserved_at_40[0x40];
34a40e68
MG		 7895};
7896
7897struct mlx5_ifc_modify_flow_table_in_bits {
7898 u8 opcode[0x10];
b4ff3a36 7899 u8 reserved_at_10[0x10];
34a40e68 7900
b4ff3a36 7901 u8 reserved_at_20[0x10];
34a40e68
MG		 7902 u8 op_mod[0x10];
7903
7d5e1423
SM		 7904 u8 other_vport[0x1];
7905 u8 reserved_at_41[0xf];
7906 u8 vport_number[0x10];
34a40e68 7907
b4ff3a36 7908 u8 reserved_at_60[0x10];
34a40e68
MG		 7909 u8 modify_field_select[0x10];
7910
7911 u8 table_type[0x8];
b4ff3a36 7912 u8 reserved_at_88[0x18];
34a40e68 7913
b4ff3a36 7914 u8 reserved_at_a0[0x8];
34a40e68
MG		 7915 u8 table_id[0x18];
7916
b4ff3a36 7917 u8 reserved_at_c0[0x4];
34a40e68 7918 u8 table_miss_mode[0x4];
b4ff3a36 7919 u8 reserved_at_c8[0x18];
34a40e68 7920
b4ff3a36 7921 u8 reserved_at_e0[0x8];
34a40e68
MG		 7922 u8 table_miss_id[0x18];
7923
84df61eb
AH		 7924 u8 reserved_at_100[0x8];
7925 u8 lag_master_next_table_id[0x18];
7926
7927 u8 reserved_at_120[0x80];
34a40e68
MG		 7928};
7929
4f3961ee
SM		 7930struct mlx5_ifc_ets_tcn_config_reg_bits {
7931 u8 g[0x1];
7932 u8 b[0x1];
7933 u8 r[0x1];
7934 u8 reserved_at_3[0x9];
7935 u8 group[0x4];
7936 u8 reserved_at_10[0x9];
7937 u8 bw_allocation[0x7];
7938
7939 u8 reserved_at_20[0xc];
7940 u8 max_bw_units[0x4];
7941 u8 reserved_at_30[0x8];
7942 u8 max_bw_value[0x8];
7943};
7944
7945struct mlx5_ifc_ets_global_config_reg_bits {
7946 u8 reserved_at_0[0x2];
7947 u8 r[0x1];
7948 u8 reserved_at_3[0x1d];
7949
7950 u8 reserved_at_20[0xc];
7951 u8 max_bw_units[0x4];
7952 u8 reserved_at_30[0x8];
7953 u8 max_bw_value[0x8];
7954};
7955
7956struct mlx5_ifc_qetc_reg_bits {
7957 u8 reserved_at_0[0x8];
7958 u8 port_number[0x8];
7959 u8 reserved_at_10[0x30];
7960
7961 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
7962 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
7963};
7964
7965struct mlx5_ifc_qtct_reg_bits {
7966 u8 reserved_at_0[0x8];
7967 u8 port_number[0x8];
7968 u8 reserved_at_10[0xd];
7969 u8 prio[0x3];
7970
7971 u8 reserved_at_20[0x1d];
7972 u8 tclass[0x3];
7973};
7974
7d5e1423
SM		 7975struct mlx5_ifc_mcia_reg_bits {
7976 u8 l[0x1];
7977 u8 reserved_at_1[0x7];
7978 u8 module[0x8];
7979 u8 reserved_at_10[0x8];
7980 u8 status[0x8];
7981
7982 u8 i2c_device_address[0x8];
7983 u8 page_number[0x8];
7984 u8 device_address[0x10];
7985
7986 u8 reserved_at_40[0x10];
7987 u8 size[0x10];
7988
7989 u8 reserved_at_60[0x20];
7990
7991 u8 dword_0[0x20];
7992 u8 dword_1[0x20];
7993 u8 dword_2[0x20];
7994 u8 dword_3[0x20];
7995 u8 dword_4[0x20];
7996 u8 dword_5[0x20];
7997 u8 dword_6[0x20];
7998 u8 dword_7[0x20];
7999 u8 dword_8[0x20];
8000 u8 dword_9[0x20];
8001 u8 dword_10[0x20];
8002 u8 dword_11[0x20];
8003};
8004
7486216b
SM		 8005struct mlx5_ifc_dcbx_param_bits {
8006 u8 dcbx_cee_cap[0x1];
8007 u8 dcbx_ieee_cap[0x1];
8008 u8 dcbx_standby_cap[0x1];
8009 u8 reserved_at_0[0x5];
8010 u8 port_number[0x8];
8011 u8 reserved_at_10[0xa];
8012 u8 max_application_table_size[6];
8013 u8 reserved_at_20[0x15];
8014 u8 version_oper[0x3];
8015 u8 reserved_at_38[5];
8016 u8 version_admin[0x3];
8017 u8 willing_admin[0x1];
8018 u8 reserved_at_41[0x3];
8019 u8 pfc_cap_oper[0x4];
8020 u8 reserved_at_48[0x4];
8021 u8 pfc_cap_admin[0x4];
8022 u8 reserved_at_50[0x4];
8023 u8 num_of_tc_oper[0x4];
8024 u8 reserved_at_58[0x4];
8025 u8 num_of_tc_admin[0x4];
8026 u8 remote_willing[0x1];
8027 u8 reserved_at_61[3];
8028 u8 remote_pfc_cap[4];
8029 u8 reserved_at_68[0x14];
8030 u8 remote_num_of_tc[0x4];
8031 u8 reserved_at_80[0x18];
8032 u8 error[0x8];
8033 u8 reserved_at_a0[0x160];
8034};
84df61eb
AH		 8035
8036struct mlx5_ifc_lagc_bits {
8037 u8 reserved_at_0[0x1d];
8038 u8 lag_state[0x3];
8039
8040 u8 reserved_at_20[0x14];
8041 u8 tx_remap_affinity_2[0x4];
8042 u8 reserved_at_38[0x4];
8043 u8 tx_remap_affinity_1[0x4];
8044};
8045
8046struct mlx5_ifc_create_lag_out_bits {
8047 u8 status[0x8];
8048 u8 reserved_at_8[0x18];
8049
8050 u8 syndrome[0x20];
8051
8052 u8 reserved_at_40[0x40];
8053};
8054
8055struct mlx5_ifc_create_lag_in_bits {
8056 u8 opcode[0x10];
8057 u8 reserved_at_10[0x10];
8058
8059 u8 reserved_at_20[0x10];
8060 u8 op_mod[0x10];
8061
8062 struct mlx5_ifc_lagc_bits ctx;
8063};
8064
8065struct mlx5_ifc_modify_lag_out_bits {
8066 u8 status[0x8];
8067 u8 reserved_at_8[0x18];
8068
8069 u8 syndrome[0x20];
8070
8071 u8 reserved_at_40[0x40];
8072};
8073
8074struct mlx5_ifc_modify_lag_in_bits {
8075 u8 opcode[0x10];
8076 u8 reserved_at_10[0x10];
8077
8078 u8 reserved_at_20[0x10];
8079 u8 op_mod[0x10];
8080
8081 u8 reserved_at_40[0x20];
8082 u8 field_select[0x20];
8083
8084 struct mlx5_ifc_lagc_bits ctx;
8085};
8086
8087struct mlx5_ifc_query_lag_out_bits {
8088 u8 status[0x8];
8089 u8 reserved_at_8[0x18];
8090
8091 u8 syndrome[0x20];
8092
8093 u8 reserved_at_40[0x40];
8094
8095 struct mlx5_ifc_lagc_bits ctx;
8096};
8097
8098struct mlx5_ifc_query_lag_in_bits {
8099 u8 opcode[0x10];
8100 u8 reserved_at_10[0x10];
8101
8102 u8 reserved_at_20[0x10];
8103 u8 op_mod[0x10];
8104
8105 u8 reserved_at_40[0x40];
8106};
8107
8108struct mlx5_ifc_destroy_lag_out_bits {
8109 u8 status[0x8];
8110 u8 reserved_at_8[0x18];
8111
8112 u8 syndrome[0x20];
8113
8114 u8 reserved_at_40[0x40];
8115};
8116
8117struct mlx5_ifc_destroy_lag_in_bits {
8118 u8 opcode[0x10];
8119 u8 reserved_at_10[0x10];
8120
8121 u8 reserved_at_20[0x10];
8122 u8 op_mod[0x10];
8123
8124 u8 reserved_at_40[0x40];
8125};
8126
8127struct mlx5_ifc_create_vport_lag_out_bits {
8128 u8 status[0x8];
8129 u8 reserved_at_8[0x18];
8130
8131 u8 syndrome[0x20];
8132
8133 u8 reserved_at_40[0x40];
8134};
8135
8136struct mlx5_ifc_create_vport_lag_in_bits {
8137 u8 opcode[0x10];
8138 u8 reserved_at_10[0x10];
8139
8140 u8 reserved_at_20[0x10];
8141 u8 op_mod[0x10];
8142
8143 u8 reserved_at_40[0x40];
8144};
8145
8146struct mlx5_ifc_destroy_vport_lag_out_bits {
8147 u8 status[0x8];
8148 u8 reserved_at_8[0x18];
8149
8150 u8 syndrome[0x20];
8151
8152 u8 reserved_at_40[0x40];
8153};
8154
8155struct mlx5_ifc_destroy_vport_lag_in_bits {
8156 u8 opcode[0x10];
8157 u8 reserved_at_10[0x10];
8158
8159 u8 reserved_at_20[0x10];
8160 u8 op_mod[0x10];
8161
8162 u8 reserved_at_40[0x40];
8163};
8164
d29b796a 8165#endif /* MLX5_IFC_H */
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