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net/mlx5: Update eqe_type_str() event names
[mirror_ubuntu-bionic-kernel.git] / include / linux / mlx5 / mlx5_ifc.h
CommitLineData
d29b796a 1/*
e281682b 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
d29b796a
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
e281682b 31*/
d29b796a
EC		 32#ifndef MLX5_IFC_H
33#define MLX5_IFC_H
34
e29341fb
IT		 35#include "mlx5_ifc_fpga.h"
36
e281682b
SM		 37enum {
38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
e29341fb
IT		 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb,
62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20,
e281682b
SM		 63};
64
65enum {
66 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
67 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
68 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
69 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
70};
71
f91e6d89
EBE		 72enum {
73 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
74 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
75};
76
d29b796a
EC		 77enum {
78 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
79 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
80 MLX5_CMD_OP_INIT_HCA = 0x102,
81 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
82 MLX5_CMD_OP_ENABLE_HCA = 0x104,
83 MLX5_CMD_OP_DISABLE_HCA = 0x105,
84 MLX5_CMD_OP_QUERY_PAGES = 0x107,
85 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
86 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
e281682b
SM		 87 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
88 MLX5_CMD_OP_SET_ISSI = 0x10b,
0dbc6fe0 89 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
d29b796a
EC		 90 MLX5_CMD_OP_CREATE_MKEY = 0x200,
91 MLX5_CMD_OP_QUERY_MKEY = 0x201,
92 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
93 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
94 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
95 MLX5_CMD_OP_CREATE_EQ = 0x301,
96 MLX5_CMD_OP_DESTROY_EQ = 0x302,
97 MLX5_CMD_OP_QUERY_EQ = 0x303,
98 MLX5_CMD_OP_GEN_EQE = 0x304,
99 MLX5_CMD_OP_CREATE_CQ = 0x400,
100 MLX5_CMD_OP_DESTROY_CQ = 0x401,
101 MLX5_CMD_OP_QUERY_CQ = 0x402,
102 MLX5_CMD_OP_MODIFY_CQ = 0x403,
103 MLX5_CMD_OP_CREATE_QP = 0x500,
104 MLX5_CMD_OP_DESTROY_QP = 0x501,
105 MLX5_CMD_OP_RST2INIT_QP = 0x502,
106 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
107 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
108 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
109 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
110 MLX5_CMD_OP_2ERR_QP = 0x507,
111 MLX5_CMD_OP_2RST_QP = 0x50a,
112 MLX5_CMD_OP_QUERY_QP = 0x50b,
e281682b 113 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
d29b796a
EC		 114 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
115 MLX5_CMD_OP_CREATE_PSV = 0x600,
116 MLX5_CMD_OP_DESTROY_PSV = 0x601,
117 MLX5_CMD_OP_CREATE_SRQ = 0x700,
118 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
119 MLX5_CMD_OP_QUERY_SRQ = 0x702,
120 MLX5_CMD_OP_ARM_RQ = 0x703,
e281682b
SM		 121 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
122 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
123 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
124 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
d29b796a
EC		 125 MLX5_CMD_OP_CREATE_DCT = 0x710,
126 MLX5_CMD_OP_DESTROY_DCT = 0x711,
127 MLX5_CMD_OP_DRAIN_DCT = 0x712,
128 MLX5_CMD_OP_QUERY_DCT = 0x713,
129 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
7486216b
SM		 130 MLX5_CMD_OP_CREATE_XRQ = 0x717,
131 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
132 MLX5_CMD_OP_QUERY_XRQ = 0x719,
133 MLX5_CMD_OP_ARM_XRQ = 0x71a,
d29b796a
EC		 134 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
135 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
136 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
137 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
138 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
139 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
e281682b 140 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
d29b796a 141 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
e281682b
SM		 142 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
143 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
144 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
145 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
d29b796a
EC		 146 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
147 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
148 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
149 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
7486216b
SM		 150 MLX5_CMD_OP_SET_RATE_LIMIT = 0x780,
151 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
813f8540
MHY		 152 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
153 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
154 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
155 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
156 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
157 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
d29b796a
EC		 158 MLX5_CMD_OP_ALLOC_PD = 0x800,
159 MLX5_CMD_OP_DEALLOC_PD = 0x801,
160 MLX5_CMD_OP_ALLOC_UAR = 0x802,
161 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
162 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
163 MLX5_CMD_OP_ACCESS_REG = 0x805,
164 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
20bb566b 165 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
d29b796a
EC		 166 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
167 MLX5_CMD_OP_MAD_IFC = 0x50d,
168 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
169 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
170 MLX5_CMD_OP_NOP = 0x80d,
171 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
172 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
e281682b
SM		 173 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
174 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
175 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
176 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
177 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
178 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
179 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
180 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
181 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
182 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
183 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
184 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
928cfe87
TT		 185 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
186 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
84df61eb
AH		 187 MLX5_CMD_OP_CREATE_LAG = 0x840,
188 MLX5_CMD_OP_MODIFY_LAG = 0x841,
189 MLX5_CMD_OP_QUERY_LAG = 0x842,
190 MLX5_CMD_OP_DESTROY_LAG = 0x843,
191 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
192 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
d29b796a
EC		 193 MLX5_CMD_OP_CREATE_TIR = 0x900,
194 MLX5_CMD_OP_MODIFY_TIR = 0x901,
195 MLX5_CMD_OP_DESTROY_TIR = 0x902,
196 MLX5_CMD_OP_QUERY_TIR = 0x903,
d29b796a
EC		 197 MLX5_CMD_OP_CREATE_SQ = 0x904,
198 MLX5_CMD_OP_MODIFY_SQ = 0x905,
199 MLX5_CMD_OP_DESTROY_SQ = 0x906,
200 MLX5_CMD_OP_QUERY_SQ = 0x907,
201 MLX5_CMD_OP_CREATE_RQ = 0x908,
202 MLX5_CMD_OP_MODIFY_RQ = 0x909,
203 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
204 MLX5_CMD_OP_QUERY_RQ = 0x90b,
205 MLX5_CMD_OP_CREATE_RMP = 0x90c,
206 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
207 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
208 MLX5_CMD_OP_QUERY_RMP = 0x90f,
e281682b
SM		 209 MLX5_CMD_OP_CREATE_TIS = 0x912,
210 MLX5_CMD_OP_MODIFY_TIS = 0x913,
211 MLX5_CMD_OP_DESTROY_TIS = 0x914,
212 MLX5_CMD_OP_QUERY_TIS = 0x915,
213 MLX5_CMD_OP_CREATE_RQT = 0x916,
214 MLX5_CMD_OP_MODIFY_RQT = 0x917,
215 MLX5_CMD_OP_DESTROY_RQT = 0x918,
216 MLX5_CMD_OP_QUERY_RQT = 0x919,
2cc43b49 217 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
e281682b
SM		 218 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
219 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
220 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
221 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
222 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
223 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
224 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
225 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
34a40e68 226 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
9dc0b289
AV		 227 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
228 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
229 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
86d56a1a 230 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
7adbde20
HHZ		 231 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d,
232 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e,
2a69cb9f
OG		 233 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940,
234 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
86d56a1a 235 MLX5_CMD_OP_MAX
e281682b
SM		 236};
237
238struct mlx5_ifc_flow_table_fields_supported_bits {
239 u8 outer_dmac[0x1];
240 u8 outer_smac[0x1];
241 u8 outer_ether_type[0x1];
19cc7524 242 u8 outer_ip_version[0x1];
e281682b
SM		 243 u8 outer_first_prio[0x1];
244 u8 outer_first_cfi[0x1];
245 u8 outer_first_vid[0x1];
b4ff3a36 246 u8 reserved_at_7[0x1];
e281682b
SM		 247 u8 outer_second_prio[0x1];
248 u8 outer_second_cfi[0x1];
249 u8 outer_second_vid[0x1];
b4ff3a36 250 u8 reserved_at_b[0x1];
e281682b
SM		 251 u8 outer_sip[0x1];
252 u8 outer_dip[0x1];
253 u8 outer_frag[0x1];
254 u8 outer_ip_protocol[0x1];
255 u8 outer_ip_ecn[0x1];
256 u8 outer_ip_dscp[0x1];
257 u8 outer_udp_sport[0x1];
258 u8 outer_udp_dport[0x1];
259 u8 outer_tcp_sport[0x1];
260 u8 outer_tcp_dport[0x1];
261 u8 outer_tcp_flags[0x1];
262 u8 outer_gre_protocol[0x1];
263 u8 outer_gre_key[0x1];
264 u8 outer_vxlan_vni[0x1];
b4ff3a36 265 u8 reserved_at_1a[0x5];
e281682b
SM		 266 u8 source_eswitch_port[0x1];
267
268 u8 inner_dmac[0x1];
269 u8 inner_smac[0x1];
270 u8 inner_ether_type[0x1];
19cc7524 271 u8 inner_ip_version[0x1];
e281682b
SM		 272 u8 inner_first_prio[0x1];
273 u8 inner_first_cfi[0x1];
274 u8 inner_first_vid[0x1];
b4ff3a36 275 u8 reserved_at_27[0x1];
e281682b
SM		 276 u8 inner_second_prio[0x1];
277 u8 inner_second_cfi[0x1];
278 u8 inner_second_vid[0x1];
b4ff3a36 279 u8 reserved_at_2b[0x1];
e281682b
SM		 280 u8 inner_sip[0x1];
281 u8 inner_dip[0x1];
282 u8 inner_frag[0x1];
283 u8 inner_ip_protocol[0x1];
284 u8 inner_ip_ecn[0x1];
285 u8 inner_ip_dscp[0x1];
286 u8 inner_udp_sport[0x1];
287 u8 inner_udp_dport[0x1];
288 u8 inner_tcp_sport[0x1];
289 u8 inner_tcp_dport[0x1];
290 u8 inner_tcp_flags[0x1];
b4ff3a36 291 u8 reserved_at_37[0x9];
e281682b 292
b4ff3a36 293 u8 reserved_at_40[0x40];
e281682b
SM		 294};
295
296struct mlx5_ifc_flow_table_prop_layout_bits {
297 u8 ft_support[0x1];
9dc0b289
AV		 298 u8 reserved_at_1[0x1];
299 u8 flow_counter[0x1];
26a81453 300 u8 flow_modify_en[0x1];
2cc43b49 301 u8 modify_root[0x1];
34a40e68
MG		 302 u8 identified_miss_table_mode[0x1];
303 u8 flow_table_modify[0x1];
7adbde20
HHZ		 304 u8 encap[0x1];
305 u8 decap[0x1];
306 u8 reserved_at_9[0x17];
e281682b 307
b4ff3a36 308 u8 reserved_at_20[0x2];
e281682b 309 u8 log_max_ft_size[0x6];
2a69cb9f
OG		 310 u8 log_max_modify_header_context[0x8];
311 u8 max_modify_header_actions[0x8];
e281682b
SM		 312 u8 max_ft_level[0x8];
313
b4ff3a36 314 u8 reserved_at_40[0x20];
e281682b 315
b4ff3a36 316 u8 reserved_at_60[0x18];
e281682b
SM		 317 u8 log_max_ft_num[0x8];
318
b4ff3a36 319 u8 reserved_at_80[0x18];
e281682b
SM		 320 u8 log_max_destination[0x8];
321
b4ff3a36 322 u8 reserved_at_a0[0x18];
e281682b
SM		 323 u8 log_max_flow[0x8];
324
b4ff3a36 325 u8 reserved_at_c0[0x40];
e281682b
SM		 326
327 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
328
329 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
330};
331
332struct mlx5_ifc_odp_per_transport_service_cap_bits {
333 u8 send[0x1];
334 u8 receive[0x1];
335 u8 write[0x1];
336 u8 read[0x1];
17d2f88f 337 u8 atomic[0x1];
e281682b 338 u8 srq_receive[0x1];
b4ff3a36 339 u8 reserved_at_6[0x1a];
e281682b
SM		 340};
341
b4d1f032 342struct mlx5_ifc_ipv4_layout_bits {
b4ff3a36 343 u8 reserved_at_0[0x60];
b4d1f032
MG		 344
345 u8 ipv4[0x20];
346};
347
348struct mlx5_ifc_ipv6_layout_bits {
349 u8 ipv6[16][0x8];
350};
351
352union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
353 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
354 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
b4ff3a36 355 u8 reserved_at_0[0x80];
b4d1f032
MG		 356};
357
e281682b
SM		 358struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
359 u8 smac_47_16[0x20];
360
361 u8 smac_15_0[0x10];
362 u8 ethertype[0x10];
363
364 u8 dmac_47_16[0x20];
365
366 u8 dmac_15_0[0x10];
367 u8 first_prio[0x3];
368 u8 first_cfi[0x1];
369 u8 first_vid[0xc];
370
371 u8 ip_protocol[0x8];
372 u8 ip_dscp[0x6];
373 u8 ip_ecn[0x2];
10543365
MHY		 374 u8 cvlan_tag[0x1];
375 u8 svlan_tag[0x1];
e281682b 376 u8 frag[0x1];
19cc7524 377 u8 ip_version[0x4];
e281682b
SM		 378 u8 tcp_flags[0x9];
379
380 u8 tcp_sport[0x10];
381 u8 tcp_dport[0x10];
382
b4ff3a36 383 u8 reserved_at_c0[0x20];
e281682b
SM		 384
385 u8 udp_sport[0x10];
386 u8 udp_dport[0x10];
387
b4d1f032 388 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
e281682b 389
b4d1f032 390 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
e281682b
SM		 391};
392
393struct mlx5_ifc_fte_match_set_misc_bits {
7486216b
SM		 394 u8 reserved_at_0[0x8];
395 u8 source_sqn[0x18];
e281682b 396
b4ff3a36 397 u8 reserved_at_20[0x10];
e281682b
SM		 398 u8 source_port[0x10];
399
400 u8 outer_second_prio[0x3];
401 u8 outer_second_cfi[0x1];
402 u8 outer_second_vid[0xc];
403 u8 inner_second_prio[0x3];
404 u8 inner_second_cfi[0x1];
405 u8 inner_second_vid[0xc];
406
10543365
MHY		 407 u8 outer_second_cvlan_tag[0x1];
408 u8 inner_second_cvlan_tag[0x1];
409 u8 outer_second_svlan_tag[0x1];
410 u8 inner_second_svlan_tag[0x1];
411 u8 reserved_at_64[0xc];
e281682b
SM		 412 u8 gre_protocol[0x10];
413
414 u8 gre_key_h[0x18];
415 u8 gre_key_l[0x8];
416
417 u8 vxlan_vni[0x18];
b4ff3a36 418 u8 reserved_at_b8[0x8];
e281682b 419
b4ff3a36 420 u8 reserved_at_c0[0x20];
e281682b 421
b4ff3a36 422 u8 reserved_at_e0[0xc];
e281682b
SM		 423 u8 outer_ipv6_flow_label[0x14];
424
b4ff3a36 425 u8 reserved_at_100[0xc];
e281682b
SM		 426 u8 inner_ipv6_flow_label[0x14];
427
b4ff3a36 428 u8 reserved_at_120[0xe0];
e281682b
SM		 429};
430
431struct mlx5_ifc_cmd_pas_bits {
432 u8 pa_h[0x20];
433
434 u8 pa_l[0x14];
b4ff3a36 435 u8 reserved_at_34[0xc];
e281682b
SM		 436};
437
438struct mlx5_ifc_uint64_bits {
439 u8 hi[0x20];
440
441 u8 lo[0x20];
442};
443
444enum {
445 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
446 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
447 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
448 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
449 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
450 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
451 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
452 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
453 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
454 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
455};
456
457struct mlx5_ifc_ads_bits {
458 u8 fl[0x1];
459 u8 free_ar[0x1];
b4ff3a36 460 u8 reserved_at_2[0xe];
e281682b
SM		 461 u8 pkey_index[0x10];
462
b4ff3a36 463 u8 reserved_at_20[0x8];
e281682b
SM		 464 u8 grh[0x1];
465 u8 mlid[0x7];
466 u8 rlid[0x10];
467
468 u8 ack_timeout[0x5];
b4ff3a36 469 u8 reserved_at_45[0x3];
e281682b 470 u8 src_addr_index[0x8];
b4ff3a36 471 u8 reserved_at_50[0x4];
e281682b
SM		 472 u8 stat_rate[0x4];
473 u8 hop_limit[0x8];
474
b4ff3a36 475 u8 reserved_at_60[0x4];
e281682b
SM		 476 u8 tclass[0x8];
477 u8 flow_label[0x14];
478
479 u8 rgid_rip[16][0x8];
480
b4ff3a36 481 u8 reserved_at_100[0x4];
e281682b
SM		 482 u8 f_dscp[0x1];
483 u8 f_ecn[0x1];
b4ff3a36 484 u8 reserved_at_106[0x1];
e281682b
SM		 485 u8 f_eth_prio[0x1];
486 u8 ecn[0x2];
487 u8 dscp[0x6];
488 u8 udp_sport[0x10];
489
490 u8 dei_cfi[0x1];
491 u8 eth_prio[0x3];
492 u8 sl[0x4];
493 u8 port[0x8];
494 u8 rmac_47_32[0x10];
495
496 u8 rmac_31_0[0x20];
497};
498
499struct mlx5_ifc_flow_table_nic_cap_bits {
b3638e1a 500 u8 nic_rx_multi_path_tirs[0x1];
cea824d4
MG		 501 u8 nic_rx_multi_path_tirs_fts[0x1];
502 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
503 u8 reserved_at_3[0x1fd];
e281682b
SM		 504
505 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
506
b4ff3a36 507 u8 reserved_at_400[0x200];
e281682b
SM		 508
509 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
510
511 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
512
b4ff3a36 513 u8 reserved_at_a00[0x200];
e281682b
SM		 514
515 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
516
b4ff3a36 517 u8 reserved_at_e00[0x7200];
e281682b
SM		 518};
519
495716b1 520struct mlx5_ifc_flow_table_eswitch_cap_bits {
b4ff3a36 521 u8 reserved_at_0[0x200];
495716b1
SM		 522
523 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
524
525 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
526
527 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
528
b4ff3a36 529 u8 reserved_at_800[0x7800];
495716b1
SM		 530};
531
d6666753
SM		 532struct mlx5_ifc_e_switch_cap_bits {
533 u8 vport_svlan_strip[0x1];
534 u8 vport_cvlan_strip[0x1];
535 u8 vport_svlan_insert[0x1];
536 u8 vport_cvlan_insert_if_not_exist[0x1];
537 u8 vport_cvlan_insert_overwrite[0x1];
23898c76
NO		 538 u8 reserved_at_5[0x19];
539 u8 nic_vport_node_guid_modify[0x1];
540 u8 nic_vport_port_guid_modify[0x1];
d6666753 541
7adbde20
HHZ		 542 u8 vxlan_encap_decap[0x1];
543 u8 nvgre_encap_decap[0x1];
544 u8 reserved_at_22[0x9];
545 u8 log_max_encap_headers[0x5];
546 u8 reserved_2b[0x6];
547 u8 max_encap_header_size[0xa];
548
549 u8 reserved_40[0x7c0];
550
d6666753
SM		 551};
552
7486216b
SM		 553struct mlx5_ifc_qos_cap_bits {
554 u8 packet_pacing[0x1];
813f8540 555 u8 esw_scheduling[0x1];
c9497c98
MHY		 556 u8 esw_bw_share[0x1];
557 u8 esw_rate_limit[0x1];
558 u8 reserved_at_4[0x1c];
813f8540
MHY		 559
560 u8 reserved_at_20[0x20];
561
7486216b 562 u8 packet_pacing_max_rate[0x20];
813f8540 563
7486216b 564 u8 packet_pacing_min_rate[0x20];
813f8540
MHY		 565
566 u8 reserved_at_80[0x10];
7486216b 567 u8 packet_pacing_rate_table_size[0x10];
813f8540
MHY		 568
569 u8 esw_element_type[0x10];
570 u8 esw_tsar_type[0x10];
571
572 u8 reserved_at_c0[0x10];
573 u8 max_qos_para_vport[0x10];
574
575 u8 max_tsar_bw_share[0x20];
576
577 u8 reserved_at_100[0x700];
7486216b
SM		 578};
579
e281682b
SM		 580struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
581 u8 csum_cap[0x1];
582 u8 vlan_cap[0x1];
583 u8 lro_cap[0x1];
584 u8 lro_psh_flag[0x1];
585 u8 lro_time_stamp[0x1];
2b31f7ae
SM		 586 u8 reserved_at_5[0x2];
587 u8 wqe_vlan_insert[0x1];
66189961 588 u8 self_lb_en_modifiable[0x1];
b4ff3a36 589 u8 reserved_at_9[0x2];
e281682b 590 u8 max_lso_cap[0x5];
c226dc22 591 u8 multi_pkt_send_wqe[0x2];
cff92d7c 592 u8 wqe_inline_mode[0x2];
e281682b 593 u8 rss_ind_tbl_cap[0x4];
7d5e1423
SM		 594 u8 reg_umr_sq[0x1];
595 u8 scatter_fcs[0x1];
596 u8 reserved_at_1a[0x1];
e281682b 597 u8 tunnel_lso_const_out_ip_id[0x1];
b4ff3a36 598 u8 reserved_at_1c[0x2];
e281682b
SM		 599 u8 tunnel_statless_gre[0x1];
600 u8 tunnel_stateless_vxlan[0x1];
601
b4ff3a36 602 u8 reserved_at_20[0x20];
e281682b 603
b4ff3a36 604 u8 reserved_at_40[0x10];
e281682b
SM		 605 u8 lro_min_mss_size[0x10];
606
b4ff3a36 607 u8 reserved_at_60[0x120];
e281682b
SM		 608
609 u8 lro_timer_supported_periods[4][0x20];
610
b4ff3a36 611 u8 reserved_at_200[0x600];
e281682b
SM		 612};
613
614struct mlx5_ifc_roce_cap_bits {
615 u8 roce_apm[0x1];
b4ff3a36 616 u8 reserved_at_1[0x1f];
e281682b 617
b4ff3a36 618 u8 reserved_at_20[0x60];
e281682b 619
b4ff3a36 620 u8 reserved_at_80[0xc];
e281682b 621 u8 l3_type[0x4];
b4ff3a36 622 u8 reserved_at_90[0x8];
e281682b
SM		 623 u8 roce_version[0x8];
624
b4ff3a36 625 u8 reserved_at_a0[0x10];
e281682b
SM		 626 u8 r_roce_dest_udp_port[0x10];
627
628 u8 r_roce_max_src_udp_port[0x10];
629 u8 r_roce_min_src_udp_port[0x10];
630
b4ff3a36 631 u8 reserved_at_e0[0x10];
e281682b
SM		 632 u8 roce_address_table_size[0x10];
633
b4ff3a36 634 u8 reserved_at_100[0x700];
e281682b
SM		 635};
636
637enum {
638 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
639 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
640 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
641 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
642 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
643 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
644 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
645 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
646 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
647};
648
649enum {
650 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
651 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
652 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
653 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
654 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
655 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
656 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
657 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
658 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
659};
660
661struct mlx5_ifc_atomic_caps_bits {
b4ff3a36 662 u8 reserved_at_0[0x40];
e281682b 663
f91e6d89 664 u8 atomic_req_8B_endianess_mode[0x2];
b4ff3a36 665 u8 reserved_at_42[0x4];
f91e6d89 666 u8 supported_atomic_req_8B_endianess_mode_1[0x1];
e281682b 667
b4ff3a36 668 u8 reserved_at_47[0x19];
e281682b 669
b4ff3a36 670 u8 reserved_at_60[0x20];
e281682b 671
b4ff3a36 672 u8 reserved_at_80[0x10];
f91e6d89 673 u8 atomic_operations[0x10];
e281682b 674
b4ff3a36 675 u8 reserved_at_a0[0x10];
f91e6d89
EBE		 676 u8 atomic_size_qp[0x10];
677
b4ff3a36 678 u8 reserved_at_c0[0x10];
e281682b
SM		 679 u8 atomic_size_dc[0x10];
680
b4ff3a36 681 u8 reserved_at_e0[0x720];
e281682b
SM		 682};
683
684struct mlx5_ifc_odp_cap_bits {
b4ff3a36 685 u8 reserved_at_0[0x40];
e281682b
SM		 686
687 u8 sig[0x1];
b4ff3a36 688 u8 reserved_at_41[0x1f];
e281682b 689
b4ff3a36 690 u8 reserved_at_60[0x20];
e281682b
SM		 691
692 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
693
694 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
695
696 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
697
b4ff3a36 698 u8 reserved_at_e0[0x720];
e281682b
SM		 699};
700
3f0393a5
SG		 701struct mlx5_ifc_calc_op {
702 u8 reserved_at_0[0x10];
703 u8 reserved_at_10[0x9];
704 u8 op_swap_endianness[0x1];
705 u8 op_min[0x1];
706 u8 op_xor[0x1];
707 u8 op_or[0x1];
708 u8 op_and[0x1];
709 u8 op_max[0x1];
710 u8 op_add[0x1];
711};
712
713struct mlx5_ifc_vector_calc_cap_bits {
714 u8 calc_matrix[0x1];
715 u8 reserved_at_1[0x1f];
716 u8 reserved_at_20[0x8];
717 u8 max_vec_count[0x8];
718 u8 reserved_at_30[0xd];
719 u8 max_chunk_size[0x3];
720 struct mlx5_ifc_calc_op calc0;
721 struct mlx5_ifc_calc_op calc1;
722 struct mlx5_ifc_calc_op calc2;
723 struct mlx5_ifc_calc_op calc3;
724
725 u8 reserved_at_e0[0x720];
726};
727
e281682b
SM		 728enum {
729 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
730 MLX5_WQ_TYPE_CYCLIC = 0x1,
7d5e1423 731 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
e281682b
SM		 732};
733
734enum {
735 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
736 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
737};
738
739enum {
740 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
741 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
742 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
743 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
744 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
745};
746
747enum {
748 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
749 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
750 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
751 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
752 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
753 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
754};
755
756enum {
757 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
758 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
759};
760
761enum {
762 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
763 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
764 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
765};
766
767enum {
768 MLX5_CAP_PORT_TYPE_IB = 0x0,
769 MLX5_CAP_PORT_TYPE_ETH = 0x1,
d29b796a
EC		 770};
771
1410a90a
MG		 772enum {
773 MLX5_CAP_UMR_FENCE_STRONG = 0x0,
774 MLX5_CAP_UMR_FENCE_SMALL = 0x1,
775 MLX5_CAP_UMR_FENCE_NONE = 0x2,
776};
777
b775516b 778struct mlx5_ifc_cmd_hca_cap_bits {
b4ff3a36 779 u8 reserved_at_0[0x80];
b775516b
EC		 780
781 u8 log_max_srq_sz[0x8];
782 u8 log_max_qp_sz[0x8];
b4ff3a36 783 u8 reserved_at_90[0xb];
b775516b
EC		 784 u8 log_max_qp[0x5];
785
b4ff3a36 786 u8 reserved_at_a0[0xb];
e281682b 787 u8 log_max_srq[0x5];
b4ff3a36 788 u8 reserved_at_b0[0x10];
b775516b 789
b4ff3a36 790 u8 reserved_at_c0[0x8];
b775516b 791 u8 log_max_cq_sz[0x8];
b4ff3a36 792 u8 reserved_at_d0[0xb];
b775516b
EC		 793 u8 log_max_cq[0x5];
794
795 u8 log_max_eq_sz[0x8];
b4ff3a36 796 u8 reserved_at_e8[0x2];
b775516b 797 u8 log_max_mkey[0x6];
b4ff3a36 798 u8 reserved_at_f0[0xc];
b775516b
EC		 799 u8 log_max_eq[0x4];
800
801 u8 max_indirection[0x8];
bcda1aca 802 u8 fixed_buffer_size[0x1];
b775516b 803 u8 log_max_mrw_sz[0x7];
b4ff3a36 804 u8 reserved_at_110[0x2];
b775516b 805 u8 log_max_bsf_list_size[0x6];
bcda1aca
AK		 806 u8 umr_extended_translation_offset[0x1];
807 u8 null_mkey[0x1];
b775516b
EC		 808 u8 log_max_klm_list_size[0x6];
809
b4ff3a36 810 u8 reserved_at_120[0xa];
b775516b 811 u8 log_max_ra_req_dc[0x6];
b4ff3a36 812 u8 reserved_at_130[0xa];
b775516b
EC		 813 u8 log_max_ra_res_dc[0x6];
814
b4ff3a36 815 u8 reserved_at_140[0xa];
b775516b 816 u8 log_max_ra_req_qp[0x6];
b4ff3a36 817 u8 reserved_at_150[0xa];
b775516b
EC		 818 u8 log_max_ra_res_qp[0x6];
819
f32f5bd2 820 u8 end_pad[0x1];
b775516b
EC		 821 u8 cc_query_allowed[0x1];
822 u8 cc_modify_allowed[0x1];
f32f5bd2
DJ		 823 u8 start_pad[0x1];
824 u8 cache_line_128byte[0x1];
825 u8 reserved_at_163[0xb];
e281682b 826 u8 gid_table_size[0x10];
b775516b 827
e281682b
SM		 828 u8 out_of_seq_cnt[0x1];
829 u8 vport_counters[0x1];
7486216b 830 u8 retransmission_q_counters[0x1];
83b502a1
AV		 831 u8 reserved_at_183[0x1];
832 u8 modify_rq_counter_set_id[0x1];
833 u8 reserved_at_185[0x1];
b775516b
EC		 834 u8 max_qp_cnt[0xa];
835 u8 pkey_table_size[0x10];
836
e281682b
SM		 837 u8 vport_group_manager[0x1];
838 u8 vhca_group_manager[0x1];
839 u8 ib_virt[0x1];
840 u8 eth_virt[0x1];
b4ff3a36 841 u8 reserved_at_1a4[0x1];
e281682b
SM		 842 u8 ets[0x1];
843 u8 nic_flow_table[0x1];
54f0a411 844 u8 eswitch_flow_table[0x1];
e1c9c62b 845 u8 early_vf_enable[0x1];
cfdcbcea
GP		 846 u8 mcam_reg[0x1];
847 u8 pcam_reg[0x1];
b775516b 848 u8 local_ca_ack_delay[0x5];
4ce3bf2f 849 u8 port_module_event[0x1];
7b13558f 850 u8 reserved_at_1b1[0x1];
7d5e1423 851 u8 ports_check[0x1];
7b13558f 852 u8 reserved_at_1b3[0x1];
7d5e1423
SM		 853 u8 disable_link_up[0x1];
854 u8 beacon_led[0x1];
e281682b 855 u8 port_type[0x2];
b775516b
EC		 856 u8 num_ports[0x8];
857
f9a1ef72
EE		 858 u8 reserved_at_1c0[0x1];
859 u8 pps[0x1];
860 u8 pps_modify[0x1];
b775516b 861 u8 log_max_msg[0x5];
e1c9c62b 862 u8 reserved_at_1c8[0x4];
4f3961ee 863 u8 max_tc[0x4];
7486216b
SM		 864 u8 reserved_at_1d0[0x1];
865 u8 dcbx[0x1];
e29341fb
IT		 866 u8 reserved_at_1d2[0x3];
867 u8 fpga[0x1];
928cfe87
TT		 868 u8 rol_s[0x1];
869 u8 rol_g[0x1];
e1c9c62b 870 u8 reserved_at_1d8[0x1];
928cfe87
TT		 871 u8 wol_s[0x1];
872 u8 wol_g[0x1];
873 u8 wol_a[0x1];
874 u8 wol_b[0x1];
875 u8 wol_m[0x1];
876 u8 wol_u[0x1];
877 u8 wol_p[0x1];
b775516b
EC		 878
879 u8 stat_rate_support[0x10];
e1c9c62b 880 u8 reserved_at_1f0[0xc];
e281682b 881 u8 cqe_version[0x4];
b775516b 882
e281682b 883 u8 compact_address_vector[0x1];
7d5e1423 884 u8 striding_rq[0x1];
500a3d0d
ES		 885 u8 reserved_at_202[0x1];
886 u8 ipoib_enhanced_offloads[0x1];
1015c2e8 887 u8 ipoib_basic_offloads[0x1];
1410a90a
MG		 888 u8 reserved_at_205[0x5];
889 u8 umr_fence[0x2];
890 u8 reserved_at_20c[0x3];
e281682b 891 u8 drain_sigerr[0x1];
b775516b
EC		 892 u8 cmdif_checksum[0x2];
893 u8 sigerr_cqe[0x1];
e1c9c62b 894 u8 reserved_at_213[0x1];
b775516b
EC		 895 u8 wq_signature[0x1];
896 u8 sctr_data_cqe[0x1];
e1c9c62b 897 u8 reserved_at_216[0x1];
b775516b
EC		 898 u8 sho[0x1];
899 u8 tph[0x1];
900 u8 rf[0x1];
e281682b 901 u8 dct[0x1];
7486216b 902 u8 qos[0x1];
e281682b 903 u8 eth_net_offloads[0x1];
b775516b
EC		 904 u8 roce[0x1];
905 u8 atomic[0x1];
e1c9c62b 906 u8 reserved_at_21f[0x1];
b775516b
EC		 907
908 u8 cq_oi[0x1];
909 u8 cq_resize[0x1];
910 u8 cq_moderation[0x1];
e1c9c62b 911 u8 reserved_at_223[0x3];
e281682b 912 u8 cq_eq_remap[0x1];
b775516b
EC		 913 u8 pg[0x1];
914 u8 block_lb_mc[0x1];
e1c9c62b 915 u8 reserved_at_229[0x1];
e281682b 916 u8 scqe_break_moderation[0x1];
7d5e1423 917 u8 cq_period_start_from_cqe[0x1];
b775516b 918 u8 cd[0x1];
e1c9c62b 919 u8 reserved_at_22d[0x1];
b775516b 920 u8 apm[0x1];
3f0393a5 921 u8 vector_calc[0x1];
7d5e1423 922 u8 umr_ptr_rlky[0x1];
d2370e0a 923 u8 imaicl[0x1];
e1c9c62b 924 u8 reserved_at_232[0x4];
b775516b
EC		 925 u8 qkv[0x1];
926 u8 pkv[0x1];
b11a4f9c
HE		 927 u8 set_deth_sqpn[0x1];
928 u8 reserved_at_239[0x3];
b775516b
EC		 929 u8 xrc[0x1];
930 u8 ud[0x1];
931 u8 uc[0x1];
932 u8 rc[0x1];
933
a6d51b68
EC		 934 u8 uar_4k[0x1];
935 u8 reserved_at_241[0x9];
b775516b 936 u8 uar_sz[0x6];
e1c9c62b 937 u8 reserved_at_250[0x8];
b775516b
EC		 938 u8 log_pg_sz[0x8];
939
940 u8 bf[0x1];
0dbc6fe0 941 u8 driver_version[0x1];
e281682b 942 u8 pad_tx_eth_packet[0x1];
e1c9c62b 943 u8 reserved_at_263[0x8];
b775516b 944 u8 log_bf_reg_size[0x5];
84df61eb
AH		 945
946 u8 reserved_at_270[0xb];
947 u8 lag_master[0x1];
948 u8 num_lag_ports[0x4];
b775516b 949
e1c9c62b 950 u8 reserved_at_280[0x10];
b775516b
EC		 951 u8 max_wqe_sz_sq[0x10];
952
e1c9c62b 953 u8 reserved_at_2a0[0x10];
b775516b
EC		 954 u8 max_wqe_sz_rq[0x10];
955
e1c9c62b 956 u8 reserved_at_2c0[0x10];
b775516b
EC		 957 u8 max_wqe_sz_sq_dc[0x10];
958
e1c9c62b 959 u8 reserved_at_2e0[0x7];
b775516b
EC		 960 u8 max_qp_mcg[0x19];
961
e1c9c62b 962 u8 reserved_at_300[0x18];
b775516b
EC		 963 u8 log_max_mcg[0x8];
964
e1c9c62b 965 u8 reserved_at_320[0x3];
e281682b 966 u8 log_max_transport_domain[0x5];
e1c9c62b 967 u8 reserved_at_328[0x3];
b775516b 968 u8 log_max_pd[0x5];
e1c9c62b 969 u8 reserved_at_330[0xb];
b775516b
EC		 970 u8 log_max_xrcd[0x5];
971
a351a1b0
AV		 972 u8 reserved_at_340[0x8];
973 u8 log_max_flow_counter_bulk[0x8];
974 u8 max_flow_counter[0x10];
975
b775516b 976
e1c9c62b 977 u8 reserved_at_360[0x3];
b775516b 978 u8 log_max_rq[0x5];
e1c9c62b 979 u8 reserved_at_368[0x3];
b775516b 980 u8 log_max_sq[0x5];
e1c9c62b 981 u8 reserved_at_370[0x3];
b775516b 982 u8 log_max_tir[0x5];
e1c9c62b 983 u8 reserved_at_378[0x3];
b775516b
EC		 984 u8 log_max_tis[0x5];
985
e281682b 986 u8 basic_cyclic_rcv_wqe[0x1];
e1c9c62b 987 u8 reserved_at_381[0x2];
e281682b 988 u8 log_max_rmp[0x5];
e1c9c62b 989 u8 reserved_at_388[0x3];
e281682b 990 u8 log_max_rqt[0x5];
e1c9c62b 991 u8 reserved_at_390[0x3];
e281682b 992 u8 log_max_rqt_size[0x5];
e1c9c62b 993 u8 reserved_at_398[0x3];
b775516b
EC		 994 u8 log_max_tis_per_sq[0x5];
995
e1c9c62b 996 u8 reserved_at_3a0[0x3];
e281682b 997 u8 log_max_stride_sz_rq[0x5];
e1c9c62b 998 u8 reserved_at_3a8[0x3];
e281682b 999 u8 log_min_stride_sz_rq[0x5];
e1c9c62b 1000 u8 reserved_at_3b0[0x3];
e281682b 1001 u8 log_max_stride_sz_sq[0x5];
e1c9c62b 1002 u8 reserved_at_3b8[0x3];
e281682b
SM		 1003 u8 log_min_stride_sz_sq[0x5];
1004
e1c9c62b 1005 u8 reserved_at_3c0[0x1b];
e281682b
SM		 1006 u8 log_max_wq_sz[0x5];
1007
54f0a411 1008 u8 nic_vport_change_event[0x1];
e1c9c62b 1009 u8 reserved_at_3e1[0xa];
54f0a411 1010 u8 log_max_vlan_list[0x5];
e1c9c62b 1011 u8 reserved_at_3f0[0x3];
54f0a411 1012 u8 log_max_current_mc_list[0x5];
e1c9c62b 1013 u8 reserved_at_3f8[0x3];
54f0a411
SM		 1014 u8 log_max_current_uc_list[0x5];
1015
e1c9c62b 1016 u8 reserved_at_400[0x80];
54f0a411 1017
e1c9c62b 1018 u8 reserved_at_480[0x3];
e281682b 1019 u8 log_max_l2_table[0x5];
e1c9c62b 1020 u8 reserved_at_488[0x8];
b775516b
EC		 1021 u8 log_uar_page_sz[0x10];
1022
e1c9c62b 1023 u8 reserved_at_4a0[0x20];
048ccca8 1024 u8 device_frequency_mhz[0x20];
b0844444 1025 u8 device_frequency_khz[0x20];
e1c9c62b 1026
a6d51b68
EC		 1027 u8 reserved_at_500[0x20];
1028 u8 num_of_uars_per_page[0x20];
1029 u8 reserved_at_540[0x40];
e1c9c62b
TT		 1030
1031 u8 reserved_at_580[0x3f];
7d5e1423 1032 u8 cqe_compression[0x1];
b775516b 1033
7d5e1423
SM		 1034 u8 cqe_compression_timeout[0x10];
1035 u8 cqe_compression_max_num[0x10];
b775516b 1036
7486216b
SM		 1037 u8 reserved_at_5e0[0x10];
1038 u8 tag_matching[0x1];
1039 u8 rndv_offload_rc[0x1];
1040 u8 rndv_offload_dc[0x1];
1041 u8 log_tag_matching_list_sz[0x5];
7b13558f 1042 u8 reserved_at_5f8[0x3];
7486216b
SM		 1043 u8 log_max_xrq[0x5];
1044
7b13558f 1045 u8 reserved_at_600[0x200];
b775516b
EC		 1046};
1047
81848731
SM		 1048enum mlx5_flow_destination_type {
1049 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1050 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1051 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
bd5251db
AV		 1052
1053 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
e281682b 1054};
b775516b 1055
e281682b
SM		 1056struct mlx5_ifc_dest_format_struct_bits {
1057 u8 destination_type[0x8];
1058 u8 destination_id[0x18];
b775516b 1059
b4ff3a36 1060 u8 reserved_at_20[0x20];
e281682b
SM		 1061};
1062
9dc0b289 1063struct mlx5_ifc_flow_counter_list_bits {
a351a1b0
AV		 1064 u8 clear[0x1];
1065 u8 num_of_counters[0xf];
9dc0b289
AV		 1066 u8 flow_counter_id[0x10];
1067
1068 u8 reserved_at_20[0x20];
1069};
1070
1071union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1072 struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1073 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1074 u8 reserved_at_0[0x40];
1075};
1076
e281682b
SM		 1077struct mlx5_ifc_fte_match_param_bits {
1078 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1079
1080 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1081
1082 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
b775516b 1083
b4ff3a36 1084 u8 reserved_at_600[0xa00];
b775516b
EC		 1085};
1086
e281682b
SM		 1087enum {
1088 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1089 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1090 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1091 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1092 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1093};
b775516b 1094
e281682b
SM		 1095struct mlx5_ifc_rx_hash_field_select_bits {
1096 u8 l3_prot_type[0x1];
1097 u8 l4_prot_type[0x1];
1098 u8 selected_fields[0x1e];
1099};
b775516b 1100
e281682b
SM		 1101enum {
1102 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
1103 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
b775516b
EC		 1104};
1105
e281682b
SM		 1106enum {
1107 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
1108 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
1109};
1110
1111struct mlx5_ifc_wq_bits {
1112 u8 wq_type[0x4];
1113 u8 wq_signature[0x1];
1114 u8 end_padding_mode[0x2];
1115 u8 cd_slave[0x1];
b4ff3a36 1116 u8 reserved_at_8[0x18];
b775516b 1117
e281682b
SM		 1118 u8 hds_skip_first_sge[0x1];
1119 u8 log2_hds_buf_size[0x3];
b4ff3a36 1120 u8 reserved_at_24[0x7];
e281682b
SM		 1121 u8 page_offset[0x5];
1122 u8 lwm[0x10];
b775516b 1123
b4ff3a36 1124 u8 reserved_at_40[0x8];
e281682b
SM		 1125 u8 pd[0x18];
1126
b4ff3a36 1127 u8 reserved_at_60[0x8];
e281682b
SM		 1128 u8 uar_page[0x18];
1129
1130 u8 dbr_addr[0x40];
1131
1132 u8 hw_counter[0x20];
1133
1134 u8 sw_counter[0x20];
1135
b4ff3a36 1136 u8 reserved_at_100[0xc];
e281682b 1137 u8 log_wq_stride[0x4];
b4ff3a36 1138 u8 reserved_at_110[0x3];
e281682b 1139 u8 log_wq_pg_sz[0x5];
b4ff3a36 1140 u8 reserved_at_118[0x3];
e281682b
SM		 1141 u8 log_wq_sz[0x5];
1142
7d5e1423
SM		 1143 u8 reserved_at_120[0x15];
1144 u8 log_wqe_num_of_strides[0x3];
1145 u8 two_byte_shift_en[0x1];
1146 u8 reserved_at_139[0x4];
1147 u8 log_wqe_stride_size[0x3];
1148
1149 u8 reserved_at_140[0x4c0];
b775516b 1150
e281682b 1151 struct mlx5_ifc_cmd_pas_bits pas[0];
b775516b
EC		 1152};
1153
e281682b 1154struct mlx5_ifc_rq_num_bits {
b4ff3a36 1155 u8 reserved_at_0[0x8];
e281682b
SM		 1156 u8 rq_num[0x18];
1157};
b775516b 1158
e281682b 1159struct mlx5_ifc_mac_address_layout_bits {
b4ff3a36 1160 u8 reserved_at_0[0x10];
e281682b 1161 u8 mac_addr_47_32[0x10];
b775516b 1162
e281682b
SM		 1163 u8 mac_addr_31_0[0x20];
1164};
1165
c0046cf7 1166struct mlx5_ifc_vlan_layout_bits {
b4ff3a36 1167 u8 reserved_at_0[0x14];
c0046cf7
SM		 1168 u8 vlan[0x0c];
1169
b4ff3a36 1170 u8 reserved_at_20[0x20];
c0046cf7
SM		 1171};
1172
e281682b 1173struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
b4ff3a36 1174 u8 reserved_at_0[0xa0];
e281682b
SM		 1175
1176 u8 min_time_between_cnps[0x20];
1177
b4ff3a36 1178 u8 reserved_at_c0[0x12];
e281682b 1179 u8 cnp_dscp[0x6];
b4ff3a36 1180 u8 reserved_at_d8[0x5];
e281682b
SM		 1181 u8 cnp_802p_prio[0x3];
1182
b4ff3a36 1183 u8 reserved_at_e0[0x720];
e281682b
SM		 1184};
1185
1186struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
b4ff3a36 1187 u8 reserved_at_0[0x60];
e281682b 1188
b4ff3a36 1189 u8 reserved_at_60[0x4];
e281682b 1190 u8 clamp_tgt_rate[0x1];
b4ff3a36 1191 u8 reserved_at_65[0x3];
e281682b 1192 u8 clamp_tgt_rate_after_time_inc[0x1];
b4ff3a36 1193 u8 reserved_at_69[0x17];
e281682b 1194
b4ff3a36 1195 u8 reserved_at_80[0x20];
e281682b
SM		 1196
1197 u8 rpg_time_reset[0x20];
1198
1199 u8 rpg_byte_reset[0x20];
1200
1201 u8 rpg_threshold[0x20];
1202
1203 u8 rpg_max_rate[0x20];
1204
1205 u8 rpg_ai_rate[0x20];
1206
1207 u8 rpg_hai_rate[0x20];
1208
1209 u8 rpg_gd[0x20];
1210
1211 u8 rpg_min_dec_fac[0x20];
1212
1213 u8 rpg_min_rate[0x20];
1214
b4ff3a36 1215 u8 reserved_at_1c0[0xe0];
e281682b
SM		 1216
1217 u8 rate_to_set_on_first_cnp[0x20];
1218
1219 u8 dce_tcp_g[0x20];
1220
1221 u8 dce_tcp_rtt[0x20];
1222
1223 u8 rate_reduce_monitor_period[0x20];
1224
b4ff3a36 1225 u8 reserved_at_320[0x20];
e281682b
SM		 1226
1227 u8 initial_alpha_value[0x20];
1228
b4ff3a36 1229 u8 reserved_at_360[0x4a0];
e281682b
SM		 1230};
1231
1232struct mlx5_ifc_cong_control_802_1qau_rp_bits {
b4ff3a36 1233 u8 reserved_at_0[0x80];
e281682b
SM		 1234
1235 u8 rppp_max_rps[0x20];
1236
1237 u8 rpg_time_reset[0x20];
1238
1239 u8 rpg_byte_reset[0x20];
1240
1241 u8 rpg_threshold[0x20];
1242
1243 u8 rpg_max_rate[0x20];
1244
1245 u8 rpg_ai_rate[0x20];
1246
1247 u8 rpg_hai_rate[0x20];
1248
1249 u8 rpg_gd[0x20];
1250
1251 u8 rpg_min_dec_fac[0x20];
1252
1253 u8 rpg_min_rate[0x20];
1254
b4ff3a36 1255 u8 reserved_at_1c0[0x640];
e281682b
SM		 1256};
1257
1258enum {
1259 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1260 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1261 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1262};
1263
1264struct mlx5_ifc_resize_field_select_bits {
1265 u8 resize_field_select[0x20];
1266};
1267
1268enum {
1269 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1270 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1271 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1272 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1273};
1274
1275struct mlx5_ifc_modify_field_select_bits {
1276 u8 modify_field_select[0x20];
1277};
1278
1279struct mlx5_ifc_field_select_r_roce_np_bits {
1280 u8 field_select_r_roce_np[0x20];
1281};
1282
1283struct mlx5_ifc_field_select_r_roce_rp_bits {
1284 u8 field_select_r_roce_rp[0x20];
1285};
1286
1287enum {
1288 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1289 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1290 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1291 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1292 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1293 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1294 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1295 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1296 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1297 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1298};
1299
1300struct mlx5_ifc_field_select_802_1qau_rp_bits {
1301 u8 field_select_8021qaurp[0x20];
1302};
1303
1304struct mlx5_ifc_phys_layer_cntrs_bits {
1305 u8 time_since_last_clear_high[0x20];
1306
1307 u8 time_since_last_clear_low[0x20];
1308
1309 u8 symbol_errors_high[0x20];
1310
1311 u8 symbol_errors_low[0x20];
1312
1313 u8 sync_headers_errors_high[0x20];
1314
1315 u8 sync_headers_errors_low[0x20];
1316
1317 u8 edpl_bip_errors_lane0_high[0x20];
1318
1319 u8 edpl_bip_errors_lane0_low[0x20];
1320
1321 u8 edpl_bip_errors_lane1_high[0x20];
1322
1323 u8 edpl_bip_errors_lane1_low[0x20];
1324
1325 u8 edpl_bip_errors_lane2_high[0x20];
1326
1327 u8 edpl_bip_errors_lane2_low[0x20];
1328
1329 u8 edpl_bip_errors_lane3_high[0x20];
1330
1331 u8 edpl_bip_errors_lane3_low[0x20];
1332
1333 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1334
1335 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1336
1337 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1338
1339 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1340
1341 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1342
1343 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1344
1345 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1346
1347 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1348
1349 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1350
1351 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1352
1353 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1354
1355 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1356
1357 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1358
1359 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1360
1361 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1362
1363 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1364
1365 u8 rs_fec_corrected_blocks_high[0x20];
1366
1367 u8 rs_fec_corrected_blocks_low[0x20];
1368
1369 u8 rs_fec_uncorrectable_blocks_high[0x20];
1370
1371 u8 rs_fec_uncorrectable_blocks_low[0x20];
1372
1373 u8 rs_fec_no_errors_blocks_high[0x20];
1374
1375 u8 rs_fec_no_errors_blocks_low[0x20];
1376
1377 u8 rs_fec_single_error_blocks_high[0x20];
1378
1379 u8 rs_fec_single_error_blocks_low[0x20];
1380
1381 u8 rs_fec_corrected_symbols_total_high[0x20];
1382
1383 u8 rs_fec_corrected_symbols_total_low[0x20];
1384
1385 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1386
1387 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1388
1389 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1390
1391 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1392
1393 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1394
1395 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1396
1397 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1398
1399 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1400
1401 u8 link_down_events[0x20];
1402
1403 u8 successful_recovery_events[0x20];
1404
b4ff3a36 1405 u8 reserved_at_640[0x180];
e281682b
SM		 1406};
1407
d8dc0508
GP		 1408struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1409 u8 time_since_last_clear_high[0x20];
1410
1411 u8 time_since_last_clear_low[0x20];
1412
1413 u8 phy_received_bits_high[0x20];
1414
1415 u8 phy_received_bits_low[0x20];
1416
1417 u8 phy_symbol_errors_high[0x20];
1418
1419 u8 phy_symbol_errors_low[0x20];
1420
1421 u8 phy_corrected_bits_high[0x20];
1422
1423 u8 phy_corrected_bits_low[0x20];
1424
1425 u8 phy_corrected_bits_lane0_high[0x20];
1426
1427 u8 phy_corrected_bits_lane0_low[0x20];
1428
1429 u8 phy_corrected_bits_lane1_high[0x20];
1430
1431 u8 phy_corrected_bits_lane1_low[0x20];
1432
1433 u8 phy_corrected_bits_lane2_high[0x20];
1434
1435 u8 phy_corrected_bits_lane2_low[0x20];
1436
1437 u8 phy_corrected_bits_lane3_high[0x20];
1438
1439 u8 phy_corrected_bits_lane3_low[0x20];
1440
1441 u8 reserved_at_200[0x5c0];
1442};
1443
1c64bf6f
MY		 1444struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1445 u8 symbol_error_counter[0x10];
1446
1447 u8 link_error_recovery_counter[0x8];
1448
1449 u8 link_downed_counter[0x8];
1450
1451 u8 port_rcv_errors[0x10];
1452
1453 u8 port_rcv_remote_physical_errors[0x10];
1454
1455 u8 port_rcv_switch_relay_errors[0x10];
1456
1457 u8 port_xmit_discards[0x10];
1458
1459 u8 port_xmit_constraint_errors[0x8];
1460
1461 u8 port_rcv_constraint_errors[0x8];
1462
1463 u8 reserved_at_70[0x8];
1464
1465 u8 link_overrun_errors[0x8];
1466
1467 u8 reserved_at_80[0x10];
1468
1469 u8 vl_15_dropped[0x10];
1470
133bea04
TW		 1471 u8 reserved_at_a0[0x80];
1472
1473 u8 port_xmit_wait[0x20];
1c64bf6f
MY		 1474};
1475
e281682b
SM		 1476struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1477 u8 transmit_queue_high[0x20];
1478
1479 u8 transmit_queue_low[0x20];
1480
b4ff3a36 1481 u8 reserved_at_40[0x780];
e281682b
SM		 1482};
1483
1484struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1485 u8 rx_octets_high[0x20];
1486
1487 u8 rx_octets_low[0x20];
1488
b4ff3a36 1489 u8 reserved_at_40[0xc0];
e281682b
SM		 1490
1491 u8 rx_frames_high[0x20];
1492
1493 u8 rx_frames_low[0x20];
1494
1495 u8 tx_octets_high[0x20];
1496
1497 u8 tx_octets_low[0x20];
1498
b4ff3a36 1499 u8 reserved_at_180[0xc0];
e281682b
SM		 1500
1501 u8 tx_frames_high[0x20];
1502
1503 u8 tx_frames_low[0x20];
1504
1505 u8 rx_pause_high[0x20];
1506
1507 u8 rx_pause_low[0x20];
1508
1509 u8 rx_pause_duration_high[0x20];
1510
1511 u8 rx_pause_duration_low[0x20];
1512
1513 u8 tx_pause_high[0x20];
1514
1515 u8 tx_pause_low[0x20];
1516
1517 u8 tx_pause_duration_high[0x20];
1518
1519 u8 tx_pause_duration_low[0x20];
1520
1521 u8 rx_pause_transition_high[0x20];
1522
1523 u8 rx_pause_transition_low[0x20];
1524
b4ff3a36 1525 u8 reserved_at_3c0[0x400];
e281682b
SM		 1526};
1527
1528struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1529 u8 port_transmit_wait_high[0x20];
1530
1531 u8 port_transmit_wait_low[0x20];
1532
b4ff3a36 1533 u8 reserved_at_40[0x780];
e281682b
SM		 1534};
1535
1536struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1537 u8 dot3stats_alignment_errors_high[0x20];
1538
1539 u8 dot3stats_alignment_errors_low[0x20];
1540
1541 u8 dot3stats_fcs_errors_high[0x20];
1542
1543 u8 dot3stats_fcs_errors_low[0x20];
1544
1545 u8 dot3stats_single_collision_frames_high[0x20];
1546
1547 u8 dot3stats_single_collision_frames_low[0x20];
1548
1549 u8 dot3stats_multiple_collision_frames_high[0x20];
1550
1551 u8 dot3stats_multiple_collision_frames_low[0x20];
1552
1553 u8 dot3stats_sqe_test_errors_high[0x20];
1554
1555 u8 dot3stats_sqe_test_errors_low[0x20];
1556
1557 u8 dot3stats_deferred_transmissions_high[0x20];
1558
1559 u8 dot3stats_deferred_transmissions_low[0x20];
1560
1561 u8 dot3stats_late_collisions_high[0x20];
1562
1563 u8 dot3stats_late_collisions_low[0x20];
1564
1565 u8 dot3stats_excessive_collisions_high[0x20];
1566
1567 u8 dot3stats_excessive_collisions_low[0x20];
1568
1569 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1570
1571 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1572
1573 u8 dot3stats_carrier_sense_errors_high[0x20];
1574
1575 u8 dot3stats_carrier_sense_errors_low[0x20];
1576
1577 u8 dot3stats_frame_too_longs_high[0x20];
1578
1579 u8 dot3stats_frame_too_longs_low[0x20];
1580
1581 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1582
1583 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1584
1585 u8 dot3stats_symbol_errors_high[0x20];
1586
1587 u8 dot3stats_symbol_errors_low[0x20];
1588
1589 u8 dot3control_in_unknown_opcodes_high[0x20];
1590
1591 u8 dot3control_in_unknown_opcodes_low[0x20];
1592
1593 u8 dot3in_pause_frames_high[0x20];
1594
1595 u8 dot3in_pause_frames_low[0x20];
1596
1597 u8 dot3out_pause_frames_high[0x20];
1598
1599 u8 dot3out_pause_frames_low[0x20];
1600
b4ff3a36 1601 u8 reserved_at_400[0x3c0];
e281682b
SM		 1602};
1603
1604struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1605 u8 ether_stats_drop_events_high[0x20];
1606
1607 u8 ether_stats_drop_events_low[0x20];
1608
1609 u8 ether_stats_octets_high[0x20];
1610
1611 u8 ether_stats_octets_low[0x20];
1612
1613 u8 ether_stats_pkts_high[0x20];
1614
1615 u8 ether_stats_pkts_low[0x20];
1616
1617 u8 ether_stats_broadcast_pkts_high[0x20];
1618
1619 u8 ether_stats_broadcast_pkts_low[0x20];
1620
1621 u8 ether_stats_multicast_pkts_high[0x20];
1622
1623 u8 ether_stats_multicast_pkts_low[0x20];
1624
1625 u8 ether_stats_crc_align_errors_high[0x20];
1626
1627 u8 ether_stats_crc_align_errors_low[0x20];
1628
1629 u8 ether_stats_undersize_pkts_high[0x20];
1630
1631 u8 ether_stats_undersize_pkts_low[0x20];
1632
1633 u8 ether_stats_oversize_pkts_high[0x20];
1634
1635 u8 ether_stats_oversize_pkts_low[0x20];
1636
1637 u8 ether_stats_fragments_high[0x20];
1638
1639 u8 ether_stats_fragments_low[0x20];
1640
1641 u8 ether_stats_jabbers_high[0x20];
1642
1643 u8 ether_stats_jabbers_low[0x20];
1644
1645 u8 ether_stats_collisions_high[0x20];
1646
1647 u8 ether_stats_collisions_low[0x20];
1648
1649 u8 ether_stats_pkts64octets_high[0x20];
1650
1651 u8 ether_stats_pkts64octets_low[0x20];
1652
1653 u8 ether_stats_pkts65to127octets_high[0x20];
1654
1655 u8 ether_stats_pkts65to127octets_low[0x20];
1656
1657 u8 ether_stats_pkts128to255octets_high[0x20];
1658
1659 u8 ether_stats_pkts128to255octets_low[0x20];
1660
1661 u8 ether_stats_pkts256to511octets_high[0x20];
1662
1663 u8 ether_stats_pkts256to511octets_low[0x20];
1664
1665 u8 ether_stats_pkts512to1023octets_high[0x20];
1666
1667 u8 ether_stats_pkts512to1023octets_low[0x20];
1668
1669 u8 ether_stats_pkts1024to1518octets_high[0x20];
1670
1671 u8 ether_stats_pkts1024to1518octets_low[0x20];
1672
1673 u8 ether_stats_pkts1519to2047octets_high[0x20];
1674
1675 u8 ether_stats_pkts1519to2047octets_low[0x20];
1676
1677 u8 ether_stats_pkts2048to4095octets_high[0x20];
1678
1679 u8 ether_stats_pkts2048to4095octets_low[0x20];
1680
1681 u8 ether_stats_pkts4096to8191octets_high[0x20];
1682
1683 u8 ether_stats_pkts4096to8191octets_low[0x20];
1684
1685 u8 ether_stats_pkts8192to10239octets_high[0x20];
1686
1687 u8 ether_stats_pkts8192to10239octets_low[0x20];
1688
b4ff3a36 1689 u8 reserved_at_540[0x280];
e281682b
SM		 1690};
1691
1692struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1693 u8 if_in_octets_high[0x20];
1694
1695 u8 if_in_octets_low[0x20];
1696
1697 u8 if_in_ucast_pkts_high[0x20];
1698
1699 u8 if_in_ucast_pkts_low[0x20];
1700
1701 u8 if_in_discards_high[0x20];
1702
1703 u8 if_in_discards_low[0x20];
1704
1705 u8 if_in_errors_high[0x20];
1706
1707 u8 if_in_errors_low[0x20];
1708
1709 u8 if_in_unknown_protos_high[0x20];
1710
1711 u8 if_in_unknown_protos_low[0x20];
1712
1713 u8 if_out_octets_high[0x20];
1714
1715 u8 if_out_octets_low[0x20];
1716
1717 u8 if_out_ucast_pkts_high[0x20];
1718
1719 u8 if_out_ucast_pkts_low[0x20];
1720
1721 u8 if_out_discards_high[0x20];
1722
1723 u8 if_out_discards_low[0x20];
1724
1725 u8 if_out_errors_high[0x20];
1726
1727 u8 if_out_errors_low[0x20];
1728
1729 u8 if_in_multicast_pkts_high[0x20];
1730
1731 u8 if_in_multicast_pkts_low[0x20];
1732
1733 u8 if_in_broadcast_pkts_high[0x20];
1734
1735 u8 if_in_broadcast_pkts_low[0x20];
1736
1737 u8 if_out_multicast_pkts_high[0x20];
1738
1739 u8 if_out_multicast_pkts_low[0x20];
1740
1741 u8 if_out_broadcast_pkts_high[0x20];
1742
1743 u8 if_out_broadcast_pkts_low[0x20];
1744
b4ff3a36 1745 u8 reserved_at_340[0x480];
e281682b
SM		 1746};
1747
1748struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1749 u8 a_frames_transmitted_ok_high[0x20];
1750
1751 u8 a_frames_transmitted_ok_low[0x20];
1752
1753 u8 a_frames_received_ok_high[0x20];
1754
1755 u8 a_frames_received_ok_low[0x20];
1756
1757 u8 a_frame_check_sequence_errors_high[0x20];
1758
1759 u8 a_frame_check_sequence_errors_low[0x20];
1760
1761 u8 a_alignment_errors_high[0x20];
1762
1763 u8 a_alignment_errors_low[0x20];
1764
1765 u8 a_octets_transmitted_ok_high[0x20];
1766
1767 u8 a_octets_transmitted_ok_low[0x20];
1768
1769 u8 a_octets_received_ok_high[0x20];
1770
1771 u8 a_octets_received_ok_low[0x20];
1772
1773 u8 a_multicast_frames_xmitted_ok_high[0x20];
1774
1775 u8 a_multicast_frames_xmitted_ok_low[0x20];
1776
1777 u8 a_broadcast_frames_xmitted_ok_high[0x20];
1778
1779 u8 a_broadcast_frames_xmitted_ok_low[0x20];
1780
1781 u8 a_multicast_frames_received_ok_high[0x20];
1782
1783 u8 a_multicast_frames_received_ok_low[0x20];
1784
1785 u8 a_broadcast_frames_received_ok_high[0x20];
1786
1787 u8 a_broadcast_frames_received_ok_low[0x20];
1788
1789 u8 a_in_range_length_errors_high[0x20];
1790
1791 u8 a_in_range_length_errors_low[0x20];
1792
1793 u8 a_out_of_range_length_field_high[0x20];
1794
1795 u8 a_out_of_range_length_field_low[0x20];
1796
1797 u8 a_frame_too_long_errors_high[0x20];
1798
1799 u8 a_frame_too_long_errors_low[0x20];
1800
1801 u8 a_symbol_error_during_carrier_high[0x20];
1802
1803 u8 a_symbol_error_during_carrier_low[0x20];
1804
1805 u8 a_mac_control_frames_transmitted_high[0x20];
1806
1807 u8 a_mac_control_frames_transmitted_low[0x20];
1808
1809 u8 a_mac_control_frames_received_high[0x20];
1810
1811 u8 a_mac_control_frames_received_low[0x20];
1812
1813 u8 a_unsupported_opcodes_received_high[0x20];
1814
1815 u8 a_unsupported_opcodes_received_low[0x20];
1816
1817 u8 a_pause_mac_ctrl_frames_received_high[0x20];
1818
1819 u8 a_pause_mac_ctrl_frames_received_low[0x20];
1820
1821 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
1822
1823 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
1824
b4ff3a36 1825 u8 reserved_at_4c0[0x300];
e281682b
SM		 1826};
1827
8ed1a630
GP		 1828struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
1829 u8 life_time_counter_high[0x20];
1830
1831 u8 life_time_counter_low[0x20];
1832
1833 u8 rx_errors[0x20];
1834
1835 u8 tx_errors[0x20];
1836
1837 u8 l0_to_recovery_eieos[0x20];
1838
1839 u8 l0_to_recovery_ts[0x20];
1840
1841 u8 l0_to_recovery_framing[0x20];
1842
1843 u8 l0_to_recovery_retrain[0x20];
1844
1845 u8 crc_error_dllp[0x20];
1846
1847 u8 crc_error_tlp[0x20];
1848
1849 u8 reserved_at_140[0x680];
1850};
1851
e281682b
SM		 1852struct mlx5_ifc_cmd_inter_comp_event_bits {
1853 u8 command_completion_vector[0x20];
1854
b4ff3a36 1855 u8 reserved_at_20[0xc0];
e281682b
SM		 1856};
1857
1858struct mlx5_ifc_stall_vl_event_bits {
b4ff3a36 1859 u8 reserved_at_0[0x18];
e281682b 1860 u8 port_num[0x1];
b4ff3a36 1861 u8 reserved_at_19[0x3];
e281682b
SM		 1862 u8 vl[0x4];
1863
b4ff3a36 1864 u8 reserved_at_20[0xa0];
e281682b
SM		 1865};
1866
1867struct mlx5_ifc_db_bf_congestion_event_bits {
1868 u8 event_subtype[0x8];
b4ff3a36 1869 u8 reserved_at_8[0x8];
e281682b 1870 u8 congestion_level[0x8];
b4ff3a36 1871 u8 reserved_at_18[0x8];
e281682b 1872
b4ff3a36 1873 u8 reserved_at_20[0xa0];
e281682b
SM		 1874};
1875
1876struct mlx5_ifc_gpio_event_bits {
b4ff3a36 1877 u8 reserved_at_0[0x60];
e281682b
SM		 1878
1879 u8 gpio_event_hi[0x20];
1880
1881 u8 gpio_event_lo[0x20];
1882
b4ff3a36 1883 u8 reserved_at_a0[0x40];
e281682b
SM		 1884};
1885
1886struct mlx5_ifc_port_state_change_event_bits {
b4ff3a36 1887 u8 reserved_at_0[0x40];
e281682b
SM		 1888
1889 u8 port_num[0x4];
b4ff3a36 1890 u8 reserved_at_44[0x1c];
e281682b 1891
b4ff3a36 1892 u8 reserved_at_60[0x80];
e281682b
SM		 1893};
1894
1895struct mlx5_ifc_dropped_packet_logged_bits {
b4ff3a36 1896 u8 reserved_at_0[0xe0];
e281682b
SM		 1897};
1898
1899enum {
1900 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
1901 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
1902};
1903
1904struct mlx5_ifc_cq_error_bits {
b4ff3a36 1905 u8 reserved_at_0[0x8];
e281682b
SM		 1906 u8 cqn[0x18];
1907
b4ff3a36 1908 u8 reserved_at_20[0x20];
e281682b 1909
b4ff3a36 1910 u8 reserved_at_40[0x18];
e281682b
SM		 1911 u8 syndrome[0x8];
1912
b4ff3a36 1913 u8 reserved_at_60[0x80];
e281682b
SM		 1914};
1915
1916struct mlx5_ifc_rdma_page_fault_event_bits {
1917 u8 bytes_committed[0x20];
1918
1919 u8 r_key[0x20];
1920
b4ff3a36 1921 u8 reserved_at_40[0x10];
e281682b
SM		 1922 u8 packet_len[0x10];
1923
1924 u8 rdma_op_len[0x20];
1925
1926 u8 rdma_va[0x40];
1927
b4ff3a36 1928 u8 reserved_at_c0[0x5];
e281682b
SM		 1929 u8 rdma[0x1];
1930 u8 write[0x1];
1931 u8 requestor[0x1];
1932 u8 qp_number[0x18];
1933};
1934
1935struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1936 u8 bytes_committed[0x20];
1937
b4ff3a36 1938 u8 reserved_at_20[0x10];
e281682b
SM		 1939 u8 wqe_index[0x10];
1940
b4ff3a36 1941 u8 reserved_at_40[0x10];
e281682b
SM		 1942 u8 len[0x10];
1943
b4ff3a36 1944 u8 reserved_at_60[0x60];
e281682b 1945
b4ff3a36 1946 u8 reserved_at_c0[0x5];
e281682b
SM		 1947 u8 rdma[0x1];
1948 u8 write_read[0x1];
1949 u8 requestor[0x1];
1950 u8 qpn[0x18];
1951};
1952
1953struct mlx5_ifc_qp_events_bits {
b4ff3a36 1954 u8 reserved_at_0[0xa0];
e281682b
SM		 1955
1956 u8 type[0x8];
b4ff3a36 1957 u8 reserved_at_a8[0x18];
e281682b 1958
b4ff3a36 1959 u8 reserved_at_c0[0x8];
e281682b
SM		 1960 u8 qpn_rqn_sqn[0x18];
1961};
1962
1963struct mlx5_ifc_dct_events_bits {
b4ff3a36 1964 u8 reserved_at_0[0xc0];
e281682b 1965
b4ff3a36 1966 u8 reserved_at_c0[0x8];
e281682b
SM		 1967 u8 dct_number[0x18];
1968};
1969
1970struct mlx5_ifc_comp_event_bits {
b4ff3a36 1971 u8 reserved_at_0[0xc0];
e281682b 1972
b4ff3a36 1973 u8 reserved_at_c0[0x8];
e281682b
SM		 1974 u8 cq_number[0x18];
1975};
1976
1977enum {
1978 MLX5_QPC_STATE_RST = 0x0,
1979 MLX5_QPC_STATE_INIT = 0x1,
1980 MLX5_QPC_STATE_RTR = 0x2,
1981 MLX5_QPC_STATE_RTS = 0x3,
1982 MLX5_QPC_STATE_SQER = 0x4,
1983 MLX5_QPC_STATE_ERR = 0x6,
1984 MLX5_QPC_STATE_SQD = 0x7,
1985 MLX5_QPC_STATE_SUSPENDED = 0x9,
1986};
1987
1988enum {
1989 MLX5_QPC_ST_RC = 0x0,
1990 MLX5_QPC_ST_UC = 0x1,
1991 MLX5_QPC_ST_UD = 0x2,
1992 MLX5_QPC_ST_XRC = 0x3,
1993 MLX5_QPC_ST_DCI = 0x5,
1994 MLX5_QPC_ST_QP0 = 0x7,
1995 MLX5_QPC_ST_QP1 = 0x8,
1996 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
1997 MLX5_QPC_ST_REG_UMR = 0xc,
1998};
1999
2000enum {
2001 MLX5_QPC_PM_STATE_ARMED = 0x0,
2002 MLX5_QPC_PM_STATE_REARM = 0x1,
2003 MLX5_QPC_PM_STATE_RESERVED = 0x2,
2004 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
2005};
2006
2007enum {
2008 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
2009 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
2010};
2011
2012enum {
2013 MLX5_QPC_MTU_256_BYTES = 0x1,
2014 MLX5_QPC_MTU_512_BYTES = 0x2,
2015 MLX5_QPC_MTU_1K_BYTES = 0x3,
2016 MLX5_QPC_MTU_2K_BYTES = 0x4,
2017 MLX5_QPC_MTU_4K_BYTES = 0x5,
2018 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
2019};
2020
2021enum {
2022 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
2023 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
2024 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
2025 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
2026 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
2027 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
2028 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
2029 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
2030};
2031
2032enum {
2033 MLX5_QPC_CS_REQ_DISABLE = 0x0,
2034 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
2035 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
2036};
2037
2038enum {
2039 MLX5_QPC_CS_RES_DISABLE = 0x0,
2040 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
2041 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
2042};
2043
2044struct mlx5_ifc_qpc_bits {
2045 u8 state[0x4];
84df61eb 2046 u8 lag_tx_port_affinity[0x4];
e281682b 2047 u8 st[0x8];
b4ff3a36 2048 u8 reserved_at_10[0x3];
e281682b 2049 u8 pm_state[0x2];
b4ff3a36 2050 u8 reserved_at_15[0x7];
e281682b 2051 u8 end_padding_mode[0x2];
b4ff3a36 2052 u8 reserved_at_1e[0x2];
e281682b
SM		 2053
2054 u8 wq_signature[0x1];
2055 u8 block_lb_mc[0x1];
2056 u8 atomic_like_write_en[0x1];
2057 u8 latency_sensitive[0x1];
b4ff3a36 2058 u8 reserved_at_24[0x1];
e281682b 2059 u8 drain_sigerr[0x1];
b4ff3a36 2060 u8 reserved_at_26[0x2];
e281682b
SM		 2061 u8 pd[0x18];
2062
2063 u8 mtu[0x3];
2064 u8 log_msg_max[0x5];
b4ff3a36 2065 u8 reserved_at_48[0x1];
e281682b
SM		 2066 u8 log_rq_size[0x4];
2067 u8 log_rq_stride[0x3];
2068 u8 no_sq[0x1];
2069 u8 log_sq_size[0x4];
b4ff3a36 2070 u8 reserved_at_55[0x6];
e281682b 2071 u8 rlky[0x1];
1015c2e8 2072 u8 ulp_stateless_offload_mode[0x4];
e281682b
SM		 2073
2074 u8 counter_set_id[0x8];
2075 u8 uar_page[0x18];
2076
b4ff3a36 2077 u8 reserved_at_80[0x8];
e281682b
SM		 2078 u8 user_index[0x18];
2079
b4ff3a36 2080 u8 reserved_at_a0[0x3];
e281682b
SM		 2081 u8 log_page_size[0x5];
2082 u8 remote_qpn[0x18];
2083
2084 struct mlx5_ifc_ads_bits primary_address_path;
2085
2086 struct mlx5_ifc_ads_bits secondary_address_path;
2087
2088 u8 log_ack_req_freq[0x4];
b4ff3a36 2089 u8 reserved_at_384[0x4];
e281682b 2090 u8 log_sra_max[0x3];
b4ff3a36 2091 u8 reserved_at_38b[0x2];
e281682b
SM		 2092 u8 retry_count[0x3];
2093 u8 rnr_retry[0x3];
b4ff3a36 2094 u8 reserved_at_393[0x1];
e281682b
SM		 2095 u8 fre[0x1];
2096 u8 cur_rnr_retry[0x3];
2097 u8 cur_retry_count[0x3];
b4ff3a36 2098 u8 reserved_at_39b[0x5];
e281682b 2099
b4ff3a36 2100 u8 reserved_at_3a0[0x20];
e281682b 2101
b4ff3a36 2102 u8 reserved_at_3c0[0x8];
e281682b
SM		 2103 u8 next_send_psn[0x18];
2104
b4ff3a36 2105 u8 reserved_at_3e0[0x8];
e281682b
SM		 2106 u8 cqn_snd[0x18];
2107
09a7d9ec
SM		 2108 u8 reserved_at_400[0x8];
2109 u8 deth_sqpn[0x18];
2110
2111 u8 reserved_at_420[0x20];
e281682b 2112
b4ff3a36 2113 u8 reserved_at_440[0x8];
e281682b
SM		 2114 u8 last_acked_psn[0x18];
2115
b4ff3a36 2116 u8 reserved_at_460[0x8];
e281682b
SM		 2117 u8 ssn[0x18];
2118
b4ff3a36 2119 u8 reserved_at_480[0x8];
e281682b 2120 u8 log_rra_max[0x3];
b4ff3a36 2121 u8 reserved_at_48b[0x1];
e281682b
SM		 2122 u8 atomic_mode[0x4];
2123 u8 rre[0x1];
2124 u8 rwe[0x1];
2125 u8 rae[0x1];
b4ff3a36 2126 u8 reserved_at_493[0x1];
e281682b 2127 u8 page_offset[0x6];
b4ff3a36 2128 u8 reserved_at_49a[0x3];
e281682b
SM		 2129 u8 cd_slave_receive[0x1];
2130 u8 cd_slave_send[0x1];
2131 u8 cd_master[0x1];
2132
b4ff3a36 2133 u8 reserved_at_4a0[0x3];
e281682b
SM		 2134 u8 min_rnr_nak[0x5];
2135 u8 next_rcv_psn[0x18];
2136
b4ff3a36 2137 u8 reserved_at_4c0[0x8];
e281682b
SM		 2138 u8 xrcd[0x18];
2139
b4ff3a36 2140 u8 reserved_at_4e0[0x8];
e281682b
SM		 2141 u8 cqn_rcv[0x18];
2142
2143 u8 dbr_addr[0x40];
2144
2145 u8 q_key[0x20];
2146
b4ff3a36 2147 u8 reserved_at_560[0x5];
e281682b 2148 u8 rq_type[0x3];
7486216b 2149 u8 srqn_rmpn_xrqn[0x18];
e281682b 2150
b4ff3a36 2151 u8 reserved_at_580[0x8];
e281682b
SM		 2152 u8 rmsn[0x18];
2153
2154 u8 hw_sq_wqebb_counter[0x10];
2155 u8 sw_sq_wqebb_counter[0x10];
2156
2157 u8 hw_rq_counter[0x20];
2158
2159 u8 sw_rq_counter[0x20];
2160
b4ff3a36 2161 u8 reserved_at_600[0x20];
e281682b 2162
b4ff3a36 2163 u8 reserved_at_620[0xf];
e281682b
SM		 2164 u8 cgs[0x1];
2165 u8 cs_req[0x8];
2166 u8 cs_res[0x8];
2167
2168 u8 dc_access_key[0x40];
2169
b4ff3a36 2170 u8 reserved_at_680[0xc0];
e281682b
SM		 2171};
2172
2173struct mlx5_ifc_roce_addr_layout_bits {
2174 u8 source_l3_address[16][0x8];
2175
b4ff3a36 2176 u8 reserved_at_80[0x3];
e281682b
SM		 2177 u8 vlan_valid[0x1];
2178 u8 vlan_id[0xc];
2179 u8 source_mac_47_32[0x10];
2180
2181 u8 source_mac_31_0[0x20];
2182
b4ff3a36 2183 u8 reserved_at_c0[0x14];
e281682b
SM		 2184 u8 roce_l3_type[0x4];
2185 u8 roce_version[0x8];
2186
b4ff3a36 2187 u8 reserved_at_e0[0x20];
e281682b
SM		 2188};
2189
2190union mlx5_ifc_hca_cap_union_bits {
2191 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2192 struct mlx5_ifc_odp_cap_bits odp_cap;
2193 struct mlx5_ifc_atomic_caps_bits atomic_caps;
2194 struct mlx5_ifc_roce_cap_bits roce_cap;
2195 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2196 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
495716b1 2197 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
d6666753 2198 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
3f0393a5 2199 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
7486216b 2200 struct mlx5_ifc_qos_cap_bits qos_cap;
e29341fb 2201 struct mlx5_ifc_fpga_cap_bits fpga_cap;
b4ff3a36 2202 u8 reserved_at_0[0x8000];
e281682b
SM		 2203};
2204
2205enum {
2206 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
2207 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
2208 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
9dc0b289 2209 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
7adbde20
HHZ		 2210 MLX5_FLOW_CONTEXT_ACTION_ENCAP = 0x10,
2211 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
2a69cb9f 2212 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40,
e281682b
SM		 2213};
2214
2215struct mlx5_ifc_flow_context_bits {
b4ff3a36 2216 u8 reserved_at_0[0x20];
e281682b
SM		 2217
2218 u8 group_id[0x20];
2219
b4ff3a36 2220 u8 reserved_at_40[0x8];
e281682b
SM		 2221 u8 flow_tag[0x18];
2222
b4ff3a36 2223 u8 reserved_at_60[0x10];
e281682b
SM		 2224 u8 action[0x10];
2225
b4ff3a36 2226 u8 reserved_at_80[0x8];
e281682b
SM		 2227 u8 destination_list_size[0x18];
2228
9dc0b289
AV		 2229 u8 reserved_at_a0[0x8];
2230 u8 flow_counter_list_size[0x18];
2231
7adbde20
HHZ		 2232 u8 encap_id[0x20];
2233
2a69cb9f
OG		 2234 u8 modify_header_id[0x20];
2235
2236 u8 reserved_at_100[0x100];
e281682b
SM		 2237
2238 struct mlx5_ifc_fte_match_param_bits match_value;
2239
b4ff3a36 2240 u8 reserved_at_1200[0x600];
e281682b 2241
9dc0b289 2242 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
e281682b
SM		 2243};
2244
2245enum {
2246 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
2247 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
2248};
2249
2250struct mlx5_ifc_xrc_srqc_bits {
2251 u8 state[0x4];
2252 u8 log_xrc_srq_size[0x4];
b4ff3a36 2253 u8 reserved_at_8[0x18];
e281682b
SM		 2254
2255 u8 wq_signature[0x1];
2256 u8 cont_srq[0x1];
b4ff3a36 2257 u8 reserved_at_22[0x1];
e281682b
SM		 2258 u8 rlky[0x1];
2259 u8 basic_cyclic_rcv_wqe[0x1];
2260 u8 log_rq_stride[0x3];
2261 u8 xrcd[0x18];
2262
2263 u8 page_offset[0x6];
b4ff3a36 2264 u8 reserved_at_46[0x2];
e281682b
SM		 2265 u8 cqn[0x18];
2266
b4ff3a36 2267 u8 reserved_at_60[0x20];
e281682b
SM		 2268
2269 u8 user_index_equal_xrc_srqn[0x1];
b4ff3a36 2270 u8 reserved_at_81[0x1];
e281682b
SM		 2271 u8 log_page_size[0x6];
2272 u8 user_index[0x18];
2273
b4ff3a36 2274 u8 reserved_at_a0[0x20];
e281682b 2275
b4ff3a36 2276 u8 reserved_at_c0[0x8];
e281682b
SM		 2277 u8 pd[0x18];
2278
2279 u8 lwm[0x10];
2280 u8 wqe_cnt[0x10];
2281
b4ff3a36 2282 u8 reserved_at_100[0x40];
e281682b
SM		 2283
2284 u8 db_record_addr_h[0x20];
2285
2286 u8 db_record_addr_l[0x1e];
b4ff3a36 2287 u8 reserved_at_17e[0x2];
e281682b 2288
b4ff3a36 2289 u8 reserved_at_180[0x80];
e281682b
SM		 2290};
2291
2292struct mlx5_ifc_traffic_counter_bits {
2293 u8 packets[0x40];
2294
2295 u8 octets[0x40];
2296};
2297
2298struct mlx5_ifc_tisc_bits {
84df61eb
AH		 2299 u8 strict_lag_tx_port_affinity[0x1];
2300 u8 reserved_at_1[0x3];
2301 u8 lag_tx_port_affinity[0x04];
2302
2303 u8 reserved_at_8[0x4];
e281682b 2304 u8 prio[0x4];
b4ff3a36 2305 u8 reserved_at_10[0x10];
e281682b 2306
b4ff3a36 2307 u8 reserved_at_20[0x100];
e281682b 2308
b4ff3a36 2309 u8 reserved_at_120[0x8];
e281682b
SM		 2310 u8 transport_domain[0x18];
2311
500a3d0d
ES		 2312 u8 reserved_at_140[0x8];
2313 u8 underlay_qpn[0x18];
2314 u8 reserved_at_160[0x3a0];
e281682b
SM		 2315};
2316
2317enum {
2318 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2319 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2320};
2321
2322enum {
2323 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2324 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2325};
2326
2327enum {
2be6967c
SM		 2328 MLX5_RX_HASH_FN_NONE = 0x0,
2329 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
2330 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
e281682b
SM		 2331};
2332
2333enum {
2334 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1,
2335 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2,
2336};
2337
2338struct mlx5_ifc_tirc_bits {
b4ff3a36 2339 u8 reserved_at_0[0x20];
e281682b
SM		 2340
2341 u8 disp_type[0x4];
b4ff3a36 2342 u8 reserved_at_24[0x1c];
e281682b 2343
b4ff3a36 2344 u8 reserved_at_40[0x40];
e281682b 2345
b4ff3a36 2346 u8 reserved_at_80[0x4];
e281682b
SM		 2347 u8 lro_timeout_period_usecs[0x10];
2348 u8 lro_enable_mask[0x4];
2349 u8 lro_max_ip_payload_size[0x8];
2350
b4ff3a36 2351 u8 reserved_at_a0[0x40];
e281682b 2352
b4ff3a36 2353 u8 reserved_at_e0[0x8];
e281682b
SM		 2354 u8 inline_rqn[0x18];
2355
2356 u8 rx_hash_symmetric[0x1];
b4ff3a36 2357 u8 reserved_at_101[0x1];
e281682b 2358 u8 tunneled_offload_en[0x1];
b4ff3a36 2359 u8 reserved_at_103[0x5];
e281682b
SM		 2360 u8 indirect_table[0x18];
2361
2362 u8 rx_hash_fn[0x4];
b4ff3a36 2363 u8 reserved_at_124[0x2];
e281682b
SM		 2364 u8 self_lb_block[0x2];
2365 u8 transport_domain[0x18];
2366
2367 u8 rx_hash_toeplitz_key[10][0x20];
2368
2369 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2370
2371 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2372
b4ff3a36 2373 u8 reserved_at_2c0[0x4c0];
e281682b
SM		 2374};
2375
2376enum {
2377 MLX5_SRQC_STATE_GOOD = 0x0,
2378 MLX5_SRQC_STATE_ERROR = 0x1,
2379};
2380
2381struct mlx5_ifc_srqc_bits {
2382 u8 state[0x4];
2383 u8 log_srq_size[0x4];
b4ff3a36 2384 u8 reserved_at_8[0x18];
e281682b
SM		 2385
2386 u8 wq_signature[0x1];
2387 u8 cont_srq[0x1];
b4ff3a36 2388 u8 reserved_at_22[0x1];
e281682b 2389 u8 rlky[0x1];
b4ff3a36 2390 u8 reserved_at_24[0x1];
e281682b
SM		 2391 u8 log_rq_stride[0x3];
2392 u8 xrcd[0x18];
2393
2394 u8 page_offset[0x6];
b4ff3a36 2395 u8 reserved_at_46[0x2];
e281682b
SM		 2396 u8 cqn[0x18];
2397
b4ff3a36 2398 u8 reserved_at_60[0x20];
e281682b 2399
b4ff3a36 2400 u8 reserved_at_80[0x2];
e281682b 2401 u8 log_page_size[0x6];
b4ff3a36 2402 u8 reserved_at_88[0x18];
e281682b 2403
b4ff3a36 2404 u8 reserved_at_a0[0x20];
e281682b 2405
b4ff3a36 2406 u8 reserved_at_c0[0x8];
e281682b
SM		 2407 u8 pd[0x18];
2408
2409 u8 lwm[0x10];
2410 u8 wqe_cnt[0x10];
2411
b4ff3a36 2412 u8 reserved_at_100[0x40];
e281682b 2413
01949d01 2414 u8 dbr_addr[0x40];
e281682b 2415
b4ff3a36 2416 u8 reserved_at_180[0x80];
e281682b
SM		 2417};
2418
2419enum {
2420 MLX5_SQC_STATE_RST = 0x0,
2421 MLX5_SQC_STATE_RDY = 0x1,
2422 MLX5_SQC_STATE_ERR = 0x3,
2423};
2424
2425struct mlx5_ifc_sqc_bits {
2426 u8 rlky[0x1];
2427 u8 cd_master[0x1];
2428 u8 fre[0x1];
2429 u8 flush_in_error_en[0x1];
cff92d7c
HHZ		 2430 u8 reserved_at_4[0x1];
2431 u8 min_wqe_inline_mode[0x3];
e281682b 2432 u8 state[0x4];
7d5e1423
SM		 2433 u8 reg_umr[0x1];
2434 u8 reserved_at_d[0x13];
e281682b 2435
b4ff3a36 2436 u8 reserved_at_20[0x8];
e281682b
SM		 2437 u8 user_index[0x18];
2438
b4ff3a36 2439 u8 reserved_at_40[0x8];
e281682b
SM		 2440 u8 cqn[0x18];
2441
7486216b 2442 u8 reserved_at_60[0x90];
e281682b 2443
7486216b 2444 u8 packet_pacing_rate_limit_index[0x10];
e281682b 2445 u8 tis_lst_sz[0x10];
b4ff3a36 2446 u8 reserved_at_110[0x10];
e281682b 2447
b4ff3a36 2448 u8 reserved_at_120[0x40];
e281682b 2449
b4ff3a36 2450 u8 reserved_at_160[0x8];
e281682b
SM		 2451 u8 tis_num_0[0x18];
2452
2453 struct mlx5_ifc_wq_bits wq;
2454};
2455
813f8540
MHY		 2456enum {
2457 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2458 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2459 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2460 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2461};
2462
2463struct mlx5_ifc_scheduling_context_bits {
2464 u8 element_type[0x8];
2465 u8 reserved_at_8[0x18];
2466
2467 u8 element_attributes[0x20];
2468
2469 u8 parent_element_id[0x20];
2470
2471 u8 reserved_at_60[0x40];
2472
2473 u8 bw_share[0x20];
2474
2475 u8 max_average_bw[0x20];
2476
2477 u8 reserved_at_e0[0x120];
2478};
2479
e281682b 2480struct mlx5_ifc_rqtc_bits {
b4ff3a36 2481 u8 reserved_at_0[0xa0];
e281682b 2482
b4ff3a36 2483 u8 reserved_at_a0[0x10];
e281682b
SM		 2484 u8 rqt_max_size[0x10];
2485
b4ff3a36 2486 u8 reserved_at_c0[0x10];
e281682b
SM		 2487 u8 rqt_actual_size[0x10];
2488
b4ff3a36 2489 u8 reserved_at_e0[0x6a0];
e281682b
SM		 2490
2491 struct mlx5_ifc_rq_num_bits rq_num[0];
2492};
2493
2494enum {
2495 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2496 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2497};
2498
2499enum {
2500 MLX5_RQC_STATE_RST = 0x0,
2501 MLX5_RQC_STATE_RDY = 0x1,
2502 MLX5_RQC_STATE_ERR = 0x3,
2503};
2504
2505struct mlx5_ifc_rqc_bits {
2506 u8 rlky[0x1];
7d5e1423
SM		 2507 u8 reserved_at_1[0x1];
2508 u8 scatter_fcs[0x1];
e281682b
SM		 2509 u8 vsd[0x1];
2510 u8 mem_rq_type[0x4];
2511 u8 state[0x4];
b4ff3a36 2512 u8 reserved_at_c[0x1];
e281682b 2513 u8 flush_in_error_en[0x1];
b4ff3a36 2514 u8 reserved_at_e[0x12];
e281682b 2515
b4ff3a36 2516 u8 reserved_at_20[0x8];
e281682b
SM		 2517 u8 user_index[0x18];
2518
b4ff3a36 2519 u8 reserved_at_40[0x8];
e281682b
SM		 2520 u8 cqn[0x18];
2521
2522 u8 counter_set_id[0x8];
b4ff3a36 2523 u8 reserved_at_68[0x18];
e281682b 2524
b4ff3a36 2525 u8 reserved_at_80[0x8];
e281682b
SM		 2526 u8 rmpn[0x18];
2527
b4ff3a36 2528 u8 reserved_at_a0[0xe0];
e281682b
SM		 2529
2530 struct mlx5_ifc_wq_bits wq;
2531};
2532
2533enum {
2534 MLX5_RMPC_STATE_RDY = 0x1,
2535 MLX5_RMPC_STATE_ERR = 0x3,
2536};
2537
2538struct mlx5_ifc_rmpc_bits {
b4ff3a36 2539 u8 reserved_at_0[0x8];
e281682b 2540 u8 state[0x4];
b4ff3a36 2541 u8 reserved_at_c[0x14];
e281682b
SM		 2542
2543 u8 basic_cyclic_rcv_wqe[0x1];
b4ff3a36 2544 u8 reserved_at_21[0x1f];
e281682b 2545
b4ff3a36 2546 u8 reserved_at_40[0x140];
e281682b
SM		 2547
2548 struct mlx5_ifc_wq_bits wq;
2549};
2550
e281682b 2551struct mlx5_ifc_nic_vport_context_bits {
cff92d7c
HHZ		 2552 u8 reserved_at_0[0x5];
2553 u8 min_wqe_inline_mode[0x3];
2554 u8 reserved_at_8[0x17];
e281682b
SM		 2555 u8 roce_en[0x1];
2556
d82b7318 2557 u8 arm_change_event[0x1];
b4ff3a36 2558 u8 reserved_at_21[0x1a];
d82b7318
SM		 2559 u8 event_on_mtu[0x1];
2560 u8 event_on_promisc_change[0x1];
2561 u8 event_on_vlan_change[0x1];
2562 u8 event_on_mc_address_change[0x1];
2563 u8 event_on_uc_address_change[0x1];
e281682b 2564
b4ff3a36 2565 u8 reserved_at_40[0xf0];
d82b7318
SM		 2566
2567 u8 mtu[0x10];
2568
9efa7525
AS		 2569 u8 system_image_guid[0x40];
2570 u8 port_guid[0x40];
2571 u8 node_guid[0x40];
2572
b4ff3a36 2573 u8 reserved_at_200[0x140];
9efa7525 2574 u8 qkey_violation_counter[0x10];
b4ff3a36 2575 u8 reserved_at_350[0x430];
d82b7318
SM		 2576
2577 u8 promisc_uc[0x1];
2578 u8 promisc_mc[0x1];
2579 u8 promisc_all[0x1];
b4ff3a36 2580 u8 reserved_at_783[0x2];
e281682b 2581 u8 allowed_list_type[0x3];
b4ff3a36 2582 u8 reserved_at_788[0xc];
e281682b
SM		 2583 u8 allowed_list_size[0xc];
2584
2585 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2586
b4ff3a36 2587 u8 reserved_at_7e0[0x20];
e281682b
SM		 2588
2589 u8 current_uc_mac_address[0][0x40];
2590};
2591
2592enum {
2593 MLX5_MKC_ACCESS_MODE_PA = 0x0,
2594 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
2595 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
bcda1aca 2596 MLX5_MKC_ACCESS_MODE_KSM = 0x3,
e281682b
SM		 2597};
2598
2599struct mlx5_ifc_mkc_bits {
b4ff3a36 2600 u8 reserved_at_0[0x1];
e281682b 2601 u8 free[0x1];
b4ff3a36 2602 u8 reserved_at_2[0xd];
e281682b
SM		 2603 u8 small_fence_on_rdma_read_response[0x1];
2604 u8 umr_en[0x1];
2605 u8 a[0x1];
2606 u8 rw[0x1];
2607 u8 rr[0x1];
2608 u8 lw[0x1];
2609 u8 lr[0x1];
2610 u8 access_mode[0x2];
b4ff3a36 2611 u8 reserved_at_18[0x8];
e281682b
SM		 2612
2613 u8 qpn[0x18];
2614 u8 mkey_7_0[0x8];
2615
b4ff3a36 2616 u8 reserved_at_40[0x20];
e281682b
SM		 2617
2618 u8 length64[0x1];
2619 u8 bsf_en[0x1];
2620 u8 sync_umr[0x1];
b4ff3a36 2621 u8 reserved_at_63[0x2];
e281682b 2622 u8 expected_sigerr_count[0x1];
b4ff3a36 2623 u8 reserved_at_66[0x1];
e281682b
SM		 2624 u8 en_rinval[0x1];
2625 u8 pd[0x18];
2626
2627 u8 start_addr[0x40];
2628
2629 u8 len[0x40];
2630
2631 u8 bsf_octword_size[0x20];
2632
b4ff3a36 2633 u8 reserved_at_120[0x80];
e281682b
SM		 2634
2635 u8 translations_octword_size[0x20];
2636
b4ff3a36 2637 u8 reserved_at_1c0[0x1b];
e281682b
SM		 2638 u8 log_page_size[0x5];
2639
b4ff3a36 2640 u8 reserved_at_1e0[0x20];
e281682b
SM		 2641};
2642
2643struct mlx5_ifc_pkey_bits {
b4ff3a36 2644 u8 reserved_at_0[0x10];
e281682b
SM		 2645 u8 pkey[0x10];
2646};
2647
2648struct mlx5_ifc_array128_auto_bits {
2649 u8 array128_auto[16][0x8];
2650};
2651
2652struct mlx5_ifc_hca_vport_context_bits {
2653 u8 field_select[0x20];
2654
b4ff3a36 2655 u8 reserved_at_20[0xe0];
e281682b
SM		 2656
2657 u8 sm_virt_aware[0x1];
2658 u8 has_smi[0x1];
2659 u8 has_raw[0x1];
2660 u8 grh_required[0x1];
b4ff3a36 2661 u8 reserved_at_104[0xc];
707c4602
MD		 2662 u8 port_physical_state[0x4];
2663 u8 vport_state_policy[0x4];
2664 u8 port_state[0x4];
e281682b
SM		 2665 u8 vport_state[0x4];
2666
b4ff3a36 2667 u8 reserved_at_120[0x20];
707c4602
MD		 2668
2669 u8 system_image_guid[0x40];
e281682b
SM		 2670
2671 u8 port_guid[0x40];
2672
2673 u8 node_guid[0x40];
2674
2675 u8 cap_mask1[0x20];
2676
2677 u8 cap_mask1_field_select[0x20];
2678
2679 u8 cap_mask2[0x20];
2680
2681 u8 cap_mask2_field_select[0x20];
2682
b4ff3a36 2683 u8 reserved_at_280[0x80];
e281682b
SM		 2684
2685 u8 lid[0x10];
b4ff3a36 2686 u8 reserved_at_310[0x4];
e281682b
SM		 2687 u8 init_type_reply[0x4];
2688 u8 lmc[0x3];
2689 u8 subnet_timeout[0x5];
2690
2691 u8 sm_lid[0x10];
2692 u8 sm_sl[0x4];
b4ff3a36 2693 u8 reserved_at_334[0xc];
e281682b
SM		 2694
2695 u8 qkey_violation_counter[0x10];
2696 u8 pkey_violation_counter[0x10];
2697
b4ff3a36 2698 u8 reserved_at_360[0xca0];
e281682b
SM		 2699};
2700
d6666753 2701struct mlx5_ifc_esw_vport_context_bits {
b4ff3a36 2702 u8 reserved_at_0[0x3];
d6666753
SM		 2703 u8 vport_svlan_strip[0x1];
2704 u8 vport_cvlan_strip[0x1];
2705 u8 vport_svlan_insert[0x1];
2706 u8 vport_cvlan_insert[0x2];
b4ff3a36 2707 u8 reserved_at_8[0x18];
d6666753 2708
b4ff3a36 2709 u8 reserved_at_20[0x20];
d6666753
SM		 2710
2711 u8 svlan_cfi[0x1];
2712 u8 svlan_pcp[0x3];
2713 u8 svlan_id[0xc];
2714 u8 cvlan_cfi[0x1];
2715 u8 cvlan_pcp[0x3];
2716 u8 cvlan_id[0xc];
2717
b4ff3a36 2718 u8 reserved_at_60[0x7a0];
d6666753
SM		 2719};
2720
e281682b
SM		 2721enum {
2722 MLX5_EQC_STATUS_OK = 0x0,
2723 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
2724};
2725
2726enum {
2727 MLX5_EQC_ST_ARMED = 0x9,
2728 MLX5_EQC_ST_FIRED = 0xa,
2729};
2730
2731struct mlx5_ifc_eqc_bits {
2732 u8 status[0x4];
b4ff3a36 2733 u8 reserved_at_4[0x9];
e281682b
SM		 2734 u8 ec[0x1];
2735 u8 oi[0x1];
b4ff3a36 2736 u8 reserved_at_f[0x5];
e281682b 2737 u8 st[0x4];
b4ff3a36 2738 u8 reserved_at_18[0x8];
e281682b 2739
b4ff3a36 2740 u8 reserved_at_20[0x20];
e281682b 2741
b4ff3a36 2742 u8 reserved_at_40[0x14];
e281682b 2743 u8 page_offset[0x6];
b4ff3a36 2744 u8 reserved_at_5a[0x6];
e281682b 2745
b4ff3a36 2746 u8 reserved_at_60[0x3];
e281682b
SM		 2747 u8 log_eq_size[0x5];
2748 u8 uar_page[0x18];
2749
b4ff3a36 2750 u8 reserved_at_80[0x20];
e281682b 2751
b4ff3a36 2752 u8 reserved_at_a0[0x18];
e281682b
SM		 2753 u8 intr[0x8];
2754
b4ff3a36 2755 u8 reserved_at_c0[0x3];
e281682b 2756 u8 log_page_size[0x5];
b4ff3a36 2757 u8 reserved_at_c8[0x18];
e281682b 2758
b4ff3a36 2759 u8 reserved_at_e0[0x60];
e281682b 2760
b4ff3a36 2761 u8 reserved_at_140[0x8];
e281682b
SM		 2762 u8 consumer_counter[0x18];
2763
b4ff3a36 2764 u8 reserved_at_160[0x8];
e281682b
SM		 2765 u8 producer_counter[0x18];
2766
b4ff3a36 2767 u8 reserved_at_180[0x80];
e281682b
SM		 2768};
2769
2770enum {
2771 MLX5_DCTC_STATE_ACTIVE = 0x0,
2772 MLX5_DCTC_STATE_DRAINING = 0x1,
2773 MLX5_DCTC_STATE_DRAINED = 0x2,
2774};
2775
2776enum {
2777 MLX5_DCTC_CS_RES_DISABLE = 0x0,
2778 MLX5_DCTC_CS_RES_NA = 0x1,
2779 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
2780};
2781
2782enum {
2783 MLX5_DCTC_MTU_256_BYTES = 0x1,
2784 MLX5_DCTC_MTU_512_BYTES = 0x2,
2785 MLX5_DCTC_MTU_1K_BYTES = 0x3,
2786 MLX5_DCTC_MTU_2K_BYTES = 0x4,
2787 MLX5_DCTC_MTU_4K_BYTES = 0x5,
2788};
2789
2790struct mlx5_ifc_dctc_bits {
b4ff3a36 2791 u8 reserved_at_0[0x4];
e281682b 2792 u8 state[0x4];
b4ff3a36 2793 u8 reserved_at_8[0x18];
e281682b 2794
b4ff3a36 2795 u8 reserved_at_20[0x8];
e281682b
SM		 2796 u8 user_index[0x18];
2797
b4ff3a36 2798 u8 reserved_at_40[0x8];
e281682b
SM		 2799 u8 cqn[0x18];
2800
2801 u8 counter_set_id[0x8];
2802 u8 atomic_mode[0x4];
2803 u8 rre[0x1];
2804 u8 rwe[0x1];
2805 u8 rae[0x1];
2806 u8 atomic_like_write_en[0x1];
2807 u8 latency_sensitive[0x1];
2808 u8 rlky[0x1];
2809 u8 free_ar[0x1];
b4ff3a36 2810 u8 reserved_at_73[0xd];
e281682b 2811
b4ff3a36 2812 u8 reserved_at_80[0x8];
e281682b 2813 u8 cs_res[0x8];
b4ff3a36 2814 u8 reserved_at_90[0x3];
e281682b 2815 u8 min_rnr_nak[0x5];
b4ff3a36 2816 u8 reserved_at_98[0x8];
e281682b 2817
b4ff3a36 2818 u8 reserved_at_a0[0x8];
7486216b 2819 u8 srqn_xrqn[0x18];
e281682b 2820
b4ff3a36 2821 u8 reserved_at_c0[0x8];
e281682b
SM		 2822 u8 pd[0x18];
2823
2824 u8 tclass[0x8];
b4ff3a36 2825 u8 reserved_at_e8[0x4];
e281682b
SM		 2826 u8 flow_label[0x14];
2827
2828 u8 dc_access_key[0x40];
2829
b4ff3a36 2830 u8 reserved_at_140[0x5];
e281682b
SM		 2831 u8 mtu[0x3];
2832 u8 port[0x8];
2833 u8 pkey_index[0x10];
2834
b4ff3a36 2835 u8 reserved_at_160[0x8];
e281682b 2836 u8 my_addr_index[0x8];
b4ff3a36 2837 u8 reserved_at_170[0x8];
e281682b
SM		 2838 u8 hop_limit[0x8];
2839
2840 u8 dc_access_key_violation_count[0x20];
2841
b4ff3a36 2842 u8 reserved_at_1a0[0x14];
e281682b
SM		 2843 u8 dei_cfi[0x1];
2844 u8 eth_prio[0x3];
2845 u8 ecn[0x2];
2846 u8 dscp[0x6];
2847
b4ff3a36 2848 u8 reserved_at_1c0[0x40];
e281682b
SM		 2849};
2850
2851enum {
2852 MLX5_CQC_STATUS_OK = 0x0,
2853 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
2854 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
2855};
2856
2857enum {
2858 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
2859 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
2860};
2861
2862enum {
2863 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
2864 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
2865 MLX5_CQC_ST_FIRED = 0xa,
2866};
2867
7d5e1423
SM		 2868enum {
2869 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
2870 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
7486216b 2871 MLX5_CQ_PERIOD_NUM_MODES
7d5e1423
SM		 2872};
2873
e281682b
SM		 2874struct mlx5_ifc_cqc_bits {
2875 u8 status[0x4];
b4ff3a36 2876 u8 reserved_at_4[0x4];
e281682b
SM		 2877 u8 cqe_sz[0x3];
2878 u8 cc[0x1];
b4ff3a36 2879 u8 reserved_at_c[0x1];
e281682b
SM		 2880 u8 scqe_break_moderation_en[0x1];
2881 u8 oi[0x1];
7d5e1423
SM		 2882 u8 cq_period_mode[0x2];
2883 u8 cqe_comp_en[0x1];
e281682b
SM		 2884 u8 mini_cqe_res_format[0x2];
2885 u8 st[0x4];
b4ff3a36 2886 u8 reserved_at_18[0x8];
e281682b 2887
b4ff3a36 2888 u8 reserved_at_20[0x20];
e281682b 2889
b4ff3a36 2890 u8 reserved_at_40[0x14];
e281682b 2891 u8 page_offset[0x6];
b4ff3a36 2892 u8 reserved_at_5a[0x6];
e281682b 2893
b4ff3a36 2894 u8 reserved_at_60[0x3];
e281682b
SM		 2895 u8 log_cq_size[0x5];
2896 u8 uar_page[0x18];
2897
b4ff3a36 2898 u8 reserved_at_80[0x4];
e281682b
SM		 2899 u8 cq_period[0xc];
2900 u8 cq_max_count[0x10];
2901
b4ff3a36 2902 u8 reserved_at_a0[0x18];
e281682b
SM		 2903 u8 c_eqn[0x8];
2904
b4ff3a36 2905 u8 reserved_at_c0[0x3];
e281682b 2906 u8 log_page_size[0x5];
b4ff3a36 2907 u8 reserved_at_c8[0x18];
e281682b 2908
b4ff3a36 2909 u8 reserved_at_e0[0x20];
e281682b 2910
b4ff3a36 2911 u8 reserved_at_100[0x8];
e281682b
SM		 2912 u8 last_notified_index[0x18];
2913
b4ff3a36 2914 u8 reserved_at_120[0x8];
e281682b
SM		 2915 u8 last_solicit_index[0x18];
2916
b4ff3a36 2917 u8 reserved_at_140[0x8];
e281682b
SM		 2918 u8 consumer_counter[0x18];
2919
b4ff3a36 2920 u8 reserved_at_160[0x8];
e281682b
SM		 2921 u8 producer_counter[0x18];
2922
b4ff3a36 2923 u8 reserved_at_180[0x40];
e281682b
SM		 2924
2925 u8 dbr_addr[0x40];
2926};
2927
2928union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2929 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2930 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2931 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
b4ff3a36 2932 u8 reserved_at_0[0x800];
e281682b
SM		 2933};
2934
2935struct mlx5_ifc_query_adapter_param_block_bits {
b4ff3a36 2936 u8 reserved_at_0[0xc0];
e281682b 2937
b4ff3a36 2938 u8 reserved_at_c0[0x8];
211e6c80
MD		 2939 u8 ieee_vendor_id[0x18];
2940
b4ff3a36 2941 u8 reserved_at_e0[0x10];
e281682b
SM		 2942 u8 vsd_vendor_id[0x10];
2943
2944 u8 vsd[208][0x8];
2945
2946 u8 vsd_contd_psid[16][0x8];
2947};
2948
7486216b
SM		 2949enum {
2950 MLX5_XRQC_STATE_GOOD = 0x0,
2951 MLX5_XRQC_STATE_ERROR = 0x1,
2952};
2953
2954enum {
2955 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
2956 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
2957};
2958
2959enum {
2960 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
2961};
2962
2963struct mlx5_ifc_tag_matching_topology_context_bits {
2964 u8 log_matching_list_sz[0x4];
2965 u8 reserved_at_4[0xc];
2966 u8 append_next_index[0x10];
2967
2968 u8 sw_phase_cnt[0x10];
2969 u8 hw_phase_cnt[0x10];
2970
2971 u8 reserved_at_40[0x40];
2972};
2973
2974struct mlx5_ifc_xrqc_bits {
2975 u8 state[0x4];
2976 u8 rlkey[0x1];
2977 u8 reserved_at_5[0xf];
2978 u8 topology[0x4];
2979 u8 reserved_at_18[0x4];
2980 u8 offload[0x4];
2981
2982 u8 reserved_at_20[0x8];
2983 u8 user_index[0x18];
2984
2985 u8 reserved_at_40[0x8];
2986 u8 cqn[0x18];
2987
2988 u8 reserved_at_60[0xa0];
2989
2990 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
2991
5579e151 2992 u8 reserved_at_180[0x880];
7486216b
SM		 2993
2994 struct mlx5_ifc_wq_bits wq;
2995};
2996
e281682b
SM		 2997union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2998 struct mlx5_ifc_modify_field_select_bits modify_field_select;
2999 struct mlx5_ifc_resize_field_select_bits resize_field_select;
b4ff3a36 3000 u8 reserved_at_0[0x20];
e281682b
SM		 3001};
3002
3003union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3004 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3005 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3006 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
b4ff3a36 3007 u8 reserved_at_0[0x20];
e281682b
SM		 3008};
3009
3010union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3011 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3012 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3013 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3014 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3015 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3016 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3017 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
1c64bf6f 3018 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b 3019 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
d8dc0508 3020 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
b4ff3a36 3021 u8 reserved_at_0[0x7c0];
e281682b
SM		 3022};
3023
8ed1a630
GP		 3024union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3025 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3026 u8 reserved_at_0[0x7c0];
3027};
3028
e281682b
SM		 3029union mlx5_ifc_event_auto_bits {
3030 struct mlx5_ifc_comp_event_bits comp_event;
3031 struct mlx5_ifc_dct_events_bits dct_events;
3032 struct mlx5_ifc_qp_events_bits qp_events;
3033 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3034 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3035 struct mlx5_ifc_cq_error_bits cq_error;
3036 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3037 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3038 struct mlx5_ifc_gpio_event_bits gpio_event;
3039 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3040 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3041 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
b4ff3a36 3042 u8 reserved_at_0[0xe0];
e281682b
SM		 3043};
3044
3045struct mlx5_ifc_health_buffer_bits {
b4ff3a36 3046 u8 reserved_at_0[0x100];
e281682b
SM		 3047
3048 u8 assert_existptr[0x20];
3049
3050 u8 assert_callra[0x20];
3051
b4ff3a36 3052 u8 reserved_at_140[0x40];
e281682b
SM		 3053
3054 u8 fw_version[0x20];
3055
3056 u8 hw_id[0x20];
3057
b4ff3a36 3058 u8 reserved_at_1c0[0x20];
e281682b
SM		 3059
3060 u8 irisc_index[0x8];
3061 u8 synd[0x8];
3062 u8 ext_synd[0x10];
3063};
3064
3065struct mlx5_ifc_register_loopback_control_bits {
3066 u8 no_lb[0x1];
b4ff3a36 3067 u8 reserved_at_1[0x7];
e281682b 3068 u8 port[0x8];
b4ff3a36 3069 u8 reserved_at_10[0x10];
e281682b 3070
b4ff3a36 3071 u8 reserved_at_20[0x60];
e281682b
SM		 3072};
3073
813f8540
MHY		 3074struct mlx5_ifc_vport_tc_element_bits {
3075 u8 traffic_class[0x4];
3076 u8 reserved_at_4[0xc];
3077 u8 vport_number[0x10];
3078};
3079
3080struct mlx5_ifc_vport_element_bits {
3081 u8 reserved_at_0[0x10];
3082 u8 vport_number[0x10];
3083};
3084
3085enum {
3086 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3087 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3088 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3089};
3090
3091struct mlx5_ifc_tsar_element_bits {
3092 u8 reserved_at_0[0x8];
3093 u8 tsar_type[0x8];
3094 u8 reserved_at_10[0x10];
3095};
3096
e281682b
SM		 3097struct mlx5_ifc_teardown_hca_out_bits {
3098 u8 status[0x8];
b4ff3a36 3099 u8 reserved_at_8[0x18];
e281682b
SM		 3100
3101 u8 syndrome[0x20];
3102
b4ff3a36 3103 u8 reserved_at_40[0x40];
e281682b
SM		 3104};
3105
3106enum {
3107 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
3108 MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE = 0x1,
3109};
3110
3111struct mlx5_ifc_teardown_hca_in_bits {
3112 u8 opcode[0x10];
b4ff3a36 3113 u8 reserved_at_10[0x10];
e281682b 3114
b4ff3a36 3115 u8 reserved_at_20[0x10];
e281682b
SM		 3116 u8 op_mod[0x10];
3117
b4ff3a36 3118 u8 reserved_at_40[0x10];
e281682b
SM		 3119 u8 profile[0x10];
3120
b4ff3a36 3121 u8 reserved_at_60[0x20];
e281682b
SM		 3122};
3123
3124struct mlx5_ifc_sqerr2rts_qp_out_bits {
3125 u8 status[0x8];
b4ff3a36 3126 u8 reserved_at_8[0x18];
e281682b
SM		 3127
3128 u8 syndrome[0x20];
3129
b4ff3a36 3130 u8 reserved_at_40[0x40];
e281682b
SM		 3131};
3132
3133struct mlx5_ifc_sqerr2rts_qp_in_bits {
3134 u8 opcode[0x10];
b4ff3a36 3135 u8 reserved_at_10[0x10];
e281682b 3136
b4ff3a36 3137 u8 reserved_at_20[0x10];
e281682b
SM		 3138 u8 op_mod[0x10];
3139
b4ff3a36 3140 u8 reserved_at_40[0x8];
e281682b
SM		 3141 u8 qpn[0x18];
3142
b4ff3a36 3143 u8 reserved_at_60[0x20];
e281682b
SM		 3144
3145 u8 opt_param_mask[0x20];
3146
b4ff3a36 3147 u8 reserved_at_a0[0x20];
e281682b
SM		 3148
3149 struct mlx5_ifc_qpc_bits qpc;
3150
b4ff3a36 3151 u8 reserved_at_800[0x80];
e281682b
SM		 3152};
3153
3154struct mlx5_ifc_sqd2rts_qp_out_bits {
3155 u8 status[0x8];
b4ff3a36 3156 u8 reserved_at_8[0x18];
e281682b
SM		 3157
3158 u8 syndrome[0x20];
3159
b4ff3a36 3160 u8 reserved_at_40[0x40];
e281682b
SM		 3161};
3162
3163struct mlx5_ifc_sqd2rts_qp_in_bits {
3164 u8 opcode[0x10];
b4ff3a36 3165 u8 reserved_at_10[0x10];
e281682b 3166
b4ff3a36 3167 u8 reserved_at_20[0x10];
e281682b
SM		 3168 u8 op_mod[0x10];
3169
b4ff3a36 3170 u8 reserved_at_40[0x8];
e281682b
SM		 3171 u8 qpn[0x18];
3172
b4ff3a36 3173 u8 reserved_at_60[0x20];
e281682b
SM		 3174
3175 u8 opt_param_mask[0x20];
3176
b4ff3a36 3177 u8 reserved_at_a0[0x20];
e281682b
SM		 3178
3179 struct mlx5_ifc_qpc_bits qpc;
3180
b4ff3a36 3181 u8 reserved_at_800[0x80];
e281682b
SM		 3182};
3183
3184struct mlx5_ifc_set_roce_address_out_bits {
3185 u8 status[0x8];
b4ff3a36 3186 u8 reserved_at_8[0x18];
e281682b
SM		 3187
3188 u8 syndrome[0x20];
3189
b4ff3a36 3190 u8 reserved_at_40[0x40];
e281682b
SM		 3191};
3192
3193struct mlx5_ifc_set_roce_address_in_bits {
3194 u8 opcode[0x10];
b4ff3a36 3195 u8 reserved_at_10[0x10];
e281682b 3196
b4ff3a36 3197 u8 reserved_at_20[0x10];
e281682b
SM		 3198 u8 op_mod[0x10];
3199
3200 u8 roce_address_index[0x10];
b4ff3a36 3201 u8 reserved_at_50[0x10];
e281682b 3202
b4ff3a36 3203 u8 reserved_at_60[0x20];
e281682b
SM		 3204
3205 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3206};
3207
3208struct mlx5_ifc_set_mad_demux_out_bits {
3209 u8 status[0x8];
b4ff3a36 3210 u8 reserved_at_8[0x18];
e281682b
SM		 3211
3212 u8 syndrome[0x20];
3213
b4ff3a36 3214 u8 reserved_at_40[0x40];
e281682b
SM		 3215};
3216
3217enum {
3218 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
3219 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
3220};
3221
3222struct mlx5_ifc_set_mad_demux_in_bits {
3223 u8 opcode[0x10];
b4ff3a36 3224 u8 reserved_at_10[0x10];
e281682b 3225
b4ff3a36 3226 u8 reserved_at_20[0x10];
e281682b
SM		 3227 u8 op_mod[0x10];
3228
b4ff3a36 3229 u8 reserved_at_40[0x20];
e281682b 3230
b4ff3a36 3231 u8 reserved_at_60[0x6];
e281682b 3232 u8 demux_mode[0x2];
b4ff3a36 3233 u8 reserved_at_68[0x18];
e281682b
SM		 3234};
3235
3236struct mlx5_ifc_set_l2_table_entry_out_bits {
3237 u8 status[0x8];
b4ff3a36 3238 u8 reserved_at_8[0x18];
e281682b
SM		 3239
3240 u8 syndrome[0x20];
3241
b4ff3a36 3242 u8 reserved_at_40[0x40];
e281682b
SM		 3243};
3244
3245struct mlx5_ifc_set_l2_table_entry_in_bits {
3246 u8 opcode[0x10];
b4ff3a36 3247 u8 reserved_at_10[0x10];
e281682b 3248
b4ff3a36 3249 u8 reserved_at_20[0x10];
e281682b
SM		 3250 u8 op_mod[0x10];
3251
b4ff3a36 3252 u8 reserved_at_40[0x60];
e281682b 3253
b4ff3a36 3254 u8 reserved_at_a0[0x8];
e281682b
SM		 3255 u8 table_index[0x18];
3256
b4ff3a36 3257 u8 reserved_at_c0[0x20];
e281682b 3258
b4ff3a36 3259 u8 reserved_at_e0[0x13];
e281682b
SM		 3260 u8 vlan_valid[0x1];
3261 u8 vlan[0xc];
3262
3263 struct mlx5_ifc_mac_address_layout_bits mac_address;
3264
b4ff3a36 3265 u8 reserved_at_140[0xc0];
e281682b
SM		 3266};
3267
3268struct mlx5_ifc_set_issi_out_bits {
3269 u8 status[0x8];
b4ff3a36 3270 u8 reserved_at_8[0x18];
e281682b
SM		 3271
3272 u8 syndrome[0x20];
3273
b4ff3a36 3274 u8 reserved_at_40[0x40];
e281682b
SM		 3275};
3276
3277struct mlx5_ifc_set_issi_in_bits {
3278 u8 opcode[0x10];
b4ff3a36 3279 u8 reserved_at_10[0x10];
e281682b 3280
b4ff3a36 3281 u8 reserved_at_20[0x10];
e281682b
SM		 3282 u8 op_mod[0x10];
3283
b4ff3a36 3284 u8 reserved_at_40[0x10];
e281682b
SM		 3285 u8 current_issi[0x10];
3286
b4ff3a36 3287 u8 reserved_at_60[0x20];
e281682b
SM		 3288};
3289
3290struct mlx5_ifc_set_hca_cap_out_bits {
3291 u8 status[0x8];
b4ff3a36 3292 u8 reserved_at_8[0x18];
e281682b
SM		 3293
3294 u8 syndrome[0x20];
3295
b4ff3a36 3296 u8 reserved_at_40[0x40];
e281682b
SM		 3297};
3298
3299struct mlx5_ifc_set_hca_cap_in_bits {
3300 u8 opcode[0x10];
b4ff3a36 3301 u8 reserved_at_10[0x10];
e281682b 3302
b4ff3a36 3303 u8 reserved_at_20[0x10];
e281682b
SM		 3304 u8 op_mod[0x10];
3305
b4ff3a36 3306 u8 reserved_at_40[0x40];
e281682b
SM		 3307
3308 union mlx5_ifc_hca_cap_union_bits capability;
3309};
3310
26a81453
MG		 3311enum {
3312 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
3313 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
3314 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
3315 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
3316};
3317
e281682b
SM		 3318struct mlx5_ifc_set_fte_out_bits {
3319 u8 status[0x8];
b4ff3a36 3320 u8 reserved_at_8[0x18];
e281682b
SM		 3321
3322 u8 syndrome[0x20];
3323
b4ff3a36 3324 u8 reserved_at_40[0x40];
e281682b
SM		 3325};
3326
3327struct mlx5_ifc_set_fte_in_bits {
3328 u8 opcode[0x10];
b4ff3a36 3329 u8 reserved_at_10[0x10];
e281682b 3330
b4ff3a36 3331 u8 reserved_at_20[0x10];
e281682b
SM		 3332 u8 op_mod[0x10];
3333
7d5e1423
SM		 3334 u8 other_vport[0x1];
3335 u8 reserved_at_41[0xf];
3336 u8 vport_number[0x10];
3337
3338 u8 reserved_at_60[0x20];
e281682b
SM		 3339
3340 u8 table_type[0x8];
b4ff3a36 3341 u8 reserved_at_88[0x18];
e281682b 3342
b4ff3a36 3343 u8 reserved_at_a0[0x8];
e281682b
SM		 3344 u8 table_id[0x18];
3345
b4ff3a36 3346 u8 reserved_at_c0[0x18];
26a81453
MG		 3347 u8 modify_enable_mask[0x8];
3348
b4ff3a36 3349 u8 reserved_at_e0[0x20];
e281682b
SM		 3350
3351 u8 flow_index[0x20];
3352
b4ff3a36 3353 u8 reserved_at_120[0xe0];
e281682b
SM		 3354
3355 struct mlx5_ifc_flow_context_bits flow_context;
3356};
3357
3358struct mlx5_ifc_rts2rts_qp_out_bits {
3359 u8 status[0x8];
b4ff3a36 3360 u8 reserved_at_8[0x18];
e281682b
SM		 3361
3362 u8 syndrome[0x20];
3363
b4ff3a36 3364 u8 reserved_at_40[0x40];
e281682b
SM		 3365};
3366
3367struct mlx5_ifc_rts2rts_qp_in_bits {
3368 u8 opcode[0x10];
b4ff3a36 3369 u8 reserved_at_10[0x10];
e281682b 3370
b4ff3a36 3371 u8 reserved_at_20[0x10];
e281682b
SM		 3372 u8 op_mod[0x10];
3373
b4ff3a36 3374 u8 reserved_at_40[0x8];
e281682b
SM		 3375 u8 qpn[0x18];
3376
b4ff3a36 3377 u8 reserved_at_60[0x20];
e281682b
SM		 3378
3379 u8 opt_param_mask[0x20];
3380
b4ff3a36 3381 u8 reserved_at_a0[0x20];
e281682b
SM		 3382
3383 struct mlx5_ifc_qpc_bits qpc;
3384
b4ff3a36 3385 u8 reserved_at_800[0x80];
e281682b
SM		 3386};
3387
3388struct mlx5_ifc_rtr2rts_qp_out_bits {
3389 u8 status[0x8];
b4ff3a36 3390 u8 reserved_at_8[0x18];
e281682b
SM		 3391
3392 u8 syndrome[0x20];
3393
b4ff3a36 3394 u8 reserved_at_40[0x40];
e281682b
SM		 3395};
3396
3397struct mlx5_ifc_rtr2rts_qp_in_bits {
3398 u8 opcode[0x10];
b4ff3a36 3399 u8 reserved_at_10[0x10];
e281682b 3400
b4ff3a36 3401 u8 reserved_at_20[0x10];
e281682b
SM		 3402 u8 op_mod[0x10];
3403
b4ff3a36 3404 u8 reserved_at_40[0x8];
e281682b
SM		 3405 u8 qpn[0x18];
3406
b4ff3a36 3407 u8 reserved_at_60[0x20];
e281682b
SM		 3408
3409 u8 opt_param_mask[0x20];
3410
b4ff3a36 3411 u8 reserved_at_a0[0x20];
e281682b
SM		 3412
3413 struct mlx5_ifc_qpc_bits qpc;
3414
b4ff3a36 3415 u8 reserved_at_800[0x80];
e281682b
SM		 3416};
3417
3418struct mlx5_ifc_rst2init_qp_out_bits {
3419 u8 status[0x8];
b4ff3a36 3420 u8 reserved_at_8[0x18];
e281682b
SM		 3421
3422 u8 syndrome[0x20];
3423
b4ff3a36 3424 u8 reserved_at_40[0x40];
e281682b
SM		 3425};
3426
3427struct mlx5_ifc_rst2init_qp_in_bits {
3428 u8 opcode[0x10];
b4ff3a36 3429 u8 reserved_at_10[0x10];
e281682b 3430
b4ff3a36 3431 u8 reserved_at_20[0x10];
e281682b
SM		 3432 u8 op_mod[0x10];
3433
b4ff3a36 3434 u8 reserved_at_40[0x8];
e281682b
SM		 3435 u8 qpn[0x18];
3436
b4ff3a36 3437 u8 reserved_at_60[0x20];
e281682b
SM		 3438
3439 u8 opt_param_mask[0x20];
3440
b4ff3a36 3441 u8 reserved_at_a0[0x20];
e281682b
SM		 3442
3443 struct mlx5_ifc_qpc_bits qpc;
3444
b4ff3a36 3445 u8 reserved_at_800[0x80];
e281682b
SM		 3446};
3447
7486216b
SM		 3448struct mlx5_ifc_query_xrq_out_bits {
3449 u8 status[0x8];
3450 u8 reserved_at_8[0x18];
3451
3452 u8 syndrome[0x20];
3453
3454 u8 reserved_at_40[0x40];
3455
3456 struct mlx5_ifc_xrqc_bits xrq_context;
3457};
3458
3459struct mlx5_ifc_query_xrq_in_bits {
3460 u8 opcode[0x10];
3461 u8 reserved_at_10[0x10];
3462
3463 u8 reserved_at_20[0x10];
3464 u8 op_mod[0x10];
3465
3466 u8 reserved_at_40[0x8];
3467 u8 xrqn[0x18];
3468
3469 u8 reserved_at_60[0x20];
3470};
3471
e281682b
SM		 3472struct mlx5_ifc_query_xrc_srq_out_bits {
3473 u8 status[0x8];
b4ff3a36 3474 u8 reserved_at_8[0x18];
e281682b
SM		 3475
3476 u8 syndrome[0x20];
3477
b4ff3a36 3478 u8 reserved_at_40[0x40];
e281682b
SM		 3479
3480 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3481
b4ff3a36 3482 u8 reserved_at_280[0x600];
e281682b
SM		 3483
3484 u8 pas[0][0x40];
3485};
3486
3487struct mlx5_ifc_query_xrc_srq_in_bits {
3488 u8 opcode[0x10];
b4ff3a36 3489 u8 reserved_at_10[0x10];
e281682b 3490
b4ff3a36 3491 u8 reserved_at_20[0x10];
e281682b
SM		 3492 u8 op_mod[0x10];
3493
b4ff3a36 3494 u8 reserved_at_40[0x8];
e281682b
SM		 3495 u8 xrc_srqn[0x18];
3496
b4ff3a36 3497 u8 reserved_at_60[0x20];
e281682b
SM		 3498};
3499
3500enum {
3501 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
3502 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
3503};
3504
3505struct mlx5_ifc_query_vport_state_out_bits {
3506 u8 status[0x8];
b4ff3a36 3507 u8 reserved_at_8[0x18];
e281682b
SM		 3508
3509 u8 syndrome[0x20];
3510
b4ff3a36 3511 u8 reserved_at_40[0x20];
e281682b 3512
b4ff3a36 3513 u8 reserved_at_60[0x18];
e281682b
SM		 3514 u8 admin_state[0x4];
3515 u8 state[0x4];
3516};
3517
3518enum {
3519 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0,
e7546514 3520 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1,
e281682b
SM		 3521};
3522
3523struct mlx5_ifc_query_vport_state_in_bits {
3524 u8 opcode[0x10];
b4ff3a36 3525 u8 reserved_at_10[0x10];
e281682b 3526
b4ff3a36 3527 u8 reserved_at_20[0x10];
e281682b
SM		 3528 u8 op_mod[0x10];
3529
3530 u8 other_vport[0x1];
b4ff3a36 3531 u8 reserved_at_41[0xf];
e281682b
SM		 3532 u8 vport_number[0x10];
3533
b4ff3a36 3534 u8 reserved_at_60[0x20];
e281682b
SM		 3535};
3536
3537struct mlx5_ifc_query_vport_counter_out_bits {
3538 u8 status[0x8];
b4ff3a36 3539 u8 reserved_at_8[0x18];
e281682b
SM		 3540
3541 u8 syndrome[0x20];
3542
b4ff3a36 3543 u8 reserved_at_40[0x40];
e281682b
SM		 3544
3545 struct mlx5_ifc_traffic_counter_bits received_errors;
3546
3547 struct mlx5_ifc_traffic_counter_bits transmit_errors;
3548
3549 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3550
3551 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3552
3553 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3554
3555 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3556
3557 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3558
3559 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3560
3561 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3562
3563 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3564
3565 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3566
3567 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3568
b4ff3a36 3569 u8 reserved_at_680[0xa00];
e281682b
SM		 3570};
3571
3572enum {
3573 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
3574};
3575
3576struct mlx5_ifc_query_vport_counter_in_bits {
3577 u8 opcode[0x10];
b4ff3a36 3578 u8 reserved_at_10[0x10];
e281682b 3579
b4ff3a36 3580 u8 reserved_at_20[0x10];
e281682b
SM		 3581 u8 op_mod[0x10];
3582
3583 u8 other_vport[0x1];
b54ba277
MY		 3584 u8 reserved_at_41[0xb];
3585 u8 port_num[0x4];
e281682b
SM		 3586 u8 vport_number[0x10];
3587
b4ff3a36 3588 u8 reserved_at_60[0x60];
e281682b
SM		 3589
3590 u8 clear[0x1];
b4ff3a36 3591 u8 reserved_at_c1[0x1f];
e281682b 3592
b4ff3a36 3593 u8 reserved_at_e0[0x20];
e281682b
SM		 3594};
3595
3596struct mlx5_ifc_query_tis_out_bits {
3597 u8 status[0x8];
b4ff3a36 3598 u8 reserved_at_8[0x18];
e281682b
SM		 3599
3600 u8 syndrome[0x20];
3601
b4ff3a36 3602 u8 reserved_at_40[0x40];
e281682b
SM		 3603
3604 struct mlx5_ifc_tisc_bits tis_context;
3605};
3606
3607struct mlx5_ifc_query_tis_in_bits {
3608 u8 opcode[0x10];
b4ff3a36 3609 u8 reserved_at_10[0x10];
e281682b 3610
b4ff3a36 3611 u8 reserved_at_20[0x10];
e281682b
SM		 3612 u8 op_mod[0x10];
3613
b4ff3a36 3614 u8 reserved_at_40[0x8];
e281682b
SM		 3615 u8 tisn[0x18];
3616
b4ff3a36 3617 u8 reserved_at_60[0x20];
e281682b
SM		 3618};
3619
3620struct mlx5_ifc_query_tir_out_bits {
3621 u8 status[0x8];
b4ff3a36 3622 u8 reserved_at_8[0x18];
e281682b
SM		 3623
3624 u8 syndrome[0x20];
3625
b4ff3a36 3626 u8 reserved_at_40[0xc0];
e281682b
SM		 3627
3628 struct mlx5_ifc_tirc_bits tir_context;
3629};
3630
3631struct mlx5_ifc_query_tir_in_bits {
3632 u8 opcode[0x10];
b4ff3a36 3633 u8 reserved_at_10[0x10];
e281682b 3634
b4ff3a36 3635 u8 reserved_at_20[0x10];
e281682b
SM		 3636 u8 op_mod[0x10];
3637
b4ff3a36 3638 u8 reserved_at_40[0x8];
e281682b
SM		 3639 u8 tirn[0x18];
3640
b4ff3a36 3641 u8 reserved_at_60[0x20];
e281682b
SM		 3642};
3643
3644struct mlx5_ifc_query_srq_out_bits {
3645 u8 status[0x8];
b4ff3a36 3646 u8 reserved_at_8[0x18];
e281682b
SM		 3647
3648 u8 syndrome[0x20];
3649
b4ff3a36 3650 u8 reserved_at_40[0x40];
e281682b
SM		 3651
3652 struct mlx5_ifc_srqc_bits srq_context_entry;
3653
b4ff3a36 3654 u8 reserved_at_280[0x600];
e281682b
SM		 3655
3656 u8 pas[0][0x40];
3657};
3658
3659struct mlx5_ifc_query_srq_in_bits {
3660 u8 opcode[0x10];
b4ff3a36 3661 u8 reserved_at_10[0x10];
e281682b 3662
b4ff3a36 3663 u8 reserved_at_20[0x10];
e281682b
SM		 3664 u8 op_mod[0x10];
3665
b4ff3a36 3666 u8 reserved_at_40[0x8];
e281682b
SM		 3667 u8 srqn[0x18];
3668
b4ff3a36 3669 u8 reserved_at_60[0x20];
e281682b
SM		 3670};
3671
3672struct mlx5_ifc_query_sq_out_bits {
3673 u8 status[0x8];
b4ff3a36 3674 u8 reserved_at_8[0x18];
e281682b
SM		 3675
3676 u8 syndrome[0x20];
3677
b4ff3a36 3678 u8 reserved_at_40[0xc0];
e281682b
SM		 3679
3680 struct mlx5_ifc_sqc_bits sq_context;
3681};
3682
3683struct mlx5_ifc_query_sq_in_bits {
3684 u8 opcode[0x10];
b4ff3a36 3685 u8 reserved_at_10[0x10];
e281682b 3686
b4ff3a36 3687 u8 reserved_at_20[0x10];
e281682b
SM		 3688 u8 op_mod[0x10];
3689
b4ff3a36 3690 u8 reserved_at_40[0x8];
e281682b
SM		 3691 u8 sqn[0x18];
3692
b4ff3a36 3693 u8 reserved_at_60[0x20];
e281682b
SM		 3694};
3695
3696struct mlx5_ifc_query_special_contexts_out_bits {
3697 u8 status[0x8];
b4ff3a36 3698 u8 reserved_at_8[0x18];
e281682b
SM		 3699
3700 u8 syndrome[0x20];
3701
ec22eb53 3702 u8 dump_fill_mkey[0x20];
e281682b
SM		 3703
3704 u8 resd_lkey[0x20];
bcda1aca
AK		 3705
3706 u8 null_mkey[0x20];
3707
3708 u8 reserved_at_a0[0x60];
e281682b
SM		 3709};
3710
3711struct mlx5_ifc_query_special_contexts_in_bits {
3712 u8 opcode[0x10];
b4ff3a36 3713 u8 reserved_at_10[0x10];
e281682b 3714
b4ff3a36 3715 u8 reserved_at_20[0x10];
e281682b
SM		 3716 u8 op_mod[0x10];
3717
b4ff3a36 3718 u8 reserved_at_40[0x40];
e281682b
SM		 3719};
3720
813f8540
MHY		 3721struct mlx5_ifc_query_scheduling_element_out_bits {
3722 u8 opcode[0x10];
3723 u8 reserved_at_10[0x10];
3724
3725 u8 reserved_at_20[0x10];
3726 u8 op_mod[0x10];
3727
3728 u8 reserved_at_40[0xc0];
3729
3730 struct mlx5_ifc_scheduling_context_bits scheduling_context;
3731
3732 u8 reserved_at_300[0x100];
3733};
3734
3735enum {
3736 SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
3737};
3738
3739struct mlx5_ifc_query_scheduling_element_in_bits {
3740 u8 opcode[0x10];
3741 u8 reserved_at_10[0x10];
3742
3743 u8 reserved_at_20[0x10];
3744 u8 op_mod[0x10];
3745
3746 u8 scheduling_hierarchy[0x8];
3747 u8 reserved_at_48[0x18];
3748
3749 u8 scheduling_element_id[0x20];
3750
3751 u8 reserved_at_80[0x180];
3752};
3753
e281682b
SM		 3754struct mlx5_ifc_query_rqt_out_bits {
3755 u8 status[0x8];
b4ff3a36 3756 u8 reserved_at_8[0x18];
e281682b
SM		 3757
3758 u8 syndrome[0x20];
3759
b4ff3a36 3760 u8 reserved_at_40[0xc0];
e281682b
SM		 3761
3762 struct mlx5_ifc_rqtc_bits rqt_context;
3763};
3764
3765struct mlx5_ifc_query_rqt_in_bits {
3766 u8 opcode[0x10];
b4ff3a36 3767 u8 reserved_at_10[0x10];
e281682b 3768
b4ff3a36 3769 u8 reserved_at_20[0x10];
e281682b
SM		 3770 u8 op_mod[0x10];
3771
b4ff3a36 3772 u8 reserved_at_40[0x8];
e281682b
SM		 3773 u8 rqtn[0x18];
3774
b4ff3a36 3775 u8 reserved_at_60[0x20];
e281682b
SM		 3776};
3777
3778struct mlx5_ifc_query_rq_out_bits {
3779 u8 status[0x8];
b4ff3a36 3780 u8 reserved_at_8[0x18];
e281682b
SM		 3781
3782 u8 syndrome[0x20];
3783
b4ff3a36 3784 u8 reserved_at_40[0xc0];
e281682b
SM		 3785
3786 struct mlx5_ifc_rqc_bits rq_context;
3787};
3788
3789struct mlx5_ifc_query_rq_in_bits {
3790 u8 opcode[0x10];
b4ff3a36 3791 u8 reserved_at_10[0x10];
e281682b 3792
b4ff3a36 3793 u8 reserved_at_20[0x10];
e281682b
SM		 3794 u8 op_mod[0x10];
3795
b4ff3a36 3796 u8 reserved_at_40[0x8];
e281682b
SM		 3797 u8 rqn[0x18];
3798
b4ff3a36 3799 u8 reserved_at_60[0x20];
e281682b
SM		 3800};
3801
3802struct mlx5_ifc_query_roce_address_out_bits {
3803 u8 status[0x8];
b4ff3a36 3804 u8 reserved_at_8[0x18];
e281682b
SM		 3805
3806 u8 syndrome[0x20];
3807
b4ff3a36 3808 u8 reserved_at_40[0x40];
e281682b
SM		 3809
3810 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3811};
3812
3813struct mlx5_ifc_query_roce_address_in_bits {
3814 u8 opcode[0x10];
b4ff3a36 3815 u8 reserved_at_10[0x10];
e281682b 3816
b4ff3a36 3817 u8 reserved_at_20[0x10];
e281682b
SM		 3818 u8 op_mod[0x10];
3819
3820 u8 roce_address_index[0x10];
b4ff3a36 3821 u8 reserved_at_50[0x10];
e281682b 3822
b4ff3a36 3823 u8 reserved_at_60[0x20];
e281682b
SM		 3824};
3825
3826struct mlx5_ifc_query_rmp_out_bits {
3827 u8 status[0x8];
b4ff3a36 3828 u8 reserved_at_8[0x18];
e281682b
SM		 3829
3830 u8 syndrome[0x20];
3831
b4ff3a36 3832 u8 reserved_at_40[0xc0];
e281682b
SM		 3833
3834 struct mlx5_ifc_rmpc_bits rmp_context;
3835};
3836
3837struct mlx5_ifc_query_rmp_in_bits {
3838 u8 opcode[0x10];
b4ff3a36 3839 u8 reserved_at_10[0x10];
e281682b 3840
b4ff3a36 3841 u8 reserved_at_20[0x10];
e281682b
SM		 3842 u8 op_mod[0x10];
3843
b4ff3a36 3844 u8 reserved_at_40[0x8];
e281682b
SM		 3845 u8 rmpn[0x18];
3846
b4ff3a36 3847 u8 reserved_at_60[0x20];
e281682b
SM		 3848};
3849
3850struct mlx5_ifc_query_qp_out_bits {
3851 u8 status[0x8];
b4ff3a36 3852 u8 reserved_at_8[0x18];
e281682b
SM		 3853
3854 u8 syndrome[0x20];
3855
b4ff3a36 3856 u8 reserved_at_40[0x40];
e281682b
SM		 3857
3858 u8 opt_param_mask[0x20];
3859
b4ff3a36 3860 u8 reserved_at_a0[0x20];
e281682b
SM		 3861
3862 struct mlx5_ifc_qpc_bits qpc;
3863
b4ff3a36 3864 u8 reserved_at_800[0x80];
e281682b
SM		 3865
3866 u8 pas[0][0x40];
3867};
3868
3869struct mlx5_ifc_query_qp_in_bits {
3870 u8 opcode[0x10];
b4ff3a36 3871 u8 reserved_at_10[0x10];
e281682b 3872
b4ff3a36 3873 u8 reserved_at_20[0x10];
e281682b
SM		 3874 u8 op_mod[0x10];
3875
b4ff3a36 3876 u8 reserved_at_40[0x8];
e281682b
SM		 3877 u8 qpn[0x18];
3878
b4ff3a36 3879 u8 reserved_at_60[0x20];
e281682b
SM		 3880};
3881
3882struct mlx5_ifc_query_q_counter_out_bits {
3883 u8 status[0x8];
b4ff3a36 3884 u8 reserved_at_8[0x18];
e281682b
SM		 3885
3886 u8 syndrome[0x20];
3887
b4ff3a36 3888 u8 reserved_at_40[0x40];
e281682b
SM		 3889
3890 u8 rx_write_requests[0x20];
3891
b4ff3a36 3892 u8 reserved_at_a0[0x20];
e281682b
SM		 3893
3894 u8 rx_read_requests[0x20];
3895
b4ff3a36 3896 u8 reserved_at_e0[0x20];
e281682b
SM		 3897
3898 u8 rx_atomic_requests[0x20];
3899
b4ff3a36 3900 u8 reserved_at_120[0x20];
e281682b
SM		 3901
3902 u8 rx_dct_connect[0x20];
3903
b4ff3a36 3904 u8 reserved_at_160[0x20];
e281682b
SM		 3905
3906 u8 out_of_buffer[0x20];
3907
b4ff3a36 3908 u8 reserved_at_1a0[0x20];
e281682b
SM		 3909
3910 u8 out_of_sequence[0x20];
3911
7486216b
SM		 3912 u8 reserved_at_1e0[0x20];
3913
3914 u8 duplicate_request[0x20];
3915
3916 u8 reserved_at_220[0x20];
3917
3918 u8 rnr_nak_retry_err[0x20];
3919
3920 u8 reserved_at_260[0x20];
3921
3922 u8 packet_seq_err[0x20];
3923
3924 u8 reserved_at_2a0[0x20];
3925
3926 u8 implied_nak_seq_err[0x20];
3927
3928 u8 reserved_at_2e0[0x20];
3929
3930 u8 local_ack_timeout_err[0x20];
3931
3932 u8 reserved_at_320[0x4e0];
e281682b
SM		 3933};
3934
3935struct mlx5_ifc_query_q_counter_in_bits {
3936 u8 opcode[0x10];
b4ff3a36 3937 u8 reserved_at_10[0x10];
e281682b 3938
b4ff3a36 3939 u8 reserved_at_20[0x10];
e281682b
SM		 3940 u8 op_mod[0x10];
3941
b4ff3a36 3942 u8 reserved_at_40[0x80];
e281682b
SM		 3943
3944 u8 clear[0x1];
b4ff3a36 3945 u8 reserved_at_c1[0x1f];
e281682b 3946
b4ff3a36 3947 u8 reserved_at_e0[0x18];
e281682b
SM		 3948 u8 counter_set_id[0x8];
3949};
3950
3951struct mlx5_ifc_query_pages_out_bits {
3952 u8 status[0x8];
b4ff3a36 3953 u8 reserved_at_8[0x18];
e281682b
SM		 3954
3955 u8 syndrome[0x20];
3956
b4ff3a36 3957 u8 reserved_at_40[0x10];
e281682b
SM		 3958 u8 function_id[0x10];
3959
3960 u8 num_pages[0x20];
3961};
3962
3963enum {
3964 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
3965 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
3966 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
3967};
3968
3969struct mlx5_ifc_query_pages_in_bits {
3970 u8 opcode[0x10];
b4ff3a36 3971 u8 reserved_at_10[0x10];
e281682b 3972
b4ff3a36 3973 u8 reserved_at_20[0x10];
e281682b
SM		 3974 u8 op_mod[0x10];
3975
b4ff3a36 3976 u8 reserved_at_40[0x10];
e281682b
SM		 3977 u8 function_id[0x10];
3978
b4ff3a36 3979 u8 reserved_at_60[0x20];
e281682b
SM		 3980};
3981
3982struct mlx5_ifc_query_nic_vport_context_out_bits {
3983 u8 status[0x8];
b4ff3a36 3984 u8 reserved_at_8[0x18];
e281682b
SM		 3985
3986 u8 syndrome[0x20];
3987
b4ff3a36 3988 u8 reserved_at_40[0x40];
e281682b
SM		 3989
3990 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
3991};
3992
3993struct mlx5_ifc_query_nic_vport_context_in_bits {
3994 u8 opcode[0x10];
b4ff3a36 3995 u8 reserved_at_10[0x10];
e281682b 3996
b4ff3a36 3997 u8 reserved_at_20[0x10];
e281682b
SM		 3998 u8 op_mod[0x10];
3999
4000 u8 other_vport[0x1];
b4ff3a36 4001 u8 reserved_at_41[0xf];
e281682b
SM		 4002 u8 vport_number[0x10];
4003
b4ff3a36 4004 u8 reserved_at_60[0x5];
e281682b 4005 u8 allowed_list_type[0x3];
b4ff3a36 4006 u8 reserved_at_68[0x18];
e281682b
SM		 4007};
4008
4009struct mlx5_ifc_query_mkey_out_bits {
4010 u8 status[0x8];
b4ff3a36 4011 u8 reserved_at_8[0x18];
e281682b
SM		 4012
4013 u8 syndrome[0x20];
4014
b4ff3a36 4015 u8 reserved_at_40[0x40];
e281682b
SM		 4016
4017 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4018
b4ff3a36 4019 u8 reserved_at_280[0x600];
e281682b
SM		 4020
4021 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
4022
4023 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
4024};
4025
4026struct mlx5_ifc_query_mkey_in_bits {
4027 u8 opcode[0x10];
b4ff3a36 4028 u8 reserved_at_10[0x10];
e281682b 4029
b4ff3a36 4030 u8 reserved_at_20[0x10];
e281682b
SM		 4031 u8 op_mod[0x10];
4032
b4ff3a36 4033 u8 reserved_at_40[0x8];
e281682b
SM		 4034 u8 mkey_index[0x18];
4035
4036 u8 pg_access[0x1];
b4ff3a36 4037 u8 reserved_at_61[0x1f];
e281682b
SM		 4038};
4039
4040struct mlx5_ifc_query_mad_demux_out_bits {
4041 u8 status[0x8];
b4ff3a36 4042 u8 reserved_at_8[0x18];
e281682b
SM		 4043
4044 u8 syndrome[0x20];
4045
b4ff3a36 4046 u8 reserved_at_40[0x40];
e281682b
SM		 4047
4048 u8 mad_dumux_parameters_block[0x20];
4049};
4050
4051struct mlx5_ifc_query_mad_demux_in_bits {
4052 u8 opcode[0x10];
b4ff3a36 4053 u8 reserved_at_10[0x10];
e281682b 4054
b4ff3a36 4055 u8 reserved_at_20[0x10];
e281682b
SM		 4056 u8 op_mod[0x10];
4057
b4ff3a36 4058 u8 reserved_at_40[0x40];
e281682b
SM		 4059};
4060
4061struct mlx5_ifc_query_l2_table_entry_out_bits {
4062 u8 status[0x8];
b4ff3a36 4063 u8 reserved_at_8[0x18];
e281682b
SM		 4064
4065 u8 syndrome[0x20];
4066
b4ff3a36 4067 u8 reserved_at_40[0xa0];
e281682b 4068
b4ff3a36 4069 u8 reserved_at_e0[0x13];
e281682b
SM		 4070 u8 vlan_valid[0x1];
4071 u8 vlan[0xc];
4072
4073 struct mlx5_ifc_mac_address_layout_bits mac_address;
4074
b4ff3a36 4075 u8 reserved_at_140[0xc0];
e281682b
SM		 4076};
4077
4078struct mlx5_ifc_query_l2_table_entry_in_bits {
4079 u8 opcode[0x10];
b4ff3a36 4080 u8 reserved_at_10[0x10];
e281682b 4081
b4ff3a36 4082 u8 reserved_at_20[0x10];
e281682b
SM		 4083 u8 op_mod[0x10];
4084
b4ff3a36 4085 u8 reserved_at_40[0x60];
e281682b 4086
b4ff3a36 4087 u8 reserved_at_a0[0x8];
e281682b
SM		 4088 u8 table_index[0x18];
4089
b4ff3a36 4090 u8 reserved_at_c0[0x140];
e281682b
SM		 4091};
4092
4093struct mlx5_ifc_query_issi_out_bits {
4094 u8 status[0x8];
b4ff3a36 4095 u8 reserved_at_8[0x18];
e281682b
SM		 4096
4097 u8 syndrome[0x20];
4098
b4ff3a36 4099 u8 reserved_at_40[0x10];
e281682b
SM		 4100 u8 current_issi[0x10];
4101
b4ff3a36 4102 u8 reserved_at_60[0xa0];
e281682b 4103
b4ff3a36 4104 u8 reserved_at_100[76][0x8];
e281682b
SM		 4105 u8 supported_issi_dw0[0x20];
4106};
4107
4108struct mlx5_ifc_query_issi_in_bits {
4109 u8 opcode[0x10];
b4ff3a36 4110 u8 reserved_at_10[0x10];
e281682b 4111
b4ff3a36 4112 u8 reserved_at_20[0x10];
e281682b
SM		 4113 u8 op_mod[0x10];
4114
b4ff3a36 4115 u8 reserved_at_40[0x40];
e281682b
SM		 4116};
4117
0dbc6fe0
SM		 4118struct mlx5_ifc_set_driver_version_out_bits {
4119 u8 status[0x8];
4120 u8 reserved_0[0x18];
4121
4122 u8 syndrome[0x20];
4123 u8 reserved_1[0x40];
4124};
4125
4126struct mlx5_ifc_set_driver_version_in_bits {
4127 u8 opcode[0x10];
4128 u8 reserved_0[0x10];
4129
4130 u8 reserved_1[0x10];
4131 u8 op_mod[0x10];
4132
4133 u8 reserved_2[0x40];
4134 u8 driver_version[64][0x8];
4135};
4136
e281682b
SM		 4137struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4138 u8 status[0x8];
b4ff3a36 4139 u8 reserved_at_8[0x18];
e281682b
SM		 4140
4141 u8 syndrome[0x20];
4142
b4ff3a36 4143 u8 reserved_at_40[0x40];
e281682b
SM		 4144
4145 struct mlx5_ifc_pkey_bits pkey[0];
4146};
4147
4148struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4149 u8 opcode[0x10];
b4ff3a36 4150 u8 reserved_at_10[0x10];
e281682b 4151
b4ff3a36 4152 u8 reserved_at_20[0x10];
e281682b
SM		 4153 u8 op_mod[0x10];
4154
4155 u8 other_vport[0x1];
b4ff3a36 4156 u8 reserved_at_41[0xb];
707c4602 4157 u8 port_num[0x4];
e281682b
SM		 4158 u8 vport_number[0x10];
4159
b4ff3a36 4160 u8 reserved_at_60[0x10];
e281682b
SM		 4161 u8 pkey_index[0x10];
4162};
4163
eff901d3
EC		 4164enum {
4165 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
4166 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
4167 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4168};
4169
e281682b
SM		 4170struct mlx5_ifc_query_hca_vport_gid_out_bits {
4171 u8 status[0x8];
b4ff3a36 4172 u8 reserved_at_8[0x18];
e281682b
SM		 4173
4174 u8 syndrome[0x20];
4175
b4ff3a36 4176 u8 reserved_at_40[0x20];
e281682b
SM		 4177
4178 u8 gids_num[0x10];
b4ff3a36 4179 u8 reserved_at_70[0x10];
e281682b
SM		 4180
4181 struct mlx5_ifc_array128_auto_bits gid[0];
4182};
4183
4184struct mlx5_ifc_query_hca_vport_gid_in_bits {
4185 u8 opcode[0x10];
b4ff3a36 4186 u8 reserved_at_10[0x10];
e281682b 4187
b4ff3a36 4188 u8 reserved_at_20[0x10];
e281682b
SM		 4189 u8 op_mod[0x10];
4190
4191 u8 other_vport[0x1];
b4ff3a36 4192 u8 reserved_at_41[0xb];
707c4602 4193 u8 port_num[0x4];
e281682b
SM		 4194 u8 vport_number[0x10];
4195
b4ff3a36 4196 u8 reserved_at_60[0x10];
e281682b
SM		 4197 u8 gid_index[0x10];
4198};
4199
4200struct mlx5_ifc_query_hca_vport_context_out_bits {
4201 u8 status[0x8];
b4ff3a36 4202 u8 reserved_at_8[0x18];
e281682b
SM		 4203
4204 u8 syndrome[0x20];
4205
b4ff3a36 4206 u8 reserved_at_40[0x40];
e281682b
SM		 4207
4208 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4209};
4210
4211struct mlx5_ifc_query_hca_vport_context_in_bits {
4212 u8 opcode[0x10];
b4ff3a36 4213 u8 reserved_at_10[0x10];
e281682b 4214
b4ff3a36 4215 u8 reserved_at_20[0x10];
e281682b
SM		 4216 u8 op_mod[0x10];
4217
4218 u8 other_vport[0x1];
b4ff3a36 4219 u8 reserved_at_41[0xb];
707c4602 4220 u8 port_num[0x4];
e281682b
SM		 4221 u8 vport_number[0x10];
4222
b4ff3a36 4223 u8 reserved_at_60[0x20];
e281682b
SM		 4224};
4225
4226struct mlx5_ifc_query_hca_cap_out_bits {
4227 u8 status[0x8];
b4ff3a36 4228 u8 reserved_at_8[0x18];
e281682b
SM		 4229
4230 u8 syndrome[0x20];
4231
b4ff3a36 4232 u8 reserved_at_40[0x40];
e281682b
SM		 4233
4234 union mlx5_ifc_hca_cap_union_bits capability;
4235};
4236
4237struct mlx5_ifc_query_hca_cap_in_bits {
4238 u8 opcode[0x10];
b4ff3a36 4239 u8 reserved_at_10[0x10];
e281682b 4240
b4ff3a36 4241 u8 reserved_at_20[0x10];
e281682b
SM		 4242 u8 op_mod[0x10];
4243
b4ff3a36 4244 u8 reserved_at_40[0x40];
e281682b
SM		 4245};
4246
4247struct mlx5_ifc_query_flow_table_out_bits {
4248 u8 status[0x8];
b4ff3a36 4249 u8 reserved_at_8[0x18];
e281682b
SM		 4250
4251 u8 syndrome[0x20];
4252
b4ff3a36 4253 u8 reserved_at_40[0x80];
e281682b 4254
b4ff3a36 4255 u8 reserved_at_c0[0x8];
e281682b 4256 u8 level[0x8];
b4ff3a36 4257 u8 reserved_at_d0[0x8];
e281682b
SM		 4258 u8 log_size[0x8];
4259
b4ff3a36 4260 u8 reserved_at_e0[0x120];
e281682b
SM		 4261};
4262
4263struct mlx5_ifc_query_flow_table_in_bits {
4264 u8 opcode[0x10];
b4ff3a36 4265 u8 reserved_at_10[0x10];
e281682b 4266
b4ff3a36 4267 u8 reserved_at_20[0x10];
e281682b
SM		 4268 u8 op_mod[0x10];
4269
b4ff3a36 4270 u8 reserved_at_40[0x40];
e281682b
SM		 4271
4272 u8 table_type[0x8];
b4ff3a36 4273 u8 reserved_at_88[0x18];
e281682b 4274
b4ff3a36 4275 u8 reserved_at_a0[0x8];
e281682b
SM		 4276 u8 table_id[0x18];
4277
b4ff3a36 4278 u8 reserved_at_c0[0x140];
e281682b
SM		 4279};
4280
4281struct mlx5_ifc_query_fte_out_bits {
4282 u8 status[0x8];
b4ff3a36 4283 u8 reserved_at_8[0x18];
e281682b
SM		 4284
4285 u8 syndrome[0x20];
4286
b4ff3a36 4287 u8 reserved_at_40[0x1c0];
e281682b
SM		 4288
4289 struct mlx5_ifc_flow_context_bits flow_context;
4290};
4291
4292struct mlx5_ifc_query_fte_in_bits {
4293 u8 opcode[0x10];
b4ff3a36 4294 u8 reserved_at_10[0x10];
e281682b 4295
b4ff3a36 4296 u8 reserved_at_20[0x10];
e281682b
SM		 4297 u8 op_mod[0x10];
4298
b4ff3a36 4299 u8 reserved_at_40[0x40];
e281682b
SM		 4300
4301 u8 table_type[0x8];
b4ff3a36 4302 u8 reserved_at_88[0x18];
e281682b 4303
b4ff3a36 4304 u8 reserved_at_a0[0x8];
e281682b
SM		 4305 u8 table_id[0x18];
4306
b4ff3a36 4307 u8 reserved_at_c0[0x40];
e281682b
SM		 4308
4309 u8 flow_index[0x20];
4310
b4ff3a36 4311 u8 reserved_at_120[0xe0];
e281682b
SM		 4312};
4313
4314enum {
4315 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
4316 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
4317 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
4318};
4319
4320struct mlx5_ifc_query_flow_group_out_bits {
4321 u8 status[0x8];
b4ff3a36 4322 u8 reserved_at_8[0x18];
e281682b
SM		 4323
4324 u8 syndrome[0x20];
4325
b4ff3a36 4326 u8 reserved_at_40[0xa0];
e281682b
SM		 4327
4328 u8 start_flow_index[0x20];
4329
b4ff3a36 4330 u8 reserved_at_100[0x20];
e281682b
SM		 4331
4332 u8 end_flow_index[0x20];
4333
b4ff3a36 4334 u8 reserved_at_140[0xa0];
e281682b 4335
b4ff3a36 4336 u8 reserved_at_1e0[0x18];
e281682b
SM		 4337 u8 match_criteria_enable[0x8];
4338
4339 struct mlx5_ifc_fte_match_param_bits match_criteria;
4340
b4ff3a36 4341 u8 reserved_at_1200[0xe00];
e281682b
SM		 4342};
4343
4344struct mlx5_ifc_query_flow_group_in_bits {
4345 u8 opcode[0x10];
b4ff3a36 4346 u8 reserved_at_10[0x10];
e281682b 4347
b4ff3a36 4348 u8 reserved_at_20[0x10];
e281682b
SM		 4349 u8 op_mod[0x10];
4350
b4ff3a36 4351 u8 reserved_at_40[0x40];
e281682b
SM		 4352
4353 u8 table_type[0x8];
b4ff3a36 4354 u8 reserved_at_88[0x18];
e281682b 4355
b4ff3a36 4356 u8 reserved_at_a0[0x8];
e281682b
SM		 4357 u8 table_id[0x18];
4358
4359 u8 group_id[0x20];
4360
b4ff3a36 4361 u8 reserved_at_e0[0x120];
e281682b
SM		 4362};
4363
9dc0b289
AV		 4364struct mlx5_ifc_query_flow_counter_out_bits {
4365 u8 status[0x8];
4366 u8 reserved_at_8[0x18];
4367
4368 u8 syndrome[0x20];
4369
4370 u8 reserved_at_40[0x40];
4371
4372 struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4373};
4374
4375struct mlx5_ifc_query_flow_counter_in_bits {
4376 u8 opcode[0x10];
4377 u8 reserved_at_10[0x10];
4378
4379 u8 reserved_at_20[0x10];
4380 u8 op_mod[0x10];
4381
4382 u8 reserved_at_40[0x80];
4383
4384 u8 clear[0x1];
4385 u8 reserved_at_c1[0xf];
4386 u8 num_of_counters[0x10];
4387
4388 u8 reserved_at_e0[0x10];
4389 u8 flow_counter_id[0x10];
4390};
4391
d6666753
SM		 4392struct mlx5_ifc_query_esw_vport_context_out_bits {
4393 u8 status[0x8];
b4ff3a36 4394 u8 reserved_at_8[0x18];
d6666753
SM		 4395
4396 u8 syndrome[0x20];
4397
b4ff3a36 4398 u8 reserved_at_40[0x40];
d6666753
SM		 4399
4400 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4401};
4402
4403struct mlx5_ifc_query_esw_vport_context_in_bits {
4404 u8 opcode[0x10];
b4ff3a36 4405 u8 reserved_at_10[0x10];
d6666753 4406
b4ff3a36 4407 u8 reserved_at_20[0x10];
d6666753
SM		 4408 u8 op_mod[0x10];
4409
4410 u8 other_vport[0x1];
b4ff3a36 4411 u8 reserved_at_41[0xf];
d6666753
SM		 4412 u8 vport_number[0x10];
4413
b4ff3a36 4414 u8 reserved_at_60[0x20];
d6666753
SM		 4415};
4416
4417struct mlx5_ifc_modify_esw_vport_context_out_bits {
4418 u8 status[0x8];
b4ff3a36 4419 u8 reserved_at_8[0x18];
d6666753
SM		 4420
4421 u8 syndrome[0x20];
4422
b4ff3a36 4423 u8 reserved_at_40[0x40];
d6666753
SM		 4424};
4425
4426struct mlx5_ifc_esw_vport_context_fields_select_bits {
b4ff3a36 4427 u8 reserved_at_0[0x1c];
d6666753
SM		 4428 u8 vport_cvlan_insert[0x1];
4429 u8 vport_svlan_insert[0x1];
4430 u8 vport_cvlan_strip[0x1];
4431 u8 vport_svlan_strip[0x1];
4432};
4433
4434struct mlx5_ifc_modify_esw_vport_context_in_bits {
4435 u8 opcode[0x10];
b4ff3a36 4436 u8 reserved_at_10[0x10];
d6666753 4437
b4ff3a36 4438 u8 reserved_at_20[0x10];
d6666753
SM		 4439 u8 op_mod[0x10];
4440
4441 u8 other_vport[0x1];
b4ff3a36 4442 u8 reserved_at_41[0xf];
d6666753
SM		 4443 u8 vport_number[0x10];
4444
4445 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4446
4447 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4448};
4449
e281682b
SM		 4450struct mlx5_ifc_query_eq_out_bits {
4451 u8 status[0x8];
b4ff3a36 4452 u8 reserved_at_8[0x18];
e281682b
SM		 4453
4454 u8 syndrome[0x20];
4455
b4ff3a36 4456 u8 reserved_at_40[0x40];
e281682b
SM		 4457
4458 struct mlx5_ifc_eqc_bits eq_context_entry;
4459
b4ff3a36 4460 u8 reserved_at_280[0x40];
e281682b
SM		 4461
4462 u8 event_bitmask[0x40];
4463
b4ff3a36 4464 u8 reserved_at_300[0x580];
e281682b
SM		 4465
4466 u8 pas[0][0x40];
4467};
4468
4469struct mlx5_ifc_query_eq_in_bits {
4470 u8 opcode[0x10];
b4ff3a36 4471 u8 reserved_at_10[0x10];
e281682b 4472
b4ff3a36 4473 u8 reserved_at_20[0x10];
e281682b
SM		 4474 u8 op_mod[0x10];
4475
b4ff3a36 4476 u8 reserved_at_40[0x18];
e281682b
SM		 4477 u8 eq_number[0x8];
4478
b4ff3a36 4479 u8 reserved_at_60[0x20];
e281682b
SM		 4480};
4481
7adbde20
HHZ		 4482struct mlx5_ifc_encap_header_in_bits {
4483 u8 reserved_at_0[0x5];
4484 u8 header_type[0x3];
4485 u8 reserved_at_8[0xe];
4486 u8 encap_header_size[0xa];
4487
4488 u8 reserved_at_20[0x10];
4489 u8 encap_header[2][0x8];
4490
4491 u8 more_encap_header[0][0x8];
4492};
4493
4494struct mlx5_ifc_query_encap_header_out_bits {
4495 u8 status[0x8];
4496 u8 reserved_at_8[0x18];
4497
4498 u8 syndrome[0x20];
4499
4500 u8 reserved_at_40[0xa0];
4501
4502 struct mlx5_ifc_encap_header_in_bits encap_header[0];
4503};
4504
4505struct mlx5_ifc_query_encap_header_in_bits {
4506 u8 opcode[0x10];
4507 u8 reserved_at_10[0x10];
4508
4509 u8 reserved_at_20[0x10];
4510 u8 op_mod[0x10];
4511
4512 u8 encap_id[0x20];
4513
4514 u8 reserved_at_60[0xa0];
4515};
4516
4517struct mlx5_ifc_alloc_encap_header_out_bits {
4518 u8 status[0x8];
4519 u8 reserved_at_8[0x18];
4520
4521 u8 syndrome[0x20];
4522
4523 u8 encap_id[0x20];
4524
4525 u8 reserved_at_60[0x20];
4526};
4527
4528struct mlx5_ifc_alloc_encap_header_in_bits {
4529 u8 opcode[0x10];
4530 u8 reserved_at_10[0x10];
4531
4532 u8 reserved_at_20[0x10];
4533 u8 op_mod[0x10];
4534
4535 u8 reserved_at_40[0xa0];
4536
4537 struct mlx5_ifc_encap_header_in_bits encap_header;
4538};
4539
4540struct mlx5_ifc_dealloc_encap_header_out_bits {
4541 u8 status[0x8];
4542 u8 reserved_at_8[0x18];
4543
4544 u8 syndrome[0x20];
4545
4546 u8 reserved_at_40[0x40];
4547};
4548
4549struct mlx5_ifc_dealloc_encap_header_in_bits {
4550 u8 opcode[0x10];
4551 u8 reserved_at_10[0x10];
4552
4553 u8 reserved_20[0x10];
4554 u8 op_mod[0x10];
4555
4556 u8 encap_id[0x20];
4557
4558 u8 reserved_60[0x20];
4559};
4560
2a69cb9f
OG		 4561struct mlx5_ifc_set_action_in_bits {
4562 u8 action_type[0x4];
4563 u8 field[0xc];
4564 u8 reserved_at_10[0x3];
4565 u8 offset[0x5];
4566 u8 reserved_at_18[0x3];
4567 u8 length[0x5];
4568
4569 u8 data[0x20];
4570};
4571
4572struct mlx5_ifc_add_action_in_bits {
4573 u8 action_type[0x4];
4574 u8 field[0xc];
4575 u8 reserved_at_10[0x10];
4576
4577 u8 data[0x20];
4578};
4579
4580union mlx5_ifc_set_action_in_add_action_in_auto_bits {
4581 struct mlx5_ifc_set_action_in_bits set_action_in;
4582 struct mlx5_ifc_add_action_in_bits add_action_in;
4583 u8 reserved_at_0[0x40];
4584};
4585
4586enum {
4587 MLX5_ACTION_TYPE_SET = 0x1,
4588 MLX5_ACTION_TYPE_ADD = 0x2,
4589};
4590
4591enum {
4592 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1,
4593 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2,
4594 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3,
4595 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4,
4596 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5,
4597 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6,
4598 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7,
4599 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8,
4600 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9,
4601 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa,
4602 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb,
4603 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc,
4604 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd,
4605 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe,
4606 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf,
4607 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10,
4608 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11,
4609 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12,
4610 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13,
4611 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14,
4612 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15,
4613 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16,
4614};
4615
4616struct mlx5_ifc_alloc_modify_header_context_out_bits {
4617 u8 status[0x8];
4618 u8 reserved_at_8[0x18];
4619
4620 u8 syndrome[0x20];
4621
4622 u8 modify_header_id[0x20];
4623
4624 u8 reserved_at_60[0x20];
4625};
4626
4627struct mlx5_ifc_alloc_modify_header_context_in_bits {
4628 u8 opcode[0x10];
4629 u8 reserved_at_10[0x10];
4630
4631 u8 reserved_at_20[0x10];
4632 u8 op_mod[0x10];
4633
4634 u8 reserved_at_40[0x20];
4635
4636 u8 table_type[0x8];
4637 u8 reserved_at_68[0x10];
4638 u8 num_of_actions[0x8];
4639
4640 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
4641};
4642
4643struct mlx5_ifc_dealloc_modify_header_context_out_bits {
4644 u8 status[0x8];
4645 u8 reserved_at_8[0x18];
4646
4647 u8 syndrome[0x20];
4648
4649 u8 reserved_at_40[0x40];
4650};
4651
4652struct mlx5_ifc_dealloc_modify_header_context_in_bits {
4653 u8 opcode[0x10];
4654 u8 reserved_at_10[0x10];
4655
4656 u8 reserved_at_20[0x10];
4657 u8 op_mod[0x10];
4658
4659 u8 modify_header_id[0x20];
4660
4661 u8 reserved_at_60[0x20];
4662};
4663
e281682b
SM		 4664struct mlx5_ifc_query_dct_out_bits {
4665 u8 status[0x8];
b4ff3a36 4666 u8 reserved_at_8[0x18];
e281682b
SM		 4667
4668 u8 syndrome[0x20];
4669
b4ff3a36 4670 u8 reserved_at_40[0x40];
e281682b
SM		 4671
4672 struct mlx5_ifc_dctc_bits dct_context_entry;
4673
b4ff3a36 4674 u8 reserved_at_280[0x180];
e281682b
SM		 4675};
4676
4677struct mlx5_ifc_query_dct_in_bits {
4678 u8 opcode[0x10];
b4ff3a36 4679 u8 reserved_at_10[0x10];
e281682b 4680
b4ff3a36 4681 u8 reserved_at_20[0x10];
e281682b
SM		 4682 u8 op_mod[0x10];
4683
b4ff3a36 4684 u8 reserved_at_40[0x8];
e281682b
SM		 4685 u8 dctn[0x18];
4686
b4ff3a36 4687 u8 reserved_at_60[0x20];
e281682b
SM		 4688};
4689
4690struct mlx5_ifc_query_cq_out_bits {
4691 u8 status[0x8];
b4ff3a36 4692 u8 reserved_at_8[0x18];
e281682b
SM		 4693
4694 u8 syndrome[0x20];
4695
b4ff3a36 4696 u8 reserved_at_40[0x40];
e281682b
SM		 4697
4698 struct mlx5_ifc_cqc_bits cq_context;
4699
b4ff3a36 4700 u8 reserved_at_280[0x600];
e281682b
SM		 4701
4702 u8 pas[0][0x40];
4703};
4704
4705struct mlx5_ifc_query_cq_in_bits {
4706 u8 opcode[0x10];
b4ff3a36 4707 u8 reserved_at_10[0x10];
e281682b 4708
b4ff3a36 4709 u8 reserved_at_20[0x10];
e281682b
SM		 4710 u8 op_mod[0x10];
4711
b4ff3a36 4712 u8 reserved_at_40[0x8];
e281682b
SM		 4713 u8 cqn[0x18];
4714
b4ff3a36 4715 u8 reserved_at_60[0x20];
e281682b
SM		 4716};
4717
4718struct mlx5_ifc_query_cong_status_out_bits {
4719 u8 status[0x8];
b4ff3a36 4720 u8 reserved_at_8[0x18];
e281682b
SM		 4721
4722 u8 syndrome[0x20];
4723
b4ff3a36 4724 u8 reserved_at_40[0x20];
e281682b
SM		 4725
4726 u8 enable[0x1];
4727 u8 tag_enable[0x1];
b4ff3a36 4728 u8 reserved_at_62[0x1e];
e281682b
SM		 4729};
4730
4731struct mlx5_ifc_query_cong_status_in_bits {
4732 u8 opcode[0x10];
b4ff3a36 4733 u8 reserved_at_10[0x10];
e281682b 4734
b4ff3a36 4735 u8 reserved_at_20[0x10];
e281682b
SM		 4736 u8 op_mod[0x10];
4737
b4ff3a36 4738 u8 reserved_at_40[0x18];
e281682b
SM		 4739 u8 priority[0x4];
4740 u8 cong_protocol[0x4];
4741
b4ff3a36 4742 u8 reserved_at_60[0x20];
e281682b
SM		 4743};
4744
4745struct mlx5_ifc_query_cong_statistics_out_bits {
4746 u8 status[0x8];
b4ff3a36 4747 u8 reserved_at_8[0x18];
e281682b
SM		 4748
4749 u8 syndrome[0x20];
4750
b4ff3a36 4751 u8 reserved_at_40[0x40];
e281682b 4752
e1f24a79 4753 u8 rp_cur_flows[0x20];
e281682b
SM		 4754
4755 u8 sum_flows[0x20];
4756
e1f24a79 4757 u8 rp_cnp_ignored_high[0x20];
e281682b 4758
e1f24a79 4759 u8 rp_cnp_ignored_low[0x20];
e281682b 4760
e1f24a79 4761 u8 rp_cnp_handled_high[0x20];
e281682b 4762
e1f24a79 4763 u8 rp_cnp_handled_low[0x20];
e281682b 4764
b4ff3a36 4765 u8 reserved_at_140[0x100];
e281682b
SM		 4766
4767 u8 time_stamp_high[0x20];
4768
4769 u8 time_stamp_low[0x20];
4770
4771 u8 accumulators_period[0x20];
4772
e1f24a79 4773 u8 np_ecn_marked_roce_packets_high[0x20];
e281682b 4774
e1f24a79 4775 u8 np_ecn_marked_roce_packets_low[0x20];
e281682b 4776
e1f24a79 4777 u8 np_cnp_sent_high[0x20];
e281682b 4778
e1f24a79 4779 u8 np_cnp_sent_low[0x20];
e281682b 4780
b4ff3a36 4781 u8 reserved_at_320[0x560];
e281682b
SM		 4782};
4783
4784struct mlx5_ifc_query_cong_statistics_in_bits {
4785 u8 opcode[0x10];
b4ff3a36 4786 u8 reserved_at_10[0x10];
e281682b 4787
b4ff3a36 4788 u8 reserved_at_20[0x10];
e281682b
SM		 4789 u8 op_mod[0x10];
4790
4791 u8 clear[0x1];
b4ff3a36 4792 u8 reserved_at_41[0x1f];
e281682b 4793
b4ff3a36 4794 u8 reserved_at_60[0x20];
e281682b
SM		 4795};
4796
4797struct mlx5_ifc_query_cong_params_out_bits {
4798 u8 status[0x8];
b4ff3a36 4799 u8 reserved_at_8[0x18];
e281682b
SM		 4800
4801 u8 syndrome[0x20];
4802
b4ff3a36 4803 u8 reserved_at_40[0x40];
e281682b
SM		 4804
4805 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4806};
4807
4808struct mlx5_ifc_query_cong_params_in_bits {
4809 u8 opcode[0x10];
b4ff3a36 4810 u8 reserved_at_10[0x10];
e281682b 4811
b4ff3a36 4812 u8 reserved_at_20[0x10];
e281682b
SM		 4813 u8 op_mod[0x10];
4814
b4ff3a36 4815 u8 reserved_at_40[0x1c];
e281682b
SM		 4816 u8 cong_protocol[0x4];
4817
b4ff3a36 4818 u8 reserved_at_60[0x20];
e281682b
SM		 4819};
4820
4821struct mlx5_ifc_query_adapter_out_bits {
4822 u8 status[0x8];
b4ff3a36 4823 u8 reserved_at_8[0x18];
e281682b
SM		 4824
4825 u8 syndrome[0x20];
4826
b4ff3a36 4827 u8 reserved_at_40[0x40];
e281682b
SM		 4828
4829 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4830};
4831
4832struct mlx5_ifc_query_adapter_in_bits {
4833 u8 opcode[0x10];
b4ff3a36 4834 u8 reserved_at_10[0x10];
e281682b 4835
b4ff3a36 4836 u8 reserved_at_20[0x10];
e281682b
SM		 4837 u8 op_mod[0x10];
4838
b4ff3a36 4839 u8 reserved_at_40[0x40];
e281682b
SM		 4840};
4841
4842struct mlx5_ifc_qp_2rst_out_bits {
4843 u8 status[0x8];
b4ff3a36 4844 u8 reserved_at_8[0x18];
e281682b
SM		 4845
4846 u8 syndrome[0x20];
4847
b4ff3a36 4848 u8 reserved_at_40[0x40];
e281682b
SM		 4849};
4850
4851struct mlx5_ifc_qp_2rst_in_bits {
4852 u8 opcode[0x10];
b4ff3a36 4853 u8 reserved_at_10[0x10];
e281682b 4854
b4ff3a36 4855 u8 reserved_at_20[0x10];
e281682b
SM		 4856 u8 op_mod[0x10];
4857
b4ff3a36 4858 u8 reserved_at_40[0x8];
e281682b
SM		 4859 u8 qpn[0x18];
4860
b4ff3a36 4861 u8 reserved_at_60[0x20];
e281682b
SM		 4862};
4863
4864struct mlx5_ifc_qp_2err_out_bits {
4865 u8 status[0x8];
b4ff3a36 4866 u8 reserved_at_8[0x18];
e281682b
SM		 4867
4868 u8 syndrome[0x20];
4869
b4ff3a36 4870 u8 reserved_at_40[0x40];
e281682b
SM		 4871};
4872
4873struct mlx5_ifc_qp_2err_in_bits {
4874 u8 opcode[0x10];
b4ff3a36 4875 u8 reserved_at_10[0x10];
e281682b 4876
b4ff3a36 4877 u8 reserved_at_20[0x10];
e281682b
SM		 4878 u8 op_mod[0x10];
4879
b4ff3a36 4880 u8 reserved_at_40[0x8];
e281682b
SM		 4881 u8 qpn[0x18];
4882
b4ff3a36 4883 u8 reserved_at_60[0x20];
e281682b
SM		 4884};
4885
4886struct mlx5_ifc_page_fault_resume_out_bits {
4887 u8 status[0x8];
b4ff3a36 4888 u8 reserved_at_8[0x18];
e281682b
SM		 4889
4890 u8 syndrome[0x20];
4891
b4ff3a36 4892 u8 reserved_at_40[0x40];
e281682b
SM		 4893};
4894
4895struct mlx5_ifc_page_fault_resume_in_bits {
4896 u8 opcode[0x10];
b4ff3a36 4897 u8 reserved_at_10[0x10];
e281682b 4898
b4ff3a36 4899 u8 reserved_at_20[0x10];
e281682b
SM		 4900 u8 op_mod[0x10];
4901
4902 u8 error[0x1];
b4ff3a36 4903 u8 reserved_at_41[0x4];
223cdc72
AK		 4904 u8 page_fault_type[0x3];
4905 u8 wq_number[0x18];
e281682b 4906
223cdc72
AK		 4907 u8 reserved_at_60[0x8];
4908 u8 token[0x18];
e281682b
SM		 4909};
4910
4911struct mlx5_ifc_nop_out_bits {
4912 u8 status[0x8];
b4ff3a36 4913 u8 reserved_at_8[0x18];
e281682b
SM		 4914
4915 u8 syndrome[0x20];
4916
b4ff3a36 4917 u8 reserved_at_40[0x40];
e281682b
SM		 4918};
4919
4920struct mlx5_ifc_nop_in_bits {
4921 u8 opcode[0x10];
b4ff3a36 4922 u8 reserved_at_10[0x10];
e281682b 4923
b4ff3a36 4924 u8 reserved_at_20[0x10];
e281682b
SM		 4925 u8 op_mod[0x10];
4926
b4ff3a36 4927 u8 reserved_at_40[0x40];
e281682b
SM		 4928};
4929
4930struct mlx5_ifc_modify_vport_state_out_bits {
4931 u8 status[0x8];
b4ff3a36 4932 u8 reserved_at_8[0x18];
e281682b
SM		 4933
4934 u8 syndrome[0x20];
4935
b4ff3a36 4936 u8 reserved_at_40[0x40];
e281682b
SM		 4937};
4938
4939struct mlx5_ifc_modify_vport_state_in_bits {
4940 u8 opcode[0x10];
b4ff3a36 4941 u8 reserved_at_10[0x10];
e281682b 4942
b4ff3a36 4943 u8 reserved_at_20[0x10];
e281682b
SM		 4944 u8 op_mod[0x10];
4945
4946 u8 other_vport[0x1];
b4ff3a36 4947 u8 reserved_at_41[0xf];
e281682b
SM		 4948 u8 vport_number[0x10];
4949
b4ff3a36 4950 u8 reserved_at_60[0x18];
e281682b 4951 u8 admin_state[0x4];
b4ff3a36 4952 u8 reserved_at_7c[0x4];
e281682b
SM		 4953};
4954
4955struct mlx5_ifc_modify_tis_out_bits {
4956 u8 status[0x8];
b4ff3a36 4957 u8 reserved_at_8[0x18];
e281682b
SM		 4958
4959 u8 syndrome[0x20];
4960
b4ff3a36 4961 u8 reserved_at_40[0x40];
e281682b
SM		 4962};
4963
75850d0b 4964struct mlx5_ifc_modify_tis_bitmask_bits {
b4ff3a36 4965 u8 reserved_at_0[0x20];
75850d0b 4966
84df61eb
AH		 4967 u8 reserved_at_20[0x1d];
4968 u8 lag_tx_port_affinity[0x1];
4969 u8 strict_lag_tx_port_affinity[0x1];
75850d0b 4970 u8 prio[0x1];
4971};
4972
e281682b
SM		 4973struct mlx5_ifc_modify_tis_in_bits {
4974 u8 opcode[0x10];
b4ff3a36 4975 u8 reserved_at_10[0x10];
e281682b 4976
b4ff3a36 4977 u8 reserved_at_20[0x10];
e281682b
SM		 4978 u8 op_mod[0x10];
4979
b4ff3a36 4980 u8 reserved_at_40[0x8];
e281682b
SM		 4981 u8 tisn[0x18];
4982
b4ff3a36 4983 u8 reserved_at_60[0x20];
e281682b 4984
75850d0b 4985 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
e281682b 4986
b4ff3a36 4987 u8 reserved_at_c0[0x40];
e281682b
SM		 4988
4989 struct mlx5_ifc_tisc_bits ctx;
4990};
4991
d9eea403 4992struct mlx5_ifc_modify_tir_bitmask_bits {
b4ff3a36 4993 u8 reserved_at_0[0x20];
d9eea403 4994
b4ff3a36 4995 u8 reserved_at_20[0x1b];
66189961 4996 u8 self_lb_en[0x1];
bdfc028d
TT		 4997 u8 reserved_at_3c[0x1];
4998 u8 hash[0x1];
4999 u8 reserved_at_3e[0x1];
d9eea403
AS		 5000 u8 lro[0x1];
5001};
5002
e281682b
SM		 5003struct mlx5_ifc_modify_tir_out_bits {
5004 u8 status[0x8];
b4ff3a36 5005 u8 reserved_at_8[0x18];
e281682b
SM		 5006
5007 u8 syndrome[0x20];
5008
b4ff3a36 5009 u8 reserved_at_40[0x40];
e281682b
SM		 5010};
5011
5012struct mlx5_ifc_modify_tir_in_bits {
5013 u8 opcode[0x10];
b4ff3a36 5014 u8 reserved_at_10[0x10];
e281682b 5015
b4ff3a36 5016 u8 reserved_at_20[0x10];
e281682b
SM		 5017 u8 op_mod[0x10];
5018
b4ff3a36 5019 u8 reserved_at_40[0x8];
e281682b
SM		 5020 u8 tirn[0x18];
5021
b4ff3a36 5022 u8 reserved_at_60[0x20];
e281682b 5023
d9eea403 5024 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
e281682b 5025
b4ff3a36 5026 u8 reserved_at_c0[0x40];
e281682b
SM		 5027
5028 struct mlx5_ifc_tirc_bits ctx;
5029};
5030
5031struct mlx5_ifc_modify_sq_out_bits {
5032 u8 status[0x8];
b4ff3a36 5033 u8 reserved_at_8[0x18];
e281682b
SM		 5034
5035 u8 syndrome[0x20];
5036
b4ff3a36 5037 u8 reserved_at_40[0x40];
e281682b
SM		 5038};
5039
5040struct mlx5_ifc_modify_sq_in_bits {
5041 u8 opcode[0x10];
b4ff3a36 5042 u8 reserved_at_10[0x10];
e281682b 5043
b4ff3a36 5044 u8 reserved_at_20[0x10];
e281682b
SM		 5045 u8 op_mod[0x10];
5046
5047 u8 sq_state[0x4];
b4ff3a36 5048 u8 reserved_at_44[0x4];
e281682b
SM		 5049 u8 sqn[0x18];
5050
b4ff3a36 5051 u8 reserved_at_60[0x20];
e281682b
SM		 5052
5053 u8 modify_bitmask[0x40];
5054
b4ff3a36 5055 u8 reserved_at_c0[0x40];
e281682b
SM		 5056
5057 struct mlx5_ifc_sqc_bits ctx;
5058};
5059
813f8540
MHY		 5060struct mlx5_ifc_modify_scheduling_element_out_bits {
5061 u8 status[0x8];
5062 u8 reserved_at_8[0x18];
5063
5064 u8 syndrome[0x20];
5065
5066 u8 reserved_at_40[0x1c0];
5067};
5068
5069enum {
5070 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
5071 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
5072};
5073
5074struct mlx5_ifc_modify_scheduling_element_in_bits {
5075 u8 opcode[0x10];
5076 u8 reserved_at_10[0x10];
5077
5078 u8 reserved_at_20[0x10];
5079 u8 op_mod[0x10];
5080
5081 u8 scheduling_hierarchy[0x8];
5082 u8 reserved_at_48[0x18];
5083
5084 u8 scheduling_element_id[0x20];
5085
5086 u8 reserved_at_80[0x20];
5087
5088 u8 modify_bitmask[0x20];
5089
5090 u8 reserved_at_c0[0x40];
5091
5092 struct mlx5_ifc_scheduling_context_bits scheduling_context;
5093
5094 u8 reserved_at_300[0x100];
5095};
5096
e281682b
SM		 5097struct mlx5_ifc_modify_rqt_out_bits {
5098 u8 status[0x8];
b4ff3a36 5099 u8 reserved_at_8[0x18];
e281682b
SM		 5100
5101 u8 syndrome[0x20];
5102
b4ff3a36 5103 u8 reserved_at_40[0x40];
e281682b
SM		 5104};
5105
5c50368f 5106struct mlx5_ifc_rqt_bitmask_bits {
b4ff3a36 5107 u8 reserved_at_0[0x20];
5c50368f 5108
b4ff3a36 5109 u8 reserved_at_20[0x1f];
5c50368f
AS		 5110 u8 rqn_list[0x1];
5111};
5112
e281682b
SM		 5113struct mlx5_ifc_modify_rqt_in_bits {
5114 u8 opcode[0x10];
b4ff3a36 5115 u8 reserved_at_10[0x10];
e281682b 5116
b4ff3a36 5117 u8 reserved_at_20[0x10];
e281682b
SM		 5118 u8 op_mod[0x10];
5119
b4ff3a36 5120 u8 reserved_at_40[0x8];
e281682b
SM		 5121 u8 rqtn[0x18];
5122
b4ff3a36 5123 u8 reserved_at_60[0x20];
e281682b 5124
5c50368f 5125 struct mlx5_ifc_rqt_bitmask_bits bitmask;
e281682b 5126
b4ff3a36 5127 u8 reserved_at_c0[0x40];
e281682b
SM		 5128
5129 struct mlx5_ifc_rqtc_bits ctx;
5130};
5131
5132struct mlx5_ifc_modify_rq_out_bits {
5133 u8 status[0x8];
b4ff3a36 5134 u8 reserved_at_8[0x18];
e281682b
SM		 5135
5136 u8 syndrome[0x20];
5137
b4ff3a36 5138 u8 reserved_at_40[0x40];
e281682b
SM		 5139};
5140
83b502a1
AV		 5141enum {
5142 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
102722fc 5143 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
23a6964e 5144 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
83b502a1
AV		 5145};
5146
e281682b
SM		 5147struct mlx5_ifc_modify_rq_in_bits {
5148 u8 opcode[0x10];
b4ff3a36 5149 u8 reserved_at_10[0x10];
e281682b 5150
b4ff3a36 5151 u8 reserved_at_20[0x10];
e281682b
SM		 5152 u8 op_mod[0x10];
5153
5154 u8 rq_state[0x4];
b4ff3a36 5155 u8 reserved_at_44[0x4];
e281682b
SM		 5156 u8 rqn[0x18];
5157
b4ff3a36 5158 u8 reserved_at_60[0x20];
e281682b
SM		 5159
5160 u8 modify_bitmask[0x40];
5161
b4ff3a36 5162 u8 reserved_at_c0[0x40];
e281682b
SM		 5163
5164 struct mlx5_ifc_rqc_bits ctx;
5165};
5166
5167struct mlx5_ifc_modify_rmp_out_bits {
5168 u8 status[0x8];
b4ff3a36 5169 u8 reserved_at_8[0x18];
e281682b
SM		 5170
5171 u8 syndrome[0x20];
5172
b4ff3a36 5173 u8 reserved_at_40[0x40];
e281682b
SM		 5174};
5175
01949d01 5176struct mlx5_ifc_rmp_bitmask_bits {
b4ff3a36 5177 u8 reserved_at_0[0x20];
01949d01 5178
b4ff3a36 5179 u8 reserved_at_20[0x1f];
01949d01
HA		 5180 u8 lwm[0x1];
5181};
5182
e281682b
SM		 5183struct mlx5_ifc_modify_rmp_in_bits {
5184 u8 opcode[0x10];
b4ff3a36 5185 u8 reserved_at_10[0x10];
e281682b 5186
b4ff3a36 5187 u8 reserved_at_20[0x10];
e281682b
SM		 5188 u8 op_mod[0x10];
5189
5190 u8 rmp_state[0x4];
b4ff3a36 5191 u8 reserved_at_44[0x4];
e281682b
SM		 5192 u8 rmpn[0x18];
5193
b4ff3a36 5194 u8 reserved_at_60[0x20];
e281682b 5195
01949d01 5196 struct mlx5_ifc_rmp_bitmask_bits bitmask;
e281682b 5197
b4ff3a36 5198 u8 reserved_at_c0[0x40];
e281682b
SM		 5199
5200 struct mlx5_ifc_rmpc_bits ctx;
5201};
5202
5203struct mlx5_ifc_modify_nic_vport_context_out_bits {
5204 u8 status[0x8];
b4ff3a36 5205 u8 reserved_at_8[0x18];
e281682b
SM		 5206
5207 u8 syndrome[0x20];
5208
b4ff3a36 5209 u8 reserved_at_40[0x40];
e281682b
SM		 5210};
5211
5212struct mlx5_ifc_modify_nic_vport_field_select_bits {
23898c76
NO		 5213 u8 reserved_at_0[0x16];
5214 u8 node_guid[0x1];
5215 u8 port_guid[0x1];
9def7121 5216 u8 min_inline[0x1];
d82b7318
SM		 5217 u8 mtu[0x1];
5218 u8 change_event[0x1];
5219 u8 promisc[0x1];
e281682b
SM		 5220 u8 permanent_address[0x1];
5221 u8 addresses_list[0x1];
5222 u8 roce_en[0x1];
b4ff3a36 5223 u8 reserved_at_1f[0x1];
e281682b
SM		 5224};
5225
5226struct mlx5_ifc_modify_nic_vport_context_in_bits {
5227 u8 opcode[0x10];
b4ff3a36 5228 u8 reserved_at_10[0x10];
e281682b 5229
b4ff3a36 5230 u8 reserved_at_20[0x10];
e281682b
SM		 5231 u8 op_mod[0x10];
5232
5233 u8 other_vport[0x1];
b4ff3a36 5234 u8 reserved_at_41[0xf];
e281682b
SM		 5235 u8 vport_number[0x10];
5236
5237 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5238
b4ff3a36 5239 u8 reserved_at_80[0x780];
e281682b
SM		 5240
5241 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5242};
5243
5244struct mlx5_ifc_modify_hca_vport_context_out_bits {
5245 u8 status[0x8];
b4ff3a36 5246 u8 reserved_at_8[0x18];
e281682b
SM		 5247
5248 u8 syndrome[0x20];
5249
b4ff3a36 5250 u8 reserved_at_40[0x40];
e281682b
SM		 5251};
5252
5253struct mlx5_ifc_modify_hca_vport_context_in_bits {
5254 u8 opcode[0x10];
b4ff3a36 5255 u8 reserved_at_10[0x10];
e281682b 5256
b4ff3a36 5257 u8 reserved_at_20[0x10];
e281682b
SM		 5258 u8 op_mod[0x10];
5259
5260 u8 other_vport[0x1];
b4ff3a36 5261 u8 reserved_at_41[0xb];
707c4602 5262 u8 port_num[0x4];
e281682b
SM		 5263 u8 vport_number[0x10];
5264
b4ff3a36 5265 u8 reserved_at_60[0x20];
e281682b
SM		 5266
5267 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5268};
5269
5270struct mlx5_ifc_modify_cq_out_bits {
5271 u8 status[0x8];
b4ff3a36 5272 u8 reserved_at_8[0x18];
e281682b
SM		 5273
5274 u8 syndrome[0x20];
5275
b4ff3a36 5276 u8 reserved_at_40[0x40];
e281682b
SM		 5277};
5278
5279enum {
5280 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
5281 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
5282};
5283
5284struct mlx5_ifc_modify_cq_in_bits {
5285 u8 opcode[0x10];
b4ff3a36 5286 u8 reserved_at_10[0x10];
e281682b 5287
b4ff3a36 5288 u8 reserved_at_20[0x10];
e281682b
SM		 5289 u8 op_mod[0x10];
5290
b4ff3a36 5291 u8 reserved_at_40[0x8];
e281682b
SM		 5292 u8 cqn[0x18];
5293
5294 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5295
5296 struct mlx5_ifc_cqc_bits cq_context;
5297
b4ff3a36 5298 u8 reserved_at_280[0x600];
e281682b
SM		 5299
5300 u8 pas[0][0x40];
5301};
5302
5303struct mlx5_ifc_modify_cong_status_out_bits {
5304 u8 status[0x8];
b4ff3a36 5305 u8 reserved_at_8[0x18];
e281682b
SM		 5306
5307 u8 syndrome[0x20];
5308
b4ff3a36 5309 u8 reserved_at_40[0x40];
e281682b
SM		 5310};
5311
5312struct mlx5_ifc_modify_cong_status_in_bits {
5313 u8 opcode[0x10];
b4ff3a36 5314 u8 reserved_at_10[0x10];
e281682b 5315
b4ff3a36 5316 u8 reserved_at_20[0x10];
e281682b
SM		 5317 u8 op_mod[0x10];
5318
b4ff3a36 5319 u8 reserved_at_40[0x18];
e281682b
SM		 5320 u8 priority[0x4];
5321 u8 cong_protocol[0x4];
5322
5323 u8 enable[0x1];
5324 u8 tag_enable[0x1];
b4ff3a36 5325 u8 reserved_at_62[0x1e];
e281682b
SM		 5326};
5327
5328struct mlx5_ifc_modify_cong_params_out_bits {
5329 u8 status[0x8];
b4ff3a36 5330 u8 reserved_at_8[0x18];
e281682b
SM		 5331
5332 u8 syndrome[0x20];
5333
b4ff3a36 5334 u8 reserved_at_40[0x40];
e281682b
SM		 5335};
5336
5337struct mlx5_ifc_modify_cong_params_in_bits {
5338 u8 opcode[0x10];
b4ff3a36 5339 u8 reserved_at_10[0x10];
e281682b 5340
b4ff3a36 5341 u8 reserved_at_20[0x10];
e281682b
SM		 5342 u8 op_mod[0x10];
5343
b4ff3a36 5344 u8 reserved_at_40[0x1c];
e281682b
SM		 5345 u8 cong_protocol[0x4];
5346
5347 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5348
b4ff3a36 5349 u8 reserved_at_80[0x80];
e281682b
SM		 5350
5351 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5352};
5353
5354struct mlx5_ifc_manage_pages_out_bits {
5355 u8 status[0x8];
b4ff3a36 5356 u8 reserved_at_8[0x18];
e281682b
SM		 5357
5358 u8 syndrome[0x20];
5359
5360 u8 output_num_entries[0x20];
5361
b4ff3a36 5362 u8 reserved_at_60[0x20];
e281682b
SM		 5363
5364 u8 pas[0][0x40];
5365};
5366
5367enum {
5368 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
5369 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
5370 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
5371};
5372
5373struct mlx5_ifc_manage_pages_in_bits {
5374 u8 opcode[0x10];
b4ff3a36 5375 u8 reserved_at_10[0x10];
e281682b 5376
b4ff3a36 5377 u8 reserved_at_20[0x10];
e281682b
SM		 5378 u8 op_mod[0x10];
5379
b4ff3a36 5380 u8 reserved_at_40[0x10];
e281682b
SM		 5381 u8 function_id[0x10];
5382
5383 u8 input_num_entries[0x20];
5384
5385 u8 pas[0][0x40];
5386};
5387
5388struct mlx5_ifc_mad_ifc_out_bits {
5389 u8 status[0x8];
b4ff3a36 5390 u8 reserved_at_8[0x18];
e281682b
SM		 5391
5392 u8 syndrome[0x20];
5393
b4ff3a36 5394 u8 reserved_at_40[0x40];
e281682b
SM		 5395
5396 u8 response_mad_packet[256][0x8];
5397};
5398
5399struct mlx5_ifc_mad_ifc_in_bits {
5400 u8 opcode[0x10];
b4ff3a36 5401 u8 reserved_at_10[0x10];
e281682b 5402
b4ff3a36 5403 u8 reserved_at_20[0x10];
e281682b
SM		 5404 u8 op_mod[0x10];
5405
5406 u8 remote_lid[0x10];
b4ff3a36 5407 u8 reserved_at_50[0x8];
e281682b
SM		 5408 u8 port[0x8];
5409
b4ff3a36 5410 u8 reserved_at_60[0x20];
e281682b
SM		 5411
5412 u8 mad[256][0x8];
5413};
5414
5415struct mlx5_ifc_init_hca_out_bits {
5416 u8 status[0x8];
b4ff3a36 5417 u8 reserved_at_8[0x18];
e281682b
SM		 5418
5419 u8 syndrome[0x20];
5420
b4ff3a36 5421 u8 reserved_at_40[0x40];
e281682b
SM		 5422};
5423
5424struct mlx5_ifc_init_hca_in_bits {
5425 u8 opcode[0x10];
b4ff3a36 5426 u8 reserved_at_10[0x10];
e281682b 5427
b4ff3a36 5428 u8 reserved_at_20[0x10];
e281682b
SM		 5429 u8 op_mod[0x10];
5430
b4ff3a36 5431 u8 reserved_at_40[0x40];
e281682b
SM		 5432};
5433
5434struct mlx5_ifc_init2rtr_qp_out_bits {
5435 u8 status[0x8];
b4ff3a36 5436 u8 reserved_at_8[0x18];
e281682b
SM		 5437
5438 u8 syndrome[0x20];
5439
b4ff3a36 5440 u8 reserved_at_40[0x40];
e281682b
SM		 5441};
5442
5443struct mlx5_ifc_init2rtr_qp_in_bits {
5444 u8 opcode[0x10];
b4ff3a36 5445 u8 reserved_at_10[0x10];
e281682b 5446
b4ff3a36 5447 u8 reserved_at_20[0x10];
e281682b
SM		 5448 u8 op_mod[0x10];
5449
b4ff3a36 5450 u8 reserved_at_40[0x8];
e281682b
SM		 5451 u8 qpn[0x18];
5452
b4ff3a36 5453 u8 reserved_at_60[0x20];
e281682b
SM		 5454
5455 u8 opt_param_mask[0x20];
5456
b4ff3a36 5457 u8 reserved_at_a0[0x20];
e281682b
SM		 5458
5459 struct mlx5_ifc_qpc_bits qpc;
5460
b4ff3a36 5461 u8 reserved_at_800[0x80];
e281682b
SM		 5462};
5463
5464struct mlx5_ifc_init2init_qp_out_bits {
5465 u8 status[0x8];
b4ff3a36 5466 u8 reserved_at_8[0x18];
e281682b
SM		 5467
5468 u8 syndrome[0x20];
5469
b4ff3a36 5470 u8 reserved_at_40[0x40];
e281682b
SM		 5471};
5472
5473struct mlx5_ifc_init2init_qp_in_bits {
5474 u8 opcode[0x10];
b4ff3a36 5475 u8 reserved_at_10[0x10];
e281682b 5476
b4ff3a36 5477 u8 reserved_at_20[0x10];
e281682b
SM		 5478 u8 op_mod[0x10];
5479
b4ff3a36 5480 u8 reserved_at_40[0x8];
e281682b
SM		 5481 u8 qpn[0x18];
5482
b4ff3a36 5483 u8 reserved_at_60[0x20];
e281682b
SM		 5484
5485 u8 opt_param_mask[0x20];
5486
b4ff3a36 5487 u8 reserved_at_a0[0x20];
e281682b
SM		 5488
5489 struct mlx5_ifc_qpc_bits qpc;
5490
b4ff3a36 5491 u8 reserved_at_800[0x80];
e281682b
SM		 5492};
5493
5494struct mlx5_ifc_get_dropped_packet_log_out_bits {
5495 u8 status[0x8];
b4ff3a36 5496 u8 reserved_at_8[0x18];
e281682b
SM		 5497
5498 u8 syndrome[0x20];
5499
b4ff3a36 5500 u8 reserved_at_40[0x40];
e281682b
SM		 5501
5502 u8 packet_headers_log[128][0x8];
5503
5504 u8 packet_syndrome[64][0x8];
5505};
5506
5507struct mlx5_ifc_get_dropped_packet_log_in_bits {
5508 u8 opcode[0x10];
b4ff3a36 5509 u8 reserved_at_10[0x10];
e281682b 5510
b4ff3a36 5511 u8 reserved_at_20[0x10];
e281682b
SM		 5512 u8 op_mod[0x10];
5513
b4ff3a36 5514 u8 reserved_at_40[0x40];
e281682b
SM		 5515};
5516
5517struct mlx5_ifc_gen_eqe_in_bits {
5518 u8 opcode[0x10];
b4ff3a36 5519 u8 reserved_at_10[0x10];
e281682b 5520
b4ff3a36 5521 u8 reserved_at_20[0x10];
e281682b
SM		 5522 u8 op_mod[0x10];
5523
b4ff3a36 5524 u8 reserved_at_40[0x18];
e281682b
SM		 5525 u8 eq_number[0x8];
5526
b4ff3a36 5527 u8 reserved_at_60[0x20];
e281682b
SM		 5528
5529 u8 eqe[64][0x8];
5530};
5531
5532struct mlx5_ifc_gen_eq_out_bits {
5533 u8 status[0x8];
b4ff3a36 5534 u8 reserved_at_8[0x18];
e281682b
SM		 5535
5536 u8 syndrome[0x20];
5537
b4ff3a36 5538 u8 reserved_at_40[0x40];
e281682b
SM		 5539};
5540
5541struct mlx5_ifc_enable_hca_out_bits {
5542 u8 status[0x8];
b4ff3a36 5543 u8 reserved_at_8[0x18];
e281682b
SM		 5544
5545 u8 syndrome[0x20];
5546
b4ff3a36 5547 u8 reserved_at_40[0x20];
e281682b
SM		 5548};
5549
5550struct mlx5_ifc_enable_hca_in_bits {
5551 u8 opcode[0x10];
b4ff3a36 5552 u8 reserved_at_10[0x10];
e281682b 5553
b4ff3a36 5554 u8 reserved_at_20[0x10];
e281682b
SM		 5555 u8 op_mod[0x10];
5556
b4ff3a36 5557 u8 reserved_at_40[0x10];
e281682b
SM		 5558 u8 function_id[0x10];
5559
b4ff3a36 5560 u8 reserved_at_60[0x20];
e281682b
SM		 5561};
5562
5563struct mlx5_ifc_drain_dct_out_bits {
5564 u8 status[0x8];
b4ff3a36 5565 u8 reserved_at_8[0x18];
e281682b
SM		 5566
5567 u8 syndrome[0x20];
5568
b4ff3a36 5569 u8 reserved_at_40[0x40];
e281682b
SM		 5570};
5571
5572struct mlx5_ifc_drain_dct_in_bits {
5573 u8 opcode[0x10];
b4ff3a36 5574 u8 reserved_at_10[0x10];
e281682b 5575
b4ff3a36 5576 u8 reserved_at_20[0x10];
e281682b
SM		 5577 u8 op_mod[0x10];
5578
b4ff3a36 5579 u8 reserved_at_40[0x8];
e281682b
SM		 5580 u8 dctn[0x18];
5581
b4ff3a36 5582 u8 reserved_at_60[0x20];
e281682b
SM		 5583};
5584
5585struct mlx5_ifc_disable_hca_out_bits {
5586 u8 status[0x8];
b4ff3a36 5587 u8 reserved_at_8[0x18];
e281682b
SM		 5588
5589 u8 syndrome[0x20];
5590
b4ff3a36 5591 u8 reserved_at_40[0x20];
e281682b
SM		 5592};
5593
5594struct mlx5_ifc_disable_hca_in_bits {
5595 u8 opcode[0x10];
b4ff3a36 5596 u8 reserved_at_10[0x10];
e281682b 5597
b4ff3a36 5598 u8 reserved_at_20[0x10];
e281682b
SM		 5599 u8 op_mod[0x10];
5600
b4ff3a36 5601 u8 reserved_at_40[0x10];
e281682b
SM		 5602 u8 function_id[0x10];
5603
b4ff3a36 5604 u8 reserved_at_60[0x20];
e281682b
SM		 5605};
5606
5607struct mlx5_ifc_detach_from_mcg_out_bits {
5608 u8 status[0x8];
b4ff3a36 5609 u8 reserved_at_8[0x18];
e281682b
SM		 5610
5611 u8 syndrome[0x20];
5612
b4ff3a36 5613 u8 reserved_at_40[0x40];
e281682b
SM		 5614};
5615
5616struct mlx5_ifc_detach_from_mcg_in_bits {
5617 u8 opcode[0x10];
b4ff3a36 5618 u8 reserved_at_10[0x10];
e281682b 5619
b4ff3a36 5620 u8 reserved_at_20[0x10];
e281682b
SM		 5621 u8 op_mod[0x10];
5622
b4ff3a36 5623 u8 reserved_at_40[0x8];
e281682b
SM		 5624 u8 qpn[0x18];
5625
b4ff3a36 5626 u8 reserved_at_60[0x20];
e281682b
SM		 5627
5628 u8 multicast_gid[16][0x8];
5629};
5630
7486216b
SM		 5631struct mlx5_ifc_destroy_xrq_out_bits {
5632 u8 status[0x8];
5633 u8 reserved_at_8[0x18];
5634
5635 u8 syndrome[0x20];
5636
5637 u8 reserved_at_40[0x40];
5638};
5639
5640struct mlx5_ifc_destroy_xrq_in_bits {
5641 u8 opcode[0x10];
5642 u8 reserved_at_10[0x10];
5643
5644 u8 reserved_at_20[0x10];
5645 u8 op_mod[0x10];
5646
5647 u8 reserved_at_40[0x8];
5648 u8 xrqn[0x18];
5649
5650 u8 reserved_at_60[0x20];
5651};
5652
e281682b
SM		 5653struct mlx5_ifc_destroy_xrc_srq_out_bits {
5654 u8 status[0x8];
b4ff3a36 5655 u8 reserved_at_8[0x18];
e281682b
SM		 5656
5657 u8 syndrome[0x20];
5658
b4ff3a36 5659 u8 reserved_at_40[0x40];
e281682b
SM		 5660};
5661
5662struct mlx5_ifc_destroy_xrc_srq_in_bits {
5663 u8 opcode[0x10];
b4ff3a36 5664 u8 reserved_at_10[0x10];
e281682b 5665
b4ff3a36 5666 u8 reserved_at_20[0x10];
e281682b
SM		 5667 u8 op_mod[0x10];
5668
b4ff3a36 5669 u8 reserved_at_40[0x8];
e281682b
SM		 5670 u8 xrc_srqn[0x18];
5671
b4ff3a36 5672 u8 reserved_at_60[0x20];
e281682b
SM		 5673};
5674
5675struct mlx5_ifc_destroy_tis_out_bits {
5676 u8 status[0x8];
b4ff3a36 5677 u8 reserved_at_8[0x18];
e281682b
SM		 5678
5679 u8 syndrome[0x20];
5680
b4ff3a36 5681 u8 reserved_at_40[0x40];
e281682b
SM		 5682};
5683
5684struct mlx5_ifc_destroy_tis_in_bits {
5685 u8 opcode[0x10];
b4ff3a36 5686 u8 reserved_at_10[0x10];
e281682b 5687
b4ff3a36 5688 u8 reserved_at_20[0x10];
e281682b
SM		 5689 u8 op_mod[0x10];
5690
b4ff3a36 5691 u8 reserved_at_40[0x8];
e281682b
SM		 5692 u8 tisn[0x18];
5693
b4ff3a36 5694 u8 reserved_at_60[0x20];
e281682b
SM		 5695};
5696
5697struct mlx5_ifc_destroy_tir_out_bits {
5698 u8 status[0x8];
b4ff3a36 5699 u8 reserved_at_8[0x18];
e281682b
SM		 5700
5701 u8 syndrome[0x20];
5702
b4ff3a36 5703 u8 reserved_at_40[0x40];
e281682b
SM		 5704};
5705
5706struct mlx5_ifc_destroy_tir_in_bits {
5707 u8 opcode[0x10];
b4ff3a36 5708 u8 reserved_at_10[0x10];
e281682b 5709
b4ff3a36 5710 u8 reserved_at_20[0x10];
e281682b
SM		 5711 u8 op_mod[0x10];
5712
b4ff3a36 5713 u8 reserved_at_40[0x8];
e281682b
SM		 5714 u8 tirn[0x18];
5715
b4ff3a36 5716 u8 reserved_at_60[0x20];
e281682b
SM		 5717};
5718
5719struct mlx5_ifc_destroy_srq_out_bits {
5720 u8 status[0x8];
b4ff3a36 5721 u8 reserved_at_8[0x18];
e281682b
SM		 5722
5723 u8 syndrome[0x20];
5724
b4ff3a36 5725 u8 reserved_at_40[0x40];
e281682b
SM		 5726};
5727
5728struct mlx5_ifc_destroy_srq_in_bits {
5729 u8 opcode[0x10];
b4ff3a36 5730 u8 reserved_at_10[0x10];
e281682b 5731
b4ff3a36 5732 u8 reserved_at_20[0x10];
e281682b
SM		 5733 u8 op_mod[0x10];
5734
b4ff3a36 5735 u8 reserved_at_40[0x8];
e281682b
SM		 5736 u8 srqn[0x18];
5737
b4ff3a36 5738 u8 reserved_at_60[0x20];
e281682b
SM		 5739};
5740
5741struct mlx5_ifc_destroy_sq_out_bits {
5742 u8 status[0x8];
b4ff3a36 5743 u8 reserved_at_8[0x18];
e281682b
SM		 5744
5745 u8 syndrome[0x20];
5746
b4ff3a36 5747 u8 reserved_at_40[0x40];
e281682b
SM		 5748};
5749
5750struct mlx5_ifc_destroy_sq_in_bits {
5751 u8 opcode[0x10];
b4ff3a36 5752 u8 reserved_at_10[0x10];
e281682b 5753
b4ff3a36 5754 u8 reserved_at_20[0x10];
e281682b
SM		 5755 u8 op_mod[0x10];
5756
b4ff3a36 5757 u8 reserved_at_40[0x8];
e281682b
SM		 5758 u8 sqn[0x18];
5759
b4ff3a36 5760 u8 reserved_at_60[0x20];
e281682b
SM		 5761};
5762
813f8540
MHY		 5763struct mlx5_ifc_destroy_scheduling_element_out_bits {
5764 u8 status[0x8];
5765 u8 reserved_at_8[0x18];
5766
5767 u8 syndrome[0x20];
5768
5769 u8 reserved_at_40[0x1c0];
5770};
5771
5772struct mlx5_ifc_destroy_scheduling_element_in_bits {
5773 u8 opcode[0x10];
5774 u8 reserved_at_10[0x10];
5775
5776 u8 reserved_at_20[0x10];
5777 u8 op_mod[0x10];
5778
5779 u8 scheduling_hierarchy[0x8];
5780 u8 reserved_at_48[0x18];
5781
5782 u8 scheduling_element_id[0x20];
5783
5784 u8 reserved_at_80[0x180];
5785};
5786
e281682b
SM		 5787struct mlx5_ifc_destroy_rqt_out_bits {
5788 u8 status[0x8];
b4ff3a36 5789 u8 reserved_at_8[0x18];
e281682b
SM		 5790
5791 u8 syndrome[0x20];
5792
b4ff3a36 5793 u8 reserved_at_40[0x40];
e281682b
SM		 5794};
5795
5796struct mlx5_ifc_destroy_rqt_in_bits {
5797 u8 opcode[0x10];
b4ff3a36 5798 u8 reserved_at_10[0x10];
e281682b 5799
b4ff3a36 5800 u8 reserved_at_20[0x10];
e281682b
SM		 5801 u8 op_mod[0x10];
5802
b4ff3a36 5803 u8 reserved_at_40[0x8];
e281682b
SM		 5804 u8 rqtn[0x18];
5805
b4ff3a36 5806 u8 reserved_at_60[0x20];
e281682b
SM		 5807};
5808
5809struct mlx5_ifc_destroy_rq_out_bits {
5810 u8 status[0x8];
b4ff3a36 5811 u8 reserved_at_8[0x18];
e281682b
SM		 5812
5813 u8 syndrome[0x20];
5814
b4ff3a36 5815 u8 reserved_at_40[0x40];
e281682b
SM		 5816};
5817
5818struct mlx5_ifc_destroy_rq_in_bits {
5819 u8 opcode[0x10];
b4ff3a36 5820 u8 reserved_at_10[0x10];
e281682b 5821
b4ff3a36 5822 u8 reserved_at_20[0x10];
e281682b
SM		 5823 u8 op_mod[0x10];
5824
b4ff3a36 5825 u8 reserved_at_40[0x8];
e281682b
SM		 5826 u8 rqn[0x18];
5827
b4ff3a36 5828 u8 reserved_at_60[0x20];
e281682b
SM		 5829};
5830
5831struct mlx5_ifc_destroy_rmp_out_bits {
5832 u8 status[0x8];
b4ff3a36 5833 u8 reserved_at_8[0x18];
e281682b
SM		 5834
5835 u8 syndrome[0x20];
5836
b4ff3a36 5837 u8 reserved_at_40[0x40];
e281682b
SM		 5838};
5839
5840struct mlx5_ifc_destroy_rmp_in_bits {
5841 u8 opcode[0x10];
b4ff3a36 5842 u8 reserved_at_10[0x10];
e281682b 5843
b4ff3a36 5844 u8 reserved_at_20[0x10];
e281682b
SM		 5845 u8 op_mod[0x10];
5846
b4ff3a36 5847 u8 reserved_at_40[0x8];
e281682b
SM		 5848 u8 rmpn[0x18];
5849
b4ff3a36 5850 u8 reserved_at_60[0x20];
e281682b
SM		 5851};
5852
5853struct mlx5_ifc_destroy_qp_out_bits {
5854 u8 status[0x8];
b4ff3a36 5855 u8 reserved_at_8[0x18];
e281682b
SM		 5856
5857 u8 syndrome[0x20];
5858
b4ff3a36 5859 u8 reserved_at_40[0x40];
e281682b
SM		 5860};
5861
5862struct mlx5_ifc_destroy_qp_in_bits {
5863 u8 opcode[0x10];
b4ff3a36 5864 u8 reserved_at_10[0x10];
e281682b 5865
b4ff3a36 5866 u8 reserved_at_20[0x10];
e281682b
SM		 5867 u8 op_mod[0x10];
5868
b4ff3a36 5869 u8 reserved_at_40[0x8];
e281682b
SM		 5870 u8 qpn[0x18];
5871
b4ff3a36 5872 u8 reserved_at_60[0x20];
e281682b
SM		 5873};
5874
5875struct mlx5_ifc_destroy_psv_out_bits {
5876 u8 status[0x8];
b4ff3a36 5877 u8 reserved_at_8[0x18];
e281682b
SM		 5878
5879 u8 syndrome[0x20];
5880
b4ff3a36 5881 u8 reserved_at_40[0x40];
e281682b
SM		 5882};
5883
5884struct mlx5_ifc_destroy_psv_in_bits {
5885 u8 opcode[0x10];
b4ff3a36 5886 u8 reserved_at_10[0x10];
e281682b 5887
b4ff3a36 5888 u8 reserved_at_20[0x10];
e281682b
SM		 5889 u8 op_mod[0x10];
5890
b4ff3a36 5891 u8 reserved_at_40[0x8];
e281682b
SM		 5892 u8 psvn[0x18];
5893
b4ff3a36 5894 u8 reserved_at_60[0x20];
e281682b
SM		 5895};
5896
5897struct mlx5_ifc_destroy_mkey_out_bits {
5898 u8 status[0x8];
b4ff3a36 5899 u8 reserved_at_8[0x18];
e281682b
SM		 5900
5901 u8 syndrome[0x20];
5902
b4ff3a36 5903 u8 reserved_at_40[0x40];
e281682b
SM		 5904};
5905
5906struct mlx5_ifc_destroy_mkey_in_bits {
5907 u8 opcode[0x10];
b4ff3a36 5908 u8 reserved_at_10[0x10];
e281682b 5909
b4ff3a36 5910 u8 reserved_at_20[0x10];
e281682b
SM		 5911 u8 op_mod[0x10];
5912
b4ff3a36 5913 u8 reserved_at_40[0x8];
e281682b
SM		 5914 u8 mkey_index[0x18];
5915
b4ff3a36 5916 u8 reserved_at_60[0x20];
e281682b
SM		 5917};
5918
5919struct mlx5_ifc_destroy_flow_table_out_bits {
5920 u8 status[0x8];
b4ff3a36 5921 u8 reserved_at_8[0x18];
e281682b
SM		 5922
5923 u8 syndrome[0x20];
5924
b4ff3a36 5925 u8 reserved_at_40[0x40];
e281682b
SM		 5926};
5927
5928struct mlx5_ifc_destroy_flow_table_in_bits {
5929 u8 opcode[0x10];
b4ff3a36 5930 u8 reserved_at_10[0x10];
e281682b 5931
b4ff3a36 5932 u8 reserved_at_20[0x10];
e281682b
SM		 5933 u8 op_mod[0x10];
5934
7d5e1423
SM		 5935 u8 other_vport[0x1];
5936 u8 reserved_at_41[0xf];
5937 u8 vport_number[0x10];
5938
5939 u8 reserved_at_60[0x20];
e281682b
SM		 5940
5941 u8 table_type[0x8];
b4ff3a36 5942 u8 reserved_at_88[0x18];
e281682b 5943
b4ff3a36 5944 u8 reserved_at_a0[0x8];
e281682b
SM		 5945 u8 table_id[0x18];
5946
b4ff3a36 5947 u8 reserved_at_c0[0x140];
e281682b
SM		 5948};
5949
5950struct mlx5_ifc_destroy_flow_group_out_bits {
5951 u8 status[0x8];
b4ff3a36 5952 u8 reserved_at_8[0x18];
e281682b
SM		 5953
5954 u8 syndrome[0x20];
5955
b4ff3a36 5956 u8 reserved_at_40[0x40];
e281682b
SM		 5957};
5958
5959struct mlx5_ifc_destroy_flow_group_in_bits {
5960 u8 opcode[0x10];
b4ff3a36 5961 u8 reserved_at_10[0x10];
e281682b 5962
b4ff3a36 5963 u8 reserved_at_20[0x10];
e281682b
SM		 5964 u8 op_mod[0x10];
5965
7d5e1423
SM		 5966 u8 other_vport[0x1];
5967 u8 reserved_at_41[0xf];
5968 u8 vport_number[0x10];
5969
5970 u8 reserved_at_60[0x20];
e281682b
SM		 5971
5972 u8 table_type[0x8];
b4ff3a36 5973 u8 reserved_at_88[0x18];
e281682b 5974
b4ff3a36 5975 u8 reserved_at_a0[0x8];
e281682b
SM		 5976 u8 table_id[0x18];
5977
5978 u8 group_id[0x20];
5979
b4ff3a36 5980 u8 reserved_at_e0[0x120];
e281682b
SM		 5981};
5982
5983struct mlx5_ifc_destroy_eq_out_bits {
5984 u8 status[0x8];
b4ff3a36 5985 u8 reserved_at_8[0x18];
e281682b
SM		 5986
5987 u8 syndrome[0x20];
5988
b4ff3a36 5989 u8 reserved_at_40[0x40];
e281682b
SM		 5990};
5991
5992struct mlx5_ifc_destroy_eq_in_bits {
5993 u8 opcode[0x10];
b4ff3a36 5994 u8 reserved_at_10[0x10];
e281682b 5995
b4ff3a36 5996 u8 reserved_at_20[0x10];
e281682b
SM		 5997 u8 op_mod[0x10];
5998
b4ff3a36 5999 u8 reserved_at_40[0x18];
e281682b
SM		 6000 u8 eq_number[0x8];
6001
b4ff3a36 6002 u8 reserved_at_60[0x20];
e281682b
SM		 6003};
6004
6005struct mlx5_ifc_destroy_dct_out_bits {
6006 u8 status[0x8];
b4ff3a36 6007 u8 reserved_at_8[0x18];
e281682b
SM		 6008
6009 u8 syndrome[0x20];
6010
b4ff3a36 6011 u8 reserved_at_40[0x40];
e281682b
SM		 6012};
6013
6014struct mlx5_ifc_destroy_dct_in_bits {
6015 u8 opcode[0x10];
b4ff3a36 6016 u8 reserved_at_10[0x10];
e281682b 6017
b4ff3a36 6018 u8 reserved_at_20[0x10];
e281682b
SM		 6019 u8 op_mod[0x10];
6020
b4ff3a36 6021 u8 reserved_at_40[0x8];
e281682b
SM		 6022 u8 dctn[0x18];
6023
b4ff3a36 6024 u8 reserved_at_60[0x20];
e281682b
SM		 6025};
6026
6027struct mlx5_ifc_destroy_cq_out_bits {
6028 u8 status[0x8];
b4ff3a36 6029 u8 reserved_at_8[0x18];
e281682b
SM		 6030
6031 u8 syndrome[0x20];
6032
b4ff3a36 6033 u8 reserved_at_40[0x40];
e281682b
SM		 6034};
6035
6036struct mlx5_ifc_destroy_cq_in_bits {
6037 u8 opcode[0x10];
b4ff3a36 6038 u8 reserved_at_10[0x10];
e281682b 6039
b4ff3a36 6040 u8 reserved_at_20[0x10];
e281682b
SM		 6041 u8 op_mod[0x10];
6042
b4ff3a36 6043 u8 reserved_at_40[0x8];
e281682b
SM		 6044 u8 cqn[0x18];
6045
b4ff3a36 6046 u8 reserved_at_60[0x20];
e281682b
SM		 6047};
6048
6049struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6050 u8 status[0x8];
b4ff3a36 6051 u8 reserved_at_8[0x18];
e281682b
SM		 6052
6053 u8 syndrome[0x20];
6054
b4ff3a36 6055 u8 reserved_at_40[0x40];
e281682b
SM		 6056};
6057
6058struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6059 u8 opcode[0x10];
b4ff3a36 6060 u8 reserved_at_10[0x10];
e281682b 6061
b4ff3a36 6062 u8 reserved_at_20[0x10];
e281682b
SM		 6063 u8 op_mod[0x10];
6064
b4ff3a36 6065 u8 reserved_at_40[0x20];
e281682b 6066
b4ff3a36 6067 u8 reserved_at_60[0x10];
e281682b
SM		 6068 u8 vxlan_udp_port[0x10];
6069};
6070
6071struct mlx5_ifc_delete_l2_table_entry_out_bits {
6072 u8 status[0x8];
b4ff3a36 6073 u8 reserved_at_8[0x18];
e281682b
SM		 6074
6075 u8 syndrome[0x20];
6076
b4ff3a36 6077 u8 reserved_at_40[0x40];
e281682b
SM		 6078};
6079
6080struct mlx5_ifc_delete_l2_table_entry_in_bits {
6081 u8 opcode[0x10];
b4ff3a36 6082 u8 reserved_at_10[0x10];
e281682b 6083
b4ff3a36 6084 u8 reserved_at_20[0x10];
e281682b
SM		 6085 u8 op_mod[0x10];
6086
b4ff3a36 6087 u8 reserved_at_40[0x60];
e281682b 6088
b4ff3a36 6089 u8 reserved_at_a0[0x8];
e281682b
SM		 6090 u8 table_index[0x18];
6091
b4ff3a36 6092 u8 reserved_at_c0[0x140];
e281682b
SM		 6093};
6094
6095struct mlx5_ifc_delete_fte_out_bits {
6096 u8 status[0x8];
b4ff3a36 6097 u8 reserved_at_8[0x18];
e281682b
SM		 6098
6099 u8 syndrome[0x20];
6100
b4ff3a36 6101 u8 reserved_at_40[0x40];
e281682b
SM		 6102};
6103
6104struct mlx5_ifc_delete_fte_in_bits {
6105 u8 opcode[0x10];
b4ff3a36 6106 u8 reserved_at_10[0x10];
e281682b 6107
b4ff3a36 6108 u8 reserved_at_20[0x10];
e281682b
SM		 6109 u8 op_mod[0x10];
6110
7d5e1423
SM		 6111 u8 other_vport[0x1];
6112 u8 reserved_at_41[0xf];
6113 u8 vport_number[0x10];
6114
6115 u8 reserved_at_60[0x20];
e281682b
SM		 6116
6117 u8 table_type[0x8];
b4ff3a36 6118 u8 reserved_at_88[0x18];
e281682b 6119
b4ff3a36 6120 u8 reserved_at_a0[0x8];
e281682b
SM		 6121 u8 table_id[0x18];
6122
b4ff3a36 6123 u8 reserved_at_c0[0x40];
e281682b
SM		 6124
6125 u8 flow_index[0x20];
6126
b4ff3a36 6127 u8 reserved_at_120[0xe0];
e281682b
SM		 6128};
6129
6130struct mlx5_ifc_dealloc_xrcd_out_bits {
6131 u8 status[0x8];
b4ff3a36 6132 u8 reserved_at_8[0x18];
e281682b
SM		 6133
6134 u8 syndrome[0x20];
6135
b4ff3a36 6136 u8 reserved_at_40[0x40];
e281682b
SM		 6137};
6138
6139struct mlx5_ifc_dealloc_xrcd_in_bits {
6140 u8 opcode[0x10];
b4ff3a36 6141 u8 reserved_at_10[0x10];
e281682b 6142
b4ff3a36 6143 u8 reserved_at_20[0x10];
e281682b
SM		 6144 u8 op_mod[0x10];
6145
b4ff3a36 6146 u8 reserved_at_40[0x8];
e281682b
SM		 6147 u8 xrcd[0x18];
6148
b4ff3a36 6149 u8 reserved_at_60[0x20];
e281682b
SM		 6150};
6151
6152struct mlx5_ifc_dealloc_uar_out_bits {
6153 u8 status[0x8];
b4ff3a36 6154 u8 reserved_at_8[0x18];
e281682b
SM		 6155
6156 u8 syndrome[0x20];
6157
b4ff3a36 6158 u8 reserved_at_40[0x40];
e281682b
SM		 6159};
6160
6161struct mlx5_ifc_dealloc_uar_in_bits {
6162 u8 opcode[0x10];
b4ff3a36 6163 u8 reserved_at_10[0x10];
e281682b 6164
b4ff3a36 6165 u8 reserved_at_20[0x10];
e281682b
SM		 6166 u8 op_mod[0x10];
6167
b4ff3a36 6168 u8 reserved_at_40[0x8];
e281682b
SM		 6169 u8 uar[0x18];
6170
b4ff3a36 6171 u8 reserved_at_60[0x20];
e281682b
SM		 6172};
6173
6174struct mlx5_ifc_dealloc_transport_domain_out_bits {
6175 u8 status[0x8];
b4ff3a36 6176 u8 reserved_at_8[0x18];
e281682b
SM		 6177
6178 u8 syndrome[0x20];
6179
b4ff3a36 6180 u8 reserved_at_40[0x40];
e281682b
SM		 6181};
6182
6183struct mlx5_ifc_dealloc_transport_domain_in_bits {
6184 u8 opcode[0x10];
b4ff3a36 6185 u8 reserved_at_10[0x10];
e281682b 6186
b4ff3a36 6187 u8 reserved_at_20[0x10];
e281682b
SM		 6188 u8 op_mod[0x10];
6189
b4ff3a36 6190 u8 reserved_at_40[0x8];
e281682b
SM		 6191 u8 transport_domain[0x18];
6192
b4ff3a36 6193 u8 reserved_at_60[0x20];
e281682b
SM		 6194};
6195
6196struct mlx5_ifc_dealloc_q_counter_out_bits {
6197 u8 status[0x8];
b4ff3a36 6198 u8 reserved_at_8[0x18];
e281682b
SM		 6199
6200 u8 syndrome[0x20];
6201
b4ff3a36 6202 u8 reserved_at_40[0x40];
e281682b
SM		 6203};
6204
6205struct mlx5_ifc_dealloc_q_counter_in_bits {
6206 u8 opcode[0x10];
b4ff3a36 6207 u8 reserved_at_10[0x10];
e281682b 6208
b4ff3a36 6209 u8 reserved_at_20[0x10];
e281682b
SM		 6210 u8 op_mod[0x10];
6211
b4ff3a36 6212 u8 reserved_at_40[0x18];
e281682b
SM		 6213 u8 counter_set_id[0x8];
6214
b4ff3a36 6215 u8 reserved_at_60[0x20];
e281682b
SM		 6216};
6217
6218struct mlx5_ifc_dealloc_pd_out_bits {
6219 u8 status[0x8];
b4ff3a36 6220 u8 reserved_at_8[0x18];
e281682b
SM		 6221
6222 u8 syndrome[0x20];
6223
b4ff3a36 6224 u8 reserved_at_40[0x40];
e281682b
SM		 6225};
6226
6227struct mlx5_ifc_dealloc_pd_in_bits {
6228 u8 opcode[0x10];
b4ff3a36 6229 u8 reserved_at_10[0x10];
e281682b 6230
b4ff3a36 6231 u8 reserved_at_20[0x10];
e281682b
SM		 6232 u8 op_mod[0x10];
6233
b4ff3a36 6234 u8 reserved_at_40[0x8];
e281682b
SM		 6235 u8 pd[0x18];
6236
b4ff3a36 6237 u8 reserved_at_60[0x20];
e281682b
SM		 6238};
6239
9dc0b289
AV		 6240struct mlx5_ifc_dealloc_flow_counter_out_bits {
6241 u8 status[0x8];
6242 u8 reserved_at_8[0x18];
6243
6244 u8 syndrome[0x20];
6245
6246 u8 reserved_at_40[0x40];
6247};
6248
6249struct mlx5_ifc_dealloc_flow_counter_in_bits {
6250 u8 opcode[0x10];
6251 u8 reserved_at_10[0x10];
6252
6253 u8 reserved_at_20[0x10];
6254 u8 op_mod[0x10];
6255
6256 u8 reserved_at_40[0x10];
6257 u8 flow_counter_id[0x10];
6258
6259 u8 reserved_at_60[0x20];
6260};
6261
7486216b
SM		 6262struct mlx5_ifc_create_xrq_out_bits {
6263 u8 status[0x8];
6264 u8 reserved_at_8[0x18];
6265
6266 u8 syndrome[0x20];
6267
6268 u8 reserved_at_40[0x8];
6269 u8 xrqn[0x18];
6270
6271 u8 reserved_at_60[0x20];
6272};
6273
6274struct mlx5_ifc_create_xrq_in_bits {
6275 u8 opcode[0x10];
6276 u8 reserved_at_10[0x10];
6277
6278 u8 reserved_at_20[0x10];
6279 u8 op_mod[0x10];
6280
6281 u8 reserved_at_40[0x40];
6282
6283 struct mlx5_ifc_xrqc_bits xrq_context;
6284};
6285
e281682b
SM		 6286struct mlx5_ifc_create_xrc_srq_out_bits {
6287 u8 status[0x8];
b4ff3a36 6288 u8 reserved_at_8[0x18];
e281682b
SM		 6289
6290 u8 syndrome[0x20];
6291
b4ff3a36 6292 u8 reserved_at_40[0x8];
e281682b
SM		 6293 u8 xrc_srqn[0x18];
6294
b4ff3a36 6295 u8 reserved_at_60[0x20];
e281682b
SM		 6296};
6297
6298struct mlx5_ifc_create_xrc_srq_in_bits {
6299 u8 opcode[0x10];
b4ff3a36 6300 u8 reserved_at_10[0x10];
e281682b 6301
b4ff3a36 6302 u8 reserved_at_20[0x10];
e281682b
SM		 6303 u8 op_mod[0x10];
6304
b4ff3a36 6305 u8 reserved_at_40[0x40];
e281682b
SM		 6306
6307 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6308
b4ff3a36 6309 u8 reserved_at_280[0x600];
e281682b
SM		 6310
6311 u8 pas[0][0x40];
6312};
6313
6314struct mlx5_ifc_create_tis_out_bits {
6315 u8 status[0x8];
b4ff3a36 6316 u8 reserved_at_8[0x18];
e281682b
SM		 6317
6318 u8 syndrome[0x20];
6319
b4ff3a36 6320 u8 reserved_at_40[0x8];
e281682b
SM		 6321 u8 tisn[0x18];
6322
b4ff3a36 6323 u8 reserved_at_60[0x20];
e281682b
SM		 6324};
6325
6326struct mlx5_ifc_create_tis_in_bits {
6327 u8 opcode[0x10];
b4ff3a36 6328 u8 reserved_at_10[0x10];
e281682b 6329
b4ff3a36 6330 u8 reserved_at_20[0x10];
e281682b
SM		 6331 u8 op_mod[0x10];
6332
b4ff3a36 6333 u8 reserved_at_40[0xc0];
e281682b
SM		 6334
6335 struct mlx5_ifc_tisc_bits ctx;
6336};
6337
6338struct mlx5_ifc_create_tir_out_bits {
6339 u8 status[0x8];
b4ff3a36 6340 u8 reserved_at_8[0x18];
e281682b
SM		 6341
6342 u8 syndrome[0x20];
6343
b4ff3a36 6344 u8 reserved_at_40[0x8];
e281682b
SM		 6345 u8 tirn[0x18];
6346
b4ff3a36 6347 u8 reserved_at_60[0x20];
e281682b
SM		 6348};
6349
6350struct mlx5_ifc_create_tir_in_bits {
6351 u8 opcode[0x10];
b4ff3a36 6352 u8 reserved_at_10[0x10];
e281682b 6353
b4ff3a36 6354 u8 reserved_at_20[0x10];
e281682b
SM		 6355 u8 op_mod[0x10];
6356
b4ff3a36 6357 u8 reserved_at_40[0xc0];
e281682b
SM		 6358
6359 struct mlx5_ifc_tirc_bits ctx;
6360};
6361
6362struct mlx5_ifc_create_srq_out_bits {
6363 u8 status[0x8];
b4ff3a36 6364 u8 reserved_at_8[0x18];
e281682b
SM		 6365
6366 u8 syndrome[0x20];
6367
b4ff3a36 6368 u8 reserved_at_40[0x8];
e281682b
SM		 6369 u8 srqn[0x18];
6370
b4ff3a36 6371 u8 reserved_at_60[0x20];
e281682b
SM		 6372};
6373
6374struct mlx5_ifc_create_srq_in_bits {
6375 u8 opcode[0x10];
b4ff3a36 6376 u8 reserved_at_10[0x10];
e281682b 6377
b4ff3a36 6378 u8 reserved_at_20[0x10];
e281682b
SM		 6379 u8 op_mod[0x10];
6380
b4ff3a36 6381 u8 reserved_at_40[0x40];
e281682b
SM		 6382
6383 struct mlx5_ifc_srqc_bits srq_context_entry;
6384
b4ff3a36 6385 u8 reserved_at_280[0x600];
e281682b
SM		 6386
6387 u8 pas[0][0x40];
6388};
6389
6390struct mlx5_ifc_create_sq_out_bits {
6391 u8 status[0x8];
b4ff3a36 6392 u8 reserved_at_8[0x18];
e281682b
SM		 6393
6394 u8 syndrome[0x20];
6395
b4ff3a36 6396 u8 reserved_at_40[0x8];
e281682b
SM		 6397 u8 sqn[0x18];
6398
b4ff3a36 6399 u8 reserved_at_60[0x20];
e281682b
SM		 6400};
6401
6402struct mlx5_ifc_create_sq_in_bits {
6403 u8 opcode[0x10];
b4ff3a36 6404 u8 reserved_at_10[0x10];
e281682b 6405
b4ff3a36 6406 u8 reserved_at_20[0x10];
e281682b
SM		 6407 u8 op_mod[0x10];
6408
b4ff3a36 6409 u8 reserved_at_40[0xc0];
e281682b
SM		 6410
6411 struct mlx5_ifc_sqc_bits ctx;
6412};
6413
813f8540
MHY		 6414struct mlx5_ifc_create_scheduling_element_out_bits {
6415 u8 status[0x8];
6416 u8 reserved_at_8[0x18];
6417
6418 u8 syndrome[0x20];
6419
6420 u8 reserved_at_40[0x40];
6421
6422 u8 scheduling_element_id[0x20];
6423
6424 u8 reserved_at_a0[0x160];
6425};
6426
6427struct mlx5_ifc_create_scheduling_element_in_bits {
6428 u8 opcode[0x10];
6429 u8 reserved_at_10[0x10];
6430
6431 u8 reserved_at_20[0x10];
6432 u8 op_mod[0x10];
6433
6434 u8 scheduling_hierarchy[0x8];
6435 u8 reserved_at_48[0x18];
6436
6437 u8 reserved_at_60[0xa0];
6438
6439 struct mlx5_ifc_scheduling_context_bits scheduling_context;
6440
6441 u8 reserved_at_300[0x100];
6442};
6443
e281682b
SM		 6444struct mlx5_ifc_create_rqt_out_bits {
6445 u8 status[0x8];
b4ff3a36 6446 u8 reserved_at_8[0x18];
e281682b
SM		 6447
6448 u8 syndrome[0x20];
6449
b4ff3a36 6450 u8 reserved_at_40[0x8];
e281682b
SM		 6451 u8 rqtn[0x18];
6452
b4ff3a36 6453 u8 reserved_at_60[0x20];
e281682b
SM		 6454};
6455
6456struct mlx5_ifc_create_rqt_in_bits {
6457 u8 opcode[0x10];
b4ff3a36 6458 u8 reserved_at_10[0x10];
e281682b 6459
b4ff3a36 6460 u8 reserved_at_20[0x10];
e281682b
SM		 6461 u8 op_mod[0x10];
6462
b4ff3a36 6463 u8 reserved_at_40[0xc0];
e281682b
SM		 6464
6465 struct mlx5_ifc_rqtc_bits rqt_context;
6466};
6467
6468struct mlx5_ifc_create_rq_out_bits {
6469 u8 status[0x8];
b4ff3a36 6470 u8 reserved_at_8[0x18];
e281682b
SM		 6471
6472 u8 syndrome[0x20];
6473
b4ff3a36 6474 u8 reserved_at_40[0x8];
e281682b
SM		 6475 u8 rqn[0x18];
6476
b4ff3a36 6477 u8 reserved_at_60[0x20];
e281682b
SM		 6478};
6479
6480struct mlx5_ifc_create_rq_in_bits {
6481 u8 opcode[0x10];
b4ff3a36 6482 u8 reserved_at_10[0x10];
e281682b 6483
b4ff3a36 6484 u8 reserved_at_20[0x10];
e281682b
SM		 6485 u8 op_mod[0x10];
6486
b4ff3a36 6487 u8 reserved_at_40[0xc0];
e281682b
SM		 6488
6489 struct mlx5_ifc_rqc_bits ctx;
6490};
6491
6492struct mlx5_ifc_create_rmp_out_bits {
6493 u8 status[0x8];
b4ff3a36 6494 u8 reserved_at_8[0x18];
e281682b
SM		 6495
6496 u8 syndrome[0x20];
6497
b4ff3a36 6498 u8 reserved_at_40[0x8];
e281682b
SM		 6499 u8 rmpn[0x18];
6500
b4ff3a36 6501 u8 reserved_at_60[0x20];
e281682b
SM		 6502};
6503
6504struct mlx5_ifc_create_rmp_in_bits {
6505 u8 opcode[0x10];
b4ff3a36 6506 u8 reserved_at_10[0x10];
e281682b 6507
b4ff3a36 6508 u8 reserved_at_20[0x10];
e281682b
SM		 6509 u8 op_mod[0x10];
6510
b4ff3a36 6511 u8 reserved_at_40[0xc0];
e281682b
SM		 6512
6513 struct mlx5_ifc_rmpc_bits ctx;
6514};
6515
6516struct mlx5_ifc_create_qp_out_bits {
6517 u8 status[0x8];
b4ff3a36 6518 u8 reserved_at_8[0x18];
e281682b
SM		 6519
6520 u8 syndrome[0x20];
6521
b4ff3a36 6522 u8 reserved_at_40[0x8];
e281682b
SM		 6523 u8 qpn[0x18];
6524
b4ff3a36 6525 u8 reserved_at_60[0x20];
e281682b
SM		 6526};
6527
6528struct mlx5_ifc_create_qp_in_bits {
6529 u8 opcode[0x10];
b4ff3a36 6530 u8 reserved_at_10[0x10];
e281682b 6531
b4ff3a36 6532 u8 reserved_at_20[0x10];
e281682b
SM		 6533 u8 op_mod[0x10];
6534
b4ff3a36 6535 u8 reserved_at_40[0x40];
e281682b
SM		 6536
6537 u8 opt_param_mask[0x20];
6538
b4ff3a36 6539 u8 reserved_at_a0[0x20];
e281682b
SM		 6540
6541 struct mlx5_ifc_qpc_bits qpc;
6542
b4ff3a36 6543 u8 reserved_at_800[0x80];
e281682b
SM		 6544
6545 u8 pas[0][0x40];
6546};
6547
6548struct mlx5_ifc_create_psv_out_bits {
6549 u8 status[0x8];
b4ff3a36 6550 u8 reserved_at_8[0x18];
e281682b
SM		 6551
6552 u8 syndrome[0x20];
6553
b4ff3a36 6554 u8 reserved_at_40[0x40];
e281682b 6555
b4ff3a36 6556 u8 reserved_at_80[0x8];
e281682b
SM		 6557 u8 psv0_index[0x18];
6558
b4ff3a36 6559 u8 reserved_at_a0[0x8];
e281682b
SM		 6560 u8 psv1_index[0x18];
6561
b4ff3a36 6562 u8 reserved_at_c0[0x8];
e281682b
SM		 6563 u8 psv2_index[0x18];
6564
b4ff3a36 6565 u8 reserved_at_e0[0x8];
e281682b
SM		 6566 u8 psv3_index[0x18];
6567};
6568
6569struct mlx5_ifc_create_psv_in_bits {
6570 u8 opcode[0x10];
b4ff3a36 6571 u8 reserved_at_10[0x10];
e281682b 6572
b4ff3a36 6573 u8 reserved_at_20[0x10];
e281682b
SM		 6574 u8 op_mod[0x10];
6575
6576 u8 num_psv[0x4];
b4ff3a36 6577 u8 reserved_at_44[0x4];
e281682b
SM		 6578 u8 pd[0x18];
6579
b4ff3a36 6580 u8 reserved_at_60[0x20];
e281682b
SM		 6581};
6582
6583struct mlx5_ifc_create_mkey_out_bits {
6584 u8 status[0x8];
b4ff3a36 6585 u8 reserved_at_8[0x18];
e281682b
SM		 6586
6587 u8 syndrome[0x20];
6588
b4ff3a36 6589 u8 reserved_at_40[0x8];
e281682b
SM		 6590 u8 mkey_index[0x18];
6591
b4ff3a36 6592 u8 reserved_at_60[0x20];
e281682b
SM		 6593};
6594
6595struct mlx5_ifc_create_mkey_in_bits {
6596 u8 opcode[0x10];
b4ff3a36 6597 u8 reserved_at_10[0x10];
e281682b 6598
b4ff3a36 6599 u8 reserved_at_20[0x10];
e281682b
SM		 6600 u8 op_mod[0x10];
6601
b4ff3a36 6602 u8 reserved_at_40[0x20];
e281682b
SM		 6603
6604 u8 pg_access[0x1];
b4ff3a36 6605 u8 reserved_at_61[0x1f];
e281682b
SM		 6606
6607 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6608
b4ff3a36 6609 u8 reserved_at_280[0x80];
e281682b
SM		 6610
6611 u8 translations_octword_actual_size[0x20];
6612
b4ff3a36 6613 u8 reserved_at_320[0x560];
e281682b
SM		 6614
6615 u8 klm_pas_mtt[0][0x20];
6616};
6617
6618struct mlx5_ifc_create_flow_table_out_bits {
6619 u8 status[0x8];
b4ff3a36 6620 u8 reserved_at_8[0x18];
e281682b
SM		 6621
6622 u8 syndrome[0x20];
6623
b4ff3a36 6624 u8 reserved_at_40[0x8];
e281682b
SM		 6625 u8 table_id[0x18];
6626
b4ff3a36 6627 u8 reserved_at_60[0x20];
e281682b
SM		 6628};
6629
0c90e9c6
MG		 6630struct mlx5_ifc_flow_table_context_bits {
6631 u8 encap_en[0x1];
6632 u8 decap_en[0x1];
6633 u8 reserved_at_2[0x2];
6634 u8 table_miss_action[0x4];
6635 u8 level[0x8];
6636 u8 reserved_at_10[0x8];
6637 u8 log_size[0x8];
6638
6639 u8 reserved_at_20[0x8];
6640 u8 table_miss_id[0x18];
6641
6642 u8 reserved_at_40[0x8];
6643 u8 lag_master_next_table_id[0x18];
6644
6645 u8 reserved_at_60[0xe0];
6646};
6647
e281682b
SM		 6648struct mlx5_ifc_create_flow_table_in_bits {
6649 u8 opcode[0x10];
b4ff3a36 6650 u8 reserved_at_10[0x10];
e281682b 6651
b4ff3a36 6652 u8 reserved_at_20[0x10];
e281682b
SM		 6653 u8 op_mod[0x10];
6654
7d5e1423
SM		 6655 u8 other_vport[0x1];
6656 u8 reserved_at_41[0xf];
6657 u8 vport_number[0x10];
6658
6659 u8 reserved_at_60[0x20];
e281682b
SM		 6660
6661 u8 table_type[0x8];
b4ff3a36 6662 u8 reserved_at_88[0x18];
e281682b 6663
b4ff3a36 6664 u8 reserved_at_a0[0x20];
e281682b 6665
0c90e9c6 6666 struct mlx5_ifc_flow_table_context_bits flow_table_context;
e281682b
SM		 6667};
6668
6669struct mlx5_ifc_create_flow_group_out_bits {
6670 u8 status[0x8];
b4ff3a36 6671 u8 reserved_at_8[0x18];
e281682b
SM		 6672
6673 u8 syndrome[0x20];
6674
b4ff3a36 6675 u8 reserved_at_40[0x8];
e281682b
SM		 6676 u8 group_id[0x18];
6677
b4ff3a36 6678 u8 reserved_at_60[0x20];
e281682b
SM		 6679};
6680
6681enum {
6682 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
6683 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
6684 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
6685};
6686
6687struct mlx5_ifc_create_flow_group_in_bits {
6688 u8 opcode[0x10];
b4ff3a36 6689 u8 reserved_at_10[0x10];
e281682b 6690
b4ff3a36 6691 u8 reserved_at_20[0x10];
e281682b
SM		 6692 u8 op_mod[0x10];
6693
7d5e1423
SM		 6694 u8 other_vport[0x1];
6695 u8 reserved_at_41[0xf];
6696 u8 vport_number[0x10];
6697
6698 u8 reserved_at_60[0x20];
e281682b
SM		 6699
6700 u8 table_type[0x8];
b4ff3a36 6701 u8 reserved_at_88[0x18];
e281682b 6702
b4ff3a36 6703 u8 reserved_at_a0[0x8];
e281682b
SM		 6704 u8 table_id[0x18];
6705
b4ff3a36 6706 u8 reserved_at_c0[0x20];
e281682b
SM		 6707
6708 u8 start_flow_index[0x20];
6709
b4ff3a36 6710 u8 reserved_at_100[0x20];
e281682b
SM		 6711
6712 u8 end_flow_index[0x20];
6713
b4ff3a36 6714 u8 reserved_at_140[0xa0];
e281682b 6715
b4ff3a36 6716 u8 reserved_at_1e0[0x18];
e281682b
SM		 6717 u8 match_criteria_enable[0x8];
6718
6719 struct mlx5_ifc_fte_match_param_bits match_criteria;
6720
b4ff3a36 6721 u8 reserved_at_1200[0xe00];
e281682b
SM		 6722};
6723
6724struct mlx5_ifc_create_eq_out_bits {
6725 u8 status[0x8];
b4ff3a36 6726 u8 reserved_at_8[0x18];
e281682b
SM		 6727
6728 u8 syndrome[0x20];
6729
b4ff3a36 6730 u8 reserved_at_40[0x18];
e281682b
SM		 6731 u8 eq_number[0x8];
6732
b4ff3a36 6733 u8 reserved_at_60[0x20];
e281682b
SM		 6734};
6735
6736struct mlx5_ifc_create_eq_in_bits {
6737 u8 opcode[0x10];
b4ff3a36 6738 u8 reserved_at_10[0x10];
e281682b 6739
b4ff3a36 6740 u8 reserved_at_20[0x10];
e281682b
SM		 6741 u8 op_mod[0x10];
6742
b4ff3a36 6743 u8 reserved_at_40[0x40];
e281682b
SM		 6744
6745 struct mlx5_ifc_eqc_bits eq_context_entry;
6746
b4ff3a36 6747 u8 reserved_at_280[0x40];
e281682b
SM		 6748
6749 u8 event_bitmask[0x40];
6750
b4ff3a36 6751 u8 reserved_at_300[0x580];
e281682b
SM		 6752
6753 u8 pas[0][0x40];
6754};
6755
6756struct mlx5_ifc_create_dct_out_bits {
6757 u8 status[0x8];
b4ff3a36 6758 u8 reserved_at_8[0x18];
e281682b
SM		 6759
6760 u8 syndrome[0x20];
6761
b4ff3a36 6762 u8 reserved_at_40[0x8];
e281682b
SM		 6763 u8 dctn[0x18];
6764
b4ff3a36 6765 u8 reserved_at_60[0x20];
e281682b
SM		 6766};
6767
6768struct mlx5_ifc_create_dct_in_bits {
6769 u8 opcode[0x10];
b4ff3a36 6770 u8 reserved_at_10[0x10];
e281682b 6771
b4ff3a36 6772 u8 reserved_at_20[0x10];
e281682b
SM		 6773 u8 op_mod[0x10];
6774
b4ff3a36 6775 u8 reserved_at_40[0x40];
e281682b
SM		 6776
6777 struct mlx5_ifc_dctc_bits dct_context_entry;
6778
b4ff3a36 6779 u8 reserved_at_280[0x180];
e281682b
SM		 6780};
6781
6782struct mlx5_ifc_create_cq_out_bits {
6783 u8 status[0x8];
b4ff3a36 6784 u8 reserved_at_8[0x18];
e281682b
SM		 6785
6786 u8 syndrome[0x20];
6787
b4ff3a36 6788 u8 reserved_at_40[0x8];
e281682b
SM		 6789 u8 cqn[0x18];
6790
b4ff3a36 6791 u8 reserved_at_60[0x20];
e281682b
SM		 6792};
6793
6794struct mlx5_ifc_create_cq_in_bits {
6795 u8 opcode[0x10];
b4ff3a36 6796 u8 reserved_at_10[0x10];
e281682b 6797
b4ff3a36 6798 u8 reserved_at_20[0x10];
e281682b
SM		 6799 u8 op_mod[0x10];
6800
b4ff3a36 6801 u8 reserved_at_40[0x40];
e281682b
SM		 6802
6803 struct mlx5_ifc_cqc_bits cq_context;
6804
b4ff3a36 6805 u8 reserved_at_280[0x600];
e281682b
SM		 6806
6807 u8 pas[0][0x40];
6808};
6809
6810struct mlx5_ifc_config_int_moderation_out_bits {
6811 u8 status[0x8];
b4ff3a36 6812 u8 reserved_at_8[0x18];
e281682b
SM		 6813
6814 u8 syndrome[0x20];
6815
b4ff3a36 6816 u8 reserved_at_40[0x4];
e281682b
SM		 6817 u8 min_delay[0xc];
6818 u8 int_vector[0x10];
6819
b4ff3a36 6820 u8 reserved_at_60[0x20];
e281682b
SM		 6821};
6822
6823enum {
6824 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
6825 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
6826};
6827
6828struct mlx5_ifc_config_int_moderation_in_bits {
6829 u8 opcode[0x10];
b4ff3a36 6830 u8 reserved_at_10[0x10];
e281682b 6831
b4ff3a36 6832 u8 reserved_at_20[0x10];
e281682b
SM		 6833 u8 op_mod[0x10];
6834
b4ff3a36 6835 u8 reserved_at_40[0x4];
e281682b
SM		 6836 u8 min_delay[0xc];
6837 u8 int_vector[0x10];
6838
b4ff3a36 6839 u8 reserved_at_60[0x20];
e281682b
SM		 6840};
6841
6842struct mlx5_ifc_attach_to_mcg_out_bits {
6843 u8 status[0x8];
b4ff3a36 6844 u8 reserved_at_8[0x18];
e281682b
SM		 6845
6846 u8 syndrome[0x20];
6847
b4ff3a36 6848 u8 reserved_at_40[0x40];
e281682b
SM		 6849};
6850
6851struct mlx5_ifc_attach_to_mcg_in_bits {
6852 u8 opcode[0x10];
b4ff3a36 6853 u8 reserved_at_10[0x10];
e281682b 6854
b4ff3a36 6855 u8 reserved_at_20[0x10];
e281682b
SM		 6856 u8 op_mod[0x10];
6857
b4ff3a36 6858 u8 reserved_at_40[0x8];
e281682b
SM		 6859 u8 qpn[0x18];
6860
b4ff3a36 6861 u8 reserved_at_60[0x20];
e281682b
SM		 6862
6863 u8 multicast_gid[16][0x8];
6864};
6865
7486216b
SM		 6866struct mlx5_ifc_arm_xrq_out_bits {
6867 u8 status[0x8];
6868 u8 reserved_at_8[0x18];
6869
6870 u8 syndrome[0x20];
6871
6872 u8 reserved_at_40[0x40];
6873};
6874
6875struct mlx5_ifc_arm_xrq_in_bits {
6876 u8 opcode[0x10];
6877 u8 reserved_at_10[0x10];
6878
6879 u8 reserved_at_20[0x10];
6880 u8 op_mod[0x10];
6881
6882 u8 reserved_at_40[0x8];
6883 u8 xrqn[0x18];
6884
6885 u8 reserved_at_60[0x10];
6886 u8 lwm[0x10];
6887};
6888
e281682b
SM		 6889struct mlx5_ifc_arm_xrc_srq_out_bits {
6890 u8 status[0x8];
b4ff3a36 6891 u8 reserved_at_8[0x18];
e281682b
SM		 6892
6893 u8 syndrome[0x20];
6894
b4ff3a36 6895 u8 reserved_at_40[0x40];
e281682b
SM		 6896};
6897
6898enum {
6899 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
6900};
6901
6902struct mlx5_ifc_arm_xrc_srq_in_bits {
6903 u8 opcode[0x10];
b4ff3a36 6904 u8 reserved_at_10[0x10];
e281682b 6905
b4ff3a36 6906 u8 reserved_at_20[0x10];
e281682b
SM		 6907 u8 op_mod[0x10];
6908
b4ff3a36 6909 u8 reserved_at_40[0x8];
e281682b
SM		 6910 u8 xrc_srqn[0x18];
6911
b4ff3a36 6912 u8 reserved_at_60[0x10];
e281682b
SM		 6913 u8 lwm[0x10];
6914};
6915
6916struct mlx5_ifc_arm_rq_out_bits {
6917 u8 status[0x8];
b4ff3a36 6918 u8 reserved_at_8[0x18];
e281682b
SM		 6919
6920 u8 syndrome[0x20];
6921
b4ff3a36 6922 u8 reserved_at_40[0x40];
e281682b
SM		 6923};
6924
6925enum {
7486216b
SM		 6926 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
6927 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
e281682b
SM		 6928};
6929
6930struct mlx5_ifc_arm_rq_in_bits {
6931 u8 opcode[0x10];
b4ff3a36 6932 u8 reserved_at_10[0x10];
e281682b 6933
b4ff3a36 6934 u8 reserved_at_20[0x10];
e281682b
SM		 6935 u8 op_mod[0x10];
6936
b4ff3a36 6937 u8 reserved_at_40[0x8];
e281682b
SM		 6938 u8 srq_number[0x18];
6939
b4ff3a36 6940 u8 reserved_at_60[0x10];
e281682b
SM		 6941 u8 lwm[0x10];
6942};
6943
6944struct mlx5_ifc_arm_dct_out_bits {
6945 u8 status[0x8];
b4ff3a36 6946 u8 reserved_at_8[0x18];
e281682b
SM		 6947
6948 u8 syndrome[0x20];
6949
b4ff3a36 6950 u8 reserved_at_40[0x40];
e281682b
SM		 6951};
6952
6953struct mlx5_ifc_arm_dct_in_bits {
6954 u8 opcode[0x10];
b4ff3a36 6955 u8 reserved_at_10[0x10];
e281682b 6956
b4ff3a36 6957 u8 reserved_at_20[0x10];
e281682b
SM		 6958 u8 op_mod[0x10];
6959
b4ff3a36 6960 u8 reserved_at_40[0x8];
e281682b
SM		 6961 u8 dct_number[0x18];
6962
b4ff3a36 6963 u8 reserved_at_60[0x20];
e281682b
SM		 6964};
6965
6966struct mlx5_ifc_alloc_xrcd_out_bits {
6967 u8 status[0x8];
b4ff3a36 6968 u8 reserved_at_8[0x18];
e281682b
SM		 6969
6970 u8 syndrome[0x20];
6971
b4ff3a36 6972 u8 reserved_at_40[0x8];
e281682b
SM		 6973 u8 xrcd[0x18];
6974
b4ff3a36 6975 u8 reserved_at_60[0x20];
e281682b
SM		 6976};
6977
6978struct mlx5_ifc_alloc_xrcd_in_bits {
6979 u8 opcode[0x10];
b4ff3a36 6980 u8 reserved_at_10[0x10];
e281682b 6981
b4ff3a36 6982 u8 reserved_at_20[0x10];
e281682b
SM		 6983 u8 op_mod[0x10];
6984
b4ff3a36 6985 u8 reserved_at_40[0x40];
e281682b
SM		 6986};
6987
6988struct mlx5_ifc_alloc_uar_out_bits {
6989 u8 status[0x8];
b4ff3a36 6990 u8 reserved_at_8[0x18];
e281682b
SM		 6991
6992 u8 syndrome[0x20];
6993
b4ff3a36 6994 u8 reserved_at_40[0x8];
e281682b
SM		 6995 u8 uar[0x18];
6996
b4ff3a36 6997 u8 reserved_at_60[0x20];
e281682b
SM		 6998};
6999
7000struct mlx5_ifc_alloc_uar_in_bits {
7001 u8 opcode[0x10];
b4ff3a36 7002 u8 reserved_at_10[0x10];
e281682b 7003
b4ff3a36 7004 u8 reserved_at_20[0x10];
e281682b
SM		 7005 u8 op_mod[0x10];
7006
b4ff3a36 7007 u8 reserved_at_40[0x40];
e281682b
SM		 7008};
7009
7010struct mlx5_ifc_alloc_transport_domain_out_bits {
7011 u8 status[0x8];
b4ff3a36 7012 u8 reserved_at_8[0x18];
e281682b
SM		 7013
7014 u8 syndrome[0x20];
7015
b4ff3a36 7016 u8 reserved_at_40[0x8];
e281682b
SM		 7017 u8 transport_domain[0x18];
7018
b4ff3a36 7019 u8 reserved_at_60[0x20];
e281682b
SM		 7020};
7021
7022struct mlx5_ifc_alloc_transport_domain_in_bits {
7023 u8 opcode[0x10];
b4ff3a36 7024 u8 reserved_at_10[0x10];
e281682b 7025
b4ff3a36 7026 u8 reserved_at_20[0x10];
e281682b
SM		 7027 u8 op_mod[0x10];
7028
b4ff3a36 7029 u8 reserved_at_40[0x40];
e281682b
SM		 7030};
7031
7032struct mlx5_ifc_alloc_q_counter_out_bits {
7033 u8 status[0x8];
b4ff3a36 7034 u8 reserved_at_8[0x18];
e281682b
SM		 7035
7036 u8 syndrome[0x20];
7037
b4ff3a36 7038 u8 reserved_at_40[0x18];
e281682b
SM		 7039 u8 counter_set_id[0x8];
7040
b4ff3a36 7041 u8 reserved_at_60[0x20];
e281682b
SM		 7042};
7043
7044struct mlx5_ifc_alloc_q_counter_in_bits {
7045 u8 opcode[0x10];
b4ff3a36 7046 u8 reserved_at_10[0x10];
e281682b 7047
b4ff3a36 7048 u8 reserved_at_20[0x10];
e281682b
SM		 7049 u8 op_mod[0x10];
7050
b4ff3a36 7051 u8 reserved_at_40[0x40];
e281682b
SM		 7052};
7053
7054struct mlx5_ifc_alloc_pd_out_bits {
7055 u8 status[0x8];
b4ff3a36 7056 u8 reserved_at_8[0x18];
e281682b
SM		 7057
7058 u8 syndrome[0x20];
7059
b4ff3a36 7060 u8 reserved_at_40[0x8];
e281682b
SM		 7061 u8 pd[0x18];
7062
b4ff3a36 7063 u8 reserved_at_60[0x20];
e281682b
SM		 7064};
7065
7066struct mlx5_ifc_alloc_pd_in_bits {
9dc0b289
AV		 7067 u8 opcode[0x10];
7068 u8 reserved_at_10[0x10];
7069
7070 u8 reserved_at_20[0x10];
7071 u8 op_mod[0x10];
7072
7073 u8 reserved_at_40[0x40];
7074};
7075
7076struct mlx5_ifc_alloc_flow_counter_out_bits {
7077 u8 status[0x8];
7078 u8 reserved_at_8[0x18];
7079
7080 u8 syndrome[0x20];
7081
7082 u8 reserved_at_40[0x10];
7083 u8 flow_counter_id[0x10];
7084
7085 u8 reserved_at_60[0x20];
7086};
7087
7088struct mlx5_ifc_alloc_flow_counter_in_bits {
e281682b 7089 u8 opcode[0x10];
b4ff3a36 7090 u8 reserved_at_10[0x10];
e281682b 7091
b4ff3a36 7092 u8 reserved_at_20[0x10];
e281682b
SM		 7093 u8 op_mod[0x10];
7094
b4ff3a36 7095 u8 reserved_at_40[0x40];
e281682b
SM		 7096};
7097
7098struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7099 u8 status[0x8];
b4ff3a36 7100 u8 reserved_at_8[0x18];
e281682b
SM		 7101
7102 u8 syndrome[0x20];
7103
b4ff3a36 7104 u8 reserved_at_40[0x40];
e281682b
SM		 7105};
7106
7107struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7108 u8 opcode[0x10];
b4ff3a36 7109 u8 reserved_at_10[0x10];
e281682b 7110
b4ff3a36 7111 u8 reserved_at_20[0x10];
e281682b
SM		 7112 u8 op_mod[0x10];
7113
b4ff3a36 7114 u8 reserved_at_40[0x20];
e281682b 7115
b4ff3a36 7116 u8 reserved_at_60[0x10];
e281682b
SM		 7117 u8 vxlan_udp_port[0x10];
7118};
7119
7486216b
SM		 7120struct mlx5_ifc_set_rate_limit_out_bits {
7121 u8 status[0x8];
7122 u8 reserved_at_8[0x18];
7123
7124 u8 syndrome[0x20];
7125
7126 u8 reserved_at_40[0x40];
7127};
7128
7129struct mlx5_ifc_set_rate_limit_in_bits {
7130 u8 opcode[0x10];
7131 u8 reserved_at_10[0x10];
7132
7133 u8 reserved_at_20[0x10];
7134 u8 op_mod[0x10];
7135
7136 u8 reserved_at_40[0x10];
7137 u8 rate_limit_index[0x10];
7138
7139 u8 reserved_at_60[0x20];
7140
7141 u8 rate_limit[0x20];
7142};
7143
e281682b
SM		 7144struct mlx5_ifc_access_register_out_bits {
7145 u8 status[0x8];
b4ff3a36 7146 u8 reserved_at_8[0x18];
e281682b
SM		 7147
7148 u8 syndrome[0x20];
7149
b4ff3a36 7150 u8 reserved_at_40[0x40];
e281682b
SM		 7151
7152 u8 register_data[0][0x20];
7153};
7154
7155enum {
7156 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
7157 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
7158};
7159
7160struct mlx5_ifc_access_register_in_bits {
7161 u8 opcode[0x10];
b4ff3a36 7162 u8 reserved_at_10[0x10];
e281682b 7163
b4ff3a36 7164 u8 reserved_at_20[0x10];
e281682b
SM		 7165 u8 op_mod[0x10];
7166
b4ff3a36 7167 u8 reserved_at_40[0x10];
e281682b
SM		 7168 u8 register_id[0x10];
7169
7170 u8 argument[0x20];
7171
7172 u8 register_data[0][0x20];
7173};
7174
7175struct mlx5_ifc_sltp_reg_bits {
7176 u8 status[0x4];
7177 u8 version[0x4];
7178 u8 local_port[0x8];
7179 u8 pnat[0x2];
b4ff3a36 7180 u8 reserved_at_12[0x2];
e281682b 7181 u8 lane[0x4];
b4ff3a36 7182 u8 reserved_at_18[0x8];
e281682b 7183
b4ff3a36 7184 u8 reserved_at_20[0x20];
e281682b 7185
b4ff3a36 7186 u8 reserved_at_40[0x7];
e281682b
SM		 7187 u8 polarity[0x1];
7188 u8 ob_tap0[0x8];
7189 u8 ob_tap1[0x8];
7190 u8 ob_tap2[0x8];
7191
b4ff3a36 7192 u8 reserved_at_60[0xc];
e281682b
SM		 7193 u8 ob_preemp_mode[0x4];
7194 u8 ob_reg[0x8];
7195 u8 ob_bias[0x8];
7196
b4ff3a36 7197 u8 reserved_at_80[0x20];
e281682b
SM		 7198};
7199
7200struct mlx5_ifc_slrg_reg_bits {
7201 u8 status[0x4];
7202 u8 version[0x4];
7203 u8 local_port[0x8];
7204 u8 pnat[0x2];
b4ff3a36 7205 u8 reserved_at_12[0x2];
e281682b 7206 u8 lane[0x4];
b4ff3a36 7207 u8 reserved_at_18[0x8];
e281682b
SM		 7208
7209 u8 time_to_link_up[0x10];
b4ff3a36 7210 u8 reserved_at_30[0xc];
e281682b
SM		 7211 u8 grade_lane_speed[0x4];
7212
7213 u8 grade_version[0x8];
7214 u8 grade[0x18];
7215
b4ff3a36 7216 u8 reserved_at_60[0x4];
e281682b
SM		 7217 u8 height_grade_type[0x4];
7218 u8 height_grade[0x18];
7219
7220 u8 height_dz[0x10];
7221 u8 height_dv[0x10];
7222
b4ff3a36 7223 u8 reserved_at_a0[0x10];
e281682b
SM		 7224 u8 height_sigma[0x10];
7225
b4ff3a36 7226 u8 reserved_at_c0[0x20];
e281682b 7227
b4ff3a36 7228 u8 reserved_at_e0[0x4];
e281682b
SM		 7229 u8 phase_grade_type[0x4];
7230 u8 phase_grade[0x18];
7231
b4ff3a36 7232 u8 reserved_at_100[0x8];
e281682b 7233 u8 phase_eo_pos[0x8];
b4ff3a36 7234 u8 reserved_at_110[0x8];
e281682b
SM		 7235 u8 phase_eo_neg[0x8];
7236
7237 u8 ffe_set_tested[0x10];
7238 u8 test_errors_per_lane[0x10];
7239};
7240
7241struct mlx5_ifc_pvlc_reg_bits {
b4ff3a36 7242 u8 reserved_at_0[0x8];
e281682b 7243 u8 local_port[0x8];
b4ff3a36 7244 u8 reserved_at_10[0x10];
e281682b 7245
b4ff3a36 7246 u8 reserved_at_20[0x1c];
e281682b
SM		 7247 u8 vl_hw_cap[0x4];
7248
b4ff3a36 7249 u8 reserved_at_40[0x1c];
e281682b
SM		 7250 u8 vl_admin[0x4];
7251
b4ff3a36 7252 u8 reserved_at_60[0x1c];
e281682b
SM		 7253 u8 vl_operational[0x4];
7254};
7255
7256struct mlx5_ifc_pude_reg_bits {
7257 u8 swid[0x8];
7258 u8 local_port[0x8];
b4ff3a36 7259 u8 reserved_at_10[0x4];
e281682b 7260 u8 admin_status[0x4];
b4ff3a36 7261 u8 reserved_at_18[0x4];
e281682b
SM		 7262 u8 oper_status[0x4];
7263
b4ff3a36 7264 u8 reserved_at_20[0x60];
e281682b
SM		 7265};
7266
7267struct mlx5_ifc_ptys_reg_bits {
e7e31ca4 7268 u8 reserved_at_0[0x1];
7486216b 7269 u8 an_disable_admin[0x1];
e7e31ca4
BW		 7270 u8 an_disable_cap[0x1];
7271 u8 reserved_at_3[0x5];
e281682b 7272 u8 local_port[0x8];
b4ff3a36 7273 u8 reserved_at_10[0xd];
e281682b
SM		 7274 u8 proto_mask[0x3];
7275
7486216b
SM		 7276 u8 an_status[0x4];
7277 u8 reserved_at_24[0x3c];
e281682b
SM		 7278
7279 u8 eth_proto_capability[0x20];
7280
7281 u8 ib_link_width_capability[0x10];
7282 u8 ib_proto_capability[0x10];
7283
b4ff3a36 7284 u8 reserved_at_a0[0x20];
e281682b
SM		 7285
7286 u8 eth_proto_admin[0x20];
7287
7288 u8 ib_link_width_admin[0x10];
7289 u8 ib_proto_admin[0x10];
7290
b4ff3a36 7291 u8 reserved_at_100[0x20];
e281682b
SM		 7292
7293 u8 eth_proto_oper[0x20];
7294
7295 u8 ib_link_width_oper[0x10];
7296 u8 ib_proto_oper[0x10];
7297
5b4793f8
EBE		 7298 u8 reserved_at_160[0x1c];
7299 u8 connector_type[0x4];
e281682b
SM		 7300
7301 u8 eth_proto_lp_advertise[0x20];
7302
b4ff3a36 7303 u8 reserved_at_1a0[0x60];
e281682b
SM		 7304};
7305
7d5e1423
SM		 7306struct mlx5_ifc_mlcr_reg_bits {
7307 u8 reserved_at_0[0x8];
7308 u8 local_port[0x8];
7309 u8 reserved_at_10[0x20];
7310
7311 u8 beacon_duration[0x10];
7312 u8 reserved_at_40[0x10];
7313
7314 u8 beacon_remain[0x10];
7315};
7316
e281682b 7317struct mlx5_ifc_ptas_reg_bits {
b4ff3a36 7318 u8 reserved_at_0[0x20];
e281682b
SM		 7319
7320 u8 algorithm_options[0x10];
b4ff3a36 7321 u8 reserved_at_30[0x4];
e281682b
SM		 7322 u8 repetitions_mode[0x4];
7323 u8 num_of_repetitions[0x8];
7324
7325 u8 grade_version[0x8];
7326 u8 height_grade_type[0x4];
7327 u8 phase_grade_type[0x4];
7328 u8 height_grade_weight[0x8];
7329 u8 phase_grade_weight[0x8];
7330
7331 u8 gisim_measure_bits[0x10];
7332 u8 adaptive_tap_measure_bits[0x10];
7333
7334 u8 ber_bath_high_error_threshold[0x10];
7335 u8 ber_bath_mid_error_threshold[0x10];
7336
7337 u8 ber_bath_low_error_threshold[0x10];
7338 u8 one_ratio_high_threshold[0x10];
7339
7340 u8 one_ratio_high_mid_threshold[0x10];
7341 u8 one_ratio_low_mid_threshold[0x10];
7342
7343 u8 one_ratio_low_threshold[0x10];
7344 u8 ndeo_error_threshold[0x10];
7345
7346 u8 mixer_offset_step_size[0x10];
b4ff3a36 7347 u8 reserved_at_110[0x8];
e281682b
SM		 7348 u8 mix90_phase_for_voltage_bath[0x8];
7349
7350 u8 mixer_offset_start[0x10];
7351 u8 mixer_offset_end[0x10];
7352
b4ff3a36 7353 u8 reserved_at_140[0x15];
e281682b
SM		 7354 u8 ber_test_time[0xb];
7355};
7356
7357struct mlx5_ifc_pspa_reg_bits {
7358 u8 swid[0x8];
7359 u8 local_port[0x8];
7360 u8 sub_port[0x8];
b4ff3a36 7361 u8 reserved_at_18[0x8];
e281682b 7362
b4ff3a36 7363 u8 reserved_at_20[0x20];
e281682b
SM		 7364};
7365
7366struct mlx5_ifc_pqdr_reg_bits {
b4ff3a36 7367 u8 reserved_at_0[0x8];
e281682b 7368 u8 local_port[0x8];
b4ff3a36 7369 u8 reserved_at_10[0x5];
e281682b 7370 u8 prio[0x3];
b4ff3a36 7371 u8 reserved_at_18[0x6];
e281682b
SM		 7372 u8 mode[0x2];
7373
b4ff3a36 7374 u8 reserved_at_20[0x20];
e281682b 7375
b4ff3a36 7376 u8 reserved_at_40[0x10];
e281682b
SM		 7377 u8 min_threshold[0x10];
7378
b4ff3a36 7379 u8 reserved_at_60[0x10];
e281682b
SM		 7380 u8 max_threshold[0x10];
7381
b4ff3a36 7382 u8 reserved_at_80[0x10];
e281682b
SM		 7383 u8 mark_probability_denominator[0x10];
7384
b4ff3a36 7385 u8 reserved_at_a0[0x60];
e281682b
SM		 7386};
7387
7388struct mlx5_ifc_ppsc_reg_bits {
b4ff3a36 7389 u8 reserved_at_0[0x8];
e281682b 7390 u8 local_port[0x8];
b4ff3a36 7391 u8 reserved_at_10[0x10];
e281682b 7392
b4ff3a36 7393 u8 reserved_at_20[0x60];
e281682b 7394
b4ff3a36 7395 u8 reserved_at_80[0x1c];
e281682b
SM		 7396 u8 wrps_admin[0x4];
7397
b4ff3a36 7398 u8 reserved_at_a0[0x1c];
e281682b
SM		 7399 u8 wrps_status[0x4];
7400
b4ff3a36 7401 u8 reserved_at_c0[0x8];
e281682b 7402 u8 up_threshold[0x8];
b4ff3a36 7403 u8 reserved_at_d0[0x8];
e281682b
SM		 7404 u8 down_threshold[0x8];
7405
b4ff3a36 7406 u8 reserved_at_e0[0x20];
e281682b 7407
b4ff3a36 7408 u8 reserved_at_100[0x1c];
e281682b
SM		 7409 u8 srps_admin[0x4];
7410
b4ff3a36 7411 u8 reserved_at_120[0x1c];
e281682b
SM		 7412 u8 srps_status[0x4];
7413
b4ff3a36 7414 u8 reserved_at_140[0x40];
e281682b
SM		 7415};
7416
7417struct mlx5_ifc_pplr_reg_bits {
b4ff3a36 7418 u8 reserved_at_0[0x8];
e281682b 7419 u8 local_port[0x8];
b4ff3a36 7420 u8 reserved_at_10[0x10];
e281682b 7421
b4ff3a36 7422 u8 reserved_at_20[0x8];
e281682b 7423 u8 lb_cap[0x8];
b4ff3a36 7424 u8 reserved_at_30[0x8];
e281682b
SM		 7425 u8 lb_en[0x8];
7426};
7427
7428struct mlx5_ifc_pplm_reg_bits {
b4ff3a36 7429 u8 reserved_at_0[0x8];
e281682b 7430 u8 local_port[0x8];
b4ff3a36 7431 u8 reserved_at_10[0x10];
e281682b 7432
b4ff3a36 7433 u8 reserved_at_20[0x20];
e281682b
SM		 7434
7435 u8 port_profile_mode[0x8];
7436 u8 static_port_profile[0x8];
7437 u8 active_port_profile[0x8];
b4ff3a36 7438 u8 reserved_at_58[0x8];
e281682b
SM		 7439
7440 u8 retransmission_active[0x8];
7441 u8 fec_mode_active[0x18];
7442
b4ff3a36 7443 u8 reserved_at_80[0x20];
e281682b
SM		 7444};
7445
7446struct mlx5_ifc_ppcnt_reg_bits {
7447 u8 swid[0x8];
7448 u8 local_port[0x8];
7449 u8 pnat[0x2];
b4ff3a36 7450 u8 reserved_at_12[0x8];
e281682b
SM		 7451 u8 grp[0x6];
7452
7453 u8 clr[0x1];
b4ff3a36 7454 u8 reserved_at_21[0x1c];
e281682b
SM		 7455 u8 prio_tc[0x3];
7456
7457 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
7458};
7459
8ed1a630
GP		 7460struct mlx5_ifc_mpcnt_reg_bits {
7461 u8 reserved_at_0[0x8];
7462 u8 pcie_index[0x8];
7463 u8 reserved_at_10[0xa];
7464 u8 grp[0x6];
7465
7466 u8 clr[0x1];
7467 u8 reserved_at_21[0x1f];
7468
7469 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
7470};
7471
e281682b 7472struct mlx5_ifc_ppad_reg_bits {
b4ff3a36 7473 u8 reserved_at_0[0x3];
e281682b 7474 u8 single_mac[0x1];
b4ff3a36 7475 u8 reserved_at_4[0x4];
e281682b
SM		 7476 u8 local_port[0x8];
7477 u8 mac_47_32[0x10];
7478
7479 u8 mac_31_0[0x20];
7480
b4ff3a36 7481 u8 reserved_at_40[0x40];
e281682b
SM		 7482};
7483
7484struct mlx5_ifc_pmtu_reg_bits {
b4ff3a36 7485 u8 reserved_at_0[0x8];
e281682b 7486 u8 local_port[0x8];
b4ff3a36 7487 u8 reserved_at_10[0x10];
e281682b
SM		 7488
7489 u8 max_mtu[0x10];
b4ff3a36 7490 u8 reserved_at_30[0x10];
e281682b
SM		 7491
7492 u8 admin_mtu[0x10];
b4ff3a36 7493 u8 reserved_at_50[0x10];
e281682b
SM		 7494
7495 u8 oper_mtu[0x10];
b4ff3a36 7496 u8 reserved_at_70[0x10];
e281682b
SM		 7497};
7498
7499struct mlx5_ifc_pmpr_reg_bits {
b4ff3a36 7500 u8 reserved_at_0[0x8];
e281682b 7501 u8 module[0x8];
b4ff3a36 7502 u8 reserved_at_10[0x10];
e281682b 7503
b4ff3a36 7504 u8 reserved_at_20[0x18];
e281682b
SM		 7505 u8 attenuation_5g[0x8];
7506
b4ff3a36 7507 u8 reserved_at_40[0x18];
e281682b
SM		 7508 u8 attenuation_7g[0x8];
7509
b4ff3a36 7510 u8 reserved_at_60[0x18];
e281682b
SM		 7511 u8 attenuation_12g[0x8];
7512};
7513
7514struct mlx5_ifc_pmpe_reg_bits {
b4ff3a36 7515 u8 reserved_at_0[0x8];
e281682b 7516 u8 module[0x8];
b4ff3a36 7517 u8 reserved_at_10[0xc];
e281682b
SM		 7518 u8 module_status[0x4];
7519
b4ff3a36 7520 u8 reserved_at_20[0x60];
e281682b
SM		 7521};
7522
7523struct mlx5_ifc_pmpc_reg_bits {
7524 u8 module_state_updated[32][0x8];
7525};
7526
7527struct mlx5_ifc_pmlpn_reg_bits {
b4ff3a36 7528 u8 reserved_at_0[0x4];
e281682b
SM		 7529 u8 mlpn_status[0x4];
7530 u8 local_port[0x8];
b4ff3a36 7531 u8 reserved_at_10[0x10];
e281682b
SM		 7532
7533 u8 e[0x1];
b4ff3a36 7534 u8 reserved_at_21[0x1f];
e281682b
SM		 7535};
7536
7537struct mlx5_ifc_pmlp_reg_bits {
7538 u8 rxtx[0x1];
b4ff3a36 7539 u8 reserved_at_1[0x7];
e281682b 7540 u8 local_port[0x8];
b4ff3a36 7541 u8 reserved_at_10[0x8];
e281682b
SM		 7542 u8 width[0x8];
7543
7544 u8 lane0_module_mapping[0x20];
7545
7546 u8 lane1_module_mapping[0x20];
7547
7548 u8 lane2_module_mapping[0x20];
7549
7550 u8 lane3_module_mapping[0x20];
7551
b4ff3a36 7552 u8 reserved_at_a0[0x160];
e281682b
SM		 7553};
7554
7555struct mlx5_ifc_pmaos_reg_bits {
b4ff3a36 7556 u8 reserved_at_0[0x8];
e281682b 7557 u8 module[0x8];
b4ff3a36 7558 u8 reserved_at_10[0x4];
e281682b 7559 u8 admin_status[0x4];
b4ff3a36 7560 u8 reserved_at_18[0x4];
e281682b
SM		 7561 u8 oper_status[0x4];
7562
7563 u8 ase[0x1];
7564 u8 ee[0x1];
b4ff3a36 7565 u8 reserved_at_22[0x1c];
e281682b
SM		 7566 u8 e[0x2];
7567
b4ff3a36 7568 u8 reserved_at_40[0x40];
e281682b
SM		 7569};
7570
7571struct mlx5_ifc_plpc_reg_bits {
b4ff3a36 7572 u8 reserved_at_0[0x4];
e281682b 7573 u8 profile_id[0xc];
b4ff3a36 7574 u8 reserved_at_10[0x4];
e281682b 7575 u8 proto_mask[0x4];
b4ff3a36 7576 u8 reserved_at_18[0x8];
e281682b 7577
b4ff3a36 7578 u8 reserved_at_20[0x10];
e281682b
SM		 7579 u8 lane_speed[0x10];
7580
b4ff3a36 7581 u8 reserved_at_40[0x17];
e281682b
SM		 7582 u8 lpbf[0x1];
7583 u8 fec_mode_policy[0x8];
7584
7585 u8 retransmission_capability[0x8];
7586 u8 fec_mode_capability[0x18];
7587
7588 u8 retransmission_support_admin[0x8];
7589 u8 fec_mode_support_admin[0x18];
7590
7591 u8 retransmission_request_admin[0x8];
7592 u8 fec_mode_request_admin[0x18];
7593
b4ff3a36 7594 u8 reserved_at_c0[0x80];
e281682b
SM		 7595};
7596
7597struct mlx5_ifc_plib_reg_bits {
b4ff3a36 7598 u8 reserved_at_0[0x8];
e281682b 7599 u8 local_port[0x8];
b4ff3a36 7600 u8 reserved_at_10[0x8];
e281682b
SM		 7601 u8 ib_port[0x8];
7602
b4ff3a36 7603 u8 reserved_at_20[0x60];
e281682b
SM		 7604};
7605
7606struct mlx5_ifc_plbf_reg_bits {
b4ff3a36 7607 u8 reserved_at_0[0x8];
e281682b 7608 u8 local_port[0x8];
b4ff3a36 7609 u8 reserved_at_10[0xd];
e281682b
SM		 7610 u8 lbf_mode[0x3];
7611
b4ff3a36 7612 u8 reserved_at_20[0x20];
e281682b
SM		 7613};
7614
7615struct mlx5_ifc_pipg_reg_bits {
b4ff3a36 7616 u8 reserved_at_0[0x8];
e281682b 7617 u8 local_port[0x8];
b4ff3a36 7618 u8 reserved_at_10[0x10];
e281682b
SM		 7619
7620 u8 dic[0x1];
b4ff3a36 7621 u8 reserved_at_21[0x19];
e281682b 7622 u8 ipg[0x4];
b4ff3a36 7623 u8 reserved_at_3e[0x2];
e281682b
SM		 7624};
7625
7626struct mlx5_ifc_pifr_reg_bits {
b4ff3a36 7627 u8 reserved_at_0[0x8];
e281682b 7628 u8 local_port[0x8];
b4ff3a36 7629 u8 reserved_at_10[0x10];
e281682b 7630
b4ff3a36 7631 u8 reserved_at_20[0xe0];
e281682b
SM		 7632
7633 u8 port_filter[8][0x20];
7634
7635 u8 port_filter_update_en[8][0x20];
7636};
7637
7638struct mlx5_ifc_pfcc_reg_bits {
b4ff3a36 7639 u8 reserved_at_0[0x8];
e281682b 7640 u8 local_port[0x8];
b4ff3a36 7641 u8 reserved_at_10[0x10];
e281682b
SM		 7642
7643 u8 ppan[0x4];
b4ff3a36 7644 u8 reserved_at_24[0x4];
e281682b 7645 u8 prio_mask_tx[0x8];
b4ff3a36 7646 u8 reserved_at_30[0x8];
e281682b
SM		 7647 u8 prio_mask_rx[0x8];
7648
7649 u8 pptx[0x1];
7650 u8 aptx[0x1];
b4ff3a36 7651 u8 reserved_at_42[0x6];
e281682b 7652 u8 pfctx[0x8];
b4ff3a36 7653 u8 reserved_at_50[0x10];
e281682b
SM		 7654
7655 u8 pprx[0x1];
7656 u8 aprx[0x1];
b4ff3a36 7657 u8 reserved_at_62[0x6];
e281682b 7658 u8 pfcrx[0x8];
b4ff3a36 7659 u8 reserved_at_70[0x10];
e281682b 7660
b4ff3a36 7661 u8 reserved_at_80[0x80];
e281682b
SM		 7662};
7663
7664struct mlx5_ifc_pelc_reg_bits {
7665 u8 op[0x4];
b4ff3a36 7666 u8 reserved_at_4[0x4];
e281682b 7667 u8 local_port[0x8];
b4ff3a36 7668 u8 reserved_at_10[0x10];
e281682b
SM		 7669
7670 u8 op_admin[0x8];
7671 u8 op_capability[0x8];
7672 u8 op_request[0x8];
7673 u8 op_active[0x8];
7674
7675 u8 admin[0x40];
7676
7677 u8 capability[0x40];
7678
7679 u8 request[0x40];
7680
7681 u8 active[0x40];
7682
b4ff3a36 7683 u8 reserved_at_140[0x80];
e281682b
SM		 7684};
7685
7686struct mlx5_ifc_peir_reg_bits {
b4ff3a36 7687 u8 reserved_at_0[0x8];
e281682b 7688 u8 local_port[0x8];
b4ff3a36 7689 u8 reserved_at_10[0x10];
e281682b 7690
b4ff3a36 7691 u8 reserved_at_20[0xc];
e281682b 7692 u8 error_count[0x4];
b4ff3a36 7693 u8 reserved_at_30[0x10];
e281682b 7694
b4ff3a36 7695 u8 reserved_at_40[0xc];
e281682b 7696 u8 lane[0x4];
b4ff3a36 7697 u8 reserved_at_50[0x8];
e281682b
SM		 7698 u8 error_type[0x8];
7699};
7700
cfdcbcea 7701struct mlx5_ifc_pcam_enhanced_features_bits {
5b4793f8 7702 u8 reserved_at_0[0x7c];
cfdcbcea 7703
5b4793f8
EBE		 7704 u8 ptys_connector_type[0x1];
7705 u8 reserved_at_7d[0x1];
cfdcbcea
GP		 7706 u8 ppcnt_discard_group[0x1];
7707 u8 ppcnt_statistical_group[0x1];
7708};
7709
7710struct mlx5_ifc_pcam_reg_bits {
7711 u8 reserved_at_0[0x8];
7712 u8 feature_group[0x8];
7713 u8 reserved_at_10[0x8];
7714 u8 access_reg_group[0x8];
7715
7716 u8 reserved_at_20[0x20];
7717
7718 union {
7719 u8 reserved_at_0[0x80];
7720 } port_access_reg_cap_mask;
7721
7722 u8 reserved_at_c0[0x80];
7723
7724 union {
7725 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
7726 u8 reserved_at_0[0x80];
7727 } feature_cap_mask;
7728
7729 u8 reserved_at_1c0[0xc0];
7730};
7731
7732struct mlx5_ifc_mcam_enhanced_features_bits {
7733 u8 reserved_at_0[0x7f];
7734
7735 u8 pcie_performance_group[0x1];
7736};
7737
7738struct mlx5_ifc_mcam_reg_bits {
7739 u8 reserved_at_0[0x8];
7740 u8 feature_group[0x8];
7741 u8 reserved_at_10[0x8];
7742 u8 access_reg_group[0x8];
7743
7744 u8 reserved_at_20[0x20];
7745
7746 union {
7747 u8 reserved_at_0[0x80];
7748 } mng_access_reg_cap_mask;
7749
7750 u8 reserved_at_c0[0x80];
7751
7752 union {
7753 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
7754 u8 reserved_at_0[0x80];
7755 } mng_feature_cap_mask;
7756
7757 u8 reserved_at_1c0[0x80];
7758};
7759
e281682b 7760struct mlx5_ifc_pcap_reg_bits {
b4ff3a36 7761 u8 reserved_at_0[0x8];
e281682b 7762 u8 local_port[0x8];
b4ff3a36 7763 u8 reserved_at_10[0x10];
e281682b
SM		 7764
7765 u8 port_capability_mask[4][0x20];
7766};
7767
7768struct mlx5_ifc_paos_reg_bits {
7769 u8 swid[0x8];
7770 u8 local_port[0x8];
b4ff3a36 7771 u8 reserved_at_10[0x4];
e281682b 7772 u8 admin_status[0x4];
b4ff3a36 7773 u8 reserved_at_18[0x4];
e281682b
SM		 7774 u8 oper_status[0x4];
7775
7776 u8 ase[0x1];
7777 u8 ee[0x1];
b4ff3a36 7778 u8 reserved_at_22[0x1c];
e281682b
SM		 7779 u8 e[0x2];
7780
b4ff3a36 7781 u8 reserved_at_40[0x40];
e281682b
SM		 7782};
7783
7784struct mlx5_ifc_pamp_reg_bits {
b4ff3a36 7785 u8 reserved_at_0[0x8];
e281682b 7786 u8 opamp_group[0x8];
b4ff3a36 7787 u8 reserved_at_10[0xc];
e281682b
SM		 7788 u8 opamp_group_type[0x4];
7789
7790 u8 start_index[0x10];
b4ff3a36 7791 u8 reserved_at_30[0x4];
e281682b
SM		 7792 u8 num_of_indices[0xc];
7793
7794 u8 index_data[18][0x10];
7795};
7796
7d5e1423
SM		 7797struct mlx5_ifc_pcmr_reg_bits {
7798 u8 reserved_at_0[0x8];
7799 u8 local_port[0x8];
7800 u8 reserved_at_10[0x2e];
7801 u8 fcs_cap[0x1];
7802 u8 reserved_at_3f[0x1f];
7803 u8 fcs_chk[0x1];
7804 u8 reserved_at_5f[0x1];
7805};
7806
e281682b 7807struct mlx5_ifc_lane_2_module_mapping_bits {
b4ff3a36 7808 u8 reserved_at_0[0x6];
e281682b 7809 u8 rx_lane[0x2];
b4ff3a36 7810 u8 reserved_at_8[0x6];
e281682b 7811 u8 tx_lane[0x2];
b4ff3a36 7812 u8 reserved_at_10[0x8];
e281682b
SM		 7813 u8 module[0x8];
7814};
7815
7816struct mlx5_ifc_bufferx_reg_bits {
b4ff3a36 7817 u8 reserved_at_0[0x6];
e281682b
SM		 7818 u8 lossy[0x1];
7819 u8 epsb[0x1];
b4ff3a36 7820 u8 reserved_at_8[0xc];
e281682b
SM		 7821 u8 size[0xc];
7822
7823 u8 xoff_threshold[0x10];
7824 u8 xon_threshold[0x10];
7825};
7826
7827struct mlx5_ifc_set_node_in_bits {
7828 u8 node_description[64][0x8];
7829};
7830
7831struct mlx5_ifc_register_power_settings_bits {
b4ff3a36 7832 u8 reserved_at_0[0x18];
e281682b
SM		 7833 u8 power_settings_level[0x8];
7834
b4ff3a36 7835 u8 reserved_at_20[0x60];
e281682b
SM		 7836};
7837
7838struct mlx5_ifc_register_host_endianness_bits {
7839 u8 he[0x1];
b4ff3a36 7840 u8 reserved_at_1[0x1f];
e281682b 7841
b4ff3a36 7842 u8 reserved_at_20[0x60];
e281682b
SM		 7843};
7844
7845struct mlx5_ifc_umr_pointer_desc_argument_bits {
b4ff3a36 7846 u8 reserved_at_0[0x20];
e281682b
SM		 7847
7848 u8 mkey[0x20];
7849
7850 u8 addressh_63_32[0x20];
7851
7852 u8 addressl_31_0[0x20];
7853};
7854
7855struct mlx5_ifc_ud_adrs_vector_bits {
7856 u8 dc_key[0x40];
7857
7858 u8 ext[0x1];
b4ff3a36 7859 u8 reserved_at_41[0x7];
e281682b
SM		 7860 u8 destination_qp_dct[0x18];
7861
7862 u8 static_rate[0x4];
7863 u8 sl_eth_prio[0x4];
7864 u8 fl[0x1];
7865 u8 mlid[0x7];
7866 u8 rlid_udp_sport[0x10];
7867
b4ff3a36 7868 u8 reserved_at_80[0x20];
e281682b
SM		 7869
7870 u8 rmac_47_16[0x20];
7871
7872 u8 rmac_15_0[0x10];
7873 u8 tclass[0x8];
7874 u8 hop_limit[0x8];
7875
b4ff3a36 7876 u8 reserved_at_e0[0x1];
e281682b 7877 u8 grh[0x1];
b4ff3a36 7878 u8 reserved_at_e2[0x2];
e281682b
SM		 7879 u8 src_addr_index[0x8];
7880 u8 flow_label[0x14];
7881
7882 u8 rgid_rip[16][0x8];
7883};
7884
7885struct mlx5_ifc_pages_req_event_bits {
b4ff3a36 7886 u8 reserved_at_0[0x10];
e281682b
SM		 7887 u8 function_id[0x10];
7888
7889 u8 num_pages[0x20];
7890
b4ff3a36 7891 u8 reserved_at_40[0xa0];
e281682b
SM		 7892};
7893
7894struct mlx5_ifc_eqe_bits {
b4ff3a36 7895 u8 reserved_at_0[0x8];
e281682b 7896 u8 event_type[0x8];
b4ff3a36 7897 u8 reserved_at_10[0x8];
e281682b
SM		 7898 u8 event_sub_type[0x8];
7899
b4ff3a36 7900 u8 reserved_at_20[0xe0];
e281682b
SM		 7901
7902 union mlx5_ifc_event_auto_bits event_data;
7903
b4ff3a36 7904 u8 reserved_at_1e0[0x10];
e281682b 7905 u8 signature[0x8];
b4ff3a36 7906 u8 reserved_at_1f8[0x7];
e281682b
SM		 7907 u8 owner[0x1];
7908};
7909
7910enum {
7911 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
7912};
7913
7914struct mlx5_ifc_cmd_queue_entry_bits {
7915 u8 type[0x8];
b4ff3a36 7916 u8 reserved_at_8[0x18];
e281682b
SM		 7917
7918 u8 input_length[0x20];
7919
7920 u8 input_mailbox_pointer_63_32[0x20];
7921
7922 u8 input_mailbox_pointer_31_9[0x17];
b4ff3a36 7923 u8 reserved_at_77[0x9];
e281682b
SM		 7924
7925 u8 command_input_inline_data[16][0x8];
7926
7927 u8 command_output_inline_data[16][0x8];
7928
7929 u8 output_mailbox_pointer_63_32[0x20];
7930
7931 u8 output_mailbox_pointer_31_9[0x17];
b4ff3a36 7932 u8 reserved_at_1b7[0x9];
e281682b
SM		 7933
7934 u8 output_length[0x20];
7935
7936 u8 token[0x8];
7937 u8 signature[0x8];
b4ff3a36 7938 u8 reserved_at_1f0[0x8];
e281682b
SM		 7939 u8 status[0x7];
7940 u8 ownership[0x1];
7941};
7942
7943struct mlx5_ifc_cmd_out_bits {
7944 u8 status[0x8];
b4ff3a36 7945 u8 reserved_at_8[0x18];
e281682b
SM		 7946
7947 u8 syndrome[0x20];
7948
7949 u8 command_output[0x20];
7950};
7951
7952struct mlx5_ifc_cmd_in_bits {
7953 u8 opcode[0x10];
b4ff3a36 7954 u8 reserved_at_10[0x10];
e281682b 7955
b4ff3a36 7956 u8 reserved_at_20[0x10];
e281682b
SM		 7957 u8 op_mod[0x10];
7958
7959 u8 command[0][0x20];
7960};
7961
7962struct mlx5_ifc_cmd_if_box_bits {
7963 u8 mailbox_data[512][0x8];
7964
b4ff3a36 7965 u8 reserved_at_1000[0x180];
e281682b
SM		 7966
7967 u8 next_pointer_63_32[0x20];
7968
7969 u8 next_pointer_31_10[0x16];
b4ff3a36 7970 u8 reserved_at_11b6[0xa];
e281682b
SM		 7971
7972 u8 block_number[0x20];
7973
b4ff3a36 7974 u8 reserved_at_11e0[0x8];
e281682b
SM		 7975 u8 token[0x8];
7976 u8 ctrl_signature[0x8];
7977 u8 signature[0x8];
7978};
7979
7980struct mlx5_ifc_mtt_bits {
7981 u8 ptag_63_32[0x20];
7982
7983 u8 ptag_31_8[0x18];
b4ff3a36 7984 u8 reserved_at_38[0x6];
e281682b
SM		 7985 u8 wr_en[0x1];
7986 u8 rd_en[0x1];
7987};
7988
928cfe87
TT		 7989struct mlx5_ifc_query_wol_rol_out_bits {
7990 u8 status[0x8];
7991 u8 reserved_at_8[0x18];
7992
7993 u8 syndrome[0x20];
7994
7995 u8 reserved_at_40[0x10];
7996 u8 rol_mode[0x8];
7997 u8 wol_mode[0x8];
7998
7999 u8 reserved_at_60[0x20];
8000};
8001
8002struct mlx5_ifc_query_wol_rol_in_bits {
8003 u8 opcode[0x10];
8004 u8 reserved_at_10[0x10];
8005
8006 u8 reserved_at_20[0x10];
8007 u8 op_mod[0x10];
8008
8009 u8 reserved_at_40[0x40];
8010};
8011
8012struct mlx5_ifc_set_wol_rol_out_bits {
8013 u8 status[0x8];
8014 u8 reserved_at_8[0x18];
8015
8016 u8 syndrome[0x20];
8017
8018 u8 reserved_at_40[0x40];
8019};
8020
8021struct mlx5_ifc_set_wol_rol_in_bits {
8022 u8 opcode[0x10];
8023 u8 reserved_at_10[0x10];
8024
8025 u8 reserved_at_20[0x10];
8026 u8 op_mod[0x10];
8027
8028 u8 rol_mode_valid[0x1];
8029 u8 wol_mode_valid[0x1];
8030 u8 reserved_at_42[0xe];
8031 u8 rol_mode[0x8];
8032 u8 wol_mode[0x8];
8033
8034 u8 reserved_at_60[0x20];
8035};
8036
e281682b
SM		 8037enum {
8038 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
8039 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
8040 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
8041};
8042
8043enum {
8044 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
8045 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
8046 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
8047};
8048
8049enum {
8050 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
8051 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
8052 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
8053 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
8054 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
8055 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
8056 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
8057 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
8058 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
8059 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
8060 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
8061};
8062
8063struct mlx5_ifc_initial_seg_bits {
8064 u8 fw_rev_minor[0x10];
8065 u8 fw_rev_major[0x10];
8066
8067 u8 cmd_interface_rev[0x10];
8068 u8 fw_rev_subminor[0x10];
8069
b4ff3a36 8070 u8 reserved_at_40[0x40];
e281682b
SM		 8071
8072 u8 cmdq_phy_addr_63_32[0x20];
8073
8074 u8 cmdq_phy_addr_31_12[0x14];
b4ff3a36 8075 u8 reserved_at_b4[0x2];
e281682b
SM		 8076 u8 nic_interface[0x2];
8077 u8 log_cmdq_size[0x4];
8078 u8 log_cmdq_stride[0x4];
8079
8080 u8 command_doorbell_vector[0x20];
8081
b4ff3a36 8082 u8 reserved_at_e0[0xf00];
e281682b
SM		 8083
8084 u8 initializing[0x1];
b4ff3a36 8085 u8 reserved_at_fe1[0x4];
e281682b 8086 u8 nic_interface_supported[0x3];
b4ff3a36 8087 u8 reserved_at_fe8[0x18];
e281682b
SM		 8088
8089 struct mlx5_ifc_health_buffer_bits health_buffer;
8090
8091 u8 no_dram_nic_offset[0x20];
8092
b4ff3a36 8093 u8 reserved_at_1220[0x6e40];
e281682b 8094
b4ff3a36 8095 u8 reserved_at_8060[0x1f];
e281682b
SM		 8096 u8 clear_int[0x1];
8097
8098 u8 health_syndrome[0x8];
8099 u8 health_counter[0x18];
8100
b4ff3a36 8101 u8 reserved_at_80a0[0x17fc0];
e281682b
SM		 8102};
8103
f9a1ef72
EE		 8104struct mlx5_ifc_mtpps_reg_bits {
8105 u8 reserved_at_0[0xc];
8106 u8 cap_number_of_pps_pins[0x4];
8107 u8 reserved_at_10[0x4];
8108 u8 cap_max_num_of_pps_in_pins[0x4];
8109 u8 reserved_at_18[0x4];
8110 u8 cap_max_num_of_pps_out_pins[0x4];
8111
8112 u8 reserved_at_20[0x24];
8113 u8 cap_pin_3_mode[0x4];
8114 u8 reserved_at_48[0x4];
8115 u8 cap_pin_2_mode[0x4];
8116 u8 reserved_at_50[0x4];
8117 u8 cap_pin_1_mode[0x4];
8118 u8 reserved_at_58[0x4];
8119 u8 cap_pin_0_mode[0x4];
8120
8121 u8 reserved_at_60[0x4];
8122 u8 cap_pin_7_mode[0x4];
8123 u8 reserved_at_68[0x4];
8124 u8 cap_pin_6_mode[0x4];
8125 u8 reserved_at_70[0x4];
8126 u8 cap_pin_5_mode[0x4];
8127 u8 reserved_at_78[0x4];
8128 u8 cap_pin_4_mode[0x4];
8129
8130 u8 reserved_at_80[0x80];
8131
8132 u8 enable[0x1];
8133 u8 reserved_at_101[0xb];
8134 u8 pattern[0x4];
8135 u8 reserved_at_110[0x4];
8136 u8 pin_mode[0x4];
8137 u8 pin[0x8];
8138
8139 u8 reserved_at_120[0x20];
8140
8141 u8 time_stamp[0x40];
8142
8143 u8 out_pulse_duration[0x10];
8144 u8 out_periodic_adjustment[0x10];
8145
8146 u8 reserved_at_1a0[0x60];
8147};
8148
8149struct mlx5_ifc_mtppse_reg_bits {
8150 u8 reserved_at_0[0x18];
8151 u8 pin[0x8];
8152 u8 event_arm[0x1];
8153 u8 reserved_at_21[0x1b];
8154 u8 event_generation_mode[0x4];
8155 u8 reserved_at_40[0x40];
8156};
8157
e281682b
SM		 8158union mlx5_ifc_ports_control_registers_document_bits {
8159 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
8160 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
8161 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
8162 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
8163 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
8164 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
8165 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
8166 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
8167 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
8168 struct mlx5_ifc_pamp_reg_bits pamp_reg;
8169 struct mlx5_ifc_paos_reg_bits paos_reg;
8170 struct mlx5_ifc_pcap_reg_bits pcap_reg;
8171 struct mlx5_ifc_peir_reg_bits peir_reg;
8172 struct mlx5_ifc_pelc_reg_bits pelc_reg;
8173 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
1c64bf6f 8174 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b
SM		 8175 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
8176 struct mlx5_ifc_pifr_reg_bits pifr_reg;
8177 struct mlx5_ifc_pipg_reg_bits pipg_reg;
8178 struct mlx5_ifc_plbf_reg_bits plbf_reg;
8179 struct mlx5_ifc_plib_reg_bits plib_reg;
8180 struct mlx5_ifc_plpc_reg_bits plpc_reg;
8181 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
8182 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
8183 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
8184 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
8185 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
8186 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
8187 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
8188 struct mlx5_ifc_ppad_reg_bits ppad_reg;
8189 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
8ed1a630 8190 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
e281682b
SM		 8191 struct mlx5_ifc_pplm_reg_bits pplm_reg;
8192 struct mlx5_ifc_pplr_reg_bits pplr_reg;
8193 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
8194 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
8195 struct mlx5_ifc_pspa_reg_bits pspa_reg;
8196 struct mlx5_ifc_ptas_reg_bits ptas_reg;
8197 struct mlx5_ifc_ptys_reg_bits ptys_reg;
7d5e1423 8198 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
e281682b
SM		 8199 struct mlx5_ifc_pude_reg_bits pude_reg;
8200 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
8201 struct mlx5_ifc_slrg_reg_bits slrg_reg;
8202 struct mlx5_ifc_sltp_reg_bits sltp_reg;
f9a1ef72
EE		 8203 struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
8204 struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
e29341fb
IT		 8205 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
8206 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
b4ff3a36 8207 u8 reserved_at_0[0x60e0];
e281682b
SM		 8208};
8209
8210union mlx5_ifc_debug_enhancements_document_bits {
8211 struct mlx5_ifc_health_buffer_bits health_buffer;
b4ff3a36 8212 u8 reserved_at_0[0x200];
e281682b
SM		 8213};
8214
8215union mlx5_ifc_uplink_pci_interface_document_bits {
8216 struct mlx5_ifc_initial_seg_bits initial_seg;
b4ff3a36 8217 u8 reserved_at_0[0x20060];
b775516b
EC		 8218};
8219
2cc43b49
MG		 8220struct mlx5_ifc_set_flow_table_root_out_bits {
8221 u8 status[0x8];
b4ff3a36 8222 u8 reserved_at_8[0x18];
2cc43b49
MG		 8223
8224 u8 syndrome[0x20];
8225
b4ff3a36 8226 u8 reserved_at_40[0x40];
2cc43b49
MG		 8227};
8228
8229struct mlx5_ifc_set_flow_table_root_in_bits {
8230 u8 opcode[0x10];
b4ff3a36 8231 u8 reserved_at_10[0x10];
2cc43b49 8232
b4ff3a36 8233 u8 reserved_at_20[0x10];
2cc43b49
MG		 8234 u8 op_mod[0x10];
8235
7d5e1423
SM		 8236 u8 other_vport[0x1];
8237 u8 reserved_at_41[0xf];
8238 u8 vport_number[0x10];
8239
8240 u8 reserved_at_60[0x20];
2cc43b49
MG		 8241
8242 u8 table_type[0x8];
b4ff3a36 8243 u8 reserved_at_88[0x18];
2cc43b49 8244
b4ff3a36 8245 u8 reserved_at_a0[0x8];
2cc43b49
MG		 8246 u8 table_id[0x18];
8247
500a3d0d
ES		 8248 u8 reserved_at_c0[0x8];
8249 u8 underlay_qpn[0x18];
8250 u8 reserved_at_e0[0x120];
2cc43b49
MG		 8251};
8252
34a40e68 8253enum {
84df61eb
AH		 8254 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
8255 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
34a40e68
MG		 8256};
8257
8258struct mlx5_ifc_modify_flow_table_out_bits {
8259 u8 status[0x8];
b4ff3a36 8260 u8 reserved_at_8[0x18];
34a40e68
MG		 8261
8262 u8 syndrome[0x20];
8263
b4ff3a36 8264 u8 reserved_at_40[0x40];
34a40e68
MG		 8265};
8266
8267struct mlx5_ifc_modify_flow_table_in_bits {
8268 u8 opcode[0x10];
b4ff3a36 8269 u8 reserved_at_10[0x10];
34a40e68 8270
b4ff3a36 8271 u8 reserved_at_20[0x10];
34a40e68
MG		 8272 u8 op_mod[0x10];
8273
7d5e1423
SM		 8274 u8 other_vport[0x1];
8275 u8 reserved_at_41[0xf];
8276 u8 vport_number[0x10];
34a40e68 8277
b4ff3a36 8278 u8 reserved_at_60[0x10];
34a40e68
MG		 8279 u8 modify_field_select[0x10];
8280
8281 u8 table_type[0x8];
b4ff3a36 8282 u8 reserved_at_88[0x18];
34a40e68 8283
b4ff3a36 8284 u8 reserved_at_a0[0x8];
34a40e68
MG		 8285 u8 table_id[0x18];
8286
0c90e9c6 8287 struct mlx5_ifc_flow_table_context_bits flow_table_context;
34a40e68
MG		 8288};
8289
4f3961ee
SM		 8290struct mlx5_ifc_ets_tcn_config_reg_bits {
8291 u8 g[0x1];
8292 u8 b[0x1];
8293 u8 r[0x1];
8294 u8 reserved_at_3[0x9];
8295 u8 group[0x4];
8296 u8 reserved_at_10[0x9];
8297 u8 bw_allocation[0x7];
8298
8299 u8 reserved_at_20[0xc];
8300 u8 max_bw_units[0x4];
8301 u8 reserved_at_30[0x8];
8302 u8 max_bw_value[0x8];
8303};
8304
8305struct mlx5_ifc_ets_global_config_reg_bits {
8306 u8 reserved_at_0[0x2];
8307 u8 r[0x1];
8308 u8 reserved_at_3[0x1d];
8309
8310 u8 reserved_at_20[0xc];
8311 u8 max_bw_units[0x4];
8312 u8 reserved_at_30[0x8];
8313 u8 max_bw_value[0x8];
8314};
8315
8316struct mlx5_ifc_qetc_reg_bits {
8317 u8 reserved_at_0[0x8];
8318 u8 port_number[0x8];
8319 u8 reserved_at_10[0x30];
8320
8321 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
8322 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
8323};
8324
8325struct mlx5_ifc_qtct_reg_bits {
8326 u8 reserved_at_0[0x8];
8327 u8 port_number[0x8];
8328 u8 reserved_at_10[0xd];
8329 u8 prio[0x3];
8330
8331 u8 reserved_at_20[0x1d];
8332 u8 tclass[0x3];
8333};
8334
7d5e1423
SM		 8335struct mlx5_ifc_mcia_reg_bits {
8336 u8 l[0x1];
8337 u8 reserved_at_1[0x7];
8338 u8 module[0x8];
8339 u8 reserved_at_10[0x8];
8340 u8 status[0x8];
8341
8342 u8 i2c_device_address[0x8];
8343 u8 page_number[0x8];
8344 u8 device_address[0x10];
8345
8346 u8 reserved_at_40[0x10];
8347 u8 size[0x10];
8348
8349 u8 reserved_at_60[0x20];
8350
8351 u8 dword_0[0x20];
8352 u8 dword_1[0x20];
8353 u8 dword_2[0x20];
8354 u8 dword_3[0x20];
8355 u8 dword_4[0x20];
8356 u8 dword_5[0x20];
8357 u8 dword_6[0x20];
8358 u8 dword_7[0x20];
8359 u8 dword_8[0x20];
8360 u8 dword_9[0x20];
8361 u8 dword_10[0x20];
8362 u8 dword_11[0x20];
8363};
8364
7486216b
SM		 8365struct mlx5_ifc_dcbx_param_bits {
8366 u8 dcbx_cee_cap[0x1];
8367 u8 dcbx_ieee_cap[0x1];
8368 u8 dcbx_standby_cap[0x1];
8369 u8 reserved_at_0[0x5];
8370 u8 port_number[0x8];
8371 u8 reserved_at_10[0xa];
8372 u8 max_application_table_size[6];
8373 u8 reserved_at_20[0x15];
8374 u8 version_oper[0x3];
8375 u8 reserved_at_38[5];
8376 u8 version_admin[0x3];
8377 u8 willing_admin[0x1];
8378 u8 reserved_at_41[0x3];
8379 u8 pfc_cap_oper[0x4];
8380 u8 reserved_at_48[0x4];
8381 u8 pfc_cap_admin[0x4];
8382 u8 reserved_at_50[0x4];
8383 u8 num_of_tc_oper[0x4];
8384 u8 reserved_at_58[0x4];
8385 u8 num_of_tc_admin[0x4];
8386 u8 remote_willing[0x1];
8387 u8 reserved_at_61[3];
8388 u8 remote_pfc_cap[4];
8389 u8 reserved_at_68[0x14];
8390 u8 remote_num_of_tc[0x4];
8391 u8 reserved_at_80[0x18];
8392 u8 error[0x8];
8393 u8 reserved_at_a0[0x160];
8394};
84df61eb
AH		 8395
8396struct mlx5_ifc_lagc_bits {
8397 u8 reserved_at_0[0x1d];
8398 u8 lag_state[0x3];
8399
8400 u8 reserved_at_20[0x14];
8401 u8 tx_remap_affinity_2[0x4];
8402 u8 reserved_at_38[0x4];
8403 u8 tx_remap_affinity_1[0x4];
8404};
8405
8406struct mlx5_ifc_create_lag_out_bits {
8407 u8 status[0x8];
8408 u8 reserved_at_8[0x18];
8409
8410 u8 syndrome[0x20];
8411
8412 u8 reserved_at_40[0x40];
8413};
8414
8415struct mlx5_ifc_create_lag_in_bits {
8416 u8 opcode[0x10];
8417 u8 reserved_at_10[0x10];
8418
8419 u8 reserved_at_20[0x10];
8420 u8 op_mod[0x10];
8421
8422 struct mlx5_ifc_lagc_bits ctx;
8423};
8424
8425struct mlx5_ifc_modify_lag_out_bits {
8426 u8 status[0x8];
8427 u8 reserved_at_8[0x18];
8428
8429 u8 syndrome[0x20];
8430
8431 u8 reserved_at_40[0x40];
8432};
8433
8434struct mlx5_ifc_modify_lag_in_bits {
8435 u8 opcode[0x10];
8436 u8 reserved_at_10[0x10];
8437
8438 u8 reserved_at_20[0x10];
8439 u8 op_mod[0x10];
8440
8441 u8 reserved_at_40[0x20];
8442 u8 field_select[0x20];
8443
8444 struct mlx5_ifc_lagc_bits ctx;
8445};
8446
8447struct mlx5_ifc_query_lag_out_bits {
8448 u8 status[0x8];
8449 u8 reserved_at_8[0x18];
8450
8451 u8 syndrome[0x20];
8452
8453 u8 reserved_at_40[0x40];
8454
8455 struct mlx5_ifc_lagc_bits ctx;
8456};
8457
8458struct mlx5_ifc_query_lag_in_bits {
8459 u8 opcode[0x10];
8460 u8 reserved_at_10[0x10];
8461
8462 u8 reserved_at_20[0x10];
8463 u8 op_mod[0x10];
8464
8465 u8 reserved_at_40[0x40];
8466};
8467
8468struct mlx5_ifc_destroy_lag_out_bits {
8469 u8 status[0x8];
8470 u8 reserved_at_8[0x18];
8471
8472 u8 syndrome[0x20];
8473
8474 u8 reserved_at_40[0x40];
8475};
8476
8477struct mlx5_ifc_destroy_lag_in_bits {
8478 u8 opcode[0x10];
8479 u8 reserved_at_10[0x10];
8480
8481 u8 reserved_at_20[0x10];
8482 u8 op_mod[0x10];
8483
8484 u8 reserved_at_40[0x40];
8485};
8486
8487struct mlx5_ifc_create_vport_lag_out_bits {
8488 u8 status[0x8];
8489 u8 reserved_at_8[0x18];
8490
8491 u8 syndrome[0x20];
8492
8493 u8 reserved_at_40[0x40];
8494};
8495
8496struct mlx5_ifc_create_vport_lag_in_bits {
8497 u8 opcode[0x10];
8498 u8 reserved_at_10[0x10];
8499
8500 u8 reserved_at_20[0x10];
8501 u8 op_mod[0x10];
8502
8503 u8 reserved_at_40[0x40];
8504};
8505
8506struct mlx5_ifc_destroy_vport_lag_out_bits {
8507 u8 status[0x8];
8508 u8 reserved_at_8[0x18];
8509
8510 u8 syndrome[0x20];
8511
8512 u8 reserved_at_40[0x40];
8513};
8514
8515struct mlx5_ifc_destroy_vport_lag_in_bits {
8516 u8 opcode[0x10];
8517 u8 reserved_at_10[0x10];
8518
8519 u8 reserved_at_20[0x10];
8520 u8 op_mod[0x10];
8521
8522 u8 reserved_at_40[0x40];
8523};
8524
d29b796a 8525#endif /* MLX5_IFC_H */
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