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[mirror_ubuntu-bionic-kernel.git] / include / linux / mlx5 / mlx5_ifc.h
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d29b796a 1/*
e281682b 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
d29b796a
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
e281682b 31*/
d29b796a
EC		 32#ifndef MLX5_IFC_H
33#define MLX5_IFC_H
34
e281682b
SM		 35enum {
36 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
37 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
38 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
39 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
40 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
41 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
42 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
43 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
44 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
45 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
46 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
47 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
48 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
49 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
50 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
51 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
52 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
53 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
54 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
55 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
56 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
57 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
58 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
59 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb
60};
61
62enum {
63 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
64 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
65 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
66 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
67};
68
f91e6d89
EBE		 69enum {
70 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
71 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
72};
73
d29b796a
EC		 74enum {
75 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
76 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
77 MLX5_CMD_OP_INIT_HCA = 0x102,
78 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
79 MLX5_CMD_OP_ENABLE_HCA = 0x104,
80 MLX5_CMD_OP_DISABLE_HCA = 0x105,
81 MLX5_CMD_OP_QUERY_PAGES = 0x107,
82 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
83 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
e281682b
SM		 84 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
85 MLX5_CMD_OP_SET_ISSI = 0x10b,
0dbc6fe0 86 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
d29b796a
EC		 87 MLX5_CMD_OP_CREATE_MKEY = 0x200,
88 MLX5_CMD_OP_QUERY_MKEY = 0x201,
89 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
90 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
91 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
92 MLX5_CMD_OP_CREATE_EQ = 0x301,
93 MLX5_CMD_OP_DESTROY_EQ = 0x302,
94 MLX5_CMD_OP_QUERY_EQ = 0x303,
95 MLX5_CMD_OP_GEN_EQE = 0x304,
96 MLX5_CMD_OP_CREATE_CQ = 0x400,
97 MLX5_CMD_OP_DESTROY_CQ = 0x401,
98 MLX5_CMD_OP_QUERY_CQ = 0x402,
99 MLX5_CMD_OP_MODIFY_CQ = 0x403,
100 MLX5_CMD_OP_CREATE_QP = 0x500,
101 MLX5_CMD_OP_DESTROY_QP = 0x501,
102 MLX5_CMD_OP_RST2INIT_QP = 0x502,
103 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
104 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
105 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
106 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
107 MLX5_CMD_OP_2ERR_QP = 0x507,
108 MLX5_CMD_OP_2RST_QP = 0x50a,
109 MLX5_CMD_OP_QUERY_QP = 0x50b,
e281682b 110 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
d29b796a
EC		 111 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
112 MLX5_CMD_OP_CREATE_PSV = 0x600,
113 MLX5_CMD_OP_DESTROY_PSV = 0x601,
114 MLX5_CMD_OP_CREATE_SRQ = 0x700,
115 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
116 MLX5_CMD_OP_QUERY_SRQ = 0x702,
117 MLX5_CMD_OP_ARM_RQ = 0x703,
e281682b
SM		 118 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
119 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
120 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
121 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
d29b796a
EC		 122 MLX5_CMD_OP_CREATE_DCT = 0x710,
123 MLX5_CMD_OP_DESTROY_DCT = 0x711,
124 MLX5_CMD_OP_DRAIN_DCT = 0x712,
125 MLX5_CMD_OP_QUERY_DCT = 0x713,
126 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
7486216b
SM		 127 MLX5_CMD_OP_CREATE_XRQ = 0x717,
128 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
129 MLX5_CMD_OP_QUERY_XRQ = 0x719,
130 MLX5_CMD_OP_ARM_XRQ = 0x71a,
d29b796a
EC		 131 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
132 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
133 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
134 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
135 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
136 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
e281682b 137 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
d29b796a 138 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
e281682b
SM		 139 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
140 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
141 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
142 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
d29b796a
EC		 143 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
144 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
145 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
146 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
7486216b
SM		 147 MLX5_CMD_OP_SET_RATE_LIMIT = 0x780,
148 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
813f8540
MHY		 149 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
150 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
151 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
152 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
153 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
154 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
d29b796a
EC		 155 MLX5_CMD_OP_ALLOC_PD = 0x800,
156 MLX5_CMD_OP_DEALLOC_PD = 0x801,
157 MLX5_CMD_OP_ALLOC_UAR = 0x802,
158 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
159 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
160 MLX5_CMD_OP_ACCESS_REG = 0x805,
161 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
20bb566b 162 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
d29b796a
EC		 163 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
164 MLX5_CMD_OP_MAD_IFC = 0x50d,
165 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
166 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
167 MLX5_CMD_OP_NOP = 0x80d,
168 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
169 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
e281682b
SM		 170 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
171 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
172 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
173 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
174 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
175 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
176 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
177 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
178 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
179 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
180 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
181 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
928cfe87
TT		 182 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
183 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
84df61eb
AH		 184 MLX5_CMD_OP_CREATE_LAG = 0x840,
185 MLX5_CMD_OP_MODIFY_LAG = 0x841,
186 MLX5_CMD_OP_QUERY_LAG = 0x842,
187 MLX5_CMD_OP_DESTROY_LAG = 0x843,
188 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
189 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
d29b796a
EC		 190 MLX5_CMD_OP_CREATE_TIR = 0x900,
191 MLX5_CMD_OP_MODIFY_TIR = 0x901,
192 MLX5_CMD_OP_DESTROY_TIR = 0x902,
193 MLX5_CMD_OP_QUERY_TIR = 0x903,
d29b796a
EC		 194 MLX5_CMD_OP_CREATE_SQ = 0x904,
195 MLX5_CMD_OP_MODIFY_SQ = 0x905,
196 MLX5_CMD_OP_DESTROY_SQ = 0x906,
197 MLX5_CMD_OP_QUERY_SQ = 0x907,
198 MLX5_CMD_OP_CREATE_RQ = 0x908,
199 MLX5_CMD_OP_MODIFY_RQ = 0x909,
200 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
201 MLX5_CMD_OP_QUERY_RQ = 0x90b,
202 MLX5_CMD_OP_CREATE_RMP = 0x90c,
203 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
204 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
205 MLX5_CMD_OP_QUERY_RMP = 0x90f,
e281682b
SM		 206 MLX5_CMD_OP_CREATE_TIS = 0x912,
207 MLX5_CMD_OP_MODIFY_TIS = 0x913,
208 MLX5_CMD_OP_DESTROY_TIS = 0x914,
209 MLX5_CMD_OP_QUERY_TIS = 0x915,
210 MLX5_CMD_OP_CREATE_RQT = 0x916,
211 MLX5_CMD_OP_MODIFY_RQT = 0x917,
212 MLX5_CMD_OP_DESTROY_RQT = 0x918,
213 MLX5_CMD_OP_QUERY_RQT = 0x919,
2cc43b49 214 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
e281682b
SM		 215 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
216 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
217 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
218 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
219 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
220 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
221 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
222 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
34a40e68 223 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
9dc0b289
AV		 224 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
225 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
226 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
86d56a1a 227 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
7adbde20
HHZ		 228 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d,
229 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e,
86d56a1a 230 MLX5_CMD_OP_MAX
e281682b
SM		 231};
232
233struct mlx5_ifc_flow_table_fields_supported_bits {
234 u8 outer_dmac[0x1];
235 u8 outer_smac[0x1];
236 u8 outer_ether_type[0x1];
b4ff3a36 237 u8 reserved_at_3[0x1];
e281682b
SM		 238 u8 outer_first_prio[0x1];
239 u8 outer_first_cfi[0x1];
240 u8 outer_first_vid[0x1];
b4ff3a36 241 u8 reserved_at_7[0x1];
e281682b
SM		 242 u8 outer_second_prio[0x1];
243 u8 outer_second_cfi[0x1];
244 u8 outer_second_vid[0x1];
b4ff3a36 245 u8 reserved_at_b[0x1];
e281682b
SM		 246 u8 outer_sip[0x1];
247 u8 outer_dip[0x1];
248 u8 outer_frag[0x1];
249 u8 outer_ip_protocol[0x1];
250 u8 outer_ip_ecn[0x1];
251 u8 outer_ip_dscp[0x1];
252 u8 outer_udp_sport[0x1];
253 u8 outer_udp_dport[0x1];
254 u8 outer_tcp_sport[0x1];
255 u8 outer_tcp_dport[0x1];
256 u8 outer_tcp_flags[0x1];
257 u8 outer_gre_protocol[0x1];
258 u8 outer_gre_key[0x1];
259 u8 outer_vxlan_vni[0x1];
b4ff3a36 260 u8 reserved_at_1a[0x5];
e281682b
SM		 261 u8 source_eswitch_port[0x1];
262
263 u8 inner_dmac[0x1];
264 u8 inner_smac[0x1];
265 u8 inner_ether_type[0x1];
b4ff3a36 266 u8 reserved_at_23[0x1];
e281682b
SM		 267 u8 inner_first_prio[0x1];
268 u8 inner_first_cfi[0x1];
269 u8 inner_first_vid[0x1];
b4ff3a36 270 u8 reserved_at_27[0x1];
e281682b
SM		 271 u8 inner_second_prio[0x1];
272 u8 inner_second_cfi[0x1];
273 u8 inner_second_vid[0x1];
b4ff3a36 274 u8 reserved_at_2b[0x1];
e281682b
SM		 275 u8 inner_sip[0x1];
276 u8 inner_dip[0x1];
277 u8 inner_frag[0x1];
278 u8 inner_ip_protocol[0x1];
279 u8 inner_ip_ecn[0x1];
280 u8 inner_ip_dscp[0x1];
281 u8 inner_udp_sport[0x1];
282 u8 inner_udp_dport[0x1];
283 u8 inner_tcp_sport[0x1];
284 u8 inner_tcp_dport[0x1];
285 u8 inner_tcp_flags[0x1];
b4ff3a36 286 u8 reserved_at_37[0x9];
e281682b 287
b4ff3a36 288 u8 reserved_at_40[0x40];
e281682b
SM		 289};
290
291struct mlx5_ifc_flow_table_prop_layout_bits {
292 u8 ft_support[0x1];
9dc0b289
AV		 293 u8 reserved_at_1[0x1];
294 u8 flow_counter[0x1];
26a81453 295 u8 flow_modify_en[0x1];
2cc43b49 296 u8 modify_root[0x1];
34a40e68
MG		 297 u8 identified_miss_table_mode[0x1];
298 u8 flow_table_modify[0x1];
7adbde20
HHZ		 299 u8 encap[0x1];
300 u8 decap[0x1];
301 u8 reserved_at_9[0x17];
e281682b 302
b4ff3a36 303 u8 reserved_at_20[0x2];
e281682b 304 u8 log_max_ft_size[0x6];
b4ff3a36 305 u8 reserved_at_28[0x10];
e281682b
SM		 306 u8 max_ft_level[0x8];
307
b4ff3a36 308 u8 reserved_at_40[0x20];
e281682b 309
b4ff3a36 310 u8 reserved_at_60[0x18];
e281682b
SM		 311 u8 log_max_ft_num[0x8];
312
b4ff3a36 313 u8 reserved_at_80[0x18];
e281682b
SM		 314 u8 log_max_destination[0x8];
315
b4ff3a36 316 u8 reserved_at_a0[0x18];
e281682b
SM		 317 u8 log_max_flow[0x8];
318
b4ff3a36 319 u8 reserved_at_c0[0x40];
e281682b
SM		 320
321 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
322
323 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
324};
325
326struct mlx5_ifc_odp_per_transport_service_cap_bits {
327 u8 send[0x1];
328 u8 receive[0x1];
329 u8 write[0x1];
330 u8 read[0x1];
17d2f88f 331 u8 atomic[0x1];
e281682b 332 u8 srq_receive[0x1];
b4ff3a36 333 u8 reserved_at_6[0x1a];
e281682b
SM		 334};
335
b4d1f032 336struct mlx5_ifc_ipv4_layout_bits {
b4ff3a36 337 u8 reserved_at_0[0x60];
b4d1f032
MG		 338
339 u8 ipv4[0x20];
340};
341
342struct mlx5_ifc_ipv6_layout_bits {
343 u8 ipv6[16][0x8];
344};
345
346union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
347 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
348 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
b4ff3a36 349 u8 reserved_at_0[0x80];
b4d1f032
MG		 350};
351
e281682b
SM		 352struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
353 u8 smac_47_16[0x20];
354
355 u8 smac_15_0[0x10];
356 u8 ethertype[0x10];
357
358 u8 dmac_47_16[0x20];
359
360 u8 dmac_15_0[0x10];
361 u8 first_prio[0x3];
362 u8 first_cfi[0x1];
363 u8 first_vid[0xc];
364
365 u8 ip_protocol[0x8];
366 u8 ip_dscp[0x6];
367 u8 ip_ecn[0x2];
10543365
MHY		 368 u8 cvlan_tag[0x1];
369 u8 svlan_tag[0x1];
e281682b 370 u8 frag[0x1];
b4ff3a36 371 u8 reserved_at_93[0x4];
e281682b
SM		 372 u8 tcp_flags[0x9];
373
374 u8 tcp_sport[0x10];
375 u8 tcp_dport[0x10];
376
b4ff3a36 377 u8 reserved_at_c0[0x20];
e281682b
SM		 378
379 u8 udp_sport[0x10];
380 u8 udp_dport[0x10];
381
b4d1f032 382 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
e281682b 383
b4d1f032 384 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
e281682b
SM		 385};
386
387struct mlx5_ifc_fte_match_set_misc_bits {
7486216b
SM		 388 u8 reserved_at_0[0x8];
389 u8 source_sqn[0x18];
e281682b 390
b4ff3a36 391 u8 reserved_at_20[0x10];
e281682b
SM		 392 u8 source_port[0x10];
393
394 u8 outer_second_prio[0x3];
395 u8 outer_second_cfi[0x1];
396 u8 outer_second_vid[0xc];
397 u8 inner_second_prio[0x3];
398 u8 inner_second_cfi[0x1];
399 u8 inner_second_vid[0xc];
400
10543365
MHY		 401 u8 outer_second_cvlan_tag[0x1];
402 u8 inner_second_cvlan_tag[0x1];
403 u8 outer_second_svlan_tag[0x1];
404 u8 inner_second_svlan_tag[0x1];
405 u8 reserved_at_64[0xc];
e281682b
SM		 406 u8 gre_protocol[0x10];
407
408 u8 gre_key_h[0x18];
409 u8 gre_key_l[0x8];
410
411 u8 vxlan_vni[0x18];
b4ff3a36 412 u8 reserved_at_b8[0x8];
e281682b 413
b4ff3a36 414 u8 reserved_at_c0[0x20];
e281682b 415
b4ff3a36 416 u8 reserved_at_e0[0xc];
e281682b
SM		 417 u8 outer_ipv6_flow_label[0x14];
418
b4ff3a36 419 u8 reserved_at_100[0xc];
e281682b
SM		 420 u8 inner_ipv6_flow_label[0x14];
421
b4ff3a36 422 u8 reserved_at_120[0xe0];
e281682b
SM		 423};
424
425struct mlx5_ifc_cmd_pas_bits {
426 u8 pa_h[0x20];
427
428 u8 pa_l[0x14];
b4ff3a36 429 u8 reserved_at_34[0xc];
e281682b
SM		 430};
431
432struct mlx5_ifc_uint64_bits {
433 u8 hi[0x20];
434
435 u8 lo[0x20];
436};
437
438enum {
439 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
440 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
441 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
442 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
443 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
444 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
445 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
446 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
447 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
448 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
449};
450
451struct mlx5_ifc_ads_bits {
452 u8 fl[0x1];
453 u8 free_ar[0x1];
b4ff3a36 454 u8 reserved_at_2[0xe];
e281682b
SM		 455 u8 pkey_index[0x10];
456
b4ff3a36 457 u8 reserved_at_20[0x8];
e281682b
SM		 458 u8 grh[0x1];
459 u8 mlid[0x7];
460 u8 rlid[0x10];
461
462 u8 ack_timeout[0x5];
b4ff3a36 463 u8 reserved_at_45[0x3];
e281682b 464 u8 src_addr_index[0x8];
b4ff3a36 465 u8 reserved_at_50[0x4];
e281682b
SM		 466 u8 stat_rate[0x4];
467 u8 hop_limit[0x8];
468
b4ff3a36 469 u8 reserved_at_60[0x4];
e281682b
SM		 470 u8 tclass[0x8];
471 u8 flow_label[0x14];
472
473 u8 rgid_rip[16][0x8];
474
b4ff3a36 475 u8 reserved_at_100[0x4];
e281682b
SM		 476 u8 f_dscp[0x1];
477 u8 f_ecn[0x1];
b4ff3a36 478 u8 reserved_at_106[0x1];
e281682b
SM		 479 u8 f_eth_prio[0x1];
480 u8 ecn[0x2];
481 u8 dscp[0x6];
482 u8 udp_sport[0x10];
483
484 u8 dei_cfi[0x1];
485 u8 eth_prio[0x3];
486 u8 sl[0x4];
487 u8 port[0x8];
488 u8 rmac_47_32[0x10];
489
490 u8 rmac_31_0[0x20];
491};
492
493struct mlx5_ifc_flow_table_nic_cap_bits {
b3638e1a 494 u8 nic_rx_multi_path_tirs[0x1];
cea824d4
MG		 495 u8 nic_rx_multi_path_tirs_fts[0x1];
496 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
497 u8 reserved_at_3[0x1fd];
e281682b
SM		 498
499 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
500
b4ff3a36 501 u8 reserved_at_400[0x200];
e281682b
SM		 502
503 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
504
505 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
506
b4ff3a36 507 u8 reserved_at_a00[0x200];
e281682b
SM		 508
509 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
510
b4ff3a36 511 u8 reserved_at_e00[0x7200];
e281682b
SM		 512};
513
495716b1 514struct mlx5_ifc_flow_table_eswitch_cap_bits {
b4ff3a36 515 u8 reserved_at_0[0x200];
495716b1
SM		 516
517 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
518
519 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
520
521 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
522
b4ff3a36 523 u8 reserved_at_800[0x7800];
495716b1
SM		 524};
525
d6666753
SM		 526struct mlx5_ifc_e_switch_cap_bits {
527 u8 vport_svlan_strip[0x1];
528 u8 vport_cvlan_strip[0x1];
529 u8 vport_svlan_insert[0x1];
530 u8 vport_cvlan_insert_if_not_exist[0x1];
531 u8 vport_cvlan_insert_overwrite[0x1];
23898c76
NO		 532 u8 reserved_at_5[0x19];
533 u8 nic_vport_node_guid_modify[0x1];
534 u8 nic_vport_port_guid_modify[0x1];
d6666753 535
7adbde20
HHZ		 536 u8 vxlan_encap_decap[0x1];
537 u8 nvgre_encap_decap[0x1];
538 u8 reserved_at_22[0x9];
539 u8 log_max_encap_headers[0x5];
540 u8 reserved_2b[0x6];
541 u8 max_encap_header_size[0xa];
542
543 u8 reserved_40[0x7c0];
544
d6666753
SM		 545};
546
7486216b
SM		 547struct mlx5_ifc_qos_cap_bits {
548 u8 packet_pacing[0x1];
813f8540
MHY		 549 u8 esw_scheduling[0x1];
550 u8 reserved_at_2[0x1e];
551
552 u8 reserved_at_20[0x20];
553
7486216b 554 u8 packet_pacing_max_rate[0x20];
813f8540 555
7486216b 556 u8 packet_pacing_min_rate[0x20];
813f8540
MHY		 557
558 u8 reserved_at_80[0x10];
7486216b 559 u8 packet_pacing_rate_table_size[0x10];
813f8540
MHY		 560
561 u8 esw_element_type[0x10];
562 u8 esw_tsar_type[0x10];
563
564 u8 reserved_at_c0[0x10];
565 u8 max_qos_para_vport[0x10];
566
567 u8 max_tsar_bw_share[0x20];
568
569 u8 reserved_at_100[0x700];
7486216b
SM		 570};
571
e281682b
SM		 572struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
573 u8 csum_cap[0x1];
574 u8 vlan_cap[0x1];
575 u8 lro_cap[0x1];
576 u8 lro_psh_flag[0x1];
577 u8 lro_time_stamp[0x1];
b4ff3a36 578 u8 reserved_at_5[0x3];
66189961 579 u8 self_lb_en_modifiable[0x1];
b4ff3a36 580 u8 reserved_at_9[0x2];
e281682b 581 u8 max_lso_cap[0x5];
c226dc22 582 u8 multi_pkt_send_wqe[0x2];
cff92d7c 583 u8 wqe_inline_mode[0x2];
e281682b 584 u8 rss_ind_tbl_cap[0x4];
7d5e1423
SM		 585 u8 reg_umr_sq[0x1];
586 u8 scatter_fcs[0x1];
587 u8 reserved_at_1a[0x1];
e281682b 588 u8 tunnel_lso_const_out_ip_id[0x1];
b4ff3a36 589 u8 reserved_at_1c[0x2];
e281682b
SM		 590 u8 tunnel_statless_gre[0x1];
591 u8 tunnel_stateless_vxlan[0x1];
592
b4ff3a36 593 u8 reserved_at_20[0x20];
e281682b 594
b4ff3a36 595 u8 reserved_at_40[0x10];
e281682b
SM		 596 u8 lro_min_mss_size[0x10];
597
b4ff3a36 598 u8 reserved_at_60[0x120];
e281682b
SM		 599
600 u8 lro_timer_supported_periods[4][0x20];
601
b4ff3a36 602 u8 reserved_at_200[0x600];
e281682b
SM		 603};
604
605struct mlx5_ifc_roce_cap_bits {
606 u8 roce_apm[0x1];
b4ff3a36 607 u8 reserved_at_1[0x1f];
e281682b 608
b4ff3a36 609 u8 reserved_at_20[0x60];
e281682b 610
b4ff3a36 611 u8 reserved_at_80[0xc];
e281682b 612 u8 l3_type[0x4];
b4ff3a36 613 u8 reserved_at_90[0x8];
e281682b
SM		 614 u8 roce_version[0x8];
615
b4ff3a36 616 u8 reserved_at_a0[0x10];
e281682b
SM		 617 u8 r_roce_dest_udp_port[0x10];
618
619 u8 r_roce_max_src_udp_port[0x10];
620 u8 r_roce_min_src_udp_port[0x10];
621
b4ff3a36 622 u8 reserved_at_e0[0x10];
e281682b
SM		 623 u8 roce_address_table_size[0x10];
624
b4ff3a36 625 u8 reserved_at_100[0x700];
e281682b
SM		 626};
627
628enum {
629 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
630 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
631 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
632 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
633 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
634 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
635 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
636 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
637 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
638};
639
640enum {
641 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
642 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
643 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
644 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
645 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
646 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
647 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
648 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
649 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
650};
651
652struct mlx5_ifc_atomic_caps_bits {
b4ff3a36 653 u8 reserved_at_0[0x40];
e281682b 654
f91e6d89 655 u8 atomic_req_8B_endianess_mode[0x2];
b4ff3a36 656 u8 reserved_at_42[0x4];
f91e6d89 657 u8 supported_atomic_req_8B_endianess_mode_1[0x1];
e281682b 658
b4ff3a36 659 u8 reserved_at_47[0x19];
e281682b 660
b4ff3a36 661 u8 reserved_at_60[0x20];
e281682b 662
b4ff3a36 663 u8 reserved_at_80[0x10];
f91e6d89 664 u8 atomic_operations[0x10];
e281682b 665
b4ff3a36 666 u8 reserved_at_a0[0x10];
f91e6d89
EBE		 667 u8 atomic_size_qp[0x10];
668
b4ff3a36 669 u8 reserved_at_c0[0x10];
e281682b
SM		 670 u8 atomic_size_dc[0x10];
671
b4ff3a36 672 u8 reserved_at_e0[0x720];
e281682b
SM		 673};
674
675struct mlx5_ifc_odp_cap_bits {
b4ff3a36 676 u8 reserved_at_0[0x40];
e281682b
SM		 677
678 u8 sig[0x1];
b4ff3a36 679 u8 reserved_at_41[0x1f];
e281682b 680
b4ff3a36 681 u8 reserved_at_60[0x20];
e281682b
SM		 682
683 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
684
685 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
686
687 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
688
b4ff3a36 689 u8 reserved_at_e0[0x720];
e281682b
SM		 690};
691
3f0393a5
SG		 692struct mlx5_ifc_calc_op {
693 u8 reserved_at_0[0x10];
694 u8 reserved_at_10[0x9];
695 u8 op_swap_endianness[0x1];
696 u8 op_min[0x1];
697 u8 op_xor[0x1];
698 u8 op_or[0x1];
699 u8 op_and[0x1];
700 u8 op_max[0x1];
701 u8 op_add[0x1];
702};
703
704struct mlx5_ifc_vector_calc_cap_bits {
705 u8 calc_matrix[0x1];
706 u8 reserved_at_1[0x1f];
707 u8 reserved_at_20[0x8];
708 u8 max_vec_count[0x8];
709 u8 reserved_at_30[0xd];
710 u8 max_chunk_size[0x3];
711 struct mlx5_ifc_calc_op calc0;
712 struct mlx5_ifc_calc_op calc1;
713 struct mlx5_ifc_calc_op calc2;
714 struct mlx5_ifc_calc_op calc3;
715
716 u8 reserved_at_e0[0x720];
717};
718
e281682b
SM		 719enum {
720 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
721 MLX5_WQ_TYPE_CYCLIC = 0x1,
7d5e1423 722 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
e281682b
SM		 723};
724
725enum {
726 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
727 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
728};
729
730enum {
731 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
732 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
733 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
734 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
735 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
736};
737
738enum {
739 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
740 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
741 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
742 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
743 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
744 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
745};
746
747enum {
748 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
749 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
750};
751
752enum {
753 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
754 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
755 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
756};
757
758enum {
759 MLX5_CAP_PORT_TYPE_IB = 0x0,
760 MLX5_CAP_PORT_TYPE_ETH = 0x1,
d29b796a
EC		 761};
762
b775516b 763struct mlx5_ifc_cmd_hca_cap_bits {
b4ff3a36 764 u8 reserved_at_0[0x80];
b775516b
EC		 765
766 u8 log_max_srq_sz[0x8];
767 u8 log_max_qp_sz[0x8];
b4ff3a36 768 u8 reserved_at_90[0xb];
b775516b
EC		 769 u8 log_max_qp[0x5];
770
b4ff3a36 771 u8 reserved_at_a0[0xb];
e281682b 772 u8 log_max_srq[0x5];
b4ff3a36 773 u8 reserved_at_b0[0x10];
b775516b 774
b4ff3a36 775 u8 reserved_at_c0[0x8];
b775516b 776 u8 log_max_cq_sz[0x8];
b4ff3a36 777 u8 reserved_at_d0[0xb];
b775516b
EC		 778 u8 log_max_cq[0x5];
779
780 u8 log_max_eq_sz[0x8];
b4ff3a36 781 u8 reserved_at_e8[0x2];
b775516b 782 u8 log_max_mkey[0x6];
b4ff3a36 783 u8 reserved_at_f0[0xc];
b775516b
EC		 784 u8 log_max_eq[0x4];
785
786 u8 max_indirection[0x8];
bcda1aca 787 u8 fixed_buffer_size[0x1];
b775516b 788 u8 log_max_mrw_sz[0x7];
b4ff3a36 789 u8 reserved_at_110[0x2];
b775516b 790 u8 log_max_bsf_list_size[0x6];
bcda1aca
AK		 791 u8 umr_extended_translation_offset[0x1];
792 u8 null_mkey[0x1];
b775516b
EC		 793 u8 log_max_klm_list_size[0x6];
794
b4ff3a36 795 u8 reserved_at_120[0xa];
b775516b 796 u8 log_max_ra_req_dc[0x6];
b4ff3a36 797 u8 reserved_at_130[0xa];
b775516b
EC		 798 u8 log_max_ra_res_dc[0x6];
799
b4ff3a36 800 u8 reserved_at_140[0xa];
b775516b 801 u8 log_max_ra_req_qp[0x6];
b4ff3a36 802 u8 reserved_at_150[0xa];
b775516b
EC		 803 u8 log_max_ra_res_qp[0x6];
804
805 u8 pad_cap[0x1];
806 u8 cc_query_allowed[0x1];
807 u8 cc_modify_allowed[0x1];
b4ff3a36 808 u8 reserved_at_163[0xd];
e281682b 809 u8 gid_table_size[0x10];
b775516b 810
e281682b
SM		 811 u8 out_of_seq_cnt[0x1];
812 u8 vport_counters[0x1];
7486216b 813 u8 retransmission_q_counters[0x1];
83b502a1
AV		 814 u8 reserved_at_183[0x1];
815 u8 modify_rq_counter_set_id[0x1];
816 u8 reserved_at_185[0x1];
b775516b
EC		 817 u8 max_qp_cnt[0xa];
818 u8 pkey_table_size[0x10];
819
e281682b
SM		 820 u8 vport_group_manager[0x1];
821 u8 vhca_group_manager[0x1];
822 u8 ib_virt[0x1];
823 u8 eth_virt[0x1];
b4ff3a36 824 u8 reserved_at_1a4[0x1];
e281682b
SM		 825 u8 ets[0x1];
826 u8 nic_flow_table[0x1];
54f0a411 827 u8 eswitch_flow_table[0x1];
e1c9c62b 828 u8 early_vf_enable[0x1];
cfdcbcea
GP		 829 u8 mcam_reg[0x1];
830 u8 pcam_reg[0x1];
b775516b 831 u8 local_ca_ack_delay[0x5];
4ce3bf2f 832 u8 port_module_event[0x1];
7b13558f 833 u8 reserved_at_1b1[0x1];
7d5e1423 834 u8 ports_check[0x1];
7b13558f 835 u8 reserved_at_1b3[0x1];
7d5e1423
SM		 836 u8 disable_link_up[0x1];
837 u8 beacon_led[0x1];
e281682b 838 u8 port_type[0x2];
b775516b
EC		 839 u8 num_ports[0x8];
840
f9a1ef72
EE		 841 u8 reserved_at_1c0[0x1];
842 u8 pps[0x1];
843 u8 pps_modify[0x1];
b775516b 844 u8 log_max_msg[0x5];
e1c9c62b 845 u8 reserved_at_1c8[0x4];
4f3961ee 846 u8 max_tc[0x4];
7486216b
SM		 847 u8 reserved_at_1d0[0x1];
848 u8 dcbx[0x1];
849 u8 reserved_at_1d2[0x4];
928cfe87
TT		 850 u8 rol_s[0x1];
851 u8 rol_g[0x1];
e1c9c62b 852 u8 reserved_at_1d8[0x1];
928cfe87
TT		 853 u8 wol_s[0x1];
854 u8 wol_g[0x1];
855 u8 wol_a[0x1];
856 u8 wol_b[0x1];
857 u8 wol_m[0x1];
858 u8 wol_u[0x1];
859 u8 wol_p[0x1];
b775516b
EC		 860
861 u8 stat_rate_support[0x10];
e1c9c62b 862 u8 reserved_at_1f0[0xc];
e281682b 863 u8 cqe_version[0x4];
b775516b 864
e281682b 865 u8 compact_address_vector[0x1];
7d5e1423 866 u8 striding_rq[0x1];
7b13558f 867 u8 reserved_at_202[0x2];
1015c2e8 868 u8 ipoib_basic_offloads[0x1];
e1c9c62b 869 u8 reserved_at_205[0xa];
e281682b 870 u8 drain_sigerr[0x1];
b775516b
EC		 871 u8 cmdif_checksum[0x2];
872 u8 sigerr_cqe[0x1];
e1c9c62b 873 u8 reserved_at_213[0x1];
b775516b
EC		 874 u8 wq_signature[0x1];
875 u8 sctr_data_cqe[0x1];
e1c9c62b 876 u8 reserved_at_216[0x1];
b775516b
EC		 877 u8 sho[0x1];
878 u8 tph[0x1];
879 u8 rf[0x1];
e281682b 880 u8 dct[0x1];
7486216b 881 u8 qos[0x1];
e281682b 882 u8 eth_net_offloads[0x1];
b775516b
EC		 883 u8 roce[0x1];
884 u8 atomic[0x1];
e1c9c62b 885 u8 reserved_at_21f[0x1];
b775516b
EC		 886
887 u8 cq_oi[0x1];
888 u8 cq_resize[0x1];
889 u8 cq_moderation[0x1];
e1c9c62b 890 u8 reserved_at_223[0x3];
e281682b 891 u8 cq_eq_remap[0x1];
b775516b
EC		 892 u8 pg[0x1];
893 u8 block_lb_mc[0x1];
e1c9c62b 894 u8 reserved_at_229[0x1];
e281682b 895 u8 scqe_break_moderation[0x1];
7d5e1423 896 u8 cq_period_start_from_cqe[0x1];
b775516b 897 u8 cd[0x1];
e1c9c62b 898 u8 reserved_at_22d[0x1];
b775516b 899 u8 apm[0x1];
3f0393a5 900 u8 vector_calc[0x1];
7d5e1423 901 u8 umr_ptr_rlky[0x1];
d2370e0a 902 u8 imaicl[0x1];
e1c9c62b 903 u8 reserved_at_232[0x4];
b775516b
EC		 904 u8 qkv[0x1];
905 u8 pkv[0x1];
b11a4f9c
HE		 906 u8 set_deth_sqpn[0x1];
907 u8 reserved_at_239[0x3];
b775516b
EC		 908 u8 xrc[0x1];
909 u8 ud[0x1];
910 u8 uc[0x1];
911 u8 rc[0x1];
912
a6d51b68
EC		 913 u8 uar_4k[0x1];
914 u8 reserved_at_241[0x9];
b775516b 915 u8 uar_sz[0x6];
e1c9c62b 916 u8 reserved_at_250[0x8];
b775516b
EC		 917 u8 log_pg_sz[0x8];
918
919 u8 bf[0x1];
0dbc6fe0 920 u8 driver_version[0x1];
e281682b 921 u8 pad_tx_eth_packet[0x1];
e1c9c62b 922 u8 reserved_at_263[0x8];
b775516b 923 u8 log_bf_reg_size[0x5];
84df61eb
AH		 924
925 u8 reserved_at_270[0xb];
926 u8 lag_master[0x1];
927 u8 num_lag_ports[0x4];
b775516b 928
e1c9c62b 929 u8 reserved_at_280[0x10];
b775516b
EC		 930 u8 max_wqe_sz_sq[0x10];
931
e1c9c62b 932 u8 reserved_at_2a0[0x10];
b775516b
EC		 933 u8 max_wqe_sz_rq[0x10];
934
e1c9c62b 935 u8 reserved_at_2c0[0x10];
b775516b
EC		 936 u8 max_wqe_sz_sq_dc[0x10];
937
e1c9c62b 938 u8 reserved_at_2e0[0x7];
b775516b
EC		 939 u8 max_qp_mcg[0x19];
940
e1c9c62b 941 u8 reserved_at_300[0x18];
b775516b
EC		 942 u8 log_max_mcg[0x8];
943
e1c9c62b 944 u8 reserved_at_320[0x3];
e281682b 945 u8 log_max_transport_domain[0x5];
e1c9c62b 946 u8 reserved_at_328[0x3];
b775516b 947 u8 log_max_pd[0x5];
e1c9c62b 948 u8 reserved_at_330[0xb];
b775516b
EC		 949 u8 log_max_xrcd[0x5];
950
a351a1b0
AV		 951 u8 reserved_at_340[0x8];
952 u8 log_max_flow_counter_bulk[0x8];
953 u8 max_flow_counter[0x10];
954
b775516b 955
e1c9c62b 956 u8 reserved_at_360[0x3];
b775516b 957 u8 log_max_rq[0x5];
e1c9c62b 958 u8 reserved_at_368[0x3];
b775516b 959 u8 log_max_sq[0x5];
e1c9c62b 960 u8 reserved_at_370[0x3];
b775516b 961 u8 log_max_tir[0x5];
e1c9c62b 962 u8 reserved_at_378[0x3];
b775516b
EC		 963 u8 log_max_tis[0x5];
964
e281682b 965 u8 basic_cyclic_rcv_wqe[0x1];
e1c9c62b 966 u8 reserved_at_381[0x2];
e281682b 967 u8 log_max_rmp[0x5];
e1c9c62b 968 u8 reserved_at_388[0x3];
e281682b 969 u8 log_max_rqt[0x5];
e1c9c62b 970 u8 reserved_at_390[0x3];
e281682b 971 u8 log_max_rqt_size[0x5];
e1c9c62b 972 u8 reserved_at_398[0x3];
b775516b
EC		 973 u8 log_max_tis_per_sq[0x5];
974
e1c9c62b 975 u8 reserved_at_3a0[0x3];
e281682b 976 u8 log_max_stride_sz_rq[0x5];
e1c9c62b 977 u8 reserved_at_3a8[0x3];
e281682b 978 u8 log_min_stride_sz_rq[0x5];
e1c9c62b 979 u8 reserved_at_3b0[0x3];
e281682b 980 u8 log_max_stride_sz_sq[0x5];
e1c9c62b 981 u8 reserved_at_3b8[0x3];
e281682b
SM		 982 u8 log_min_stride_sz_sq[0x5];
983
e1c9c62b 984 u8 reserved_at_3c0[0x1b];
e281682b
SM		 985 u8 log_max_wq_sz[0x5];
986
54f0a411 987 u8 nic_vport_change_event[0x1];
e1c9c62b 988 u8 reserved_at_3e1[0xa];
54f0a411 989 u8 log_max_vlan_list[0x5];
e1c9c62b 990 u8 reserved_at_3f0[0x3];
54f0a411 991 u8 log_max_current_mc_list[0x5];
e1c9c62b 992 u8 reserved_at_3f8[0x3];
54f0a411
SM		 993 u8 log_max_current_uc_list[0x5];
994
e1c9c62b 995 u8 reserved_at_400[0x80];
54f0a411 996
e1c9c62b 997 u8 reserved_at_480[0x3];
e281682b 998 u8 log_max_l2_table[0x5];
e1c9c62b 999 u8 reserved_at_488[0x8];
b775516b
EC		 1000 u8 log_uar_page_sz[0x10];
1001
e1c9c62b 1002 u8 reserved_at_4a0[0x20];
048ccca8 1003 u8 device_frequency_mhz[0x20];
b0844444 1004 u8 device_frequency_khz[0x20];
e1c9c62b 1005
a6d51b68
EC		 1006 u8 reserved_at_500[0x20];
1007 u8 num_of_uars_per_page[0x20];
1008 u8 reserved_at_540[0x40];
e1c9c62b
TT		 1009
1010 u8 reserved_at_580[0x3f];
7d5e1423 1011 u8 cqe_compression[0x1];
b775516b 1012
7d5e1423
SM		 1013 u8 cqe_compression_timeout[0x10];
1014 u8 cqe_compression_max_num[0x10];
b775516b 1015
7486216b
SM		 1016 u8 reserved_at_5e0[0x10];
1017 u8 tag_matching[0x1];
1018 u8 rndv_offload_rc[0x1];
1019 u8 rndv_offload_dc[0x1];
1020 u8 log_tag_matching_list_sz[0x5];
7b13558f 1021 u8 reserved_at_5f8[0x3];
7486216b
SM		 1022 u8 log_max_xrq[0x5];
1023
7b13558f 1024 u8 reserved_at_600[0x200];
b775516b
EC		 1025};
1026
81848731
SM		 1027enum mlx5_flow_destination_type {
1028 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1029 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1030 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
bd5251db
AV		 1031
1032 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
e281682b 1033};
b775516b 1034
e281682b
SM		 1035struct mlx5_ifc_dest_format_struct_bits {
1036 u8 destination_type[0x8];
1037 u8 destination_id[0x18];
b775516b 1038
b4ff3a36 1039 u8 reserved_at_20[0x20];
e281682b
SM		 1040};
1041
9dc0b289 1042struct mlx5_ifc_flow_counter_list_bits {
a351a1b0
AV		 1043 u8 clear[0x1];
1044 u8 num_of_counters[0xf];
9dc0b289
AV		 1045 u8 flow_counter_id[0x10];
1046
1047 u8 reserved_at_20[0x20];
1048};
1049
1050union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1051 struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1052 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1053 u8 reserved_at_0[0x40];
1054};
1055
e281682b
SM		 1056struct mlx5_ifc_fte_match_param_bits {
1057 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1058
1059 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1060
1061 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
b775516b 1062
b4ff3a36 1063 u8 reserved_at_600[0xa00];
b775516b
EC		 1064};
1065
e281682b
SM		 1066enum {
1067 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1068 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1069 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1070 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1071 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1072};
b775516b 1073
e281682b
SM		 1074struct mlx5_ifc_rx_hash_field_select_bits {
1075 u8 l3_prot_type[0x1];
1076 u8 l4_prot_type[0x1];
1077 u8 selected_fields[0x1e];
1078};
b775516b 1079
e281682b
SM		 1080enum {
1081 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
1082 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
b775516b
EC		 1083};
1084
e281682b
SM		 1085enum {
1086 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
1087 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
1088};
1089
1090struct mlx5_ifc_wq_bits {
1091 u8 wq_type[0x4];
1092 u8 wq_signature[0x1];
1093 u8 end_padding_mode[0x2];
1094 u8 cd_slave[0x1];
b4ff3a36 1095 u8 reserved_at_8[0x18];
b775516b 1096
e281682b
SM		 1097 u8 hds_skip_first_sge[0x1];
1098 u8 log2_hds_buf_size[0x3];
b4ff3a36 1099 u8 reserved_at_24[0x7];
e281682b
SM		 1100 u8 page_offset[0x5];
1101 u8 lwm[0x10];
b775516b 1102
b4ff3a36 1103 u8 reserved_at_40[0x8];
e281682b
SM		 1104 u8 pd[0x18];
1105
b4ff3a36 1106 u8 reserved_at_60[0x8];
e281682b
SM		 1107 u8 uar_page[0x18];
1108
1109 u8 dbr_addr[0x40];
1110
1111 u8 hw_counter[0x20];
1112
1113 u8 sw_counter[0x20];
1114
b4ff3a36 1115 u8 reserved_at_100[0xc];
e281682b 1116 u8 log_wq_stride[0x4];
b4ff3a36 1117 u8 reserved_at_110[0x3];
e281682b 1118 u8 log_wq_pg_sz[0x5];
b4ff3a36 1119 u8 reserved_at_118[0x3];
e281682b
SM		 1120 u8 log_wq_sz[0x5];
1121
7d5e1423
SM		 1122 u8 reserved_at_120[0x15];
1123 u8 log_wqe_num_of_strides[0x3];
1124 u8 two_byte_shift_en[0x1];
1125 u8 reserved_at_139[0x4];
1126 u8 log_wqe_stride_size[0x3];
1127
1128 u8 reserved_at_140[0x4c0];
b775516b 1129
e281682b 1130 struct mlx5_ifc_cmd_pas_bits pas[0];
b775516b
EC		 1131};
1132
e281682b 1133struct mlx5_ifc_rq_num_bits {
b4ff3a36 1134 u8 reserved_at_0[0x8];
e281682b
SM		 1135 u8 rq_num[0x18];
1136};
b775516b 1137
e281682b 1138struct mlx5_ifc_mac_address_layout_bits {
b4ff3a36 1139 u8 reserved_at_0[0x10];
e281682b 1140 u8 mac_addr_47_32[0x10];
b775516b 1141
e281682b
SM		 1142 u8 mac_addr_31_0[0x20];
1143};
1144
c0046cf7 1145struct mlx5_ifc_vlan_layout_bits {
b4ff3a36 1146 u8 reserved_at_0[0x14];
c0046cf7
SM		 1147 u8 vlan[0x0c];
1148
b4ff3a36 1149 u8 reserved_at_20[0x20];
c0046cf7
SM		 1150};
1151
e281682b 1152struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
b4ff3a36 1153 u8 reserved_at_0[0xa0];
e281682b
SM		 1154
1155 u8 min_time_between_cnps[0x20];
1156
b4ff3a36 1157 u8 reserved_at_c0[0x12];
e281682b 1158 u8 cnp_dscp[0x6];
b4ff3a36 1159 u8 reserved_at_d8[0x5];
e281682b
SM		 1160 u8 cnp_802p_prio[0x3];
1161
b4ff3a36 1162 u8 reserved_at_e0[0x720];
e281682b
SM		 1163};
1164
1165struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
b4ff3a36 1166 u8 reserved_at_0[0x60];
e281682b 1167
b4ff3a36 1168 u8 reserved_at_60[0x4];
e281682b 1169 u8 clamp_tgt_rate[0x1];
b4ff3a36 1170 u8 reserved_at_65[0x3];
e281682b 1171 u8 clamp_tgt_rate_after_time_inc[0x1];
b4ff3a36 1172 u8 reserved_at_69[0x17];
e281682b 1173
b4ff3a36 1174 u8 reserved_at_80[0x20];
e281682b
SM		 1175
1176 u8 rpg_time_reset[0x20];
1177
1178 u8 rpg_byte_reset[0x20];
1179
1180 u8 rpg_threshold[0x20];
1181
1182 u8 rpg_max_rate[0x20];
1183
1184 u8 rpg_ai_rate[0x20];
1185
1186 u8 rpg_hai_rate[0x20];
1187
1188 u8 rpg_gd[0x20];
1189
1190 u8 rpg_min_dec_fac[0x20];
1191
1192 u8 rpg_min_rate[0x20];
1193
b4ff3a36 1194 u8 reserved_at_1c0[0xe0];
e281682b
SM		 1195
1196 u8 rate_to_set_on_first_cnp[0x20];
1197
1198 u8 dce_tcp_g[0x20];
1199
1200 u8 dce_tcp_rtt[0x20];
1201
1202 u8 rate_reduce_monitor_period[0x20];
1203
b4ff3a36 1204 u8 reserved_at_320[0x20];
e281682b
SM		 1205
1206 u8 initial_alpha_value[0x20];
1207
b4ff3a36 1208 u8 reserved_at_360[0x4a0];
e281682b
SM		 1209};
1210
1211struct mlx5_ifc_cong_control_802_1qau_rp_bits {
b4ff3a36 1212 u8 reserved_at_0[0x80];
e281682b
SM		 1213
1214 u8 rppp_max_rps[0x20];
1215
1216 u8 rpg_time_reset[0x20];
1217
1218 u8 rpg_byte_reset[0x20];
1219
1220 u8 rpg_threshold[0x20];
1221
1222 u8 rpg_max_rate[0x20];
1223
1224 u8 rpg_ai_rate[0x20];
1225
1226 u8 rpg_hai_rate[0x20];
1227
1228 u8 rpg_gd[0x20];
1229
1230 u8 rpg_min_dec_fac[0x20];
1231
1232 u8 rpg_min_rate[0x20];
1233
b4ff3a36 1234 u8 reserved_at_1c0[0x640];
e281682b
SM		 1235};
1236
1237enum {
1238 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1239 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1240 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1241};
1242
1243struct mlx5_ifc_resize_field_select_bits {
1244 u8 resize_field_select[0x20];
1245};
1246
1247enum {
1248 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1249 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1250 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1251 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1252};
1253
1254struct mlx5_ifc_modify_field_select_bits {
1255 u8 modify_field_select[0x20];
1256};
1257
1258struct mlx5_ifc_field_select_r_roce_np_bits {
1259 u8 field_select_r_roce_np[0x20];
1260};
1261
1262struct mlx5_ifc_field_select_r_roce_rp_bits {
1263 u8 field_select_r_roce_rp[0x20];
1264};
1265
1266enum {
1267 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1268 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1269 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1270 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1271 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1272 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1273 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1274 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1275 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1276 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1277};
1278
1279struct mlx5_ifc_field_select_802_1qau_rp_bits {
1280 u8 field_select_8021qaurp[0x20];
1281};
1282
1283struct mlx5_ifc_phys_layer_cntrs_bits {
1284 u8 time_since_last_clear_high[0x20];
1285
1286 u8 time_since_last_clear_low[0x20];
1287
1288 u8 symbol_errors_high[0x20];
1289
1290 u8 symbol_errors_low[0x20];
1291
1292 u8 sync_headers_errors_high[0x20];
1293
1294 u8 sync_headers_errors_low[0x20];
1295
1296 u8 edpl_bip_errors_lane0_high[0x20];
1297
1298 u8 edpl_bip_errors_lane0_low[0x20];
1299
1300 u8 edpl_bip_errors_lane1_high[0x20];
1301
1302 u8 edpl_bip_errors_lane1_low[0x20];
1303
1304 u8 edpl_bip_errors_lane2_high[0x20];
1305
1306 u8 edpl_bip_errors_lane2_low[0x20];
1307
1308 u8 edpl_bip_errors_lane3_high[0x20];
1309
1310 u8 edpl_bip_errors_lane3_low[0x20];
1311
1312 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1313
1314 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1315
1316 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1317
1318 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1319
1320 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1321
1322 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1323
1324 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1325
1326 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1327
1328 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1329
1330 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1331
1332 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1333
1334 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1335
1336 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1337
1338 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1339
1340 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1341
1342 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1343
1344 u8 rs_fec_corrected_blocks_high[0x20];
1345
1346 u8 rs_fec_corrected_blocks_low[0x20];
1347
1348 u8 rs_fec_uncorrectable_blocks_high[0x20];
1349
1350 u8 rs_fec_uncorrectable_blocks_low[0x20];
1351
1352 u8 rs_fec_no_errors_blocks_high[0x20];
1353
1354 u8 rs_fec_no_errors_blocks_low[0x20];
1355
1356 u8 rs_fec_single_error_blocks_high[0x20];
1357
1358 u8 rs_fec_single_error_blocks_low[0x20];
1359
1360 u8 rs_fec_corrected_symbols_total_high[0x20];
1361
1362 u8 rs_fec_corrected_symbols_total_low[0x20];
1363
1364 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1365
1366 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1367
1368 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1369
1370 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1371
1372 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1373
1374 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1375
1376 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1377
1378 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1379
1380 u8 link_down_events[0x20];
1381
1382 u8 successful_recovery_events[0x20];
1383
b4ff3a36 1384 u8 reserved_at_640[0x180];
e281682b
SM		 1385};
1386
d8dc0508
GP		 1387struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1388 u8 time_since_last_clear_high[0x20];
1389
1390 u8 time_since_last_clear_low[0x20];
1391
1392 u8 phy_received_bits_high[0x20];
1393
1394 u8 phy_received_bits_low[0x20];
1395
1396 u8 phy_symbol_errors_high[0x20];
1397
1398 u8 phy_symbol_errors_low[0x20];
1399
1400 u8 phy_corrected_bits_high[0x20];
1401
1402 u8 phy_corrected_bits_low[0x20];
1403
1404 u8 phy_corrected_bits_lane0_high[0x20];
1405
1406 u8 phy_corrected_bits_lane0_low[0x20];
1407
1408 u8 phy_corrected_bits_lane1_high[0x20];
1409
1410 u8 phy_corrected_bits_lane1_low[0x20];
1411
1412 u8 phy_corrected_bits_lane2_high[0x20];
1413
1414 u8 phy_corrected_bits_lane2_low[0x20];
1415
1416 u8 phy_corrected_bits_lane3_high[0x20];
1417
1418 u8 phy_corrected_bits_lane3_low[0x20];
1419
1420 u8 reserved_at_200[0x5c0];
1421};
1422
1c64bf6f
MY		 1423struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1424 u8 symbol_error_counter[0x10];
1425
1426 u8 link_error_recovery_counter[0x8];
1427
1428 u8 link_downed_counter[0x8];
1429
1430 u8 port_rcv_errors[0x10];
1431
1432 u8 port_rcv_remote_physical_errors[0x10];
1433
1434 u8 port_rcv_switch_relay_errors[0x10];
1435
1436 u8 port_xmit_discards[0x10];
1437
1438 u8 port_xmit_constraint_errors[0x8];
1439
1440 u8 port_rcv_constraint_errors[0x8];
1441
1442 u8 reserved_at_70[0x8];
1443
1444 u8 link_overrun_errors[0x8];
1445
1446 u8 reserved_at_80[0x10];
1447
1448 u8 vl_15_dropped[0x10];
1449
1450 u8 reserved_at_a0[0xa0];
1451};
1452
e281682b
SM		 1453struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1454 u8 transmit_queue_high[0x20];
1455
1456 u8 transmit_queue_low[0x20];
1457
b4ff3a36 1458 u8 reserved_at_40[0x780];
e281682b
SM		 1459};
1460
1461struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1462 u8 rx_octets_high[0x20];
1463
1464 u8 rx_octets_low[0x20];
1465
b4ff3a36 1466 u8 reserved_at_40[0xc0];
e281682b
SM		 1467
1468 u8 rx_frames_high[0x20];
1469
1470 u8 rx_frames_low[0x20];
1471
1472 u8 tx_octets_high[0x20];
1473
1474 u8 tx_octets_low[0x20];
1475
b4ff3a36 1476 u8 reserved_at_180[0xc0];
e281682b
SM		 1477
1478 u8 tx_frames_high[0x20];
1479
1480 u8 tx_frames_low[0x20];
1481
1482 u8 rx_pause_high[0x20];
1483
1484 u8 rx_pause_low[0x20];
1485
1486 u8 rx_pause_duration_high[0x20];
1487
1488 u8 rx_pause_duration_low[0x20];
1489
1490 u8 tx_pause_high[0x20];
1491
1492 u8 tx_pause_low[0x20];
1493
1494 u8 tx_pause_duration_high[0x20];
1495
1496 u8 tx_pause_duration_low[0x20];
1497
1498 u8 rx_pause_transition_high[0x20];
1499
1500 u8 rx_pause_transition_low[0x20];
1501
b4ff3a36 1502 u8 reserved_at_3c0[0x400];
e281682b
SM		 1503};
1504
1505struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1506 u8 port_transmit_wait_high[0x20];
1507
1508 u8 port_transmit_wait_low[0x20];
1509
b4ff3a36 1510 u8 reserved_at_40[0x780];
e281682b
SM		 1511};
1512
1513struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1514 u8 dot3stats_alignment_errors_high[0x20];
1515
1516 u8 dot3stats_alignment_errors_low[0x20];
1517
1518 u8 dot3stats_fcs_errors_high[0x20];
1519
1520 u8 dot3stats_fcs_errors_low[0x20];
1521
1522 u8 dot3stats_single_collision_frames_high[0x20];
1523
1524 u8 dot3stats_single_collision_frames_low[0x20];
1525
1526 u8 dot3stats_multiple_collision_frames_high[0x20];
1527
1528 u8 dot3stats_multiple_collision_frames_low[0x20];
1529
1530 u8 dot3stats_sqe_test_errors_high[0x20];
1531
1532 u8 dot3stats_sqe_test_errors_low[0x20];
1533
1534 u8 dot3stats_deferred_transmissions_high[0x20];
1535
1536 u8 dot3stats_deferred_transmissions_low[0x20];
1537
1538 u8 dot3stats_late_collisions_high[0x20];
1539
1540 u8 dot3stats_late_collisions_low[0x20];
1541
1542 u8 dot3stats_excessive_collisions_high[0x20];
1543
1544 u8 dot3stats_excessive_collisions_low[0x20];
1545
1546 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1547
1548 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1549
1550 u8 dot3stats_carrier_sense_errors_high[0x20];
1551
1552 u8 dot3stats_carrier_sense_errors_low[0x20];
1553
1554 u8 dot3stats_frame_too_longs_high[0x20];
1555
1556 u8 dot3stats_frame_too_longs_low[0x20];
1557
1558 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1559
1560 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1561
1562 u8 dot3stats_symbol_errors_high[0x20];
1563
1564 u8 dot3stats_symbol_errors_low[0x20];
1565
1566 u8 dot3control_in_unknown_opcodes_high[0x20];
1567
1568 u8 dot3control_in_unknown_opcodes_low[0x20];
1569
1570 u8 dot3in_pause_frames_high[0x20];
1571
1572 u8 dot3in_pause_frames_low[0x20];
1573
1574 u8 dot3out_pause_frames_high[0x20];
1575
1576 u8 dot3out_pause_frames_low[0x20];
1577
b4ff3a36 1578 u8 reserved_at_400[0x3c0];
e281682b
SM		 1579};
1580
1581struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1582 u8 ether_stats_drop_events_high[0x20];
1583
1584 u8 ether_stats_drop_events_low[0x20];
1585
1586 u8 ether_stats_octets_high[0x20];
1587
1588 u8 ether_stats_octets_low[0x20];
1589
1590 u8 ether_stats_pkts_high[0x20];
1591
1592 u8 ether_stats_pkts_low[0x20];
1593
1594 u8 ether_stats_broadcast_pkts_high[0x20];
1595
1596 u8 ether_stats_broadcast_pkts_low[0x20];
1597
1598 u8 ether_stats_multicast_pkts_high[0x20];
1599
1600 u8 ether_stats_multicast_pkts_low[0x20];
1601
1602 u8 ether_stats_crc_align_errors_high[0x20];
1603
1604 u8 ether_stats_crc_align_errors_low[0x20];
1605
1606 u8 ether_stats_undersize_pkts_high[0x20];
1607
1608 u8 ether_stats_undersize_pkts_low[0x20];
1609
1610 u8 ether_stats_oversize_pkts_high[0x20];
1611
1612 u8 ether_stats_oversize_pkts_low[0x20];
1613
1614 u8 ether_stats_fragments_high[0x20];
1615
1616 u8 ether_stats_fragments_low[0x20];
1617
1618 u8 ether_stats_jabbers_high[0x20];
1619
1620 u8 ether_stats_jabbers_low[0x20];
1621
1622 u8 ether_stats_collisions_high[0x20];
1623
1624 u8 ether_stats_collisions_low[0x20];
1625
1626 u8 ether_stats_pkts64octets_high[0x20];
1627
1628 u8 ether_stats_pkts64octets_low[0x20];
1629
1630 u8 ether_stats_pkts65to127octets_high[0x20];
1631
1632 u8 ether_stats_pkts65to127octets_low[0x20];
1633
1634 u8 ether_stats_pkts128to255octets_high[0x20];
1635
1636 u8 ether_stats_pkts128to255octets_low[0x20];
1637
1638 u8 ether_stats_pkts256to511octets_high[0x20];
1639
1640 u8 ether_stats_pkts256to511octets_low[0x20];
1641
1642 u8 ether_stats_pkts512to1023octets_high[0x20];
1643
1644 u8 ether_stats_pkts512to1023octets_low[0x20];
1645
1646 u8 ether_stats_pkts1024to1518octets_high[0x20];
1647
1648 u8 ether_stats_pkts1024to1518octets_low[0x20];
1649
1650 u8 ether_stats_pkts1519to2047octets_high[0x20];
1651
1652 u8 ether_stats_pkts1519to2047octets_low[0x20];
1653
1654 u8 ether_stats_pkts2048to4095octets_high[0x20];
1655
1656 u8 ether_stats_pkts2048to4095octets_low[0x20];
1657
1658 u8 ether_stats_pkts4096to8191octets_high[0x20];
1659
1660 u8 ether_stats_pkts4096to8191octets_low[0x20];
1661
1662 u8 ether_stats_pkts8192to10239octets_high[0x20];
1663
1664 u8 ether_stats_pkts8192to10239octets_low[0x20];
1665
b4ff3a36 1666 u8 reserved_at_540[0x280];
e281682b
SM		 1667};
1668
1669struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1670 u8 if_in_octets_high[0x20];
1671
1672 u8 if_in_octets_low[0x20];
1673
1674 u8 if_in_ucast_pkts_high[0x20];
1675
1676 u8 if_in_ucast_pkts_low[0x20];
1677
1678 u8 if_in_discards_high[0x20];
1679
1680 u8 if_in_discards_low[0x20];
1681
1682 u8 if_in_errors_high[0x20];
1683
1684 u8 if_in_errors_low[0x20];
1685
1686 u8 if_in_unknown_protos_high[0x20];
1687
1688 u8 if_in_unknown_protos_low[0x20];
1689
1690 u8 if_out_octets_high[0x20];
1691
1692 u8 if_out_octets_low[0x20];
1693
1694 u8 if_out_ucast_pkts_high[0x20];
1695
1696 u8 if_out_ucast_pkts_low[0x20];
1697
1698 u8 if_out_discards_high[0x20];
1699
1700 u8 if_out_discards_low[0x20];
1701
1702 u8 if_out_errors_high[0x20];
1703
1704 u8 if_out_errors_low[0x20];
1705
1706 u8 if_in_multicast_pkts_high[0x20];
1707
1708 u8 if_in_multicast_pkts_low[0x20];
1709
1710 u8 if_in_broadcast_pkts_high[0x20];
1711
1712 u8 if_in_broadcast_pkts_low[0x20];
1713
1714 u8 if_out_multicast_pkts_high[0x20];
1715
1716 u8 if_out_multicast_pkts_low[0x20];
1717
1718 u8 if_out_broadcast_pkts_high[0x20];
1719
1720 u8 if_out_broadcast_pkts_low[0x20];
1721
b4ff3a36 1722 u8 reserved_at_340[0x480];
e281682b
SM		 1723};
1724
1725struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1726 u8 a_frames_transmitted_ok_high[0x20];
1727
1728 u8 a_frames_transmitted_ok_low[0x20];
1729
1730 u8 a_frames_received_ok_high[0x20];
1731
1732 u8 a_frames_received_ok_low[0x20];
1733
1734 u8 a_frame_check_sequence_errors_high[0x20];
1735
1736 u8 a_frame_check_sequence_errors_low[0x20];
1737
1738 u8 a_alignment_errors_high[0x20];
1739
1740 u8 a_alignment_errors_low[0x20];
1741
1742 u8 a_octets_transmitted_ok_high[0x20];
1743
1744 u8 a_octets_transmitted_ok_low[0x20];
1745
1746 u8 a_octets_received_ok_high[0x20];
1747
1748 u8 a_octets_received_ok_low[0x20];
1749
1750 u8 a_multicast_frames_xmitted_ok_high[0x20];
1751
1752 u8 a_multicast_frames_xmitted_ok_low[0x20];
1753
1754 u8 a_broadcast_frames_xmitted_ok_high[0x20];
1755
1756 u8 a_broadcast_frames_xmitted_ok_low[0x20];
1757
1758 u8 a_multicast_frames_received_ok_high[0x20];
1759
1760 u8 a_multicast_frames_received_ok_low[0x20];
1761
1762 u8 a_broadcast_frames_received_ok_high[0x20];
1763
1764 u8 a_broadcast_frames_received_ok_low[0x20];
1765
1766 u8 a_in_range_length_errors_high[0x20];
1767
1768 u8 a_in_range_length_errors_low[0x20];
1769
1770 u8 a_out_of_range_length_field_high[0x20];
1771
1772 u8 a_out_of_range_length_field_low[0x20];
1773
1774 u8 a_frame_too_long_errors_high[0x20];
1775
1776 u8 a_frame_too_long_errors_low[0x20];
1777
1778 u8 a_symbol_error_during_carrier_high[0x20];
1779
1780 u8 a_symbol_error_during_carrier_low[0x20];
1781
1782 u8 a_mac_control_frames_transmitted_high[0x20];
1783
1784 u8 a_mac_control_frames_transmitted_low[0x20];
1785
1786 u8 a_mac_control_frames_received_high[0x20];
1787
1788 u8 a_mac_control_frames_received_low[0x20];
1789
1790 u8 a_unsupported_opcodes_received_high[0x20];
1791
1792 u8 a_unsupported_opcodes_received_low[0x20];
1793
1794 u8 a_pause_mac_ctrl_frames_received_high[0x20];
1795
1796 u8 a_pause_mac_ctrl_frames_received_low[0x20];
1797
1798 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
1799
1800 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
1801
b4ff3a36 1802 u8 reserved_at_4c0[0x300];
e281682b
SM		 1803};
1804
8ed1a630
GP		 1805struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
1806 u8 life_time_counter_high[0x20];
1807
1808 u8 life_time_counter_low[0x20];
1809
1810 u8 rx_errors[0x20];
1811
1812 u8 tx_errors[0x20];
1813
1814 u8 l0_to_recovery_eieos[0x20];
1815
1816 u8 l0_to_recovery_ts[0x20];
1817
1818 u8 l0_to_recovery_framing[0x20];
1819
1820 u8 l0_to_recovery_retrain[0x20];
1821
1822 u8 crc_error_dllp[0x20];
1823
1824 u8 crc_error_tlp[0x20];
1825
1826 u8 reserved_at_140[0x680];
1827};
1828
e281682b
SM		 1829struct mlx5_ifc_cmd_inter_comp_event_bits {
1830 u8 command_completion_vector[0x20];
1831
b4ff3a36 1832 u8 reserved_at_20[0xc0];
e281682b
SM		 1833};
1834
1835struct mlx5_ifc_stall_vl_event_bits {
b4ff3a36 1836 u8 reserved_at_0[0x18];
e281682b 1837 u8 port_num[0x1];
b4ff3a36 1838 u8 reserved_at_19[0x3];
e281682b
SM		 1839 u8 vl[0x4];
1840
b4ff3a36 1841 u8 reserved_at_20[0xa0];
e281682b
SM		 1842};
1843
1844struct mlx5_ifc_db_bf_congestion_event_bits {
1845 u8 event_subtype[0x8];
b4ff3a36 1846 u8 reserved_at_8[0x8];
e281682b 1847 u8 congestion_level[0x8];
b4ff3a36 1848 u8 reserved_at_18[0x8];
e281682b 1849
b4ff3a36 1850 u8 reserved_at_20[0xa0];
e281682b
SM		 1851};
1852
1853struct mlx5_ifc_gpio_event_bits {
b4ff3a36 1854 u8 reserved_at_0[0x60];
e281682b
SM		 1855
1856 u8 gpio_event_hi[0x20];
1857
1858 u8 gpio_event_lo[0x20];
1859
b4ff3a36 1860 u8 reserved_at_a0[0x40];
e281682b
SM		 1861};
1862
1863struct mlx5_ifc_port_state_change_event_bits {
b4ff3a36 1864 u8 reserved_at_0[0x40];
e281682b
SM		 1865
1866 u8 port_num[0x4];
b4ff3a36 1867 u8 reserved_at_44[0x1c];
e281682b 1868
b4ff3a36 1869 u8 reserved_at_60[0x80];
e281682b
SM		 1870};
1871
1872struct mlx5_ifc_dropped_packet_logged_bits {
b4ff3a36 1873 u8 reserved_at_0[0xe0];
e281682b
SM		 1874};
1875
1876enum {
1877 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
1878 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
1879};
1880
1881struct mlx5_ifc_cq_error_bits {
b4ff3a36 1882 u8 reserved_at_0[0x8];
e281682b
SM		 1883 u8 cqn[0x18];
1884
b4ff3a36 1885 u8 reserved_at_20[0x20];
e281682b 1886
b4ff3a36 1887 u8 reserved_at_40[0x18];
e281682b
SM		 1888 u8 syndrome[0x8];
1889
b4ff3a36 1890 u8 reserved_at_60[0x80];
e281682b
SM		 1891};
1892
1893struct mlx5_ifc_rdma_page_fault_event_bits {
1894 u8 bytes_committed[0x20];
1895
1896 u8 r_key[0x20];
1897
b4ff3a36 1898 u8 reserved_at_40[0x10];
e281682b
SM		 1899 u8 packet_len[0x10];
1900
1901 u8 rdma_op_len[0x20];
1902
1903 u8 rdma_va[0x40];
1904
b4ff3a36 1905 u8 reserved_at_c0[0x5];
e281682b
SM		 1906 u8 rdma[0x1];
1907 u8 write[0x1];
1908 u8 requestor[0x1];
1909 u8 qp_number[0x18];
1910};
1911
1912struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1913 u8 bytes_committed[0x20];
1914
b4ff3a36 1915 u8 reserved_at_20[0x10];
e281682b
SM		 1916 u8 wqe_index[0x10];
1917
b4ff3a36 1918 u8 reserved_at_40[0x10];
e281682b
SM		 1919 u8 len[0x10];
1920
b4ff3a36 1921 u8 reserved_at_60[0x60];
e281682b 1922
b4ff3a36 1923 u8 reserved_at_c0[0x5];
e281682b
SM		 1924 u8 rdma[0x1];
1925 u8 write_read[0x1];
1926 u8 requestor[0x1];
1927 u8 qpn[0x18];
1928};
1929
1930struct mlx5_ifc_qp_events_bits {
b4ff3a36 1931 u8 reserved_at_0[0xa0];
e281682b
SM		 1932
1933 u8 type[0x8];
b4ff3a36 1934 u8 reserved_at_a8[0x18];
e281682b 1935
b4ff3a36 1936 u8 reserved_at_c0[0x8];
e281682b
SM		 1937 u8 qpn_rqn_sqn[0x18];
1938};
1939
1940struct mlx5_ifc_dct_events_bits {
b4ff3a36 1941 u8 reserved_at_0[0xc0];
e281682b 1942
b4ff3a36 1943 u8 reserved_at_c0[0x8];
e281682b
SM		 1944 u8 dct_number[0x18];
1945};
1946
1947struct mlx5_ifc_comp_event_bits {
b4ff3a36 1948 u8 reserved_at_0[0xc0];
e281682b 1949
b4ff3a36 1950 u8 reserved_at_c0[0x8];
e281682b
SM		 1951 u8 cq_number[0x18];
1952};
1953
1954enum {
1955 MLX5_QPC_STATE_RST = 0x0,
1956 MLX5_QPC_STATE_INIT = 0x1,
1957 MLX5_QPC_STATE_RTR = 0x2,
1958 MLX5_QPC_STATE_RTS = 0x3,
1959 MLX5_QPC_STATE_SQER = 0x4,
1960 MLX5_QPC_STATE_ERR = 0x6,
1961 MLX5_QPC_STATE_SQD = 0x7,
1962 MLX5_QPC_STATE_SUSPENDED = 0x9,
1963};
1964
1965enum {
1966 MLX5_QPC_ST_RC = 0x0,
1967 MLX5_QPC_ST_UC = 0x1,
1968 MLX5_QPC_ST_UD = 0x2,
1969 MLX5_QPC_ST_XRC = 0x3,
1970 MLX5_QPC_ST_DCI = 0x5,
1971 MLX5_QPC_ST_QP0 = 0x7,
1972 MLX5_QPC_ST_QP1 = 0x8,
1973 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
1974 MLX5_QPC_ST_REG_UMR = 0xc,
1975};
1976
1977enum {
1978 MLX5_QPC_PM_STATE_ARMED = 0x0,
1979 MLX5_QPC_PM_STATE_REARM = 0x1,
1980 MLX5_QPC_PM_STATE_RESERVED = 0x2,
1981 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
1982};
1983
1984enum {
1985 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
1986 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
1987};
1988
1989enum {
1990 MLX5_QPC_MTU_256_BYTES = 0x1,
1991 MLX5_QPC_MTU_512_BYTES = 0x2,
1992 MLX5_QPC_MTU_1K_BYTES = 0x3,
1993 MLX5_QPC_MTU_2K_BYTES = 0x4,
1994 MLX5_QPC_MTU_4K_BYTES = 0x5,
1995 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
1996};
1997
1998enum {
1999 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
2000 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
2001 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
2002 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
2003 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
2004 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
2005 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
2006 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
2007};
2008
2009enum {
2010 MLX5_QPC_CS_REQ_DISABLE = 0x0,
2011 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
2012 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
2013};
2014
2015enum {
2016 MLX5_QPC_CS_RES_DISABLE = 0x0,
2017 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
2018 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
2019};
2020
2021struct mlx5_ifc_qpc_bits {
2022 u8 state[0x4];
84df61eb 2023 u8 lag_tx_port_affinity[0x4];
e281682b 2024 u8 st[0x8];
b4ff3a36 2025 u8 reserved_at_10[0x3];
e281682b 2026 u8 pm_state[0x2];
b4ff3a36 2027 u8 reserved_at_15[0x7];
e281682b 2028 u8 end_padding_mode[0x2];
b4ff3a36 2029 u8 reserved_at_1e[0x2];
e281682b
SM		 2030
2031 u8 wq_signature[0x1];
2032 u8 block_lb_mc[0x1];
2033 u8 atomic_like_write_en[0x1];
2034 u8 latency_sensitive[0x1];
b4ff3a36 2035 u8 reserved_at_24[0x1];
e281682b 2036 u8 drain_sigerr[0x1];
b4ff3a36 2037 u8 reserved_at_26[0x2];
e281682b
SM		 2038 u8 pd[0x18];
2039
2040 u8 mtu[0x3];
2041 u8 log_msg_max[0x5];
b4ff3a36 2042 u8 reserved_at_48[0x1];
e281682b
SM		 2043 u8 log_rq_size[0x4];
2044 u8 log_rq_stride[0x3];
2045 u8 no_sq[0x1];
2046 u8 log_sq_size[0x4];
b4ff3a36 2047 u8 reserved_at_55[0x6];
e281682b 2048 u8 rlky[0x1];
1015c2e8 2049 u8 ulp_stateless_offload_mode[0x4];
e281682b
SM		 2050
2051 u8 counter_set_id[0x8];
2052 u8 uar_page[0x18];
2053
b4ff3a36 2054 u8 reserved_at_80[0x8];
e281682b
SM		 2055 u8 user_index[0x18];
2056
b4ff3a36 2057 u8 reserved_at_a0[0x3];
e281682b
SM		 2058 u8 log_page_size[0x5];
2059 u8 remote_qpn[0x18];
2060
2061 struct mlx5_ifc_ads_bits primary_address_path;
2062
2063 struct mlx5_ifc_ads_bits secondary_address_path;
2064
2065 u8 log_ack_req_freq[0x4];
b4ff3a36 2066 u8 reserved_at_384[0x4];
e281682b 2067 u8 log_sra_max[0x3];
b4ff3a36 2068 u8 reserved_at_38b[0x2];
e281682b
SM		 2069 u8 retry_count[0x3];
2070 u8 rnr_retry[0x3];
b4ff3a36 2071 u8 reserved_at_393[0x1];
e281682b
SM		 2072 u8 fre[0x1];
2073 u8 cur_rnr_retry[0x3];
2074 u8 cur_retry_count[0x3];
b4ff3a36 2075 u8 reserved_at_39b[0x5];
e281682b 2076
b4ff3a36 2077 u8 reserved_at_3a0[0x20];
e281682b 2078
b4ff3a36 2079 u8 reserved_at_3c0[0x8];
e281682b
SM		 2080 u8 next_send_psn[0x18];
2081
b4ff3a36 2082 u8 reserved_at_3e0[0x8];
e281682b
SM		 2083 u8 cqn_snd[0x18];
2084
09a7d9ec
SM		 2085 u8 reserved_at_400[0x8];
2086 u8 deth_sqpn[0x18];
2087
2088 u8 reserved_at_420[0x20];
e281682b 2089
b4ff3a36 2090 u8 reserved_at_440[0x8];
e281682b
SM		 2091 u8 last_acked_psn[0x18];
2092
b4ff3a36 2093 u8 reserved_at_460[0x8];
e281682b
SM		 2094 u8 ssn[0x18];
2095
b4ff3a36 2096 u8 reserved_at_480[0x8];
e281682b 2097 u8 log_rra_max[0x3];
b4ff3a36 2098 u8 reserved_at_48b[0x1];
e281682b
SM		 2099 u8 atomic_mode[0x4];
2100 u8 rre[0x1];
2101 u8 rwe[0x1];
2102 u8 rae[0x1];
b4ff3a36 2103 u8 reserved_at_493[0x1];
e281682b 2104 u8 page_offset[0x6];
b4ff3a36 2105 u8 reserved_at_49a[0x3];
e281682b
SM		 2106 u8 cd_slave_receive[0x1];
2107 u8 cd_slave_send[0x1];
2108 u8 cd_master[0x1];
2109
b4ff3a36 2110 u8 reserved_at_4a0[0x3];
e281682b
SM		 2111 u8 min_rnr_nak[0x5];
2112 u8 next_rcv_psn[0x18];
2113
b4ff3a36 2114 u8 reserved_at_4c0[0x8];
e281682b
SM		 2115 u8 xrcd[0x18];
2116
b4ff3a36 2117 u8 reserved_at_4e0[0x8];
e281682b
SM		 2118 u8 cqn_rcv[0x18];
2119
2120 u8 dbr_addr[0x40];
2121
2122 u8 q_key[0x20];
2123
b4ff3a36 2124 u8 reserved_at_560[0x5];
e281682b 2125 u8 rq_type[0x3];
7486216b 2126 u8 srqn_rmpn_xrqn[0x18];
e281682b 2127
b4ff3a36 2128 u8 reserved_at_580[0x8];
e281682b
SM		 2129 u8 rmsn[0x18];
2130
2131 u8 hw_sq_wqebb_counter[0x10];
2132 u8 sw_sq_wqebb_counter[0x10];
2133
2134 u8 hw_rq_counter[0x20];
2135
2136 u8 sw_rq_counter[0x20];
2137
b4ff3a36 2138 u8 reserved_at_600[0x20];
e281682b 2139
b4ff3a36 2140 u8 reserved_at_620[0xf];
e281682b
SM		 2141 u8 cgs[0x1];
2142 u8 cs_req[0x8];
2143 u8 cs_res[0x8];
2144
2145 u8 dc_access_key[0x40];
2146
b4ff3a36 2147 u8 reserved_at_680[0xc0];
e281682b
SM		 2148};
2149
2150struct mlx5_ifc_roce_addr_layout_bits {
2151 u8 source_l3_address[16][0x8];
2152
b4ff3a36 2153 u8 reserved_at_80[0x3];
e281682b
SM		 2154 u8 vlan_valid[0x1];
2155 u8 vlan_id[0xc];
2156 u8 source_mac_47_32[0x10];
2157
2158 u8 source_mac_31_0[0x20];
2159
b4ff3a36 2160 u8 reserved_at_c0[0x14];
e281682b
SM		 2161 u8 roce_l3_type[0x4];
2162 u8 roce_version[0x8];
2163
b4ff3a36 2164 u8 reserved_at_e0[0x20];
e281682b
SM		 2165};
2166
2167union mlx5_ifc_hca_cap_union_bits {
2168 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2169 struct mlx5_ifc_odp_cap_bits odp_cap;
2170 struct mlx5_ifc_atomic_caps_bits atomic_caps;
2171 struct mlx5_ifc_roce_cap_bits roce_cap;
2172 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2173 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
495716b1 2174 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
d6666753 2175 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
3f0393a5 2176 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
7486216b 2177 struct mlx5_ifc_qos_cap_bits qos_cap;
b4ff3a36 2178 u8 reserved_at_0[0x8000];
e281682b
SM		 2179};
2180
2181enum {
2182 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
2183 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
2184 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
9dc0b289 2185 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
7adbde20
HHZ		 2186 MLX5_FLOW_CONTEXT_ACTION_ENCAP = 0x10,
2187 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
e281682b
SM		 2188};
2189
2190struct mlx5_ifc_flow_context_bits {
b4ff3a36 2191 u8 reserved_at_0[0x20];
e281682b
SM		 2192
2193 u8 group_id[0x20];
2194
b4ff3a36 2195 u8 reserved_at_40[0x8];
e281682b
SM		 2196 u8 flow_tag[0x18];
2197
b4ff3a36 2198 u8 reserved_at_60[0x10];
e281682b
SM		 2199 u8 action[0x10];
2200
b4ff3a36 2201 u8 reserved_at_80[0x8];
e281682b
SM		 2202 u8 destination_list_size[0x18];
2203
9dc0b289
AV		 2204 u8 reserved_at_a0[0x8];
2205 u8 flow_counter_list_size[0x18];
2206
7adbde20
HHZ		 2207 u8 encap_id[0x20];
2208
2209 u8 reserved_at_e0[0x120];
e281682b
SM		 2210
2211 struct mlx5_ifc_fte_match_param_bits match_value;
2212
b4ff3a36 2213 u8 reserved_at_1200[0x600];
e281682b 2214
9dc0b289 2215 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
e281682b
SM		 2216};
2217
2218enum {
2219 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
2220 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
2221};
2222
2223struct mlx5_ifc_xrc_srqc_bits {
2224 u8 state[0x4];
2225 u8 log_xrc_srq_size[0x4];
b4ff3a36 2226 u8 reserved_at_8[0x18];
e281682b
SM		 2227
2228 u8 wq_signature[0x1];
2229 u8 cont_srq[0x1];
b4ff3a36 2230 u8 reserved_at_22[0x1];
e281682b
SM		 2231 u8 rlky[0x1];
2232 u8 basic_cyclic_rcv_wqe[0x1];
2233 u8 log_rq_stride[0x3];
2234 u8 xrcd[0x18];
2235
2236 u8 page_offset[0x6];
b4ff3a36 2237 u8 reserved_at_46[0x2];
e281682b
SM		 2238 u8 cqn[0x18];
2239
b4ff3a36 2240 u8 reserved_at_60[0x20];
e281682b
SM		 2241
2242 u8 user_index_equal_xrc_srqn[0x1];
b4ff3a36 2243 u8 reserved_at_81[0x1];
e281682b
SM		 2244 u8 log_page_size[0x6];
2245 u8 user_index[0x18];
2246
b4ff3a36 2247 u8 reserved_at_a0[0x20];
e281682b 2248
b4ff3a36 2249 u8 reserved_at_c0[0x8];
e281682b
SM		 2250 u8 pd[0x18];
2251
2252 u8 lwm[0x10];
2253 u8 wqe_cnt[0x10];
2254
b4ff3a36 2255 u8 reserved_at_100[0x40];
e281682b
SM		 2256
2257 u8 db_record_addr_h[0x20];
2258
2259 u8 db_record_addr_l[0x1e];
b4ff3a36 2260 u8 reserved_at_17e[0x2];
e281682b 2261
b4ff3a36 2262 u8 reserved_at_180[0x80];
e281682b
SM		 2263};
2264
2265struct mlx5_ifc_traffic_counter_bits {
2266 u8 packets[0x40];
2267
2268 u8 octets[0x40];
2269};
2270
2271struct mlx5_ifc_tisc_bits {
84df61eb
AH		 2272 u8 strict_lag_tx_port_affinity[0x1];
2273 u8 reserved_at_1[0x3];
2274 u8 lag_tx_port_affinity[0x04];
2275
2276 u8 reserved_at_8[0x4];
e281682b 2277 u8 prio[0x4];
b4ff3a36 2278 u8 reserved_at_10[0x10];
e281682b 2279
b4ff3a36 2280 u8 reserved_at_20[0x100];
e281682b 2281
b4ff3a36 2282 u8 reserved_at_120[0x8];
e281682b
SM		 2283 u8 transport_domain[0x18];
2284
b4ff3a36 2285 u8 reserved_at_140[0x3c0];
e281682b
SM		 2286};
2287
2288enum {
2289 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2290 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2291};
2292
2293enum {
2294 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2295 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2296};
2297
2298enum {
2be6967c
SM		 2299 MLX5_RX_HASH_FN_NONE = 0x0,
2300 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
2301 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
e281682b
SM		 2302};
2303
2304enum {
2305 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1,
2306 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2,
2307};
2308
2309struct mlx5_ifc_tirc_bits {
b4ff3a36 2310 u8 reserved_at_0[0x20];
e281682b
SM		 2311
2312 u8 disp_type[0x4];
b4ff3a36 2313 u8 reserved_at_24[0x1c];
e281682b 2314
b4ff3a36 2315 u8 reserved_at_40[0x40];
e281682b 2316
b4ff3a36 2317 u8 reserved_at_80[0x4];
e281682b
SM		 2318 u8 lro_timeout_period_usecs[0x10];
2319 u8 lro_enable_mask[0x4];
2320 u8 lro_max_ip_payload_size[0x8];
2321
b4ff3a36 2322 u8 reserved_at_a0[0x40];
e281682b 2323
b4ff3a36 2324 u8 reserved_at_e0[0x8];
e281682b
SM		 2325 u8 inline_rqn[0x18];
2326
2327 u8 rx_hash_symmetric[0x1];
b4ff3a36 2328 u8 reserved_at_101[0x1];
e281682b 2329 u8 tunneled_offload_en[0x1];
b4ff3a36 2330 u8 reserved_at_103[0x5];
e281682b
SM		 2331 u8 indirect_table[0x18];
2332
2333 u8 rx_hash_fn[0x4];
b4ff3a36 2334 u8 reserved_at_124[0x2];
e281682b
SM		 2335 u8 self_lb_block[0x2];
2336 u8 transport_domain[0x18];
2337
2338 u8 rx_hash_toeplitz_key[10][0x20];
2339
2340 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2341
2342 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2343
b4ff3a36 2344 u8 reserved_at_2c0[0x4c0];
e281682b
SM		 2345};
2346
2347enum {
2348 MLX5_SRQC_STATE_GOOD = 0x0,
2349 MLX5_SRQC_STATE_ERROR = 0x1,
2350};
2351
2352struct mlx5_ifc_srqc_bits {
2353 u8 state[0x4];
2354 u8 log_srq_size[0x4];
b4ff3a36 2355 u8 reserved_at_8[0x18];
e281682b
SM		 2356
2357 u8 wq_signature[0x1];
2358 u8 cont_srq[0x1];
b4ff3a36 2359 u8 reserved_at_22[0x1];
e281682b 2360 u8 rlky[0x1];
b4ff3a36 2361 u8 reserved_at_24[0x1];
e281682b
SM		 2362 u8 log_rq_stride[0x3];
2363 u8 xrcd[0x18];
2364
2365 u8 page_offset[0x6];
b4ff3a36 2366 u8 reserved_at_46[0x2];
e281682b
SM		 2367 u8 cqn[0x18];
2368
b4ff3a36 2369 u8 reserved_at_60[0x20];
e281682b 2370
b4ff3a36 2371 u8 reserved_at_80[0x2];
e281682b 2372 u8 log_page_size[0x6];
b4ff3a36 2373 u8 reserved_at_88[0x18];
e281682b 2374
b4ff3a36 2375 u8 reserved_at_a0[0x20];
e281682b 2376
b4ff3a36 2377 u8 reserved_at_c0[0x8];
e281682b
SM		 2378 u8 pd[0x18];
2379
2380 u8 lwm[0x10];
2381 u8 wqe_cnt[0x10];
2382
b4ff3a36 2383 u8 reserved_at_100[0x40];
e281682b 2384
01949d01 2385 u8 dbr_addr[0x40];
e281682b 2386
b4ff3a36 2387 u8 reserved_at_180[0x80];
e281682b
SM		 2388};
2389
2390enum {
2391 MLX5_SQC_STATE_RST = 0x0,
2392 MLX5_SQC_STATE_RDY = 0x1,
2393 MLX5_SQC_STATE_ERR = 0x3,
2394};
2395
2396struct mlx5_ifc_sqc_bits {
2397 u8 rlky[0x1];
2398 u8 cd_master[0x1];
2399 u8 fre[0x1];
2400 u8 flush_in_error_en[0x1];
cff92d7c
HHZ		 2401 u8 reserved_at_4[0x1];
2402 u8 min_wqe_inline_mode[0x3];
e281682b 2403 u8 state[0x4];
7d5e1423
SM		 2404 u8 reg_umr[0x1];
2405 u8 reserved_at_d[0x13];
e281682b 2406
b4ff3a36 2407 u8 reserved_at_20[0x8];
e281682b
SM		 2408 u8 user_index[0x18];
2409
b4ff3a36 2410 u8 reserved_at_40[0x8];
e281682b
SM		 2411 u8 cqn[0x18];
2412
7486216b 2413 u8 reserved_at_60[0x90];
e281682b 2414
7486216b 2415 u8 packet_pacing_rate_limit_index[0x10];
e281682b 2416 u8 tis_lst_sz[0x10];
b4ff3a36 2417 u8 reserved_at_110[0x10];
e281682b 2418
b4ff3a36 2419 u8 reserved_at_120[0x40];
e281682b 2420
b4ff3a36 2421 u8 reserved_at_160[0x8];
e281682b
SM		 2422 u8 tis_num_0[0x18];
2423
2424 struct mlx5_ifc_wq_bits wq;
2425};
2426
813f8540
MHY		 2427enum {
2428 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2429 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2430 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2431 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2432};
2433
2434struct mlx5_ifc_scheduling_context_bits {
2435 u8 element_type[0x8];
2436 u8 reserved_at_8[0x18];
2437
2438 u8 element_attributes[0x20];
2439
2440 u8 parent_element_id[0x20];
2441
2442 u8 reserved_at_60[0x40];
2443
2444 u8 bw_share[0x20];
2445
2446 u8 max_average_bw[0x20];
2447
2448 u8 reserved_at_e0[0x120];
2449};
2450
e281682b 2451struct mlx5_ifc_rqtc_bits {
b4ff3a36 2452 u8 reserved_at_0[0xa0];
e281682b 2453
b4ff3a36 2454 u8 reserved_at_a0[0x10];
e281682b
SM		 2455 u8 rqt_max_size[0x10];
2456
b4ff3a36 2457 u8 reserved_at_c0[0x10];
e281682b
SM		 2458 u8 rqt_actual_size[0x10];
2459
b4ff3a36 2460 u8 reserved_at_e0[0x6a0];
e281682b
SM		 2461
2462 struct mlx5_ifc_rq_num_bits rq_num[0];
2463};
2464
2465enum {
2466 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2467 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2468};
2469
2470enum {
2471 MLX5_RQC_STATE_RST = 0x0,
2472 MLX5_RQC_STATE_RDY = 0x1,
2473 MLX5_RQC_STATE_ERR = 0x3,
2474};
2475
2476struct mlx5_ifc_rqc_bits {
2477 u8 rlky[0x1];
7d5e1423
SM		 2478 u8 reserved_at_1[0x1];
2479 u8 scatter_fcs[0x1];
e281682b
SM		 2480 u8 vsd[0x1];
2481 u8 mem_rq_type[0x4];
2482 u8 state[0x4];
b4ff3a36 2483 u8 reserved_at_c[0x1];
e281682b 2484 u8 flush_in_error_en[0x1];
b4ff3a36 2485 u8 reserved_at_e[0x12];
e281682b 2486
b4ff3a36 2487 u8 reserved_at_20[0x8];
e281682b
SM		 2488 u8 user_index[0x18];
2489
b4ff3a36 2490 u8 reserved_at_40[0x8];
e281682b
SM		 2491 u8 cqn[0x18];
2492
2493 u8 counter_set_id[0x8];
b4ff3a36 2494 u8 reserved_at_68[0x18];
e281682b 2495
b4ff3a36 2496 u8 reserved_at_80[0x8];
e281682b
SM		 2497 u8 rmpn[0x18];
2498
b4ff3a36 2499 u8 reserved_at_a0[0xe0];
e281682b
SM		 2500
2501 struct mlx5_ifc_wq_bits wq;
2502};
2503
2504enum {
2505 MLX5_RMPC_STATE_RDY = 0x1,
2506 MLX5_RMPC_STATE_ERR = 0x3,
2507};
2508
2509struct mlx5_ifc_rmpc_bits {
b4ff3a36 2510 u8 reserved_at_0[0x8];
e281682b 2511 u8 state[0x4];
b4ff3a36 2512 u8 reserved_at_c[0x14];
e281682b
SM		 2513
2514 u8 basic_cyclic_rcv_wqe[0x1];
b4ff3a36 2515 u8 reserved_at_21[0x1f];
e281682b 2516
b4ff3a36 2517 u8 reserved_at_40[0x140];
e281682b
SM		 2518
2519 struct mlx5_ifc_wq_bits wq;
2520};
2521
e281682b 2522struct mlx5_ifc_nic_vport_context_bits {
cff92d7c
HHZ		 2523 u8 reserved_at_0[0x5];
2524 u8 min_wqe_inline_mode[0x3];
2525 u8 reserved_at_8[0x17];
e281682b
SM		 2526 u8 roce_en[0x1];
2527
d82b7318 2528 u8 arm_change_event[0x1];
b4ff3a36 2529 u8 reserved_at_21[0x1a];
d82b7318
SM		 2530 u8 event_on_mtu[0x1];
2531 u8 event_on_promisc_change[0x1];
2532 u8 event_on_vlan_change[0x1];
2533 u8 event_on_mc_address_change[0x1];
2534 u8 event_on_uc_address_change[0x1];
e281682b 2535
b4ff3a36 2536 u8 reserved_at_40[0xf0];
d82b7318
SM		 2537
2538 u8 mtu[0x10];
2539
9efa7525
AS		 2540 u8 system_image_guid[0x40];
2541 u8 port_guid[0x40];
2542 u8 node_guid[0x40];
2543
b4ff3a36 2544 u8 reserved_at_200[0x140];
9efa7525 2545 u8 qkey_violation_counter[0x10];
b4ff3a36 2546 u8 reserved_at_350[0x430];
d82b7318
SM		 2547
2548 u8 promisc_uc[0x1];
2549 u8 promisc_mc[0x1];
2550 u8 promisc_all[0x1];
b4ff3a36 2551 u8 reserved_at_783[0x2];
e281682b 2552 u8 allowed_list_type[0x3];
b4ff3a36 2553 u8 reserved_at_788[0xc];
e281682b
SM		 2554 u8 allowed_list_size[0xc];
2555
2556 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2557
b4ff3a36 2558 u8 reserved_at_7e0[0x20];
e281682b
SM		 2559
2560 u8 current_uc_mac_address[0][0x40];
2561};
2562
2563enum {
2564 MLX5_MKC_ACCESS_MODE_PA = 0x0,
2565 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
2566 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
bcda1aca 2567 MLX5_MKC_ACCESS_MODE_KSM = 0x3,
e281682b
SM		 2568};
2569
2570struct mlx5_ifc_mkc_bits {
b4ff3a36 2571 u8 reserved_at_0[0x1];
e281682b 2572 u8 free[0x1];
b4ff3a36 2573 u8 reserved_at_2[0xd];
e281682b
SM		 2574 u8 small_fence_on_rdma_read_response[0x1];
2575 u8 umr_en[0x1];
2576 u8 a[0x1];
2577 u8 rw[0x1];
2578 u8 rr[0x1];
2579 u8 lw[0x1];
2580 u8 lr[0x1];
2581 u8 access_mode[0x2];
b4ff3a36 2582 u8 reserved_at_18[0x8];
e281682b
SM		 2583
2584 u8 qpn[0x18];
2585 u8 mkey_7_0[0x8];
2586
b4ff3a36 2587 u8 reserved_at_40[0x20];
e281682b
SM		 2588
2589 u8 length64[0x1];
2590 u8 bsf_en[0x1];
2591 u8 sync_umr[0x1];
b4ff3a36 2592 u8 reserved_at_63[0x2];
e281682b 2593 u8 expected_sigerr_count[0x1];
b4ff3a36 2594 u8 reserved_at_66[0x1];
e281682b
SM		 2595 u8 en_rinval[0x1];
2596 u8 pd[0x18];
2597
2598 u8 start_addr[0x40];
2599
2600 u8 len[0x40];
2601
2602 u8 bsf_octword_size[0x20];
2603
b4ff3a36 2604 u8 reserved_at_120[0x80];
e281682b
SM		 2605
2606 u8 translations_octword_size[0x20];
2607
b4ff3a36 2608 u8 reserved_at_1c0[0x1b];
e281682b
SM		 2609 u8 log_page_size[0x5];
2610
b4ff3a36 2611 u8 reserved_at_1e0[0x20];
e281682b
SM		 2612};
2613
2614struct mlx5_ifc_pkey_bits {
b4ff3a36 2615 u8 reserved_at_0[0x10];
e281682b
SM		 2616 u8 pkey[0x10];
2617};
2618
2619struct mlx5_ifc_array128_auto_bits {
2620 u8 array128_auto[16][0x8];
2621};
2622
2623struct mlx5_ifc_hca_vport_context_bits {
2624 u8 field_select[0x20];
2625
b4ff3a36 2626 u8 reserved_at_20[0xe0];
e281682b
SM		 2627
2628 u8 sm_virt_aware[0x1];
2629 u8 has_smi[0x1];
2630 u8 has_raw[0x1];
2631 u8 grh_required[0x1];
b4ff3a36 2632 u8 reserved_at_104[0xc];
707c4602
MD		 2633 u8 port_physical_state[0x4];
2634 u8 vport_state_policy[0x4];
2635 u8 port_state[0x4];
e281682b
SM		 2636 u8 vport_state[0x4];
2637
b4ff3a36 2638 u8 reserved_at_120[0x20];
707c4602
MD		 2639
2640 u8 system_image_guid[0x40];
e281682b
SM		 2641
2642 u8 port_guid[0x40];
2643
2644 u8 node_guid[0x40];
2645
2646 u8 cap_mask1[0x20];
2647
2648 u8 cap_mask1_field_select[0x20];
2649
2650 u8 cap_mask2[0x20];
2651
2652 u8 cap_mask2_field_select[0x20];
2653
b4ff3a36 2654 u8 reserved_at_280[0x80];
e281682b
SM		 2655
2656 u8 lid[0x10];
b4ff3a36 2657 u8 reserved_at_310[0x4];
e281682b
SM		 2658 u8 init_type_reply[0x4];
2659 u8 lmc[0x3];
2660 u8 subnet_timeout[0x5];
2661
2662 u8 sm_lid[0x10];
2663 u8 sm_sl[0x4];
b4ff3a36 2664 u8 reserved_at_334[0xc];
e281682b
SM		 2665
2666 u8 qkey_violation_counter[0x10];
2667 u8 pkey_violation_counter[0x10];
2668
b4ff3a36 2669 u8 reserved_at_360[0xca0];
e281682b
SM		 2670};
2671
d6666753 2672struct mlx5_ifc_esw_vport_context_bits {
b4ff3a36 2673 u8 reserved_at_0[0x3];
d6666753
SM		 2674 u8 vport_svlan_strip[0x1];
2675 u8 vport_cvlan_strip[0x1];
2676 u8 vport_svlan_insert[0x1];
2677 u8 vport_cvlan_insert[0x2];
b4ff3a36 2678 u8 reserved_at_8[0x18];
d6666753 2679
b4ff3a36 2680 u8 reserved_at_20[0x20];
d6666753
SM		 2681
2682 u8 svlan_cfi[0x1];
2683 u8 svlan_pcp[0x3];
2684 u8 svlan_id[0xc];
2685 u8 cvlan_cfi[0x1];
2686 u8 cvlan_pcp[0x3];
2687 u8 cvlan_id[0xc];
2688
b4ff3a36 2689 u8 reserved_at_60[0x7a0];
d6666753
SM		 2690};
2691
e281682b
SM		 2692enum {
2693 MLX5_EQC_STATUS_OK = 0x0,
2694 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
2695};
2696
2697enum {
2698 MLX5_EQC_ST_ARMED = 0x9,
2699 MLX5_EQC_ST_FIRED = 0xa,
2700};
2701
2702struct mlx5_ifc_eqc_bits {
2703 u8 status[0x4];
b4ff3a36 2704 u8 reserved_at_4[0x9];
e281682b
SM		 2705 u8 ec[0x1];
2706 u8 oi[0x1];
b4ff3a36 2707 u8 reserved_at_f[0x5];
e281682b 2708 u8 st[0x4];
b4ff3a36 2709 u8 reserved_at_18[0x8];
e281682b 2710
b4ff3a36 2711 u8 reserved_at_20[0x20];
e281682b 2712
b4ff3a36 2713 u8 reserved_at_40[0x14];
e281682b 2714 u8 page_offset[0x6];
b4ff3a36 2715 u8 reserved_at_5a[0x6];
e281682b 2716
b4ff3a36 2717 u8 reserved_at_60[0x3];
e281682b
SM		 2718 u8 log_eq_size[0x5];
2719 u8 uar_page[0x18];
2720
b4ff3a36 2721 u8 reserved_at_80[0x20];
e281682b 2722
b4ff3a36 2723 u8 reserved_at_a0[0x18];
e281682b
SM		 2724 u8 intr[0x8];
2725
b4ff3a36 2726 u8 reserved_at_c0[0x3];
e281682b 2727 u8 log_page_size[0x5];
b4ff3a36 2728 u8 reserved_at_c8[0x18];
e281682b 2729
b4ff3a36 2730 u8 reserved_at_e0[0x60];
e281682b 2731
b4ff3a36 2732 u8 reserved_at_140[0x8];
e281682b
SM		 2733 u8 consumer_counter[0x18];
2734
b4ff3a36 2735 u8 reserved_at_160[0x8];
e281682b
SM		 2736 u8 producer_counter[0x18];
2737
b4ff3a36 2738 u8 reserved_at_180[0x80];
e281682b
SM		 2739};
2740
2741enum {
2742 MLX5_DCTC_STATE_ACTIVE = 0x0,
2743 MLX5_DCTC_STATE_DRAINING = 0x1,
2744 MLX5_DCTC_STATE_DRAINED = 0x2,
2745};
2746
2747enum {
2748 MLX5_DCTC_CS_RES_DISABLE = 0x0,
2749 MLX5_DCTC_CS_RES_NA = 0x1,
2750 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
2751};
2752
2753enum {
2754 MLX5_DCTC_MTU_256_BYTES = 0x1,
2755 MLX5_DCTC_MTU_512_BYTES = 0x2,
2756 MLX5_DCTC_MTU_1K_BYTES = 0x3,
2757 MLX5_DCTC_MTU_2K_BYTES = 0x4,
2758 MLX5_DCTC_MTU_4K_BYTES = 0x5,
2759};
2760
2761struct mlx5_ifc_dctc_bits {
b4ff3a36 2762 u8 reserved_at_0[0x4];
e281682b 2763 u8 state[0x4];
b4ff3a36 2764 u8 reserved_at_8[0x18];
e281682b 2765
b4ff3a36 2766 u8 reserved_at_20[0x8];
e281682b
SM		 2767 u8 user_index[0x18];
2768
b4ff3a36 2769 u8 reserved_at_40[0x8];
e281682b
SM		 2770 u8 cqn[0x18];
2771
2772 u8 counter_set_id[0x8];
2773 u8 atomic_mode[0x4];
2774 u8 rre[0x1];
2775 u8 rwe[0x1];
2776 u8 rae[0x1];
2777 u8 atomic_like_write_en[0x1];
2778 u8 latency_sensitive[0x1];
2779 u8 rlky[0x1];
2780 u8 free_ar[0x1];
b4ff3a36 2781 u8 reserved_at_73[0xd];
e281682b 2782
b4ff3a36 2783 u8 reserved_at_80[0x8];
e281682b 2784 u8 cs_res[0x8];
b4ff3a36 2785 u8 reserved_at_90[0x3];
e281682b 2786 u8 min_rnr_nak[0x5];
b4ff3a36 2787 u8 reserved_at_98[0x8];
e281682b 2788
b4ff3a36 2789 u8 reserved_at_a0[0x8];
7486216b 2790 u8 srqn_xrqn[0x18];
e281682b 2791
b4ff3a36 2792 u8 reserved_at_c0[0x8];
e281682b
SM		 2793 u8 pd[0x18];
2794
2795 u8 tclass[0x8];
b4ff3a36 2796 u8 reserved_at_e8[0x4];
e281682b
SM		 2797 u8 flow_label[0x14];
2798
2799 u8 dc_access_key[0x40];
2800
b4ff3a36 2801 u8 reserved_at_140[0x5];
e281682b
SM		 2802 u8 mtu[0x3];
2803 u8 port[0x8];
2804 u8 pkey_index[0x10];
2805
b4ff3a36 2806 u8 reserved_at_160[0x8];
e281682b 2807 u8 my_addr_index[0x8];
b4ff3a36 2808 u8 reserved_at_170[0x8];
e281682b
SM		 2809 u8 hop_limit[0x8];
2810
2811 u8 dc_access_key_violation_count[0x20];
2812
b4ff3a36 2813 u8 reserved_at_1a0[0x14];
e281682b
SM		 2814 u8 dei_cfi[0x1];
2815 u8 eth_prio[0x3];
2816 u8 ecn[0x2];
2817 u8 dscp[0x6];
2818
b4ff3a36 2819 u8 reserved_at_1c0[0x40];
e281682b
SM		 2820};
2821
2822enum {
2823 MLX5_CQC_STATUS_OK = 0x0,
2824 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
2825 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
2826};
2827
2828enum {
2829 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
2830 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
2831};
2832
2833enum {
2834 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
2835 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
2836 MLX5_CQC_ST_FIRED = 0xa,
2837};
2838
7d5e1423
SM		 2839enum {
2840 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
2841 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
7486216b 2842 MLX5_CQ_PERIOD_NUM_MODES
7d5e1423
SM		 2843};
2844
e281682b
SM		 2845struct mlx5_ifc_cqc_bits {
2846 u8 status[0x4];
b4ff3a36 2847 u8 reserved_at_4[0x4];
e281682b
SM		 2848 u8 cqe_sz[0x3];
2849 u8 cc[0x1];
b4ff3a36 2850 u8 reserved_at_c[0x1];
e281682b
SM		 2851 u8 scqe_break_moderation_en[0x1];
2852 u8 oi[0x1];
7d5e1423
SM		 2853 u8 cq_period_mode[0x2];
2854 u8 cqe_comp_en[0x1];
e281682b
SM		 2855 u8 mini_cqe_res_format[0x2];
2856 u8 st[0x4];
b4ff3a36 2857 u8 reserved_at_18[0x8];
e281682b 2858
b4ff3a36 2859 u8 reserved_at_20[0x20];
e281682b 2860
b4ff3a36 2861 u8 reserved_at_40[0x14];
e281682b 2862 u8 page_offset[0x6];
b4ff3a36 2863 u8 reserved_at_5a[0x6];
e281682b 2864
b4ff3a36 2865 u8 reserved_at_60[0x3];
e281682b
SM		 2866 u8 log_cq_size[0x5];
2867 u8 uar_page[0x18];
2868
b4ff3a36 2869 u8 reserved_at_80[0x4];
e281682b
SM		 2870 u8 cq_period[0xc];
2871 u8 cq_max_count[0x10];
2872
b4ff3a36 2873 u8 reserved_at_a0[0x18];
e281682b
SM		 2874 u8 c_eqn[0x8];
2875
b4ff3a36 2876 u8 reserved_at_c0[0x3];
e281682b 2877 u8 log_page_size[0x5];
b4ff3a36 2878 u8 reserved_at_c8[0x18];
e281682b 2879
b4ff3a36 2880 u8 reserved_at_e0[0x20];
e281682b 2881
b4ff3a36 2882 u8 reserved_at_100[0x8];
e281682b
SM		 2883 u8 last_notified_index[0x18];
2884
b4ff3a36 2885 u8 reserved_at_120[0x8];
e281682b
SM		 2886 u8 last_solicit_index[0x18];
2887
b4ff3a36 2888 u8 reserved_at_140[0x8];
e281682b
SM		 2889 u8 consumer_counter[0x18];
2890
b4ff3a36 2891 u8 reserved_at_160[0x8];
e281682b
SM		 2892 u8 producer_counter[0x18];
2893
b4ff3a36 2894 u8 reserved_at_180[0x40];
e281682b
SM		 2895
2896 u8 dbr_addr[0x40];
2897};
2898
2899union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2900 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2901 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2902 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
b4ff3a36 2903 u8 reserved_at_0[0x800];
e281682b
SM		 2904};
2905
2906struct mlx5_ifc_query_adapter_param_block_bits {
b4ff3a36 2907 u8 reserved_at_0[0xc0];
e281682b 2908
b4ff3a36 2909 u8 reserved_at_c0[0x8];
211e6c80
MD		 2910 u8 ieee_vendor_id[0x18];
2911
b4ff3a36 2912 u8 reserved_at_e0[0x10];
e281682b
SM		 2913 u8 vsd_vendor_id[0x10];
2914
2915 u8 vsd[208][0x8];
2916
2917 u8 vsd_contd_psid[16][0x8];
2918};
2919
7486216b
SM		 2920enum {
2921 MLX5_XRQC_STATE_GOOD = 0x0,
2922 MLX5_XRQC_STATE_ERROR = 0x1,
2923};
2924
2925enum {
2926 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
2927 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
2928};
2929
2930enum {
2931 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
2932};
2933
2934struct mlx5_ifc_tag_matching_topology_context_bits {
2935 u8 log_matching_list_sz[0x4];
2936 u8 reserved_at_4[0xc];
2937 u8 append_next_index[0x10];
2938
2939 u8 sw_phase_cnt[0x10];
2940 u8 hw_phase_cnt[0x10];
2941
2942 u8 reserved_at_40[0x40];
2943};
2944
2945struct mlx5_ifc_xrqc_bits {
2946 u8 state[0x4];
2947 u8 rlkey[0x1];
2948 u8 reserved_at_5[0xf];
2949 u8 topology[0x4];
2950 u8 reserved_at_18[0x4];
2951 u8 offload[0x4];
2952
2953 u8 reserved_at_20[0x8];
2954 u8 user_index[0x18];
2955
2956 u8 reserved_at_40[0x8];
2957 u8 cqn[0x18];
2958
2959 u8 reserved_at_60[0xa0];
2960
2961 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
2962
5579e151 2963 u8 reserved_at_180[0x880];
7486216b
SM		 2964
2965 struct mlx5_ifc_wq_bits wq;
2966};
2967
e281682b
SM		 2968union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2969 struct mlx5_ifc_modify_field_select_bits modify_field_select;
2970 struct mlx5_ifc_resize_field_select_bits resize_field_select;
b4ff3a36 2971 u8 reserved_at_0[0x20];
e281682b
SM		 2972};
2973
2974union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2975 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2976 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2977 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
b4ff3a36 2978 u8 reserved_at_0[0x20];
e281682b
SM		 2979};
2980
2981union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
2982 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
2983 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
2984 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
2985 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
2986 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
2987 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
2988 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
1c64bf6f 2989 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b 2990 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
d8dc0508 2991 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
b4ff3a36 2992 u8 reserved_at_0[0x7c0];
e281682b
SM		 2993};
2994
8ed1a630
GP		 2995union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
2996 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
2997 u8 reserved_at_0[0x7c0];
2998};
2999
e281682b
SM		 3000union mlx5_ifc_event_auto_bits {
3001 struct mlx5_ifc_comp_event_bits comp_event;
3002 struct mlx5_ifc_dct_events_bits dct_events;
3003 struct mlx5_ifc_qp_events_bits qp_events;
3004 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3005 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3006 struct mlx5_ifc_cq_error_bits cq_error;
3007 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3008 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3009 struct mlx5_ifc_gpio_event_bits gpio_event;
3010 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3011 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3012 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
b4ff3a36 3013 u8 reserved_at_0[0xe0];
e281682b
SM		 3014};
3015
3016struct mlx5_ifc_health_buffer_bits {
b4ff3a36 3017 u8 reserved_at_0[0x100];
e281682b
SM		 3018
3019 u8 assert_existptr[0x20];
3020
3021 u8 assert_callra[0x20];
3022
b4ff3a36 3023 u8 reserved_at_140[0x40];
e281682b
SM		 3024
3025 u8 fw_version[0x20];
3026
3027 u8 hw_id[0x20];
3028
b4ff3a36 3029 u8 reserved_at_1c0[0x20];
e281682b
SM		 3030
3031 u8 irisc_index[0x8];
3032 u8 synd[0x8];
3033 u8 ext_synd[0x10];
3034};
3035
3036struct mlx5_ifc_register_loopback_control_bits {
3037 u8 no_lb[0x1];
b4ff3a36 3038 u8 reserved_at_1[0x7];
e281682b 3039 u8 port[0x8];
b4ff3a36 3040 u8 reserved_at_10[0x10];
e281682b 3041
b4ff3a36 3042 u8 reserved_at_20[0x60];
e281682b
SM		 3043};
3044
813f8540
MHY		 3045struct mlx5_ifc_vport_tc_element_bits {
3046 u8 traffic_class[0x4];
3047 u8 reserved_at_4[0xc];
3048 u8 vport_number[0x10];
3049};
3050
3051struct mlx5_ifc_vport_element_bits {
3052 u8 reserved_at_0[0x10];
3053 u8 vport_number[0x10];
3054};
3055
3056enum {
3057 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3058 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3059 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3060};
3061
3062struct mlx5_ifc_tsar_element_bits {
3063 u8 reserved_at_0[0x8];
3064 u8 tsar_type[0x8];
3065 u8 reserved_at_10[0x10];
3066};
3067
e281682b
SM		 3068struct mlx5_ifc_teardown_hca_out_bits {
3069 u8 status[0x8];
b4ff3a36 3070 u8 reserved_at_8[0x18];
e281682b
SM		 3071
3072 u8 syndrome[0x20];
3073
b4ff3a36 3074 u8 reserved_at_40[0x40];
e281682b
SM		 3075};
3076
3077enum {
3078 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
3079 MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE = 0x1,
3080};
3081
3082struct mlx5_ifc_teardown_hca_in_bits {
3083 u8 opcode[0x10];
b4ff3a36 3084 u8 reserved_at_10[0x10];
e281682b 3085
b4ff3a36 3086 u8 reserved_at_20[0x10];
e281682b
SM		 3087 u8 op_mod[0x10];
3088
b4ff3a36 3089 u8 reserved_at_40[0x10];
e281682b
SM		 3090 u8 profile[0x10];
3091
b4ff3a36 3092 u8 reserved_at_60[0x20];
e281682b
SM		 3093};
3094
3095struct mlx5_ifc_sqerr2rts_qp_out_bits {
3096 u8 status[0x8];
b4ff3a36 3097 u8 reserved_at_8[0x18];
e281682b
SM		 3098
3099 u8 syndrome[0x20];
3100
b4ff3a36 3101 u8 reserved_at_40[0x40];
e281682b
SM		 3102};
3103
3104struct mlx5_ifc_sqerr2rts_qp_in_bits {
3105 u8 opcode[0x10];
b4ff3a36 3106 u8 reserved_at_10[0x10];
e281682b 3107
b4ff3a36 3108 u8 reserved_at_20[0x10];
e281682b
SM		 3109 u8 op_mod[0x10];
3110
b4ff3a36 3111 u8 reserved_at_40[0x8];
e281682b
SM		 3112 u8 qpn[0x18];
3113
b4ff3a36 3114 u8 reserved_at_60[0x20];
e281682b
SM		 3115
3116 u8 opt_param_mask[0x20];
3117
b4ff3a36 3118 u8 reserved_at_a0[0x20];
e281682b
SM		 3119
3120 struct mlx5_ifc_qpc_bits qpc;
3121
b4ff3a36 3122 u8 reserved_at_800[0x80];
e281682b
SM		 3123};
3124
3125struct mlx5_ifc_sqd2rts_qp_out_bits {
3126 u8 status[0x8];
b4ff3a36 3127 u8 reserved_at_8[0x18];
e281682b
SM		 3128
3129 u8 syndrome[0x20];
3130
b4ff3a36 3131 u8 reserved_at_40[0x40];
e281682b
SM		 3132};
3133
3134struct mlx5_ifc_sqd2rts_qp_in_bits {
3135 u8 opcode[0x10];
b4ff3a36 3136 u8 reserved_at_10[0x10];
e281682b 3137
b4ff3a36 3138 u8 reserved_at_20[0x10];
e281682b
SM		 3139 u8 op_mod[0x10];
3140
b4ff3a36 3141 u8 reserved_at_40[0x8];
e281682b
SM		 3142 u8 qpn[0x18];
3143
b4ff3a36 3144 u8 reserved_at_60[0x20];
e281682b
SM		 3145
3146 u8 opt_param_mask[0x20];
3147
b4ff3a36 3148 u8 reserved_at_a0[0x20];
e281682b
SM		 3149
3150 struct mlx5_ifc_qpc_bits qpc;
3151
b4ff3a36 3152 u8 reserved_at_800[0x80];
e281682b
SM		 3153};
3154
3155struct mlx5_ifc_set_roce_address_out_bits {
3156 u8 status[0x8];
b4ff3a36 3157 u8 reserved_at_8[0x18];
e281682b
SM		 3158
3159 u8 syndrome[0x20];
3160
b4ff3a36 3161 u8 reserved_at_40[0x40];
e281682b
SM		 3162};
3163
3164struct mlx5_ifc_set_roce_address_in_bits {
3165 u8 opcode[0x10];
b4ff3a36 3166 u8 reserved_at_10[0x10];
e281682b 3167
b4ff3a36 3168 u8 reserved_at_20[0x10];
e281682b
SM		 3169 u8 op_mod[0x10];
3170
3171 u8 roce_address_index[0x10];
b4ff3a36 3172 u8 reserved_at_50[0x10];
e281682b 3173
b4ff3a36 3174 u8 reserved_at_60[0x20];
e281682b
SM		 3175
3176 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3177};
3178
3179struct mlx5_ifc_set_mad_demux_out_bits {
3180 u8 status[0x8];
b4ff3a36 3181 u8 reserved_at_8[0x18];
e281682b
SM		 3182
3183 u8 syndrome[0x20];
3184
b4ff3a36 3185 u8 reserved_at_40[0x40];
e281682b
SM		 3186};
3187
3188enum {
3189 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
3190 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
3191};
3192
3193struct mlx5_ifc_set_mad_demux_in_bits {
3194 u8 opcode[0x10];
b4ff3a36 3195 u8 reserved_at_10[0x10];
e281682b 3196
b4ff3a36 3197 u8 reserved_at_20[0x10];
e281682b
SM		 3198 u8 op_mod[0x10];
3199
b4ff3a36 3200 u8 reserved_at_40[0x20];
e281682b 3201
b4ff3a36 3202 u8 reserved_at_60[0x6];
e281682b 3203 u8 demux_mode[0x2];
b4ff3a36 3204 u8 reserved_at_68[0x18];
e281682b
SM		 3205};
3206
3207struct mlx5_ifc_set_l2_table_entry_out_bits {
3208 u8 status[0x8];
b4ff3a36 3209 u8 reserved_at_8[0x18];
e281682b
SM		 3210
3211 u8 syndrome[0x20];
3212
b4ff3a36 3213 u8 reserved_at_40[0x40];
e281682b
SM		 3214};
3215
3216struct mlx5_ifc_set_l2_table_entry_in_bits {
3217 u8 opcode[0x10];
b4ff3a36 3218 u8 reserved_at_10[0x10];
e281682b 3219
b4ff3a36 3220 u8 reserved_at_20[0x10];
e281682b
SM		 3221 u8 op_mod[0x10];
3222
b4ff3a36 3223 u8 reserved_at_40[0x60];
e281682b 3224
b4ff3a36 3225 u8 reserved_at_a0[0x8];
e281682b
SM		 3226 u8 table_index[0x18];
3227
b4ff3a36 3228 u8 reserved_at_c0[0x20];
e281682b 3229
b4ff3a36 3230 u8 reserved_at_e0[0x13];
e281682b
SM		 3231 u8 vlan_valid[0x1];
3232 u8 vlan[0xc];
3233
3234 struct mlx5_ifc_mac_address_layout_bits mac_address;
3235
b4ff3a36 3236 u8 reserved_at_140[0xc0];
e281682b
SM		 3237};
3238
3239struct mlx5_ifc_set_issi_out_bits {
3240 u8 status[0x8];
b4ff3a36 3241 u8 reserved_at_8[0x18];
e281682b
SM		 3242
3243 u8 syndrome[0x20];
3244
b4ff3a36 3245 u8 reserved_at_40[0x40];
e281682b
SM		 3246};
3247
3248struct mlx5_ifc_set_issi_in_bits {
3249 u8 opcode[0x10];
b4ff3a36 3250 u8 reserved_at_10[0x10];
e281682b 3251
b4ff3a36 3252 u8 reserved_at_20[0x10];
e281682b
SM		 3253 u8 op_mod[0x10];
3254
b4ff3a36 3255 u8 reserved_at_40[0x10];
e281682b
SM		 3256 u8 current_issi[0x10];
3257
b4ff3a36 3258 u8 reserved_at_60[0x20];
e281682b
SM		 3259};
3260
3261struct mlx5_ifc_set_hca_cap_out_bits {
3262 u8 status[0x8];
b4ff3a36 3263 u8 reserved_at_8[0x18];
e281682b
SM		 3264
3265 u8 syndrome[0x20];
3266
b4ff3a36 3267 u8 reserved_at_40[0x40];
e281682b
SM		 3268};
3269
3270struct mlx5_ifc_set_hca_cap_in_bits {
3271 u8 opcode[0x10];
b4ff3a36 3272 u8 reserved_at_10[0x10];
e281682b 3273
b4ff3a36 3274 u8 reserved_at_20[0x10];
e281682b
SM		 3275 u8 op_mod[0x10];
3276
b4ff3a36 3277 u8 reserved_at_40[0x40];
e281682b
SM		 3278
3279 union mlx5_ifc_hca_cap_union_bits capability;
3280};
3281
26a81453
MG		 3282enum {
3283 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
3284 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
3285 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
3286 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
3287};
3288
e281682b
SM		 3289struct mlx5_ifc_set_fte_out_bits {
3290 u8 status[0x8];
b4ff3a36 3291 u8 reserved_at_8[0x18];
e281682b
SM		 3292
3293 u8 syndrome[0x20];
3294
b4ff3a36 3295 u8 reserved_at_40[0x40];
e281682b
SM		 3296};
3297
3298struct mlx5_ifc_set_fte_in_bits {
3299 u8 opcode[0x10];
b4ff3a36 3300 u8 reserved_at_10[0x10];
e281682b 3301
b4ff3a36 3302 u8 reserved_at_20[0x10];
e281682b
SM		 3303 u8 op_mod[0x10];
3304
7d5e1423
SM		 3305 u8 other_vport[0x1];
3306 u8 reserved_at_41[0xf];
3307 u8 vport_number[0x10];
3308
3309 u8 reserved_at_60[0x20];
e281682b
SM		 3310
3311 u8 table_type[0x8];
b4ff3a36 3312 u8 reserved_at_88[0x18];
e281682b 3313
b4ff3a36 3314 u8 reserved_at_a0[0x8];
e281682b
SM		 3315 u8 table_id[0x18];
3316
b4ff3a36 3317 u8 reserved_at_c0[0x18];
26a81453
MG		 3318 u8 modify_enable_mask[0x8];
3319
b4ff3a36 3320 u8 reserved_at_e0[0x20];
e281682b
SM		 3321
3322 u8 flow_index[0x20];
3323
b4ff3a36 3324 u8 reserved_at_120[0xe0];
e281682b
SM		 3325
3326 struct mlx5_ifc_flow_context_bits flow_context;
3327};
3328
3329struct mlx5_ifc_rts2rts_qp_out_bits {
3330 u8 status[0x8];
b4ff3a36 3331 u8 reserved_at_8[0x18];
e281682b
SM		 3332
3333 u8 syndrome[0x20];
3334
b4ff3a36 3335 u8 reserved_at_40[0x40];
e281682b
SM		 3336};
3337
3338struct mlx5_ifc_rts2rts_qp_in_bits {
3339 u8 opcode[0x10];
b4ff3a36 3340 u8 reserved_at_10[0x10];
e281682b 3341
b4ff3a36 3342 u8 reserved_at_20[0x10];
e281682b
SM		 3343 u8 op_mod[0x10];
3344
b4ff3a36 3345 u8 reserved_at_40[0x8];
e281682b
SM		 3346 u8 qpn[0x18];
3347
b4ff3a36 3348 u8 reserved_at_60[0x20];
e281682b
SM		 3349
3350 u8 opt_param_mask[0x20];
3351
b4ff3a36 3352 u8 reserved_at_a0[0x20];
e281682b
SM		 3353
3354 struct mlx5_ifc_qpc_bits qpc;
3355
b4ff3a36 3356 u8 reserved_at_800[0x80];
e281682b
SM		 3357};
3358
3359struct mlx5_ifc_rtr2rts_qp_out_bits {
3360 u8 status[0x8];
b4ff3a36 3361 u8 reserved_at_8[0x18];
e281682b
SM		 3362
3363 u8 syndrome[0x20];
3364
b4ff3a36 3365 u8 reserved_at_40[0x40];
e281682b
SM		 3366};
3367
3368struct mlx5_ifc_rtr2rts_qp_in_bits {
3369 u8 opcode[0x10];
b4ff3a36 3370 u8 reserved_at_10[0x10];
e281682b 3371
b4ff3a36 3372 u8 reserved_at_20[0x10];
e281682b
SM		 3373 u8 op_mod[0x10];
3374
b4ff3a36 3375 u8 reserved_at_40[0x8];
e281682b
SM		 3376 u8 qpn[0x18];
3377
b4ff3a36 3378 u8 reserved_at_60[0x20];
e281682b
SM		 3379
3380 u8 opt_param_mask[0x20];
3381
b4ff3a36 3382 u8 reserved_at_a0[0x20];
e281682b
SM		 3383
3384 struct mlx5_ifc_qpc_bits qpc;
3385
b4ff3a36 3386 u8 reserved_at_800[0x80];
e281682b
SM		 3387};
3388
3389struct mlx5_ifc_rst2init_qp_out_bits {
3390 u8 status[0x8];
b4ff3a36 3391 u8 reserved_at_8[0x18];
e281682b
SM		 3392
3393 u8 syndrome[0x20];
3394
b4ff3a36 3395 u8 reserved_at_40[0x40];
e281682b
SM		 3396};
3397
3398struct mlx5_ifc_rst2init_qp_in_bits {
3399 u8 opcode[0x10];
b4ff3a36 3400 u8 reserved_at_10[0x10];
e281682b 3401
b4ff3a36 3402 u8 reserved_at_20[0x10];
e281682b
SM		 3403 u8 op_mod[0x10];
3404
b4ff3a36 3405 u8 reserved_at_40[0x8];
e281682b
SM		 3406 u8 qpn[0x18];
3407
b4ff3a36 3408 u8 reserved_at_60[0x20];
e281682b
SM		 3409
3410 u8 opt_param_mask[0x20];
3411
b4ff3a36 3412 u8 reserved_at_a0[0x20];
e281682b
SM		 3413
3414 struct mlx5_ifc_qpc_bits qpc;
3415
b4ff3a36 3416 u8 reserved_at_800[0x80];
e281682b
SM		 3417};
3418
7486216b
SM		 3419struct mlx5_ifc_query_xrq_out_bits {
3420 u8 status[0x8];
3421 u8 reserved_at_8[0x18];
3422
3423 u8 syndrome[0x20];
3424
3425 u8 reserved_at_40[0x40];
3426
3427 struct mlx5_ifc_xrqc_bits xrq_context;
3428};
3429
3430struct mlx5_ifc_query_xrq_in_bits {
3431 u8 opcode[0x10];
3432 u8 reserved_at_10[0x10];
3433
3434 u8 reserved_at_20[0x10];
3435 u8 op_mod[0x10];
3436
3437 u8 reserved_at_40[0x8];
3438 u8 xrqn[0x18];
3439
3440 u8 reserved_at_60[0x20];
3441};
3442
e281682b
SM		 3443struct mlx5_ifc_query_xrc_srq_out_bits {
3444 u8 status[0x8];
b4ff3a36 3445 u8 reserved_at_8[0x18];
e281682b
SM		 3446
3447 u8 syndrome[0x20];
3448
b4ff3a36 3449 u8 reserved_at_40[0x40];
e281682b
SM		 3450
3451 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3452
b4ff3a36 3453 u8 reserved_at_280[0x600];
e281682b
SM		 3454
3455 u8 pas[0][0x40];
3456};
3457
3458struct mlx5_ifc_query_xrc_srq_in_bits {
3459 u8 opcode[0x10];
b4ff3a36 3460 u8 reserved_at_10[0x10];
e281682b 3461
b4ff3a36 3462 u8 reserved_at_20[0x10];
e281682b
SM		 3463 u8 op_mod[0x10];
3464
b4ff3a36 3465 u8 reserved_at_40[0x8];
e281682b
SM		 3466 u8 xrc_srqn[0x18];
3467
b4ff3a36 3468 u8 reserved_at_60[0x20];
e281682b
SM		 3469};
3470
3471enum {
3472 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
3473 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
3474};
3475
3476struct mlx5_ifc_query_vport_state_out_bits {
3477 u8 status[0x8];
b4ff3a36 3478 u8 reserved_at_8[0x18];
e281682b
SM		 3479
3480 u8 syndrome[0x20];
3481
b4ff3a36 3482 u8 reserved_at_40[0x20];
e281682b 3483
b4ff3a36 3484 u8 reserved_at_60[0x18];
e281682b
SM		 3485 u8 admin_state[0x4];
3486 u8 state[0x4];
3487};
3488
3489enum {
3490 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0,
e7546514 3491 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1,
e281682b
SM		 3492};
3493
3494struct mlx5_ifc_query_vport_state_in_bits {
3495 u8 opcode[0x10];
b4ff3a36 3496 u8 reserved_at_10[0x10];
e281682b 3497
b4ff3a36 3498 u8 reserved_at_20[0x10];
e281682b
SM		 3499 u8 op_mod[0x10];
3500
3501 u8 other_vport[0x1];
b4ff3a36 3502 u8 reserved_at_41[0xf];
e281682b
SM		 3503 u8 vport_number[0x10];
3504
b4ff3a36 3505 u8 reserved_at_60[0x20];
e281682b
SM		 3506};
3507
3508struct mlx5_ifc_query_vport_counter_out_bits {
3509 u8 status[0x8];
b4ff3a36 3510 u8 reserved_at_8[0x18];
e281682b
SM		 3511
3512 u8 syndrome[0x20];
3513
b4ff3a36 3514 u8 reserved_at_40[0x40];
e281682b
SM		 3515
3516 struct mlx5_ifc_traffic_counter_bits received_errors;
3517
3518 struct mlx5_ifc_traffic_counter_bits transmit_errors;
3519
3520 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3521
3522 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3523
3524 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3525
3526 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3527
3528 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3529
3530 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3531
3532 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3533
3534 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3535
3536 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3537
3538 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3539
b4ff3a36 3540 u8 reserved_at_680[0xa00];
e281682b
SM		 3541};
3542
3543enum {
3544 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
3545};
3546
3547struct mlx5_ifc_query_vport_counter_in_bits {
3548 u8 opcode[0x10];
b4ff3a36 3549 u8 reserved_at_10[0x10];
e281682b 3550
b4ff3a36 3551 u8 reserved_at_20[0x10];
e281682b
SM		 3552 u8 op_mod[0x10];
3553
3554 u8 other_vport[0x1];
b54ba277
MY		 3555 u8 reserved_at_41[0xb];
3556 u8 port_num[0x4];
e281682b
SM		 3557 u8 vport_number[0x10];
3558
b4ff3a36 3559 u8 reserved_at_60[0x60];
e281682b
SM		 3560
3561 u8 clear[0x1];
b4ff3a36 3562 u8 reserved_at_c1[0x1f];
e281682b 3563
b4ff3a36 3564 u8 reserved_at_e0[0x20];
e281682b
SM		 3565};
3566
3567struct mlx5_ifc_query_tis_out_bits {
3568 u8 status[0x8];
b4ff3a36 3569 u8 reserved_at_8[0x18];
e281682b
SM		 3570
3571 u8 syndrome[0x20];
3572
b4ff3a36 3573 u8 reserved_at_40[0x40];
e281682b
SM		 3574
3575 struct mlx5_ifc_tisc_bits tis_context;
3576};
3577
3578struct mlx5_ifc_query_tis_in_bits {
3579 u8 opcode[0x10];
b4ff3a36 3580 u8 reserved_at_10[0x10];
e281682b 3581
b4ff3a36 3582 u8 reserved_at_20[0x10];
e281682b
SM		 3583 u8 op_mod[0x10];
3584
b4ff3a36 3585 u8 reserved_at_40[0x8];
e281682b
SM		 3586 u8 tisn[0x18];
3587
b4ff3a36 3588 u8 reserved_at_60[0x20];
e281682b
SM		 3589};
3590
3591struct mlx5_ifc_query_tir_out_bits {
3592 u8 status[0x8];
b4ff3a36 3593 u8 reserved_at_8[0x18];
e281682b
SM		 3594
3595 u8 syndrome[0x20];
3596
b4ff3a36 3597 u8 reserved_at_40[0xc0];
e281682b
SM		 3598
3599 struct mlx5_ifc_tirc_bits tir_context;
3600};
3601
3602struct mlx5_ifc_query_tir_in_bits {
3603 u8 opcode[0x10];
b4ff3a36 3604 u8 reserved_at_10[0x10];
e281682b 3605
b4ff3a36 3606 u8 reserved_at_20[0x10];
e281682b
SM		 3607 u8 op_mod[0x10];
3608
b4ff3a36 3609 u8 reserved_at_40[0x8];
e281682b
SM		 3610 u8 tirn[0x18];
3611
b4ff3a36 3612 u8 reserved_at_60[0x20];
e281682b
SM		 3613};
3614
3615struct mlx5_ifc_query_srq_out_bits {
3616 u8 status[0x8];
b4ff3a36 3617 u8 reserved_at_8[0x18];
e281682b
SM		 3618
3619 u8 syndrome[0x20];
3620
b4ff3a36 3621 u8 reserved_at_40[0x40];
e281682b
SM		 3622
3623 struct mlx5_ifc_srqc_bits srq_context_entry;
3624
b4ff3a36 3625 u8 reserved_at_280[0x600];
e281682b
SM		 3626
3627 u8 pas[0][0x40];
3628};
3629
3630struct mlx5_ifc_query_srq_in_bits {
3631 u8 opcode[0x10];
b4ff3a36 3632 u8 reserved_at_10[0x10];
e281682b 3633
b4ff3a36 3634 u8 reserved_at_20[0x10];
e281682b
SM		 3635 u8 op_mod[0x10];
3636
b4ff3a36 3637 u8 reserved_at_40[0x8];
e281682b
SM		 3638 u8 srqn[0x18];
3639
b4ff3a36 3640 u8 reserved_at_60[0x20];
e281682b
SM		 3641};
3642
3643struct mlx5_ifc_query_sq_out_bits {
3644 u8 status[0x8];
b4ff3a36 3645 u8 reserved_at_8[0x18];
e281682b
SM		 3646
3647 u8 syndrome[0x20];
3648
b4ff3a36 3649 u8 reserved_at_40[0xc0];
e281682b
SM		 3650
3651 struct mlx5_ifc_sqc_bits sq_context;
3652};
3653
3654struct mlx5_ifc_query_sq_in_bits {
3655 u8 opcode[0x10];
b4ff3a36 3656 u8 reserved_at_10[0x10];
e281682b 3657
b4ff3a36 3658 u8 reserved_at_20[0x10];
e281682b
SM		 3659 u8 op_mod[0x10];
3660
b4ff3a36 3661 u8 reserved_at_40[0x8];
e281682b
SM		 3662 u8 sqn[0x18];
3663
b4ff3a36 3664 u8 reserved_at_60[0x20];
e281682b
SM		 3665};
3666
3667struct mlx5_ifc_query_special_contexts_out_bits {
3668 u8 status[0x8];
b4ff3a36 3669 u8 reserved_at_8[0x18];
e281682b
SM		 3670
3671 u8 syndrome[0x20];
3672
ec22eb53 3673 u8 dump_fill_mkey[0x20];
e281682b
SM		 3674
3675 u8 resd_lkey[0x20];
bcda1aca
AK		 3676
3677 u8 null_mkey[0x20];
3678
3679 u8 reserved_at_a0[0x60];
e281682b
SM		 3680};
3681
3682struct mlx5_ifc_query_special_contexts_in_bits {
3683 u8 opcode[0x10];
b4ff3a36 3684 u8 reserved_at_10[0x10];
e281682b 3685
b4ff3a36 3686 u8 reserved_at_20[0x10];
e281682b
SM		 3687 u8 op_mod[0x10];
3688
b4ff3a36 3689 u8 reserved_at_40[0x40];
e281682b
SM		 3690};
3691
813f8540
MHY		 3692struct mlx5_ifc_query_scheduling_element_out_bits {
3693 u8 opcode[0x10];
3694 u8 reserved_at_10[0x10];
3695
3696 u8 reserved_at_20[0x10];
3697 u8 op_mod[0x10];
3698
3699 u8 reserved_at_40[0xc0];
3700
3701 struct mlx5_ifc_scheduling_context_bits scheduling_context;
3702
3703 u8 reserved_at_300[0x100];
3704};
3705
3706enum {
3707 SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
3708};
3709
3710struct mlx5_ifc_query_scheduling_element_in_bits {
3711 u8 opcode[0x10];
3712 u8 reserved_at_10[0x10];
3713
3714 u8 reserved_at_20[0x10];
3715 u8 op_mod[0x10];
3716
3717 u8 scheduling_hierarchy[0x8];
3718 u8 reserved_at_48[0x18];
3719
3720 u8 scheduling_element_id[0x20];
3721
3722 u8 reserved_at_80[0x180];
3723};
3724
e281682b
SM		 3725struct mlx5_ifc_query_rqt_out_bits {
3726 u8 status[0x8];
b4ff3a36 3727 u8 reserved_at_8[0x18];
e281682b
SM		 3728
3729 u8 syndrome[0x20];
3730
b4ff3a36 3731 u8 reserved_at_40[0xc0];
e281682b
SM		 3732
3733 struct mlx5_ifc_rqtc_bits rqt_context;
3734};
3735
3736struct mlx5_ifc_query_rqt_in_bits {
3737 u8 opcode[0x10];
b4ff3a36 3738 u8 reserved_at_10[0x10];
e281682b 3739
b4ff3a36 3740 u8 reserved_at_20[0x10];
e281682b
SM		 3741 u8 op_mod[0x10];
3742
b4ff3a36 3743 u8 reserved_at_40[0x8];
e281682b
SM		 3744 u8 rqtn[0x18];
3745
b4ff3a36 3746 u8 reserved_at_60[0x20];
e281682b
SM		 3747};
3748
3749struct mlx5_ifc_query_rq_out_bits {
3750 u8 status[0x8];
b4ff3a36 3751 u8 reserved_at_8[0x18];
e281682b
SM		 3752
3753 u8 syndrome[0x20];
3754
b4ff3a36 3755 u8 reserved_at_40[0xc0];
e281682b
SM		 3756
3757 struct mlx5_ifc_rqc_bits rq_context;
3758};
3759
3760struct mlx5_ifc_query_rq_in_bits {
3761 u8 opcode[0x10];
b4ff3a36 3762 u8 reserved_at_10[0x10];
e281682b 3763
b4ff3a36 3764 u8 reserved_at_20[0x10];
e281682b
SM		 3765 u8 op_mod[0x10];
3766
b4ff3a36 3767 u8 reserved_at_40[0x8];
e281682b
SM		 3768 u8 rqn[0x18];
3769
b4ff3a36 3770 u8 reserved_at_60[0x20];
e281682b
SM		 3771};
3772
3773struct mlx5_ifc_query_roce_address_out_bits {
3774 u8 status[0x8];
b4ff3a36 3775 u8 reserved_at_8[0x18];
e281682b
SM		 3776
3777 u8 syndrome[0x20];
3778
b4ff3a36 3779 u8 reserved_at_40[0x40];
e281682b
SM		 3780
3781 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3782};
3783
3784struct mlx5_ifc_query_roce_address_in_bits {
3785 u8 opcode[0x10];
b4ff3a36 3786 u8 reserved_at_10[0x10];
e281682b 3787
b4ff3a36 3788 u8 reserved_at_20[0x10];
e281682b
SM		 3789 u8 op_mod[0x10];
3790
3791 u8 roce_address_index[0x10];
b4ff3a36 3792 u8 reserved_at_50[0x10];
e281682b 3793
b4ff3a36 3794 u8 reserved_at_60[0x20];
e281682b
SM		 3795};
3796
3797struct mlx5_ifc_query_rmp_out_bits {
3798 u8 status[0x8];
b4ff3a36 3799 u8 reserved_at_8[0x18];
e281682b
SM		 3800
3801 u8 syndrome[0x20];
3802
b4ff3a36 3803 u8 reserved_at_40[0xc0];
e281682b
SM		 3804
3805 struct mlx5_ifc_rmpc_bits rmp_context;
3806};
3807
3808struct mlx5_ifc_query_rmp_in_bits {
3809 u8 opcode[0x10];
b4ff3a36 3810 u8 reserved_at_10[0x10];
e281682b 3811
b4ff3a36 3812 u8 reserved_at_20[0x10];
e281682b
SM		 3813 u8 op_mod[0x10];
3814
b4ff3a36 3815 u8 reserved_at_40[0x8];
e281682b
SM		 3816 u8 rmpn[0x18];
3817
b4ff3a36 3818 u8 reserved_at_60[0x20];
e281682b
SM		 3819};
3820
3821struct mlx5_ifc_query_qp_out_bits {
3822 u8 status[0x8];
b4ff3a36 3823 u8 reserved_at_8[0x18];
e281682b
SM		 3824
3825 u8 syndrome[0x20];
3826
b4ff3a36 3827 u8 reserved_at_40[0x40];
e281682b
SM		 3828
3829 u8 opt_param_mask[0x20];
3830
b4ff3a36 3831 u8 reserved_at_a0[0x20];
e281682b
SM		 3832
3833 struct mlx5_ifc_qpc_bits qpc;
3834
b4ff3a36 3835 u8 reserved_at_800[0x80];
e281682b
SM		 3836
3837 u8 pas[0][0x40];
3838};
3839
3840struct mlx5_ifc_query_qp_in_bits {
3841 u8 opcode[0x10];
b4ff3a36 3842 u8 reserved_at_10[0x10];
e281682b 3843
b4ff3a36 3844 u8 reserved_at_20[0x10];
e281682b
SM		 3845 u8 op_mod[0x10];
3846
b4ff3a36 3847 u8 reserved_at_40[0x8];
e281682b
SM		 3848 u8 qpn[0x18];
3849
b4ff3a36 3850 u8 reserved_at_60[0x20];
e281682b
SM		 3851};
3852
3853struct mlx5_ifc_query_q_counter_out_bits {
3854 u8 status[0x8];
b4ff3a36 3855 u8 reserved_at_8[0x18];
e281682b
SM		 3856
3857 u8 syndrome[0x20];
3858
b4ff3a36 3859 u8 reserved_at_40[0x40];
e281682b
SM		 3860
3861 u8 rx_write_requests[0x20];
3862
b4ff3a36 3863 u8 reserved_at_a0[0x20];
e281682b
SM		 3864
3865 u8 rx_read_requests[0x20];
3866
b4ff3a36 3867 u8 reserved_at_e0[0x20];
e281682b
SM		 3868
3869 u8 rx_atomic_requests[0x20];
3870
b4ff3a36 3871 u8 reserved_at_120[0x20];
e281682b
SM		 3872
3873 u8 rx_dct_connect[0x20];
3874
b4ff3a36 3875 u8 reserved_at_160[0x20];
e281682b
SM		 3876
3877 u8 out_of_buffer[0x20];
3878
b4ff3a36 3879 u8 reserved_at_1a0[0x20];
e281682b
SM		 3880
3881 u8 out_of_sequence[0x20];
3882
7486216b
SM		 3883 u8 reserved_at_1e0[0x20];
3884
3885 u8 duplicate_request[0x20];
3886
3887 u8 reserved_at_220[0x20];
3888
3889 u8 rnr_nak_retry_err[0x20];
3890
3891 u8 reserved_at_260[0x20];
3892
3893 u8 packet_seq_err[0x20];
3894
3895 u8 reserved_at_2a0[0x20];
3896
3897 u8 implied_nak_seq_err[0x20];
3898
3899 u8 reserved_at_2e0[0x20];
3900
3901 u8 local_ack_timeout_err[0x20];
3902
3903 u8 reserved_at_320[0x4e0];
e281682b
SM		 3904};
3905
3906struct mlx5_ifc_query_q_counter_in_bits {
3907 u8 opcode[0x10];
b4ff3a36 3908 u8 reserved_at_10[0x10];
e281682b 3909
b4ff3a36 3910 u8 reserved_at_20[0x10];
e281682b
SM		 3911 u8 op_mod[0x10];
3912
b4ff3a36 3913 u8 reserved_at_40[0x80];
e281682b
SM		 3914
3915 u8 clear[0x1];
b4ff3a36 3916 u8 reserved_at_c1[0x1f];
e281682b 3917
b4ff3a36 3918 u8 reserved_at_e0[0x18];
e281682b
SM		 3919 u8 counter_set_id[0x8];
3920};
3921
3922struct mlx5_ifc_query_pages_out_bits {
3923 u8 status[0x8];
b4ff3a36 3924 u8 reserved_at_8[0x18];
e281682b
SM		 3925
3926 u8 syndrome[0x20];
3927
b4ff3a36 3928 u8 reserved_at_40[0x10];
e281682b
SM		 3929 u8 function_id[0x10];
3930
3931 u8 num_pages[0x20];
3932};
3933
3934enum {
3935 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
3936 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
3937 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
3938};
3939
3940struct mlx5_ifc_query_pages_in_bits {
3941 u8 opcode[0x10];
b4ff3a36 3942 u8 reserved_at_10[0x10];
e281682b 3943
b4ff3a36 3944 u8 reserved_at_20[0x10];
e281682b
SM		 3945 u8 op_mod[0x10];
3946
b4ff3a36 3947 u8 reserved_at_40[0x10];
e281682b
SM		 3948 u8 function_id[0x10];
3949
b4ff3a36 3950 u8 reserved_at_60[0x20];
e281682b
SM		 3951};
3952
3953struct mlx5_ifc_query_nic_vport_context_out_bits {
3954 u8 status[0x8];
b4ff3a36 3955 u8 reserved_at_8[0x18];
e281682b
SM		 3956
3957 u8 syndrome[0x20];
3958
b4ff3a36 3959 u8 reserved_at_40[0x40];
e281682b
SM		 3960
3961 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
3962};
3963
3964struct mlx5_ifc_query_nic_vport_context_in_bits {
3965 u8 opcode[0x10];
b4ff3a36 3966 u8 reserved_at_10[0x10];
e281682b 3967
b4ff3a36 3968 u8 reserved_at_20[0x10];
e281682b
SM		 3969 u8 op_mod[0x10];
3970
3971 u8 other_vport[0x1];
b4ff3a36 3972 u8 reserved_at_41[0xf];
e281682b
SM		 3973 u8 vport_number[0x10];
3974
b4ff3a36 3975 u8 reserved_at_60[0x5];
e281682b 3976 u8 allowed_list_type[0x3];
b4ff3a36 3977 u8 reserved_at_68[0x18];
e281682b
SM		 3978};
3979
3980struct mlx5_ifc_query_mkey_out_bits {
3981 u8 status[0x8];
b4ff3a36 3982 u8 reserved_at_8[0x18];
e281682b
SM		 3983
3984 u8 syndrome[0x20];
3985
b4ff3a36 3986 u8 reserved_at_40[0x40];
e281682b
SM		 3987
3988 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
3989
b4ff3a36 3990 u8 reserved_at_280[0x600];
e281682b
SM		 3991
3992 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
3993
3994 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
3995};
3996
3997struct mlx5_ifc_query_mkey_in_bits {
3998 u8 opcode[0x10];
b4ff3a36 3999 u8 reserved_at_10[0x10];
e281682b 4000
b4ff3a36 4001 u8 reserved_at_20[0x10];
e281682b
SM		 4002 u8 op_mod[0x10];
4003
b4ff3a36 4004 u8 reserved_at_40[0x8];
e281682b
SM		 4005 u8 mkey_index[0x18];
4006
4007 u8 pg_access[0x1];
b4ff3a36 4008 u8 reserved_at_61[0x1f];
e281682b
SM		 4009};
4010
4011struct mlx5_ifc_query_mad_demux_out_bits {
4012 u8 status[0x8];
b4ff3a36 4013 u8 reserved_at_8[0x18];
e281682b
SM		 4014
4015 u8 syndrome[0x20];
4016
b4ff3a36 4017 u8 reserved_at_40[0x40];
e281682b
SM		 4018
4019 u8 mad_dumux_parameters_block[0x20];
4020};
4021
4022struct mlx5_ifc_query_mad_demux_in_bits {
4023 u8 opcode[0x10];
b4ff3a36 4024 u8 reserved_at_10[0x10];
e281682b 4025
b4ff3a36 4026 u8 reserved_at_20[0x10];
e281682b
SM		 4027 u8 op_mod[0x10];
4028
b4ff3a36 4029 u8 reserved_at_40[0x40];
e281682b
SM		 4030};
4031
4032struct mlx5_ifc_query_l2_table_entry_out_bits {
4033 u8 status[0x8];
b4ff3a36 4034 u8 reserved_at_8[0x18];
e281682b
SM		 4035
4036 u8 syndrome[0x20];
4037
b4ff3a36 4038 u8 reserved_at_40[0xa0];
e281682b 4039
b4ff3a36 4040 u8 reserved_at_e0[0x13];
e281682b
SM		 4041 u8 vlan_valid[0x1];
4042 u8 vlan[0xc];
4043
4044 struct mlx5_ifc_mac_address_layout_bits mac_address;
4045
b4ff3a36 4046 u8 reserved_at_140[0xc0];
e281682b
SM		 4047};
4048
4049struct mlx5_ifc_query_l2_table_entry_in_bits {
4050 u8 opcode[0x10];
b4ff3a36 4051 u8 reserved_at_10[0x10];
e281682b 4052
b4ff3a36 4053 u8 reserved_at_20[0x10];
e281682b
SM		 4054 u8 op_mod[0x10];
4055
b4ff3a36 4056 u8 reserved_at_40[0x60];
e281682b 4057
b4ff3a36 4058 u8 reserved_at_a0[0x8];
e281682b
SM		 4059 u8 table_index[0x18];
4060
b4ff3a36 4061 u8 reserved_at_c0[0x140];
e281682b
SM		 4062};
4063
4064struct mlx5_ifc_query_issi_out_bits {
4065 u8 status[0x8];
b4ff3a36 4066 u8 reserved_at_8[0x18];
e281682b
SM		 4067
4068 u8 syndrome[0x20];
4069
b4ff3a36 4070 u8 reserved_at_40[0x10];
e281682b
SM		 4071 u8 current_issi[0x10];
4072
b4ff3a36 4073 u8 reserved_at_60[0xa0];
e281682b 4074
b4ff3a36 4075 u8 reserved_at_100[76][0x8];
e281682b
SM		 4076 u8 supported_issi_dw0[0x20];
4077};
4078
4079struct mlx5_ifc_query_issi_in_bits {
4080 u8 opcode[0x10];
b4ff3a36 4081 u8 reserved_at_10[0x10];
e281682b 4082
b4ff3a36 4083 u8 reserved_at_20[0x10];
e281682b
SM		 4084 u8 op_mod[0x10];
4085
b4ff3a36 4086 u8 reserved_at_40[0x40];
e281682b
SM		 4087};
4088
0dbc6fe0
SM		 4089struct mlx5_ifc_set_driver_version_out_bits {
4090 u8 status[0x8];
4091 u8 reserved_0[0x18];
4092
4093 u8 syndrome[0x20];
4094 u8 reserved_1[0x40];
4095};
4096
4097struct mlx5_ifc_set_driver_version_in_bits {
4098 u8 opcode[0x10];
4099 u8 reserved_0[0x10];
4100
4101 u8 reserved_1[0x10];
4102 u8 op_mod[0x10];
4103
4104 u8 reserved_2[0x40];
4105 u8 driver_version[64][0x8];
4106};
4107
e281682b
SM		 4108struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4109 u8 status[0x8];
b4ff3a36 4110 u8 reserved_at_8[0x18];
e281682b
SM		 4111
4112 u8 syndrome[0x20];
4113
b4ff3a36 4114 u8 reserved_at_40[0x40];
e281682b
SM		 4115
4116 struct mlx5_ifc_pkey_bits pkey[0];
4117};
4118
4119struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4120 u8 opcode[0x10];
b4ff3a36 4121 u8 reserved_at_10[0x10];
e281682b 4122
b4ff3a36 4123 u8 reserved_at_20[0x10];
e281682b
SM		 4124 u8 op_mod[0x10];
4125
4126 u8 other_vport[0x1];
b4ff3a36 4127 u8 reserved_at_41[0xb];
707c4602 4128 u8 port_num[0x4];
e281682b
SM		 4129 u8 vport_number[0x10];
4130
b4ff3a36 4131 u8 reserved_at_60[0x10];
e281682b
SM		 4132 u8 pkey_index[0x10];
4133};
4134
eff901d3
EC		 4135enum {
4136 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
4137 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
4138 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4139};
4140
e281682b
SM		 4141struct mlx5_ifc_query_hca_vport_gid_out_bits {
4142 u8 status[0x8];
b4ff3a36 4143 u8 reserved_at_8[0x18];
e281682b
SM		 4144
4145 u8 syndrome[0x20];
4146
b4ff3a36 4147 u8 reserved_at_40[0x20];
e281682b
SM		 4148
4149 u8 gids_num[0x10];
b4ff3a36 4150 u8 reserved_at_70[0x10];
e281682b
SM		 4151
4152 struct mlx5_ifc_array128_auto_bits gid[0];
4153};
4154
4155struct mlx5_ifc_query_hca_vport_gid_in_bits {
4156 u8 opcode[0x10];
b4ff3a36 4157 u8 reserved_at_10[0x10];
e281682b 4158
b4ff3a36 4159 u8 reserved_at_20[0x10];
e281682b
SM		 4160 u8 op_mod[0x10];
4161
4162 u8 other_vport[0x1];
b4ff3a36 4163 u8 reserved_at_41[0xb];
707c4602 4164 u8 port_num[0x4];
e281682b
SM		 4165 u8 vport_number[0x10];
4166
b4ff3a36 4167 u8 reserved_at_60[0x10];
e281682b
SM		 4168 u8 gid_index[0x10];
4169};
4170
4171struct mlx5_ifc_query_hca_vport_context_out_bits {
4172 u8 status[0x8];
b4ff3a36 4173 u8 reserved_at_8[0x18];
e281682b
SM		 4174
4175 u8 syndrome[0x20];
4176
b4ff3a36 4177 u8 reserved_at_40[0x40];
e281682b
SM		 4178
4179 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4180};
4181
4182struct mlx5_ifc_query_hca_vport_context_in_bits {
4183 u8 opcode[0x10];
b4ff3a36 4184 u8 reserved_at_10[0x10];
e281682b 4185
b4ff3a36 4186 u8 reserved_at_20[0x10];
e281682b
SM		 4187 u8 op_mod[0x10];
4188
4189 u8 other_vport[0x1];
b4ff3a36 4190 u8 reserved_at_41[0xb];
707c4602 4191 u8 port_num[0x4];
e281682b
SM		 4192 u8 vport_number[0x10];
4193
b4ff3a36 4194 u8 reserved_at_60[0x20];
e281682b
SM		 4195};
4196
4197struct mlx5_ifc_query_hca_cap_out_bits {
4198 u8 status[0x8];
b4ff3a36 4199 u8 reserved_at_8[0x18];
e281682b
SM		 4200
4201 u8 syndrome[0x20];
4202
b4ff3a36 4203 u8 reserved_at_40[0x40];
e281682b
SM		 4204
4205 union mlx5_ifc_hca_cap_union_bits capability;
4206};
4207
4208struct mlx5_ifc_query_hca_cap_in_bits {
4209 u8 opcode[0x10];
b4ff3a36 4210 u8 reserved_at_10[0x10];
e281682b 4211
b4ff3a36 4212 u8 reserved_at_20[0x10];
e281682b
SM		 4213 u8 op_mod[0x10];
4214
b4ff3a36 4215 u8 reserved_at_40[0x40];
e281682b
SM		 4216};
4217
4218struct mlx5_ifc_query_flow_table_out_bits {
4219 u8 status[0x8];
b4ff3a36 4220 u8 reserved_at_8[0x18];
e281682b
SM		 4221
4222 u8 syndrome[0x20];
4223
b4ff3a36 4224 u8 reserved_at_40[0x80];
e281682b 4225
b4ff3a36 4226 u8 reserved_at_c0[0x8];
e281682b 4227 u8 level[0x8];
b4ff3a36 4228 u8 reserved_at_d0[0x8];
e281682b
SM		 4229 u8 log_size[0x8];
4230
b4ff3a36 4231 u8 reserved_at_e0[0x120];
e281682b
SM		 4232};
4233
4234struct mlx5_ifc_query_flow_table_in_bits {
4235 u8 opcode[0x10];
b4ff3a36 4236 u8 reserved_at_10[0x10];
e281682b 4237
b4ff3a36 4238 u8 reserved_at_20[0x10];
e281682b
SM		 4239 u8 op_mod[0x10];
4240
b4ff3a36 4241 u8 reserved_at_40[0x40];
e281682b
SM		 4242
4243 u8 table_type[0x8];
b4ff3a36 4244 u8 reserved_at_88[0x18];
e281682b 4245
b4ff3a36 4246 u8 reserved_at_a0[0x8];
e281682b
SM		 4247 u8 table_id[0x18];
4248
b4ff3a36 4249 u8 reserved_at_c0[0x140];
e281682b
SM		 4250};
4251
4252struct mlx5_ifc_query_fte_out_bits {
4253 u8 status[0x8];
b4ff3a36 4254 u8 reserved_at_8[0x18];
e281682b
SM		 4255
4256 u8 syndrome[0x20];
4257
b4ff3a36 4258 u8 reserved_at_40[0x1c0];
e281682b
SM		 4259
4260 struct mlx5_ifc_flow_context_bits flow_context;
4261};
4262
4263struct mlx5_ifc_query_fte_in_bits {
4264 u8 opcode[0x10];
b4ff3a36 4265 u8 reserved_at_10[0x10];
e281682b 4266
b4ff3a36 4267 u8 reserved_at_20[0x10];
e281682b
SM		 4268 u8 op_mod[0x10];
4269
b4ff3a36 4270 u8 reserved_at_40[0x40];
e281682b
SM		 4271
4272 u8 table_type[0x8];
b4ff3a36 4273 u8 reserved_at_88[0x18];
e281682b 4274
b4ff3a36 4275 u8 reserved_at_a0[0x8];
e281682b
SM		 4276 u8 table_id[0x18];
4277
b4ff3a36 4278 u8 reserved_at_c0[0x40];
e281682b
SM		 4279
4280 u8 flow_index[0x20];
4281
b4ff3a36 4282 u8 reserved_at_120[0xe0];
e281682b
SM		 4283};
4284
4285enum {
4286 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
4287 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
4288 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
4289};
4290
4291struct mlx5_ifc_query_flow_group_out_bits {
4292 u8 status[0x8];
b4ff3a36 4293 u8 reserved_at_8[0x18];
e281682b
SM		 4294
4295 u8 syndrome[0x20];
4296
b4ff3a36 4297 u8 reserved_at_40[0xa0];
e281682b
SM		 4298
4299 u8 start_flow_index[0x20];
4300
b4ff3a36 4301 u8 reserved_at_100[0x20];
e281682b
SM		 4302
4303 u8 end_flow_index[0x20];
4304
b4ff3a36 4305 u8 reserved_at_140[0xa0];
e281682b 4306
b4ff3a36 4307 u8 reserved_at_1e0[0x18];
e281682b
SM		 4308 u8 match_criteria_enable[0x8];
4309
4310 struct mlx5_ifc_fte_match_param_bits match_criteria;
4311
b4ff3a36 4312 u8 reserved_at_1200[0xe00];
e281682b
SM		 4313};
4314
4315struct mlx5_ifc_query_flow_group_in_bits {
4316 u8 opcode[0x10];
b4ff3a36 4317 u8 reserved_at_10[0x10];
e281682b 4318
b4ff3a36 4319 u8 reserved_at_20[0x10];
e281682b
SM		 4320 u8 op_mod[0x10];
4321
b4ff3a36 4322 u8 reserved_at_40[0x40];
e281682b
SM		 4323
4324 u8 table_type[0x8];
b4ff3a36 4325 u8 reserved_at_88[0x18];
e281682b 4326
b4ff3a36 4327 u8 reserved_at_a0[0x8];
e281682b
SM		 4328 u8 table_id[0x18];
4329
4330 u8 group_id[0x20];
4331
b4ff3a36 4332 u8 reserved_at_e0[0x120];
e281682b
SM		 4333};
4334
9dc0b289
AV		 4335struct mlx5_ifc_query_flow_counter_out_bits {
4336 u8 status[0x8];
4337 u8 reserved_at_8[0x18];
4338
4339 u8 syndrome[0x20];
4340
4341 u8 reserved_at_40[0x40];
4342
4343 struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4344};
4345
4346struct mlx5_ifc_query_flow_counter_in_bits {
4347 u8 opcode[0x10];
4348 u8 reserved_at_10[0x10];
4349
4350 u8 reserved_at_20[0x10];
4351 u8 op_mod[0x10];
4352
4353 u8 reserved_at_40[0x80];
4354
4355 u8 clear[0x1];
4356 u8 reserved_at_c1[0xf];
4357 u8 num_of_counters[0x10];
4358
4359 u8 reserved_at_e0[0x10];
4360 u8 flow_counter_id[0x10];
4361};
4362
d6666753
SM		 4363struct mlx5_ifc_query_esw_vport_context_out_bits {
4364 u8 status[0x8];
b4ff3a36 4365 u8 reserved_at_8[0x18];
d6666753
SM		 4366
4367 u8 syndrome[0x20];
4368
b4ff3a36 4369 u8 reserved_at_40[0x40];
d6666753
SM		 4370
4371 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4372};
4373
4374struct mlx5_ifc_query_esw_vport_context_in_bits {
4375 u8 opcode[0x10];
b4ff3a36 4376 u8 reserved_at_10[0x10];
d6666753 4377
b4ff3a36 4378 u8 reserved_at_20[0x10];
d6666753
SM		 4379 u8 op_mod[0x10];
4380
4381 u8 other_vport[0x1];
b4ff3a36 4382 u8 reserved_at_41[0xf];
d6666753
SM		 4383 u8 vport_number[0x10];
4384
b4ff3a36 4385 u8 reserved_at_60[0x20];
d6666753
SM		 4386};
4387
4388struct mlx5_ifc_modify_esw_vport_context_out_bits {
4389 u8 status[0x8];
b4ff3a36 4390 u8 reserved_at_8[0x18];
d6666753
SM		 4391
4392 u8 syndrome[0x20];
4393
b4ff3a36 4394 u8 reserved_at_40[0x40];
d6666753
SM		 4395};
4396
4397struct mlx5_ifc_esw_vport_context_fields_select_bits {
b4ff3a36 4398 u8 reserved_at_0[0x1c];
d6666753
SM		 4399 u8 vport_cvlan_insert[0x1];
4400 u8 vport_svlan_insert[0x1];
4401 u8 vport_cvlan_strip[0x1];
4402 u8 vport_svlan_strip[0x1];
4403};
4404
4405struct mlx5_ifc_modify_esw_vport_context_in_bits {
4406 u8 opcode[0x10];
b4ff3a36 4407 u8 reserved_at_10[0x10];
d6666753 4408
b4ff3a36 4409 u8 reserved_at_20[0x10];
d6666753
SM		 4410 u8 op_mod[0x10];
4411
4412 u8 other_vport[0x1];
b4ff3a36 4413 u8 reserved_at_41[0xf];
d6666753
SM		 4414 u8 vport_number[0x10];
4415
4416 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4417
4418 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4419};
4420
e281682b
SM		 4421struct mlx5_ifc_query_eq_out_bits {
4422 u8 status[0x8];
b4ff3a36 4423 u8 reserved_at_8[0x18];
e281682b
SM		 4424
4425 u8 syndrome[0x20];
4426
b4ff3a36 4427 u8 reserved_at_40[0x40];
e281682b
SM		 4428
4429 struct mlx5_ifc_eqc_bits eq_context_entry;
4430
b4ff3a36 4431 u8 reserved_at_280[0x40];
e281682b
SM		 4432
4433 u8 event_bitmask[0x40];
4434
b4ff3a36 4435 u8 reserved_at_300[0x580];
e281682b
SM		 4436
4437 u8 pas[0][0x40];
4438};
4439
4440struct mlx5_ifc_query_eq_in_bits {
4441 u8 opcode[0x10];
b4ff3a36 4442 u8 reserved_at_10[0x10];
e281682b 4443
b4ff3a36 4444 u8 reserved_at_20[0x10];
e281682b
SM		 4445 u8 op_mod[0x10];
4446
b4ff3a36 4447 u8 reserved_at_40[0x18];
e281682b
SM		 4448 u8 eq_number[0x8];
4449
b4ff3a36 4450 u8 reserved_at_60[0x20];
e281682b
SM		 4451};
4452
7adbde20
HHZ		 4453struct mlx5_ifc_encap_header_in_bits {
4454 u8 reserved_at_0[0x5];
4455 u8 header_type[0x3];
4456 u8 reserved_at_8[0xe];
4457 u8 encap_header_size[0xa];
4458
4459 u8 reserved_at_20[0x10];
4460 u8 encap_header[2][0x8];
4461
4462 u8 more_encap_header[0][0x8];
4463};
4464
4465struct mlx5_ifc_query_encap_header_out_bits {
4466 u8 status[0x8];
4467 u8 reserved_at_8[0x18];
4468
4469 u8 syndrome[0x20];
4470
4471 u8 reserved_at_40[0xa0];
4472
4473 struct mlx5_ifc_encap_header_in_bits encap_header[0];
4474};
4475
4476struct mlx5_ifc_query_encap_header_in_bits {
4477 u8 opcode[0x10];
4478 u8 reserved_at_10[0x10];
4479
4480 u8 reserved_at_20[0x10];
4481 u8 op_mod[0x10];
4482
4483 u8 encap_id[0x20];
4484
4485 u8 reserved_at_60[0xa0];
4486};
4487
4488struct mlx5_ifc_alloc_encap_header_out_bits {
4489 u8 status[0x8];
4490 u8 reserved_at_8[0x18];
4491
4492 u8 syndrome[0x20];
4493
4494 u8 encap_id[0x20];
4495
4496 u8 reserved_at_60[0x20];
4497};
4498
4499struct mlx5_ifc_alloc_encap_header_in_bits {
4500 u8 opcode[0x10];
4501 u8 reserved_at_10[0x10];
4502
4503 u8 reserved_at_20[0x10];
4504 u8 op_mod[0x10];
4505
4506 u8 reserved_at_40[0xa0];
4507
4508 struct mlx5_ifc_encap_header_in_bits encap_header;
4509};
4510
4511struct mlx5_ifc_dealloc_encap_header_out_bits {
4512 u8 status[0x8];
4513 u8 reserved_at_8[0x18];
4514
4515 u8 syndrome[0x20];
4516
4517 u8 reserved_at_40[0x40];
4518};
4519
4520struct mlx5_ifc_dealloc_encap_header_in_bits {
4521 u8 opcode[0x10];
4522 u8 reserved_at_10[0x10];
4523
4524 u8 reserved_20[0x10];
4525 u8 op_mod[0x10];
4526
4527 u8 encap_id[0x20];
4528
4529 u8 reserved_60[0x20];
4530};
4531
e281682b
SM		 4532struct mlx5_ifc_query_dct_out_bits {
4533 u8 status[0x8];
b4ff3a36 4534 u8 reserved_at_8[0x18];
e281682b
SM		 4535
4536 u8 syndrome[0x20];
4537
b4ff3a36 4538 u8 reserved_at_40[0x40];
e281682b
SM		 4539
4540 struct mlx5_ifc_dctc_bits dct_context_entry;
4541
b4ff3a36 4542 u8 reserved_at_280[0x180];
e281682b
SM		 4543};
4544
4545struct mlx5_ifc_query_dct_in_bits {
4546 u8 opcode[0x10];
b4ff3a36 4547 u8 reserved_at_10[0x10];
e281682b 4548
b4ff3a36 4549 u8 reserved_at_20[0x10];
e281682b
SM		 4550 u8 op_mod[0x10];
4551
b4ff3a36 4552 u8 reserved_at_40[0x8];
e281682b
SM		 4553 u8 dctn[0x18];
4554
b4ff3a36 4555 u8 reserved_at_60[0x20];
e281682b
SM		 4556};
4557
4558struct mlx5_ifc_query_cq_out_bits {
4559 u8 status[0x8];
b4ff3a36 4560 u8 reserved_at_8[0x18];
e281682b
SM		 4561
4562 u8 syndrome[0x20];
4563
b4ff3a36 4564 u8 reserved_at_40[0x40];
e281682b
SM		 4565
4566 struct mlx5_ifc_cqc_bits cq_context;
4567
b4ff3a36 4568 u8 reserved_at_280[0x600];
e281682b
SM		 4569
4570 u8 pas[0][0x40];
4571};
4572
4573struct mlx5_ifc_query_cq_in_bits {
4574 u8 opcode[0x10];
b4ff3a36 4575 u8 reserved_at_10[0x10];
e281682b 4576
b4ff3a36 4577 u8 reserved_at_20[0x10];
e281682b
SM		 4578 u8 op_mod[0x10];
4579
b4ff3a36 4580 u8 reserved_at_40[0x8];
e281682b
SM		 4581 u8 cqn[0x18];
4582
b4ff3a36 4583 u8 reserved_at_60[0x20];
e281682b
SM		 4584};
4585
4586struct mlx5_ifc_query_cong_status_out_bits {
4587 u8 status[0x8];
b4ff3a36 4588 u8 reserved_at_8[0x18];
e281682b
SM		 4589
4590 u8 syndrome[0x20];
4591
b4ff3a36 4592 u8 reserved_at_40[0x20];
e281682b
SM		 4593
4594 u8 enable[0x1];
4595 u8 tag_enable[0x1];
b4ff3a36 4596 u8 reserved_at_62[0x1e];
e281682b
SM		 4597};
4598
4599struct mlx5_ifc_query_cong_status_in_bits {
4600 u8 opcode[0x10];
b4ff3a36 4601 u8 reserved_at_10[0x10];
e281682b 4602
b4ff3a36 4603 u8 reserved_at_20[0x10];
e281682b
SM		 4604 u8 op_mod[0x10];
4605
b4ff3a36 4606 u8 reserved_at_40[0x18];
e281682b
SM		 4607 u8 priority[0x4];
4608 u8 cong_protocol[0x4];
4609
b4ff3a36 4610 u8 reserved_at_60[0x20];
e281682b
SM		 4611};
4612
4613struct mlx5_ifc_query_cong_statistics_out_bits {
4614 u8 status[0x8];
b4ff3a36 4615 u8 reserved_at_8[0x18];
e281682b
SM		 4616
4617 u8 syndrome[0x20];
4618
b4ff3a36 4619 u8 reserved_at_40[0x40];
e281682b
SM		 4620
4621 u8 cur_flows[0x20];
4622
4623 u8 sum_flows[0x20];
4624
4625 u8 cnp_ignored_high[0x20];
4626
4627 u8 cnp_ignored_low[0x20];
4628
4629 u8 cnp_handled_high[0x20];
4630
4631 u8 cnp_handled_low[0x20];
4632
b4ff3a36 4633 u8 reserved_at_140[0x100];
e281682b
SM		 4634
4635 u8 time_stamp_high[0x20];
4636
4637 u8 time_stamp_low[0x20];
4638
4639 u8 accumulators_period[0x20];
4640
4641 u8 ecn_marked_roce_packets_high[0x20];
4642
4643 u8 ecn_marked_roce_packets_low[0x20];
4644
4645 u8 cnps_sent_high[0x20];
4646
4647 u8 cnps_sent_low[0x20];
4648
b4ff3a36 4649 u8 reserved_at_320[0x560];
e281682b
SM		 4650};
4651
4652struct mlx5_ifc_query_cong_statistics_in_bits {
4653 u8 opcode[0x10];
b4ff3a36 4654 u8 reserved_at_10[0x10];
e281682b 4655
b4ff3a36 4656 u8 reserved_at_20[0x10];
e281682b
SM		 4657 u8 op_mod[0x10];
4658
4659 u8 clear[0x1];
b4ff3a36 4660 u8 reserved_at_41[0x1f];
e281682b 4661
b4ff3a36 4662 u8 reserved_at_60[0x20];
e281682b
SM		 4663};
4664
4665struct mlx5_ifc_query_cong_params_out_bits {
4666 u8 status[0x8];
b4ff3a36 4667 u8 reserved_at_8[0x18];
e281682b
SM		 4668
4669 u8 syndrome[0x20];
4670
b4ff3a36 4671 u8 reserved_at_40[0x40];
e281682b
SM		 4672
4673 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4674};
4675
4676struct mlx5_ifc_query_cong_params_in_bits {
4677 u8 opcode[0x10];
b4ff3a36 4678 u8 reserved_at_10[0x10];
e281682b 4679
b4ff3a36 4680 u8 reserved_at_20[0x10];
e281682b
SM		 4681 u8 op_mod[0x10];
4682
b4ff3a36 4683 u8 reserved_at_40[0x1c];
e281682b
SM		 4684 u8 cong_protocol[0x4];
4685
b4ff3a36 4686 u8 reserved_at_60[0x20];
e281682b
SM		 4687};
4688
4689struct mlx5_ifc_query_adapter_out_bits {
4690 u8 status[0x8];
b4ff3a36 4691 u8 reserved_at_8[0x18];
e281682b
SM		 4692
4693 u8 syndrome[0x20];
4694
b4ff3a36 4695 u8 reserved_at_40[0x40];
e281682b
SM		 4696
4697 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4698};
4699
4700struct mlx5_ifc_query_adapter_in_bits {
4701 u8 opcode[0x10];
b4ff3a36 4702 u8 reserved_at_10[0x10];
e281682b 4703
b4ff3a36 4704 u8 reserved_at_20[0x10];
e281682b
SM		 4705 u8 op_mod[0x10];
4706
b4ff3a36 4707 u8 reserved_at_40[0x40];
e281682b
SM		 4708};
4709
4710struct mlx5_ifc_qp_2rst_out_bits {
4711 u8 status[0x8];
b4ff3a36 4712 u8 reserved_at_8[0x18];
e281682b
SM		 4713
4714 u8 syndrome[0x20];
4715
b4ff3a36 4716 u8 reserved_at_40[0x40];
e281682b
SM		 4717};
4718
4719struct mlx5_ifc_qp_2rst_in_bits {
4720 u8 opcode[0x10];
b4ff3a36 4721 u8 reserved_at_10[0x10];
e281682b 4722
b4ff3a36 4723 u8 reserved_at_20[0x10];
e281682b
SM		 4724 u8 op_mod[0x10];
4725
b4ff3a36 4726 u8 reserved_at_40[0x8];
e281682b
SM		 4727 u8 qpn[0x18];
4728
b4ff3a36 4729 u8 reserved_at_60[0x20];
e281682b
SM		 4730};
4731
4732struct mlx5_ifc_qp_2err_out_bits {
4733 u8 status[0x8];
b4ff3a36 4734 u8 reserved_at_8[0x18];
e281682b
SM		 4735
4736 u8 syndrome[0x20];
4737
b4ff3a36 4738 u8 reserved_at_40[0x40];
e281682b
SM		 4739};
4740
4741struct mlx5_ifc_qp_2err_in_bits {
4742 u8 opcode[0x10];
b4ff3a36 4743 u8 reserved_at_10[0x10];
e281682b 4744
b4ff3a36 4745 u8 reserved_at_20[0x10];
e281682b
SM		 4746 u8 op_mod[0x10];
4747
b4ff3a36 4748 u8 reserved_at_40[0x8];
e281682b
SM		 4749 u8 qpn[0x18];
4750
b4ff3a36 4751 u8 reserved_at_60[0x20];
e281682b
SM		 4752};
4753
4754struct mlx5_ifc_page_fault_resume_out_bits {
4755 u8 status[0x8];
b4ff3a36 4756 u8 reserved_at_8[0x18];
e281682b
SM		 4757
4758 u8 syndrome[0x20];
4759
b4ff3a36 4760 u8 reserved_at_40[0x40];
e281682b
SM		 4761};
4762
4763struct mlx5_ifc_page_fault_resume_in_bits {
4764 u8 opcode[0x10];
b4ff3a36 4765 u8 reserved_at_10[0x10];
e281682b 4766
b4ff3a36 4767 u8 reserved_at_20[0x10];
e281682b
SM		 4768 u8 op_mod[0x10];
4769
4770 u8 error[0x1];
b4ff3a36 4771 u8 reserved_at_41[0x4];
223cdc72
AK		 4772 u8 page_fault_type[0x3];
4773 u8 wq_number[0x18];
e281682b 4774
223cdc72
AK		 4775 u8 reserved_at_60[0x8];
4776 u8 token[0x18];
e281682b
SM		 4777};
4778
4779struct mlx5_ifc_nop_out_bits {
4780 u8 status[0x8];
b4ff3a36 4781 u8 reserved_at_8[0x18];
e281682b
SM		 4782
4783 u8 syndrome[0x20];
4784
b4ff3a36 4785 u8 reserved_at_40[0x40];
e281682b
SM		 4786};
4787
4788struct mlx5_ifc_nop_in_bits {
4789 u8 opcode[0x10];
b4ff3a36 4790 u8 reserved_at_10[0x10];
e281682b 4791
b4ff3a36 4792 u8 reserved_at_20[0x10];
e281682b
SM		 4793 u8 op_mod[0x10];
4794
b4ff3a36 4795 u8 reserved_at_40[0x40];
e281682b
SM		 4796};
4797
4798struct mlx5_ifc_modify_vport_state_out_bits {
4799 u8 status[0x8];
b4ff3a36 4800 u8 reserved_at_8[0x18];
e281682b
SM		 4801
4802 u8 syndrome[0x20];
4803
b4ff3a36 4804 u8 reserved_at_40[0x40];
e281682b
SM		 4805};
4806
4807struct mlx5_ifc_modify_vport_state_in_bits {
4808 u8 opcode[0x10];
b4ff3a36 4809 u8 reserved_at_10[0x10];
e281682b 4810
b4ff3a36 4811 u8 reserved_at_20[0x10];
e281682b
SM		 4812 u8 op_mod[0x10];
4813
4814 u8 other_vport[0x1];
b4ff3a36 4815 u8 reserved_at_41[0xf];
e281682b
SM		 4816 u8 vport_number[0x10];
4817
b4ff3a36 4818 u8 reserved_at_60[0x18];
e281682b 4819 u8 admin_state[0x4];
b4ff3a36 4820 u8 reserved_at_7c[0x4];
e281682b
SM		 4821};
4822
4823struct mlx5_ifc_modify_tis_out_bits {
4824 u8 status[0x8];
b4ff3a36 4825 u8 reserved_at_8[0x18];
e281682b
SM		 4826
4827 u8 syndrome[0x20];
4828
b4ff3a36 4829 u8 reserved_at_40[0x40];
e281682b
SM		 4830};
4831
75850d0b 4832struct mlx5_ifc_modify_tis_bitmask_bits {
b4ff3a36 4833 u8 reserved_at_0[0x20];
75850d0b 4834
84df61eb
AH		 4835 u8 reserved_at_20[0x1d];
4836 u8 lag_tx_port_affinity[0x1];
4837 u8 strict_lag_tx_port_affinity[0x1];
75850d0b 4838 u8 prio[0x1];
4839};
4840
e281682b
SM		 4841struct mlx5_ifc_modify_tis_in_bits {
4842 u8 opcode[0x10];
b4ff3a36 4843 u8 reserved_at_10[0x10];
e281682b 4844
b4ff3a36 4845 u8 reserved_at_20[0x10];
e281682b
SM		 4846 u8 op_mod[0x10];
4847
b4ff3a36 4848 u8 reserved_at_40[0x8];
e281682b
SM		 4849 u8 tisn[0x18];
4850
b4ff3a36 4851 u8 reserved_at_60[0x20];
e281682b 4852
75850d0b 4853 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
e281682b 4854
b4ff3a36 4855 u8 reserved_at_c0[0x40];
e281682b
SM		 4856
4857 struct mlx5_ifc_tisc_bits ctx;
4858};
4859
d9eea403 4860struct mlx5_ifc_modify_tir_bitmask_bits {
b4ff3a36 4861 u8 reserved_at_0[0x20];
d9eea403 4862
b4ff3a36 4863 u8 reserved_at_20[0x1b];
66189961 4864 u8 self_lb_en[0x1];
bdfc028d
TT		 4865 u8 reserved_at_3c[0x1];
4866 u8 hash[0x1];
4867 u8 reserved_at_3e[0x1];
d9eea403
AS		 4868 u8 lro[0x1];
4869};
4870
e281682b
SM		 4871struct mlx5_ifc_modify_tir_out_bits {
4872 u8 status[0x8];
b4ff3a36 4873 u8 reserved_at_8[0x18];
e281682b
SM		 4874
4875 u8 syndrome[0x20];
4876
b4ff3a36 4877 u8 reserved_at_40[0x40];
e281682b
SM		 4878};
4879
4880struct mlx5_ifc_modify_tir_in_bits {
4881 u8 opcode[0x10];
b4ff3a36 4882 u8 reserved_at_10[0x10];
e281682b 4883
b4ff3a36 4884 u8 reserved_at_20[0x10];
e281682b
SM		 4885 u8 op_mod[0x10];
4886
b4ff3a36 4887 u8 reserved_at_40[0x8];
e281682b
SM		 4888 u8 tirn[0x18];
4889
b4ff3a36 4890 u8 reserved_at_60[0x20];
e281682b 4891
d9eea403 4892 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
e281682b 4893
b4ff3a36 4894 u8 reserved_at_c0[0x40];
e281682b
SM		 4895
4896 struct mlx5_ifc_tirc_bits ctx;
4897};
4898
4899struct mlx5_ifc_modify_sq_out_bits {
4900 u8 status[0x8];
b4ff3a36 4901 u8 reserved_at_8[0x18];
e281682b
SM		 4902
4903 u8 syndrome[0x20];
4904
b4ff3a36 4905 u8 reserved_at_40[0x40];
e281682b
SM		 4906};
4907
4908struct mlx5_ifc_modify_sq_in_bits {
4909 u8 opcode[0x10];
b4ff3a36 4910 u8 reserved_at_10[0x10];
e281682b 4911
b4ff3a36 4912 u8 reserved_at_20[0x10];
e281682b
SM		 4913 u8 op_mod[0x10];
4914
4915 u8 sq_state[0x4];
b4ff3a36 4916 u8 reserved_at_44[0x4];
e281682b
SM		 4917 u8 sqn[0x18];
4918
b4ff3a36 4919 u8 reserved_at_60[0x20];
e281682b
SM		 4920
4921 u8 modify_bitmask[0x40];
4922
b4ff3a36 4923 u8 reserved_at_c0[0x40];
e281682b
SM		 4924
4925 struct mlx5_ifc_sqc_bits ctx;
4926};
4927
813f8540
MHY		 4928struct mlx5_ifc_modify_scheduling_element_out_bits {
4929 u8 status[0x8];
4930 u8 reserved_at_8[0x18];
4931
4932 u8 syndrome[0x20];
4933
4934 u8 reserved_at_40[0x1c0];
4935};
4936
4937enum {
4938 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
4939 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
4940};
4941
4942struct mlx5_ifc_modify_scheduling_element_in_bits {
4943 u8 opcode[0x10];
4944 u8 reserved_at_10[0x10];
4945
4946 u8 reserved_at_20[0x10];
4947 u8 op_mod[0x10];
4948
4949 u8 scheduling_hierarchy[0x8];
4950 u8 reserved_at_48[0x18];
4951
4952 u8 scheduling_element_id[0x20];
4953
4954 u8 reserved_at_80[0x20];
4955
4956 u8 modify_bitmask[0x20];
4957
4958 u8 reserved_at_c0[0x40];
4959
4960 struct mlx5_ifc_scheduling_context_bits scheduling_context;
4961
4962 u8 reserved_at_300[0x100];
4963};
4964
e281682b
SM		 4965struct mlx5_ifc_modify_rqt_out_bits {
4966 u8 status[0x8];
b4ff3a36 4967 u8 reserved_at_8[0x18];
e281682b
SM		 4968
4969 u8 syndrome[0x20];
4970
b4ff3a36 4971 u8 reserved_at_40[0x40];
e281682b
SM		 4972};
4973
5c50368f 4974struct mlx5_ifc_rqt_bitmask_bits {
b4ff3a36 4975 u8 reserved_at_0[0x20];
5c50368f 4976
b4ff3a36 4977 u8 reserved_at_20[0x1f];
5c50368f
AS		 4978 u8 rqn_list[0x1];
4979};
4980
e281682b
SM		 4981struct mlx5_ifc_modify_rqt_in_bits {
4982 u8 opcode[0x10];
b4ff3a36 4983 u8 reserved_at_10[0x10];
e281682b 4984
b4ff3a36 4985 u8 reserved_at_20[0x10];
e281682b
SM		 4986 u8 op_mod[0x10];
4987
b4ff3a36 4988 u8 reserved_at_40[0x8];
e281682b
SM		 4989 u8 rqtn[0x18];
4990
b4ff3a36 4991 u8 reserved_at_60[0x20];
e281682b 4992
5c50368f 4993 struct mlx5_ifc_rqt_bitmask_bits bitmask;
e281682b 4994
b4ff3a36 4995 u8 reserved_at_c0[0x40];
e281682b
SM		 4996
4997 struct mlx5_ifc_rqtc_bits ctx;
4998};
4999
5000struct mlx5_ifc_modify_rq_out_bits {
5001 u8 status[0x8];
b4ff3a36 5002 u8 reserved_at_8[0x18];
e281682b
SM		 5003
5004 u8 syndrome[0x20];
5005
b4ff3a36 5006 u8 reserved_at_40[0x40];
e281682b
SM		 5007};
5008
83b502a1
AV		 5009enum {
5010 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
5011 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID = 1ULL << 3,
5012};
5013
e281682b
SM		 5014struct mlx5_ifc_modify_rq_in_bits {
5015 u8 opcode[0x10];
b4ff3a36 5016 u8 reserved_at_10[0x10];
e281682b 5017
b4ff3a36 5018 u8 reserved_at_20[0x10];
e281682b
SM		 5019 u8 op_mod[0x10];
5020
5021 u8 rq_state[0x4];
b4ff3a36 5022 u8 reserved_at_44[0x4];
e281682b
SM		 5023 u8 rqn[0x18];
5024
b4ff3a36 5025 u8 reserved_at_60[0x20];
e281682b
SM		 5026
5027 u8 modify_bitmask[0x40];
5028
b4ff3a36 5029 u8 reserved_at_c0[0x40];
e281682b
SM		 5030
5031 struct mlx5_ifc_rqc_bits ctx;
5032};
5033
5034struct mlx5_ifc_modify_rmp_out_bits {
5035 u8 status[0x8];
b4ff3a36 5036 u8 reserved_at_8[0x18];
e281682b
SM		 5037
5038 u8 syndrome[0x20];
5039
b4ff3a36 5040 u8 reserved_at_40[0x40];
e281682b
SM		 5041};
5042
01949d01 5043struct mlx5_ifc_rmp_bitmask_bits {
b4ff3a36 5044 u8 reserved_at_0[0x20];
01949d01 5045
b4ff3a36 5046 u8 reserved_at_20[0x1f];
01949d01
HA		 5047 u8 lwm[0x1];
5048};
5049
e281682b
SM		 5050struct mlx5_ifc_modify_rmp_in_bits {
5051 u8 opcode[0x10];
b4ff3a36 5052 u8 reserved_at_10[0x10];
e281682b 5053
b4ff3a36 5054 u8 reserved_at_20[0x10];
e281682b
SM		 5055 u8 op_mod[0x10];
5056
5057 u8 rmp_state[0x4];
b4ff3a36 5058 u8 reserved_at_44[0x4];
e281682b
SM		 5059 u8 rmpn[0x18];
5060
b4ff3a36 5061 u8 reserved_at_60[0x20];
e281682b 5062
01949d01 5063 struct mlx5_ifc_rmp_bitmask_bits bitmask;
e281682b 5064
b4ff3a36 5065 u8 reserved_at_c0[0x40];
e281682b
SM		 5066
5067 struct mlx5_ifc_rmpc_bits ctx;
5068};
5069
5070struct mlx5_ifc_modify_nic_vport_context_out_bits {
5071 u8 status[0x8];
b4ff3a36 5072 u8 reserved_at_8[0x18];
e281682b
SM		 5073
5074 u8 syndrome[0x20];
5075
b4ff3a36 5076 u8 reserved_at_40[0x40];
e281682b
SM		 5077};
5078
5079struct mlx5_ifc_modify_nic_vport_field_select_bits {
23898c76
NO		 5080 u8 reserved_at_0[0x16];
5081 u8 node_guid[0x1];
5082 u8 port_guid[0x1];
9def7121 5083 u8 min_inline[0x1];
d82b7318
SM		 5084 u8 mtu[0x1];
5085 u8 change_event[0x1];
5086 u8 promisc[0x1];
e281682b
SM		 5087 u8 permanent_address[0x1];
5088 u8 addresses_list[0x1];
5089 u8 roce_en[0x1];
b4ff3a36 5090 u8 reserved_at_1f[0x1];
e281682b
SM		 5091};
5092
5093struct mlx5_ifc_modify_nic_vport_context_in_bits {
5094 u8 opcode[0x10];
b4ff3a36 5095 u8 reserved_at_10[0x10];
e281682b 5096
b4ff3a36 5097 u8 reserved_at_20[0x10];
e281682b
SM		 5098 u8 op_mod[0x10];
5099
5100 u8 other_vport[0x1];
b4ff3a36 5101 u8 reserved_at_41[0xf];
e281682b
SM		 5102 u8 vport_number[0x10];
5103
5104 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5105
b4ff3a36 5106 u8 reserved_at_80[0x780];
e281682b
SM		 5107
5108 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5109};
5110
5111struct mlx5_ifc_modify_hca_vport_context_out_bits {
5112 u8 status[0x8];
b4ff3a36 5113 u8 reserved_at_8[0x18];
e281682b
SM		 5114
5115 u8 syndrome[0x20];
5116
b4ff3a36 5117 u8 reserved_at_40[0x40];
e281682b
SM		 5118};
5119
5120struct mlx5_ifc_modify_hca_vport_context_in_bits {
5121 u8 opcode[0x10];
b4ff3a36 5122 u8 reserved_at_10[0x10];
e281682b 5123
b4ff3a36 5124 u8 reserved_at_20[0x10];
e281682b
SM		 5125 u8 op_mod[0x10];
5126
5127 u8 other_vport[0x1];
b4ff3a36 5128 u8 reserved_at_41[0xb];
707c4602 5129 u8 port_num[0x4];
e281682b
SM		 5130 u8 vport_number[0x10];
5131
b4ff3a36 5132 u8 reserved_at_60[0x20];
e281682b
SM		 5133
5134 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5135};
5136
5137struct mlx5_ifc_modify_cq_out_bits {
5138 u8 status[0x8];
b4ff3a36 5139 u8 reserved_at_8[0x18];
e281682b
SM		 5140
5141 u8 syndrome[0x20];
5142
b4ff3a36 5143 u8 reserved_at_40[0x40];
e281682b
SM		 5144};
5145
5146enum {
5147 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
5148 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
5149};
5150
5151struct mlx5_ifc_modify_cq_in_bits {
5152 u8 opcode[0x10];
b4ff3a36 5153 u8 reserved_at_10[0x10];
e281682b 5154
b4ff3a36 5155 u8 reserved_at_20[0x10];
e281682b
SM		 5156 u8 op_mod[0x10];
5157
b4ff3a36 5158 u8 reserved_at_40[0x8];
e281682b
SM		 5159 u8 cqn[0x18];
5160
5161 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5162
5163 struct mlx5_ifc_cqc_bits cq_context;
5164
b4ff3a36 5165 u8 reserved_at_280[0x600];
e281682b
SM		 5166
5167 u8 pas[0][0x40];
5168};
5169
5170struct mlx5_ifc_modify_cong_status_out_bits {
5171 u8 status[0x8];
b4ff3a36 5172 u8 reserved_at_8[0x18];
e281682b
SM		 5173
5174 u8 syndrome[0x20];
5175
b4ff3a36 5176 u8 reserved_at_40[0x40];
e281682b
SM		 5177};
5178
5179struct mlx5_ifc_modify_cong_status_in_bits {
5180 u8 opcode[0x10];
b4ff3a36 5181 u8 reserved_at_10[0x10];
e281682b 5182
b4ff3a36 5183 u8 reserved_at_20[0x10];
e281682b
SM		 5184 u8 op_mod[0x10];
5185
b4ff3a36 5186 u8 reserved_at_40[0x18];
e281682b
SM		 5187 u8 priority[0x4];
5188 u8 cong_protocol[0x4];
5189
5190 u8 enable[0x1];
5191 u8 tag_enable[0x1];
b4ff3a36 5192 u8 reserved_at_62[0x1e];
e281682b
SM		 5193};
5194
5195struct mlx5_ifc_modify_cong_params_out_bits {
5196 u8 status[0x8];
b4ff3a36 5197 u8 reserved_at_8[0x18];
e281682b
SM		 5198
5199 u8 syndrome[0x20];
5200
b4ff3a36 5201 u8 reserved_at_40[0x40];
e281682b
SM		 5202};
5203
5204struct mlx5_ifc_modify_cong_params_in_bits {
5205 u8 opcode[0x10];
b4ff3a36 5206 u8 reserved_at_10[0x10];
e281682b 5207
b4ff3a36 5208 u8 reserved_at_20[0x10];
e281682b
SM		 5209 u8 op_mod[0x10];
5210
b4ff3a36 5211 u8 reserved_at_40[0x1c];
e281682b
SM		 5212 u8 cong_protocol[0x4];
5213
5214 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5215
b4ff3a36 5216 u8 reserved_at_80[0x80];
e281682b
SM		 5217
5218 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5219};
5220
5221struct mlx5_ifc_manage_pages_out_bits {
5222 u8 status[0x8];
b4ff3a36 5223 u8 reserved_at_8[0x18];
e281682b
SM		 5224
5225 u8 syndrome[0x20];
5226
5227 u8 output_num_entries[0x20];
5228
b4ff3a36 5229 u8 reserved_at_60[0x20];
e281682b
SM		 5230
5231 u8 pas[0][0x40];
5232};
5233
5234enum {
5235 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
5236 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
5237 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
5238};
5239
5240struct mlx5_ifc_manage_pages_in_bits {
5241 u8 opcode[0x10];
b4ff3a36 5242 u8 reserved_at_10[0x10];
e281682b 5243
b4ff3a36 5244 u8 reserved_at_20[0x10];
e281682b
SM		 5245 u8 op_mod[0x10];
5246
b4ff3a36 5247 u8 reserved_at_40[0x10];
e281682b
SM		 5248 u8 function_id[0x10];
5249
5250 u8 input_num_entries[0x20];
5251
5252 u8 pas[0][0x40];
5253};
5254
5255struct mlx5_ifc_mad_ifc_out_bits {
5256 u8 status[0x8];
b4ff3a36 5257 u8 reserved_at_8[0x18];
e281682b
SM		 5258
5259 u8 syndrome[0x20];
5260
b4ff3a36 5261 u8 reserved_at_40[0x40];
e281682b
SM		 5262
5263 u8 response_mad_packet[256][0x8];
5264};
5265
5266struct mlx5_ifc_mad_ifc_in_bits {
5267 u8 opcode[0x10];
b4ff3a36 5268 u8 reserved_at_10[0x10];
e281682b 5269
b4ff3a36 5270 u8 reserved_at_20[0x10];
e281682b
SM		 5271 u8 op_mod[0x10];
5272
5273 u8 remote_lid[0x10];
b4ff3a36 5274 u8 reserved_at_50[0x8];
e281682b
SM		 5275 u8 port[0x8];
5276
b4ff3a36 5277 u8 reserved_at_60[0x20];
e281682b
SM		 5278
5279 u8 mad[256][0x8];
5280};
5281
5282struct mlx5_ifc_init_hca_out_bits {
5283 u8 status[0x8];
b4ff3a36 5284 u8 reserved_at_8[0x18];
e281682b
SM		 5285
5286 u8 syndrome[0x20];
5287
b4ff3a36 5288 u8 reserved_at_40[0x40];
e281682b
SM		 5289};
5290
5291struct mlx5_ifc_init_hca_in_bits {
5292 u8 opcode[0x10];
b4ff3a36 5293 u8 reserved_at_10[0x10];
e281682b 5294
b4ff3a36 5295 u8 reserved_at_20[0x10];
e281682b
SM		 5296 u8 op_mod[0x10];
5297
b4ff3a36 5298 u8 reserved_at_40[0x40];
e281682b
SM		 5299};
5300
5301struct mlx5_ifc_init2rtr_qp_out_bits {
5302 u8 status[0x8];
b4ff3a36 5303 u8 reserved_at_8[0x18];
e281682b
SM		 5304
5305 u8 syndrome[0x20];
5306
b4ff3a36 5307 u8 reserved_at_40[0x40];
e281682b
SM		 5308};
5309
5310struct mlx5_ifc_init2rtr_qp_in_bits {
5311 u8 opcode[0x10];
b4ff3a36 5312 u8 reserved_at_10[0x10];
e281682b 5313
b4ff3a36 5314 u8 reserved_at_20[0x10];
e281682b
SM		 5315 u8 op_mod[0x10];
5316
b4ff3a36 5317 u8 reserved_at_40[0x8];
e281682b
SM		 5318 u8 qpn[0x18];
5319
b4ff3a36 5320 u8 reserved_at_60[0x20];
e281682b
SM		 5321
5322 u8 opt_param_mask[0x20];
5323
b4ff3a36 5324 u8 reserved_at_a0[0x20];
e281682b
SM		 5325
5326 struct mlx5_ifc_qpc_bits qpc;
5327
b4ff3a36 5328 u8 reserved_at_800[0x80];
e281682b
SM		 5329};
5330
5331struct mlx5_ifc_init2init_qp_out_bits {
5332 u8 status[0x8];
b4ff3a36 5333 u8 reserved_at_8[0x18];
e281682b
SM		 5334
5335 u8 syndrome[0x20];
5336
b4ff3a36 5337 u8 reserved_at_40[0x40];
e281682b
SM		 5338};
5339
5340struct mlx5_ifc_init2init_qp_in_bits {
5341 u8 opcode[0x10];
b4ff3a36 5342 u8 reserved_at_10[0x10];
e281682b 5343
b4ff3a36 5344 u8 reserved_at_20[0x10];
e281682b
SM		 5345 u8 op_mod[0x10];
5346
b4ff3a36 5347 u8 reserved_at_40[0x8];
e281682b
SM		 5348 u8 qpn[0x18];
5349
b4ff3a36 5350 u8 reserved_at_60[0x20];
e281682b
SM		 5351
5352 u8 opt_param_mask[0x20];
5353
b4ff3a36 5354 u8 reserved_at_a0[0x20];
e281682b
SM		 5355
5356 struct mlx5_ifc_qpc_bits qpc;
5357
b4ff3a36 5358 u8 reserved_at_800[0x80];
e281682b
SM		 5359};
5360
5361struct mlx5_ifc_get_dropped_packet_log_out_bits {
5362 u8 status[0x8];
b4ff3a36 5363 u8 reserved_at_8[0x18];
e281682b
SM		 5364
5365 u8 syndrome[0x20];
5366
b4ff3a36 5367 u8 reserved_at_40[0x40];
e281682b
SM		 5368
5369 u8 packet_headers_log[128][0x8];
5370
5371 u8 packet_syndrome[64][0x8];
5372};
5373
5374struct mlx5_ifc_get_dropped_packet_log_in_bits {
5375 u8 opcode[0x10];
b4ff3a36 5376 u8 reserved_at_10[0x10];
e281682b 5377
b4ff3a36 5378 u8 reserved_at_20[0x10];
e281682b
SM		 5379 u8 op_mod[0x10];
5380
b4ff3a36 5381 u8 reserved_at_40[0x40];
e281682b
SM		 5382};
5383
5384struct mlx5_ifc_gen_eqe_in_bits {
5385 u8 opcode[0x10];
b4ff3a36 5386 u8 reserved_at_10[0x10];
e281682b 5387
b4ff3a36 5388 u8 reserved_at_20[0x10];
e281682b
SM		 5389 u8 op_mod[0x10];
5390
b4ff3a36 5391 u8 reserved_at_40[0x18];
e281682b
SM		 5392 u8 eq_number[0x8];
5393
b4ff3a36 5394 u8 reserved_at_60[0x20];
e281682b
SM		 5395
5396 u8 eqe[64][0x8];
5397};
5398
5399struct mlx5_ifc_gen_eq_out_bits {
5400 u8 status[0x8];
b4ff3a36 5401 u8 reserved_at_8[0x18];
e281682b
SM		 5402
5403 u8 syndrome[0x20];
5404
b4ff3a36 5405 u8 reserved_at_40[0x40];
e281682b
SM		 5406};
5407
5408struct mlx5_ifc_enable_hca_out_bits {
5409 u8 status[0x8];
b4ff3a36 5410 u8 reserved_at_8[0x18];
e281682b
SM		 5411
5412 u8 syndrome[0x20];
5413
b4ff3a36 5414 u8 reserved_at_40[0x20];
e281682b
SM		 5415};
5416
5417struct mlx5_ifc_enable_hca_in_bits {
5418 u8 opcode[0x10];
b4ff3a36 5419 u8 reserved_at_10[0x10];
e281682b 5420
b4ff3a36 5421 u8 reserved_at_20[0x10];
e281682b
SM		 5422 u8 op_mod[0x10];
5423
b4ff3a36 5424 u8 reserved_at_40[0x10];
e281682b
SM		 5425 u8 function_id[0x10];
5426
b4ff3a36 5427 u8 reserved_at_60[0x20];
e281682b
SM		 5428};
5429
5430struct mlx5_ifc_drain_dct_out_bits {
5431 u8 status[0x8];
b4ff3a36 5432 u8 reserved_at_8[0x18];
e281682b
SM		 5433
5434 u8 syndrome[0x20];
5435
b4ff3a36 5436 u8 reserved_at_40[0x40];
e281682b
SM		 5437};
5438
5439struct mlx5_ifc_drain_dct_in_bits {
5440 u8 opcode[0x10];
b4ff3a36 5441 u8 reserved_at_10[0x10];
e281682b 5442
b4ff3a36 5443 u8 reserved_at_20[0x10];
e281682b
SM		 5444 u8 op_mod[0x10];
5445
b4ff3a36 5446 u8 reserved_at_40[0x8];
e281682b
SM		 5447 u8 dctn[0x18];
5448
b4ff3a36 5449 u8 reserved_at_60[0x20];
e281682b
SM		 5450};
5451
5452struct mlx5_ifc_disable_hca_out_bits {
5453 u8 status[0x8];
b4ff3a36 5454 u8 reserved_at_8[0x18];
e281682b
SM		 5455
5456 u8 syndrome[0x20];
5457
b4ff3a36 5458 u8 reserved_at_40[0x20];
e281682b
SM		 5459};
5460
5461struct mlx5_ifc_disable_hca_in_bits {
5462 u8 opcode[0x10];
b4ff3a36 5463 u8 reserved_at_10[0x10];
e281682b 5464
b4ff3a36 5465 u8 reserved_at_20[0x10];
e281682b
SM		 5466 u8 op_mod[0x10];
5467
b4ff3a36 5468 u8 reserved_at_40[0x10];
e281682b
SM		 5469 u8 function_id[0x10];
5470
b4ff3a36 5471 u8 reserved_at_60[0x20];
e281682b
SM		 5472};
5473
5474struct mlx5_ifc_detach_from_mcg_out_bits {
5475 u8 status[0x8];
b4ff3a36 5476 u8 reserved_at_8[0x18];
e281682b
SM		 5477
5478 u8 syndrome[0x20];
5479
b4ff3a36 5480 u8 reserved_at_40[0x40];
e281682b
SM		 5481};
5482
5483struct mlx5_ifc_detach_from_mcg_in_bits {
5484 u8 opcode[0x10];
b4ff3a36 5485 u8 reserved_at_10[0x10];
e281682b 5486
b4ff3a36 5487 u8 reserved_at_20[0x10];
e281682b
SM		 5488 u8 op_mod[0x10];
5489
b4ff3a36 5490 u8 reserved_at_40[0x8];
e281682b
SM		 5491 u8 qpn[0x18];
5492
b4ff3a36 5493 u8 reserved_at_60[0x20];
e281682b
SM		 5494
5495 u8 multicast_gid[16][0x8];
5496};
5497
7486216b
SM		 5498struct mlx5_ifc_destroy_xrq_out_bits {
5499 u8 status[0x8];
5500 u8 reserved_at_8[0x18];
5501
5502 u8 syndrome[0x20];
5503
5504 u8 reserved_at_40[0x40];
5505};
5506
5507struct mlx5_ifc_destroy_xrq_in_bits {
5508 u8 opcode[0x10];
5509 u8 reserved_at_10[0x10];
5510
5511 u8 reserved_at_20[0x10];
5512 u8 op_mod[0x10];
5513
5514 u8 reserved_at_40[0x8];
5515 u8 xrqn[0x18];
5516
5517 u8 reserved_at_60[0x20];
5518};
5519
e281682b
SM		 5520struct mlx5_ifc_destroy_xrc_srq_out_bits {
5521 u8 status[0x8];
b4ff3a36 5522 u8 reserved_at_8[0x18];
e281682b
SM		 5523
5524 u8 syndrome[0x20];
5525
b4ff3a36 5526 u8 reserved_at_40[0x40];
e281682b
SM		 5527};
5528
5529struct mlx5_ifc_destroy_xrc_srq_in_bits {
5530 u8 opcode[0x10];
b4ff3a36 5531 u8 reserved_at_10[0x10];
e281682b 5532
b4ff3a36 5533 u8 reserved_at_20[0x10];
e281682b
SM		 5534 u8 op_mod[0x10];
5535
b4ff3a36 5536 u8 reserved_at_40[0x8];
e281682b
SM		 5537 u8 xrc_srqn[0x18];
5538
b4ff3a36 5539 u8 reserved_at_60[0x20];
e281682b
SM		 5540};
5541
5542struct mlx5_ifc_destroy_tis_out_bits {
5543 u8 status[0x8];
b4ff3a36 5544 u8 reserved_at_8[0x18];
e281682b
SM		 5545
5546 u8 syndrome[0x20];
5547
b4ff3a36 5548 u8 reserved_at_40[0x40];
e281682b
SM		 5549};
5550
5551struct mlx5_ifc_destroy_tis_in_bits {
5552 u8 opcode[0x10];
b4ff3a36 5553 u8 reserved_at_10[0x10];
e281682b 5554
b4ff3a36 5555 u8 reserved_at_20[0x10];
e281682b
SM		 5556 u8 op_mod[0x10];
5557
b4ff3a36 5558 u8 reserved_at_40[0x8];
e281682b
SM		 5559 u8 tisn[0x18];
5560
b4ff3a36 5561 u8 reserved_at_60[0x20];
e281682b
SM		 5562};
5563
5564struct mlx5_ifc_destroy_tir_out_bits {
5565 u8 status[0x8];
b4ff3a36 5566 u8 reserved_at_8[0x18];
e281682b
SM		 5567
5568 u8 syndrome[0x20];
5569
b4ff3a36 5570 u8 reserved_at_40[0x40];
e281682b
SM		 5571};
5572
5573struct mlx5_ifc_destroy_tir_in_bits {
5574 u8 opcode[0x10];
b4ff3a36 5575 u8 reserved_at_10[0x10];
e281682b 5576
b4ff3a36 5577 u8 reserved_at_20[0x10];
e281682b
SM		 5578 u8 op_mod[0x10];
5579
b4ff3a36 5580 u8 reserved_at_40[0x8];
e281682b
SM		 5581 u8 tirn[0x18];
5582
b4ff3a36 5583 u8 reserved_at_60[0x20];
e281682b
SM		 5584};
5585
5586struct mlx5_ifc_destroy_srq_out_bits {
5587 u8 status[0x8];
b4ff3a36 5588 u8 reserved_at_8[0x18];
e281682b
SM		 5589
5590 u8 syndrome[0x20];
5591
b4ff3a36 5592 u8 reserved_at_40[0x40];
e281682b
SM		 5593};
5594
5595struct mlx5_ifc_destroy_srq_in_bits {
5596 u8 opcode[0x10];
b4ff3a36 5597 u8 reserved_at_10[0x10];
e281682b 5598
b4ff3a36 5599 u8 reserved_at_20[0x10];
e281682b
SM		 5600 u8 op_mod[0x10];
5601
b4ff3a36 5602 u8 reserved_at_40[0x8];
e281682b
SM		 5603 u8 srqn[0x18];
5604
b4ff3a36 5605 u8 reserved_at_60[0x20];
e281682b
SM		 5606};
5607
5608struct mlx5_ifc_destroy_sq_out_bits {
5609 u8 status[0x8];
b4ff3a36 5610 u8 reserved_at_8[0x18];
e281682b
SM		 5611
5612 u8 syndrome[0x20];
5613
b4ff3a36 5614 u8 reserved_at_40[0x40];
e281682b
SM		 5615};
5616
5617struct mlx5_ifc_destroy_sq_in_bits {
5618 u8 opcode[0x10];
b4ff3a36 5619 u8 reserved_at_10[0x10];
e281682b 5620
b4ff3a36 5621 u8 reserved_at_20[0x10];
e281682b
SM		 5622 u8 op_mod[0x10];
5623
b4ff3a36 5624 u8 reserved_at_40[0x8];
e281682b
SM		 5625 u8 sqn[0x18];
5626
b4ff3a36 5627 u8 reserved_at_60[0x20];
e281682b
SM		 5628};
5629
813f8540
MHY		 5630struct mlx5_ifc_destroy_scheduling_element_out_bits {
5631 u8 status[0x8];
5632 u8 reserved_at_8[0x18];
5633
5634 u8 syndrome[0x20];
5635
5636 u8 reserved_at_40[0x1c0];
5637};
5638
5639struct mlx5_ifc_destroy_scheduling_element_in_bits {
5640 u8 opcode[0x10];
5641 u8 reserved_at_10[0x10];
5642
5643 u8 reserved_at_20[0x10];
5644 u8 op_mod[0x10];
5645
5646 u8 scheduling_hierarchy[0x8];
5647 u8 reserved_at_48[0x18];
5648
5649 u8 scheduling_element_id[0x20];
5650
5651 u8 reserved_at_80[0x180];
5652};
5653
e281682b
SM		 5654struct mlx5_ifc_destroy_rqt_out_bits {
5655 u8 status[0x8];
b4ff3a36 5656 u8 reserved_at_8[0x18];
e281682b
SM		 5657
5658 u8 syndrome[0x20];
5659
b4ff3a36 5660 u8 reserved_at_40[0x40];
e281682b
SM		 5661};
5662
5663struct mlx5_ifc_destroy_rqt_in_bits {
5664 u8 opcode[0x10];
b4ff3a36 5665 u8 reserved_at_10[0x10];
e281682b 5666
b4ff3a36 5667 u8 reserved_at_20[0x10];
e281682b
SM		 5668 u8 op_mod[0x10];
5669
b4ff3a36 5670 u8 reserved_at_40[0x8];
e281682b
SM		 5671 u8 rqtn[0x18];
5672
b4ff3a36 5673 u8 reserved_at_60[0x20];
e281682b
SM		 5674};
5675
5676struct mlx5_ifc_destroy_rq_out_bits {
5677 u8 status[0x8];
b4ff3a36 5678 u8 reserved_at_8[0x18];
e281682b
SM		 5679
5680 u8 syndrome[0x20];
5681
b4ff3a36 5682 u8 reserved_at_40[0x40];
e281682b
SM		 5683};
5684
5685struct mlx5_ifc_destroy_rq_in_bits {
5686 u8 opcode[0x10];
b4ff3a36 5687 u8 reserved_at_10[0x10];
e281682b 5688
b4ff3a36 5689 u8 reserved_at_20[0x10];
e281682b
SM		 5690 u8 op_mod[0x10];
5691
b4ff3a36 5692 u8 reserved_at_40[0x8];
e281682b
SM		 5693 u8 rqn[0x18];
5694
b4ff3a36 5695 u8 reserved_at_60[0x20];
e281682b
SM		 5696};
5697
5698struct mlx5_ifc_destroy_rmp_out_bits {
5699 u8 status[0x8];
b4ff3a36 5700 u8 reserved_at_8[0x18];
e281682b
SM		 5701
5702 u8 syndrome[0x20];
5703
b4ff3a36 5704 u8 reserved_at_40[0x40];
e281682b
SM		 5705};
5706
5707struct mlx5_ifc_destroy_rmp_in_bits {
5708 u8 opcode[0x10];
b4ff3a36 5709 u8 reserved_at_10[0x10];
e281682b 5710
b4ff3a36 5711 u8 reserved_at_20[0x10];
e281682b
SM		 5712 u8 op_mod[0x10];
5713
b4ff3a36 5714 u8 reserved_at_40[0x8];
e281682b
SM		 5715 u8 rmpn[0x18];
5716
b4ff3a36 5717 u8 reserved_at_60[0x20];
e281682b
SM		 5718};
5719
5720struct mlx5_ifc_destroy_qp_out_bits {
5721 u8 status[0x8];
b4ff3a36 5722 u8 reserved_at_8[0x18];
e281682b
SM		 5723
5724 u8 syndrome[0x20];
5725
b4ff3a36 5726 u8 reserved_at_40[0x40];
e281682b
SM		 5727};
5728
5729struct mlx5_ifc_destroy_qp_in_bits {
5730 u8 opcode[0x10];
b4ff3a36 5731 u8 reserved_at_10[0x10];
e281682b 5732
b4ff3a36 5733 u8 reserved_at_20[0x10];
e281682b
SM		 5734 u8 op_mod[0x10];
5735
b4ff3a36 5736 u8 reserved_at_40[0x8];
e281682b
SM		 5737 u8 qpn[0x18];
5738
b4ff3a36 5739 u8 reserved_at_60[0x20];
e281682b
SM		 5740};
5741
5742struct mlx5_ifc_destroy_psv_out_bits {
5743 u8 status[0x8];
b4ff3a36 5744 u8 reserved_at_8[0x18];
e281682b
SM		 5745
5746 u8 syndrome[0x20];
5747
b4ff3a36 5748 u8 reserved_at_40[0x40];
e281682b
SM		 5749};
5750
5751struct mlx5_ifc_destroy_psv_in_bits {
5752 u8 opcode[0x10];
b4ff3a36 5753 u8 reserved_at_10[0x10];
e281682b 5754
b4ff3a36 5755 u8 reserved_at_20[0x10];
e281682b
SM		 5756 u8 op_mod[0x10];
5757
b4ff3a36 5758 u8 reserved_at_40[0x8];
e281682b
SM		 5759 u8 psvn[0x18];
5760
b4ff3a36 5761 u8 reserved_at_60[0x20];
e281682b
SM		 5762};
5763
5764struct mlx5_ifc_destroy_mkey_out_bits {
5765 u8 status[0x8];
b4ff3a36 5766 u8 reserved_at_8[0x18];
e281682b
SM		 5767
5768 u8 syndrome[0x20];
5769
b4ff3a36 5770 u8 reserved_at_40[0x40];
e281682b
SM		 5771};
5772
5773struct mlx5_ifc_destroy_mkey_in_bits {
5774 u8 opcode[0x10];
b4ff3a36 5775 u8 reserved_at_10[0x10];
e281682b 5776
b4ff3a36 5777 u8 reserved_at_20[0x10];
e281682b
SM		 5778 u8 op_mod[0x10];
5779
b4ff3a36 5780 u8 reserved_at_40[0x8];
e281682b
SM		 5781 u8 mkey_index[0x18];
5782
b4ff3a36 5783 u8 reserved_at_60[0x20];
e281682b
SM		 5784};
5785
5786struct mlx5_ifc_destroy_flow_table_out_bits {
5787 u8 status[0x8];
b4ff3a36 5788 u8 reserved_at_8[0x18];
e281682b
SM		 5789
5790 u8 syndrome[0x20];
5791
b4ff3a36 5792 u8 reserved_at_40[0x40];
e281682b
SM		 5793};
5794
5795struct mlx5_ifc_destroy_flow_table_in_bits {
5796 u8 opcode[0x10];
b4ff3a36 5797 u8 reserved_at_10[0x10];
e281682b 5798
b4ff3a36 5799 u8 reserved_at_20[0x10];
e281682b
SM		 5800 u8 op_mod[0x10];
5801
7d5e1423
SM		 5802 u8 other_vport[0x1];
5803 u8 reserved_at_41[0xf];
5804 u8 vport_number[0x10];
5805
5806 u8 reserved_at_60[0x20];
e281682b
SM		 5807
5808 u8 table_type[0x8];
b4ff3a36 5809 u8 reserved_at_88[0x18];
e281682b 5810
b4ff3a36 5811 u8 reserved_at_a0[0x8];
e281682b
SM		 5812 u8 table_id[0x18];
5813
b4ff3a36 5814 u8 reserved_at_c0[0x140];
e281682b
SM		 5815};
5816
5817struct mlx5_ifc_destroy_flow_group_out_bits {
5818 u8 status[0x8];
b4ff3a36 5819 u8 reserved_at_8[0x18];
e281682b
SM		 5820
5821 u8 syndrome[0x20];
5822
b4ff3a36 5823 u8 reserved_at_40[0x40];
e281682b
SM		 5824};
5825
5826struct mlx5_ifc_destroy_flow_group_in_bits {
5827 u8 opcode[0x10];
b4ff3a36 5828 u8 reserved_at_10[0x10];
e281682b 5829
b4ff3a36 5830 u8 reserved_at_20[0x10];
e281682b
SM		 5831 u8 op_mod[0x10];
5832
7d5e1423
SM		 5833 u8 other_vport[0x1];
5834 u8 reserved_at_41[0xf];
5835 u8 vport_number[0x10];
5836
5837 u8 reserved_at_60[0x20];
e281682b
SM		 5838
5839 u8 table_type[0x8];
b4ff3a36 5840 u8 reserved_at_88[0x18];
e281682b 5841
b4ff3a36 5842 u8 reserved_at_a0[0x8];
e281682b
SM		 5843 u8 table_id[0x18];
5844
5845 u8 group_id[0x20];
5846
b4ff3a36 5847 u8 reserved_at_e0[0x120];
e281682b
SM		 5848};
5849
5850struct mlx5_ifc_destroy_eq_out_bits {
5851 u8 status[0x8];
b4ff3a36 5852 u8 reserved_at_8[0x18];
e281682b
SM		 5853
5854 u8 syndrome[0x20];
5855
b4ff3a36 5856 u8 reserved_at_40[0x40];
e281682b
SM		 5857};
5858
5859struct mlx5_ifc_destroy_eq_in_bits {
5860 u8 opcode[0x10];
b4ff3a36 5861 u8 reserved_at_10[0x10];
e281682b 5862
b4ff3a36 5863 u8 reserved_at_20[0x10];
e281682b
SM		 5864 u8 op_mod[0x10];
5865
b4ff3a36 5866 u8 reserved_at_40[0x18];
e281682b
SM		 5867 u8 eq_number[0x8];
5868
b4ff3a36 5869 u8 reserved_at_60[0x20];
e281682b
SM		 5870};
5871
5872struct mlx5_ifc_destroy_dct_out_bits {
5873 u8 status[0x8];
b4ff3a36 5874 u8 reserved_at_8[0x18];
e281682b
SM		 5875
5876 u8 syndrome[0x20];
5877
b4ff3a36 5878 u8 reserved_at_40[0x40];
e281682b
SM		 5879};
5880
5881struct mlx5_ifc_destroy_dct_in_bits {
5882 u8 opcode[0x10];
b4ff3a36 5883 u8 reserved_at_10[0x10];
e281682b 5884
b4ff3a36 5885 u8 reserved_at_20[0x10];
e281682b
SM		 5886 u8 op_mod[0x10];
5887
b4ff3a36 5888 u8 reserved_at_40[0x8];
e281682b
SM		 5889 u8 dctn[0x18];
5890
b4ff3a36 5891 u8 reserved_at_60[0x20];
e281682b
SM		 5892};
5893
5894struct mlx5_ifc_destroy_cq_out_bits {
5895 u8 status[0x8];
b4ff3a36 5896 u8 reserved_at_8[0x18];
e281682b
SM		 5897
5898 u8 syndrome[0x20];
5899
b4ff3a36 5900 u8 reserved_at_40[0x40];
e281682b
SM		 5901};
5902
5903struct mlx5_ifc_destroy_cq_in_bits {
5904 u8 opcode[0x10];
b4ff3a36 5905 u8 reserved_at_10[0x10];
e281682b 5906
b4ff3a36 5907 u8 reserved_at_20[0x10];
e281682b
SM		 5908 u8 op_mod[0x10];
5909
b4ff3a36 5910 u8 reserved_at_40[0x8];
e281682b
SM		 5911 u8 cqn[0x18];
5912
b4ff3a36 5913 u8 reserved_at_60[0x20];
e281682b
SM		 5914};
5915
5916struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
5917 u8 status[0x8];
b4ff3a36 5918 u8 reserved_at_8[0x18];
e281682b
SM		 5919
5920 u8 syndrome[0x20];
5921
b4ff3a36 5922 u8 reserved_at_40[0x40];
e281682b
SM		 5923};
5924
5925struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
5926 u8 opcode[0x10];
b4ff3a36 5927 u8 reserved_at_10[0x10];
e281682b 5928
b4ff3a36 5929 u8 reserved_at_20[0x10];
e281682b
SM		 5930 u8 op_mod[0x10];
5931
b4ff3a36 5932 u8 reserved_at_40[0x20];
e281682b 5933
b4ff3a36 5934 u8 reserved_at_60[0x10];
e281682b
SM		 5935 u8 vxlan_udp_port[0x10];
5936};
5937
5938struct mlx5_ifc_delete_l2_table_entry_out_bits {
5939 u8 status[0x8];
b4ff3a36 5940 u8 reserved_at_8[0x18];
e281682b
SM		 5941
5942 u8 syndrome[0x20];
5943
b4ff3a36 5944 u8 reserved_at_40[0x40];
e281682b
SM		 5945};
5946
5947struct mlx5_ifc_delete_l2_table_entry_in_bits {
5948 u8 opcode[0x10];
b4ff3a36 5949 u8 reserved_at_10[0x10];
e281682b 5950
b4ff3a36 5951 u8 reserved_at_20[0x10];
e281682b
SM		 5952 u8 op_mod[0x10];
5953
b4ff3a36 5954 u8 reserved_at_40[0x60];
e281682b 5955
b4ff3a36 5956 u8 reserved_at_a0[0x8];
e281682b
SM		 5957 u8 table_index[0x18];
5958
b4ff3a36 5959 u8 reserved_at_c0[0x140];
e281682b
SM		 5960};
5961
5962struct mlx5_ifc_delete_fte_out_bits {
5963 u8 status[0x8];
b4ff3a36 5964 u8 reserved_at_8[0x18];
e281682b
SM		 5965
5966 u8 syndrome[0x20];
5967
b4ff3a36 5968 u8 reserved_at_40[0x40];
e281682b
SM		 5969};
5970
5971struct mlx5_ifc_delete_fte_in_bits {
5972 u8 opcode[0x10];
b4ff3a36 5973 u8 reserved_at_10[0x10];
e281682b 5974
b4ff3a36 5975 u8 reserved_at_20[0x10];
e281682b
SM		 5976 u8 op_mod[0x10];
5977
7d5e1423
SM		 5978 u8 other_vport[0x1];
5979 u8 reserved_at_41[0xf];
5980 u8 vport_number[0x10];
5981
5982 u8 reserved_at_60[0x20];
e281682b
SM		 5983
5984 u8 table_type[0x8];
b4ff3a36 5985 u8 reserved_at_88[0x18];
e281682b 5986
b4ff3a36 5987 u8 reserved_at_a0[0x8];
e281682b
SM		 5988 u8 table_id[0x18];
5989
b4ff3a36 5990 u8 reserved_at_c0[0x40];
e281682b
SM		 5991
5992 u8 flow_index[0x20];
5993
b4ff3a36 5994 u8 reserved_at_120[0xe0];
e281682b
SM		 5995};
5996
5997struct mlx5_ifc_dealloc_xrcd_out_bits {
5998 u8 status[0x8];
b4ff3a36 5999 u8 reserved_at_8[0x18];
e281682b
SM		 6000
6001 u8 syndrome[0x20];
6002
b4ff3a36 6003 u8 reserved_at_40[0x40];
e281682b
SM		 6004};
6005
6006struct mlx5_ifc_dealloc_xrcd_in_bits {
6007 u8 opcode[0x10];
b4ff3a36 6008 u8 reserved_at_10[0x10];
e281682b 6009
b4ff3a36 6010 u8 reserved_at_20[0x10];
e281682b
SM		 6011 u8 op_mod[0x10];
6012
b4ff3a36 6013 u8 reserved_at_40[0x8];
e281682b
SM		 6014 u8 xrcd[0x18];
6015
b4ff3a36 6016 u8 reserved_at_60[0x20];
e281682b
SM		 6017};
6018
6019struct mlx5_ifc_dealloc_uar_out_bits {
6020 u8 status[0x8];
b4ff3a36 6021 u8 reserved_at_8[0x18];
e281682b
SM		 6022
6023 u8 syndrome[0x20];
6024
b4ff3a36 6025 u8 reserved_at_40[0x40];
e281682b
SM		 6026};
6027
6028struct mlx5_ifc_dealloc_uar_in_bits {
6029 u8 opcode[0x10];
b4ff3a36 6030 u8 reserved_at_10[0x10];
e281682b 6031
b4ff3a36 6032 u8 reserved_at_20[0x10];
e281682b
SM		 6033 u8 op_mod[0x10];
6034
b4ff3a36 6035 u8 reserved_at_40[0x8];
e281682b
SM		 6036 u8 uar[0x18];
6037
b4ff3a36 6038 u8 reserved_at_60[0x20];
e281682b
SM		 6039};
6040
6041struct mlx5_ifc_dealloc_transport_domain_out_bits {
6042 u8 status[0x8];
b4ff3a36 6043 u8 reserved_at_8[0x18];
e281682b
SM		 6044
6045 u8 syndrome[0x20];
6046
b4ff3a36 6047 u8 reserved_at_40[0x40];
e281682b
SM		 6048};
6049
6050struct mlx5_ifc_dealloc_transport_domain_in_bits {
6051 u8 opcode[0x10];
b4ff3a36 6052 u8 reserved_at_10[0x10];
e281682b 6053
b4ff3a36 6054 u8 reserved_at_20[0x10];
e281682b
SM		 6055 u8 op_mod[0x10];
6056
b4ff3a36 6057 u8 reserved_at_40[0x8];
e281682b
SM		 6058 u8 transport_domain[0x18];
6059
b4ff3a36 6060 u8 reserved_at_60[0x20];
e281682b
SM		 6061};
6062
6063struct mlx5_ifc_dealloc_q_counter_out_bits {
6064 u8 status[0x8];
b4ff3a36 6065 u8 reserved_at_8[0x18];
e281682b
SM		 6066
6067 u8 syndrome[0x20];
6068
b4ff3a36 6069 u8 reserved_at_40[0x40];
e281682b
SM		 6070};
6071
6072struct mlx5_ifc_dealloc_q_counter_in_bits {
6073 u8 opcode[0x10];
b4ff3a36 6074 u8 reserved_at_10[0x10];
e281682b 6075
b4ff3a36 6076 u8 reserved_at_20[0x10];
e281682b
SM		 6077 u8 op_mod[0x10];
6078
b4ff3a36 6079 u8 reserved_at_40[0x18];
e281682b
SM		 6080 u8 counter_set_id[0x8];
6081
b4ff3a36 6082 u8 reserved_at_60[0x20];
e281682b
SM		 6083};
6084
6085struct mlx5_ifc_dealloc_pd_out_bits {
6086 u8 status[0x8];
b4ff3a36 6087 u8 reserved_at_8[0x18];
e281682b
SM		 6088
6089 u8 syndrome[0x20];
6090
b4ff3a36 6091 u8 reserved_at_40[0x40];
e281682b
SM		 6092};
6093
6094struct mlx5_ifc_dealloc_pd_in_bits {
6095 u8 opcode[0x10];
b4ff3a36 6096 u8 reserved_at_10[0x10];
e281682b 6097
b4ff3a36 6098 u8 reserved_at_20[0x10];
e281682b
SM		 6099 u8 op_mod[0x10];
6100
b4ff3a36 6101 u8 reserved_at_40[0x8];
e281682b
SM		 6102 u8 pd[0x18];
6103
b4ff3a36 6104 u8 reserved_at_60[0x20];
e281682b
SM		 6105};
6106
9dc0b289
AV		 6107struct mlx5_ifc_dealloc_flow_counter_out_bits {
6108 u8 status[0x8];
6109 u8 reserved_at_8[0x18];
6110
6111 u8 syndrome[0x20];
6112
6113 u8 reserved_at_40[0x40];
6114};
6115
6116struct mlx5_ifc_dealloc_flow_counter_in_bits {
6117 u8 opcode[0x10];
6118 u8 reserved_at_10[0x10];
6119
6120 u8 reserved_at_20[0x10];
6121 u8 op_mod[0x10];
6122
6123 u8 reserved_at_40[0x10];
6124 u8 flow_counter_id[0x10];
6125
6126 u8 reserved_at_60[0x20];
6127};
6128
7486216b
SM		 6129struct mlx5_ifc_create_xrq_out_bits {
6130 u8 status[0x8];
6131 u8 reserved_at_8[0x18];
6132
6133 u8 syndrome[0x20];
6134
6135 u8 reserved_at_40[0x8];
6136 u8 xrqn[0x18];
6137
6138 u8 reserved_at_60[0x20];
6139};
6140
6141struct mlx5_ifc_create_xrq_in_bits {
6142 u8 opcode[0x10];
6143 u8 reserved_at_10[0x10];
6144
6145 u8 reserved_at_20[0x10];
6146 u8 op_mod[0x10];
6147
6148 u8 reserved_at_40[0x40];
6149
6150 struct mlx5_ifc_xrqc_bits xrq_context;
6151};
6152
e281682b
SM		 6153struct mlx5_ifc_create_xrc_srq_out_bits {
6154 u8 status[0x8];
b4ff3a36 6155 u8 reserved_at_8[0x18];
e281682b
SM		 6156
6157 u8 syndrome[0x20];
6158
b4ff3a36 6159 u8 reserved_at_40[0x8];
e281682b
SM		 6160 u8 xrc_srqn[0x18];
6161
b4ff3a36 6162 u8 reserved_at_60[0x20];
e281682b
SM		 6163};
6164
6165struct mlx5_ifc_create_xrc_srq_in_bits {
6166 u8 opcode[0x10];
b4ff3a36 6167 u8 reserved_at_10[0x10];
e281682b 6168
b4ff3a36 6169 u8 reserved_at_20[0x10];
e281682b
SM		 6170 u8 op_mod[0x10];
6171
b4ff3a36 6172 u8 reserved_at_40[0x40];
e281682b
SM		 6173
6174 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6175
b4ff3a36 6176 u8 reserved_at_280[0x600];
e281682b
SM		 6177
6178 u8 pas[0][0x40];
6179};
6180
6181struct mlx5_ifc_create_tis_out_bits {
6182 u8 status[0x8];
b4ff3a36 6183 u8 reserved_at_8[0x18];
e281682b
SM		 6184
6185 u8 syndrome[0x20];
6186
b4ff3a36 6187 u8 reserved_at_40[0x8];
e281682b
SM		 6188 u8 tisn[0x18];
6189
b4ff3a36 6190 u8 reserved_at_60[0x20];
e281682b
SM		 6191};
6192
6193struct mlx5_ifc_create_tis_in_bits {
6194 u8 opcode[0x10];
b4ff3a36 6195 u8 reserved_at_10[0x10];
e281682b 6196
b4ff3a36 6197 u8 reserved_at_20[0x10];
e281682b
SM		 6198 u8 op_mod[0x10];
6199
b4ff3a36 6200 u8 reserved_at_40[0xc0];
e281682b
SM		 6201
6202 struct mlx5_ifc_tisc_bits ctx;
6203};
6204
6205struct mlx5_ifc_create_tir_out_bits {
6206 u8 status[0x8];
b4ff3a36 6207 u8 reserved_at_8[0x18];
e281682b
SM		 6208
6209 u8 syndrome[0x20];
6210
b4ff3a36 6211 u8 reserved_at_40[0x8];
e281682b
SM		 6212 u8 tirn[0x18];
6213
b4ff3a36 6214 u8 reserved_at_60[0x20];
e281682b
SM		 6215};
6216
6217struct mlx5_ifc_create_tir_in_bits {
6218 u8 opcode[0x10];
b4ff3a36 6219 u8 reserved_at_10[0x10];
e281682b 6220
b4ff3a36 6221 u8 reserved_at_20[0x10];
e281682b
SM		 6222 u8 op_mod[0x10];
6223
b4ff3a36 6224 u8 reserved_at_40[0xc0];
e281682b
SM		 6225
6226 struct mlx5_ifc_tirc_bits ctx;
6227};
6228
6229struct mlx5_ifc_create_srq_out_bits {
6230 u8 status[0x8];
b4ff3a36 6231 u8 reserved_at_8[0x18];
e281682b
SM		 6232
6233 u8 syndrome[0x20];
6234
b4ff3a36 6235 u8 reserved_at_40[0x8];
e281682b
SM		 6236 u8 srqn[0x18];
6237
b4ff3a36 6238 u8 reserved_at_60[0x20];
e281682b
SM		 6239};
6240
6241struct mlx5_ifc_create_srq_in_bits {
6242 u8 opcode[0x10];
b4ff3a36 6243 u8 reserved_at_10[0x10];
e281682b 6244
b4ff3a36 6245 u8 reserved_at_20[0x10];
e281682b
SM		 6246 u8 op_mod[0x10];
6247
b4ff3a36 6248 u8 reserved_at_40[0x40];
e281682b
SM		 6249
6250 struct mlx5_ifc_srqc_bits srq_context_entry;
6251
b4ff3a36 6252 u8 reserved_at_280[0x600];
e281682b
SM		 6253
6254 u8 pas[0][0x40];
6255};
6256
6257struct mlx5_ifc_create_sq_out_bits {
6258 u8 status[0x8];
b4ff3a36 6259 u8 reserved_at_8[0x18];
e281682b
SM		 6260
6261 u8 syndrome[0x20];
6262
b4ff3a36 6263 u8 reserved_at_40[0x8];
e281682b
SM		 6264 u8 sqn[0x18];
6265
b4ff3a36 6266 u8 reserved_at_60[0x20];
e281682b
SM		 6267};
6268
6269struct mlx5_ifc_create_sq_in_bits {
6270 u8 opcode[0x10];
b4ff3a36 6271 u8 reserved_at_10[0x10];
e281682b 6272
b4ff3a36 6273 u8 reserved_at_20[0x10];
e281682b
SM		 6274 u8 op_mod[0x10];
6275
b4ff3a36 6276 u8 reserved_at_40[0xc0];
e281682b
SM		 6277
6278 struct mlx5_ifc_sqc_bits ctx;
6279};
6280
813f8540
MHY		 6281struct mlx5_ifc_create_scheduling_element_out_bits {
6282 u8 status[0x8];
6283 u8 reserved_at_8[0x18];
6284
6285 u8 syndrome[0x20];
6286
6287 u8 reserved_at_40[0x40];
6288
6289 u8 scheduling_element_id[0x20];
6290
6291 u8 reserved_at_a0[0x160];
6292};
6293
6294struct mlx5_ifc_create_scheduling_element_in_bits {
6295 u8 opcode[0x10];
6296 u8 reserved_at_10[0x10];
6297
6298 u8 reserved_at_20[0x10];
6299 u8 op_mod[0x10];
6300
6301 u8 scheduling_hierarchy[0x8];
6302 u8 reserved_at_48[0x18];
6303
6304 u8 reserved_at_60[0xa0];
6305
6306 struct mlx5_ifc_scheduling_context_bits scheduling_context;
6307
6308 u8 reserved_at_300[0x100];
6309};
6310
e281682b
SM		 6311struct mlx5_ifc_create_rqt_out_bits {
6312 u8 status[0x8];
b4ff3a36 6313 u8 reserved_at_8[0x18];
e281682b
SM		 6314
6315 u8 syndrome[0x20];
6316
b4ff3a36 6317 u8 reserved_at_40[0x8];
e281682b
SM		 6318 u8 rqtn[0x18];
6319
b4ff3a36 6320 u8 reserved_at_60[0x20];
e281682b
SM		 6321};
6322
6323struct mlx5_ifc_create_rqt_in_bits {
6324 u8 opcode[0x10];
b4ff3a36 6325 u8 reserved_at_10[0x10];
e281682b 6326
b4ff3a36 6327 u8 reserved_at_20[0x10];
e281682b
SM		 6328 u8 op_mod[0x10];
6329
b4ff3a36 6330 u8 reserved_at_40[0xc0];
e281682b
SM		 6331
6332 struct mlx5_ifc_rqtc_bits rqt_context;
6333};
6334
6335struct mlx5_ifc_create_rq_out_bits {
6336 u8 status[0x8];
b4ff3a36 6337 u8 reserved_at_8[0x18];
e281682b
SM		 6338
6339 u8 syndrome[0x20];
6340
b4ff3a36 6341 u8 reserved_at_40[0x8];
e281682b
SM		 6342 u8 rqn[0x18];
6343
b4ff3a36 6344 u8 reserved_at_60[0x20];
e281682b
SM		 6345};
6346
6347struct mlx5_ifc_create_rq_in_bits {
6348 u8 opcode[0x10];
b4ff3a36 6349 u8 reserved_at_10[0x10];
e281682b 6350
b4ff3a36 6351 u8 reserved_at_20[0x10];
e281682b
SM		 6352 u8 op_mod[0x10];
6353
b4ff3a36 6354 u8 reserved_at_40[0xc0];
e281682b
SM		 6355
6356 struct mlx5_ifc_rqc_bits ctx;
6357};
6358
6359struct mlx5_ifc_create_rmp_out_bits {
6360 u8 status[0x8];
b4ff3a36 6361 u8 reserved_at_8[0x18];
e281682b
SM		 6362
6363 u8 syndrome[0x20];
6364
b4ff3a36 6365 u8 reserved_at_40[0x8];
e281682b
SM		 6366 u8 rmpn[0x18];
6367
b4ff3a36 6368 u8 reserved_at_60[0x20];
e281682b
SM		 6369};
6370
6371struct mlx5_ifc_create_rmp_in_bits {
6372 u8 opcode[0x10];
b4ff3a36 6373 u8 reserved_at_10[0x10];
e281682b 6374
b4ff3a36 6375 u8 reserved_at_20[0x10];
e281682b
SM		 6376 u8 op_mod[0x10];
6377
b4ff3a36 6378 u8 reserved_at_40[0xc0];
e281682b
SM		 6379
6380 struct mlx5_ifc_rmpc_bits ctx;
6381};
6382
6383struct mlx5_ifc_create_qp_out_bits {
6384 u8 status[0x8];
b4ff3a36 6385 u8 reserved_at_8[0x18];
e281682b
SM		 6386
6387 u8 syndrome[0x20];
6388
b4ff3a36 6389 u8 reserved_at_40[0x8];
e281682b
SM		 6390 u8 qpn[0x18];
6391
b4ff3a36 6392 u8 reserved_at_60[0x20];
e281682b
SM		 6393};
6394
6395struct mlx5_ifc_create_qp_in_bits {
6396 u8 opcode[0x10];
b4ff3a36 6397 u8 reserved_at_10[0x10];
e281682b 6398
b4ff3a36 6399 u8 reserved_at_20[0x10];
e281682b
SM		 6400 u8 op_mod[0x10];
6401
b4ff3a36 6402 u8 reserved_at_40[0x40];
e281682b
SM		 6403
6404 u8 opt_param_mask[0x20];
6405
b4ff3a36 6406 u8 reserved_at_a0[0x20];
e281682b
SM		 6407
6408 struct mlx5_ifc_qpc_bits qpc;
6409
b4ff3a36 6410 u8 reserved_at_800[0x80];
e281682b
SM		 6411
6412 u8 pas[0][0x40];
6413};
6414
6415struct mlx5_ifc_create_psv_out_bits {
6416 u8 status[0x8];
b4ff3a36 6417 u8 reserved_at_8[0x18];
e281682b
SM		 6418
6419 u8 syndrome[0x20];
6420
b4ff3a36 6421 u8 reserved_at_40[0x40];
e281682b 6422
b4ff3a36 6423 u8 reserved_at_80[0x8];
e281682b
SM		 6424 u8 psv0_index[0x18];
6425
b4ff3a36 6426 u8 reserved_at_a0[0x8];
e281682b
SM		 6427 u8 psv1_index[0x18];
6428
b4ff3a36 6429 u8 reserved_at_c0[0x8];
e281682b
SM		 6430 u8 psv2_index[0x18];
6431
b4ff3a36 6432 u8 reserved_at_e0[0x8];
e281682b
SM		 6433 u8 psv3_index[0x18];
6434};
6435
6436struct mlx5_ifc_create_psv_in_bits {
6437 u8 opcode[0x10];
b4ff3a36 6438 u8 reserved_at_10[0x10];
e281682b 6439
b4ff3a36 6440 u8 reserved_at_20[0x10];
e281682b
SM		 6441 u8 op_mod[0x10];
6442
6443 u8 num_psv[0x4];
b4ff3a36 6444 u8 reserved_at_44[0x4];
e281682b
SM		 6445 u8 pd[0x18];
6446
b4ff3a36 6447 u8 reserved_at_60[0x20];
e281682b
SM		 6448};
6449
6450struct mlx5_ifc_create_mkey_out_bits {
6451 u8 status[0x8];
b4ff3a36 6452 u8 reserved_at_8[0x18];
e281682b
SM		 6453
6454 u8 syndrome[0x20];
6455
b4ff3a36 6456 u8 reserved_at_40[0x8];
e281682b
SM		 6457 u8 mkey_index[0x18];
6458
b4ff3a36 6459 u8 reserved_at_60[0x20];
e281682b
SM		 6460};
6461
6462struct mlx5_ifc_create_mkey_in_bits {
6463 u8 opcode[0x10];
b4ff3a36 6464 u8 reserved_at_10[0x10];
e281682b 6465
b4ff3a36 6466 u8 reserved_at_20[0x10];
e281682b
SM		 6467 u8 op_mod[0x10];
6468
b4ff3a36 6469 u8 reserved_at_40[0x20];
e281682b
SM		 6470
6471 u8 pg_access[0x1];
b4ff3a36 6472 u8 reserved_at_61[0x1f];
e281682b
SM		 6473
6474 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6475
b4ff3a36 6476 u8 reserved_at_280[0x80];
e281682b
SM		 6477
6478 u8 translations_octword_actual_size[0x20];
6479
b4ff3a36 6480 u8 reserved_at_320[0x560];
e281682b
SM		 6481
6482 u8 klm_pas_mtt[0][0x20];
6483};
6484
6485struct mlx5_ifc_create_flow_table_out_bits {
6486 u8 status[0x8];
b4ff3a36 6487 u8 reserved_at_8[0x18];
e281682b
SM		 6488
6489 u8 syndrome[0x20];
6490
b4ff3a36 6491 u8 reserved_at_40[0x8];
e281682b
SM		 6492 u8 table_id[0x18];
6493
b4ff3a36 6494 u8 reserved_at_60[0x20];
e281682b
SM		 6495};
6496
6497struct mlx5_ifc_create_flow_table_in_bits {
6498 u8 opcode[0x10];
b4ff3a36 6499 u8 reserved_at_10[0x10];
e281682b 6500
b4ff3a36 6501 u8 reserved_at_20[0x10];
e281682b
SM		 6502 u8 op_mod[0x10];
6503
7d5e1423
SM		 6504 u8 other_vport[0x1];
6505 u8 reserved_at_41[0xf];
6506 u8 vport_number[0x10];
6507
6508 u8 reserved_at_60[0x20];
e281682b
SM		 6509
6510 u8 table_type[0x8];
b4ff3a36 6511 u8 reserved_at_88[0x18];
e281682b 6512
b4ff3a36 6513 u8 reserved_at_a0[0x20];
e281682b 6514
7adbde20
HHZ		 6515 u8 encap_en[0x1];
6516 u8 decap_en[0x1];
6517 u8 reserved_at_c2[0x2];
34a40e68 6518 u8 table_miss_mode[0x4];
e281682b 6519 u8 level[0x8];
b4ff3a36 6520 u8 reserved_at_d0[0x8];
e281682b
SM		 6521 u8 log_size[0x8];
6522
b4ff3a36 6523 u8 reserved_at_e0[0x8];
34a40e68
MG		 6524 u8 table_miss_id[0x18];
6525
84df61eb
AH		 6526 u8 reserved_at_100[0x8];
6527 u8 lag_master_next_table_id[0x18];
6528
6529 u8 reserved_at_120[0x80];
e281682b
SM		 6530};
6531
6532struct mlx5_ifc_create_flow_group_out_bits {
6533 u8 status[0x8];
b4ff3a36 6534 u8 reserved_at_8[0x18];
e281682b
SM		 6535
6536 u8 syndrome[0x20];
6537
b4ff3a36 6538 u8 reserved_at_40[0x8];
e281682b
SM		 6539 u8 group_id[0x18];
6540
b4ff3a36 6541 u8 reserved_at_60[0x20];
e281682b
SM		 6542};
6543
6544enum {
6545 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
6546 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
6547 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
6548};
6549
6550struct mlx5_ifc_create_flow_group_in_bits {
6551 u8 opcode[0x10];
b4ff3a36 6552 u8 reserved_at_10[0x10];
e281682b 6553
b4ff3a36 6554 u8 reserved_at_20[0x10];
e281682b
SM		 6555 u8 op_mod[0x10];
6556
7d5e1423
SM		 6557 u8 other_vport[0x1];
6558 u8 reserved_at_41[0xf];
6559 u8 vport_number[0x10];
6560
6561 u8 reserved_at_60[0x20];
e281682b
SM		 6562
6563 u8 table_type[0x8];
b4ff3a36 6564 u8 reserved_at_88[0x18];
e281682b 6565
b4ff3a36 6566 u8 reserved_at_a0[0x8];
e281682b
SM		 6567 u8 table_id[0x18];
6568
b4ff3a36 6569 u8 reserved_at_c0[0x20];
e281682b
SM		 6570
6571 u8 start_flow_index[0x20];
6572
b4ff3a36 6573 u8 reserved_at_100[0x20];
e281682b
SM		 6574
6575 u8 end_flow_index[0x20];
6576
b4ff3a36 6577 u8 reserved_at_140[0xa0];
e281682b 6578
b4ff3a36 6579 u8 reserved_at_1e0[0x18];
e281682b
SM		 6580 u8 match_criteria_enable[0x8];
6581
6582 struct mlx5_ifc_fte_match_param_bits match_criteria;
6583
b4ff3a36 6584 u8 reserved_at_1200[0xe00];
e281682b
SM		 6585};
6586
6587struct mlx5_ifc_create_eq_out_bits {
6588 u8 status[0x8];
b4ff3a36 6589 u8 reserved_at_8[0x18];
e281682b
SM		 6590
6591 u8 syndrome[0x20];
6592
b4ff3a36 6593 u8 reserved_at_40[0x18];
e281682b
SM		 6594 u8 eq_number[0x8];
6595
b4ff3a36 6596 u8 reserved_at_60[0x20];
e281682b
SM		 6597};
6598
6599struct mlx5_ifc_create_eq_in_bits {
6600 u8 opcode[0x10];
b4ff3a36 6601 u8 reserved_at_10[0x10];
e281682b 6602
b4ff3a36 6603 u8 reserved_at_20[0x10];
e281682b
SM		 6604 u8 op_mod[0x10];
6605
b4ff3a36 6606 u8 reserved_at_40[0x40];
e281682b
SM		 6607
6608 struct mlx5_ifc_eqc_bits eq_context_entry;
6609
b4ff3a36 6610 u8 reserved_at_280[0x40];
e281682b
SM		 6611
6612 u8 event_bitmask[0x40];
6613
b4ff3a36 6614 u8 reserved_at_300[0x580];
e281682b
SM		 6615
6616 u8 pas[0][0x40];
6617};
6618
6619struct mlx5_ifc_create_dct_out_bits {
6620 u8 status[0x8];
b4ff3a36 6621 u8 reserved_at_8[0x18];
e281682b
SM		 6622
6623 u8 syndrome[0x20];
6624
b4ff3a36 6625 u8 reserved_at_40[0x8];
e281682b
SM		 6626 u8 dctn[0x18];
6627
b4ff3a36 6628 u8 reserved_at_60[0x20];
e281682b
SM		 6629};
6630
6631struct mlx5_ifc_create_dct_in_bits {
6632 u8 opcode[0x10];
b4ff3a36 6633 u8 reserved_at_10[0x10];
e281682b 6634
b4ff3a36 6635 u8 reserved_at_20[0x10];
e281682b
SM		 6636 u8 op_mod[0x10];
6637
b4ff3a36 6638 u8 reserved_at_40[0x40];
e281682b
SM		 6639
6640 struct mlx5_ifc_dctc_bits dct_context_entry;
6641
b4ff3a36 6642 u8 reserved_at_280[0x180];
e281682b
SM		 6643};
6644
6645struct mlx5_ifc_create_cq_out_bits {
6646 u8 status[0x8];
b4ff3a36 6647 u8 reserved_at_8[0x18];
e281682b
SM		 6648
6649 u8 syndrome[0x20];
6650
b4ff3a36 6651 u8 reserved_at_40[0x8];
e281682b
SM		 6652 u8 cqn[0x18];
6653
b4ff3a36 6654 u8 reserved_at_60[0x20];
e281682b
SM		 6655};
6656
6657struct mlx5_ifc_create_cq_in_bits {
6658 u8 opcode[0x10];
b4ff3a36 6659 u8 reserved_at_10[0x10];
e281682b 6660
b4ff3a36 6661 u8 reserved_at_20[0x10];
e281682b
SM		 6662 u8 op_mod[0x10];
6663
b4ff3a36 6664 u8 reserved_at_40[0x40];
e281682b
SM		 6665
6666 struct mlx5_ifc_cqc_bits cq_context;
6667
b4ff3a36 6668 u8 reserved_at_280[0x600];
e281682b
SM		 6669
6670 u8 pas[0][0x40];
6671};
6672
6673struct mlx5_ifc_config_int_moderation_out_bits {
6674 u8 status[0x8];
b4ff3a36 6675 u8 reserved_at_8[0x18];
e281682b
SM		 6676
6677 u8 syndrome[0x20];
6678
b4ff3a36 6679 u8 reserved_at_40[0x4];
e281682b
SM		 6680 u8 min_delay[0xc];
6681 u8 int_vector[0x10];
6682
b4ff3a36 6683 u8 reserved_at_60[0x20];
e281682b
SM		 6684};
6685
6686enum {
6687 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
6688 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
6689};
6690
6691struct mlx5_ifc_config_int_moderation_in_bits {
6692 u8 opcode[0x10];
b4ff3a36 6693 u8 reserved_at_10[0x10];
e281682b 6694
b4ff3a36 6695 u8 reserved_at_20[0x10];
e281682b
SM		 6696 u8 op_mod[0x10];
6697
b4ff3a36 6698 u8 reserved_at_40[0x4];
e281682b
SM		 6699 u8 min_delay[0xc];
6700 u8 int_vector[0x10];
6701
b4ff3a36 6702 u8 reserved_at_60[0x20];
e281682b
SM		 6703};
6704
6705struct mlx5_ifc_attach_to_mcg_out_bits {
6706 u8 status[0x8];
b4ff3a36 6707 u8 reserved_at_8[0x18];
e281682b
SM		 6708
6709 u8 syndrome[0x20];
6710
b4ff3a36 6711 u8 reserved_at_40[0x40];
e281682b
SM		 6712};
6713
6714struct mlx5_ifc_attach_to_mcg_in_bits {
6715 u8 opcode[0x10];
b4ff3a36 6716 u8 reserved_at_10[0x10];
e281682b 6717
b4ff3a36 6718 u8 reserved_at_20[0x10];
e281682b
SM		 6719 u8 op_mod[0x10];
6720
b4ff3a36 6721 u8 reserved_at_40[0x8];
e281682b
SM		 6722 u8 qpn[0x18];
6723
b4ff3a36 6724 u8 reserved_at_60[0x20];
e281682b
SM		 6725
6726 u8 multicast_gid[16][0x8];
6727};
6728
7486216b
SM		 6729struct mlx5_ifc_arm_xrq_out_bits {
6730 u8 status[0x8];
6731 u8 reserved_at_8[0x18];
6732
6733 u8 syndrome[0x20];
6734
6735 u8 reserved_at_40[0x40];
6736};
6737
6738struct mlx5_ifc_arm_xrq_in_bits {
6739 u8 opcode[0x10];
6740 u8 reserved_at_10[0x10];
6741
6742 u8 reserved_at_20[0x10];
6743 u8 op_mod[0x10];
6744
6745 u8 reserved_at_40[0x8];
6746 u8 xrqn[0x18];
6747
6748 u8 reserved_at_60[0x10];
6749 u8 lwm[0x10];
6750};
6751
e281682b
SM		 6752struct mlx5_ifc_arm_xrc_srq_out_bits {
6753 u8 status[0x8];
b4ff3a36 6754 u8 reserved_at_8[0x18];
e281682b
SM		 6755
6756 u8 syndrome[0x20];
6757
b4ff3a36 6758 u8 reserved_at_40[0x40];
e281682b
SM		 6759};
6760
6761enum {
6762 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
6763};
6764
6765struct mlx5_ifc_arm_xrc_srq_in_bits {
6766 u8 opcode[0x10];
b4ff3a36 6767 u8 reserved_at_10[0x10];
e281682b 6768
b4ff3a36 6769 u8 reserved_at_20[0x10];
e281682b
SM		 6770 u8 op_mod[0x10];
6771
b4ff3a36 6772 u8 reserved_at_40[0x8];
e281682b
SM		 6773 u8 xrc_srqn[0x18];
6774
b4ff3a36 6775 u8 reserved_at_60[0x10];
e281682b
SM		 6776 u8 lwm[0x10];
6777};
6778
6779struct mlx5_ifc_arm_rq_out_bits {
6780 u8 status[0x8];
b4ff3a36 6781 u8 reserved_at_8[0x18];
e281682b
SM		 6782
6783 u8 syndrome[0x20];
6784
b4ff3a36 6785 u8 reserved_at_40[0x40];
e281682b
SM		 6786};
6787
6788enum {
7486216b
SM		 6789 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
6790 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
e281682b
SM		 6791};
6792
6793struct mlx5_ifc_arm_rq_in_bits {
6794 u8 opcode[0x10];
b4ff3a36 6795 u8 reserved_at_10[0x10];
e281682b 6796
b4ff3a36 6797 u8 reserved_at_20[0x10];
e281682b
SM		 6798 u8 op_mod[0x10];
6799
b4ff3a36 6800 u8 reserved_at_40[0x8];
e281682b
SM		 6801 u8 srq_number[0x18];
6802
b4ff3a36 6803 u8 reserved_at_60[0x10];
e281682b
SM		 6804 u8 lwm[0x10];
6805};
6806
6807struct mlx5_ifc_arm_dct_out_bits {
6808 u8 status[0x8];
b4ff3a36 6809 u8 reserved_at_8[0x18];
e281682b
SM		 6810
6811 u8 syndrome[0x20];
6812
b4ff3a36 6813 u8 reserved_at_40[0x40];
e281682b
SM		 6814};
6815
6816struct mlx5_ifc_arm_dct_in_bits {
6817 u8 opcode[0x10];
b4ff3a36 6818 u8 reserved_at_10[0x10];
e281682b 6819
b4ff3a36 6820 u8 reserved_at_20[0x10];
e281682b
SM		 6821 u8 op_mod[0x10];
6822
b4ff3a36 6823 u8 reserved_at_40[0x8];
e281682b
SM		 6824 u8 dct_number[0x18];
6825
b4ff3a36 6826 u8 reserved_at_60[0x20];
e281682b
SM		 6827};
6828
6829struct mlx5_ifc_alloc_xrcd_out_bits {
6830 u8 status[0x8];
b4ff3a36 6831 u8 reserved_at_8[0x18];
e281682b
SM		 6832
6833 u8 syndrome[0x20];
6834
b4ff3a36 6835 u8 reserved_at_40[0x8];
e281682b
SM		 6836 u8 xrcd[0x18];
6837
b4ff3a36 6838 u8 reserved_at_60[0x20];
e281682b
SM		 6839};
6840
6841struct mlx5_ifc_alloc_xrcd_in_bits {
6842 u8 opcode[0x10];
b4ff3a36 6843 u8 reserved_at_10[0x10];
e281682b 6844
b4ff3a36 6845 u8 reserved_at_20[0x10];
e281682b
SM		 6846 u8 op_mod[0x10];
6847
b4ff3a36 6848 u8 reserved_at_40[0x40];
e281682b
SM		 6849};
6850
6851struct mlx5_ifc_alloc_uar_out_bits {
6852 u8 status[0x8];
b4ff3a36 6853 u8 reserved_at_8[0x18];
e281682b
SM		 6854
6855 u8 syndrome[0x20];
6856
b4ff3a36 6857 u8 reserved_at_40[0x8];
e281682b
SM		 6858 u8 uar[0x18];
6859
b4ff3a36 6860 u8 reserved_at_60[0x20];
e281682b
SM		 6861};
6862
6863struct mlx5_ifc_alloc_uar_in_bits {
6864 u8 opcode[0x10];
b4ff3a36 6865 u8 reserved_at_10[0x10];
e281682b 6866
b4ff3a36 6867 u8 reserved_at_20[0x10];
e281682b
SM		 6868 u8 op_mod[0x10];
6869
b4ff3a36 6870 u8 reserved_at_40[0x40];
e281682b
SM		 6871};
6872
6873struct mlx5_ifc_alloc_transport_domain_out_bits {
6874 u8 status[0x8];
b4ff3a36 6875 u8 reserved_at_8[0x18];
e281682b
SM		 6876
6877 u8 syndrome[0x20];
6878
b4ff3a36 6879 u8 reserved_at_40[0x8];
e281682b
SM		 6880 u8 transport_domain[0x18];
6881
b4ff3a36 6882 u8 reserved_at_60[0x20];
e281682b
SM		 6883};
6884
6885struct mlx5_ifc_alloc_transport_domain_in_bits {
6886 u8 opcode[0x10];
b4ff3a36 6887 u8 reserved_at_10[0x10];
e281682b 6888
b4ff3a36 6889 u8 reserved_at_20[0x10];
e281682b
SM		 6890 u8 op_mod[0x10];
6891
b4ff3a36 6892 u8 reserved_at_40[0x40];
e281682b
SM		 6893};
6894
6895struct mlx5_ifc_alloc_q_counter_out_bits {
6896 u8 status[0x8];
b4ff3a36 6897 u8 reserved_at_8[0x18];
e281682b
SM		 6898
6899 u8 syndrome[0x20];
6900
b4ff3a36 6901 u8 reserved_at_40[0x18];
e281682b
SM		 6902 u8 counter_set_id[0x8];
6903
b4ff3a36 6904 u8 reserved_at_60[0x20];
e281682b
SM		 6905};
6906
6907struct mlx5_ifc_alloc_q_counter_in_bits {
6908 u8 opcode[0x10];
b4ff3a36 6909 u8 reserved_at_10[0x10];
e281682b 6910
b4ff3a36 6911 u8 reserved_at_20[0x10];
e281682b
SM		 6912 u8 op_mod[0x10];
6913
b4ff3a36 6914 u8 reserved_at_40[0x40];
e281682b
SM		 6915};
6916
6917struct mlx5_ifc_alloc_pd_out_bits {
6918 u8 status[0x8];
b4ff3a36 6919 u8 reserved_at_8[0x18];
e281682b
SM		 6920
6921 u8 syndrome[0x20];
6922
b4ff3a36 6923 u8 reserved_at_40[0x8];
e281682b
SM		 6924 u8 pd[0x18];
6925
b4ff3a36 6926 u8 reserved_at_60[0x20];
e281682b
SM		 6927};
6928
6929struct mlx5_ifc_alloc_pd_in_bits {
9dc0b289
AV		 6930 u8 opcode[0x10];
6931 u8 reserved_at_10[0x10];
6932
6933 u8 reserved_at_20[0x10];
6934 u8 op_mod[0x10];
6935
6936 u8 reserved_at_40[0x40];
6937};
6938
6939struct mlx5_ifc_alloc_flow_counter_out_bits {
6940 u8 status[0x8];
6941 u8 reserved_at_8[0x18];
6942
6943 u8 syndrome[0x20];
6944
6945 u8 reserved_at_40[0x10];
6946 u8 flow_counter_id[0x10];
6947
6948 u8 reserved_at_60[0x20];
6949};
6950
6951struct mlx5_ifc_alloc_flow_counter_in_bits {
e281682b 6952 u8 opcode[0x10];
b4ff3a36 6953 u8 reserved_at_10[0x10];
e281682b 6954
b4ff3a36 6955 u8 reserved_at_20[0x10];
e281682b
SM		 6956 u8 op_mod[0x10];
6957
b4ff3a36 6958 u8 reserved_at_40[0x40];
e281682b
SM		 6959};
6960
6961struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
6962 u8 status[0x8];
b4ff3a36 6963 u8 reserved_at_8[0x18];
e281682b
SM		 6964
6965 u8 syndrome[0x20];
6966
b4ff3a36 6967 u8 reserved_at_40[0x40];
e281682b
SM		 6968};
6969
6970struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
6971 u8 opcode[0x10];
b4ff3a36 6972 u8 reserved_at_10[0x10];
e281682b 6973
b4ff3a36 6974 u8 reserved_at_20[0x10];
e281682b
SM		 6975 u8 op_mod[0x10];
6976
b4ff3a36 6977 u8 reserved_at_40[0x20];
e281682b 6978
b4ff3a36 6979 u8 reserved_at_60[0x10];
e281682b
SM		 6980 u8 vxlan_udp_port[0x10];
6981};
6982
7486216b
SM		 6983struct mlx5_ifc_set_rate_limit_out_bits {
6984 u8 status[0x8];
6985 u8 reserved_at_8[0x18];
6986
6987 u8 syndrome[0x20];
6988
6989 u8 reserved_at_40[0x40];
6990};
6991
6992struct mlx5_ifc_set_rate_limit_in_bits {
6993 u8 opcode[0x10];
6994 u8 reserved_at_10[0x10];
6995
6996 u8 reserved_at_20[0x10];
6997 u8 op_mod[0x10];
6998
6999 u8 reserved_at_40[0x10];
7000 u8 rate_limit_index[0x10];
7001
7002 u8 reserved_at_60[0x20];
7003
7004 u8 rate_limit[0x20];
7005};
7006
e281682b
SM		 7007struct mlx5_ifc_access_register_out_bits {
7008 u8 status[0x8];
b4ff3a36 7009 u8 reserved_at_8[0x18];
e281682b
SM		 7010
7011 u8 syndrome[0x20];
7012
b4ff3a36 7013 u8 reserved_at_40[0x40];
e281682b
SM		 7014
7015 u8 register_data[0][0x20];
7016};
7017
7018enum {
7019 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
7020 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
7021};
7022
7023struct mlx5_ifc_access_register_in_bits {
7024 u8 opcode[0x10];
b4ff3a36 7025 u8 reserved_at_10[0x10];
e281682b 7026
b4ff3a36 7027 u8 reserved_at_20[0x10];
e281682b
SM		 7028 u8 op_mod[0x10];
7029
b4ff3a36 7030 u8 reserved_at_40[0x10];
e281682b
SM		 7031 u8 register_id[0x10];
7032
7033 u8 argument[0x20];
7034
7035 u8 register_data[0][0x20];
7036};
7037
7038struct mlx5_ifc_sltp_reg_bits {
7039 u8 status[0x4];
7040 u8 version[0x4];
7041 u8 local_port[0x8];
7042 u8 pnat[0x2];
b4ff3a36 7043 u8 reserved_at_12[0x2];
e281682b 7044 u8 lane[0x4];
b4ff3a36 7045 u8 reserved_at_18[0x8];
e281682b 7046
b4ff3a36 7047 u8 reserved_at_20[0x20];
e281682b 7048
b4ff3a36 7049 u8 reserved_at_40[0x7];
e281682b
SM		 7050 u8 polarity[0x1];
7051 u8 ob_tap0[0x8];
7052 u8 ob_tap1[0x8];
7053 u8 ob_tap2[0x8];
7054
b4ff3a36 7055 u8 reserved_at_60[0xc];
e281682b
SM		 7056 u8 ob_preemp_mode[0x4];
7057 u8 ob_reg[0x8];
7058 u8 ob_bias[0x8];
7059
b4ff3a36 7060 u8 reserved_at_80[0x20];
e281682b
SM		 7061};
7062
7063struct mlx5_ifc_slrg_reg_bits {
7064 u8 status[0x4];
7065 u8 version[0x4];
7066 u8 local_port[0x8];
7067 u8 pnat[0x2];
b4ff3a36 7068 u8 reserved_at_12[0x2];
e281682b 7069 u8 lane[0x4];
b4ff3a36 7070 u8 reserved_at_18[0x8];
e281682b
SM		 7071
7072 u8 time_to_link_up[0x10];
b4ff3a36 7073 u8 reserved_at_30[0xc];
e281682b
SM		 7074 u8 grade_lane_speed[0x4];
7075
7076 u8 grade_version[0x8];
7077 u8 grade[0x18];
7078
b4ff3a36 7079 u8 reserved_at_60[0x4];
e281682b
SM		 7080 u8 height_grade_type[0x4];
7081 u8 height_grade[0x18];
7082
7083 u8 height_dz[0x10];
7084 u8 height_dv[0x10];
7085
b4ff3a36 7086 u8 reserved_at_a0[0x10];
e281682b
SM		 7087 u8 height_sigma[0x10];
7088
b4ff3a36 7089 u8 reserved_at_c0[0x20];
e281682b 7090
b4ff3a36 7091 u8 reserved_at_e0[0x4];
e281682b
SM		 7092 u8 phase_grade_type[0x4];
7093 u8 phase_grade[0x18];
7094
b4ff3a36 7095 u8 reserved_at_100[0x8];
e281682b 7096 u8 phase_eo_pos[0x8];
b4ff3a36 7097 u8 reserved_at_110[0x8];
e281682b
SM		 7098 u8 phase_eo_neg[0x8];
7099
7100 u8 ffe_set_tested[0x10];
7101 u8 test_errors_per_lane[0x10];
7102};
7103
7104struct mlx5_ifc_pvlc_reg_bits {
b4ff3a36 7105 u8 reserved_at_0[0x8];
e281682b 7106 u8 local_port[0x8];
b4ff3a36 7107 u8 reserved_at_10[0x10];
e281682b 7108
b4ff3a36 7109 u8 reserved_at_20[0x1c];
e281682b
SM		 7110 u8 vl_hw_cap[0x4];
7111
b4ff3a36 7112 u8 reserved_at_40[0x1c];
e281682b
SM		 7113 u8 vl_admin[0x4];
7114
b4ff3a36 7115 u8 reserved_at_60[0x1c];
e281682b
SM		 7116 u8 vl_operational[0x4];
7117};
7118
7119struct mlx5_ifc_pude_reg_bits {
7120 u8 swid[0x8];
7121 u8 local_port[0x8];
b4ff3a36 7122 u8 reserved_at_10[0x4];
e281682b 7123 u8 admin_status[0x4];
b4ff3a36 7124 u8 reserved_at_18[0x4];
e281682b
SM		 7125 u8 oper_status[0x4];
7126
b4ff3a36 7127 u8 reserved_at_20[0x60];
e281682b
SM		 7128};
7129
7130struct mlx5_ifc_ptys_reg_bits {
e7e31ca4 7131 u8 reserved_at_0[0x1];
7486216b 7132 u8 an_disable_admin[0x1];
e7e31ca4
BW		 7133 u8 an_disable_cap[0x1];
7134 u8 reserved_at_3[0x5];
e281682b 7135 u8 local_port[0x8];
b4ff3a36 7136 u8 reserved_at_10[0xd];
e281682b
SM		 7137 u8 proto_mask[0x3];
7138
7486216b
SM		 7139 u8 an_status[0x4];
7140 u8 reserved_at_24[0x3c];
e281682b
SM		 7141
7142 u8 eth_proto_capability[0x20];
7143
7144 u8 ib_link_width_capability[0x10];
7145 u8 ib_proto_capability[0x10];
7146
b4ff3a36 7147 u8 reserved_at_a0[0x20];
e281682b
SM		 7148
7149 u8 eth_proto_admin[0x20];
7150
7151 u8 ib_link_width_admin[0x10];
7152 u8 ib_proto_admin[0x10];
7153
b4ff3a36 7154 u8 reserved_at_100[0x20];
e281682b
SM		 7155
7156 u8 eth_proto_oper[0x20];
7157
7158 u8 ib_link_width_oper[0x10];
7159 u8 ib_proto_oper[0x10];
7160
b4ff3a36 7161 u8 reserved_at_160[0x20];
e281682b
SM		 7162
7163 u8 eth_proto_lp_advertise[0x20];
7164
b4ff3a36 7165 u8 reserved_at_1a0[0x60];
e281682b
SM		 7166};
7167
7d5e1423
SM		 7168struct mlx5_ifc_mlcr_reg_bits {
7169 u8 reserved_at_0[0x8];
7170 u8 local_port[0x8];
7171 u8 reserved_at_10[0x20];
7172
7173 u8 beacon_duration[0x10];
7174 u8 reserved_at_40[0x10];
7175
7176 u8 beacon_remain[0x10];
7177};
7178
e281682b 7179struct mlx5_ifc_ptas_reg_bits {
b4ff3a36 7180 u8 reserved_at_0[0x20];
e281682b
SM		 7181
7182 u8 algorithm_options[0x10];
b4ff3a36 7183 u8 reserved_at_30[0x4];
e281682b
SM		 7184 u8 repetitions_mode[0x4];
7185 u8 num_of_repetitions[0x8];
7186
7187 u8 grade_version[0x8];
7188 u8 height_grade_type[0x4];
7189 u8 phase_grade_type[0x4];
7190 u8 height_grade_weight[0x8];
7191 u8 phase_grade_weight[0x8];
7192
7193 u8 gisim_measure_bits[0x10];
7194 u8 adaptive_tap_measure_bits[0x10];
7195
7196 u8 ber_bath_high_error_threshold[0x10];
7197 u8 ber_bath_mid_error_threshold[0x10];
7198
7199 u8 ber_bath_low_error_threshold[0x10];
7200 u8 one_ratio_high_threshold[0x10];
7201
7202 u8 one_ratio_high_mid_threshold[0x10];
7203 u8 one_ratio_low_mid_threshold[0x10];
7204
7205 u8 one_ratio_low_threshold[0x10];
7206 u8 ndeo_error_threshold[0x10];
7207
7208 u8 mixer_offset_step_size[0x10];
b4ff3a36 7209 u8 reserved_at_110[0x8];
e281682b
SM		 7210 u8 mix90_phase_for_voltage_bath[0x8];
7211
7212 u8 mixer_offset_start[0x10];
7213 u8 mixer_offset_end[0x10];
7214
b4ff3a36 7215 u8 reserved_at_140[0x15];
e281682b
SM		 7216 u8 ber_test_time[0xb];
7217};
7218
7219struct mlx5_ifc_pspa_reg_bits {
7220 u8 swid[0x8];
7221 u8 local_port[0x8];
7222 u8 sub_port[0x8];
b4ff3a36 7223 u8 reserved_at_18[0x8];
e281682b 7224
b4ff3a36 7225 u8 reserved_at_20[0x20];
e281682b
SM		 7226};
7227
7228struct mlx5_ifc_pqdr_reg_bits {
b4ff3a36 7229 u8 reserved_at_0[0x8];
e281682b 7230 u8 local_port[0x8];
b4ff3a36 7231 u8 reserved_at_10[0x5];
e281682b 7232 u8 prio[0x3];
b4ff3a36 7233 u8 reserved_at_18[0x6];
e281682b
SM		 7234 u8 mode[0x2];
7235
b4ff3a36 7236 u8 reserved_at_20[0x20];
e281682b 7237
b4ff3a36 7238 u8 reserved_at_40[0x10];
e281682b
SM		 7239 u8 min_threshold[0x10];
7240
b4ff3a36 7241 u8 reserved_at_60[0x10];
e281682b
SM		 7242 u8 max_threshold[0x10];
7243
b4ff3a36 7244 u8 reserved_at_80[0x10];
e281682b
SM		 7245 u8 mark_probability_denominator[0x10];
7246
b4ff3a36 7247 u8 reserved_at_a0[0x60];
e281682b
SM		 7248};
7249
7250struct mlx5_ifc_ppsc_reg_bits {
b4ff3a36 7251 u8 reserved_at_0[0x8];
e281682b 7252 u8 local_port[0x8];
b4ff3a36 7253 u8 reserved_at_10[0x10];
e281682b 7254
b4ff3a36 7255 u8 reserved_at_20[0x60];
e281682b 7256
b4ff3a36 7257 u8 reserved_at_80[0x1c];
e281682b
SM		 7258 u8 wrps_admin[0x4];
7259
b4ff3a36 7260 u8 reserved_at_a0[0x1c];
e281682b
SM		 7261 u8 wrps_status[0x4];
7262
b4ff3a36 7263 u8 reserved_at_c0[0x8];
e281682b 7264 u8 up_threshold[0x8];
b4ff3a36 7265 u8 reserved_at_d0[0x8];
e281682b
SM		 7266 u8 down_threshold[0x8];
7267
b4ff3a36 7268 u8 reserved_at_e0[0x20];
e281682b 7269
b4ff3a36 7270 u8 reserved_at_100[0x1c];
e281682b
SM		 7271 u8 srps_admin[0x4];
7272
b4ff3a36 7273 u8 reserved_at_120[0x1c];
e281682b
SM		 7274 u8 srps_status[0x4];
7275
b4ff3a36 7276 u8 reserved_at_140[0x40];
e281682b
SM		 7277};
7278
7279struct mlx5_ifc_pplr_reg_bits {
b4ff3a36 7280 u8 reserved_at_0[0x8];
e281682b 7281 u8 local_port[0x8];
b4ff3a36 7282 u8 reserved_at_10[0x10];
e281682b 7283
b4ff3a36 7284 u8 reserved_at_20[0x8];
e281682b 7285 u8 lb_cap[0x8];
b4ff3a36 7286 u8 reserved_at_30[0x8];
e281682b
SM		 7287 u8 lb_en[0x8];
7288};
7289
7290struct mlx5_ifc_pplm_reg_bits {
b4ff3a36 7291 u8 reserved_at_0[0x8];
e281682b 7292 u8 local_port[0x8];
b4ff3a36 7293 u8 reserved_at_10[0x10];
e281682b 7294
b4ff3a36 7295 u8 reserved_at_20[0x20];
e281682b
SM		 7296
7297 u8 port_profile_mode[0x8];
7298 u8 static_port_profile[0x8];
7299 u8 active_port_profile[0x8];
b4ff3a36 7300 u8 reserved_at_58[0x8];
e281682b
SM		 7301
7302 u8 retransmission_active[0x8];
7303 u8 fec_mode_active[0x18];
7304
b4ff3a36 7305 u8 reserved_at_80[0x20];
e281682b
SM		 7306};
7307
7308struct mlx5_ifc_ppcnt_reg_bits {
7309 u8 swid[0x8];
7310 u8 local_port[0x8];
7311 u8 pnat[0x2];
b4ff3a36 7312 u8 reserved_at_12[0x8];
e281682b
SM		 7313 u8 grp[0x6];
7314
7315 u8 clr[0x1];
b4ff3a36 7316 u8 reserved_at_21[0x1c];
e281682b
SM		 7317 u8 prio_tc[0x3];
7318
7319 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
7320};
7321
8ed1a630
GP		 7322struct mlx5_ifc_mpcnt_reg_bits {
7323 u8 reserved_at_0[0x8];
7324 u8 pcie_index[0x8];
7325 u8 reserved_at_10[0xa];
7326 u8 grp[0x6];
7327
7328 u8 clr[0x1];
7329 u8 reserved_at_21[0x1f];
7330
7331 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
7332};
7333
e281682b 7334struct mlx5_ifc_ppad_reg_bits {
b4ff3a36 7335 u8 reserved_at_0[0x3];
e281682b 7336 u8 single_mac[0x1];
b4ff3a36 7337 u8 reserved_at_4[0x4];
e281682b
SM		 7338 u8 local_port[0x8];
7339 u8 mac_47_32[0x10];
7340
7341 u8 mac_31_0[0x20];
7342
b4ff3a36 7343 u8 reserved_at_40[0x40];
e281682b
SM		 7344};
7345
7346struct mlx5_ifc_pmtu_reg_bits {
b4ff3a36 7347 u8 reserved_at_0[0x8];
e281682b 7348 u8 local_port[0x8];
b4ff3a36 7349 u8 reserved_at_10[0x10];
e281682b
SM		 7350
7351 u8 max_mtu[0x10];
b4ff3a36 7352 u8 reserved_at_30[0x10];
e281682b
SM		 7353
7354 u8 admin_mtu[0x10];
b4ff3a36 7355 u8 reserved_at_50[0x10];
e281682b
SM		 7356
7357 u8 oper_mtu[0x10];
b4ff3a36 7358 u8 reserved_at_70[0x10];
e281682b
SM		 7359};
7360
7361struct mlx5_ifc_pmpr_reg_bits {
b4ff3a36 7362 u8 reserved_at_0[0x8];
e281682b 7363 u8 module[0x8];
b4ff3a36 7364 u8 reserved_at_10[0x10];
e281682b 7365
b4ff3a36 7366 u8 reserved_at_20[0x18];
e281682b
SM		 7367 u8 attenuation_5g[0x8];
7368
b4ff3a36 7369 u8 reserved_at_40[0x18];
e281682b
SM		 7370 u8 attenuation_7g[0x8];
7371
b4ff3a36 7372 u8 reserved_at_60[0x18];
e281682b
SM		 7373 u8 attenuation_12g[0x8];
7374};
7375
7376struct mlx5_ifc_pmpe_reg_bits {
b4ff3a36 7377 u8 reserved_at_0[0x8];
e281682b 7378 u8 module[0x8];
b4ff3a36 7379 u8 reserved_at_10[0xc];
e281682b
SM		 7380 u8 module_status[0x4];
7381
b4ff3a36 7382 u8 reserved_at_20[0x60];
e281682b
SM		 7383};
7384
7385struct mlx5_ifc_pmpc_reg_bits {
7386 u8 module_state_updated[32][0x8];
7387};
7388
7389struct mlx5_ifc_pmlpn_reg_bits {
b4ff3a36 7390 u8 reserved_at_0[0x4];
e281682b
SM		 7391 u8 mlpn_status[0x4];
7392 u8 local_port[0x8];
b4ff3a36 7393 u8 reserved_at_10[0x10];
e281682b
SM		 7394
7395 u8 e[0x1];
b4ff3a36 7396 u8 reserved_at_21[0x1f];
e281682b
SM		 7397};
7398
7399struct mlx5_ifc_pmlp_reg_bits {
7400 u8 rxtx[0x1];
b4ff3a36 7401 u8 reserved_at_1[0x7];
e281682b 7402 u8 local_port[0x8];
b4ff3a36 7403 u8 reserved_at_10[0x8];
e281682b
SM		 7404 u8 width[0x8];
7405
7406 u8 lane0_module_mapping[0x20];
7407
7408 u8 lane1_module_mapping[0x20];
7409
7410 u8 lane2_module_mapping[0x20];
7411
7412 u8 lane3_module_mapping[0x20];
7413
b4ff3a36 7414 u8 reserved_at_a0[0x160];
e281682b
SM		 7415};
7416
7417struct mlx5_ifc_pmaos_reg_bits {
b4ff3a36 7418 u8 reserved_at_0[0x8];
e281682b 7419 u8 module[0x8];
b4ff3a36 7420 u8 reserved_at_10[0x4];
e281682b 7421 u8 admin_status[0x4];
b4ff3a36 7422 u8 reserved_at_18[0x4];
e281682b
SM		 7423 u8 oper_status[0x4];
7424
7425 u8 ase[0x1];
7426 u8 ee[0x1];
b4ff3a36 7427 u8 reserved_at_22[0x1c];
e281682b
SM		 7428 u8 e[0x2];
7429
b4ff3a36 7430 u8 reserved_at_40[0x40];
e281682b
SM		 7431};
7432
7433struct mlx5_ifc_plpc_reg_bits {
b4ff3a36 7434 u8 reserved_at_0[0x4];
e281682b 7435 u8 profile_id[0xc];
b4ff3a36 7436 u8 reserved_at_10[0x4];
e281682b 7437 u8 proto_mask[0x4];
b4ff3a36 7438 u8 reserved_at_18[0x8];
e281682b 7439
b4ff3a36 7440 u8 reserved_at_20[0x10];
e281682b
SM		 7441 u8 lane_speed[0x10];
7442
b4ff3a36 7443 u8 reserved_at_40[0x17];
e281682b
SM		 7444 u8 lpbf[0x1];
7445 u8 fec_mode_policy[0x8];
7446
7447 u8 retransmission_capability[0x8];
7448 u8 fec_mode_capability[0x18];
7449
7450 u8 retransmission_support_admin[0x8];
7451 u8 fec_mode_support_admin[0x18];
7452
7453 u8 retransmission_request_admin[0x8];
7454 u8 fec_mode_request_admin[0x18];
7455
b4ff3a36 7456 u8 reserved_at_c0[0x80];
e281682b
SM		 7457};
7458
7459struct mlx5_ifc_plib_reg_bits {
b4ff3a36 7460 u8 reserved_at_0[0x8];
e281682b 7461 u8 local_port[0x8];
b4ff3a36 7462 u8 reserved_at_10[0x8];
e281682b
SM		 7463 u8 ib_port[0x8];
7464
b4ff3a36 7465 u8 reserved_at_20[0x60];
e281682b
SM		 7466};
7467
7468struct mlx5_ifc_plbf_reg_bits {
b4ff3a36 7469 u8 reserved_at_0[0x8];
e281682b 7470 u8 local_port[0x8];
b4ff3a36 7471 u8 reserved_at_10[0xd];
e281682b
SM		 7472 u8 lbf_mode[0x3];
7473
b4ff3a36 7474 u8 reserved_at_20[0x20];
e281682b
SM		 7475};
7476
7477struct mlx5_ifc_pipg_reg_bits {
b4ff3a36 7478 u8 reserved_at_0[0x8];
e281682b 7479 u8 local_port[0x8];
b4ff3a36 7480 u8 reserved_at_10[0x10];
e281682b
SM		 7481
7482 u8 dic[0x1];
b4ff3a36 7483 u8 reserved_at_21[0x19];
e281682b 7484 u8 ipg[0x4];
b4ff3a36 7485 u8 reserved_at_3e[0x2];
e281682b
SM		 7486};
7487
7488struct mlx5_ifc_pifr_reg_bits {
b4ff3a36 7489 u8 reserved_at_0[0x8];
e281682b 7490 u8 local_port[0x8];
b4ff3a36 7491 u8 reserved_at_10[0x10];
e281682b 7492
b4ff3a36 7493 u8 reserved_at_20[0xe0];
e281682b
SM		 7494
7495 u8 port_filter[8][0x20];
7496
7497 u8 port_filter_update_en[8][0x20];
7498};
7499
7500struct mlx5_ifc_pfcc_reg_bits {
b4ff3a36 7501 u8 reserved_at_0[0x8];
e281682b 7502 u8 local_port[0x8];
b4ff3a36 7503 u8 reserved_at_10[0x10];
e281682b
SM		 7504
7505 u8 ppan[0x4];
b4ff3a36 7506 u8 reserved_at_24[0x4];
e281682b 7507 u8 prio_mask_tx[0x8];
b4ff3a36 7508 u8 reserved_at_30[0x8];
e281682b
SM		 7509 u8 prio_mask_rx[0x8];
7510
7511 u8 pptx[0x1];
7512 u8 aptx[0x1];
b4ff3a36 7513 u8 reserved_at_42[0x6];
e281682b 7514 u8 pfctx[0x8];
b4ff3a36 7515 u8 reserved_at_50[0x10];
e281682b
SM		 7516
7517 u8 pprx[0x1];
7518 u8 aprx[0x1];
b4ff3a36 7519 u8 reserved_at_62[0x6];
e281682b 7520 u8 pfcrx[0x8];
b4ff3a36 7521 u8 reserved_at_70[0x10];
e281682b 7522
b4ff3a36 7523 u8 reserved_at_80[0x80];
e281682b
SM		 7524};
7525
7526struct mlx5_ifc_pelc_reg_bits {
7527 u8 op[0x4];
b4ff3a36 7528 u8 reserved_at_4[0x4];
e281682b 7529 u8 local_port[0x8];
b4ff3a36 7530 u8 reserved_at_10[0x10];
e281682b
SM		 7531
7532 u8 op_admin[0x8];
7533 u8 op_capability[0x8];
7534 u8 op_request[0x8];
7535 u8 op_active[0x8];
7536
7537 u8 admin[0x40];
7538
7539 u8 capability[0x40];
7540
7541 u8 request[0x40];
7542
7543 u8 active[0x40];
7544
b4ff3a36 7545 u8 reserved_at_140[0x80];
e281682b
SM		 7546};
7547
7548struct mlx5_ifc_peir_reg_bits {
b4ff3a36 7549 u8 reserved_at_0[0x8];
e281682b 7550 u8 local_port[0x8];
b4ff3a36 7551 u8 reserved_at_10[0x10];
e281682b 7552
b4ff3a36 7553 u8 reserved_at_20[0xc];
e281682b 7554 u8 error_count[0x4];
b4ff3a36 7555 u8 reserved_at_30[0x10];
e281682b 7556
b4ff3a36 7557 u8 reserved_at_40[0xc];
e281682b 7558 u8 lane[0x4];
b4ff3a36 7559 u8 reserved_at_50[0x8];
e281682b
SM		 7560 u8 error_type[0x8];
7561};
7562
cfdcbcea
GP		 7563struct mlx5_ifc_pcam_enhanced_features_bits {
7564 u8 reserved_at_0[0x7e];
7565
7566 u8 ppcnt_discard_group[0x1];
7567 u8 ppcnt_statistical_group[0x1];
7568};
7569
7570struct mlx5_ifc_pcam_reg_bits {
7571 u8 reserved_at_0[0x8];
7572 u8 feature_group[0x8];
7573 u8 reserved_at_10[0x8];
7574 u8 access_reg_group[0x8];
7575
7576 u8 reserved_at_20[0x20];
7577
7578 union {
7579 u8 reserved_at_0[0x80];
7580 } port_access_reg_cap_mask;
7581
7582 u8 reserved_at_c0[0x80];
7583
7584 union {
7585 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
7586 u8 reserved_at_0[0x80];
7587 } feature_cap_mask;
7588
7589 u8 reserved_at_1c0[0xc0];
7590};
7591
7592struct mlx5_ifc_mcam_enhanced_features_bits {
7593 u8 reserved_at_0[0x7f];
7594
7595 u8 pcie_performance_group[0x1];
7596};
7597
7598struct mlx5_ifc_mcam_reg_bits {
7599 u8 reserved_at_0[0x8];
7600 u8 feature_group[0x8];
7601 u8 reserved_at_10[0x8];
7602 u8 access_reg_group[0x8];
7603
7604 u8 reserved_at_20[0x20];
7605
7606 union {
7607 u8 reserved_at_0[0x80];
7608 } mng_access_reg_cap_mask;
7609
7610 u8 reserved_at_c0[0x80];
7611
7612 union {
7613 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
7614 u8 reserved_at_0[0x80];
7615 } mng_feature_cap_mask;
7616
7617 u8 reserved_at_1c0[0x80];
7618};
7619
e281682b 7620struct mlx5_ifc_pcap_reg_bits {
b4ff3a36 7621 u8 reserved_at_0[0x8];
e281682b 7622 u8 local_port[0x8];
b4ff3a36 7623 u8 reserved_at_10[0x10];
e281682b
SM		 7624
7625 u8 port_capability_mask[4][0x20];
7626};
7627
7628struct mlx5_ifc_paos_reg_bits {
7629 u8 swid[0x8];
7630 u8 local_port[0x8];
b4ff3a36 7631 u8 reserved_at_10[0x4];
e281682b 7632 u8 admin_status[0x4];
b4ff3a36 7633 u8 reserved_at_18[0x4];
e281682b
SM		 7634 u8 oper_status[0x4];
7635
7636 u8 ase[0x1];
7637 u8 ee[0x1];
b4ff3a36 7638 u8 reserved_at_22[0x1c];
e281682b
SM		 7639 u8 e[0x2];
7640
b4ff3a36 7641 u8 reserved_at_40[0x40];
e281682b
SM		 7642};
7643
7644struct mlx5_ifc_pamp_reg_bits {
b4ff3a36 7645 u8 reserved_at_0[0x8];
e281682b 7646 u8 opamp_group[0x8];
b4ff3a36 7647 u8 reserved_at_10[0xc];
e281682b
SM		 7648 u8 opamp_group_type[0x4];
7649
7650 u8 start_index[0x10];
b4ff3a36 7651 u8 reserved_at_30[0x4];
e281682b
SM		 7652 u8 num_of_indices[0xc];
7653
7654 u8 index_data[18][0x10];
7655};
7656
7d5e1423
SM		 7657struct mlx5_ifc_pcmr_reg_bits {
7658 u8 reserved_at_0[0x8];
7659 u8 local_port[0x8];
7660 u8 reserved_at_10[0x2e];
7661 u8 fcs_cap[0x1];
7662 u8 reserved_at_3f[0x1f];
7663 u8 fcs_chk[0x1];
7664 u8 reserved_at_5f[0x1];
7665};
7666
e281682b 7667struct mlx5_ifc_lane_2_module_mapping_bits {
b4ff3a36 7668 u8 reserved_at_0[0x6];
e281682b 7669 u8 rx_lane[0x2];
b4ff3a36 7670 u8 reserved_at_8[0x6];
e281682b 7671 u8 tx_lane[0x2];
b4ff3a36 7672 u8 reserved_at_10[0x8];
e281682b
SM		 7673 u8 module[0x8];
7674};
7675
7676struct mlx5_ifc_bufferx_reg_bits {
b4ff3a36 7677 u8 reserved_at_0[0x6];
e281682b
SM		 7678 u8 lossy[0x1];
7679 u8 epsb[0x1];
b4ff3a36 7680 u8 reserved_at_8[0xc];
e281682b
SM		 7681 u8 size[0xc];
7682
7683 u8 xoff_threshold[0x10];
7684 u8 xon_threshold[0x10];
7685};
7686
7687struct mlx5_ifc_set_node_in_bits {
7688 u8 node_description[64][0x8];
7689};
7690
7691struct mlx5_ifc_register_power_settings_bits {
b4ff3a36 7692 u8 reserved_at_0[0x18];
e281682b
SM		 7693 u8 power_settings_level[0x8];
7694
b4ff3a36 7695 u8 reserved_at_20[0x60];
e281682b
SM		 7696};
7697
7698struct mlx5_ifc_register_host_endianness_bits {
7699 u8 he[0x1];
b4ff3a36 7700 u8 reserved_at_1[0x1f];
e281682b 7701
b4ff3a36 7702 u8 reserved_at_20[0x60];
e281682b
SM		 7703};
7704
7705struct mlx5_ifc_umr_pointer_desc_argument_bits {
b4ff3a36 7706 u8 reserved_at_0[0x20];
e281682b
SM		 7707
7708 u8 mkey[0x20];
7709
7710 u8 addressh_63_32[0x20];
7711
7712 u8 addressl_31_0[0x20];
7713};
7714
7715struct mlx5_ifc_ud_adrs_vector_bits {
7716 u8 dc_key[0x40];
7717
7718 u8 ext[0x1];
b4ff3a36 7719 u8 reserved_at_41[0x7];
e281682b
SM		 7720 u8 destination_qp_dct[0x18];
7721
7722 u8 static_rate[0x4];
7723 u8 sl_eth_prio[0x4];
7724 u8 fl[0x1];
7725 u8 mlid[0x7];
7726 u8 rlid_udp_sport[0x10];
7727
b4ff3a36 7728 u8 reserved_at_80[0x20];
e281682b
SM		 7729
7730 u8 rmac_47_16[0x20];
7731
7732 u8 rmac_15_0[0x10];
7733 u8 tclass[0x8];
7734 u8 hop_limit[0x8];
7735
b4ff3a36 7736 u8 reserved_at_e0[0x1];
e281682b 7737 u8 grh[0x1];
b4ff3a36 7738 u8 reserved_at_e2[0x2];
e281682b
SM		 7739 u8 src_addr_index[0x8];
7740 u8 flow_label[0x14];
7741
7742 u8 rgid_rip[16][0x8];
7743};
7744
7745struct mlx5_ifc_pages_req_event_bits {
b4ff3a36 7746 u8 reserved_at_0[0x10];
e281682b
SM		 7747 u8 function_id[0x10];
7748
7749 u8 num_pages[0x20];
7750
b4ff3a36 7751 u8 reserved_at_40[0xa0];
e281682b
SM		 7752};
7753
7754struct mlx5_ifc_eqe_bits {
b4ff3a36 7755 u8 reserved_at_0[0x8];
e281682b 7756 u8 event_type[0x8];
b4ff3a36 7757 u8 reserved_at_10[0x8];
e281682b
SM		 7758 u8 event_sub_type[0x8];
7759
b4ff3a36 7760 u8 reserved_at_20[0xe0];
e281682b
SM		 7761
7762 union mlx5_ifc_event_auto_bits event_data;
7763
b4ff3a36 7764 u8 reserved_at_1e0[0x10];
e281682b 7765 u8 signature[0x8];
b4ff3a36 7766 u8 reserved_at_1f8[0x7];
e281682b
SM		 7767 u8 owner[0x1];
7768};
7769
7770enum {
7771 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
7772};
7773
7774struct mlx5_ifc_cmd_queue_entry_bits {
7775 u8 type[0x8];
b4ff3a36 7776 u8 reserved_at_8[0x18];
e281682b
SM		 7777
7778 u8 input_length[0x20];
7779
7780 u8 input_mailbox_pointer_63_32[0x20];
7781
7782 u8 input_mailbox_pointer_31_9[0x17];
b4ff3a36 7783 u8 reserved_at_77[0x9];
e281682b
SM		 7784
7785 u8 command_input_inline_data[16][0x8];
7786
7787 u8 command_output_inline_data[16][0x8];
7788
7789 u8 output_mailbox_pointer_63_32[0x20];
7790
7791 u8 output_mailbox_pointer_31_9[0x17];
b4ff3a36 7792 u8 reserved_at_1b7[0x9];
e281682b
SM		 7793
7794 u8 output_length[0x20];
7795
7796 u8 token[0x8];
7797 u8 signature[0x8];
b4ff3a36 7798 u8 reserved_at_1f0[0x8];
e281682b
SM		 7799 u8 status[0x7];
7800 u8 ownership[0x1];
7801};
7802
7803struct mlx5_ifc_cmd_out_bits {
7804 u8 status[0x8];
b4ff3a36 7805 u8 reserved_at_8[0x18];
e281682b
SM		 7806
7807 u8 syndrome[0x20];
7808
7809 u8 command_output[0x20];
7810};
7811
7812struct mlx5_ifc_cmd_in_bits {
7813 u8 opcode[0x10];
b4ff3a36 7814 u8 reserved_at_10[0x10];
e281682b 7815
b4ff3a36 7816 u8 reserved_at_20[0x10];
e281682b
SM		 7817 u8 op_mod[0x10];
7818
7819 u8 command[0][0x20];
7820};
7821
7822struct mlx5_ifc_cmd_if_box_bits {
7823 u8 mailbox_data[512][0x8];
7824
b4ff3a36 7825 u8 reserved_at_1000[0x180];
e281682b
SM		 7826
7827 u8 next_pointer_63_32[0x20];
7828
7829 u8 next_pointer_31_10[0x16];
b4ff3a36 7830 u8 reserved_at_11b6[0xa];
e281682b
SM		 7831
7832 u8 block_number[0x20];
7833
b4ff3a36 7834 u8 reserved_at_11e0[0x8];
e281682b
SM		 7835 u8 token[0x8];
7836 u8 ctrl_signature[0x8];
7837 u8 signature[0x8];
7838};
7839
7840struct mlx5_ifc_mtt_bits {
7841 u8 ptag_63_32[0x20];
7842
7843 u8 ptag_31_8[0x18];
b4ff3a36 7844 u8 reserved_at_38[0x6];
e281682b
SM		 7845 u8 wr_en[0x1];
7846 u8 rd_en[0x1];
7847};
7848
928cfe87
TT		 7849struct mlx5_ifc_query_wol_rol_out_bits {
7850 u8 status[0x8];
7851 u8 reserved_at_8[0x18];
7852
7853 u8 syndrome[0x20];
7854
7855 u8 reserved_at_40[0x10];
7856 u8 rol_mode[0x8];
7857 u8 wol_mode[0x8];
7858
7859 u8 reserved_at_60[0x20];
7860};
7861
7862struct mlx5_ifc_query_wol_rol_in_bits {
7863 u8 opcode[0x10];
7864 u8 reserved_at_10[0x10];
7865
7866 u8 reserved_at_20[0x10];
7867 u8 op_mod[0x10];
7868
7869 u8 reserved_at_40[0x40];
7870};
7871
7872struct mlx5_ifc_set_wol_rol_out_bits {
7873 u8 status[0x8];
7874 u8 reserved_at_8[0x18];
7875
7876 u8 syndrome[0x20];
7877
7878 u8 reserved_at_40[0x40];
7879};
7880
7881struct mlx5_ifc_set_wol_rol_in_bits {
7882 u8 opcode[0x10];
7883 u8 reserved_at_10[0x10];
7884
7885 u8 reserved_at_20[0x10];
7886 u8 op_mod[0x10];
7887
7888 u8 rol_mode_valid[0x1];
7889 u8 wol_mode_valid[0x1];
7890 u8 reserved_at_42[0xe];
7891 u8 rol_mode[0x8];
7892 u8 wol_mode[0x8];
7893
7894 u8 reserved_at_60[0x20];
7895};
7896
e281682b
SM		 7897enum {
7898 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
7899 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
7900 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
7901};
7902
7903enum {
7904 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
7905 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
7906 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
7907};
7908
7909enum {
7910 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
7911 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
7912 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
7913 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
7914 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
7915 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
7916 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
7917 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
7918 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
7919 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
7920 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
7921};
7922
7923struct mlx5_ifc_initial_seg_bits {
7924 u8 fw_rev_minor[0x10];
7925 u8 fw_rev_major[0x10];
7926
7927 u8 cmd_interface_rev[0x10];
7928 u8 fw_rev_subminor[0x10];
7929
b4ff3a36 7930 u8 reserved_at_40[0x40];
e281682b
SM		 7931
7932 u8 cmdq_phy_addr_63_32[0x20];
7933
7934 u8 cmdq_phy_addr_31_12[0x14];
b4ff3a36 7935 u8 reserved_at_b4[0x2];
e281682b
SM		 7936 u8 nic_interface[0x2];
7937 u8 log_cmdq_size[0x4];
7938 u8 log_cmdq_stride[0x4];
7939
7940 u8 command_doorbell_vector[0x20];
7941
b4ff3a36 7942 u8 reserved_at_e0[0xf00];
e281682b
SM		 7943
7944 u8 initializing[0x1];
b4ff3a36 7945 u8 reserved_at_fe1[0x4];
e281682b 7946 u8 nic_interface_supported[0x3];
b4ff3a36 7947 u8 reserved_at_fe8[0x18];
e281682b
SM		 7948
7949 struct mlx5_ifc_health_buffer_bits health_buffer;
7950
7951 u8 no_dram_nic_offset[0x20];
7952
b4ff3a36 7953 u8 reserved_at_1220[0x6e40];
e281682b 7954
b4ff3a36 7955 u8 reserved_at_8060[0x1f];
e281682b
SM		 7956 u8 clear_int[0x1];
7957
7958 u8 health_syndrome[0x8];
7959 u8 health_counter[0x18];
7960
b4ff3a36 7961 u8 reserved_at_80a0[0x17fc0];
e281682b
SM		 7962};
7963
f9a1ef72
EE		 7964struct mlx5_ifc_mtpps_reg_bits {
7965 u8 reserved_at_0[0xc];
7966 u8 cap_number_of_pps_pins[0x4];
7967 u8 reserved_at_10[0x4];
7968 u8 cap_max_num_of_pps_in_pins[0x4];
7969 u8 reserved_at_18[0x4];
7970 u8 cap_max_num_of_pps_out_pins[0x4];
7971
7972 u8 reserved_at_20[0x24];
7973 u8 cap_pin_3_mode[0x4];
7974 u8 reserved_at_48[0x4];
7975 u8 cap_pin_2_mode[0x4];
7976 u8 reserved_at_50[0x4];
7977 u8 cap_pin_1_mode[0x4];
7978 u8 reserved_at_58[0x4];
7979 u8 cap_pin_0_mode[0x4];
7980
7981 u8 reserved_at_60[0x4];
7982 u8 cap_pin_7_mode[0x4];
7983 u8 reserved_at_68[0x4];
7984 u8 cap_pin_6_mode[0x4];
7985 u8 reserved_at_70[0x4];
7986 u8 cap_pin_5_mode[0x4];
7987 u8 reserved_at_78[0x4];
7988 u8 cap_pin_4_mode[0x4];
7989
7990 u8 reserved_at_80[0x80];
7991
7992 u8 enable[0x1];
7993 u8 reserved_at_101[0xb];
7994 u8 pattern[0x4];
7995 u8 reserved_at_110[0x4];
7996 u8 pin_mode[0x4];
7997 u8 pin[0x8];
7998
7999 u8 reserved_at_120[0x20];
8000
8001 u8 time_stamp[0x40];
8002
8003 u8 out_pulse_duration[0x10];
8004 u8 out_periodic_adjustment[0x10];
8005
8006 u8 reserved_at_1a0[0x60];
8007};
8008
8009struct mlx5_ifc_mtppse_reg_bits {
8010 u8 reserved_at_0[0x18];
8011 u8 pin[0x8];
8012 u8 event_arm[0x1];
8013 u8 reserved_at_21[0x1b];
8014 u8 event_generation_mode[0x4];
8015 u8 reserved_at_40[0x40];
8016};
8017
e281682b
SM		 8018union mlx5_ifc_ports_control_registers_document_bits {
8019 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
8020 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
8021 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
8022 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
8023 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
8024 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
8025 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
8026 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
8027 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
8028 struct mlx5_ifc_pamp_reg_bits pamp_reg;
8029 struct mlx5_ifc_paos_reg_bits paos_reg;
8030 struct mlx5_ifc_pcap_reg_bits pcap_reg;
8031 struct mlx5_ifc_peir_reg_bits peir_reg;
8032 struct mlx5_ifc_pelc_reg_bits pelc_reg;
8033 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
1c64bf6f 8034 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b
SM		 8035 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
8036 struct mlx5_ifc_pifr_reg_bits pifr_reg;
8037 struct mlx5_ifc_pipg_reg_bits pipg_reg;
8038 struct mlx5_ifc_plbf_reg_bits plbf_reg;
8039 struct mlx5_ifc_plib_reg_bits plib_reg;
8040 struct mlx5_ifc_plpc_reg_bits plpc_reg;
8041 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
8042 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
8043 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
8044 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
8045 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
8046 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
8047 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
8048 struct mlx5_ifc_ppad_reg_bits ppad_reg;
8049 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
8ed1a630 8050 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
e281682b
SM		 8051 struct mlx5_ifc_pplm_reg_bits pplm_reg;
8052 struct mlx5_ifc_pplr_reg_bits pplr_reg;
8053 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
8054 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
8055 struct mlx5_ifc_pspa_reg_bits pspa_reg;
8056 struct mlx5_ifc_ptas_reg_bits ptas_reg;
8057 struct mlx5_ifc_ptys_reg_bits ptys_reg;
7d5e1423 8058 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
e281682b
SM		 8059 struct mlx5_ifc_pude_reg_bits pude_reg;
8060 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
8061 struct mlx5_ifc_slrg_reg_bits slrg_reg;
8062 struct mlx5_ifc_sltp_reg_bits sltp_reg;
f9a1ef72
EE		 8063 struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
8064 struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
b4ff3a36 8065 u8 reserved_at_0[0x60e0];
e281682b
SM		 8066};
8067
8068union mlx5_ifc_debug_enhancements_document_bits {
8069 struct mlx5_ifc_health_buffer_bits health_buffer;
b4ff3a36 8070 u8 reserved_at_0[0x200];
e281682b
SM		 8071};
8072
8073union mlx5_ifc_uplink_pci_interface_document_bits {
8074 struct mlx5_ifc_initial_seg_bits initial_seg;
b4ff3a36 8075 u8 reserved_at_0[0x20060];
b775516b
EC		 8076};
8077
2cc43b49
MG		 8078struct mlx5_ifc_set_flow_table_root_out_bits {
8079 u8 status[0x8];
b4ff3a36 8080 u8 reserved_at_8[0x18];
2cc43b49
MG		 8081
8082 u8 syndrome[0x20];
8083
b4ff3a36 8084 u8 reserved_at_40[0x40];
2cc43b49
MG		 8085};
8086
8087struct mlx5_ifc_set_flow_table_root_in_bits {
8088 u8 opcode[0x10];
b4ff3a36 8089 u8 reserved_at_10[0x10];
2cc43b49 8090
b4ff3a36 8091 u8 reserved_at_20[0x10];
2cc43b49
MG		 8092 u8 op_mod[0x10];
8093
7d5e1423
SM		 8094 u8 other_vport[0x1];
8095 u8 reserved_at_41[0xf];
8096 u8 vport_number[0x10];
8097
8098 u8 reserved_at_60[0x20];
2cc43b49
MG		 8099
8100 u8 table_type[0x8];
b4ff3a36 8101 u8 reserved_at_88[0x18];
2cc43b49 8102
b4ff3a36 8103 u8 reserved_at_a0[0x8];
2cc43b49
MG		 8104 u8 table_id[0x18];
8105
b4ff3a36 8106 u8 reserved_at_c0[0x140];
2cc43b49
MG		 8107};
8108
34a40e68 8109enum {
84df61eb
AH		 8110 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
8111 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
34a40e68
MG		 8112};
8113
8114struct mlx5_ifc_modify_flow_table_out_bits {
8115 u8 status[0x8];
b4ff3a36 8116 u8 reserved_at_8[0x18];
34a40e68
MG		 8117
8118 u8 syndrome[0x20];
8119
b4ff3a36 8120 u8 reserved_at_40[0x40];
34a40e68
MG		 8121};
8122
8123struct mlx5_ifc_modify_flow_table_in_bits {
8124 u8 opcode[0x10];
b4ff3a36 8125 u8 reserved_at_10[0x10];
34a40e68 8126
b4ff3a36 8127 u8 reserved_at_20[0x10];
34a40e68
MG		 8128 u8 op_mod[0x10];
8129
7d5e1423
SM		 8130 u8 other_vport[0x1];
8131 u8 reserved_at_41[0xf];
8132 u8 vport_number[0x10];
34a40e68 8133
b4ff3a36 8134 u8 reserved_at_60[0x10];
34a40e68
MG		 8135 u8 modify_field_select[0x10];
8136
8137 u8 table_type[0x8];
b4ff3a36 8138 u8 reserved_at_88[0x18];
34a40e68 8139
b4ff3a36 8140 u8 reserved_at_a0[0x8];
34a40e68
MG		 8141 u8 table_id[0x18];
8142
b4ff3a36 8143 u8 reserved_at_c0[0x4];
34a40e68 8144 u8 table_miss_mode[0x4];
b4ff3a36 8145 u8 reserved_at_c8[0x18];
34a40e68 8146
b4ff3a36 8147 u8 reserved_at_e0[0x8];
34a40e68
MG		 8148 u8 table_miss_id[0x18];
8149
84df61eb
AH		 8150 u8 reserved_at_100[0x8];
8151 u8 lag_master_next_table_id[0x18];
8152
8153 u8 reserved_at_120[0x80];
34a40e68
MG		 8154};
8155
4f3961ee
SM		 8156struct mlx5_ifc_ets_tcn_config_reg_bits {
8157 u8 g[0x1];
8158 u8 b[0x1];
8159 u8 r[0x1];
8160 u8 reserved_at_3[0x9];
8161 u8 group[0x4];
8162 u8 reserved_at_10[0x9];
8163 u8 bw_allocation[0x7];
8164
8165 u8 reserved_at_20[0xc];
8166 u8 max_bw_units[0x4];
8167 u8 reserved_at_30[0x8];
8168 u8 max_bw_value[0x8];
8169};
8170
8171struct mlx5_ifc_ets_global_config_reg_bits {
8172 u8 reserved_at_0[0x2];
8173 u8 r[0x1];
8174 u8 reserved_at_3[0x1d];
8175
8176 u8 reserved_at_20[0xc];
8177 u8 max_bw_units[0x4];
8178 u8 reserved_at_30[0x8];
8179 u8 max_bw_value[0x8];
8180};
8181
8182struct mlx5_ifc_qetc_reg_bits {
8183 u8 reserved_at_0[0x8];
8184 u8 port_number[0x8];
8185 u8 reserved_at_10[0x30];
8186
8187 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
8188 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
8189};
8190
8191struct mlx5_ifc_qtct_reg_bits {
8192 u8 reserved_at_0[0x8];
8193 u8 port_number[0x8];
8194 u8 reserved_at_10[0xd];
8195 u8 prio[0x3];
8196
8197 u8 reserved_at_20[0x1d];
8198 u8 tclass[0x3];
8199};
8200
7d5e1423
SM		 8201struct mlx5_ifc_mcia_reg_bits {
8202 u8 l[0x1];
8203 u8 reserved_at_1[0x7];
8204 u8 module[0x8];
8205 u8 reserved_at_10[0x8];
8206 u8 status[0x8];
8207
8208 u8 i2c_device_address[0x8];
8209 u8 page_number[0x8];
8210 u8 device_address[0x10];
8211
8212 u8 reserved_at_40[0x10];
8213 u8 size[0x10];
8214
8215 u8 reserved_at_60[0x20];
8216
8217 u8 dword_0[0x20];
8218 u8 dword_1[0x20];
8219 u8 dword_2[0x20];
8220 u8 dword_3[0x20];
8221 u8 dword_4[0x20];
8222 u8 dword_5[0x20];
8223 u8 dword_6[0x20];
8224 u8 dword_7[0x20];
8225 u8 dword_8[0x20];
8226 u8 dword_9[0x20];
8227 u8 dword_10[0x20];
8228 u8 dword_11[0x20];
8229};
8230
7486216b
SM		 8231struct mlx5_ifc_dcbx_param_bits {
8232 u8 dcbx_cee_cap[0x1];
8233 u8 dcbx_ieee_cap[0x1];
8234 u8 dcbx_standby_cap[0x1];
8235 u8 reserved_at_0[0x5];
8236 u8 port_number[0x8];
8237 u8 reserved_at_10[0xa];
8238 u8 max_application_table_size[6];
8239 u8 reserved_at_20[0x15];
8240 u8 version_oper[0x3];
8241 u8 reserved_at_38[5];
8242 u8 version_admin[0x3];
8243 u8 willing_admin[0x1];
8244 u8 reserved_at_41[0x3];
8245 u8 pfc_cap_oper[0x4];
8246 u8 reserved_at_48[0x4];
8247 u8 pfc_cap_admin[0x4];
8248 u8 reserved_at_50[0x4];
8249 u8 num_of_tc_oper[0x4];
8250 u8 reserved_at_58[0x4];
8251 u8 num_of_tc_admin[0x4];
8252 u8 remote_willing[0x1];
8253 u8 reserved_at_61[3];
8254 u8 remote_pfc_cap[4];
8255 u8 reserved_at_68[0x14];
8256 u8 remote_num_of_tc[0x4];
8257 u8 reserved_at_80[0x18];
8258 u8 error[0x8];
8259 u8 reserved_at_a0[0x160];
8260};
84df61eb
AH		 8261
8262struct mlx5_ifc_lagc_bits {
8263 u8 reserved_at_0[0x1d];
8264 u8 lag_state[0x3];
8265
8266 u8 reserved_at_20[0x14];
8267 u8 tx_remap_affinity_2[0x4];
8268 u8 reserved_at_38[0x4];
8269 u8 tx_remap_affinity_1[0x4];
8270};
8271
8272struct mlx5_ifc_create_lag_out_bits {
8273 u8 status[0x8];
8274 u8 reserved_at_8[0x18];
8275
8276 u8 syndrome[0x20];
8277
8278 u8 reserved_at_40[0x40];
8279};
8280
8281struct mlx5_ifc_create_lag_in_bits {
8282 u8 opcode[0x10];
8283 u8 reserved_at_10[0x10];
8284
8285 u8 reserved_at_20[0x10];
8286 u8 op_mod[0x10];
8287
8288 struct mlx5_ifc_lagc_bits ctx;
8289};
8290
8291struct mlx5_ifc_modify_lag_out_bits {
8292 u8 status[0x8];
8293 u8 reserved_at_8[0x18];
8294
8295 u8 syndrome[0x20];
8296
8297 u8 reserved_at_40[0x40];
8298};
8299
8300struct mlx5_ifc_modify_lag_in_bits {
8301 u8 opcode[0x10];
8302 u8 reserved_at_10[0x10];
8303
8304 u8 reserved_at_20[0x10];
8305 u8 op_mod[0x10];
8306
8307 u8 reserved_at_40[0x20];
8308 u8 field_select[0x20];
8309
8310 struct mlx5_ifc_lagc_bits ctx;
8311};
8312
8313struct mlx5_ifc_query_lag_out_bits {
8314 u8 status[0x8];
8315 u8 reserved_at_8[0x18];
8316
8317 u8 syndrome[0x20];
8318
8319 u8 reserved_at_40[0x40];
8320
8321 struct mlx5_ifc_lagc_bits ctx;
8322};
8323
8324struct mlx5_ifc_query_lag_in_bits {
8325 u8 opcode[0x10];
8326 u8 reserved_at_10[0x10];
8327
8328 u8 reserved_at_20[0x10];
8329 u8 op_mod[0x10];
8330
8331 u8 reserved_at_40[0x40];
8332};
8333
8334struct mlx5_ifc_destroy_lag_out_bits {
8335 u8 status[0x8];
8336 u8 reserved_at_8[0x18];
8337
8338 u8 syndrome[0x20];
8339
8340 u8 reserved_at_40[0x40];
8341};
8342
8343struct mlx5_ifc_destroy_lag_in_bits {
8344 u8 opcode[0x10];
8345 u8 reserved_at_10[0x10];
8346
8347 u8 reserved_at_20[0x10];
8348 u8 op_mod[0x10];
8349
8350 u8 reserved_at_40[0x40];
8351};
8352
8353struct mlx5_ifc_create_vport_lag_out_bits {
8354 u8 status[0x8];
8355 u8 reserved_at_8[0x18];
8356
8357 u8 syndrome[0x20];
8358
8359 u8 reserved_at_40[0x40];
8360};
8361
8362struct mlx5_ifc_create_vport_lag_in_bits {
8363 u8 opcode[0x10];
8364 u8 reserved_at_10[0x10];
8365
8366 u8 reserved_at_20[0x10];
8367 u8 op_mod[0x10];
8368
8369 u8 reserved_at_40[0x40];
8370};
8371
8372struct mlx5_ifc_destroy_vport_lag_out_bits {
8373 u8 status[0x8];
8374 u8 reserved_at_8[0x18];
8375
8376 u8 syndrome[0x20];
8377
8378 u8 reserved_at_40[0x40];
8379};
8380
8381struct mlx5_ifc_destroy_vport_lag_in_bits {
8382 u8 opcode[0x10];
8383 u8 reserved_at_10[0x10];
8384
8385 u8 reserved_at_20[0x10];
8386 u8 op_mod[0x10];
8387
8388 u8 reserved_at_40[0x40];
8389};
8390
d29b796a 8391#endif /* MLX5_IFC_H */
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