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net/mlx5_core: Enable flow steering support for the IB driver
[mirror_ubuntu-bionic-kernel.git] / include / linux / mlx5 / mlx5_ifc.h
CommitLineData
d29b796a 1/*
e281682b 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
d29b796a
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
e281682b 31*/
d29b796a
EC		 32#ifndef MLX5_IFC_H
33#define MLX5_IFC_H
34
e281682b
SM		 35enum {
36 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
37 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
38 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
39 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
40 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
41 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
42 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
43 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
44 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
45 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
46 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
47 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
48 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
49 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
50 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
51 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
52 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
53 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
54 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
55 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
56 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
57 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
58 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
59 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb
60};
61
62enum {
63 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
64 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
65 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
66 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
67};
68
d29b796a
EC		 69enum {
70 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
71 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
72 MLX5_CMD_OP_INIT_HCA = 0x102,
73 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
74 MLX5_CMD_OP_ENABLE_HCA = 0x104,
75 MLX5_CMD_OP_DISABLE_HCA = 0x105,
76 MLX5_CMD_OP_QUERY_PAGES = 0x107,
77 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
78 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
e281682b
SM		 79 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
80 MLX5_CMD_OP_SET_ISSI = 0x10b,
d29b796a
EC		 81 MLX5_CMD_OP_CREATE_MKEY = 0x200,
82 MLX5_CMD_OP_QUERY_MKEY = 0x201,
83 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
84 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
85 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
86 MLX5_CMD_OP_CREATE_EQ = 0x301,
87 MLX5_CMD_OP_DESTROY_EQ = 0x302,
88 MLX5_CMD_OP_QUERY_EQ = 0x303,
89 MLX5_CMD_OP_GEN_EQE = 0x304,
90 MLX5_CMD_OP_CREATE_CQ = 0x400,
91 MLX5_CMD_OP_DESTROY_CQ = 0x401,
92 MLX5_CMD_OP_QUERY_CQ = 0x402,
93 MLX5_CMD_OP_MODIFY_CQ = 0x403,
94 MLX5_CMD_OP_CREATE_QP = 0x500,
95 MLX5_CMD_OP_DESTROY_QP = 0x501,
96 MLX5_CMD_OP_RST2INIT_QP = 0x502,
97 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
98 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
99 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
100 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
101 MLX5_CMD_OP_2ERR_QP = 0x507,
102 MLX5_CMD_OP_2RST_QP = 0x50a,
103 MLX5_CMD_OP_QUERY_QP = 0x50b,
e281682b 104 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
d29b796a
EC		 105 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
106 MLX5_CMD_OP_CREATE_PSV = 0x600,
107 MLX5_CMD_OP_DESTROY_PSV = 0x601,
108 MLX5_CMD_OP_CREATE_SRQ = 0x700,
109 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
110 MLX5_CMD_OP_QUERY_SRQ = 0x702,
111 MLX5_CMD_OP_ARM_RQ = 0x703,
e281682b
SM		 112 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
113 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
114 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
115 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
d29b796a
EC		 116 MLX5_CMD_OP_CREATE_DCT = 0x710,
117 MLX5_CMD_OP_DESTROY_DCT = 0x711,
118 MLX5_CMD_OP_DRAIN_DCT = 0x712,
119 MLX5_CMD_OP_QUERY_DCT = 0x713,
120 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
121 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
122 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
123 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
124 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
125 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
126 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
e281682b 127 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
d29b796a 128 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
e281682b
SM		 129 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
130 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
131 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
132 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
d29b796a
EC		 133 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
134 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
135 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
136 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
137 MLX5_CMD_OP_ALLOC_PD = 0x800,
138 MLX5_CMD_OP_DEALLOC_PD = 0x801,
139 MLX5_CMD_OP_ALLOC_UAR = 0x802,
140 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
141 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
142 MLX5_CMD_OP_ACCESS_REG = 0x805,
143 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
e281682b 144 MLX5_CMD_OP_DETTACH_FROM_MCG = 0x807,
d29b796a
EC		 145 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
146 MLX5_CMD_OP_MAD_IFC = 0x50d,
147 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
148 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
149 MLX5_CMD_OP_NOP = 0x80d,
150 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
151 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
e281682b
SM		 152 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
153 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
154 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
155 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
156 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
157 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
158 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
159 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
160 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
161 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
162 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
163 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
d29b796a
EC		 164 MLX5_CMD_OP_CREATE_TIR = 0x900,
165 MLX5_CMD_OP_MODIFY_TIR = 0x901,
166 MLX5_CMD_OP_DESTROY_TIR = 0x902,
167 MLX5_CMD_OP_QUERY_TIR = 0x903,
d29b796a
EC		 168 MLX5_CMD_OP_CREATE_SQ = 0x904,
169 MLX5_CMD_OP_MODIFY_SQ = 0x905,
170 MLX5_CMD_OP_DESTROY_SQ = 0x906,
171 MLX5_CMD_OP_QUERY_SQ = 0x907,
172 MLX5_CMD_OP_CREATE_RQ = 0x908,
173 MLX5_CMD_OP_MODIFY_RQ = 0x909,
174 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
175 MLX5_CMD_OP_QUERY_RQ = 0x90b,
176 MLX5_CMD_OP_CREATE_RMP = 0x90c,
177 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
178 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
179 MLX5_CMD_OP_QUERY_RMP = 0x90f,
e281682b
SM		 180 MLX5_CMD_OP_CREATE_TIS = 0x912,
181 MLX5_CMD_OP_MODIFY_TIS = 0x913,
182 MLX5_CMD_OP_DESTROY_TIS = 0x914,
183 MLX5_CMD_OP_QUERY_TIS = 0x915,
184 MLX5_CMD_OP_CREATE_RQT = 0x916,
185 MLX5_CMD_OP_MODIFY_RQT = 0x917,
186 MLX5_CMD_OP_DESTROY_RQT = 0x918,
187 MLX5_CMD_OP_QUERY_RQT = 0x919,
2cc43b49 188 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
e281682b
SM		 189 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
190 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
191 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
192 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
193 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
194 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
195 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
196 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
34a40e68
MG		 197 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
198 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c
e281682b
SM		 199};
200
201struct mlx5_ifc_flow_table_fields_supported_bits {
202 u8 outer_dmac[0x1];
203 u8 outer_smac[0x1];
204 u8 outer_ether_type[0x1];
205 u8 reserved_0[0x1];
206 u8 outer_first_prio[0x1];
207 u8 outer_first_cfi[0x1];
208 u8 outer_first_vid[0x1];
209 u8 reserved_1[0x1];
210 u8 outer_second_prio[0x1];
211 u8 outer_second_cfi[0x1];
212 u8 outer_second_vid[0x1];
213 u8 reserved_2[0x1];
214 u8 outer_sip[0x1];
215 u8 outer_dip[0x1];
216 u8 outer_frag[0x1];
217 u8 outer_ip_protocol[0x1];
218 u8 outer_ip_ecn[0x1];
219 u8 outer_ip_dscp[0x1];
220 u8 outer_udp_sport[0x1];
221 u8 outer_udp_dport[0x1];
222 u8 outer_tcp_sport[0x1];
223 u8 outer_tcp_dport[0x1];
224 u8 outer_tcp_flags[0x1];
225 u8 outer_gre_protocol[0x1];
226 u8 outer_gre_key[0x1];
227 u8 outer_vxlan_vni[0x1];
228 u8 reserved_3[0x5];
229 u8 source_eswitch_port[0x1];
230
231 u8 inner_dmac[0x1];
232 u8 inner_smac[0x1];
233 u8 inner_ether_type[0x1];
234 u8 reserved_4[0x1];
235 u8 inner_first_prio[0x1];
236 u8 inner_first_cfi[0x1];
237 u8 inner_first_vid[0x1];
238 u8 reserved_5[0x1];
239 u8 inner_second_prio[0x1];
240 u8 inner_second_cfi[0x1];
241 u8 inner_second_vid[0x1];
242 u8 reserved_6[0x1];
243 u8 inner_sip[0x1];
244 u8 inner_dip[0x1];
245 u8 inner_frag[0x1];
246 u8 inner_ip_protocol[0x1];
247 u8 inner_ip_ecn[0x1];
248 u8 inner_ip_dscp[0x1];
249 u8 inner_udp_sport[0x1];
250 u8 inner_udp_dport[0x1];
251 u8 inner_tcp_sport[0x1];
252 u8 inner_tcp_dport[0x1];
253 u8 inner_tcp_flags[0x1];
254 u8 reserved_7[0x9];
255
256 u8 reserved_8[0x40];
257};
258
259struct mlx5_ifc_flow_table_prop_layout_bits {
260 u8 ft_support[0x1];
26a81453
MG		 261 u8 reserved_0[0x2];
262 u8 flow_modify_en[0x1];
2cc43b49 263 u8 modify_root[0x1];
34a40e68
MG		 264 u8 identified_miss_table_mode[0x1];
265 u8 flow_table_modify[0x1];
266 u8 reserved_1[0x19];
e281682b 267
26a81453 268 u8 reserved_2[0x2];
e281682b 269 u8 log_max_ft_size[0x6];
26a81453 270 u8 reserved_3[0x10];
e281682b
SM		 271 u8 max_ft_level[0x8];
272
26a81453 273 u8 reserved_4[0x20];
e281682b 274
26a81453 275 u8 reserved_5[0x18];
e281682b
SM		 276 u8 log_max_ft_num[0x8];
277
26a81453 278 u8 reserved_6[0x18];
e281682b
SM		 279 u8 log_max_destination[0x8];
280
26a81453 281 u8 reserved_7[0x18];
e281682b
SM		 282 u8 log_max_flow[0x8];
283
26a81453 284 u8 reserved_8[0x40];
e281682b
SM		 285
286 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
287
288 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
289};
290
291struct mlx5_ifc_odp_per_transport_service_cap_bits {
292 u8 send[0x1];
293 u8 receive[0x1];
294 u8 write[0x1];
295 u8 read[0x1];
296 u8 reserved_0[0x1];
297 u8 srq_receive[0x1];
298 u8 reserved_1[0x1a];
299};
300
301struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
302 u8 smac_47_16[0x20];
303
304 u8 smac_15_0[0x10];
305 u8 ethertype[0x10];
306
307 u8 dmac_47_16[0x20];
308
309 u8 dmac_15_0[0x10];
310 u8 first_prio[0x3];
311 u8 first_cfi[0x1];
312 u8 first_vid[0xc];
313
314 u8 ip_protocol[0x8];
315 u8 ip_dscp[0x6];
316 u8 ip_ecn[0x2];
317 u8 vlan_tag[0x1];
318 u8 reserved_0[0x1];
319 u8 frag[0x1];
320 u8 reserved_1[0x4];
321 u8 tcp_flags[0x9];
322
323 u8 tcp_sport[0x10];
324 u8 tcp_dport[0x10];
325
326 u8 reserved_2[0x20];
327
328 u8 udp_sport[0x10];
329 u8 udp_dport[0x10];
330
331 u8 src_ip[4][0x20];
332
333 u8 dst_ip[4][0x20];
334};
335
336struct mlx5_ifc_fte_match_set_misc_bits {
337 u8 reserved_0[0x20];
338
339 u8 reserved_1[0x10];
340 u8 source_port[0x10];
341
342 u8 outer_second_prio[0x3];
343 u8 outer_second_cfi[0x1];
344 u8 outer_second_vid[0xc];
345 u8 inner_second_prio[0x3];
346 u8 inner_second_cfi[0x1];
347 u8 inner_second_vid[0xc];
348
349 u8 outer_second_vlan_tag[0x1];
350 u8 inner_second_vlan_tag[0x1];
351 u8 reserved_2[0xe];
352 u8 gre_protocol[0x10];
353
354 u8 gre_key_h[0x18];
355 u8 gre_key_l[0x8];
356
357 u8 vxlan_vni[0x18];
358 u8 reserved_3[0x8];
359
360 u8 reserved_4[0x20];
361
362 u8 reserved_5[0xc];
363 u8 outer_ipv6_flow_label[0x14];
364
365 u8 reserved_6[0xc];
366 u8 inner_ipv6_flow_label[0x14];
367
368 u8 reserved_7[0xe0];
369};
370
371struct mlx5_ifc_cmd_pas_bits {
372 u8 pa_h[0x20];
373
374 u8 pa_l[0x14];
375 u8 reserved_0[0xc];
376};
377
378struct mlx5_ifc_uint64_bits {
379 u8 hi[0x20];
380
381 u8 lo[0x20];
382};
383
384enum {
385 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
386 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
387 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
388 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
389 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
390 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
391 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
392 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
393 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
394 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
395};
396
397struct mlx5_ifc_ads_bits {
398 u8 fl[0x1];
399 u8 free_ar[0x1];
400 u8 reserved_0[0xe];
401 u8 pkey_index[0x10];
402
403 u8 reserved_1[0x8];
404 u8 grh[0x1];
405 u8 mlid[0x7];
406 u8 rlid[0x10];
407
408 u8 ack_timeout[0x5];
409 u8 reserved_2[0x3];
410 u8 src_addr_index[0x8];
411 u8 reserved_3[0x4];
412 u8 stat_rate[0x4];
413 u8 hop_limit[0x8];
414
415 u8 reserved_4[0x4];
416 u8 tclass[0x8];
417 u8 flow_label[0x14];
418
419 u8 rgid_rip[16][0x8];
420
421 u8 reserved_5[0x4];
422 u8 f_dscp[0x1];
423 u8 f_ecn[0x1];
424 u8 reserved_6[0x1];
425 u8 f_eth_prio[0x1];
426 u8 ecn[0x2];
427 u8 dscp[0x6];
428 u8 udp_sport[0x10];
429
430 u8 dei_cfi[0x1];
431 u8 eth_prio[0x3];
432 u8 sl[0x4];
433 u8 port[0x8];
434 u8 rmac_47_32[0x10];
435
436 u8 rmac_31_0[0x20];
437};
438
439struct mlx5_ifc_flow_table_nic_cap_bits {
440 u8 reserved_0[0x200];
441
442 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
443
444 u8 reserved_1[0x200];
445
446 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
447
448 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
449
450 u8 reserved_2[0x200];
451
452 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
453
454 u8 reserved_3[0x7200];
455};
456
495716b1
SM		 457struct mlx5_ifc_flow_table_eswitch_cap_bits {
458 u8 reserved_0[0x200];
459
460 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
461
462 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
463
464 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
465
466 u8 reserved_1[0x7800];
467};
468
d6666753
SM		 469struct mlx5_ifc_e_switch_cap_bits {
470 u8 vport_svlan_strip[0x1];
471 u8 vport_cvlan_strip[0x1];
472 u8 vport_svlan_insert[0x1];
473 u8 vport_cvlan_insert_if_not_exist[0x1];
474 u8 vport_cvlan_insert_overwrite[0x1];
475 u8 reserved_0[0x1b];
476
477 u8 reserved_1[0x7e0];
478};
479
e281682b
SM		 480struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
481 u8 csum_cap[0x1];
482 u8 vlan_cap[0x1];
483 u8 lro_cap[0x1];
484 u8 lro_psh_flag[0x1];
485 u8 lro_time_stamp[0x1];
66189961
TT		 486 u8 reserved_0[0x3];
487 u8 self_lb_en_modifiable[0x1];
488 u8 reserved_1[0x2];
e281682b 489 u8 max_lso_cap[0x5];
66189961 490 u8 reserved_2[0x4];
e281682b 491 u8 rss_ind_tbl_cap[0x4];
66189961 492 u8 reserved_3[0x3];
e281682b 493 u8 tunnel_lso_const_out_ip_id[0x1];
66189961 494 u8 reserved_4[0x2];
e281682b
SM		 495 u8 tunnel_statless_gre[0x1];
496 u8 tunnel_stateless_vxlan[0x1];
497
66189961 498 u8 reserved_5[0x20];
e281682b 499
66189961 500 u8 reserved_6[0x10];
e281682b
SM		 501 u8 lro_min_mss_size[0x10];
502
66189961 503 u8 reserved_7[0x120];
e281682b
SM		 504
505 u8 lro_timer_supported_periods[4][0x20];
506
66189961 507 u8 reserved_8[0x600];
e281682b
SM		 508};
509
510struct mlx5_ifc_roce_cap_bits {
511 u8 roce_apm[0x1];
512 u8 reserved_0[0x1f];
513
514 u8 reserved_1[0x60];
515
516 u8 reserved_2[0xc];
517 u8 l3_type[0x4];
518 u8 reserved_3[0x8];
519 u8 roce_version[0x8];
520
521 u8 reserved_4[0x10];
522 u8 r_roce_dest_udp_port[0x10];
523
524 u8 r_roce_max_src_udp_port[0x10];
525 u8 r_roce_min_src_udp_port[0x10];
526
527 u8 reserved_5[0x10];
528 u8 roce_address_table_size[0x10];
529
530 u8 reserved_6[0x700];
531};
532
533enum {
534 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
535 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
536 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
537 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
538 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
539 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
540 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
541 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
542 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
543};
544
545enum {
546 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
547 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
548 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
549 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
550 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
551 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
552 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
553 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
554 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
555};
556
557struct mlx5_ifc_atomic_caps_bits {
558 u8 reserved_0[0x40];
559
560 u8 atomic_req_endianness[0x1];
561 u8 reserved_1[0x1f];
562
563 u8 reserved_2[0x20];
564
565 u8 reserved_3[0x10];
566 u8 atomic_operations[0x10];
567
568 u8 reserved_4[0x10];
569 u8 atomic_size_qp[0x10];
570
571 u8 reserved_5[0x10];
572 u8 atomic_size_dc[0x10];
573
574 u8 reserved_6[0x720];
575};
576
577struct mlx5_ifc_odp_cap_bits {
578 u8 reserved_0[0x40];
579
580 u8 sig[0x1];
581 u8 reserved_1[0x1f];
582
583 u8 reserved_2[0x20];
584
585 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
586
587 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
588
589 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
590
591 u8 reserved_3[0x720];
592};
593
594enum {
595 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
596 MLX5_WQ_TYPE_CYCLIC = 0x1,
597 MLX5_WQ_TYPE_STRQ = 0x2,
598};
599
600enum {
601 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
602 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
603};
604
605enum {
606 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
607 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
608 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
609 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
610 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
611};
612
613enum {
614 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
615 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
616 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
617 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
618 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
619 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
620};
621
622enum {
623 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
624 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
625};
626
627enum {
628 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
629 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
630 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
631};
632
633enum {
634 MLX5_CAP_PORT_TYPE_IB = 0x0,
635 MLX5_CAP_PORT_TYPE_ETH = 0x1,
d29b796a
EC		 636};
637
b775516b
EC		 638struct mlx5_ifc_cmd_hca_cap_bits {
639 u8 reserved_0[0x80];
640
641 u8 log_max_srq_sz[0x8];
642 u8 log_max_qp_sz[0x8];
643 u8 reserved_1[0xb];
644 u8 log_max_qp[0x5];
645
e281682b
SM		 646 u8 reserved_2[0xb];
647 u8 log_max_srq[0x5];
b775516b
EC		 648 u8 reserved_3[0x10];
649
650 u8 reserved_4[0x8];
651 u8 log_max_cq_sz[0x8];
652 u8 reserved_5[0xb];
653 u8 log_max_cq[0x5];
654
655 u8 log_max_eq_sz[0x8];
656 u8 reserved_6[0x2];
657 u8 log_max_mkey[0x6];
658 u8 reserved_7[0xc];
659 u8 log_max_eq[0x4];
660
661 u8 max_indirection[0x8];
662 u8 reserved_8[0x1];
663 u8 log_max_mrw_sz[0x7];
664 u8 reserved_9[0x2];
665 u8 log_max_bsf_list_size[0x6];
666 u8 reserved_10[0x2];
667 u8 log_max_klm_list_size[0x6];
668
669 u8 reserved_11[0xa];
670 u8 log_max_ra_req_dc[0x6];
671 u8 reserved_12[0xa];
672 u8 log_max_ra_res_dc[0x6];
673
674 u8 reserved_13[0xa];
675 u8 log_max_ra_req_qp[0x6];
676 u8 reserved_14[0xa];
677 u8 log_max_ra_res_qp[0x6];
678
679 u8 pad_cap[0x1];
680 u8 cc_query_allowed[0x1];
681 u8 cc_modify_allowed[0x1];
e281682b
SM		 682 u8 reserved_15[0xd];
683 u8 gid_table_size[0x10];
b775516b 684
e281682b
SM		 685 u8 out_of_seq_cnt[0x1];
686 u8 vport_counters[0x1];
687 u8 reserved_16[0x4];
b775516b
EC		 688 u8 max_qp_cnt[0xa];
689 u8 pkey_table_size[0x10];
690
e281682b
SM		 691 u8 vport_group_manager[0x1];
692 u8 vhca_group_manager[0x1];
693 u8 ib_virt[0x1];
694 u8 eth_virt[0x1];
695 u8 reserved_17[0x1];
696 u8 ets[0x1];
697 u8 nic_flow_table[0x1];
54f0a411 698 u8 eswitch_flow_table[0x1];
fc50db98
EC		 699 u8 early_vf_enable;
700 u8 reserved_18[0x2];
b775516b 701 u8 local_ca_ack_delay[0x5];
e281682b
SM		 702 u8 reserved_19[0x6];
703 u8 port_type[0x2];
b775516b
EC		 704 u8 num_ports[0x8];
705
e281682b 706 u8 reserved_20[0x3];
b775516b 707 u8 log_max_msg[0x5];
e281682b 708 u8 reserved_21[0x18];
b775516b
EC		 709
710 u8 stat_rate_support[0x10];
e281682b
SM		 711 u8 reserved_22[0xc];
712 u8 cqe_version[0x4];
b775516b 713
e281682b
SM		 714 u8 compact_address_vector[0x1];
715 u8 reserved_23[0xe];
716 u8 drain_sigerr[0x1];
b775516b
EC		 717 u8 cmdif_checksum[0x2];
718 u8 sigerr_cqe[0x1];
e281682b 719 u8 reserved_24[0x1];
b775516b
EC		 720 u8 wq_signature[0x1];
721 u8 sctr_data_cqe[0x1];
e281682b 722 u8 reserved_25[0x1];
b775516b
EC		 723 u8 sho[0x1];
724 u8 tph[0x1];
725 u8 rf[0x1];
e281682b
SM		 726 u8 dct[0x1];
727 u8 reserved_26[0x1];
728 u8 eth_net_offloads[0x1];
b775516b
EC		 729 u8 roce[0x1];
730 u8 atomic[0x1];
e281682b 731 u8 reserved_27[0x1];
b775516b
EC		 732
733 u8 cq_oi[0x1];
734 u8 cq_resize[0x1];
735 u8 cq_moderation[0x1];
e281682b
SM		 736 u8 reserved_28[0x3];
737 u8 cq_eq_remap[0x1];
b775516b
EC		 738 u8 pg[0x1];
739 u8 block_lb_mc[0x1];
e281682b
SM		 740 u8 reserved_29[0x1];
741 u8 scqe_break_moderation[0x1];
742 u8 reserved_30[0x1];
b775516b 743 u8 cd[0x1];
e281682b 744 u8 reserved_31[0x1];
b775516b 745 u8 apm[0x1];
e281682b 746 u8 reserved_32[0x7];
b775516b
EC		 747 u8 qkv[0x1];
748 u8 pkv[0x1];
e281682b 749 u8 reserved_33[0x4];
b775516b
EC		 750 u8 xrc[0x1];
751 u8 ud[0x1];
752 u8 uc[0x1];
753 u8 rc[0x1];
754
e281682b 755 u8 reserved_34[0xa];
b775516b 756 u8 uar_sz[0x6];
e281682b 757 u8 reserved_35[0x8];
b775516b
EC		 758 u8 log_pg_sz[0x8];
759
760 u8 bf[0x1];
e281682b
SM		 761 u8 reserved_36[0x1];
762 u8 pad_tx_eth_packet[0x1];
763 u8 reserved_37[0x8];
b775516b 764 u8 log_bf_reg_size[0x5];
e281682b 765 u8 reserved_38[0x10];
b775516b 766
e281682b 767 u8 reserved_39[0x10];
b775516b
EC		 768 u8 max_wqe_sz_sq[0x10];
769
e281682b 770 u8 reserved_40[0x10];
b775516b
EC		 771 u8 max_wqe_sz_rq[0x10];
772
e281682b 773 u8 reserved_41[0x10];
b775516b
EC		 774 u8 max_wqe_sz_sq_dc[0x10];
775
e281682b 776 u8 reserved_42[0x7];
b775516b
EC		 777 u8 max_qp_mcg[0x19];
778
e281682b 779 u8 reserved_43[0x18];
b775516b
EC		 780 u8 log_max_mcg[0x8];
781
e281682b
SM		 782 u8 reserved_44[0x3];
783 u8 log_max_transport_domain[0x5];
784 u8 reserved_45[0x3];
b775516b 785 u8 log_max_pd[0x5];
e281682b 786 u8 reserved_46[0xb];
b775516b
EC		 787 u8 log_max_xrcd[0x5];
788
e281682b 789 u8 reserved_47[0x20];
b775516b 790
e281682b 791 u8 reserved_48[0x3];
b775516b 792 u8 log_max_rq[0x5];
e281682b 793 u8 reserved_49[0x3];
b775516b 794 u8 log_max_sq[0x5];
e281682b 795 u8 reserved_50[0x3];
b775516b 796 u8 log_max_tir[0x5];
e281682b 797 u8 reserved_51[0x3];
b775516b
EC		 798 u8 log_max_tis[0x5];
799
e281682b
SM		 800 u8 basic_cyclic_rcv_wqe[0x1];
801 u8 reserved_52[0x2];
802 u8 log_max_rmp[0x5];
803 u8 reserved_53[0x3];
804 u8 log_max_rqt[0x5];
805 u8 reserved_54[0x3];
806 u8 log_max_rqt_size[0x5];
807 u8 reserved_55[0x3];
b775516b
EC		 808 u8 log_max_tis_per_sq[0x5];
809
e281682b
SM		 810 u8 reserved_56[0x3];
811 u8 log_max_stride_sz_rq[0x5];
812 u8 reserved_57[0x3];
813 u8 log_min_stride_sz_rq[0x5];
814 u8 reserved_58[0x3];
815 u8 log_max_stride_sz_sq[0x5];
816 u8 reserved_59[0x3];
817 u8 log_min_stride_sz_sq[0x5];
818
819 u8 reserved_60[0x1b];
820 u8 log_max_wq_sz[0x5];
821
54f0a411
SM		 822 u8 nic_vport_change_event[0x1];
823 u8 reserved_61[0xa];
824 u8 log_max_vlan_list[0x5];
e281682b 825 u8 reserved_62[0x3];
54f0a411
SM		 826 u8 log_max_current_mc_list[0x5];
827 u8 reserved_63[0x3];
828 u8 log_max_current_uc_list[0x5];
829
830 u8 reserved_64[0x80];
831
832 u8 reserved_65[0x3];
e281682b 833 u8 log_max_l2_table[0x5];
54f0a411 834 u8 reserved_66[0x8];
b775516b
EC		 835 u8 log_uar_page_sz[0x10];
836
b0844444
EBE		 837 u8 reserved_67[0x40];
838 u8 device_frequency_khz[0x20];
839 u8 reserved_68[0x5f];
b775516b
EC		 840 u8 cqe_zip[0x1];
841
842 u8 cqe_zip_timeout[0x10];
843 u8 cqe_zip_max_num[0x10];
844
54f0a411 845 u8 reserved_69[0x220];
b775516b
EC		 846};
847
81848731
SM		 848enum mlx5_flow_destination_type {
849 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
850 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
851 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
e281682b 852};
b775516b 853
e281682b
SM		 854struct mlx5_ifc_dest_format_struct_bits {
855 u8 destination_type[0x8];
856 u8 destination_id[0x18];
b775516b 857
e281682b
SM		 858 u8 reserved_0[0x20];
859};
860
861struct mlx5_ifc_fte_match_param_bits {
862 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
863
864 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
865
866 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
b775516b 867
e281682b 868 u8 reserved_0[0xa00];
b775516b
EC		 869};
870
e281682b
SM		 871enum {
872 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
873 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
874 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
875 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
876 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
877};
b775516b 878
e281682b
SM		 879struct mlx5_ifc_rx_hash_field_select_bits {
880 u8 l3_prot_type[0x1];
881 u8 l4_prot_type[0x1];
882 u8 selected_fields[0x1e];
883};
b775516b 884
e281682b
SM		 885enum {
886 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
887 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
b775516b
EC		 888};
889
e281682b
SM		 890enum {
891 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
892 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
893};
894
895struct mlx5_ifc_wq_bits {
896 u8 wq_type[0x4];
897 u8 wq_signature[0x1];
898 u8 end_padding_mode[0x2];
899 u8 cd_slave[0x1];
b775516b
EC		 900 u8 reserved_0[0x18];
901
e281682b
SM		 902 u8 hds_skip_first_sge[0x1];
903 u8 log2_hds_buf_size[0x3];
904 u8 reserved_1[0x7];
905 u8 page_offset[0x5];
906 u8 lwm[0x10];
b775516b 907
e281682b
SM		 908 u8 reserved_2[0x8];
909 u8 pd[0x18];
910
911 u8 reserved_3[0x8];
912 u8 uar_page[0x18];
913
914 u8 dbr_addr[0x40];
915
916 u8 hw_counter[0x20];
917
918 u8 sw_counter[0x20];
919
920 u8 reserved_4[0xc];
921 u8 log_wq_stride[0x4];
922 u8 reserved_5[0x3];
923 u8 log_wq_pg_sz[0x5];
924 u8 reserved_6[0x3];
925 u8 log_wq_sz[0x5];
926
927 u8 reserved_7[0x4e0];
b775516b 928
e281682b 929 struct mlx5_ifc_cmd_pas_bits pas[0];
b775516b
EC		 930};
931
e281682b
SM		 932struct mlx5_ifc_rq_num_bits {
933 u8 reserved_0[0x8];
934 u8 rq_num[0x18];
935};
b775516b 936
e281682b
SM		 937struct mlx5_ifc_mac_address_layout_bits {
938 u8 reserved_0[0x10];
939 u8 mac_addr_47_32[0x10];
b775516b 940
e281682b
SM		 941 u8 mac_addr_31_0[0x20];
942};
943
c0046cf7
SM		 944struct mlx5_ifc_vlan_layout_bits {
945 u8 reserved_0[0x14];
946 u8 vlan[0x0c];
947
948 u8 reserved_1[0x20];
949};
950
e281682b
SM		 951struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
952 u8 reserved_0[0xa0];
953
954 u8 min_time_between_cnps[0x20];
955
956 u8 reserved_1[0x12];
957 u8 cnp_dscp[0x6];
958 u8 reserved_2[0x5];
959 u8 cnp_802p_prio[0x3];
960
961 u8 reserved_3[0x720];
962};
963
964struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
965 u8 reserved_0[0x60];
966
967 u8 reserved_1[0x4];
968 u8 clamp_tgt_rate[0x1];
969 u8 reserved_2[0x3];
970 u8 clamp_tgt_rate_after_time_inc[0x1];
971 u8 reserved_3[0x17];
972
973 u8 reserved_4[0x20];
974
975 u8 rpg_time_reset[0x20];
976
977 u8 rpg_byte_reset[0x20];
978
979 u8 rpg_threshold[0x20];
980
981 u8 rpg_max_rate[0x20];
982
983 u8 rpg_ai_rate[0x20];
984
985 u8 rpg_hai_rate[0x20];
986
987 u8 rpg_gd[0x20];
988
989 u8 rpg_min_dec_fac[0x20];
990
991 u8 rpg_min_rate[0x20];
992
993 u8 reserved_5[0xe0];
994
995 u8 rate_to_set_on_first_cnp[0x20];
996
997 u8 dce_tcp_g[0x20];
998
999 u8 dce_tcp_rtt[0x20];
1000
1001 u8 rate_reduce_monitor_period[0x20];
1002
1003 u8 reserved_6[0x20];
1004
1005 u8 initial_alpha_value[0x20];
1006
1007 u8 reserved_7[0x4a0];
1008};
1009
1010struct mlx5_ifc_cong_control_802_1qau_rp_bits {
1011 u8 reserved_0[0x80];
1012
1013 u8 rppp_max_rps[0x20];
1014
1015 u8 rpg_time_reset[0x20];
1016
1017 u8 rpg_byte_reset[0x20];
1018
1019 u8 rpg_threshold[0x20];
1020
1021 u8 rpg_max_rate[0x20];
1022
1023 u8 rpg_ai_rate[0x20];
1024
1025 u8 rpg_hai_rate[0x20];
1026
1027 u8 rpg_gd[0x20];
1028
1029 u8 rpg_min_dec_fac[0x20];
1030
1031 u8 rpg_min_rate[0x20];
1032
1033 u8 reserved_1[0x640];
1034};
1035
1036enum {
1037 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1038 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1039 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1040};
1041
1042struct mlx5_ifc_resize_field_select_bits {
1043 u8 resize_field_select[0x20];
1044};
1045
1046enum {
1047 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1048 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1049 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1050 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1051};
1052
1053struct mlx5_ifc_modify_field_select_bits {
1054 u8 modify_field_select[0x20];
1055};
1056
1057struct mlx5_ifc_field_select_r_roce_np_bits {
1058 u8 field_select_r_roce_np[0x20];
1059};
1060
1061struct mlx5_ifc_field_select_r_roce_rp_bits {
1062 u8 field_select_r_roce_rp[0x20];
1063};
1064
1065enum {
1066 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1067 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1068 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1069 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1070 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1071 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1072 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1073 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1074 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1075 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1076};
1077
1078struct mlx5_ifc_field_select_802_1qau_rp_bits {
1079 u8 field_select_8021qaurp[0x20];
1080};
1081
1082struct mlx5_ifc_phys_layer_cntrs_bits {
1083 u8 time_since_last_clear_high[0x20];
1084
1085 u8 time_since_last_clear_low[0x20];
1086
1087 u8 symbol_errors_high[0x20];
1088
1089 u8 symbol_errors_low[0x20];
1090
1091 u8 sync_headers_errors_high[0x20];
1092
1093 u8 sync_headers_errors_low[0x20];
1094
1095 u8 edpl_bip_errors_lane0_high[0x20];
1096
1097 u8 edpl_bip_errors_lane0_low[0x20];
1098
1099 u8 edpl_bip_errors_lane1_high[0x20];
1100
1101 u8 edpl_bip_errors_lane1_low[0x20];
1102
1103 u8 edpl_bip_errors_lane2_high[0x20];
1104
1105 u8 edpl_bip_errors_lane2_low[0x20];
1106
1107 u8 edpl_bip_errors_lane3_high[0x20];
1108
1109 u8 edpl_bip_errors_lane3_low[0x20];
1110
1111 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1112
1113 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1114
1115 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1116
1117 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1118
1119 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1120
1121 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1122
1123 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1124
1125 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1126
1127 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1128
1129 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1130
1131 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1132
1133 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1134
1135 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1136
1137 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1138
1139 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1140
1141 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1142
1143 u8 rs_fec_corrected_blocks_high[0x20];
1144
1145 u8 rs_fec_corrected_blocks_low[0x20];
1146
1147 u8 rs_fec_uncorrectable_blocks_high[0x20];
1148
1149 u8 rs_fec_uncorrectable_blocks_low[0x20];
1150
1151 u8 rs_fec_no_errors_blocks_high[0x20];
1152
1153 u8 rs_fec_no_errors_blocks_low[0x20];
1154
1155 u8 rs_fec_single_error_blocks_high[0x20];
1156
1157 u8 rs_fec_single_error_blocks_low[0x20];
1158
1159 u8 rs_fec_corrected_symbols_total_high[0x20];
1160
1161 u8 rs_fec_corrected_symbols_total_low[0x20];
1162
1163 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1164
1165 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1166
1167 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1168
1169 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1170
1171 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1172
1173 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1174
1175 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1176
1177 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1178
1179 u8 link_down_events[0x20];
1180
1181 u8 successful_recovery_events[0x20];
1182
1183 u8 reserved_0[0x180];
1184};
1185
1186struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1187 u8 transmit_queue_high[0x20];
1188
1189 u8 transmit_queue_low[0x20];
1190
1191 u8 reserved_0[0x780];
1192};
1193
1194struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1195 u8 rx_octets_high[0x20];
1196
1197 u8 rx_octets_low[0x20];
1198
1199 u8 reserved_0[0xc0];
1200
1201 u8 rx_frames_high[0x20];
1202
1203 u8 rx_frames_low[0x20];
1204
1205 u8 tx_octets_high[0x20];
1206
1207 u8 tx_octets_low[0x20];
1208
1209 u8 reserved_1[0xc0];
1210
1211 u8 tx_frames_high[0x20];
1212
1213 u8 tx_frames_low[0x20];
1214
1215 u8 rx_pause_high[0x20];
1216
1217 u8 rx_pause_low[0x20];
1218
1219 u8 rx_pause_duration_high[0x20];
1220
1221 u8 rx_pause_duration_low[0x20];
1222
1223 u8 tx_pause_high[0x20];
1224
1225 u8 tx_pause_low[0x20];
1226
1227 u8 tx_pause_duration_high[0x20];
1228
1229 u8 tx_pause_duration_low[0x20];
1230
1231 u8 rx_pause_transition_high[0x20];
1232
1233 u8 rx_pause_transition_low[0x20];
1234
1235 u8 reserved_2[0x400];
1236};
1237
1238struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1239 u8 port_transmit_wait_high[0x20];
1240
1241 u8 port_transmit_wait_low[0x20];
1242
1243 u8 reserved_0[0x780];
1244};
1245
1246struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1247 u8 dot3stats_alignment_errors_high[0x20];
1248
1249 u8 dot3stats_alignment_errors_low[0x20];
1250
1251 u8 dot3stats_fcs_errors_high[0x20];
1252
1253 u8 dot3stats_fcs_errors_low[0x20];
1254
1255 u8 dot3stats_single_collision_frames_high[0x20];
1256
1257 u8 dot3stats_single_collision_frames_low[0x20];
1258
1259 u8 dot3stats_multiple_collision_frames_high[0x20];
1260
1261 u8 dot3stats_multiple_collision_frames_low[0x20];
1262
1263 u8 dot3stats_sqe_test_errors_high[0x20];
1264
1265 u8 dot3stats_sqe_test_errors_low[0x20];
1266
1267 u8 dot3stats_deferred_transmissions_high[0x20];
1268
1269 u8 dot3stats_deferred_transmissions_low[0x20];
1270
1271 u8 dot3stats_late_collisions_high[0x20];
1272
1273 u8 dot3stats_late_collisions_low[0x20];
1274
1275 u8 dot3stats_excessive_collisions_high[0x20];
1276
1277 u8 dot3stats_excessive_collisions_low[0x20];
1278
1279 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1280
1281 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1282
1283 u8 dot3stats_carrier_sense_errors_high[0x20];
1284
1285 u8 dot3stats_carrier_sense_errors_low[0x20];
1286
1287 u8 dot3stats_frame_too_longs_high[0x20];
1288
1289 u8 dot3stats_frame_too_longs_low[0x20];
1290
1291 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1292
1293 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1294
1295 u8 dot3stats_symbol_errors_high[0x20];
1296
1297 u8 dot3stats_symbol_errors_low[0x20];
1298
1299 u8 dot3control_in_unknown_opcodes_high[0x20];
1300
1301 u8 dot3control_in_unknown_opcodes_low[0x20];
1302
1303 u8 dot3in_pause_frames_high[0x20];
1304
1305 u8 dot3in_pause_frames_low[0x20];
1306
1307 u8 dot3out_pause_frames_high[0x20];
1308
1309 u8 dot3out_pause_frames_low[0x20];
1310
1311 u8 reserved_0[0x3c0];
1312};
1313
1314struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1315 u8 ether_stats_drop_events_high[0x20];
1316
1317 u8 ether_stats_drop_events_low[0x20];
1318
1319 u8 ether_stats_octets_high[0x20];
1320
1321 u8 ether_stats_octets_low[0x20];
1322
1323 u8 ether_stats_pkts_high[0x20];
1324
1325 u8 ether_stats_pkts_low[0x20];
1326
1327 u8 ether_stats_broadcast_pkts_high[0x20];
1328
1329 u8 ether_stats_broadcast_pkts_low[0x20];
1330
1331 u8 ether_stats_multicast_pkts_high[0x20];
1332
1333 u8 ether_stats_multicast_pkts_low[0x20];
1334
1335 u8 ether_stats_crc_align_errors_high[0x20];
1336
1337 u8 ether_stats_crc_align_errors_low[0x20];
1338
1339 u8 ether_stats_undersize_pkts_high[0x20];
1340
1341 u8 ether_stats_undersize_pkts_low[0x20];
1342
1343 u8 ether_stats_oversize_pkts_high[0x20];
1344
1345 u8 ether_stats_oversize_pkts_low[0x20];
1346
1347 u8 ether_stats_fragments_high[0x20];
1348
1349 u8 ether_stats_fragments_low[0x20];
1350
1351 u8 ether_stats_jabbers_high[0x20];
1352
1353 u8 ether_stats_jabbers_low[0x20];
1354
1355 u8 ether_stats_collisions_high[0x20];
1356
1357 u8 ether_stats_collisions_low[0x20];
1358
1359 u8 ether_stats_pkts64octets_high[0x20];
1360
1361 u8 ether_stats_pkts64octets_low[0x20];
1362
1363 u8 ether_stats_pkts65to127octets_high[0x20];
1364
1365 u8 ether_stats_pkts65to127octets_low[0x20];
1366
1367 u8 ether_stats_pkts128to255octets_high[0x20];
1368
1369 u8 ether_stats_pkts128to255octets_low[0x20];
1370
1371 u8 ether_stats_pkts256to511octets_high[0x20];
1372
1373 u8 ether_stats_pkts256to511octets_low[0x20];
1374
1375 u8 ether_stats_pkts512to1023octets_high[0x20];
1376
1377 u8 ether_stats_pkts512to1023octets_low[0x20];
1378
1379 u8 ether_stats_pkts1024to1518octets_high[0x20];
1380
1381 u8 ether_stats_pkts1024to1518octets_low[0x20];
1382
1383 u8 ether_stats_pkts1519to2047octets_high[0x20];
1384
1385 u8 ether_stats_pkts1519to2047octets_low[0x20];
1386
1387 u8 ether_stats_pkts2048to4095octets_high[0x20];
1388
1389 u8 ether_stats_pkts2048to4095octets_low[0x20];
1390
1391 u8 ether_stats_pkts4096to8191octets_high[0x20];
1392
1393 u8 ether_stats_pkts4096to8191octets_low[0x20];
1394
1395 u8 ether_stats_pkts8192to10239octets_high[0x20];
1396
1397 u8 ether_stats_pkts8192to10239octets_low[0x20];
1398
1399 u8 reserved_0[0x280];
1400};
1401
1402struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1403 u8 if_in_octets_high[0x20];
1404
1405 u8 if_in_octets_low[0x20];
1406
1407 u8 if_in_ucast_pkts_high[0x20];
1408
1409 u8 if_in_ucast_pkts_low[0x20];
1410
1411 u8 if_in_discards_high[0x20];
1412
1413 u8 if_in_discards_low[0x20];
1414
1415 u8 if_in_errors_high[0x20];
1416
1417 u8 if_in_errors_low[0x20];
1418
1419 u8 if_in_unknown_protos_high[0x20];
1420
1421 u8 if_in_unknown_protos_low[0x20];
1422
1423 u8 if_out_octets_high[0x20];
1424
1425 u8 if_out_octets_low[0x20];
1426
1427 u8 if_out_ucast_pkts_high[0x20];
1428
1429 u8 if_out_ucast_pkts_low[0x20];
1430
1431 u8 if_out_discards_high[0x20];
1432
1433 u8 if_out_discards_low[0x20];
1434
1435 u8 if_out_errors_high[0x20];
1436
1437 u8 if_out_errors_low[0x20];
1438
1439 u8 if_in_multicast_pkts_high[0x20];
1440
1441 u8 if_in_multicast_pkts_low[0x20];
1442
1443 u8 if_in_broadcast_pkts_high[0x20];
1444
1445 u8 if_in_broadcast_pkts_low[0x20];
1446
1447 u8 if_out_multicast_pkts_high[0x20];
1448
1449 u8 if_out_multicast_pkts_low[0x20];
1450
1451 u8 if_out_broadcast_pkts_high[0x20];
1452
1453 u8 if_out_broadcast_pkts_low[0x20];
1454
1455 u8 reserved_0[0x480];
1456};
1457
1458struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1459 u8 a_frames_transmitted_ok_high[0x20];
1460
1461 u8 a_frames_transmitted_ok_low[0x20];
1462
1463 u8 a_frames_received_ok_high[0x20];
1464
1465 u8 a_frames_received_ok_low[0x20];
1466
1467 u8 a_frame_check_sequence_errors_high[0x20];
1468
1469 u8 a_frame_check_sequence_errors_low[0x20];
1470
1471 u8 a_alignment_errors_high[0x20];
1472
1473 u8 a_alignment_errors_low[0x20];
1474
1475 u8 a_octets_transmitted_ok_high[0x20];
1476
1477 u8 a_octets_transmitted_ok_low[0x20];
1478
1479 u8 a_octets_received_ok_high[0x20];
1480
1481 u8 a_octets_received_ok_low[0x20];
1482
1483 u8 a_multicast_frames_xmitted_ok_high[0x20];
1484
1485 u8 a_multicast_frames_xmitted_ok_low[0x20];
1486
1487 u8 a_broadcast_frames_xmitted_ok_high[0x20];
1488
1489 u8 a_broadcast_frames_xmitted_ok_low[0x20];
1490
1491 u8 a_multicast_frames_received_ok_high[0x20];
1492
1493 u8 a_multicast_frames_received_ok_low[0x20];
1494
1495 u8 a_broadcast_frames_received_ok_high[0x20];
1496
1497 u8 a_broadcast_frames_received_ok_low[0x20];
1498
1499 u8 a_in_range_length_errors_high[0x20];
1500
1501 u8 a_in_range_length_errors_low[0x20];
1502
1503 u8 a_out_of_range_length_field_high[0x20];
1504
1505 u8 a_out_of_range_length_field_low[0x20];
1506
1507 u8 a_frame_too_long_errors_high[0x20];
1508
1509 u8 a_frame_too_long_errors_low[0x20];
1510
1511 u8 a_symbol_error_during_carrier_high[0x20];
1512
1513 u8 a_symbol_error_during_carrier_low[0x20];
1514
1515 u8 a_mac_control_frames_transmitted_high[0x20];
1516
1517 u8 a_mac_control_frames_transmitted_low[0x20];
1518
1519 u8 a_mac_control_frames_received_high[0x20];
1520
1521 u8 a_mac_control_frames_received_low[0x20];
1522
1523 u8 a_unsupported_opcodes_received_high[0x20];
1524
1525 u8 a_unsupported_opcodes_received_low[0x20];
1526
1527 u8 a_pause_mac_ctrl_frames_received_high[0x20];
1528
1529 u8 a_pause_mac_ctrl_frames_received_low[0x20];
1530
1531 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
1532
1533 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
1534
1535 u8 reserved_0[0x300];
1536};
1537
1538struct mlx5_ifc_cmd_inter_comp_event_bits {
1539 u8 command_completion_vector[0x20];
1540
1541 u8 reserved_0[0xc0];
1542};
1543
1544struct mlx5_ifc_stall_vl_event_bits {
1545 u8 reserved_0[0x18];
1546 u8 port_num[0x1];
1547 u8 reserved_1[0x3];
1548 u8 vl[0x4];
1549
1550 u8 reserved_2[0xa0];
1551};
1552
1553struct mlx5_ifc_db_bf_congestion_event_bits {
1554 u8 event_subtype[0x8];
1555 u8 reserved_0[0x8];
1556 u8 congestion_level[0x8];
1557 u8 reserved_1[0x8];
1558
1559 u8 reserved_2[0xa0];
1560};
1561
1562struct mlx5_ifc_gpio_event_bits {
1563 u8 reserved_0[0x60];
1564
1565 u8 gpio_event_hi[0x20];
1566
1567 u8 gpio_event_lo[0x20];
1568
1569 u8 reserved_1[0x40];
1570};
1571
1572struct mlx5_ifc_port_state_change_event_bits {
1573 u8 reserved_0[0x40];
1574
1575 u8 port_num[0x4];
1576 u8 reserved_1[0x1c];
1577
1578 u8 reserved_2[0x80];
1579};
1580
1581struct mlx5_ifc_dropped_packet_logged_bits {
1582 u8 reserved_0[0xe0];
1583};
1584
1585enum {
1586 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
1587 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
1588};
1589
1590struct mlx5_ifc_cq_error_bits {
1591 u8 reserved_0[0x8];
1592 u8 cqn[0x18];
1593
1594 u8 reserved_1[0x20];
1595
1596 u8 reserved_2[0x18];
1597 u8 syndrome[0x8];
1598
1599 u8 reserved_3[0x80];
1600};
1601
1602struct mlx5_ifc_rdma_page_fault_event_bits {
1603 u8 bytes_committed[0x20];
1604
1605 u8 r_key[0x20];
1606
1607 u8 reserved_0[0x10];
1608 u8 packet_len[0x10];
1609
1610 u8 rdma_op_len[0x20];
1611
1612 u8 rdma_va[0x40];
1613
1614 u8 reserved_1[0x5];
1615 u8 rdma[0x1];
1616 u8 write[0x1];
1617 u8 requestor[0x1];
1618 u8 qp_number[0x18];
1619};
1620
1621struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1622 u8 bytes_committed[0x20];
1623
1624 u8 reserved_0[0x10];
1625 u8 wqe_index[0x10];
1626
1627 u8 reserved_1[0x10];
1628 u8 len[0x10];
1629
1630 u8 reserved_2[0x60];
1631
1632 u8 reserved_3[0x5];
1633 u8 rdma[0x1];
1634 u8 write_read[0x1];
1635 u8 requestor[0x1];
1636 u8 qpn[0x18];
1637};
1638
1639struct mlx5_ifc_qp_events_bits {
1640 u8 reserved_0[0xa0];
1641
1642 u8 type[0x8];
1643 u8 reserved_1[0x18];
1644
1645 u8 reserved_2[0x8];
1646 u8 qpn_rqn_sqn[0x18];
1647};
1648
1649struct mlx5_ifc_dct_events_bits {
1650 u8 reserved_0[0xc0];
1651
1652 u8 reserved_1[0x8];
1653 u8 dct_number[0x18];
1654};
1655
1656struct mlx5_ifc_comp_event_bits {
1657 u8 reserved_0[0xc0];
1658
1659 u8 reserved_1[0x8];
1660 u8 cq_number[0x18];
1661};
1662
1663enum {
1664 MLX5_QPC_STATE_RST = 0x0,
1665 MLX5_QPC_STATE_INIT = 0x1,
1666 MLX5_QPC_STATE_RTR = 0x2,
1667 MLX5_QPC_STATE_RTS = 0x3,
1668 MLX5_QPC_STATE_SQER = 0x4,
1669 MLX5_QPC_STATE_ERR = 0x6,
1670 MLX5_QPC_STATE_SQD = 0x7,
1671 MLX5_QPC_STATE_SUSPENDED = 0x9,
1672};
1673
1674enum {
1675 MLX5_QPC_ST_RC = 0x0,
1676 MLX5_QPC_ST_UC = 0x1,
1677 MLX5_QPC_ST_UD = 0x2,
1678 MLX5_QPC_ST_XRC = 0x3,
1679 MLX5_QPC_ST_DCI = 0x5,
1680 MLX5_QPC_ST_QP0 = 0x7,
1681 MLX5_QPC_ST_QP1 = 0x8,
1682 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
1683 MLX5_QPC_ST_REG_UMR = 0xc,
1684};
1685
1686enum {
1687 MLX5_QPC_PM_STATE_ARMED = 0x0,
1688 MLX5_QPC_PM_STATE_REARM = 0x1,
1689 MLX5_QPC_PM_STATE_RESERVED = 0x2,
1690 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
1691};
1692
1693enum {
1694 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
1695 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
1696};
1697
1698enum {
1699 MLX5_QPC_MTU_256_BYTES = 0x1,
1700 MLX5_QPC_MTU_512_BYTES = 0x2,
1701 MLX5_QPC_MTU_1K_BYTES = 0x3,
1702 MLX5_QPC_MTU_2K_BYTES = 0x4,
1703 MLX5_QPC_MTU_4K_BYTES = 0x5,
1704 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
1705};
1706
1707enum {
1708 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
1709 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
1710 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
1711 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
1712 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
1713 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
1714 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
1715 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
1716};
1717
1718enum {
1719 MLX5_QPC_CS_REQ_DISABLE = 0x0,
1720 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
1721 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
1722};
1723
1724enum {
1725 MLX5_QPC_CS_RES_DISABLE = 0x0,
1726 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
1727 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
1728};
1729
1730struct mlx5_ifc_qpc_bits {
1731 u8 state[0x4];
1732 u8 reserved_0[0x4];
1733 u8 st[0x8];
1734 u8 reserved_1[0x3];
1735 u8 pm_state[0x2];
1736 u8 reserved_2[0x7];
1737 u8 end_padding_mode[0x2];
1738 u8 reserved_3[0x2];
1739
1740 u8 wq_signature[0x1];
1741 u8 block_lb_mc[0x1];
1742 u8 atomic_like_write_en[0x1];
1743 u8 latency_sensitive[0x1];
1744 u8 reserved_4[0x1];
1745 u8 drain_sigerr[0x1];
1746 u8 reserved_5[0x2];
1747 u8 pd[0x18];
1748
1749 u8 mtu[0x3];
1750 u8 log_msg_max[0x5];
1751 u8 reserved_6[0x1];
1752 u8 log_rq_size[0x4];
1753 u8 log_rq_stride[0x3];
1754 u8 no_sq[0x1];
1755 u8 log_sq_size[0x4];
1756 u8 reserved_7[0x6];
1757 u8 rlky[0x1];
1758 u8 reserved_8[0x4];
1759
1760 u8 counter_set_id[0x8];
1761 u8 uar_page[0x18];
1762
1763 u8 reserved_9[0x8];
1764 u8 user_index[0x18];
1765
1766 u8 reserved_10[0x3];
1767 u8 log_page_size[0x5];
1768 u8 remote_qpn[0x18];
1769
1770 struct mlx5_ifc_ads_bits primary_address_path;
1771
1772 struct mlx5_ifc_ads_bits secondary_address_path;
1773
1774 u8 log_ack_req_freq[0x4];
1775 u8 reserved_11[0x4];
1776 u8 log_sra_max[0x3];
1777 u8 reserved_12[0x2];
1778 u8 retry_count[0x3];
1779 u8 rnr_retry[0x3];
1780 u8 reserved_13[0x1];
1781 u8 fre[0x1];
1782 u8 cur_rnr_retry[0x3];
1783 u8 cur_retry_count[0x3];
1784 u8 reserved_14[0x5];
1785
1786 u8 reserved_15[0x20];
1787
1788 u8 reserved_16[0x8];
1789 u8 next_send_psn[0x18];
1790
1791 u8 reserved_17[0x8];
1792 u8 cqn_snd[0x18];
1793
1794 u8 reserved_18[0x40];
1795
1796 u8 reserved_19[0x8];
1797 u8 last_acked_psn[0x18];
1798
1799 u8 reserved_20[0x8];
1800 u8 ssn[0x18];
1801
1802 u8 reserved_21[0x8];
1803 u8 log_rra_max[0x3];
1804 u8 reserved_22[0x1];
1805 u8 atomic_mode[0x4];
1806 u8 rre[0x1];
1807 u8 rwe[0x1];
1808 u8 rae[0x1];
1809 u8 reserved_23[0x1];
1810 u8 page_offset[0x6];
1811 u8 reserved_24[0x3];
1812 u8 cd_slave_receive[0x1];
1813 u8 cd_slave_send[0x1];
1814 u8 cd_master[0x1];
1815
1816 u8 reserved_25[0x3];
1817 u8 min_rnr_nak[0x5];
1818 u8 next_rcv_psn[0x18];
1819
1820 u8 reserved_26[0x8];
1821 u8 xrcd[0x18];
1822
1823 u8 reserved_27[0x8];
1824 u8 cqn_rcv[0x18];
1825
1826 u8 dbr_addr[0x40];
1827
1828 u8 q_key[0x20];
1829
1830 u8 reserved_28[0x5];
1831 u8 rq_type[0x3];
1832 u8 srqn_rmpn[0x18];
1833
1834 u8 reserved_29[0x8];
1835 u8 rmsn[0x18];
1836
1837 u8 hw_sq_wqebb_counter[0x10];
1838 u8 sw_sq_wqebb_counter[0x10];
1839
1840 u8 hw_rq_counter[0x20];
1841
1842 u8 sw_rq_counter[0x20];
1843
1844 u8 reserved_30[0x20];
1845
1846 u8 reserved_31[0xf];
1847 u8 cgs[0x1];
1848 u8 cs_req[0x8];
1849 u8 cs_res[0x8];
1850
1851 u8 dc_access_key[0x40];
1852
1853 u8 reserved_32[0xc0];
1854};
1855
1856struct mlx5_ifc_roce_addr_layout_bits {
1857 u8 source_l3_address[16][0x8];
1858
1859 u8 reserved_0[0x3];
1860 u8 vlan_valid[0x1];
1861 u8 vlan_id[0xc];
1862 u8 source_mac_47_32[0x10];
1863
1864 u8 source_mac_31_0[0x20];
1865
1866 u8 reserved_1[0x14];
1867 u8 roce_l3_type[0x4];
1868 u8 roce_version[0x8];
1869
1870 u8 reserved_2[0x20];
1871};
1872
1873union mlx5_ifc_hca_cap_union_bits {
1874 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
1875 struct mlx5_ifc_odp_cap_bits odp_cap;
1876 struct mlx5_ifc_atomic_caps_bits atomic_caps;
1877 struct mlx5_ifc_roce_cap_bits roce_cap;
1878 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
1879 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
495716b1 1880 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
d6666753 1881 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
e281682b
SM		 1882 u8 reserved_0[0x8000];
1883};
1884
1885enum {
1886 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
1887 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
1888 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
1889};
1890
1891struct mlx5_ifc_flow_context_bits {
1892 u8 reserved_0[0x20];
1893
1894 u8 group_id[0x20];
1895
1896 u8 reserved_1[0x8];
1897 u8 flow_tag[0x18];
1898
1899 u8 reserved_2[0x10];
1900 u8 action[0x10];
1901
1902 u8 reserved_3[0x8];
1903 u8 destination_list_size[0x18];
1904
1905 u8 reserved_4[0x160];
1906
1907 struct mlx5_ifc_fte_match_param_bits match_value;
1908
1909 u8 reserved_5[0x600];
1910
1911 struct mlx5_ifc_dest_format_struct_bits destination[0];
1912};
1913
1914enum {
1915 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
1916 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
1917};
1918
1919struct mlx5_ifc_xrc_srqc_bits {
1920 u8 state[0x4];
1921 u8 log_xrc_srq_size[0x4];
1922 u8 reserved_0[0x18];
1923
1924 u8 wq_signature[0x1];
1925 u8 cont_srq[0x1];
1926 u8 reserved_1[0x1];
1927 u8 rlky[0x1];
1928 u8 basic_cyclic_rcv_wqe[0x1];
1929 u8 log_rq_stride[0x3];
1930 u8 xrcd[0x18];
1931
1932 u8 page_offset[0x6];
1933 u8 reserved_2[0x2];
1934 u8 cqn[0x18];
1935
1936 u8 reserved_3[0x20];
1937
1938 u8 user_index_equal_xrc_srqn[0x1];
1939 u8 reserved_4[0x1];
1940 u8 log_page_size[0x6];
1941 u8 user_index[0x18];
1942
1943 u8 reserved_5[0x20];
1944
1945 u8 reserved_6[0x8];
1946 u8 pd[0x18];
1947
1948 u8 lwm[0x10];
1949 u8 wqe_cnt[0x10];
1950
1951 u8 reserved_7[0x40];
1952
1953 u8 db_record_addr_h[0x20];
1954
1955 u8 db_record_addr_l[0x1e];
1956 u8 reserved_8[0x2];
1957
1958 u8 reserved_9[0x80];
1959};
1960
1961struct mlx5_ifc_traffic_counter_bits {
1962 u8 packets[0x40];
1963
1964 u8 octets[0x40];
1965};
1966
1967struct mlx5_ifc_tisc_bits {
1968 u8 reserved_0[0xc];
1969 u8 prio[0x4];
1970 u8 reserved_1[0x10];
1971
1972 u8 reserved_2[0x100];
1973
1974 u8 reserved_3[0x8];
1975 u8 transport_domain[0x18];
1976
1977 u8 reserved_4[0x3c0];
1978};
1979
1980enum {
1981 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
1982 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
1983};
1984
1985enum {
1986 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
1987 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
1988};
1989
1990enum {
2be6967c
SM		 1991 MLX5_RX_HASH_FN_NONE = 0x0,
1992 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
1993 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
e281682b
SM		 1994};
1995
1996enum {
1997 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1,
1998 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2,
1999};
2000
2001struct mlx5_ifc_tirc_bits {
2002 u8 reserved_0[0x20];
2003
2004 u8 disp_type[0x4];
2005 u8 reserved_1[0x1c];
2006
2007 u8 reserved_2[0x40];
2008
2009 u8 reserved_3[0x4];
2010 u8 lro_timeout_period_usecs[0x10];
2011 u8 lro_enable_mask[0x4];
2012 u8 lro_max_ip_payload_size[0x8];
2013
2014 u8 reserved_4[0x40];
2015
2016 u8 reserved_5[0x8];
2017 u8 inline_rqn[0x18];
2018
2019 u8 rx_hash_symmetric[0x1];
2020 u8 reserved_6[0x1];
2021 u8 tunneled_offload_en[0x1];
2022 u8 reserved_7[0x5];
2023 u8 indirect_table[0x18];
2024
2025 u8 rx_hash_fn[0x4];
2026 u8 reserved_8[0x2];
2027 u8 self_lb_block[0x2];
2028 u8 transport_domain[0x18];
2029
2030 u8 rx_hash_toeplitz_key[10][0x20];
2031
2032 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2033
2034 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2035
2036 u8 reserved_9[0x4c0];
2037};
2038
2039enum {
2040 MLX5_SRQC_STATE_GOOD = 0x0,
2041 MLX5_SRQC_STATE_ERROR = 0x1,
2042};
2043
2044struct mlx5_ifc_srqc_bits {
2045 u8 state[0x4];
2046 u8 log_srq_size[0x4];
2047 u8 reserved_0[0x18];
2048
2049 u8 wq_signature[0x1];
2050 u8 cont_srq[0x1];
2051 u8 reserved_1[0x1];
2052 u8 rlky[0x1];
2053 u8 reserved_2[0x1];
2054 u8 log_rq_stride[0x3];
2055 u8 xrcd[0x18];
2056
2057 u8 page_offset[0x6];
2058 u8 reserved_3[0x2];
2059 u8 cqn[0x18];
2060
2061 u8 reserved_4[0x20];
2062
2063 u8 reserved_5[0x2];
2064 u8 log_page_size[0x6];
2065 u8 reserved_6[0x18];
2066
2067 u8 reserved_7[0x20];
2068
2069 u8 reserved_8[0x8];
2070 u8 pd[0x18];
2071
2072 u8 lwm[0x10];
2073 u8 wqe_cnt[0x10];
2074
2075 u8 reserved_9[0x40];
2076
01949d01 2077 u8 dbr_addr[0x40];
e281682b 2078
01949d01 2079 u8 reserved_10[0x80];
e281682b
SM		 2080};
2081
2082enum {
2083 MLX5_SQC_STATE_RST = 0x0,
2084 MLX5_SQC_STATE_RDY = 0x1,
2085 MLX5_SQC_STATE_ERR = 0x3,
2086};
2087
2088struct mlx5_ifc_sqc_bits {
2089 u8 rlky[0x1];
2090 u8 cd_master[0x1];
2091 u8 fre[0x1];
2092 u8 flush_in_error_en[0x1];
2093 u8 reserved_0[0x4];
2094 u8 state[0x4];
2095 u8 reserved_1[0x14];
2096
2097 u8 reserved_2[0x8];
2098 u8 user_index[0x18];
2099
2100 u8 reserved_3[0x8];
2101 u8 cqn[0x18];
2102
2103 u8 reserved_4[0xa0];
2104
2105 u8 tis_lst_sz[0x10];
2106 u8 reserved_5[0x10];
2107
2108 u8 reserved_6[0x40];
2109
2110 u8 reserved_7[0x8];
2111 u8 tis_num_0[0x18];
2112
2113 struct mlx5_ifc_wq_bits wq;
2114};
2115
2116struct mlx5_ifc_rqtc_bits {
2117 u8 reserved_0[0xa0];
2118
2119 u8 reserved_1[0x10];
2120 u8 rqt_max_size[0x10];
2121
2122 u8 reserved_2[0x10];
2123 u8 rqt_actual_size[0x10];
2124
2125 u8 reserved_3[0x6a0];
2126
2127 struct mlx5_ifc_rq_num_bits rq_num[0];
2128};
2129
2130enum {
2131 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2132 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2133};
2134
2135enum {
2136 MLX5_RQC_STATE_RST = 0x0,
2137 MLX5_RQC_STATE_RDY = 0x1,
2138 MLX5_RQC_STATE_ERR = 0x3,
2139};
2140
2141struct mlx5_ifc_rqc_bits {
2142 u8 rlky[0x1];
2143 u8 reserved_0[0x2];
2144 u8 vsd[0x1];
2145 u8 mem_rq_type[0x4];
2146 u8 state[0x4];
2147 u8 reserved_1[0x1];
2148 u8 flush_in_error_en[0x1];
2149 u8 reserved_2[0x12];
2150
2151 u8 reserved_3[0x8];
2152 u8 user_index[0x18];
2153
2154 u8 reserved_4[0x8];
2155 u8 cqn[0x18];
2156
2157 u8 counter_set_id[0x8];
2158 u8 reserved_5[0x18];
2159
2160 u8 reserved_6[0x8];
2161 u8 rmpn[0x18];
2162
2163 u8 reserved_7[0xe0];
2164
2165 struct mlx5_ifc_wq_bits wq;
2166};
2167
2168enum {
2169 MLX5_RMPC_STATE_RDY = 0x1,
2170 MLX5_RMPC_STATE_ERR = 0x3,
2171};
2172
2173struct mlx5_ifc_rmpc_bits {
2174 u8 reserved_0[0x8];
2175 u8 state[0x4];
2176 u8 reserved_1[0x14];
2177
2178 u8 basic_cyclic_rcv_wqe[0x1];
2179 u8 reserved_2[0x1f];
2180
2181 u8 reserved_3[0x140];
2182
2183 struct mlx5_ifc_wq_bits wq;
2184};
2185
e281682b
SM		 2186struct mlx5_ifc_nic_vport_context_bits {
2187 u8 reserved_0[0x1f];
2188 u8 roce_en[0x1];
2189
d82b7318
SM		 2190 u8 arm_change_event[0x1];
2191 u8 reserved_1[0x1a];
2192 u8 event_on_mtu[0x1];
2193 u8 event_on_promisc_change[0x1];
2194 u8 event_on_vlan_change[0x1];
2195 u8 event_on_mc_address_change[0x1];
2196 u8 event_on_uc_address_change[0x1];
e281682b 2197
d82b7318
SM		 2198 u8 reserved_2[0xf0];
2199
2200 u8 mtu[0x10];
2201
2202 u8 reserved_3[0x640];
2203
2204 u8 promisc_uc[0x1];
2205 u8 promisc_mc[0x1];
2206 u8 promisc_all[0x1];
2207 u8 reserved_4[0x2];
e281682b 2208 u8 allowed_list_type[0x3];
d82b7318 2209 u8 reserved_5[0xc];
e281682b
SM		 2210 u8 allowed_list_size[0xc];
2211
2212 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2213
d82b7318 2214 u8 reserved_6[0x20];
e281682b
SM		 2215
2216 u8 current_uc_mac_address[0][0x40];
2217};
2218
2219enum {
2220 MLX5_MKC_ACCESS_MODE_PA = 0x0,
2221 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
2222 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
2223};
2224
2225struct mlx5_ifc_mkc_bits {
2226 u8 reserved_0[0x1];
2227 u8 free[0x1];
2228 u8 reserved_1[0xd];
2229 u8 small_fence_on_rdma_read_response[0x1];
2230 u8 umr_en[0x1];
2231 u8 a[0x1];
2232 u8 rw[0x1];
2233 u8 rr[0x1];
2234 u8 lw[0x1];
2235 u8 lr[0x1];
2236 u8 access_mode[0x2];
2237 u8 reserved_2[0x8];
2238
2239 u8 qpn[0x18];
2240 u8 mkey_7_0[0x8];
2241
2242 u8 reserved_3[0x20];
2243
2244 u8 length64[0x1];
2245 u8 bsf_en[0x1];
2246 u8 sync_umr[0x1];
2247 u8 reserved_4[0x2];
2248 u8 expected_sigerr_count[0x1];
2249 u8 reserved_5[0x1];
2250 u8 en_rinval[0x1];
2251 u8 pd[0x18];
2252
2253 u8 start_addr[0x40];
2254
2255 u8 len[0x40];
2256
2257 u8 bsf_octword_size[0x20];
2258
2259 u8 reserved_6[0x80];
2260
2261 u8 translations_octword_size[0x20];
2262
2263 u8 reserved_7[0x1b];
2264 u8 log_page_size[0x5];
2265
2266 u8 reserved_8[0x20];
2267};
2268
2269struct mlx5_ifc_pkey_bits {
2270 u8 reserved_0[0x10];
2271 u8 pkey[0x10];
2272};
2273
2274struct mlx5_ifc_array128_auto_bits {
2275 u8 array128_auto[16][0x8];
2276};
2277
2278struct mlx5_ifc_hca_vport_context_bits {
2279 u8 field_select[0x20];
2280
2281 u8 reserved_0[0xe0];
2282
2283 u8 sm_virt_aware[0x1];
2284 u8 has_smi[0x1];
2285 u8 has_raw[0x1];
2286 u8 grh_required[0x1];
707c4602
MD		 2287 u8 reserved_1[0xc];
2288 u8 port_physical_state[0x4];
2289 u8 vport_state_policy[0x4];
2290 u8 port_state[0x4];
e281682b
SM		 2291 u8 vport_state[0x4];
2292
707c4602
MD		 2293 u8 reserved_2[0x20];
2294
2295 u8 system_image_guid[0x40];
e281682b
SM		 2296
2297 u8 port_guid[0x40];
2298
2299 u8 node_guid[0x40];
2300
2301 u8 cap_mask1[0x20];
2302
2303 u8 cap_mask1_field_select[0x20];
2304
2305 u8 cap_mask2[0x20];
2306
2307 u8 cap_mask2_field_select[0x20];
2308
2309 u8 reserved_3[0x80];
2310
2311 u8 lid[0x10];
2312 u8 reserved_4[0x4];
2313 u8 init_type_reply[0x4];
2314 u8 lmc[0x3];
2315 u8 subnet_timeout[0x5];
2316
2317 u8 sm_lid[0x10];
2318 u8 sm_sl[0x4];
2319 u8 reserved_5[0xc];
2320
2321 u8 qkey_violation_counter[0x10];
2322 u8 pkey_violation_counter[0x10];
2323
2324 u8 reserved_6[0xca0];
2325};
2326
d6666753
SM		 2327struct mlx5_ifc_esw_vport_context_bits {
2328 u8 reserved_0[0x3];
2329 u8 vport_svlan_strip[0x1];
2330 u8 vport_cvlan_strip[0x1];
2331 u8 vport_svlan_insert[0x1];
2332 u8 vport_cvlan_insert[0x2];
2333 u8 reserved_1[0x18];
2334
2335 u8 reserved_2[0x20];
2336
2337 u8 svlan_cfi[0x1];
2338 u8 svlan_pcp[0x3];
2339 u8 svlan_id[0xc];
2340 u8 cvlan_cfi[0x1];
2341 u8 cvlan_pcp[0x3];
2342 u8 cvlan_id[0xc];
2343
2344 u8 reserved_3[0x7a0];
2345};
2346
e281682b
SM		 2347enum {
2348 MLX5_EQC_STATUS_OK = 0x0,
2349 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
2350};
2351
2352enum {
2353 MLX5_EQC_ST_ARMED = 0x9,
2354 MLX5_EQC_ST_FIRED = 0xa,
2355};
2356
2357struct mlx5_ifc_eqc_bits {
2358 u8 status[0x4];
2359 u8 reserved_0[0x9];
2360 u8 ec[0x1];
2361 u8 oi[0x1];
2362 u8 reserved_1[0x5];
2363 u8 st[0x4];
2364 u8 reserved_2[0x8];
2365
2366 u8 reserved_3[0x20];
2367
2368 u8 reserved_4[0x14];
2369 u8 page_offset[0x6];
2370 u8 reserved_5[0x6];
2371
2372 u8 reserved_6[0x3];
2373 u8 log_eq_size[0x5];
2374 u8 uar_page[0x18];
2375
2376 u8 reserved_7[0x20];
2377
2378 u8 reserved_8[0x18];
2379 u8 intr[0x8];
2380
2381 u8 reserved_9[0x3];
2382 u8 log_page_size[0x5];
2383 u8 reserved_10[0x18];
2384
2385 u8 reserved_11[0x60];
2386
2387 u8 reserved_12[0x8];
2388 u8 consumer_counter[0x18];
2389
2390 u8 reserved_13[0x8];
2391 u8 producer_counter[0x18];
2392
2393 u8 reserved_14[0x80];
2394};
2395
2396enum {
2397 MLX5_DCTC_STATE_ACTIVE = 0x0,
2398 MLX5_DCTC_STATE_DRAINING = 0x1,
2399 MLX5_DCTC_STATE_DRAINED = 0x2,
2400};
2401
2402enum {
2403 MLX5_DCTC_CS_RES_DISABLE = 0x0,
2404 MLX5_DCTC_CS_RES_NA = 0x1,
2405 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
2406};
2407
2408enum {
2409 MLX5_DCTC_MTU_256_BYTES = 0x1,
2410 MLX5_DCTC_MTU_512_BYTES = 0x2,
2411 MLX5_DCTC_MTU_1K_BYTES = 0x3,
2412 MLX5_DCTC_MTU_2K_BYTES = 0x4,
2413 MLX5_DCTC_MTU_4K_BYTES = 0x5,
2414};
2415
2416struct mlx5_ifc_dctc_bits {
2417 u8 reserved_0[0x4];
2418 u8 state[0x4];
2419 u8 reserved_1[0x18];
2420
2421 u8 reserved_2[0x8];
2422 u8 user_index[0x18];
2423
2424 u8 reserved_3[0x8];
2425 u8 cqn[0x18];
2426
2427 u8 counter_set_id[0x8];
2428 u8 atomic_mode[0x4];
2429 u8 rre[0x1];
2430 u8 rwe[0x1];
2431 u8 rae[0x1];
2432 u8 atomic_like_write_en[0x1];
2433 u8 latency_sensitive[0x1];
2434 u8 rlky[0x1];
2435 u8 free_ar[0x1];
2436 u8 reserved_4[0xd];
2437
2438 u8 reserved_5[0x8];
2439 u8 cs_res[0x8];
2440 u8 reserved_6[0x3];
2441 u8 min_rnr_nak[0x5];
2442 u8 reserved_7[0x8];
2443
2444 u8 reserved_8[0x8];
2445 u8 srqn[0x18];
2446
2447 u8 reserved_9[0x8];
2448 u8 pd[0x18];
2449
2450 u8 tclass[0x8];
2451 u8 reserved_10[0x4];
2452 u8 flow_label[0x14];
2453
2454 u8 dc_access_key[0x40];
2455
2456 u8 reserved_11[0x5];
2457 u8 mtu[0x3];
2458 u8 port[0x8];
2459 u8 pkey_index[0x10];
2460
2461 u8 reserved_12[0x8];
2462 u8 my_addr_index[0x8];
2463 u8 reserved_13[0x8];
2464 u8 hop_limit[0x8];
2465
2466 u8 dc_access_key_violation_count[0x20];
2467
2468 u8 reserved_14[0x14];
2469 u8 dei_cfi[0x1];
2470 u8 eth_prio[0x3];
2471 u8 ecn[0x2];
2472 u8 dscp[0x6];
2473
2474 u8 reserved_15[0x40];
2475};
2476
2477enum {
2478 MLX5_CQC_STATUS_OK = 0x0,
2479 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
2480 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
2481};
2482
2483enum {
2484 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
2485 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
2486};
2487
2488enum {
2489 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
2490 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
2491 MLX5_CQC_ST_FIRED = 0xa,
2492};
2493
2494struct mlx5_ifc_cqc_bits {
2495 u8 status[0x4];
2496 u8 reserved_0[0x4];
2497 u8 cqe_sz[0x3];
2498 u8 cc[0x1];
2499 u8 reserved_1[0x1];
2500 u8 scqe_break_moderation_en[0x1];
2501 u8 oi[0x1];
2502 u8 reserved_2[0x2];
2503 u8 cqe_zip_en[0x1];
2504 u8 mini_cqe_res_format[0x2];
2505 u8 st[0x4];
2506 u8 reserved_3[0x8];
2507
2508 u8 reserved_4[0x20];
2509
2510 u8 reserved_5[0x14];
2511 u8 page_offset[0x6];
2512 u8 reserved_6[0x6];
2513
2514 u8 reserved_7[0x3];
2515 u8 log_cq_size[0x5];
2516 u8 uar_page[0x18];
2517
2518 u8 reserved_8[0x4];
2519 u8 cq_period[0xc];
2520 u8 cq_max_count[0x10];
2521
2522 u8 reserved_9[0x18];
2523 u8 c_eqn[0x8];
2524
2525 u8 reserved_10[0x3];
2526 u8 log_page_size[0x5];
2527 u8 reserved_11[0x18];
2528
2529 u8 reserved_12[0x20];
2530
2531 u8 reserved_13[0x8];
2532 u8 last_notified_index[0x18];
2533
2534 u8 reserved_14[0x8];
2535 u8 last_solicit_index[0x18];
2536
2537 u8 reserved_15[0x8];
2538 u8 consumer_counter[0x18];
2539
2540 u8 reserved_16[0x8];
2541 u8 producer_counter[0x18];
2542
2543 u8 reserved_17[0x40];
2544
2545 u8 dbr_addr[0x40];
2546};
2547
2548union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2549 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2550 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2551 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2552 u8 reserved_0[0x800];
2553};
2554
2555struct mlx5_ifc_query_adapter_param_block_bits {
211e6c80 2556 u8 reserved_0[0xc0];
e281682b 2557
211e6c80
MD		 2558 u8 reserved_1[0x8];
2559 u8 ieee_vendor_id[0x18];
2560
2561 u8 reserved_2[0x10];
e281682b
SM		 2562 u8 vsd_vendor_id[0x10];
2563
2564 u8 vsd[208][0x8];
2565
2566 u8 vsd_contd_psid[16][0x8];
2567};
2568
2569union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2570 struct mlx5_ifc_modify_field_select_bits modify_field_select;
2571 struct mlx5_ifc_resize_field_select_bits resize_field_select;
2572 u8 reserved_0[0x20];
2573};
2574
2575union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2576 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2577 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2578 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
2579 u8 reserved_0[0x20];
2580};
2581
2582union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
2583 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
2584 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
2585 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
2586 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
2587 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
2588 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
2589 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
2590 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
2591 u8 reserved_0[0x7c0];
2592};
2593
2594union mlx5_ifc_event_auto_bits {
2595 struct mlx5_ifc_comp_event_bits comp_event;
2596 struct mlx5_ifc_dct_events_bits dct_events;
2597 struct mlx5_ifc_qp_events_bits qp_events;
2598 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
2599 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
2600 struct mlx5_ifc_cq_error_bits cq_error;
2601 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
2602 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
2603 struct mlx5_ifc_gpio_event_bits gpio_event;
2604 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
2605 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
2606 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
2607 u8 reserved_0[0xe0];
2608};
2609
2610struct mlx5_ifc_health_buffer_bits {
2611 u8 reserved_0[0x100];
2612
2613 u8 assert_existptr[0x20];
2614
2615 u8 assert_callra[0x20];
2616
2617 u8 reserved_1[0x40];
2618
2619 u8 fw_version[0x20];
2620
2621 u8 hw_id[0x20];
2622
2623 u8 reserved_2[0x20];
2624
2625 u8 irisc_index[0x8];
2626 u8 synd[0x8];
2627 u8 ext_synd[0x10];
2628};
2629
2630struct mlx5_ifc_register_loopback_control_bits {
2631 u8 no_lb[0x1];
2632 u8 reserved_0[0x7];
2633 u8 port[0x8];
2634 u8 reserved_1[0x10];
2635
2636 u8 reserved_2[0x60];
2637};
2638
2639struct mlx5_ifc_teardown_hca_out_bits {
2640 u8 status[0x8];
2641 u8 reserved_0[0x18];
2642
2643 u8 syndrome[0x20];
2644
2645 u8 reserved_1[0x40];
2646};
2647
2648enum {
2649 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
2650 MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE = 0x1,
2651};
2652
2653struct mlx5_ifc_teardown_hca_in_bits {
2654 u8 opcode[0x10];
2655 u8 reserved_0[0x10];
2656
2657 u8 reserved_1[0x10];
2658 u8 op_mod[0x10];
2659
2660 u8 reserved_2[0x10];
2661 u8 profile[0x10];
2662
2663 u8 reserved_3[0x20];
2664};
2665
2666struct mlx5_ifc_sqerr2rts_qp_out_bits {
2667 u8 status[0x8];
2668 u8 reserved_0[0x18];
2669
2670 u8 syndrome[0x20];
2671
2672 u8 reserved_1[0x40];
2673};
2674
2675struct mlx5_ifc_sqerr2rts_qp_in_bits {
2676 u8 opcode[0x10];
2677 u8 reserved_0[0x10];
2678
2679 u8 reserved_1[0x10];
2680 u8 op_mod[0x10];
2681
2682 u8 reserved_2[0x8];
2683 u8 qpn[0x18];
2684
2685 u8 reserved_3[0x20];
2686
2687 u8 opt_param_mask[0x20];
2688
2689 u8 reserved_4[0x20];
2690
2691 struct mlx5_ifc_qpc_bits qpc;
2692
2693 u8 reserved_5[0x80];
2694};
2695
2696struct mlx5_ifc_sqd2rts_qp_out_bits {
2697 u8 status[0x8];
2698 u8 reserved_0[0x18];
2699
2700 u8 syndrome[0x20];
2701
2702 u8 reserved_1[0x40];
2703};
2704
2705struct mlx5_ifc_sqd2rts_qp_in_bits {
2706 u8 opcode[0x10];
2707 u8 reserved_0[0x10];
2708
2709 u8 reserved_1[0x10];
2710 u8 op_mod[0x10];
2711
2712 u8 reserved_2[0x8];
2713 u8 qpn[0x18];
2714
2715 u8 reserved_3[0x20];
2716
2717 u8 opt_param_mask[0x20];
2718
2719 u8 reserved_4[0x20];
2720
2721 struct mlx5_ifc_qpc_bits qpc;
2722
2723 u8 reserved_5[0x80];
2724};
2725
2726struct mlx5_ifc_set_roce_address_out_bits {
2727 u8 status[0x8];
2728 u8 reserved_0[0x18];
2729
2730 u8 syndrome[0x20];
2731
2732 u8 reserved_1[0x40];
2733};
2734
2735struct mlx5_ifc_set_roce_address_in_bits {
2736 u8 opcode[0x10];
2737 u8 reserved_0[0x10];
2738
2739 u8 reserved_1[0x10];
2740 u8 op_mod[0x10];
2741
2742 u8 roce_address_index[0x10];
2743 u8 reserved_2[0x10];
2744
2745 u8 reserved_3[0x20];
2746
2747 struct mlx5_ifc_roce_addr_layout_bits roce_address;
2748};
2749
2750struct mlx5_ifc_set_mad_demux_out_bits {
2751 u8 status[0x8];
2752 u8 reserved_0[0x18];
2753
2754 u8 syndrome[0x20];
2755
2756 u8 reserved_1[0x40];
2757};
2758
2759enum {
2760 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
2761 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
2762};
2763
2764struct mlx5_ifc_set_mad_demux_in_bits {
2765 u8 opcode[0x10];
2766 u8 reserved_0[0x10];
2767
2768 u8 reserved_1[0x10];
2769 u8 op_mod[0x10];
2770
2771 u8 reserved_2[0x20];
2772
2773 u8 reserved_3[0x6];
2774 u8 demux_mode[0x2];
2775 u8 reserved_4[0x18];
2776};
2777
2778struct mlx5_ifc_set_l2_table_entry_out_bits {
2779 u8 status[0x8];
2780 u8 reserved_0[0x18];
2781
2782 u8 syndrome[0x20];
2783
2784 u8 reserved_1[0x40];
2785};
2786
2787struct mlx5_ifc_set_l2_table_entry_in_bits {
2788 u8 opcode[0x10];
2789 u8 reserved_0[0x10];
2790
2791 u8 reserved_1[0x10];
2792 u8 op_mod[0x10];
2793
2794 u8 reserved_2[0x60];
2795
2796 u8 reserved_3[0x8];
2797 u8 table_index[0x18];
2798
2799 u8 reserved_4[0x20];
2800
2801 u8 reserved_5[0x13];
2802 u8 vlan_valid[0x1];
2803 u8 vlan[0xc];
2804
2805 struct mlx5_ifc_mac_address_layout_bits mac_address;
2806
2807 u8 reserved_6[0xc0];
2808};
2809
2810struct mlx5_ifc_set_issi_out_bits {
2811 u8 status[0x8];
2812 u8 reserved_0[0x18];
2813
2814 u8 syndrome[0x20];
2815
2816 u8 reserved_1[0x40];
2817};
2818
2819struct mlx5_ifc_set_issi_in_bits {
2820 u8 opcode[0x10];
2821 u8 reserved_0[0x10];
2822
2823 u8 reserved_1[0x10];
2824 u8 op_mod[0x10];
2825
2826 u8 reserved_2[0x10];
2827 u8 current_issi[0x10];
2828
2829 u8 reserved_3[0x20];
2830};
2831
2832struct mlx5_ifc_set_hca_cap_out_bits {
2833 u8 status[0x8];
2834 u8 reserved_0[0x18];
2835
2836 u8 syndrome[0x20];
2837
2838 u8 reserved_1[0x40];
2839};
2840
2841struct mlx5_ifc_set_hca_cap_in_bits {
2842 u8 opcode[0x10];
2843 u8 reserved_0[0x10];
2844
2845 u8 reserved_1[0x10];
2846 u8 op_mod[0x10];
2847
2848 u8 reserved_2[0x40];
2849
2850 union mlx5_ifc_hca_cap_union_bits capability;
2851};
2852
26a81453
MG		 2853enum {
2854 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
2855 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
2856 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
2857 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
2858};
2859
e281682b
SM		 2860struct mlx5_ifc_set_fte_out_bits {
2861 u8 status[0x8];
2862 u8 reserved_0[0x18];
2863
2864 u8 syndrome[0x20];
2865
2866 u8 reserved_1[0x40];
2867};
2868
2869struct mlx5_ifc_set_fte_in_bits {
2870 u8 opcode[0x10];
2871 u8 reserved_0[0x10];
2872
2873 u8 reserved_1[0x10];
2874 u8 op_mod[0x10];
2875
2876 u8 reserved_2[0x40];
2877
2878 u8 table_type[0x8];
2879 u8 reserved_3[0x18];
2880
2881 u8 reserved_4[0x8];
2882 u8 table_id[0x18];
2883
26a81453
MG		 2884 u8 reserved_5[0x18];
2885 u8 modify_enable_mask[0x8];
2886
2887 u8 reserved_6[0x20];
e281682b
SM		 2888
2889 u8 flow_index[0x20];
2890
26a81453 2891 u8 reserved_7[0xe0];
e281682b
SM		 2892
2893 struct mlx5_ifc_flow_context_bits flow_context;
2894};
2895
2896struct mlx5_ifc_rts2rts_qp_out_bits {
2897 u8 status[0x8];
2898 u8 reserved_0[0x18];
2899
2900 u8 syndrome[0x20];
2901
2902 u8 reserved_1[0x40];
2903};
2904
2905struct mlx5_ifc_rts2rts_qp_in_bits {
2906 u8 opcode[0x10];
2907 u8 reserved_0[0x10];
2908
2909 u8 reserved_1[0x10];
2910 u8 op_mod[0x10];
2911
2912 u8 reserved_2[0x8];
2913 u8 qpn[0x18];
2914
2915 u8 reserved_3[0x20];
2916
2917 u8 opt_param_mask[0x20];
2918
2919 u8 reserved_4[0x20];
2920
2921 struct mlx5_ifc_qpc_bits qpc;
2922
2923 u8 reserved_5[0x80];
2924};
2925
2926struct mlx5_ifc_rtr2rts_qp_out_bits {
2927 u8 status[0x8];
2928 u8 reserved_0[0x18];
2929
2930 u8 syndrome[0x20];
2931
2932 u8 reserved_1[0x40];
2933};
2934
2935struct mlx5_ifc_rtr2rts_qp_in_bits {
2936 u8 opcode[0x10];
2937 u8 reserved_0[0x10];
2938
2939 u8 reserved_1[0x10];
2940 u8 op_mod[0x10];
2941
2942 u8 reserved_2[0x8];
2943 u8 qpn[0x18];
2944
2945 u8 reserved_3[0x20];
2946
2947 u8 opt_param_mask[0x20];
2948
2949 u8 reserved_4[0x20];
2950
2951 struct mlx5_ifc_qpc_bits qpc;
2952
2953 u8 reserved_5[0x80];
2954};
2955
2956struct mlx5_ifc_rst2init_qp_out_bits {
2957 u8 status[0x8];
2958 u8 reserved_0[0x18];
2959
2960 u8 syndrome[0x20];
2961
2962 u8 reserved_1[0x40];
2963};
2964
2965struct mlx5_ifc_rst2init_qp_in_bits {
2966 u8 opcode[0x10];
2967 u8 reserved_0[0x10];
2968
2969 u8 reserved_1[0x10];
2970 u8 op_mod[0x10];
2971
2972 u8 reserved_2[0x8];
2973 u8 qpn[0x18];
2974
2975 u8 reserved_3[0x20];
2976
2977 u8 opt_param_mask[0x20];
2978
2979 u8 reserved_4[0x20];
2980
2981 struct mlx5_ifc_qpc_bits qpc;
2982
2983 u8 reserved_5[0x80];
2984};
2985
2986struct mlx5_ifc_query_xrc_srq_out_bits {
2987 u8 status[0x8];
2988 u8 reserved_0[0x18];
2989
2990 u8 syndrome[0x20];
2991
2992 u8 reserved_1[0x40];
2993
2994 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
2995
2996 u8 reserved_2[0x600];
2997
2998 u8 pas[0][0x40];
2999};
3000
3001struct mlx5_ifc_query_xrc_srq_in_bits {
3002 u8 opcode[0x10];
3003 u8 reserved_0[0x10];
3004
3005 u8 reserved_1[0x10];
3006 u8 op_mod[0x10];
3007
3008 u8 reserved_2[0x8];
3009 u8 xrc_srqn[0x18];
3010
3011 u8 reserved_3[0x20];
3012};
3013
3014enum {
3015 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
3016 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
3017};
3018
3019struct mlx5_ifc_query_vport_state_out_bits {
3020 u8 status[0x8];
3021 u8 reserved_0[0x18];
3022
3023 u8 syndrome[0x20];
3024
3025 u8 reserved_1[0x20];
3026
3027 u8 reserved_2[0x18];
3028 u8 admin_state[0x4];
3029 u8 state[0x4];
3030};
3031
3032enum {
3033 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0,
e7546514 3034 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1,
e281682b
SM		 3035};
3036
3037struct mlx5_ifc_query_vport_state_in_bits {
3038 u8 opcode[0x10];
3039 u8 reserved_0[0x10];
3040
3041 u8 reserved_1[0x10];
3042 u8 op_mod[0x10];
3043
3044 u8 other_vport[0x1];
3045 u8 reserved_2[0xf];
3046 u8 vport_number[0x10];
3047
3048 u8 reserved_3[0x20];
3049};
3050
3051struct mlx5_ifc_query_vport_counter_out_bits {
3052 u8 status[0x8];
3053 u8 reserved_0[0x18];
3054
3055 u8 syndrome[0x20];
3056
3057 u8 reserved_1[0x40];
3058
3059 struct mlx5_ifc_traffic_counter_bits received_errors;
3060
3061 struct mlx5_ifc_traffic_counter_bits transmit_errors;
3062
3063 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3064
3065 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3066
3067 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3068
3069 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3070
3071 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3072
3073 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3074
3075 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3076
3077 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3078
3079 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3080
3081 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3082
3083 u8 reserved_2[0xa00];
3084};
3085
3086enum {
3087 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
3088};
3089
3090struct mlx5_ifc_query_vport_counter_in_bits {
3091 u8 opcode[0x10];
3092 u8 reserved_0[0x10];
3093
3094 u8 reserved_1[0x10];
3095 u8 op_mod[0x10];
3096
3097 u8 other_vport[0x1];
3098 u8 reserved_2[0xf];
3099 u8 vport_number[0x10];
3100
3101 u8 reserved_3[0x60];
3102
3103 u8 clear[0x1];
3104 u8 reserved_4[0x1f];
3105
3106 u8 reserved_5[0x20];
3107};
3108
3109struct mlx5_ifc_query_tis_out_bits {
3110 u8 status[0x8];
3111 u8 reserved_0[0x18];
3112
3113 u8 syndrome[0x20];
3114
3115 u8 reserved_1[0x40];
3116
3117 struct mlx5_ifc_tisc_bits tis_context;
3118};
3119
3120struct mlx5_ifc_query_tis_in_bits {
3121 u8 opcode[0x10];
3122 u8 reserved_0[0x10];
3123
3124 u8 reserved_1[0x10];
3125 u8 op_mod[0x10];
3126
3127 u8 reserved_2[0x8];
3128 u8 tisn[0x18];
3129
3130 u8 reserved_3[0x20];
3131};
3132
3133struct mlx5_ifc_query_tir_out_bits {
3134 u8 status[0x8];
3135 u8 reserved_0[0x18];
3136
3137 u8 syndrome[0x20];
3138
3139 u8 reserved_1[0xc0];
3140
3141 struct mlx5_ifc_tirc_bits tir_context;
3142};
3143
3144struct mlx5_ifc_query_tir_in_bits {
3145 u8 opcode[0x10];
3146 u8 reserved_0[0x10];
3147
3148 u8 reserved_1[0x10];
3149 u8 op_mod[0x10];
3150
3151 u8 reserved_2[0x8];
3152 u8 tirn[0x18];
3153
3154 u8 reserved_3[0x20];
3155};
3156
3157struct mlx5_ifc_query_srq_out_bits {
3158 u8 status[0x8];
3159 u8 reserved_0[0x18];
3160
3161 u8 syndrome[0x20];
3162
3163 u8 reserved_1[0x40];
3164
3165 struct mlx5_ifc_srqc_bits srq_context_entry;
3166
3167 u8 reserved_2[0x600];
3168
3169 u8 pas[0][0x40];
3170};
3171
3172struct mlx5_ifc_query_srq_in_bits {
3173 u8 opcode[0x10];
3174 u8 reserved_0[0x10];
3175
3176 u8 reserved_1[0x10];
3177 u8 op_mod[0x10];
3178
3179 u8 reserved_2[0x8];
3180 u8 srqn[0x18];
3181
3182 u8 reserved_3[0x20];
3183};
3184
3185struct mlx5_ifc_query_sq_out_bits {
3186 u8 status[0x8];
3187 u8 reserved_0[0x18];
3188
3189 u8 syndrome[0x20];
3190
3191 u8 reserved_1[0xc0];
3192
3193 struct mlx5_ifc_sqc_bits sq_context;
3194};
3195
3196struct mlx5_ifc_query_sq_in_bits {
3197 u8 opcode[0x10];
3198 u8 reserved_0[0x10];
3199
3200 u8 reserved_1[0x10];
3201 u8 op_mod[0x10];
3202
3203 u8 reserved_2[0x8];
3204 u8 sqn[0x18];
3205
3206 u8 reserved_3[0x20];
3207};
3208
3209struct mlx5_ifc_query_special_contexts_out_bits {
3210 u8 status[0x8];
3211 u8 reserved_0[0x18];
3212
3213 u8 syndrome[0x20];
3214
3215 u8 reserved_1[0x20];
3216
3217 u8 resd_lkey[0x20];
3218};
3219
3220struct mlx5_ifc_query_special_contexts_in_bits {
3221 u8 opcode[0x10];
3222 u8 reserved_0[0x10];
3223
3224 u8 reserved_1[0x10];
3225 u8 op_mod[0x10];
3226
3227 u8 reserved_2[0x40];
3228};
3229
3230struct mlx5_ifc_query_rqt_out_bits {
3231 u8 status[0x8];
3232 u8 reserved_0[0x18];
3233
3234 u8 syndrome[0x20];
3235
3236 u8 reserved_1[0xc0];
3237
3238 struct mlx5_ifc_rqtc_bits rqt_context;
3239};
3240
3241struct mlx5_ifc_query_rqt_in_bits {
3242 u8 opcode[0x10];
3243 u8 reserved_0[0x10];
3244
3245 u8 reserved_1[0x10];
3246 u8 op_mod[0x10];
3247
3248 u8 reserved_2[0x8];
3249 u8 rqtn[0x18];
3250
3251 u8 reserved_3[0x20];
3252};
3253
3254struct mlx5_ifc_query_rq_out_bits {
3255 u8 status[0x8];
3256 u8 reserved_0[0x18];
3257
3258 u8 syndrome[0x20];
3259
3260 u8 reserved_1[0xc0];
3261
3262 struct mlx5_ifc_rqc_bits rq_context;
3263};
3264
3265struct mlx5_ifc_query_rq_in_bits {
3266 u8 opcode[0x10];
3267 u8 reserved_0[0x10];
3268
3269 u8 reserved_1[0x10];
3270 u8 op_mod[0x10];
3271
3272 u8 reserved_2[0x8];
3273 u8 rqn[0x18];
3274
3275 u8 reserved_3[0x20];
3276};
3277
3278struct mlx5_ifc_query_roce_address_out_bits {
3279 u8 status[0x8];
3280 u8 reserved_0[0x18];
3281
3282 u8 syndrome[0x20];
3283
3284 u8 reserved_1[0x40];
3285
3286 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3287};
3288
3289struct mlx5_ifc_query_roce_address_in_bits {
3290 u8 opcode[0x10];
3291 u8 reserved_0[0x10];
3292
3293 u8 reserved_1[0x10];
3294 u8 op_mod[0x10];
3295
3296 u8 roce_address_index[0x10];
3297 u8 reserved_2[0x10];
3298
3299 u8 reserved_3[0x20];
3300};
3301
3302struct mlx5_ifc_query_rmp_out_bits {
3303 u8 status[0x8];
3304 u8 reserved_0[0x18];
3305
3306 u8 syndrome[0x20];
3307
3308 u8 reserved_1[0xc0];
3309
3310 struct mlx5_ifc_rmpc_bits rmp_context;
3311};
3312
3313struct mlx5_ifc_query_rmp_in_bits {
3314 u8 opcode[0x10];
3315 u8 reserved_0[0x10];
3316
3317 u8 reserved_1[0x10];
3318 u8 op_mod[0x10];
3319
3320 u8 reserved_2[0x8];
3321 u8 rmpn[0x18];
3322
3323 u8 reserved_3[0x20];
3324};
3325
3326struct mlx5_ifc_query_qp_out_bits {
3327 u8 status[0x8];
3328 u8 reserved_0[0x18];
3329
3330 u8 syndrome[0x20];
3331
3332 u8 reserved_1[0x40];
3333
3334 u8 opt_param_mask[0x20];
3335
3336 u8 reserved_2[0x20];
3337
3338 struct mlx5_ifc_qpc_bits qpc;
3339
3340 u8 reserved_3[0x80];
3341
3342 u8 pas[0][0x40];
3343};
3344
3345struct mlx5_ifc_query_qp_in_bits {
3346 u8 opcode[0x10];
3347 u8 reserved_0[0x10];
3348
3349 u8 reserved_1[0x10];
3350 u8 op_mod[0x10];
3351
3352 u8 reserved_2[0x8];
3353 u8 qpn[0x18];
3354
3355 u8 reserved_3[0x20];
3356};
3357
3358struct mlx5_ifc_query_q_counter_out_bits {
3359 u8 status[0x8];
3360 u8 reserved_0[0x18];
3361
3362 u8 syndrome[0x20];
3363
3364 u8 reserved_1[0x40];
3365
3366 u8 rx_write_requests[0x20];
3367
3368 u8 reserved_2[0x20];
3369
3370 u8 rx_read_requests[0x20];
3371
3372 u8 reserved_3[0x20];
3373
3374 u8 rx_atomic_requests[0x20];
3375
3376 u8 reserved_4[0x20];
3377
3378 u8 rx_dct_connect[0x20];
3379
3380 u8 reserved_5[0x20];
3381
3382 u8 out_of_buffer[0x20];
3383
3384 u8 reserved_6[0x20];
3385
3386 u8 out_of_sequence[0x20];
3387
3388 u8 reserved_7[0x620];
3389};
3390
3391struct mlx5_ifc_query_q_counter_in_bits {
3392 u8 opcode[0x10];
3393 u8 reserved_0[0x10];
3394
3395 u8 reserved_1[0x10];
3396 u8 op_mod[0x10];
3397
3398 u8 reserved_2[0x80];
3399
3400 u8 clear[0x1];
3401 u8 reserved_3[0x1f];
3402
3403 u8 reserved_4[0x18];
3404 u8 counter_set_id[0x8];
3405};
3406
3407struct mlx5_ifc_query_pages_out_bits {
3408 u8 status[0x8];
3409 u8 reserved_0[0x18];
3410
3411 u8 syndrome[0x20];
3412
3413 u8 reserved_1[0x10];
3414 u8 function_id[0x10];
3415
3416 u8 num_pages[0x20];
3417};
3418
3419enum {
3420 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
3421 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
3422 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
3423};
3424
3425struct mlx5_ifc_query_pages_in_bits {
3426 u8 opcode[0x10];
3427 u8 reserved_0[0x10];
3428
3429 u8 reserved_1[0x10];
3430 u8 op_mod[0x10];
3431
3432 u8 reserved_2[0x10];
3433 u8 function_id[0x10];
3434
3435 u8 reserved_3[0x20];
3436};
3437
3438struct mlx5_ifc_query_nic_vport_context_out_bits {
3439 u8 status[0x8];
3440 u8 reserved_0[0x18];
3441
3442 u8 syndrome[0x20];
3443
3444 u8 reserved_1[0x40];
3445
3446 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
3447};
3448
3449struct mlx5_ifc_query_nic_vport_context_in_bits {
3450 u8 opcode[0x10];
3451 u8 reserved_0[0x10];
3452
3453 u8 reserved_1[0x10];
3454 u8 op_mod[0x10];
3455
3456 u8 other_vport[0x1];
3457 u8 reserved_2[0xf];
3458 u8 vport_number[0x10];
3459
3460 u8 reserved_3[0x5];
3461 u8 allowed_list_type[0x3];
3462 u8 reserved_4[0x18];
3463};
3464
3465struct mlx5_ifc_query_mkey_out_bits {
3466 u8 status[0x8];
3467 u8 reserved_0[0x18];
3468
3469 u8 syndrome[0x20];
3470
3471 u8 reserved_1[0x40];
3472
3473 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
3474
3475 u8 reserved_2[0x600];
3476
3477 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
3478
3479 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
3480};
3481
3482struct mlx5_ifc_query_mkey_in_bits {
3483 u8 opcode[0x10];
3484 u8 reserved_0[0x10];
3485
3486 u8 reserved_1[0x10];
3487 u8 op_mod[0x10];
3488
3489 u8 reserved_2[0x8];
3490 u8 mkey_index[0x18];
3491
3492 u8 pg_access[0x1];
3493 u8 reserved_3[0x1f];
3494};
3495
3496struct mlx5_ifc_query_mad_demux_out_bits {
3497 u8 status[0x8];
3498 u8 reserved_0[0x18];
3499
3500 u8 syndrome[0x20];
3501
3502 u8 reserved_1[0x40];
3503
3504 u8 mad_dumux_parameters_block[0x20];
3505};
3506
3507struct mlx5_ifc_query_mad_demux_in_bits {
3508 u8 opcode[0x10];
3509 u8 reserved_0[0x10];
3510
3511 u8 reserved_1[0x10];
3512 u8 op_mod[0x10];
3513
3514 u8 reserved_2[0x40];
3515};
3516
3517struct mlx5_ifc_query_l2_table_entry_out_bits {
3518 u8 status[0x8];
3519 u8 reserved_0[0x18];
3520
3521 u8 syndrome[0x20];
3522
3523 u8 reserved_1[0xa0];
3524
3525 u8 reserved_2[0x13];
3526 u8 vlan_valid[0x1];
3527 u8 vlan[0xc];
3528
3529 struct mlx5_ifc_mac_address_layout_bits mac_address;
3530
3531 u8 reserved_3[0xc0];
3532};
3533
3534struct mlx5_ifc_query_l2_table_entry_in_bits {
3535 u8 opcode[0x10];
3536 u8 reserved_0[0x10];
3537
3538 u8 reserved_1[0x10];
3539 u8 op_mod[0x10];
3540
3541 u8 reserved_2[0x60];
3542
3543 u8 reserved_3[0x8];
3544 u8 table_index[0x18];
3545
3546 u8 reserved_4[0x140];
3547};
3548
3549struct mlx5_ifc_query_issi_out_bits {
3550 u8 status[0x8];
3551 u8 reserved_0[0x18];
3552
3553 u8 syndrome[0x20];
3554
3555 u8 reserved_1[0x10];
3556 u8 current_issi[0x10];
3557
3558 u8 reserved_2[0xa0];
3559
3560 u8 supported_issi_reserved[76][0x8];
3561 u8 supported_issi_dw0[0x20];
3562};
3563
3564struct mlx5_ifc_query_issi_in_bits {
3565 u8 opcode[0x10];
3566 u8 reserved_0[0x10];
3567
3568 u8 reserved_1[0x10];
3569 u8 op_mod[0x10];
3570
3571 u8 reserved_2[0x40];
3572};
3573
3574struct mlx5_ifc_query_hca_vport_pkey_out_bits {
3575 u8 status[0x8];
3576 u8 reserved_0[0x18];
3577
3578 u8 syndrome[0x20];
3579
3580 u8 reserved_1[0x40];
3581
3582 struct mlx5_ifc_pkey_bits pkey[0];
3583};
3584
3585struct mlx5_ifc_query_hca_vport_pkey_in_bits {
3586 u8 opcode[0x10];
3587 u8 reserved_0[0x10];
3588
3589 u8 reserved_1[0x10];
3590 u8 op_mod[0x10];
3591
3592 u8 other_vport[0x1];
707c4602
MD		 3593 u8 reserved_2[0xb];
3594 u8 port_num[0x4];
e281682b
SM		 3595 u8 vport_number[0x10];
3596
3597 u8 reserved_3[0x10];
3598 u8 pkey_index[0x10];
3599};
3600
3601struct mlx5_ifc_query_hca_vport_gid_out_bits {
3602 u8 status[0x8];
3603 u8 reserved_0[0x18];
3604
3605 u8 syndrome[0x20];
3606
3607 u8 reserved_1[0x20];
3608
3609 u8 gids_num[0x10];
3610 u8 reserved_2[0x10];
3611
3612 struct mlx5_ifc_array128_auto_bits gid[0];
3613};
3614
3615struct mlx5_ifc_query_hca_vport_gid_in_bits {
3616 u8 opcode[0x10];
3617 u8 reserved_0[0x10];
3618
3619 u8 reserved_1[0x10];
3620 u8 op_mod[0x10];
3621
3622 u8 other_vport[0x1];
707c4602
MD		 3623 u8 reserved_2[0xb];
3624 u8 port_num[0x4];
e281682b
SM		 3625 u8 vport_number[0x10];
3626
3627 u8 reserved_3[0x10];
3628 u8 gid_index[0x10];
3629};
3630
3631struct mlx5_ifc_query_hca_vport_context_out_bits {
3632 u8 status[0x8];
3633 u8 reserved_0[0x18];
3634
3635 u8 syndrome[0x20];
3636
3637 u8 reserved_1[0x40];
3638
3639 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
3640};
3641
3642struct mlx5_ifc_query_hca_vport_context_in_bits {
3643 u8 opcode[0x10];
3644 u8 reserved_0[0x10];
3645
3646 u8 reserved_1[0x10];
3647 u8 op_mod[0x10];
3648
3649 u8 other_vport[0x1];
707c4602
MD		 3650 u8 reserved_2[0xb];
3651 u8 port_num[0x4];
e281682b
SM		 3652 u8 vport_number[0x10];
3653
3654 u8 reserved_3[0x20];
3655};
3656
3657struct mlx5_ifc_query_hca_cap_out_bits {
3658 u8 status[0x8];
3659 u8 reserved_0[0x18];
3660
3661 u8 syndrome[0x20];
3662
3663 u8 reserved_1[0x40];
3664
3665 union mlx5_ifc_hca_cap_union_bits capability;
3666};
3667
3668struct mlx5_ifc_query_hca_cap_in_bits {
3669 u8 opcode[0x10];
3670 u8 reserved_0[0x10];
3671
3672 u8 reserved_1[0x10];
3673 u8 op_mod[0x10];
3674
3675 u8 reserved_2[0x40];
3676};
3677
3678struct mlx5_ifc_query_flow_table_out_bits {
3679 u8 status[0x8];
3680 u8 reserved_0[0x18];
3681
3682 u8 syndrome[0x20];
3683
3684 u8 reserved_1[0x80];
3685
3686 u8 reserved_2[0x8];
3687 u8 level[0x8];
3688 u8 reserved_3[0x8];
3689 u8 log_size[0x8];
3690
3691 u8 reserved_4[0x120];
3692};
3693
3694struct mlx5_ifc_query_flow_table_in_bits {
3695 u8 opcode[0x10];
3696 u8 reserved_0[0x10];
3697
3698 u8 reserved_1[0x10];
3699 u8 op_mod[0x10];
3700
3701 u8 reserved_2[0x40];
3702
3703 u8 table_type[0x8];
3704 u8 reserved_3[0x18];
3705
3706 u8 reserved_4[0x8];
3707 u8 table_id[0x18];
3708
3709 u8 reserved_5[0x140];
3710};
3711
3712struct mlx5_ifc_query_fte_out_bits {
3713 u8 status[0x8];
3714 u8 reserved_0[0x18];
3715
3716 u8 syndrome[0x20];
3717
3718 u8 reserved_1[0x1c0];
3719
3720 struct mlx5_ifc_flow_context_bits flow_context;
3721};
3722
3723struct mlx5_ifc_query_fte_in_bits {
3724 u8 opcode[0x10];
3725 u8 reserved_0[0x10];
3726
3727 u8 reserved_1[0x10];
3728 u8 op_mod[0x10];
3729
3730 u8 reserved_2[0x40];
3731
3732 u8 table_type[0x8];
3733 u8 reserved_3[0x18];
3734
3735 u8 reserved_4[0x8];
3736 u8 table_id[0x18];
3737
3738 u8 reserved_5[0x40];
3739
3740 u8 flow_index[0x20];
3741
3742 u8 reserved_6[0xe0];
3743};
3744
3745enum {
3746 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
3747 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
3748 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
3749};
3750
3751struct mlx5_ifc_query_flow_group_out_bits {
3752 u8 status[0x8];
3753 u8 reserved_0[0x18];
3754
3755 u8 syndrome[0x20];
3756
3757 u8 reserved_1[0xa0];
3758
3759 u8 start_flow_index[0x20];
3760
3761 u8 reserved_2[0x20];
3762
3763 u8 end_flow_index[0x20];
3764
3765 u8 reserved_3[0xa0];
3766
3767 u8 reserved_4[0x18];
3768 u8 match_criteria_enable[0x8];
3769
3770 struct mlx5_ifc_fte_match_param_bits match_criteria;
3771
3772 u8 reserved_5[0xe00];
3773};
3774
3775struct mlx5_ifc_query_flow_group_in_bits {
3776 u8 opcode[0x10];
3777 u8 reserved_0[0x10];
3778
3779 u8 reserved_1[0x10];
3780 u8 op_mod[0x10];
3781
3782 u8 reserved_2[0x40];
3783
3784 u8 table_type[0x8];
3785 u8 reserved_3[0x18];
3786
3787 u8 reserved_4[0x8];
3788 u8 table_id[0x18];
3789
3790 u8 group_id[0x20];
3791
3792 u8 reserved_5[0x120];
3793};
3794
d6666753
SM		 3795struct mlx5_ifc_query_esw_vport_context_out_bits {
3796 u8 status[0x8];
3797 u8 reserved_0[0x18];
3798
3799 u8 syndrome[0x20];
3800
3801 u8 reserved_1[0x40];
3802
3803 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
3804};
3805
3806struct mlx5_ifc_query_esw_vport_context_in_bits {
3807 u8 opcode[0x10];
3808 u8 reserved_0[0x10];
3809
3810 u8 reserved_1[0x10];
3811 u8 op_mod[0x10];
3812
3813 u8 other_vport[0x1];
3814 u8 reserved_2[0xf];
3815 u8 vport_number[0x10];
3816
3817 u8 reserved_3[0x20];
3818};
3819
3820struct mlx5_ifc_modify_esw_vport_context_out_bits {
3821 u8 status[0x8];
3822 u8 reserved_0[0x18];
3823
3824 u8 syndrome[0x20];
3825
3826 u8 reserved_1[0x40];
3827};
3828
3829struct mlx5_ifc_esw_vport_context_fields_select_bits {
3830 u8 reserved[0x1c];
3831 u8 vport_cvlan_insert[0x1];
3832 u8 vport_svlan_insert[0x1];
3833 u8 vport_cvlan_strip[0x1];
3834 u8 vport_svlan_strip[0x1];
3835};
3836
3837struct mlx5_ifc_modify_esw_vport_context_in_bits {
3838 u8 opcode[0x10];
3839 u8 reserved_0[0x10];
3840
3841 u8 reserved_1[0x10];
3842 u8 op_mod[0x10];
3843
3844 u8 other_vport[0x1];
3845 u8 reserved_2[0xf];
3846 u8 vport_number[0x10];
3847
3848 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
3849
3850 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
3851};
3852
e281682b
SM		 3853struct mlx5_ifc_query_eq_out_bits {
3854 u8 status[0x8];
3855 u8 reserved_0[0x18];
3856
3857 u8 syndrome[0x20];
3858
3859 u8 reserved_1[0x40];
3860
3861 struct mlx5_ifc_eqc_bits eq_context_entry;
3862
3863 u8 reserved_2[0x40];
3864
3865 u8 event_bitmask[0x40];
3866
3867 u8 reserved_3[0x580];
3868
3869 u8 pas[0][0x40];
3870};
3871
3872struct mlx5_ifc_query_eq_in_bits {
3873 u8 opcode[0x10];
3874 u8 reserved_0[0x10];
3875
3876 u8 reserved_1[0x10];
3877 u8 op_mod[0x10];
3878
3879 u8 reserved_2[0x18];
3880 u8 eq_number[0x8];
3881
3882 u8 reserved_3[0x20];
3883};
3884
3885struct mlx5_ifc_query_dct_out_bits {
3886 u8 status[0x8];
3887 u8 reserved_0[0x18];
3888
3889 u8 syndrome[0x20];
3890
3891 u8 reserved_1[0x40];
3892
3893 struct mlx5_ifc_dctc_bits dct_context_entry;
3894
3895 u8 reserved_2[0x180];
3896};
3897
3898struct mlx5_ifc_query_dct_in_bits {
3899 u8 opcode[0x10];
3900 u8 reserved_0[0x10];
3901
3902 u8 reserved_1[0x10];
3903 u8 op_mod[0x10];
3904
3905 u8 reserved_2[0x8];
3906 u8 dctn[0x18];
3907
3908 u8 reserved_3[0x20];
3909};
3910
3911struct mlx5_ifc_query_cq_out_bits {
3912 u8 status[0x8];
3913 u8 reserved_0[0x18];
3914
3915 u8 syndrome[0x20];
3916
3917 u8 reserved_1[0x40];
3918
3919 struct mlx5_ifc_cqc_bits cq_context;
3920
3921 u8 reserved_2[0x600];
3922
3923 u8 pas[0][0x40];
3924};
3925
3926struct mlx5_ifc_query_cq_in_bits {
3927 u8 opcode[0x10];
3928 u8 reserved_0[0x10];
3929
3930 u8 reserved_1[0x10];
3931 u8 op_mod[0x10];
3932
3933 u8 reserved_2[0x8];
3934 u8 cqn[0x18];
3935
3936 u8 reserved_3[0x20];
3937};
3938
3939struct mlx5_ifc_query_cong_status_out_bits {
3940 u8 status[0x8];
3941 u8 reserved_0[0x18];
3942
3943 u8 syndrome[0x20];
3944
3945 u8 reserved_1[0x20];
3946
3947 u8 enable[0x1];
3948 u8 tag_enable[0x1];
3949 u8 reserved_2[0x1e];
3950};
3951
3952struct mlx5_ifc_query_cong_status_in_bits {
3953 u8 opcode[0x10];
3954 u8 reserved_0[0x10];
3955
3956 u8 reserved_1[0x10];
3957 u8 op_mod[0x10];
3958
3959 u8 reserved_2[0x18];
3960 u8 priority[0x4];
3961 u8 cong_protocol[0x4];
3962
3963 u8 reserved_3[0x20];
3964};
3965
3966struct mlx5_ifc_query_cong_statistics_out_bits {
3967 u8 status[0x8];
3968 u8 reserved_0[0x18];
3969
3970 u8 syndrome[0x20];
3971
3972 u8 reserved_1[0x40];
3973
3974 u8 cur_flows[0x20];
3975
3976 u8 sum_flows[0x20];
3977
3978 u8 cnp_ignored_high[0x20];
3979
3980 u8 cnp_ignored_low[0x20];
3981
3982 u8 cnp_handled_high[0x20];
3983
3984 u8 cnp_handled_low[0x20];
3985
3986 u8 reserved_2[0x100];
3987
3988 u8 time_stamp_high[0x20];
3989
3990 u8 time_stamp_low[0x20];
3991
3992 u8 accumulators_period[0x20];
3993
3994 u8 ecn_marked_roce_packets_high[0x20];
3995
3996 u8 ecn_marked_roce_packets_low[0x20];
3997
3998 u8 cnps_sent_high[0x20];
3999
4000 u8 cnps_sent_low[0x20];
4001
4002 u8 reserved_3[0x560];
4003};
4004
4005struct mlx5_ifc_query_cong_statistics_in_bits {
4006 u8 opcode[0x10];
4007 u8 reserved_0[0x10];
4008
4009 u8 reserved_1[0x10];
4010 u8 op_mod[0x10];
4011
4012 u8 clear[0x1];
4013 u8 reserved_2[0x1f];
4014
4015 u8 reserved_3[0x20];
4016};
4017
4018struct mlx5_ifc_query_cong_params_out_bits {
4019 u8 status[0x8];
4020 u8 reserved_0[0x18];
4021
4022 u8 syndrome[0x20];
4023
4024 u8 reserved_1[0x40];
4025
4026 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4027};
4028
4029struct mlx5_ifc_query_cong_params_in_bits {
4030 u8 opcode[0x10];
4031 u8 reserved_0[0x10];
4032
4033 u8 reserved_1[0x10];
4034 u8 op_mod[0x10];
4035
4036 u8 reserved_2[0x1c];
4037 u8 cong_protocol[0x4];
4038
4039 u8 reserved_3[0x20];
4040};
4041
4042struct mlx5_ifc_query_adapter_out_bits {
4043 u8 status[0x8];
4044 u8 reserved_0[0x18];
4045
4046 u8 syndrome[0x20];
4047
4048 u8 reserved_1[0x40];
4049
4050 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4051};
4052
4053struct mlx5_ifc_query_adapter_in_bits {
4054 u8 opcode[0x10];
4055 u8 reserved_0[0x10];
4056
4057 u8 reserved_1[0x10];
4058 u8 op_mod[0x10];
4059
4060 u8 reserved_2[0x40];
4061};
4062
4063struct mlx5_ifc_qp_2rst_out_bits {
4064 u8 status[0x8];
4065 u8 reserved_0[0x18];
4066
4067 u8 syndrome[0x20];
4068
4069 u8 reserved_1[0x40];
4070};
4071
4072struct mlx5_ifc_qp_2rst_in_bits {
4073 u8 opcode[0x10];
4074 u8 reserved_0[0x10];
4075
4076 u8 reserved_1[0x10];
4077 u8 op_mod[0x10];
4078
4079 u8 reserved_2[0x8];
4080 u8 qpn[0x18];
4081
4082 u8 reserved_3[0x20];
4083};
4084
4085struct mlx5_ifc_qp_2err_out_bits {
4086 u8 status[0x8];
4087 u8 reserved_0[0x18];
4088
4089 u8 syndrome[0x20];
4090
4091 u8 reserved_1[0x40];
4092};
4093
4094struct mlx5_ifc_qp_2err_in_bits {
4095 u8 opcode[0x10];
4096 u8 reserved_0[0x10];
4097
4098 u8 reserved_1[0x10];
4099 u8 op_mod[0x10];
4100
4101 u8 reserved_2[0x8];
4102 u8 qpn[0x18];
4103
4104 u8 reserved_3[0x20];
4105};
4106
4107struct mlx5_ifc_page_fault_resume_out_bits {
4108 u8 status[0x8];
4109 u8 reserved_0[0x18];
4110
4111 u8 syndrome[0x20];
4112
4113 u8 reserved_1[0x40];
4114};
4115
4116struct mlx5_ifc_page_fault_resume_in_bits {
4117 u8 opcode[0x10];
4118 u8 reserved_0[0x10];
4119
4120 u8 reserved_1[0x10];
4121 u8 op_mod[0x10];
4122
4123 u8 error[0x1];
4124 u8 reserved_2[0x4];
4125 u8 rdma[0x1];
4126 u8 read_write[0x1];
4127 u8 req_res[0x1];
4128 u8 qpn[0x18];
4129
4130 u8 reserved_3[0x20];
4131};
4132
4133struct mlx5_ifc_nop_out_bits {
4134 u8 status[0x8];
4135 u8 reserved_0[0x18];
4136
4137 u8 syndrome[0x20];
4138
4139 u8 reserved_1[0x40];
4140};
4141
4142struct mlx5_ifc_nop_in_bits {
4143 u8 opcode[0x10];
4144 u8 reserved_0[0x10];
4145
4146 u8 reserved_1[0x10];
4147 u8 op_mod[0x10];
4148
4149 u8 reserved_2[0x40];
4150};
4151
4152struct mlx5_ifc_modify_vport_state_out_bits {
4153 u8 status[0x8];
4154 u8 reserved_0[0x18];
4155
4156 u8 syndrome[0x20];
4157
4158 u8 reserved_1[0x40];
4159};
4160
4161struct mlx5_ifc_modify_vport_state_in_bits {
4162 u8 opcode[0x10];
4163 u8 reserved_0[0x10];
4164
4165 u8 reserved_1[0x10];
4166 u8 op_mod[0x10];
4167
4168 u8 other_vport[0x1];
4169 u8 reserved_2[0xf];
4170 u8 vport_number[0x10];
4171
4172 u8 reserved_3[0x18];
4173 u8 admin_state[0x4];
4174 u8 reserved_4[0x4];
4175};
4176
4177struct mlx5_ifc_modify_tis_out_bits {
4178 u8 status[0x8];
4179 u8 reserved_0[0x18];
4180
4181 u8 syndrome[0x20];
4182
4183 u8 reserved_1[0x40];
4184};
4185
4186struct mlx5_ifc_modify_tis_in_bits {
4187 u8 opcode[0x10];
4188 u8 reserved_0[0x10];
4189
4190 u8 reserved_1[0x10];
4191 u8 op_mod[0x10];
4192
4193 u8 reserved_2[0x8];
4194 u8 tisn[0x18];
4195
4196 u8 reserved_3[0x20];
4197
4198 u8 modify_bitmask[0x40];
4199
4200 u8 reserved_4[0x40];
4201
4202 struct mlx5_ifc_tisc_bits ctx;
4203};
4204
d9eea403 4205struct mlx5_ifc_modify_tir_bitmask_bits {
66189961 4206 u8 reserved_0[0x20];
d9eea403 4207
66189961
TT		 4208 u8 reserved_1[0x1b];
4209 u8 self_lb_en[0x1];
4210 u8 reserved_2[0x3];
d9eea403
AS		 4211 u8 lro[0x1];
4212};
4213
e281682b
SM		 4214struct mlx5_ifc_modify_tir_out_bits {
4215 u8 status[0x8];
4216 u8 reserved_0[0x18];
4217
4218 u8 syndrome[0x20];
4219
4220 u8 reserved_1[0x40];
4221};
4222
4223struct mlx5_ifc_modify_tir_in_bits {
4224 u8 opcode[0x10];
4225 u8 reserved_0[0x10];
4226
4227 u8 reserved_1[0x10];
4228 u8 op_mod[0x10];
4229
4230 u8 reserved_2[0x8];
4231 u8 tirn[0x18];
4232
4233 u8 reserved_3[0x20];
4234
d9eea403 4235 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
e281682b
SM		 4236
4237 u8 reserved_4[0x40];
4238
4239 struct mlx5_ifc_tirc_bits ctx;
4240};
4241
4242struct mlx5_ifc_modify_sq_out_bits {
4243 u8 status[0x8];
4244 u8 reserved_0[0x18];
4245
4246 u8 syndrome[0x20];
4247
4248 u8 reserved_1[0x40];
4249};
4250
4251struct mlx5_ifc_modify_sq_in_bits {
4252 u8 opcode[0x10];
4253 u8 reserved_0[0x10];
4254
4255 u8 reserved_1[0x10];
4256 u8 op_mod[0x10];
4257
4258 u8 sq_state[0x4];
4259 u8 reserved_2[0x4];
4260 u8 sqn[0x18];
4261
4262 u8 reserved_3[0x20];
4263
4264 u8 modify_bitmask[0x40];
4265
4266 u8 reserved_4[0x40];
4267
4268 struct mlx5_ifc_sqc_bits ctx;
4269};
4270
4271struct mlx5_ifc_modify_rqt_out_bits {
4272 u8 status[0x8];
4273 u8 reserved_0[0x18];
4274
4275 u8 syndrome[0x20];
4276
4277 u8 reserved_1[0x40];
4278};
4279
5c50368f
AS		 4280struct mlx5_ifc_rqt_bitmask_bits {
4281 u8 reserved[0x20];
4282
4283 u8 reserved1[0x1f];
4284 u8 rqn_list[0x1];
4285};
4286
e281682b
SM		 4287struct mlx5_ifc_modify_rqt_in_bits {
4288 u8 opcode[0x10];
4289 u8 reserved_0[0x10];
4290
4291 u8 reserved_1[0x10];
4292 u8 op_mod[0x10];
4293
4294 u8 reserved_2[0x8];
4295 u8 rqtn[0x18];
4296
4297 u8 reserved_3[0x20];
4298
5c50368f 4299 struct mlx5_ifc_rqt_bitmask_bits bitmask;
e281682b
SM		 4300
4301 u8 reserved_4[0x40];
4302
4303 struct mlx5_ifc_rqtc_bits ctx;
4304};
4305
4306struct mlx5_ifc_modify_rq_out_bits {
4307 u8 status[0x8];
4308 u8 reserved_0[0x18];
4309
4310 u8 syndrome[0x20];
4311
4312 u8 reserved_1[0x40];
4313};
4314
4315struct mlx5_ifc_modify_rq_in_bits {
4316 u8 opcode[0x10];
4317 u8 reserved_0[0x10];
4318
4319 u8 reserved_1[0x10];
4320 u8 op_mod[0x10];
4321
4322 u8 rq_state[0x4];
4323 u8 reserved_2[0x4];
4324 u8 rqn[0x18];
4325
4326 u8 reserved_3[0x20];
4327
4328 u8 modify_bitmask[0x40];
4329
4330 u8 reserved_4[0x40];
4331
4332 struct mlx5_ifc_rqc_bits ctx;
4333};
4334
4335struct mlx5_ifc_modify_rmp_out_bits {
4336 u8 status[0x8];
4337 u8 reserved_0[0x18];
4338
4339 u8 syndrome[0x20];
4340
4341 u8 reserved_1[0x40];
4342};
4343
01949d01
HA		 4344struct mlx5_ifc_rmp_bitmask_bits {
4345 u8 reserved[0x20];
4346
4347 u8 reserved1[0x1f];
4348 u8 lwm[0x1];
4349};
4350
e281682b
SM		 4351struct mlx5_ifc_modify_rmp_in_bits {
4352 u8 opcode[0x10];
4353 u8 reserved_0[0x10];
4354
4355 u8 reserved_1[0x10];
4356 u8 op_mod[0x10];
4357
4358 u8 rmp_state[0x4];
4359 u8 reserved_2[0x4];
4360 u8 rmpn[0x18];
4361
4362 u8 reserved_3[0x20];
4363
01949d01 4364 struct mlx5_ifc_rmp_bitmask_bits bitmask;
e281682b
SM		 4365
4366 u8 reserved_4[0x40];
4367
4368 struct mlx5_ifc_rmpc_bits ctx;
4369};
4370
4371struct mlx5_ifc_modify_nic_vport_context_out_bits {
4372 u8 status[0x8];
4373 u8 reserved_0[0x18];
4374
4375 u8 syndrome[0x20];
4376
4377 u8 reserved_1[0x40];
4378};
4379
4380struct mlx5_ifc_modify_nic_vport_field_select_bits {
d82b7318
SM		 4381 u8 reserved_0[0x19];
4382 u8 mtu[0x1];
4383 u8 change_event[0x1];
4384 u8 promisc[0x1];
e281682b
SM		 4385 u8 permanent_address[0x1];
4386 u8 addresses_list[0x1];
4387 u8 roce_en[0x1];
4388 u8 reserved_1[0x1];
4389};
4390
4391struct mlx5_ifc_modify_nic_vport_context_in_bits {
4392 u8 opcode[0x10];
4393 u8 reserved_0[0x10];
4394
4395 u8 reserved_1[0x10];
4396 u8 op_mod[0x10];
4397
4398 u8 other_vport[0x1];
4399 u8 reserved_2[0xf];
4400 u8 vport_number[0x10];
4401
4402 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
4403
4404 u8 reserved_3[0x780];
4405
4406 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4407};
4408
4409struct mlx5_ifc_modify_hca_vport_context_out_bits {
4410 u8 status[0x8];
4411 u8 reserved_0[0x18];
4412
4413 u8 syndrome[0x20];
4414
4415 u8 reserved_1[0x40];
4416};
4417
4418struct mlx5_ifc_modify_hca_vport_context_in_bits {
4419 u8 opcode[0x10];
4420 u8 reserved_0[0x10];
4421
4422 u8 reserved_1[0x10];
4423 u8 op_mod[0x10];
4424
4425 u8 other_vport[0x1];
707c4602
MD		 4426 u8 reserved_2[0xb];
4427 u8 port_num[0x4];
e281682b
SM		 4428 u8 vport_number[0x10];
4429
4430 u8 reserved_3[0x20];
4431
4432 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4433};
4434
4435struct mlx5_ifc_modify_cq_out_bits {
4436 u8 status[0x8];
4437 u8 reserved_0[0x18];
4438
4439 u8 syndrome[0x20];
4440
4441 u8 reserved_1[0x40];
4442};
4443
4444enum {
4445 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
4446 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
4447};
4448
4449struct mlx5_ifc_modify_cq_in_bits {
4450 u8 opcode[0x10];
4451 u8 reserved_0[0x10];
4452
4453 u8 reserved_1[0x10];
4454 u8 op_mod[0x10];
4455
4456 u8 reserved_2[0x8];
4457 u8 cqn[0x18];
4458
4459 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
4460
4461 struct mlx5_ifc_cqc_bits cq_context;
4462
4463 u8 reserved_3[0x600];
4464
4465 u8 pas[0][0x40];
4466};
4467
4468struct mlx5_ifc_modify_cong_status_out_bits {
4469 u8 status[0x8];
4470 u8 reserved_0[0x18];
4471
4472 u8 syndrome[0x20];
4473
4474 u8 reserved_1[0x40];
4475};
4476
4477struct mlx5_ifc_modify_cong_status_in_bits {
4478 u8 opcode[0x10];
4479 u8 reserved_0[0x10];
4480
4481 u8 reserved_1[0x10];
4482 u8 op_mod[0x10];
4483
4484 u8 reserved_2[0x18];
4485 u8 priority[0x4];
4486 u8 cong_protocol[0x4];
4487
4488 u8 enable[0x1];
4489 u8 tag_enable[0x1];
4490 u8 reserved_3[0x1e];
4491};
4492
4493struct mlx5_ifc_modify_cong_params_out_bits {
4494 u8 status[0x8];
4495 u8 reserved_0[0x18];
4496
4497 u8 syndrome[0x20];
4498
4499 u8 reserved_1[0x40];
4500};
4501
4502struct mlx5_ifc_modify_cong_params_in_bits {
4503 u8 opcode[0x10];
4504 u8 reserved_0[0x10];
4505
4506 u8 reserved_1[0x10];
4507 u8 op_mod[0x10];
4508
4509 u8 reserved_2[0x1c];
4510 u8 cong_protocol[0x4];
4511
4512 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
4513
4514 u8 reserved_3[0x80];
4515
4516 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4517};
4518
4519struct mlx5_ifc_manage_pages_out_bits {
4520 u8 status[0x8];
4521 u8 reserved_0[0x18];
4522
4523 u8 syndrome[0x20];
4524
4525 u8 output_num_entries[0x20];
4526
4527 u8 reserved_1[0x20];
4528
4529 u8 pas[0][0x40];
4530};
4531
4532enum {
4533 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
4534 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
4535 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
4536};
4537
4538struct mlx5_ifc_manage_pages_in_bits {
4539 u8 opcode[0x10];
4540 u8 reserved_0[0x10];
4541
4542 u8 reserved_1[0x10];
4543 u8 op_mod[0x10];
4544
4545 u8 reserved_2[0x10];
4546 u8 function_id[0x10];
4547
4548 u8 input_num_entries[0x20];
4549
4550 u8 pas[0][0x40];
4551};
4552
4553struct mlx5_ifc_mad_ifc_out_bits {
4554 u8 status[0x8];
4555 u8 reserved_0[0x18];
4556
4557 u8 syndrome[0x20];
4558
4559 u8 reserved_1[0x40];
4560
4561 u8 response_mad_packet[256][0x8];
4562};
4563
4564struct mlx5_ifc_mad_ifc_in_bits {
4565 u8 opcode[0x10];
4566 u8 reserved_0[0x10];
4567
4568 u8 reserved_1[0x10];
4569 u8 op_mod[0x10];
4570
4571 u8 remote_lid[0x10];
4572 u8 reserved_2[0x8];
4573 u8 port[0x8];
4574
4575 u8 reserved_3[0x20];
4576
4577 u8 mad[256][0x8];
4578};
4579
4580struct mlx5_ifc_init_hca_out_bits {
4581 u8 status[0x8];
4582 u8 reserved_0[0x18];
4583
4584 u8 syndrome[0x20];
4585
4586 u8 reserved_1[0x40];
4587};
4588
4589struct mlx5_ifc_init_hca_in_bits {
4590 u8 opcode[0x10];
4591 u8 reserved_0[0x10];
4592
4593 u8 reserved_1[0x10];
4594 u8 op_mod[0x10];
4595
4596 u8 reserved_2[0x40];
4597};
4598
4599struct mlx5_ifc_init2rtr_qp_out_bits {
4600 u8 status[0x8];
4601 u8 reserved_0[0x18];
4602
4603 u8 syndrome[0x20];
4604
4605 u8 reserved_1[0x40];
4606};
4607
4608struct mlx5_ifc_init2rtr_qp_in_bits {
4609 u8 opcode[0x10];
4610 u8 reserved_0[0x10];
4611
4612 u8 reserved_1[0x10];
4613 u8 op_mod[0x10];
4614
4615 u8 reserved_2[0x8];
4616 u8 qpn[0x18];
4617
4618 u8 reserved_3[0x20];
4619
4620 u8 opt_param_mask[0x20];
4621
4622 u8 reserved_4[0x20];
4623
4624 struct mlx5_ifc_qpc_bits qpc;
4625
4626 u8 reserved_5[0x80];
4627};
4628
4629struct mlx5_ifc_init2init_qp_out_bits {
4630 u8 status[0x8];
4631 u8 reserved_0[0x18];
4632
4633 u8 syndrome[0x20];
4634
4635 u8 reserved_1[0x40];
4636};
4637
4638struct mlx5_ifc_init2init_qp_in_bits {
4639 u8 opcode[0x10];
4640 u8 reserved_0[0x10];
4641
4642 u8 reserved_1[0x10];
4643 u8 op_mod[0x10];
4644
4645 u8 reserved_2[0x8];
4646 u8 qpn[0x18];
4647
4648 u8 reserved_3[0x20];
4649
4650 u8 opt_param_mask[0x20];
4651
4652 u8 reserved_4[0x20];
4653
4654 struct mlx5_ifc_qpc_bits qpc;
4655
4656 u8 reserved_5[0x80];
4657};
4658
4659struct mlx5_ifc_get_dropped_packet_log_out_bits {
4660 u8 status[0x8];
4661 u8 reserved_0[0x18];
4662
4663 u8 syndrome[0x20];
4664
4665 u8 reserved_1[0x40];
4666
4667 u8 packet_headers_log[128][0x8];
4668
4669 u8 packet_syndrome[64][0x8];
4670};
4671
4672struct mlx5_ifc_get_dropped_packet_log_in_bits {
4673 u8 opcode[0x10];
4674 u8 reserved_0[0x10];
4675
4676 u8 reserved_1[0x10];
4677 u8 op_mod[0x10];
4678
4679 u8 reserved_2[0x40];
4680};
4681
4682struct mlx5_ifc_gen_eqe_in_bits {
4683 u8 opcode[0x10];
4684 u8 reserved_0[0x10];
4685
4686 u8 reserved_1[0x10];
4687 u8 op_mod[0x10];
4688
4689 u8 reserved_2[0x18];
4690 u8 eq_number[0x8];
4691
4692 u8 reserved_3[0x20];
4693
4694 u8 eqe[64][0x8];
4695};
4696
4697struct mlx5_ifc_gen_eq_out_bits {
4698 u8 status[0x8];
4699 u8 reserved_0[0x18];
4700
4701 u8 syndrome[0x20];
4702
4703 u8 reserved_1[0x40];
4704};
4705
4706struct mlx5_ifc_enable_hca_out_bits {
4707 u8 status[0x8];
4708 u8 reserved_0[0x18];
4709
4710 u8 syndrome[0x20];
4711
4712 u8 reserved_1[0x20];
4713};
4714
4715struct mlx5_ifc_enable_hca_in_bits {
4716 u8 opcode[0x10];
4717 u8 reserved_0[0x10];
4718
4719 u8 reserved_1[0x10];
4720 u8 op_mod[0x10];
4721
4722 u8 reserved_2[0x10];
4723 u8 function_id[0x10];
4724
4725 u8 reserved_3[0x20];
4726};
4727
4728struct mlx5_ifc_drain_dct_out_bits {
4729 u8 status[0x8];
4730 u8 reserved_0[0x18];
4731
4732 u8 syndrome[0x20];
4733
4734 u8 reserved_1[0x40];
4735};
4736
4737struct mlx5_ifc_drain_dct_in_bits {
4738 u8 opcode[0x10];
4739 u8 reserved_0[0x10];
4740
4741 u8 reserved_1[0x10];
4742 u8 op_mod[0x10];
4743
4744 u8 reserved_2[0x8];
4745 u8 dctn[0x18];
4746
4747 u8 reserved_3[0x20];
4748};
4749
4750struct mlx5_ifc_disable_hca_out_bits {
4751 u8 status[0x8];
4752 u8 reserved_0[0x18];
4753
4754 u8 syndrome[0x20];
4755
4756 u8 reserved_1[0x20];
4757};
4758
4759struct mlx5_ifc_disable_hca_in_bits {
4760 u8 opcode[0x10];
4761 u8 reserved_0[0x10];
4762
4763 u8 reserved_1[0x10];
4764 u8 op_mod[0x10];
4765
4766 u8 reserved_2[0x10];
4767 u8 function_id[0x10];
4768
4769 u8 reserved_3[0x20];
4770};
4771
4772struct mlx5_ifc_detach_from_mcg_out_bits {
4773 u8 status[0x8];
4774 u8 reserved_0[0x18];
4775
4776 u8 syndrome[0x20];
4777
4778 u8 reserved_1[0x40];
4779};
4780
4781struct mlx5_ifc_detach_from_mcg_in_bits {
4782 u8 opcode[0x10];
4783 u8 reserved_0[0x10];
4784
4785 u8 reserved_1[0x10];
4786 u8 op_mod[0x10];
4787
4788 u8 reserved_2[0x8];
4789 u8 qpn[0x18];
4790
4791 u8 reserved_3[0x20];
4792
4793 u8 multicast_gid[16][0x8];
4794};
4795
4796struct mlx5_ifc_destroy_xrc_srq_out_bits {
4797 u8 status[0x8];
4798 u8 reserved_0[0x18];
4799
4800 u8 syndrome[0x20];
4801
4802 u8 reserved_1[0x40];
4803};
4804
4805struct mlx5_ifc_destroy_xrc_srq_in_bits {
4806 u8 opcode[0x10];
4807 u8 reserved_0[0x10];
4808
4809 u8 reserved_1[0x10];
4810 u8 op_mod[0x10];
4811
4812 u8 reserved_2[0x8];
4813 u8 xrc_srqn[0x18];
4814
4815 u8 reserved_3[0x20];
4816};
4817
4818struct mlx5_ifc_destroy_tis_out_bits {
4819 u8 status[0x8];
4820 u8 reserved_0[0x18];
4821
4822 u8 syndrome[0x20];
4823
4824 u8 reserved_1[0x40];
4825};
4826
4827struct mlx5_ifc_destroy_tis_in_bits {
4828 u8 opcode[0x10];
4829 u8 reserved_0[0x10];
4830
4831 u8 reserved_1[0x10];
4832 u8 op_mod[0x10];
4833
4834 u8 reserved_2[0x8];
4835 u8 tisn[0x18];
4836
4837 u8 reserved_3[0x20];
4838};
4839
4840struct mlx5_ifc_destroy_tir_out_bits {
4841 u8 status[0x8];
4842 u8 reserved_0[0x18];
4843
4844 u8 syndrome[0x20];
4845
4846 u8 reserved_1[0x40];
4847};
4848
4849struct mlx5_ifc_destroy_tir_in_bits {
4850 u8 opcode[0x10];
4851 u8 reserved_0[0x10];
4852
4853 u8 reserved_1[0x10];
4854 u8 op_mod[0x10];
4855
4856 u8 reserved_2[0x8];
4857 u8 tirn[0x18];
4858
4859 u8 reserved_3[0x20];
4860};
4861
4862struct mlx5_ifc_destroy_srq_out_bits {
4863 u8 status[0x8];
4864 u8 reserved_0[0x18];
4865
4866 u8 syndrome[0x20];
4867
4868 u8 reserved_1[0x40];
4869};
4870
4871struct mlx5_ifc_destroy_srq_in_bits {
4872 u8 opcode[0x10];
4873 u8 reserved_0[0x10];
4874
4875 u8 reserved_1[0x10];
4876 u8 op_mod[0x10];
4877
4878 u8 reserved_2[0x8];
4879 u8 srqn[0x18];
4880
4881 u8 reserved_3[0x20];
4882};
4883
4884struct mlx5_ifc_destroy_sq_out_bits {
4885 u8 status[0x8];
4886 u8 reserved_0[0x18];
4887
4888 u8 syndrome[0x20];
4889
4890 u8 reserved_1[0x40];
4891};
4892
4893struct mlx5_ifc_destroy_sq_in_bits {
4894 u8 opcode[0x10];
4895 u8 reserved_0[0x10];
4896
4897 u8 reserved_1[0x10];
4898 u8 op_mod[0x10];
4899
4900 u8 reserved_2[0x8];
4901 u8 sqn[0x18];
4902
4903 u8 reserved_3[0x20];
4904};
4905
4906struct mlx5_ifc_destroy_rqt_out_bits {
4907 u8 status[0x8];
4908 u8 reserved_0[0x18];
4909
4910 u8 syndrome[0x20];
4911
4912 u8 reserved_1[0x40];
4913};
4914
4915struct mlx5_ifc_destroy_rqt_in_bits {
4916 u8 opcode[0x10];
4917 u8 reserved_0[0x10];
4918
4919 u8 reserved_1[0x10];
4920 u8 op_mod[0x10];
4921
4922 u8 reserved_2[0x8];
4923 u8 rqtn[0x18];
4924
4925 u8 reserved_3[0x20];
4926};
4927
4928struct mlx5_ifc_destroy_rq_out_bits {
4929 u8 status[0x8];
4930 u8 reserved_0[0x18];
4931
4932 u8 syndrome[0x20];
4933
4934 u8 reserved_1[0x40];
4935};
4936
4937struct mlx5_ifc_destroy_rq_in_bits {
4938 u8 opcode[0x10];
4939 u8 reserved_0[0x10];
4940
4941 u8 reserved_1[0x10];
4942 u8 op_mod[0x10];
4943
4944 u8 reserved_2[0x8];
4945 u8 rqn[0x18];
4946
4947 u8 reserved_3[0x20];
4948};
4949
4950struct mlx5_ifc_destroy_rmp_out_bits {
4951 u8 status[0x8];
4952 u8 reserved_0[0x18];
4953
4954 u8 syndrome[0x20];
4955
4956 u8 reserved_1[0x40];
4957};
4958
4959struct mlx5_ifc_destroy_rmp_in_bits {
4960 u8 opcode[0x10];
4961 u8 reserved_0[0x10];
4962
4963 u8 reserved_1[0x10];
4964 u8 op_mod[0x10];
4965
4966 u8 reserved_2[0x8];
4967 u8 rmpn[0x18];
4968
4969 u8 reserved_3[0x20];
4970};
4971
4972struct mlx5_ifc_destroy_qp_out_bits {
4973 u8 status[0x8];
4974 u8 reserved_0[0x18];
4975
4976 u8 syndrome[0x20];
4977
4978 u8 reserved_1[0x40];
4979};
4980
4981struct mlx5_ifc_destroy_qp_in_bits {
4982 u8 opcode[0x10];
4983 u8 reserved_0[0x10];
4984
4985 u8 reserved_1[0x10];
4986 u8 op_mod[0x10];
4987
4988 u8 reserved_2[0x8];
4989 u8 qpn[0x18];
4990
4991 u8 reserved_3[0x20];
4992};
4993
4994struct mlx5_ifc_destroy_psv_out_bits {
4995 u8 status[0x8];
4996 u8 reserved_0[0x18];
4997
4998 u8 syndrome[0x20];
4999
5000 u8 reserved_1[0x40];
5001};
5002
5003struct mlx5_ifc_destroy_psv_in_bits {
5004 u8 opcode[0x10];
5005 u8 reserved_0[0x10];
5006
5007 u8 reserved_1[0x10];
5008 u8 op_mod[0x10];
5009
5010 u8 reserved_2[0x8];
5011 u8 psvn[0x18];
5012
5013 u8 reserved_3[0x20];
5014};
5015
5016struct mlx5_ifc_destroy_mkey_out_bits {
5017 u8 status[0x8];
5018 u8 reserved_0[0x18];
5019
5020 u8 syndrome[0x20];
5021
5022 u8 reserved_1[0x40];
5023};
5024
5025struct mlx5_ifc_destroy_mkey_in_bits {
5026 u8 opcode[0x10];
5027 u8 reserved_0[0x10];
5028
5029 u8 reserved_1[0x10];
5030 u8 op_mod[0x10];
5031
5032 u8 reserved_2[0x8];
5033 u8 mkey_index[0x18];
5034
5035 u8 reserved_3[0x20];
5036};
5037
5038struct mlx5_ifc_destroy_flow_table_out_bits {
5039 u8 status[0x8];
5040 u8 reserved_0[0x18];
5041
5042 u8 syndrome[0x20];
5043
5044 u8 reserved_1[0x40];
5045};
5046
5047struct mlx5_ifc_destroy_flow_table_in_bits {
5048 u8 opcode[0x10];
5049 u8 reserved_0[0x10];
5050
5051 u8 reserved_1[0x10];
5052 u8 op_mod[0x10];
5053
5054 u8 reserved_2[0x40];
5055
5056 u8 table_type[0x8];
5057 u8 reserved_3[0x18];
5058
5059 u8 reserved_4[0x8];
5060 u8 table_id[0x18];
5061
5062 u8 reserved_5[0x140];
5063};
5064
5065struct mlx5_ifc_destroy_flow_group_out_bits {
5066 u8 status[0x8];
5067 u8 reserved_0[0x18];
5068
5069 u8 syndrome[0x20];
5070
5071 u8 reserved_1[0x40];
5072};
5073
5074struct mlx5_ifc_destroy_flow_group_in_bits {
5075 u8 opcode[0x10];
5076 u8 reserved_0[0x10];
5077
5078 u8 reserved_1[0x10];
5079 u8 op_mod[0x10];
5080
5081 u8 reserved_2[0x40];
5082
5083 u8 table_type[0x8];
5084 u8 reserved_3[0x18];
5085
5086 u8 reserved_4[0x8];
5087 u8 table_id[0x18];
5088
5089 u8 group_id[0x20];
5090
5091 u8 reserved_5[0x120];
5092};
5093
5094struct mlx5_ifc_destroy_eq_out_bits {
5095 u8 status[0x8];
5096 u8 reserved_0[0x18];
5097
5098 u8 syndrome[0x20];
5099
5100 u8 reserved_1[0x40];
5101};
5102
5103struct mlx5_ifc_destroy_eq_in_bits {
5104 u8 opcode[0x10];
5105 u8 reserved_0[0x10];
5106
5107 u8 reserved_1[0x10];
5108 u8 op_mod[0x10];
5109
5110 u8 reserved_2[0x18];
5111 u8 eq_number[0x8];
5112
5113 u8 reserved_3[0x20];
5114};
5115
5116struct mlx5_ifc_destroy_dct_out_bits {
5117 u8 status[0x8];
5118 u8 reserved_0[0x18];
5119
5120 u8 syndrome[0x20];
5121
5122 u8 reserved_1[0x40];
5123};
5124
5125struct mlx5_ifc_destroy_dct_in_bits {
5126 u8 opcode[0x10];
5127 u8 reserved_0[0x10];
5128
5129 u8 reserved_1[0x10];
5130 u8 op_mod[0x10];
5131
5132 u8 reserved_2[0x8];
5133 u8 dctn[0x18];
5134
5135 u8 reserved_3[0x20];
5136};
5137
5138struct mlx5_ifc_destroy_cq_out_bits {
5139 u8 status[0x8];
5140 u8 reserved_0[0x18];
5141
5142 u8 syndrome[0x20];
5143
5144 u8 reserved_1[0x40];
5145};
5146
5147struct mlx5_ifc_destroy_cq_in_bits {
5148 u8 opcode[0x10];
5149 u8 reserved_0[0x10];
5150
5151 u8 reserved_1[0x10];
5152 u8 op_mod[0x10];
5153
5154 u8 reserved_2[0x8];
5155 u8 cqn[0x18];
5156
5157 u8 reserved_3[0x20];
5158};
5159
5160struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
5161 u8 status[0x8];
5162 u8 reserved_0[0x18];
5163
5164 u8 syndrome[0x20];
5165
5166 u8 reserved_1[0x40];
5167};
5168
5169struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
5170 u8 opcode[0x10];
5171 u8 reserved_0[0x10];
5172
5173 u8 reserved_1[0x10];
5174 u8 op_mod[0x10];
5175
5176 u8 reserved_2[0x20];
5177
5178 u8 reserved_3[0x10];
5179 u8 vxlan_udp_port[0x10];
5180};
5181
5182struct mlx5_ifc_delete_l2_table_entry_out_bits {
5183 u8 status[0x8];
5184 u8 reserved_0[0x18];
5185
5186 u8 syndrome[0x20];
5187
5188 u8 reserved_1[0x40];
5189};
5190
5191struct mlx5_ifc_delete_l2_table_entry_in_bits {
5192 u8 opcode[0x10];
5193 u8 reserved_0[0x10];
5194
5195 u8 reserved_1[0x10];
5196 u8 op_mod[0x10];
5197
5198 u8 reserved_2[0x60];
5199
5200 u8 reserved_3[0x8];
5201 u8 table_index[0x18];
5202
5203 u8 reserved_4[0x140];
5204};
5205
5206struct mlx5_ifc_delete_fte_out_bits {
5207 u8 status[0x8];
5208 u8 reserved_0[0x18];
5209
5210 u8 syndrome[0x20];
5211
5212 u8 reserved_1[0x40];
5213};
5214
5215struct mlx5_ifc_delete_fte_in_bits {
5216 u8 opcode[0x10];
5217 u8 reserved_0[0x10];
5218
5219 u8 reserved_1[0x10];
5220 u8 op_mod[0x10];
5221
5222 u8 reserved_2[0x40];
5223
5224 u8 table_type[0x8];
5225 u8 reserved_3[0x18];
5226
5227 u8 reserved_4[0x8];
5228 u8 table_id[0x18];
5229
5230 u8 reserved_5[0x40];
5231
5232 u8 flow_index[0x20];
5233
5234 u8 reserved_6[0xe0];
5235};
5236
5237struct mlx5_ifc_dealloc_xrcd_out_bits {
5238 u8 status[0x8];
5239 u8 reserved_0[0x18];
5240
5241 u8 syndrome[0x20];
5242
5243 u8 reserved_1[0x40];
5244};
5245
5246struct mlx5_ifc_dealloc_xrcd_in_bits {
5247 u8 opcode[0x10];
5248 u8 reserved_0[0x10];
5249
5250 u8 reserved_1[0x10];
5251 u8 op_mod[0x10];
5252
5253 u8 reserved_2[0x8];
5254 u8 xrcd[0x18];
5255
5256 u8 reserved_3[0x20];
5257};
5258
5259struct mlx5_ifc_dealloc_uar_out_bits {
5260 u8 status[0x8];
5261 u8 reserved_0[0x18];
5262
5263 u8 syndrome[0x20];
5264
5265 u8 reserved_1[0x40];
5266};
5267
5268struct mlx5_ifc_dealloc_uar_in_bits {
5269 u8 opcode[0x10];
5270 u8 reserved_0[0x10];
5271
5272 u8 reserved_1[0x10];
5273 u8 op_mod[0x10];
5274
5275 u8 reserved_2[0x8];
5276 u8 uar[0x18];
5277
5278 u8 reserved_3[0x20];
5279};
5280
5281struct mlx5_ifc_dealloc_transport_domain_out_bits {
5282 u8 status[0x8];
5283 u8 reserved_0[0x18];
5284
5285 u8 syndrome[0x20];
5286
5287 u8 reserved_1[0x40];
5288};
5289
5290struct mlx5_ifc_dealloc_transport_domain_in_bits {
5291 u8 opcode[0x10];
5292 u8 reserved_0[0x10];
5293
5294 u8 reserved_1[0x10];
5295 u8 op_mod[0x10];
5296
5297 u8 reserved_2[0x8];
5298 u8 transport_domain[0x18];
5299
5300 u8 reserved_3[0x20];
5301};
5302
5303struct mlx5_ifc_dealloc_q_counter_out_bits {
5304 u8 status[0x8];
5305 u8 reserved_0[0x18];
5306
5307 u8 syndrome[0x20];
5308
5309 u8 reserved_1[0x40];
5310};
5311
5312struct mlx5_ifc_dealloc_q_counter_in_bits {
5313 u8 opcode[0x10];
5314 u8 reserved_0[0x10];
5315
5316 u8 reserved_1[0x10];
5317 u8 op_mod[0x10];
5318
5319 u8 reserved_2[0x18];
5320 u8 counter_set_id[0x8];
5321
5322 u8 reserved_3[0x20];
5323};
5324
5325struct mlx5_ifc_dealloc_pd_out_bits {
5326 u8 status[0x8];
5327 u8 reserved_0[0x18];
5328
5329 u8 syndrome[0x20];
5330
5331 u8 reserved_1[0x40];
5332};
5333
5334struct mlx5_ifc_dealloc_pd_in_bits {
5335 u8 opcode[0x10];
5336 u8 reserved_0[0x10];
5337
5338 u8 reserved_1[0x10];
5339 u8 op_mod[0x10];
5340
5341 u8 reserved_2[0x8];
5342 u8 pd[0x18];
5343
5344 u8 reserved_3[0x20];
5345};
5346
5347struct mlx5_ifc_create_xrc_srq_out_bits {
5348 u8 status[0x8];
5349 u8 reserved_0[0x18];
5350
5351 u8 syndrome[0x20];
5352
5353 u8 reserved_1[0x8];
5354 u8 xrc_srqn[0x18];
5355
5356 u8 reserved_2[0x20];
5357};
5358
5359struct mlx5_ifc_create_xrc_srq_in_bits {
5360 u8 opcode[0x10];
5361 u8 reserved_0[0x10];
5362
5363 u8 reserved_1[0x10];
5364 u8 op_mod[0x10];
5365
5366 u8 reserved_2[0x40];
5367
5368 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
5369
5370 u8 reserved_3[0x600];
5371
5372 u8 pas[0][0x40];
5373};
5374
5375struct mlx5_ifc_create_tis_out_bits {
5376 u8 status[0x8];
5377 u8 reserved_0[0x18];
5378
5379 u8 syndrome[0x20];
5380
5381 u8 reserved_1[0x8];
5382 u8 tisn[0x18];
5383
5384 u8 reserved_2[0x20];
5385};
5386
5387struct mlx5_ifc_create_tis_in_bits {
5388 u8 opcode[0x10];
5389 u8 reserved_0[0x10];
5390
5391 u8 reserved_1[0x10];
5392 u8 op_mod[0x10];
5393
5394 u8 reserved_2[0xc0];
5395
5396 struct mlx5_ifc_tisc_bits ctx;
5397};
5398
5399struct mlx5_ifc_create_tir_out_bits {
5400 u8 status[0x8];
5401 u8 reserved_0[0x18];
5402
5403 u8 syndrome[0x20];
5404
5405 u8 reserved_1[0x8];
5406 u8 tirn[0x18];
5407
5408 u8 reserved_2[0x20];
5409};
5410
5411struct mlx5_ifc_create_tir_in_bits {
5412 u8 opcode[0x10];
5413 u8 reserved_0[0x10];
5414
5415 u8 reserved_1[0x10];
5416 u8 op_mod[0x10];
5417
5418 u8 reserved_2[0xc0];
5419
5420 struct mlx5_ifc_tirc_bits ctx;
5421};
5422
5423struct mlx5_ifc_create_srq_out_bits {
5424 u8 status[0x8];
5425 u8 reserved_0[0x18];
5426
5427 u8 syndrome[0x20];
5428
5429 u8 reserved_1[0x8];
5430 u8 srqn[0x18];
5431
5432 u8 reserved_2[0x20];
5433};
5434
5435struct mlx5_ifc_create_srq_in_bits {
5436 u8 opcode[0x10];
5437 u8 reserved_0[0x10];
5438
5439 u8 reserved_1[0x10];
5440 u8 op_mod[0x10];
5441
5442 u8 reserved_2[0x40];
5443
5444 struct mlx5_ifc_srqc_bits srq_context_entry;
5445
5446 u8 reserved_3[0x600];
5447
5448 u8 pas[0][0x40];
5449};
5450
5451struct mlx5_ifc_create_sq_out_bits {
5452 u8 status[0x8];
5453 u8 reserved_0[0x18];
5454
5455 u8 syndrome[0x20];
5456
5457 u8 reserved_1[0x8];
5458 u8 sqn[0x18];
5459
5460 u8 reserved_2[0x20];
5461};
5462
5463struct mlx5_ifc_create_sq_in_bits {
5464 u8 opcode[0x10];
5465 u8 reserved_0[0x10];
5466
5467 u8 reserved_1[0x10];
5468 u8 op_mod[0x10];
5469
5470 u8 reserved_2[0xc0];
5471
5472 struct mlx5_ifc_sqc_bits ctx;
5473};
5474
5475struct mlx5_ifc_create_rqt_out_bits {
5476 u8 status[0x8];
5477 u8 reserved_0[0x18];
5478
5479 u8 syndrome[0x20];
5480
5481 u8 reserved_1[0x8];
5482 u8 rqtn[0x18];
5483
5484 u8 reserved_2[0x20];
5485};
5486
5487struct mlx5_ifc_create_rqt_in_bits {
5488 u8 opcode[0x10];
5489 u8 reserved_0[0x10];
5490
5491 u8 reserved_1[0x10];
5492 u8 op_mod[0x10];
5493
5494 u8 reserved_2[0xc0];
5495
5496 struct mlx5_ifc_rqtc_bits rqt_context;
5497};
5498
5499struct mlx5_ifc_create_rq_out_bits {
5500 u8 status[0x8];
5501 u8 reserved_0[0x18];
5502
5503 u8 syndrome[0x20];
5504
5505 u8 reserved_1[0x8];
5506 u8 rqn[0x18];
5507
5508 u8 reserved_2[0x20];
5509};
5510
5511struct mlx5_ifc_create_rq_in_bits {
5512 u8 opcode[0x10];
5513 u8 reserved_0[0x10];
5514
5515 u8 reserved_1[0x10];
5516 u8 op_mod[0x10];
5517
5518 u8 reserved_2[0xc0];
5519
5520 struct mlx5_ifc_rqc_bits ctx;
5521};
5522
5523struct mlx5_ifc_create_rmp_out_bits {
5524 u8 status[0x8];
5525 u8 reserved_0[0x18];
5526
5527 u8 syndrome[0x20];
5528
5529 u8 reserved_1[0x8];
5530 u8 rmpn[0x18];
5531
5532 u8 reserved_2[0x20];
5533};
5534
5535struct mlx5_ifc_create_rmp_in_bits {
5536 u8 opcode[0x10];
5537 u8 reserved_0[0x10];
5538
5539 u8 reserved_1[0x10];
5540 u8 op_mod[0x10];
5541
5542 u8 reserved_2[0xc0];
5543
5544 struct mlx5_ifc_rmpc_bits ctx;
5545};
5546
5547struct mlx5_ifc_create_qp_out_bits {
5548 u8 status[0x8];
5549 u8 reserved_0[0x18];
5550
5551 u8 syndrome[0x20];
5552
5553 u8 reserved_1[0x8];
5554 u8 qpn[0x18];
5555
5556 u8 reserved_2[0x20];
5557};
5558
5559struct mlx5_ifc_create_qp_in_bits {
5560 u8 opcode[0x10];
5561 u8 reserved_0[0x10];
5562
5563 u8 reserved_1[0x10];
5564 u8 op_mod[0x10];
5565
5566 u8 reserved_2[0x40];
5567
5568 u8 opt_param_mask[0x20];
5569
5570 u8 reserved_3[0x20];
5571
5572 struct mlx5_ifc_qpc_bits qpc;
5573
5574 u8 reserved_4[0x80];
5575
5576 u8 pas[0][0x40];
5577};
5578
5579struct mlx5_ifc_create_psv_out_bits {
5580 u8 status[0x8];
5581 u8 reserved_0[0x18];
5582
5583 u8 syndrome[0x20];
5584
5585 u8 reserved_1[0x40];
5586
5587 u8 reserved_2[0x8];
5588 u8 psv0_index[0x18];
5589
5590 u8 reserved_3[0x8];
5591 u8 psv1_index[0x18];
5592
5593 u8 reserved_4[0x8];
5594 u8 psv2_index[0x18];
5595
5596 u8 reserved_5[0x8];
5597 u8 psv3_index[0x18];
5598};
5599
5600struct mlx5_ifc_create_psv_in_bits {
5601 u8 opcode[0x10];
5602 u8 reserved_0[0x10];
5603
5604 u8 reserved_1[0x10];
5605 u8 op_mod[0x10];
5606
5607 u8 num_psv[0x4];
5608 u8 reserved_2[0x4];
5609 u8 pd[0x18];
5610
5611 u8 reserved_3[0x20];
5612};
5613
5614struct mlx5_ifc_create_mkey_out_bits {
5615 u8 status[0x8];
5616 u8 reserved_0[0x18];
5617
5618 u8 syndrome[0x20];
5619
5620 u8 reserved_1[0x8];
5621 u8 mkey_index[0x18];
5622
5623 u8 reserved_2[0x20];
5624};
5625
5626struct mlx5_ifc_create_mkey_in_bits {
5627 u8 opcode[0x10];
5628 u8 reserved_0[0x10];
5629
5630 u8 reserved_1[0x10];
5631 u8 op_mod[0x10];
5632
5633 u8 reserved_2[0x20];
5634
5635 u8 pg_access[0x1];
5636 u8 reserved_3[0x1f];
5637
5638 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5639
5640 u8 reserved_4[0x80];
5641
5642 u8 translations_octword_actual_size[0x20];
5643
5644 u8 reserved_5[0x560];
5645
5646 u8 klm_pas_mtt[0][0x20];
5647};
5648
5649struct mlx5_ifc_create_flow_table_out_bits {
5650 u8 status[0x8];
5651 u8 reserved_0[0x18];
5652
5653 u8 syndrome[0x20];
5654
5655 u8 reserved_1[0x8];
5656 u8 table_id[0x18];
5657
5658 u8 reserved_2[0x20];
5659};
5660
5661struct mlx5_ifc_create_flow_table_in_bits {
5662 u8 opcode[0x10];
5663 u8 reserved_0[0x10];
5664
5665 u8 reserved_1[0x10];
5666 u8 op_mod[0x10];
5667
5668 u8 reserved_2[0x40];
5669
5670 u8 table_type[0x8];
5671 u8 reserved_3[0x18];
5672
5673 u8 reserved_4[0x20];
5674
34a40e68
MG		 5675 u8 reserved_5[0x4];
5676 u8 table_miss_mode[0x4];
e281682b
SM		 5677 u8 level[0x8];
5678 u8 reserved_6[0x8];
5679 u8 log_size[0x8];
5680
34a40e68
MG		 5681 u8 reserved_7[0x8];
5682 u8 table_miss_id[0x18];
5683
5684 u8 reserved_8[0x100];
e281682b
SM		 5685};
5686
5687struct mlx5_ifc_create_flow_group_out_bits {
5688 u8 status[0x8];
5689 u8 reserved_0[0x18];
5690
5691 u8 syndrome[0x20];
5692
5693 u8 reserved_1[0x8];
5694 u8 group_id[0x18];
5695
5696 u8 reserved_2[0x20];
5697};
5698
5699enum {
5700 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
5701 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
5702 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
5703};
5704
5705struct mlx5_ifc_create_flow_group_in_bits {
5706 u8 opcode[0x10];
5707 u8 reserved_0[0x10];
5708
5709 u8 reserved_1[0x10];
5710 u8 op_mod[0x10];
5711
5712 u8 reserved_2[0x40];
5713
5714 u8 table_type[0x8];
5715 u8 reserved_3[0x18];
5716
5717 u8 reserved_4[0x8];
5718 u8 table_id[0x18];
5719
5720 u8 reserved_5[0x20];
5721
5722 u8 start_flow_index[0x20];
5723
5724 u8 reserved_6[0x20];
5725
5726 u8 end_flow_index[0x20];
5727
5728 u8 reserved_7[0xa0];
5729
5730 u8 reserved_8[0x18];
5731 u8 match_criteria_enable[0x8];
5732
5733 struct mlx5_ifc_fte_match_param_bits match_criteria;
5734
5735 u8 reserved_9[0xe00];
5736};
5737
5738struct mlx5_ifc_create_eq_out_bits {
5739 u8 status[0x8];
5740 u8 reserved_0[0x18];
5741
5742 u8 syndrome[0x20];
5743
5744 u8 reserved_1[0x18];
5745 u8 eq_number[0x8];
5746
5747 u8 reserved_2[0x20];
5748};
5749
5750struct mlx5_ifc_create_eq_in_bits {
5751 u8 opcode[0x10];
5752 u8 reserved_0[0x10];
5753
5754 u8 reserved_1[0x10];
5755 u8 op_mod[0x10];
5756
5757 u8 reserved_2[0x40];
5758
5759 struct mlx5_ifc_eqc_bits eq_context_entry;
5760
5761 u8 reserved_3[0x40];
5762
5763 u8 event_bitmask[0x40];
5764
5765 u8 reserved_4[0x580];
5766
5767 u8 pas[0][0x40];
5768};
5769
5770struct mlx5_ifc_create_dct_out_bits {
5771 u8 status[0x8];
5772 u8 reserved_0[0x18];
5773
5774 u8 syndrome[0x20];
5775
5776 u8 reserved_1[0x8];
5777 u8 dctn[0x18];
5778
5779 u8 reserved_2[0x20];
5780};
5781
5782struct mlx5_ifc_create_dct_in_bits {
5783 u8 opcode[0x10];
5784 u8 reserved_0[0x10];
5785
5786 u8 reserved_1[0x10];
5787 u8 op_mod[0x10];
5788
5789 u8 reserved_2[0x40];
5790
5791 struct mlx5_ifc_dctc_bits dct_context_entry;
5792
5793 u8 reserved_3[0x180];
5794};
5795
5796struct mlx5_ifc_create_cq_out_bits {
5797 u8 status[0x8];
5798 u8 reserved_0[0x18];
5799
5800 u8 syndrome[0x20];
5801
5802 u8 reserved_1[0x8];
5803 u8 cqn[0x18];
5804
5805 u8 reserved_2[0x20];
5806};
5807
5808struct mlx5_ifc_create_cq_in_bits {
5809 u8 opcode[0x10];
5810 u8 reserved_0[0x10];
5811
5812 u8 reserved_1[0x10];
5813 u8 op_mod[0x10];
5814
5815 u8 reserved_2[0x40];
5816
5817 struct mlx5_ifc_cqc_bits cq_context;
5818
5819 u8 reserved_3[0x600];
5820
5821 u8 pas[0][0x40];
5822};
5823
5824struct mlx5_ifc_config_int_moderation_out_bits {
5825 u8 status[0x8];
5826 u8 reserved_0[0x18];
5827
5828 u8 syndrome[0x20];
5829
5830 u8 reserved_1[0x4];
5831 u8 min_delay[0xc];
5832 u8 int_vector[0x10];
5833
5834 u8 reserved_2[0x20];
5835};
5836
5837enum {
5838 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
5839 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
5840};
5841
5842struct mlx5_ifc_config_int_moderation_in_bits {
5843 u8 opcode[0x10];
5844 u8 reserved_0[0x10];
5845
5846 u8 reserved_1[0x10];
5847 u8 op_mod[0x10];
5848
5849 u8 reserved_2[0x4];
5850 u8 min_delay[0xc];
5851 u8 int_vector[0x10];
5852
5853 u8 reserved_3[0x20];
5854};
5855
5856struct mlx5_ifc_attach_to_mcg_out_bits {
5857 u8 status[0x8];
5858 u8 reserved_0[0x18];
5859
5860 u8 syndrome[0x20];
5861
5862 u8 reserved_1[0x40];
5863};
5864
5865struct mlx5_ifc_attach_to_mcg_in_bits {
5866 u8 opcode[0x10];
5867 u8 reserved_0[0x10];
5868
5869 u8 reserved_1[0x10];
5870 u8 op_mod[0x10];
5871
5872 u8 reserved_2[0x8];
5873 u8 qpn[0x18];
5874
5875 u8 reserved_3[0x20];
5876
5877 u8 multicast_gid[16][0x8];
5878};
5879
5880struct mlx5_ifc_arm_xrc_srq_out_bits {
5881 u8 status[0x8];
5882 u8 reserved_0[0x18];
5883
5884 u8 syndrome[0x20];
5885
5886 u8 reserved_1[0x40];
5887};
5888
5889enum {
5890 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
5891};
5892
5893struct mlx5_ifc_arm_xrc_srq_in_bits {
5894 u8 opcode[0x10];
5895 u8 reserved_0[0x10];
5896
5897 u8 reserved_1[0x10];
5898 u8 op_mod[0x10];
5899
5900 u8 reserved_2[0x8];
5901 u8 xrc_srqn[0x18];
5902
5903 u8 reserved_3[0x10];
5904 u8 lwm[0x10];
5905};
5906
5907struct mlx5_ifc_arm_rq_out_bits {
5908 u8 status[0x8];
5909 u8 reserved_0[0x18];
5910
5911 u8 syndrome[0x20];
5912
5913 u8 reserved_1[0x40];
5914};
5915
5916enum {
5917 MLX5_ARM_RQ_IN_OP_MOD_SRQ_ = 0x1,
5918};
5919
5920struct mlx5_ifc_arm_rq_in_bits {
5921 u8 opcode[0x10];
5922 u8 reserved_0[0x10];
5923
5924 u8 reserved_1[0x10];
5925 u8 op_mod[0x10];
5926
5927 u8 reserved_2[0x8];
5928 u8 srq_number[0x18];
5929
5930 u8 reserved_3[0x10];
5931 u8 lwm[0x10];
5932};
5933
5934struct mlx5_ifc_arm_dct_out_bits {
5935 u8 status[0x8];
5936 u8 reserved_0[0x18];
5937
5938 u8 syndrome[0x20];
5939
5940 u8 reserved_1[0x40];
5941};
5942
5943struct mlx5_ifc_arm_dct_in_bits {
5944 u8 opcode[0x10];
5945 u8 reserved_0[0x10];
5946
5947 u8 reserved_1[0x10];
5948 u8 op_mod[0x10];
5949
5950 u8 reserved_2[0x8];
5951 u8 dct_number[0x18];
5952
5953 u8 reserved_3[0x20];
5954};
5955
5956struct mlx5_ifc_alloc_xrcd_out_bits {
5957 u8 status[0x8];
5958 u8 reserved_0[0x18];
5959
5960 u8 syndrome[0x20];
5961
5962 u8 reserved_1[0x8];
5963 u8 xrcd[0x18];
5964
5965 u8 reserved_2[0x20];
5966};
5967
5968struct mlx5_ifc_alloc_xrcd_in_bits {
5969 u8 opcode[0x10];
5970 u8 reserved_0[0x10];
5971
5972 u8 reserved_1[0x10];
5973 u8 op_mod[0x10];
5974
5975 u8 reserved_2[0x40];
5976};
5977
5978struct mlx5_ifc_alloc_uar_out_bits {
5979 u8 status[0x8];
5980 u8 reserved_0[0x18];
5981
5982 u8 syndrome[0x20];
5983
5984 u8 reserved_1[0x8];
5985 u8 uar[0x18];
5986
5987 u8 reserved_2[0x20];
5988};
5989
5990struct mlx5_ifc_alloc_uar_in_bits {
5991 u8 opcode[0x10];
5992 u8 reserved_0[0x10];
5993
5994 u8 reserved_1[0x10];
5995 u8 op_mod[0x10];
5996
5997 u8 reserved_2[0x40];
5998};
5999
6000struct mlx5_ifc_alloc_transport_domain_out_bits {
6001 u8 status[0x8];
6002 u8 reserved_0[0x18];
6003
6004 u8 syndrome[0x20];
6005
6006 u8 reserved_1[0x8];
6007 u8 transport_domain[0x18];
6008
6009 u8 reserved_2[0x20];
6010};
6011
6012struct mlx5_ifc_alloc_transport_domain_in_bits {
6013 u8 opcode[0x10];
6014 u8 reserved_0[0x10];
6015
6016 u8 reserved_1[0x10];
6017 u8 op_mod[0x10];
6018
6019 u8 reserved_2[0x40];
6020};
6021
6022struct mlx5_ifc_alloc_q_counter_out_bits {
6023 u8 status[0x8];
6024 u8 reserved_0[0x18];
6025
6026 u8 syndrome[0x20];
6027
6028 u8 reserved_1[0x18];
6029 u8 counter_set_id[0x8];
6030
6031 u8 reserved_2[0x20];
6032};
6033
6034struct mlx5_ifc_alloc_q_counter_in_bits {
6035 u8 opcode[0x10];
6036 u8 reserved_0[0x10];
6037
6038 u8 reserved_1[0x10];
6039 u8 op_mod[0x10];
6040
6041 u8 reserved_2[0x40];
6042};
6043
6044struct mlx5_ifc_alloc_pd_out_bits {
6045 u8 status[0x8];
6046 u8 reserved_0[0x18];
6047
6048 u8 syndrome[0x20];
6049
6050 u8 reserved_1[0x8];
6051 u8 pd[0x18];
6052
6053 u8 reserved_2[0x20];
6054};
6055
6056struct mlx5_ifc_alloc_pd_in_bits {
6057 u8 opcode[0x10];
6058 u8 reserved_0[0x10];
6059
6060 u8 reserved_1[0x10];
6061 u8 op_mod[0x10];
6062
6063 u8 reserved_2[0x40];
6064};
6065
6066struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
6067 u8 status[0x8];
6068 u8 reserved_0[0x18];
6069
6070 u8 syndrome[0x20];
6071
6072 u8 reserved_1[0x40];
6073};
6074
6075struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
6076 u8 opcode[0x10];
6077 u8 reserved_0[0x10];
6078
6079 u8 reserved_1[0x10];
6080 u8 op_mod[0x10];
6081
6082 u8 reserved_2[0x20];
6083
6084 u8 reserved_3[0x10];
6085 u8 vxlan_udp_port[0x10];
6086};
6087
6088struct mlx5_ifc_access_register_out_bits {
6089 u8 status[0x8];
6090 u8 reserved_0[0x18];
6091
6092 u8 syndrome[0x20];
6093
6094 u8 reserved_1[0x40];
6095
6096 u8 register_data[0][0x20];
6097};
6098
6099enum {
6100 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
6101 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
6102};
6103
6104struct mlx5_ifc_access_register_in_bits {
6105 u8 opcode[0x10];
6106 u8 reserved_0[0x10];
6107
6108 u8 reserved_1[0x10];
6109 u8 op_mod[0x10];
6110
6111 u8 reserved_2[0x10];
6112 u8 register_id[0x10];
6113
6114 u8 argument[0x20];
6115
6116 u8 register_data[0][0x20];
6117};
6118
6119struct mlx5_ifc_sltp_reg_bits {
6120 u8 status[0x4];
6121 u8 version[0x4];
6122 u8 local_port[0x8];
6123 u8 pnat[0x2];
6124 u8 reserved_0[0x2];
6125 u8 lane[0x4];
6126 u8 reserved_1[0x8];
6127
6128 u8 reserved_2[0x20];
6129
6130 u8 reserved_3[0x7];
6131 u8 polarity[0x1];
6132 u8 ob_tap0[0x8];
6133 u8 ob_tap1[0x8];
6134 u8 ob_tap2[0x8];
6135
6136 u8 reserved_4[0xc];
6137 u8 ob_preemp_mode[0x4];
6138 u8 ob_reg[0x8];
6139 u8 ob_bias[0x8];
6140
6141 u8 reserved_5[0x20];
6142};
6143
6144struct mlx5_ifc_slrg_reg_bits {
6145 u8 status[0x4];
6146 u8 version[0x4];
6147 u8 local_port[0x8];
6148 u8 pnat[0x2];
6149 u8 reserved_0[0x2];
6150 u8 lane[0x4];
6151 u8 reserved_1[0x8];
6152
6153 u8 time_to_link_up[0x10];
6154 u8 reserved_2[0xc];
6155 u8 grade_lane_speed[0x4];
6156
6157 u8 grade_version[0x8];
6158 u8 grade[0x18];
6159
6160 u8 reserved_3[0x4];
6161 u8 height_grade_type[0x4];
6162 u8 height_grade[0x18];
6163
6164 u8 height_dz[0x10];
6165 u8 height_dv[0x10];
6166
6167 u8 reserved_4[0x10];
6168 u8 height_sigma[0x10];
6169
6170 u8 reserved_5[0x20];
6171
6172 u8 reserved_6[0x4];
6173 u8 phase_grade_type[0x4];
6174 u8 phase_grade[0x18];
6175
6176 u8 reserved_7[0x8];
6177 u8 phase_eo_pos[0x8];
6178 u8 reserved_8[0x8];
6179 u8 phase_eo_neg[0x8];
6180
6181 u8 ffe_set_tested[0x10];
6182 u8 test_errors_per_lane[0x10];
6183};
6184
6185struct mlx5_ifc_pvlc_reg_bits {
6186 u8 reserved_0[0x8];
6187 u8 local_port[0x8];
6188 u8 reserved_1[0x10];
6189
6190 u8 reserved_2[0x1c];
6191 u8 vl_hw_cap[0x4];
6192
6193 u8 reserved_3[0x1c];
6194 u8 vl_admin[0x4];
6195
6196 u8 reserved_4[0x1c];
6197 u8 vl_operational[0x4];
6198};
6199
6200struct mlx5_ifc_pude_reg_bits {
6201 u8 swid[0x8];
6202 u8 local_port[0x8];
6203 u8 reserved_0[0x4];
6204 u8 admin_status[0x4];
6205 u8 reserved_1[0x4];
6206 u8 oper_status[0x4];
6207
6208 u8 reserved_2[0x60];
6209};
6210
6211struct mlx5_ifc_ptys_reg_bits {
6212 u8 reserved_0[0x8];
6213 u8 local_port[0x8];
6214 u8 reserved_1[0xd];
6215 u8 proto_mask[0x3];
6216
6217 u8 reserved_2[0x40];
6218
6219 u8 eth_proto_capability[0x20];
6220
6221 u8 ib_link_width_capability[0x10];
6222 u8 ib_proto_capability[0x10];
6223
6224 u8 reserved_3[0x20];
6225
6226 u8 eth_proto_admin[0x20];
6227
6228 u8 ib_link_width_admin[0x10];
6229 u8 ib_proto_admin[0x10];
6230
6231 u8 reserved_4[0x20];
6232
6233 u8 eth_proto_oper[0x20];
6234
6235 u8 ib_link_width_oper[0x10];
6236 u8 ib_proto_oper[0x10];
6237
6238 u8 reserved_5[0x20];
6239
6240 u8 eth_proto_lp_advertise[0x20];
6241
6242 u8 reserved_6[0x60];
6243};
6244
6245struct mlx5_ifc_ptas_reg_bits {
6246 u8 reserved_0[0x20];
6247
6248 u8 algorithm_options[0x10];
6249 u8 reserved_1[0x4];
6250 u8 repetitions_mode[0x4];
6251 u8 num_of_repetitions[0x8];
6252
6253 u8 grade_version[0x8];
6254 u8 height_grade_type[0x4];
6255 u8 phase_grade_type[0x4];
6256 u8 height_grade_weight[0x8];
6257 u8 phase_grade_weight[0x8];
6258
6259 u8 gisim_measure_bits[0x10];
6260 u8 adaptive_tap_measure_bits[0x10];
6261
6262 u8 ber_bath_high_error_threshold[0x10];
6263 u8 ber_bath_mid_error_threshold[0x10];
6264
6265 u8 ber_bath_low_error_threshold[0x10];
6266 u8 one_ratio_high_threshold[0x10];
6267
6268 u8 one_ratio_high_mid_threshold[0x10];
6269 u8 one_ratio_low_mid_threshold[0x10];
6270
6271 u8 one_ratio_low_threshold[0x10];
6272 u8 ndeo_error_threshold[0x10];
6273
6274 u8 mixer_offset_step_size[0x10];
6275 u8 reserved_2[0x8];
6276 u8 mix90_phase_for_voltage_bath[0x8];
6277
6278 u8 mixer_offset_start[0x10];
6279 u8 mixer_offset_end[0x10];
6280
6281 u8 reserved_3[0x15];
6282 u8 ber_test_time[0xb];
6283};
6284
6285struct mlx5_ifc_pspa_reg_bits {
6286 u8 swid[0x8];
6287 u8 local_port[0x8];
6288 u8 sub_port[0x8];
6289 u8 reserved_0[0x8];
6290
6291 u8 reserved_1[0x20];
6292};
6293
6294struct mlx5_ifc_pqdr_reg_bits {
6295 u8 reserved_0[0x8];
6296 u8 local_port[0x8];
6297 u8 reserved_1[0x5];
6298 u8 prio[0x3];
6299 u8 reserved_2[0x6];
6300 u8 mode[0x2];
6301
6302 u8 reserved_3[0x20];
6303
6304 u8 reserved_4[0x10];
6305 u8 min_threshold[0x10];
6306
6307 u8 reserved_5[0x10];
6308 u8 max_threshold[0x10];
6309
6310 u8 reserved_6[0x10];
6311 u8 mark_probability_denominator[0x10];
6312
6313 u8 reserved_7[0x60];
6314};
6315
6316struct mlx5_ifc_ppsc_reg_bits {
6317 u8 reserved_0[0x8];
6318 u8 local_port[0x8];
6319 u8 reserved_1[0x10];
6320
6321 u8 reserved_2[0x60];
6322
6323 u8 reserved_3[0x1c];
6324 u8 wrps_admin[0x4];
6325
6326 u8 reserved_4[0x1c];
6327 u8 wrps_status[0x4];
6328
6329 u8 reserved_5[0x8];
6330 u8 up_threshold[0x8];
6331 u8 reserved_6[0x8];
6332 u8 down_threshold[0x8];
6333
6334 u8 reserved_7[0x20];
6335
6336 u8 reserved_8[0x1c];
6337 u8 srps_admin[0x4];
6338
6339 u8 reserved_9[0x1c];
6340 u8 srps_status[0x4];
6341
6342 u8 reserved_10[0x40];
6343};
6344
6345struct mlx5_ifc_pplr_reg_bits {
6346 u8 reserved_0[0x8];
6347 u8 local_port[0x8];
6348 u8 reserved_1[0x10];
6349
6350 u8 reserved_2[0x8];
6351 u8 lb_cap[0x8];
6352 u8 reserved_3[0x8];
6353 u8 lb_en[0x8];
6354};
6355
6356struct mlx5_ifc_pplm_reg_bits {
6357 u8 reserved_0[0x8];
6358 u8 local_port[0x8];
6359 u8 reserved_1[0x10];
6360
6361 u8 reserved_2[0x20];
6362
6363 u8 port_profile_mode[0x8];
6364 u8 static_port_profile[0x8];
6365 u8 active_port_profile[0x8];
6366 u8 reserved_3[0x8];
6367
6368 u8 retransmission_active[0x8];
6369 u8 fec_mode_active[0x18];
6370
6371 u8 reserved_4[0x20];
6372};
6373
6374struct mlx5_ifc_ppcnt_reg_bits {
6375 u8 swid[0x8];
6376 u8 local_port[0x8];
6377 u8 pnat[0x2];
6378 u8 reserved_0[0x8];
6379 u8 grp[0x6];
6380
6381 u8 clr[0x1];
6382 u8 reserved_1[0x1c];
6383 u8 prio_tc[0x3];
6384
6385 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
6386};
6387
6388struct mlx5_ifc_ppad_reg_bits {
6389 u8 reserved_0[0x3];
6390 u8 single_mac[0x1];
6391 u8 reserved_1[0x4];
6392 u8 local_port[0x8];
6393 u8 mac_47_32[0x10];
6394
6395 u8 mac_31_0[0x20];
6396
6397 u8 reserved_2[0x40];
6398};
6399
6400struct mlx5_ifc_pmtu_reg_bits {
6401 u8 reserved_0[0x8];
6402 u8 local_port[0x8];
6403 u8 reserved_1[0x10];
6404
6405 u8 max_mtu[0x10];
6406 u8 reserved_2[0x10];
6407
6408 u8 admin_mtu[0x10];
6409 u8 reserved_3[0x10];
6410
6411 u8 oper_mtu[0x10];
6412 u8 reserved_4[0x10];
6413};
6414
6415struct mlx5_ifc_pmpr_reg_bits {
6416 u8 reserved_0[0x8];
6417 u8 module[0x8];
6418 u8 reserved_1[0x10];
6419
6420 u8 reserved_2[0x18];
6421 u8 attenuation_5g[0x8];
6422
6423 u8 reserved_3[0x18];
6424 u8 attenuation_7g[0x8];
6425
6426 u8 reserved_4[0x18];
6427 u8 attenuation_12g[0x8];
6428};
6429
6430struct mlx5_ifc_pmpe_reg_bits {
6431 u8 reserved_0[0x8];
6432 u8 module[0x8];
6433 u8 reserved_1[0xc];
6434 u8 module_status[0x4];
6435
6436 u8 reserved_2[0x60];
6437};
6438
6439struct mlx5_ifc_pmpc_reg_bits {
6440 u8 module_state_updated[32][0x8];
6441};
6442
6443struct mlx5_ifc_pmlpn_reg_bits {
6444 u8 reserved_0[0x4];
6445 u8 mlpn_status[0x4];
6446 u8 local_port[0x8];
6447 u8 reserved_1[0x10];
6448
6449 u8 e[0x1];
6450 u8 reserved_2[0x1f];
6451};
6452
6453struct mlx5_ifc_pmlp_reg_bits {
6454 u8 rxtx[0x1];
6455 u8 reserved_0[0x7];
6456 u8 local_port[0x8];
6457 u8 reserved_1[0x8];
6458 u8 width[0x8];
6459
6460 u8 lane0_module_mapping[0x20];
6461
6462 u8 lane1_module_mapping[0x20];
6463
6464 u8 lane2_module_mapping[0x20];
6465
6466 u8 lane3_module_mapping[0x20];
6467
6468 u8 reserved_2[0x160];
6469};
6470
6471struct mlx5_ifc_pmaos_reg_bits {
6472 u8 reserved_0[0x8];
6473 u8 module[0x8];
6474 u8 reserved_1[0x4];
6475 u8 admin_status[0x4];
6476 u8 reserved_2[0x4];
6477 u8 oper_status[0x4];
6478
6479 u8 ase[0x1];
6480 u8 ee[0x1];
6481 u8 reserved_3[0x1c];
6482 u8 e[0x2];
6483
6484 u8 reserved_4[0x40];
6485};
6486
6487struct mlx5_ifc_plpc_reg_bits {
6488 u8 reserved_0[0x4];
6489 u8 profile_id[0xc];
6490 u8 reserved_1[0x4];
6491 u8 proto_mask[0x4];
6492 u8 reserved_2[0x8];
6493
6494 u8 reserved_3[0x10];
6495 u8 lane_speed[0x10];
6496
6497 u8 reserved_4[0x17];
6498 u8 lpbf[0x1];
6499 u8 fec_mode_policy[0x8];
6500
6501 u8 retransmission_capability[0x8];
6502 u8 fec_mode_capability[0x18];
6503
6504 u8 retransmission_support_admin[0x8];
6505 u8 fec_mode_support_admin[0x18];
6506
6507 u8 retransmission_request_admin[0x8];
6508 u8 fec_mode_request_admin[0x18];
6509
6510 u8 reserved_5[0x80];
6511};
6512
6513struct mlx5_ifc_plib_reg_bits {
6514 u8 reserved_0[0x8];
6515 u8 local_port[0x8];
6516 u8 reserved_1[0x8];
6517 u8 ib_port[0x8];
6518
6519 u8 reserved_2[0x60];
6520};
6521
6522struct mlx5_ifc_plbf_reg_bits {
6523 u8 reserved_0[0x8];
6524 u8 local_port[0x8];
6525 u8 reserved_1[0xd];
6526 u8 lbf_mode[0x3];
6527
6528 u8 reserved_2[0x20];
6529};
6530
6531struct mlx5_ifc_pipg_reg_bits {
6532 u8 reserved_0[0x8];
6533 u8 local_port[0x8];
6534 u8 reserved_1[0x10];
6535
6536 u8 dic[0x1];
6537 u8 reserved_2[0x19];
6538 u8 ipg[0x4];
6539 u8 reserved_3[0x2];
6540};
6541
6542struct mlx5_ifc_pifr_reg_bits {
6543 u8 reserved_0[0x8];
6544 u8 local_port[0x8];
6545 u8 reserved_1[0x10];
6546
6547 u8 reserved_2[0xe0];
6548
6549 u8 port_filter[8][0x20];
6550
6551 u8 port_filter_update_en[8][0x20];
6552};
6553
6554struct mlx5_ifc_pfcc_reg_bits {
6555 u8 reserved_0[0x8];
6556 u8 local_port[0x8];
6557 u8 reserved_1[0x10];
6558
6559 u8 ppan[0x4];
6560 u8 reserved_2[0x4];
6561 u8 prio_mask_tx[0x8];
6562 u8 reserved_3[0x8];
6563 u8 prio_mask_rx[0x8];
6564
6565 u8 pptx[0x1];
6566 u8 aptx[0x1];
6567 u8 reserved_4[0x6];
6568 u8 pfctx[0x8];
6569 u8 reserved_5[0x10];
6570
6571 u8 pprx[0x1];
6572 u8 aprx[0x1];
6573 u8 reserved_6[0x6];
6574 u8 pfcrx[0x8];
6575 u8 reserved_7[0x10];
6576
6577 u8 reserved_8[0x80];
6578};
6579
6580struct mlx5_ifc_pelc_reg_bits {
6581 u8 op[0x4];
6582 u8 reserved_0[0x4];
6583 u8 local_port[0x8];
6584 u8 reserved_1[0x10];
6585
6586 u8 op_admin[0x8];
6587 u8 op_capability[0x8];
6588 u8 op_request[0x8];
6589 u8 op_active[0x8];
6590
6591 u8 admin[0x40];
6592
6593 u8 capability[0x40];
6594
6595 u8 request[0x40];
6596
6597 u8 active[0x40];
6598
6599 u8 reserved_2[0x80];
6600};
6601
6602struct mlx5_ifc_peir_reg_bits {
6603 u8 reserved_0[0x8];
6604 u8 local_port[0x8];
6605 u8 reserved_1[0x10];
6606
6607 u8 reserved_2[0xc];
6608 u8 error_count[0x4];
6609 u8 reserved_3[0x10];
6610
6611 u8 reserved_4[0xc];
6612 u8 lane[0x4];
6613 u8 reserved_5[0x8];
6614 u8 error_type[0x8];
6615};
6616
6617struct mlx5_ifc_pcap_reg_bits {
6618 u8 reserved_0[0x8];
6619 u8 local_port[0x8];
6620 u8 reserved_1[0x10];
6621
6622 u8 port_capability_mask[4][0x20];
6623};
6624
6625struct mlx5_ifc_paos_reg_bits {
6626 u8 swid[0x8];
6627 u8 local_port[0x8];
6628 u8 reserved_0[0x4];
6629 u8 admin_status[0x4];
6630 u8 reserved_1[0x4];
6631 u8 oper_status[0x4];
6632
6633 u8 ase[0x1];
6634 u8 ee[0x1];
6635 u8 reserved_2[0x1c];
6636 u8 e[0x2];
6637
6638 u8 reserved_3[0x40];
6639};
6640
6641struct mlx5_ifc_pamp_reg_bits {
6642 u8 reserved_0[0x8];
6643 u8 opamp_group[0x8];
6644 u8 reserved_1[0xc];
6645 u8 opamp_group_type[0x4];
6646
6647 u8 start_index[0x10];
6648 u8 reserved_2[0x4];
6649 u8 num_of_indices[0xc];
6650
6651 u8 index_data[18][0x10];
6652};
6653
6654struct mlx5_ifc_lane_2_module_mapping_bits {
6655 u8 reserved_0[0x6];
6656 u8 rx_lane[0x2];
6657 u8 reserved_1[0x6];
6658 u8 tx_lane[0x2];
6659 u8 reserved_2[0x8];
6660 u8 module[0x8];
6661};
6662
6663struct mlx5_ifc_bufferx_reg_bits {
6664 u8 reserved_0[0x6];
6665 u8 lossy[0x1];
6666 u8 epsb[0x1];
6667 u8 reserved_1[0xc];
6668 u8 size[0xc];
6669
6670 u8 xoff_threshold[0x10];
6671 u8 xon_threshold[0x10];
6672};
6673
6674struct mlx5_ifc_set_node_in_bits {
6675 u8 node_description[64][0x8];
6676};
6677
6678struct mlx5_ifc_register_power_settings_bits {
6679 u8 reserved_0[0x18];
6680 u8 power_settings_level[0x8];
6681
6682 u8 reserved_1[0x60];
6683};
6684
6685struct mlx5_ifc_register_host_endianness_bits {
6686 u8 he[0x1];
6687 u8 reserved_0[0x1f];
6688
6689 u8 reserved_1[0x60];
6690};
6691
6692struct mlx5_ifc_umr_pointer_desc_argument_bits {
6693 u8 reserved_0[0x20];
6694
6695 u8 mkey[0x20];
6696
6697 u8 addressh_63_32[0x20];
6698
6699 u8 addressl_31_0[0x20];
6700};
6701
6702struct mlx5_ifc_ud_adrs_vector_bits {
6703 u8 dc_key[0x40];
6704
6705 u8 ext[0x1];
6706 u8 reserved_0[0x7];
6707 u8 destination_qp_dct[0x18];
6708
6709 u8 static_rate[0x4];
6710 u8 sl_eth_prio[0x4];
6711 u8 fl[0x1];
6712 u8 mlid[0x7];
6713 u8 rlid_udp_sport[0x10];
6714
6715 u8 reserved_1[0x20];
6716
6717 u8 rmac_47_16[0x20];
6718
6719 u8 rmac_15_0[0x10];
6720 u8 tclass[0x8];
6721 u8 hop_limit[0x8];
6722
6723 u8 reserved_2[0x1];
6724 u8 grh[0x1];
6725 u8 reserved_3[0x2];
6726 u8 src_addr_index[0x8];
6727 u8 flow_label[0x14];
6728
6729 u8 rgid_rip[16][0x8];
6730};
6731
6732struct mlx5_ifc_pages_req_event_bits {
6733 u8 reserved_0[0x10];
6734 u8 function_id[0x10];
6735
6736 u8 num_pages[0x20];
6737
6738 u8 reserved_1[0xa0];
6739};
6740
6741struct mlx5_ifc_eqe_bits {
6742 u8 reserved_0[0x8];
6743 u8 event_type[0x8];
6744 u8 reserved_1[0x8];
6745 u8 event_sub_type[0x8];
6746
6747 u8 reserved_2[0xe0];
6748
6749 union mlx5_ifc_event_auto_bits event_data;
6750
6751 u8 reserved_3[0x10];
6752 u8 signature[0x8];
6753 u8 reserved_4[0x7];
6754 u8 owner[0x1];
6755};
6756
6757enum {
6758 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
6759};
6760
6761struct mlx5_ifc_cmd_queue_entry_bits {
6762 u8 type[0x8];
6763 u8 reserved_0[0x18];
6764
6765 u8 input_length[0x20];
6766
6767 u8 input_mailbox_pointer_63_32[0x20];
6768
6769 u8 input_mailbox_pointer_31_9[0x17];
6770 u8 reserved_1[0x9];
6771
6772 u8 command_input_inline_data[16][0x8];
6773
6774 u8 command_output_inline_data[16][0x8];
6775
6776 u8 output_mailbox_pointer_63_32[0x20];
6777
6778 u8 output_mailbox_pointer_31_9[0x17];
6779 u8 reserved_2[0x9];
6780
6781 u8 output_length[0x20];
6782
6783 u8 token[0x8];
6784 u8 signature[0x8];
6785 u8 reserved_3[0x8];
6786 u8 status[0x7];
6787 u8 ownership[0x1];
6788};
6789
6790struct mlx5_ifc_cmd_out_bits {
6791 u8 status[0x8];
6792 u8 reserved_0[0x18];
6793
6794 u8 syndrome[0x20];
6795
6796 u8 command_output[0x20];
6797};
6798
6799struct mlx5_ifc_cmd_in_bits {
6800 u8 opcode[0x10];
6801 u8 reserved_0[0x10];
6802
6803 u8 reserved_1[0x10];
6804 u8 op_mod[0x10];
6805
6806 u8 command[0][0x20];
6807};
6808
6809struct mlx5_ifc_cmd_if_box_bits {
6810 u8 mailbox_data[512][0x8];
6811
6812 u8 reserved_0[0x180];
6813
6814 u8 next_pointer_63_32[0x20];
6815
6816 u8 next_pointer_31_10[0x16];
6817 u8 reserved_1[0xa];
6818
6819 u8 block_number[0x20];
6820
6821 u8 reserved_2[0x8];
6822 u8 token[0x8];
6823 u8 ctrl_signature[0x8];
6824 u8 signature[0x8];
6825};
6826
6827struct mlx5_ifc_mtt_bits {
6828 u8 ptag_63_32[0x20];
6829
6830 u8 ptag_31_8[0x18];
6831 u8 reserved_0[0x6];
6832 u8 wr_en[0x1];
6833 u8 rd_en[0x1];
6834};
6835
6836enum {
6837 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
6838 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
6839 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
6840};
6841
6842enum {
6843 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
6844 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
6845 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
6846};
6847
6848enum {
6849 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
6850 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
6851 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
6852 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
6853 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
6854 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
6855 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
6856 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
6857 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
6858 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
6859 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
6860};
6861
6862struct mlx5_ifc_initial_seg_bits {
6863 u8 fw_rev_minor[0x10];
6864 u8 fw_rev_major[0x10];
6865
6866 u8 cmd_interface_rev[0x10];
6867 u8 fw_rev_subminor[0x10];
6868
6869 u8 reserved_0[0x40];
6870
6871 u8 cmdq_phy_addr_63_32[0x20];
6872
6873 u8 cmdq_phy_addr_31_12[0x14];
6874 u8 reserved_1[0x2];
6875 u8 nic_interface[0x2];
6876 u8 log_cmdq_size[0x4];
6877 u8 log_cmdq_stride[0x4];
6878
6879 u8 command_doorbell_vector[0x20];
6880
6881 u8 reserved_2[0xf00];
6882
6883 u8 initializing[0x1];
6884 u8 reserved_3[0x4];
6885 u8 nic_interface_supported[0x3];
6886 u8 reserved_4[0x18];
6887
6888 struct mlx5_ifc_health_buffer_bits health_buffer;
6889
6890 u8 no_dram_nic_offset[0x20];
6891
6892 u8 reserved_5[0x6e40];
6893
6894 u8 reserved_6[0x1f];
6895 u8 clear_int[0x1];
6896
6897 u8 health_syndrome[0x8];
6898 u8 health_counter[0x18];
6899
6900 u8 reserved_7[0x17fc0];
6901};
6902
6903union mlx5_ifc_ports_control_registers_document_bits {
6904 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
6905 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
6906 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
6907 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
6908 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
6909 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
6910 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
6911 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
6912 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
6913 struct mlx5_ifc_pamp_reg_bits pamp_reg;
6914 struct mlx5_ifc_paos_reg_bits paos_reg;
6915 struct mlx5_ifc_pcap_reg_bits pcap_reg;
6916 struct mlx5_ifc_peir_reg_bits peir_reg;
6917 struct mlx5_ifc_pelc_reg_bits pelc_reg;
6918 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
6919 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
6920 struct mlx5_ifc_pifr_reg_bits pifr_reg;
6921 struct mlx5_ifc_pipg_reg_bits pipg_reg;
6922 struct mlx5_ifc_plbf_reg_bits plbf_reg;
6923 struct mlx5_ifc_plib_reg_bits plib_reg;
6924 struct mlx5_ifc_plpc_reg_bits plpc_reg;
6925 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
6926 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
6927 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
6928 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
6929 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
6930 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
6931 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
6932 struct mlx5_ifc_ppad_reg_bits ppad_reg;
6933 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
6934 struct mlx5_ifc_pplm_reg_bits pplm_reg;
6935 struct mlx5_ifc_pplr_reg_bits pplr_reg;
6936 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
6937 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
6938 struct mlx5_ifc_pspa_reg_bits pspa_reg;
6939 struct mlx5_ifc_ptas_reg_bits ptas_reg;
6940 struct mlx5_ifc_ptys_reg_bits ptys_reg;
6941 struct mlx5_ifc_pude_reg_bits pude_reg;
6942 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
6943 struct mlx5_ifc_slrg_reg_bits slrg_reg;
6944 struct mlx5_ifc_sltp_reg_bits sltp_reg;
6945 u8 reserved_0[0x60e0];
6946};
6947
6948union mlx5_ifc_debug_enhancements_document_bits {
6949 struct mlx5_ifc_health_buffer_bits health_buffer;
6950 u8 reserved_0[0x200];
6951};
6952
6953union mlx5_ifc_uplink_pci_interface_document_bits {
6954 struct mlx5_ifc_initial_seg_bits initial_seg;
6955 u8 reserved_0[0x20060];
b775516b
EC		 6956};
6957
2cc43b49
MG		 6958struct mlx5_ifc_set_flow_table_root_out_bits {
6959 u8 status[0x8];
6960 u8 reserved_0[0x18];
6961
6962 u8 syndrome[0x20];
6963
6964 u8 reserved_1[0x40];
6965};
6966
6967struct mlx5_ifc_set_flow_table_root_in_bits {
6968 u8 opcode[0x10];
6969 u8 reserved_0[0x10];
6970
6971 u8 reserved_1[0x10];
6972 u8 op_mod[0x10];
6973
6974 u8 reserved_2[0x40];
6975
6976 u8 table_type[0x8];
6977 u8 reserved_3[0x18];
6978
6979 u8 reserved_4[0x8];
6980 u8 table_id[0x18];
6981
6982 u8 reserved_5[0x140];
6983};
6984
34a40e68
MG		 6985enum {
6986 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = 0x1,
6987};
6988
6989struct mlx5_ifc_modify_flow_table_out_bits {
6990 u8 status[0x8];
6991 u8 reserved_0[0x18];
6992
6993 u8 syndrome[0x20];
6994
6995 u8 reserved_1[0x40];
6996};
6997
6998struct mlx5_ifc_modify_flow_table_in_bits {
6999 u8 opcode[0x10];
7000 u8 reserved_0[0x10];
7001
7002 u8 reserved_1[0x10];
7003 u8 op_mod[0x10];
7004
7005 u8 reserved_2[0x20];
7006
7007 u8 reserved_3[0x10];
7008 u8 modify_field_select[0x10];
7009
7010 u8 table_type[0x8];
7011 u8 reserved_4[0x18];
7012
7013 u8 reserved_5[0x8];
7014 u8 table_id[0x18];
7015
7016 u8 reserved_6[0x4];
7017 u8 table_miss_mode[0x4];
7018 u8 reserved_7[0x18];
7019
7020 u8 reserved_8[0x8];
7021 u8 table_miss_id[0x18];
7022
7023 u8 reserved_9[0x100];
7024};
7025
d29b796a 7026#endif /* MLX5_IFC_H */
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