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net/mlx5e: Expose physical layer statistical counters to ethtool
[mirror_ubuntu-bionic-kernel.git] / include / linux / mlx5 / mlx5_ifc.h
CommitLineData
d29b796a 1/*
e281682b 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
d29b796a
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
e281682b 31*/
d29b796a
EC		 32#ifndef MLX5_IFC_H
33#define MLX5_IFC_H
34
e281682b
SM		 35enum {
36 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
37 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
38 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
39 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
40 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
41 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
42 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
43 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
44 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
45 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
46 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
47 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
48 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
49 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
50 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
51 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
52 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
53 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
54 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
55 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
56 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
57 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
58 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
59 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb
60};
61
62enum {
63 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
64 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
65 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
66 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
67};
68
f91e6d89
EBE		 69enum {
70 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
71 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
72};
73
d29b796a
EC		 74enum {
75 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
76 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
77 MLX5_CMD_OP_INIT_HCA = 0x102,
78 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
79 MLX5_CMD_OP_ENABLE_HCA = 0x104,
80 MLX5_CMD_OP_DISABLE_HCA = 0x105,
81 MLX5_CMD_OP_QUERY_PAGES = 0x107,
82 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
83 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
e281682b
SM		 84 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
85 MLX5_CMD_OP_SET_ISSI = 0x10b,
0dbc6fe0 86 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
d29b796a
EC		 87 MLX5_CMD_OP_CREATE_MKEY = 0x200,
88 MLX5_CMD_OP_QUERY_MKEY = 0x201,
89 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
90 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
91 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
92 MLX5_CMD_OP_CREATE_EQ = 0x301,
93 MLX5_CMD_OP_DESTROY_EQ = 0x302,
94 MLX5_CMD_OP_QUERY_EQ = 0x303,
95 MLX5_CMD_OP_GEN_EQE = 0x304,
96 MLX5_CMD_OP_CREATE_CQ = 0x400,
97 MLX5_CMD_OP_DESTROY_CQ = 0x401,
98 MLX5_CMD_OP_QUERY_CQ = 0x402,
99 MLX5_CMD_OP_MODIFY_CQ = 0x403,
100 MLX5_CMD_OP_CREATE_QP = 0x500,
101 MLX5_CMD_OP_DESTROY_QP = 0x501,
102 MLX5_CMD_OP_RST2INIT_QP = 0x502,
103 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
104 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
105 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
106 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
107 MLX5_CMD_OP_2ERR_QP = 0x507,
108 MLX5_CMD_OP_2RST_QP = 0x50a,
109 MLX5_CMD_OP_QUERY_QP = 0x50b,
e281682b 110 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
d29b796a
EC		 111 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
112 MLX5_CMD_OP_CREATE_PSV = 0x600,
113 MLX5_CMD_OP_DESTROY_PSV = 0x601,
114 MLX5_CMD_OP_CREATE_SRQ = 0x700,
115 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
116 MLX5_CMD_OP_QUERY_SRQ = 0x702,
117 MLX5_CMD_OP_ARM_RQ = 0x703,
e281682b
SM		 118 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
119 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
120 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
121 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
d29b796a
EC		 122 MLX5_CMD_OP_CREATE_DCT = 0x710,
123 MLX5_CMD_OP_DESTROY_DCT = 0x711,
124 MLX5_CMD_OP_DRAIN_DCT = 0x712,
125 MLX5_CMD_OP_QUERY_DCT = 0x713,
126 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
7486216b
SM		 127 MLX5_CMD_OP_CREATE_XRQ = 0x717,
128 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
129 MLX5_CMD_OP_QUERY_XRQ = 0x719,
130 MLX5_CMD_OP_ARM_XRQ = 0x71a,
d29b796a
EC		 131 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
132 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
133 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
134 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
135 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
136 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
e281682b 137 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
d29b796a 138 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
e281682b
SM		 139 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
140 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
141 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
142 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
d29b796a
EC		 143 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
144 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
145 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
146 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
7486216b
SM		 147 MLX5_CMD_OP_SET_RATE_LIMIT = 0x780,
148 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
813f8540
MHY		 149 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
150 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
151 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
152 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
153 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
154 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
d29b796a
EC		 155 MLX5_CMD_OP_ALLOC_PD = 0x800,
156 MLX5_CMD_OP_DEALLOC_PD = 0x801,
157 MLX5_CMD_OP_ALLOC_UAR = 0x802,
158 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
159 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
160 MLX5_CMD_OP_ACCESS_REG = 0x805,
161 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
20bb566b 162 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
d29b796a
EC		 163 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
164 MLX5_CMD_OP_MAD_IFC = 0x50d,
165 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
166 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
167 MLX5_CMD_OP_NOP = 0x80d,
168 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
169 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
e281682b
SM		 170 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
171 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
172 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
173 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
174 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
175 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
176 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
177 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
178 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
179 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
180 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
181 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
928cfe87
TT		 182 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
183 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
84df61eb
AH		 184 MLX5_CMD_OP_CREATE_LAG = 0x840,
185 MLX5_CMD_OP_MODIFY_LAG = 0x841,
186 MLX5_CMD_OP_QUERY_LAG = 0x842,
187 MLX5_CMD_OP_DESTROY_LAG = 0x843,
188 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
189 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
d29b796a
EC		 190 MLX5_CMD_OP_CREATE_TIR = 0x900,
191 MLX5_CMD_OP_MODIFY_TIR = 0x901,
192 MLX5_CMD_OP_DESTROY_TIR = 0x902,
193 MLX5_CMD_OP_QUERY_TIR = 0x903,
d29b796a
EC		 194 MLX5_CMD_OP_CREATE_SQ = 0x904,
195 MLX5_CMD_OP_MODIFY_SQ = 0x905,
196 MLX5_CMD_OP_DESTROY_SQ = 0x906,
197 MLX5_CMD_OP_QUERY_SQ = 0x907,
198 MLX5_CMD_OP_CREATE_RQ = 0x908,
199 MLX5_CMD_OP_MODIFY_RQ = 0x909,
200 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
201 MLX5_CMD_OP_QUERY_RQ = 0x90b,
202 MLX5_CMD_OP_CREATE_RMP = 0x90c,
203 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
204 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
205 MLX5_CMD_OP_QUERY_RMP = 0x90f,
e281682b
SM		 206 MLX5_CMD_OP_CREATE_TIS = 0x912,
207 MLX5_CMD_OP_MODIFY_TIS = 0x913,
208 MLX5_CMD_OP_DESTROY_TIS = 0x914,
209 MLX5_CMD_OP_QUERY_TIS = 0x915,
210 MLX5_CMD_OP_CREATE_RQT = 0x916,
211 MLX5_CMD_OP_MODIFY_RQT = 0x917,
212 MLX5_CMD_OP_DESTROY_RQT = 0x918,
213 MLX5_CMD_OP_QUERY_RQT = 0x919,
2cc43b49 214 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
e281682b
SM		 215 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
216 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
217 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
218 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
219 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
220 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
221 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
222 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
34a40e68 223 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
9dc0b289
AV		 224 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
225 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
226 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
86d56a1a 227 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
7adbde20
HHZ		 228 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d,
229 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e,
86d56a1a 230 MLX5_CMD_OP_MAX
e281682b
SM		 231};
232
233struct mlx5_ifc_flow_table_fields_supported_bits {
234 u8 outer_dmac[0x1];
235 u8 outer_smac[0x1];
236 u8 outer_ether_type[0x1];
b4ff3a36 237 u8 reserved_at_3[0x1];
e281682b
SM		 238 u8 outer_first_prio[0x1];
239 u8 outer_first_cfi[0x1];
240 u8 outer_first_vid[0x1];
b4ff3a36 241 u8 reserved_at_7[0x1];
e281682b
SM		 242 u8 outer_second_prio[0x1];
243 u8 outer_second_cfi[0x1];
244 u8 outer_second_vid[0x1];
b4ff3a36 245 u8 reserved_at_b[0x1];
e281682b
SM		 246 u8 outer_sip[0x1];
247 u8 outer_dip[0x1];
248 u8 outer_frag[0x1];
249 u8 outer_ip_protocol[0x1];
250 u8 outer_ip_ecn[0x1];
251 u8 outer_ip_dscp[0x1];
252 u8 outer_udp_sport[0x1];
253 u8 outer_udp_dport[0x1];
254 u8 outer_tcp_sport[0x1];
255 u8 outer_tcp_dport[0x1];
256 u8 outer_tcp_flags[0x1];
257 u8 outer_gre_protocol[0x1];
258 u8 outer_gre_key[0x1];
259 u8 outer_vxlan_vni[0x1];
b4ff3a36 260 u8 reserved_at_1a[0x5];
e281682b
SM		 261 u8 source_eswitch_port[0x1];
262
263 u8 inner_dmac[0x1];
264 u8 inner_smac[0x1];
265 u8 inner_ether_type[0x1];
b4ff3a36 266 u8 reserved_at_23[0x1];
e281682b
SM		 267 u8 inner_first_prio[0x1];
268 u8 inner_first_cfi[0x1];
269 u8 inner_first_vid[0x1];
b4ff3a36 270 u8 reserved_at_27[0x1];
e281682b
SM		 271 u8 inner_second_prio[0x1];
272 u8 inner_second_cfi[0x1];
273 u8 inner_second_vid[0x1];
b4ff3a36 274 u8 reserved_at_2b[0x1];
e281682b
SM		 275 u8 inner_sip[0x1];
276 u8 inner_dip[0x1];
277 u8 inner_frag[0x1];
278 u8 inner_ip_protocol[0x1];
279 u8 inner_ip_ecn[0x1];
280 u8 inner_ip_dscp[0x1];
281 u8 inner_udp_sport[0x1];
282 u8 inner_udp_dport[0x1];
283 u8 inner_tcp_sport[0x1];
284 u8 inner_tcp_dport[0x1];
285 u8 inner_tcp_flags[0x1];
b4ff3a36 286 u8 reserved_at_37[0x9];
e281682b 287
b4ff3a36 288 u8 reserved_at_40[0x40];
e281682b
SM		 289};
290
291struct mlx5_ifc_flow_table_prop_layout_bits {
292 u8 ft_support[0x1];
9dc0b289
AV		 293 u8 reserved_at_1[0x1];
294 u8 flow_counter[0x1];
26a81453 295 u8 flow_modify_en[0x1];
2cc43b49 296 u8 modify_root[0x1];
34a40e68
MG		 297 u8 identified_miss_table_mode[0x1];
298 u8 flow_table_modify[0x1];
7adbde20
HHZ		 299 u8 encap[0x1];
300 u8 decap[0x1];
301 u8 reserved_at_9[0x17];
e281682b 302
b4ff3a36 303 u8 reserved_at_20[0x2];
e281682b 304 u8 log_max_ft_size[0x6];
b4ff3a36 305 u8 reserved_at_28[0x10];
e281682b
SM		 306 u8 max_ft_level[0x8];
307
b4ff3a36 308 u8 reserved_at_40[0x20];
e281682b 309
b4ff3a36 310 u8 reserved_at_60[0x18];
e281682b
SM		 311 u8 log_max_ft_num[0x8];
312
b4ff3a36 313 u8 reserved_at_80[0x18];
e281682b
SM		 314 u8 log_max_destination[0x8];
315
b4ff3a36 316 u8 reserved_at_a0[0x18];
e281682b
SM		 317 u8 log_max_flow[0x8];
318
b4ff3a36 319 u8 reserved_at_c0[0x40];
e281682b
SM		 320
321 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
322
323 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
324};
325
326struct mlx5_ifc_odp_per_transport_service_cap_bits {
327 u8 send[0x1];
328 u8 receive[0x1];
329 u8 write[0x1];
330 u8 read[0x1];
17d2f88f 331 u8 atomic[0x1];
e281682b 332 u8 srq_receive[0x1];
b4ff3a36 333 u8 reserved_at_6[0x1a];
e281682b
SM		 334};
335
b4d1f032 336struct mlx5_ifc_ipv4_layout_bits {
b4ff3a36 337 u8 reserved_at_0[0x60];
b4d1f032
MG		 338
339 u8 ipv4[0x20];
340};
341
342struct mlx5_ifc_ipv6_layout_bits {
343 u8 ipv6[16][0x8];
344};
345
346union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
347 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
348 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
b4ff3a36 349 u8 reserved_at_0[0x80];
b4d1f032
MG		 350};
351
e281682b
SM		 352struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
353 u8 smac_47_16[0x20];
354
355 u8 smac_15_0[0x10];
356 u8 ethertype[0x10];
357
358 u8 dmac_47_16[0x20];
359
360 u8 dmac_15_0[0x10];
361 u8 first_prio[0x3];
362 u8 first_cfi[0x1];
363 u8 first_vid[0xc];
364
365 u8 ip_protocol[0x8];
366 u8 ip_dscp[0x6];
367 u8 ip_ecn[0x2];
10543365
MHY		 368 u8 cvlan_tag[0x1];
369 u8 svlan_tag[0x1];
e281682b 370 u8 frag[0x1];
b4ff3a36 371 u8 reserved_at_93[0x4];
e281682b
SM		 372 u8 tcp_flags[0x9];
373
374 u8 tcp_sport[0x10];
375 u8 tcp_dport[0x10];
376
b4ff3a36 377 u8 reserved_at_c0[0x20];
e281682b
SM		 378
379 u8 udp_sport[0x10];
380 u8 udp_dport[0x10];
381
b4d1f032 382 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
e281682b 383
b4d1f032 384 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
e281682b
SM		 385};
386
387struct mlx5_ifc_fte_match_set_misc_bits {
7486216b
SM		 388 u8 reserved_at_0[0x8];
389 u8 source_sqn[0x18];
e281682b 390
b4ff3a36 391 u8 reserved_at_20[0x10];
e281682b
SM		 392 u8 source_port[0x10];
393
394 u8 outer_second_prio[0x3];
395 u8 outer_second_cfi[0x1];
396 u8 outer_second_vid[0xc];
397 u8 inner_second_prio[0x3];
398 u8 inner_second_cfi[0x1];
399 u8 inner_second_vid[0xc];
400
10543365
MHY		 401 u8 outer_second_cvlan_tag[0x1];
402 u8 inner_second_cvlan_tag[0x1];
403 u8 outer_second_svlan_tag[0x1];
404 u8 inner_second_svlan_tag[0x1];
405 u8 reserved_at_64[0xc];
e281682b
SM		 406 u8 gre_protocol[0x10];
407
408 u8 gre_key_h[0x18];
409 u8 gre_key_l[0x8];
410
411 u8 vxlan_vni[0x18];
b4ff3a36 412 u8 reserved_at_b8[0x8];
e281682b 413
b4ff3a36 414 u8 reserved_at_c0[0x20];
e281682b 415
b4ff3a36 416 u8 reserved_at_e0[0xc];
e281682b
SM		 417 u8 outer_ipv6_flow_label[0x14];
418
b4ff3a36 419 u8 reserved_at_100[0xc];
e281682b
SM		 420 u8 inner_ipv6_flow_label[0x14];
421
b4ff3a36 422 u8 reserved_at_120[0xe0];
e281682b
SM		 423};
424
425struct mlx5_ifc_cmd_pas_bits {
426 u8 pa_h[0x20];
427
428 u8 pa_l[0x14];
b4ff3a36 429 u8 reserved_at_34[0xc];
e281682b
SM		 430};
431
432struct mlx5_ifc_uint64_bits {
433 u8 hi[0x20];
434
435 u8 lo[0x20];
436};
437
438enum {
439 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
440 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
441 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
442 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
443 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
444 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
445 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
446 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
447 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
448 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
449};
450
451struct mlx5_ifc_ads_bits {
452 u8 fl[0x1];
453 u8 free_ar[0x1];
b4ff3a36 454 u8 reserved_at_2[0xe];
e281682b
SM		 455 u8 pkey_index[0x10];
456
b4ff3a36 457 u8 reserved_at_20[0x8];
e281682b
SM		 458 u8 grh[0x1];
459 u8 mlid[0x7];
460 u8 rlid[0x10];
461
462 u8 ack_timeout[0x5];
b4ff3a36 463 u8 reserved_at_45[0x3];
e281682b 464 u8 src_addr_index[0x8];
b4ff3a36 465 u8 reserved_at_50[0x4];
e281682b
SM		 466 u8 stat_rate[0x4];
467 u8 hop_limit[0x8];
468
b4ff3a36 469 u8 reserved_at_60[0x4];
e281682b
SM		 470 u8 tclass[0x8];
471 u8 flow_label[0x14];
472
473 u8 rgid_rip[16][0x8];
474
b4ff3a36 475 u8 reserved_at_100[0x4];
e281682b
SM		 476 u8 f_dscp[0x1];
477 u8 f_ecn[0x1];
b4ff3a36 478 u8 reserved_at_106[0x1];
e281682b
SM		 479 u8 f_eth_prio[0x1];
480 u8 ecn[0x2];
481 u8 dscp[0x6];
482 u8 udp_sport[0x10];
483
484 u8 dei_cfi[0x1];
485 u8 eth_prio[0x3];
486 u8 sl[0x4];
487 u8 port[0x8];
488 u8 rmac_47_32[0x10];
489
490 u8 rmac_31_0[0x20];
491};
492
493struct mlx5_ifc_flow_table_nic_cap_bits {
b3638e1a 494 u8 nic_rx_multi_path_tirs[0x1];
cea824d4
MG		 495 u8 nic_rx_multi_path_tirs_fts[0x1];
496 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
497 u8 reserved_at_3[0x1fd];
e281682b
SM		 498
499 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
500
b4ff3a36 501 u8 reserved_at_400[0x200];
e281682b
SM		 502
503 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
504
505 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
506
b4ff3a36 507 u8 reserved_at_a00[0x200];
e281682b
SM		 508
509 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
510
b4ff3a36 511 u8 reserved_at_e00[0x7200];
e281682b
SM		 512};
513
495716b1 514struct mlx5_ifc_flow_table_eswitch_cap_bits {
b4ff3a36 515 u8 reserved_at_0[0x200];
495716b1
SM		 516
517 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
518
519 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
520
521 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
522
b4ff3a36 523 u8 reserved_at_800[0x7800];
495716b1
SM		 524};
525
d6666753
SM		 526struct mlx5_ifc_e_switch_cap_bits {
527 u8 vport_svlan_strip[0x1];
528 u8 vport_cvlan_strip[0x1];
529 u8 vport_svlan_insert[0x1];
530 u8 vport_cvlan_insert_if_not_exist[0x1];
531 u8 vport_cvlan_insert_overwrite[0x1];
23898c76
NO		 532 u8 reserved_at_5[0x19];
533 u8 nic_vport_node_guid_modify[0x1];
534 u8 nic_vport_port_guid_modify[0x1];
d6666753 535
7adbde20
HHZ		 536 u8 vxlan_encap_decap[0x1];
537 u8 nvgre_encap_decap[0x1];
538 u8 reserved_at_22[0x9];
539 u8 log_max_encap_headers[0x5];
540 u8 reserved_2b[0x6];
541 u8 max_encap_header_size[0xa];
542
543 u8 reserved_40[0x7c0];
544
d6666753
SM		 545};
546
7486216b
SM		 547struct mlx5_ifc_qos_cap_bits {
548 u8 packet_pacing[0x1];
813f8540
MHY		 549 u8 esw_scheduling[0x1];
550 u8 reserved_at_2[0x1e];
551
552 u8 reserved_at_20[0x20];
553
7486216b 554 u8 packet_pacing_max_rate[0x20];
813f8540 555
7486216b 556 u8 packet_pacing_min_rate[0x20];
813f8540
MHY		 557
558 u8 reserved_at_80[0x10];
7486216b 559 u8 packet_pacing_rate_table_size[0x10];
813f8540
MHY		 560
561 u8 esw_element_type[0x10];
562 u8 esw_tsar_type[0x10];
563
564 u8 reserved_at_c0[0x10];
565 u8 max_qos_para_vport[0x10];
566
567 u8 max_tsar_bw_share[0x20];
568
569 u8 reserved_at_100[0x700];
7486216b
SM		 570};
571
e281682b
SM		 572struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
573 u8 csum_cap[0x1];
574 u8 vlan_cap[0x1];
575 u8 lro_cap[0x1];
576 u8 lro_psh_flag[0x1];
577 u8 lro_time_stamp[0x1];
b4ff3a36 578 u8 reserved_at_5[0x3];
66189961 579 u8 self_lb_en_modifiable[0x1];
b4ff3a36 580 u8 reserved_at_9[0x2];
e281682b 581 u8 max_lso_cap[0x5];
c226dc22 582 u8 multi_pkt_send_wqe[0x2];
cff92d7c 583 u8 wqe_inline_mode[0x2];
e281682b 584 u8 rss_ind_tbl_cap[0x4];
7d5e1423
SM		 585 u8 reg_umr_sq[0x1];
586 u8 scatter_fcs[0x1];
587 u8 reserved_at_1a[0x1];
e281682b 588 u8 tunnel_lso_const_out_ip_id[0x1];
b4ff3a36 589 u8 reserved_at_1c[0x2];
e281682b
SM		 590 u8 tunnel_statless_gre[0x1];
591 u8 tunnel_stateless_vxlan[0x1];
592
b4ff3a36 593 u8 reserved_at_20[0x20];
e281682b 594
b4ff3a36 595 u8 reserved_at_40[0x10];
e281682b
SM		 596 u8 lro_min_mss_size[0x10];
597
b4ff3a36 598 u8 reserved_at_60[0x120];
e281682b
SM		 599
600 u8 lro_timer_supported_periods[4][0x20];
601
b4ff3a36 602 u8 reserved_at_200[0x600];
e281682b
SM		 603};
604
605struct mlx5_ifc_roce_cap_bits {
606 u8 roce_apm[0x1];
b4ff3a36 607 u8 reserved_at_1[0x1f];
e281682b 608
b4ff3a36 609 u8 reserved_at_20[0x60];
e281682b 610
b4ff3a36 611 u8 reserved_at_80[0xc];
e281682b 612 u8 l3_type[0x4];
b4ff3a36 613 u8 reserved_at_90[0x8];
e281682b
SM		 614 u8 roce_version[0x8];
615
b4ff3a36 616 u8 reserved_at_a0[0x10];
e281682b
SM		 617 u8 r_roce_dest_udp_port[0x10];
618
619 u8 r_roce_max_src_udp_port[0x10];
620 u8 r_roce_min_src_udp_port[0x10];
621
b4ff3a36 622 u8 reserved_at_e0[0x10];
e281682b
SM		 623 u8 roce_address_table_size[0x10];
624
b4ff3a36 625 u8 reserved_at_100[0x700];
e281682b
SM		 626};
627
628enum {
629 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
630 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
631 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
632 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
633 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
634 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
635 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
636 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
637 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
638};
639
640enum {
641 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
642 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
643 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
644 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
645 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
646 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
647 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
648 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
649 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
650};
651
652struct mlx5_ifc_atomic_caps_bits {
b4ff3a36 653 u8 reserved_at_0[0x40];
e281682b 654
f91e6d89 655 u8 atomic_req_8B_endianess_mode[0x2];
b4ff3a36 656 u8 reserved_at_42[0x4];
f91e6d89 657 u8 supported_atomic_req_8B_endianess_mode_1[0x1];
e281682b 658
b4ff3a36 659 u8 reserved_at_47[0x19];
e281682b 660
b4ff3a36 661 u8 reserved_at_60[0x20];
e281682b 662
b4ff3a36 663 u8 reserved_at_80[0x10];
f91e6d89 664 u8 atomic_operations[0x10];
e281682b 665
b4ff3a36 666 u8 reserved_at_a0[0x10];
f91e6d89
EBE		 667 u8 atomic_size_qp[0x10];
668
b4ff3a36 669 u8 reserved_at_c0[0x10];
e281682b
SM		 670 u8 atomic_size_dc[0x10];
671
b4ff3a36 672 u8 reserved_at_e0[0x720];
e281682b
SM		 673};
674
675struct mlx5_ifc_odp_cap_bits {
b4ff3a36 676 u8 reserved_at_0[0x40];
e281682b
SM		 677
678 u8 sig[0x1];
b4ff3a36 679 u8 reserved_at_41[0x1f];
e281682b 680
b4ff3a36 681 u8 reserved_at_60[0x20];
e281682b
SM		 682
683 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
684
685 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
686
687 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
688
b4ff3a36 689 u8 reserved_at_e0[0x720];
e281682b
SM		 690};
691
3f0393a5
SG		 692struct mlx5_ifc_calc_op {
693 u8 reserved_at_0[0x10];
694 u8 reserved_at_10[0x9];
695 u8 op_swap_endianness[0x1];
696 u8 op_min[0x1];
697 u8 op_xor[0x1];
698 u8 op_or[0x1];
699 u8 op_and[0x1];
700 u8 op_max[0x1];
701 u8 op_add[0x1];
702};
703
704struct mlx5_ifc_vector_calc_cap_bits {
705 u8 calc_matrix[0x1];
706 u8 reserved_at_1[0x1f];
707 u8 reserved_at_20[0x8];
708 u8 max_vec_count[0x8];
709 u8 reserved_at_30[0xd];
710 u8 max_chunk_size[0x3];
711 struct mlx5_ifc_calc_op calc0;
712 struct mlx5_ifc_calc_op calc1;
713 struct mlx5_ifc_calc_op calc2;
714 struct mlx5_ifc_calc_op calc3;
715
716 u8 reserved_at_e0[0x720];
717};
718
e281682b
SM		 719enum {
720 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
721 MLX5_WQ_TYPE_CYCLIC = 0x1,
7d5e1423 722 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
e281682b
SM		 723};
724
725enum {
726 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
727 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
728};
729
730enum {
731 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
732 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
733 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
734 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
735 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
736};
737
738enum {
739 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
740 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
741 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
742 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
743 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
744 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
745};
746
747enum {
748 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
749 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
750};
751
752enum {
753 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
754 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
755 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
756};
757
758enum {
759 MLX5_CAP_PORT_TYPE_IB = 0x0,
760 MLX5_CAP_PORT_TYPE_ETH = 0x1,
d29b796a
EC		 761};
762
b775516b 763struct mlx5_ifc_cmd_hca_cap_bits {
b4ff3a36 764 u8 reserved_at_0[0x80];
b775516b
EC		 765
766 u8 log_max_srq_sz[0x8];
767 u8 log_max_qp_sz[0x8];
b4ff3a36 768 u8 reserved_at_90[0xb];
b775516b
EC		 769 u8 log_max_qp[0x5];
770
b4ff3a36 771 u8 reserved_at_a0[0xb];
e281682b 772 u8 log_max_srq[0x5];
b4ff3a36 773 u8 reserved_at_b0[0x10];
b775516b 774
b4ff3a36 775 u8 reserved_at_c0[0x8];
b775516b 776 u8 log_max_cq_sz[0x8];
b4ff3a36 777 u8 reserved_at_d0[0xb];
b775516b
EC		 778 u8 log_max_cq[0x5];
779
780 u8 log_max_eq_sz[0x8];
b4ff3a36 781 u8 reserved_at_e8[0x2];
b775516b 782 u8 log_max_mkey[0x6];
b4ff3a36 783 u8 reserved_at_f0[0xc];
b775516b
EC		 784 u8 log_max_eq[0x4];
785
786 u8 max_indirection[0x8];
bcda1aca 787 u8 fixed_buffer_size[0x1];
b775516b 788 u8 log_max_mrw_sz[0x7];
b4ff3a36 789 u8 reserved_at_110[0x2];
b775516b 790 u8 log_max_bsf_list_size[0x6];
bcda1aca
AK		 791 u8 umr_extended_translation_offset[0x1];
792 u8 null_mkey[0x1];
b775516b
EC		 793 u8 log_max_klm_list_size[0x6];
794
b4ff3a36 795 u8 reserved_at_120[0xa];
b775516b 796 u8 log_max_ra_req_dc[0x6];
b4ff3a36 797 u8 reserved_at_130[0xa];
b775516b
EC		 798 u8 log_max_ra_res_dc[0x6];
799
b4ff3a36 800 u8 reserved_at_140[0xa];
b775516b 801 u8 log_max_ra_req_qp[0x6];
b4ff3a36 802 u8 reserved_at_150[0xa];
b775516b
EC		 803 u8 log_max_ra_res_qp[0x6];
804
805 u8 pad_cap[0x1];
806 u8 cc_query_allowed[0x1];
807 u8 cc_modify_allowed[0x1];
b4ff3a36 808 u8 reserved_at_163[0xd];
e281682b 809 u8 gid_table_size[0x10];
b775516b 810
e281682b
SM		 811 u8 out_of_seq_cnt[0x1];
812 u8 vport_counters[0x1];
7486216b 813 u8 retransmission_q_counters[0x1];
83b502a1
AV		 814 u8 reserved_at_183[0x1];
815 u8 modify_rq_counter_set_id[0x1];
816 u8 reserved_at_185[0x1];
b775516b
EC		 817 u8 max_qp_cnt[0xa];
818 u8 pkey_table_size[0x10];
819
e281682b
SM		 820 u8 vport_group_manager[0x1];
821 u8 vhca_group_manager[0x1];
822 u8 ib_virt[0x1];
823 u8 eth_virt[0x1];
b4ff3a36 824 u8 reserved_at_1a4[0x1];
e281682b
SM		 825 u8 ets[0x1];
826 u8 nic_flow_table[0x1];
54f0a411 827 u8 eswitch_flow_table[0x1];
e1c9c62b 828 u8 early_vf_enable[0x1];
cfdcbcea
GP		 829 u8 mcam_reg[0x1];
830 u8 pcam_reg[0x1];
b775516b 831 u8 local_ca_ack_delay[0x5];
4ce3bf2f 832 u8 port_module_event[0x1];
7b13558f 833 u8 reserved_at_1b1[0x1];
7d5e1423 834 u8 ports_check[0x1];
7b13558f 835 u8 reserved_at_1b3[0x1];
7d5e1423
SM		 836 u8 disable_link_up[0x1];
837 u8 beacon_led[0x1];
e281682b 838 u8 port_type[0x2];
b775516b
EC		 839 u8 num_ports[0x8];
840
f9a1ef72
EE		 841 u8 reserved_at_1c0[0x1];
842 u8 pps[0x1];
843 u8 pps_modify[0x1];
b775516b 844 u8 log_max_msg[0x5];
e1c9c62b 845 u8 reserved_at_1c8[0x4];
4f3961ee 846 u8 max_tc[0x4];
7486216b
SM		 847 u8 reserved_at_1d0[0x1];
848 u8 dcbx[0x1];
849 u8 reserved_at_1d2[0x4];
928cfe87
TT		 850 u8 rol_s[0x1];
851 u8 rol_g[0x1];
e1c9c62b 852 u8 reserved_at_1d8[0x1];
928cfe87
TT		 853 u8 wol_s[0x1];
854 u8 wol_g[0x1];
855 u8 wol_a[0x1];
856 u8 wol_b[0x1];
857 u8 wol_m[0x1];
858 u8 wol_u[0x1];
859 u8 wol_p[0x1];
b775516b
EC		 860
861 u8 stat_rate_support[0x10];
e1c9c62b 862 u8 reserved_at_1f0[0xc];
e281682b 863 u8 cqe_version[0x4];
b775516b 864
e281682b 865 u8 compact_address_vector[0x1];
7d5e1423 866 u8 striding_rq[0x1];
7b13558f 867 u8 reserved_at_202[0x2];
1015c2e8 868 u8 ipoib_basic_offloads[0x1];
e1c9c62b 869 u8 reserved_at_205[0xa];
e281682b 870 u8 drain_sigerr[0x1];
b775516b
EC		 871 u8 cmdif_checksum[0x2];
872 u8 sigerr_cqe[0x1];
e1c9c62b 873 u8 reserved_at_213[0x1];
b775516b
EC		 874 u8 wq_signature[0x1];
875 u8 sctr_data_cqe[0x1];
e1c9c62b 876 u8 reserved_at_216[0x1];
b775516b
EC		 877 u8 sho[0x1];
878 u8 tph[0x1];
879 u8 rf[0x1];
e281682b 880 u8 dct[0x1];
7486216b 881 u8 qos[0x1];
e281682b 882 u8 eth_net_offloads[0x1];
b775516b
EC		 883 u8 roce[0x1];
884 u8 atomic[0x1];
e1c9c62b 885 u8 reserved_at_21f[0x1];
b775516b
EC		 886
887 u8 cq_oi[0x1];
888 u8 cq_resize[0x1];
889 u8 cq_moderation[0x1];
e1c9c62b 890 u8 reserved_at_223[0x3];
e281682b 891 u8 cq_eq_remap[0x1];
b775516b
EC		 892 u8 pg[0x1];
893 u8 block_lb_mc[0x1];
e1c9c62b 894 u8 reserved_at_229[0x1];
e281682b 895 u8 scqe_break_moderation[0x1];
7d5e1423 896 u8 cq_period_start_from_cqe[0x1];
b775516b 897 u8 cd[0x1];
e1c9c62b 898 u8 reserved_at_22d[0x1];
b775516b 899 u8 apm[0x1];
3f0393a5 900 u8 vector_calc[0x1];
7d5e1423 901 u8 umr_ptr_rlky[0x1];
d2370e0a 902 u8 imaicl[0x1];
e1c9c62b 903 u8 reserved_at_232[0x4];
b775516b
EC		 904 u8 qkv[0x1];
905 u8 pkv[0x1];
b11a4f9c
HE		 906 u8 set_deth_sqpn[0x1];
907 u8 reserved_at_239[0x3];
b775516b
EC		 908 u8 xrc[0x1];
909 u8 ud[0x1];
910 u8 uc[0x1];
911 u8 rc[0x1];
912
a6d51b68
EC		 913 u8 uar_4k[0x1];
914 u8 reserved_at_241[0x9];
b775516b 915 u8 uar_sz[0x6];
e1c9c62b 916 u8 reserved_at_250[0x8];
b775516b
EC		 917 u8 log_pg_sz[0x8];
918
919 u8 bf[0x1];
0dbc6fe0 920 u8 driver_version[0x1];
e281682b 921 u8 pad_tx_eth_packet[0x1];
e1c9c62b 922 u8 reserved_at_263[0x8];
b775516b 923 u8 log_bf_reg_size[0x5];
84df61eb
AH		 924
925 u8 reserved_at_270[0xb];
926 u8 lag_master[0x1];
927 u8 num_lag_ports[0x4];
b775516b 928
e1c9c62b 929 u8 reserved_at_280[0x10];
b775516b
EC		 930 u8 max_wqe_sz_sq[0x10];
931
e1c9c62b 932 u8 reserved_at_2a0[0x10];
b775516b
EC		 933 u8 max_wqe_sz_rq[0x10];
934
e1c9c62b 935 u8 reserved_at_2c0[0x10];
b775516b
EC		 936 u8 max_wqe_sz_sq_dc[0x10];
937
e1c9c62b 938 u8 reserved_at_2e0[0x7];
b775516b
EC		 939 u8 max_qp_mcg[0x19];
940
e1c9c62b 941 u8 reserved_at_300[0x18];
b775516b
EC		 942 u8 log_max_mcg[0x8];
943
e1c9c62b 944 u8 reserved_at_320[0x3];
e281682b 945 u8 log_max_transport_domain[0x5];
e1c9c62b 946 u8 reserved_at_328[0x3];
b775516b 947 u8 log_max_pd[0x5];
e1c9c62b 948 u8 reserved_at_330[0xb];
b775516b
EC		 949 u8 log_max_xrcd[0x5];
950
a351a1b0
AV		 951 u8 reserved_at_340[0x8];
952 u8 log_max_flow_counter_bulk[0x8];
953 u8 max_flow_counter[0x10];
954
b775516b 955
e1c9c62b 956 u8 reserved_at_360[0x3];
b775516b 957 u8 log_max_rq[0x5];
e1c9c62b 958 u8 reserved_at_368[0x3];
b775516b 959 u8 log_max_sq[0x5];
e1c9c62b 960 u8 reserved_at_370[0x3];
b775516b 961 u8 log_max_tir[0x5];
e1c9c62b 962 u8 reserved_at_378[0x3];
b775516b
EC		 963 u8 log_max_tis[0x5];
964
e281682b 965 u8 basic_cyclic_rcv_wqe[0x1];
e1c9c62b 966 u8 reserved_at_381[0x2];
e281682b 967 u8 log_max_rmp[0x5];
e1c9c62b 968 u8 reserved_at_388[0x3];
e281682b 969 u8 log_max_rqt[0x5];
e1c9c62b 970 u8 reserved_at_390[0x3];
e281682b 971 u8 log_max_rqt_size[0x5];
e1c9c62b 972 u8 reserved_at_398[0x3];
b775516b
EC		 973 u8 log_max_tis_per_sq[0x5];
974
e1c9c62b 975 u8 reserved_at_3a0[0x3];
e281682b 976 u8 log_max_stride_sz_rq[0x5];
e1c9c62b 977 u8 reserved_at_3a8[0x3];
e281682b 978 u8 log_min_stride_sz_rq[0x5];
e1c9c62b 979 u8 reserved_at_3b0[0x3];
e281682b 980 u8 log_max_stride_sz_sq[0x5];
e1c9c62b 981 u8 reserved_at_3b8[0x3];
e281682b
SM		 982 u8 log_min_stride_sz_sq[0x5];
983
e1c9c62b 984 u8 reserved_at_3c0[0x1b];
e281682b
SM		 985 u8 log_max_wq_sz[0x5];
986
54f0a411 987 u8 nic_vport_change_event[0x1];
e1c9c62b 988 u8 reserved_at_3e1[0xa];
54f0a411 989 u8 log_max_vlan_list[0x5];
e1c9c62b 990 u8 reserved_at_3f0[0x3];
54f0a411 991 u8 log_max_current_mc_list[0x5];
e1c9c62b 992 u8 reserved_at_3f8[0x3];
54f0a411
SM		 993 u8 log_max_current_uc_list[0x5];
994
e1c9c62b 995 u8 reserved_at_400[0x80];
54f0a411 996
e1c9c62b 997 u8 reserved_at_480[0x3];
e281682b 998 u8 log_max_l2_table[0x5];
e1c9c62b 999 u8 reserved_at_488[0x8];
b775516b
EC		 1000 u8 log_uar_page_sz[0x10];
1001
e1c9c62b 1002 u8 reserved_at_4a0[0x20];
048ccca8 1003 u8 device_frequency_mhz[0x20];
b0844444 1004 u8 device_frequency_khz[0x20];
e1c9c62b 1005
a6d51b68
EC		 1006 u8 reserved_at_500[0x20];
1007 u8 num_of_uars_per_page[0x20];
1008 u8 reserved_at_540[0x40];
e1c9c62b
TT		 1009
1010 u8 reserved_at_580[0x3f];
7d5e1423 1011 u8 cqe_compression[0x1];
b775516b 1012
7d5e1423
SM		 1013 u8 cqe_compression_timeout[0x10];
1014 u8 cqe_compression_max_num[0x10];
b775516b 1015
7486216b
SM		 1016 u8 reserved_at_5e0[0x10];
1017 u8 tag_matching[0x1];
1018 u8 rndv_offload_rc[0x1];
1019 u8 rndv_offload_dc[0x1];
1020 u8 log_tag_matching_list_sz[0x5];
7b13558f 1021 u8 reserved_at_5f8[0x3];
7486216b
SM		 1022 u8 log_max_xrq[0x5];
1023
7b13558f 1024 u8 reserved_at_600[0x200];
b775516b
EC		 1025};
1026
81848731
SM		 1027enum mlx5_flow_destination_type {
1028 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1029 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1030 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
bd5251db
AV		 1031
1032 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
e281682b 1033};
b775516b 1034
e281682b
SM		 1035struct mlx5_ifc_dest_format_struct_bits {
1036 u8 destination_type[0x8];
1037 u8 destination_id[0x18];
b775516b 1038
b4ff3a36 1039 u8 reserved_at_20[0x20];
e281682b
SM		 1040};
1041
9dc0b289 1042struct mlx5_ifc_flow_counter_list_bits {
a351a1b0
AV		 1043 u8 clear[0x1];
1044 u8 num_of_counters[0xf];
9dc0b289
AV		 1045 u8 flow_counter_id[0x10];
1046
1047 u8 reserved_at_20[0x20];
1048};
1049
1050union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1051 struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1052 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1053 u8 reserved_at_0[0x40];
1054};
1055
e281682b
SM		 1056struct mlx5_ifc_fte_match_param_bits {
1057 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1058
1059 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1060
1061 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
b775516b 1062
b4ff3a36 1063 u8 reserved_at_600[0xa00];
b775516b
EC		 1064};
1065
e281682b
SM		 1066enum {
1067 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1068 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1069 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1070 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1071 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1072};
b775516b 1073
e281682b
SM		 1074struct mlx5_ifc_rx_hash_field_select_bits {
1075 u8 l3_prot_type[0x1];
1076 u8 l4_prot_type[0x1];
1077 u8 selected_fields[0x1e];
1078};
b775516b 1079
e281682b
SM		 1080enum {
1081 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
1082 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
b775516b
EC		 1083};
1084
e281682b
SM		 1085enum {
1086 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
1087 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
1088};
1089
1090struct mlx5_ifc_wq_bits {
1091 u8 wq_type[0x4];
1092 u8 wq_signature[0x1];
1093 u8 end_padding_mode[0x2];
1094 u8 cd_slave[0x1];
b4ff3a36 1095 u8 reserved_at_8[0x18];
b775516b 1096
e281682b
SM		 1097 u8 hds_skip_first_sge[0x1];
1098 u8 log2_hds_buf_size[0x3];
b4ff3a36 1099 u8 reserved_at_24[0x7];
e281682b
SM		 1100 u8 page_offset[0x5];
1101 u8 lwm[0x10];
b775516b 1102
b4ff3a36 1103 u8 reserved_at_40[0x8];
e281682b
SM		 1104 u8 pd[0x18];
1105
b4ff3a36 1106 u8 reserved_at_60[0x8];
e281682b
SM		 1107 u8 uar_page[0x18];
1108
1109 u8 dbr_addr[0x40];
1110
1111 u8 hw_counter[0x20];
1112
1113 u8 sw_counter[0x20];
1114
b4ff3a36 1115 u8 reserved_at_100[0xc];
e281682b 1116 u8 log_wq_stride[0x4];
b4ff3a36 1117 u8 reserved_at_110[0x3];
e281682b 1118 u8 log_wq_pg_sz[0x5];
b4ff3a36 1119 u8 reserved_at_118[0x3];
e281682b
SM		 1120 u8 log_wq_sz[0x5];
1121
7d5e1423
SM		 1122 u8 reserved_at_120[0x15];
1123 u8 log_wqe_num_of_strides[0x3];
1124 u8 two_byte_shift_en[0x1];
1125 u8 reserved_at_139[0x4];
1126 u8 log_wqe_stride_size[0x3];
1127
1128 u8 reserved_at_140[0x4c0];
b775516b 1129
e281682b 1130 struct mlx5_ifc_cmd_pas_bits pas[0];
b775516b
EC		 1131};
1132
e281682b 1133struct mlx5_ifc_rq_num_bits {
b4ff3a36 1134 u8 reserved_at_0[0x8];
e281682b
SM		 1135 u8 rq_num[0x18];
1136};
b775516b 1137
e281682b 1138struct mlx5_ifc_mac_address_layout_bits {
b4ff3a36 1139 u8 reserved_at_0[0x10];
e281682b 1140 u8 mac_addr_47_32[0x10];
b775516b 1141
e281682b
SM		 1142 u8 mac_addr_31_0[0x20];
1143};
1144
c0046cf7 1145struct mlx5_ifc_vlan_layout_bits {
b4ff3a36 1146 u8 reserved_at_0[0x14];
c0046cf7
SM		 1147 u8 vlan[0x0c];
1148
b4ff3a36 1149 u8 reserved_at_20[0x20];
c0046cf7
SM		 1150};
1151
e281682b 1152struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
b4ff3a36 1153 u8 reserved_at_0[0xa0];
e281682b
SM		 1154
1155 u8 min_time_between_cnps[0x20];
1156
b4ff3a36 1157 u8 reserved_at_c0[0x12];
e281682b 1158 u8 cnp_dscp[0x6];
b4ff3a36 1159 u8 reserved_at_d8[0x5];
e281682b
SM		 1160 u8 cnp_802p_prio[0x3];
1161
b4ff3a36 1162 u8 reserved_at_e0[0x720];
e281682b
SM		 1163};
1164
1165struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
b4ff3a36 1166 u8 reserved_at_0[0x60];
e281682b 1167
b4ff3a36 1168 u8 reserved_at_60[0x4];
e281682b 1169 u8 clamp_tgt_rate[0x1];
b4ff3a36 1170 u8 reserved_at_65[0x3];
e281682b 1171 u8 clamp_tgt_rate_after_time_inc[0x1];
b4ff3a36 1172 u8 reserved_at_69[0x17];
e281682b 1173
b4ff3a36 1174 u8 reserved_at_80[0x20];
e281682b
SM		 1175
1176 u8 rpg_time_reset[0x20];
1177
1178 u8 rpg_byte_reset[0x20];
1179
1180 u8 rpg_threshold[0x20];
1181
1182 u8 rpg_max_rate[0x20];
1183
1184 u8 rpg_ai_rate[0x20];
1185
1186 u8 rpg_hai_rate[0x20];
1187
1188 u8 rpg_gd[0x20];
1189
1190 u8 rpg_min_dec_fac[0x20];
1191
1192 u8 rpg_min_rate[0x20];
1193
b4ff3a36 1194 u8 reserved_at_1c0[0xe0];
e281682b
SM		 1195
1196 u8 rate_to_set_on_first_cnp[0x20];
1197
1198 u8 dce_tcp_g[0x20];
1199
1200 u8 dce_tcp_rtt[0x20];
1201
1202 u8 rate_reduce_monitor_period[0x20];
1203
b4ff3a36 1204 u8 reserved_at_320[0x20];
e281682b
SM		 1205
1206 u8 initial_alpha_value[0x20];
1207
b4ff3a36 1208 u8 reserved_at_360[0x4a0];
e281682b
SM		 1209};
1210
1211struct mlx5_ifc_cong_control_802_1qau_rp_bits {
b4ff3a36 1212 u8 reserved_at_0[0x80];
e281682b
SM		 1213
1214 u8 rppp_max_rps[0x20];
1215
1216 u8 rpg_time_reset[0x20];
1217
1218 u8 rpg_byte_reset[0x20];
1219
1220 u8 rpg_threshold[0x20];
1221
1222 u8 rpg_max_rate[0x20];
1223
1224 u8 rpg_ai_rate[0x20];
1225
1226 u8 rpg_hai_rate[0x20];
1227
1228 u8 rpg_gd[0x20];
1229
1230 u8 rpg_min_dec_fac[0x20];
1231
1232 u8 rpg_min_rate[0x20];
1233
b4ff3a36 1234 u8 reserved_at_1c0[0x640];
e281682b
SM		 1235};
1236
1237enum {
1238 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1239 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1240 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1241};
1242
1243struct mlx5_ifc_resize_field_select_bits {
1244 u8 resize_field_select[0x20];
1245};
1246
1247enum {
1248 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1249 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1250 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1251 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1252};
1253
1254struct mlx5_ifc_modify_field_select_bits {
1255 u8 modify_field_select[0x20];
1256};
1257
1258struct mlx5_ifc_field_select_r_roce_np_bits {
1259 u8 field_select_r_roce_np[0x20];
1260};
1261
1262struct mlx5_ifc_field_select_r_roce_rp_bits {
1263 u8 field_select_r_roce_rp[0x20];
1264};
1265
1266enum {
1267 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1268 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1269 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1270 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1271 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1272 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1273 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1274 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1275 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1276 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1277};
1278
1279struct mlx5_ifc_field_select_802_1qau_rp_bits {
1280 u8 field_select_8021qaurp[0x20];
1281};
1282
1283struct mlx5_ifc_phys_layer_cntrs_bits {
1284 u8 time_since_last_clear_high[0x20];
1285
1286 u8 time_since_last_clear_low[0x20];
1287
1288 u8 symbol_errors_high[0x20];
1289
1290 u8 symbol_errors_low[0x20];
1291
1292 u8 sync_headers_errors_high[0x20];
1293
1294 u8 sync_headers_errors_low[0x20];
1295
1296 u8 edpl_bip_errors_lane0_high[0x20];
1297
1298 u8 edpl_bip_errors_lane0_low[0x20];
1299
1300 u8 edpl_bip_errors_lane1_high[0x20];
1301
1302 u8 edpl_bip_errors_lane1_low[0x20];
1303
1304 u8 edpl_bip_errors_lane2_high[0x20];
1305
1306 u8 edpl_bip_errors_lane2_low[0x20];
1307
1308 u8 edpl_bip_errors_lane3_high[0x20];
1309
1310 u8 edpl_bip_errors_lane3_low[0x20];
1311
1312 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1313
1314 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1315
1316 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1317
1318 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1319
1320 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1321
1322 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1323
1324 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1325
1326 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1327
1328 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1329
1330 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1331
1332 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1333
1334 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1335
1336 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1337
1338 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1339
1340 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1341
1342 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1343
1344 u8 rs_fec_corrected_blocks_high[0x20];
1345
1346 u8 rs_fec_corrected_blocks_low[0x20];
1347
1348 u8 rs_fec_uncorrectable_blocks_high[0x20];
1349
1350 u8 rs_fec_uncorrectable_blocks_low[0x20];
1351
1352 u8 rs_fec_no_errors_blocks_high[0x20];
1353
1354 u8 rs_fec_no_errors_blocks_low[0x20];
1355
1356 u8 rs_fec_single_error_blocks_high[0x20];
1357
1358 u8 rs_fec_single_error_blocks_low[0x20];
1359
1360 u8 rs_fec_corrected_symbols_total_high[0x20];
1361
1362 u8 rs_fec_corrected_symbols_total_low[0x20];
1363
1364 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1365
1366 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1367
1368 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1369
1370 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1371
1372 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1373
1374 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1375
1376 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1377
1378 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1379
1380 u8 link_down_events[0x20];
1381
1382 u8 successful_recovery_events[0x20];
1383
b4ff3a36 1384 u8 reserved_at_640[0x180];
e281682b
SM		 1385};
1386
d8dc0508
GP		 1387struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1388 u8 time_since_last_clear_high[0x20];
1389
1390 u8 time_since_last_clear_low[0x20];
1391
1392 u8 phy_received_bits_high[0x20];
1393
1394 u8 phy_received_bits_low[0x20];
1395
1396 u8 phy_symbol_errors_high[0x20];
1397
1398 u8 phy_symbol_errors_low[0x20];
1399
1400 u8 phy_corrected_bits_high[0x20];
1401
1402 u8 phy_corrected_bits_low[0x20];
1403
1404 u8 phy_corrected_bits_lane0_high[0x20];
1405
1406 u8 phy_corrected_bits_lane0_low[0x20];
1407
1408 u8 phy_corrected_bits_lane1_high[0x20];
1409
1410 u8 phy_corrected_bits_lane1_low[0x20];
1411
1412 u8 phy_corrected_bits_lane2_high[0x20];
1413
1414 u8 phy_corrected_bits_lane2_low[0x20];
1415
1416 u8 phy_corrected_bits_lane3_high[0x20];
1417
1418 u8 phy_corrected_bits_lane3_low[0x20];
1419
1420 u8 reserved_at_200[0x5c0];
1421};
1422
1c64bf6f
MY		 1423struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1424 u8 symbol_error_counter[0x10];
1425
1426 u8 link_error_recovery_counter[0x8];
1427
1428 u8 link_downed_counter[0x8];
1429
1430 u8 port_rcv_errors[0x10];
1431
1432 u8 port_rcv_remote_physical_errors[0x10];
1433
1434 u8 port_rcv_switch_relay_errors[0x10];
1435
1436 u8 port_xmit_discards[0x10];
1437
1438 u8 port_xmit_constraint_errors[0x8];
1439
1440 u8 port_rcv_constraint_errors[0x8];
1441
1442 u8 reserved_at_70[0x8];
1443
1444 u8 link_overrun_errors[0x8];
1445
1446 u8 reserved_at_80[0x10];
1447
1448 u8 vl_15_dropped[0x10];
1449
1450 u8 reserved_at_a0[0xa0];
1451};
1452
e281682b
SM		 1453struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1454 u8 transmit_queue_high[0x20];
1455
1456 u8 transmit_queue_low[0x20];
1457
b4ff3a36 1458 u8 reserved_at_40[0x780];
e281682b
SM		 1459};
1460
1461struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1462 u8 rx_octets_high[0x20];
1463
1464 u8 rx_octets_low[0x20];
1465
b4ff3a36 1466 u8 reserved_at_40[0xc0];
e281682b
SM		 1467
1468 u8 rx_frames_high[0x20];
1469
1470 u8 rx_frames_low[0x20];
1471
1472 u8 tx_octets_high[0x20];
1473
1474 u8 tx_octets_low[0x20];
1475
b4ff3a36 1476 u8 reserved_at_180[0xc0];
e281682b
SM		 1477
1478 u8 tx_frames_high[0x20];
1479
1480 u8 tx_frames_low[0x20];
1481
1482 u8 rx_pause_high[0x20];
1483
1484 u8 rx_pause_low[0x20];
1485
1486 u8 rx_pause_duration_high[0x20];
1487
1488 u8 rx_pause_duration_low[0x20];
1489
1490 u8 tx_pause_high[0x20];
1491
1492 u8 tx_pause_low[0x20];
1493
1494 u8 tx_pause_duration_high[0x20];
1495
1496 u8 tx_pause_duration_low[0x20];
1497
1498 u8 rx_pause_transition_high[0x20];
1499
1500 u8 rx_pause_transition_low[0x20];
1501
b4ff3a36 1502 u8 reserved_at_3c0[0x400];
e281682b
SM		 1503};
1504
1505struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1506 u8 port_transmit_wait_high[0x20];
1507
1508 u8 port_transmit_wait_low[0x20];
1509
b4ff3a36 1510 u8 reserved_at_40[0x780];
e281682b
SM		 1511};
1512
1513struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1514 u8 dot3stats_alignment_errors_high[0x20];
1515
1516 u8 dot3stats_alignment_errors_low[0x20];
1517
1518 u8 dot3stats_fcs_errors_high[0x20];
1519
1520 u8 dot3stats_fcs_errors_low[0x20];
1521
1522 u8 dot3stats_single_collision_frames_high[0x20];
1523
1524 u8 dot3stats_single_collision_frames_low[0x20];
1525
1526 u8 dot3stats_multiple_collision_frames_high[0x20];
1527
1528 u8 dot3stats_multiple_collision_frames_low[0x20];
1529
1530 u8 dot3stats_sqe_test_errors_high[0x20];
1531
1532 u8 dot3stats_sqe_test_errors_low[0x20];
1533
1534 u8 dot3stats_deferred_transmissions_high[0x20];
1535
1536 u8 dot3stats_deferred_transmissions_low[0x20];
1537
1538 u8 dot3stats_late_collisions_high[0x20];
1539
1540 u8 dot3stats_late_collisions_low[0x20];
1541
1542 u8 dot3stats_excessive_collisions_high[0x20];
1543
1544 u8 dot3stats_excessive_collisions_low[0x20];
1545
1546 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1547
1548 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1549
1550 u8 dot3stats_carrier_sense_errors_high[0x20];
1551
1552 u8 dot3stats_carrier_sense_errors_low[0x20];
1553
1554 u8 dot3stats_frame_too_longs_high[0x20];
1555
1556 u8 dot3stats_frame_too_longs_low[0x20];
1557
1558 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1559
1560 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1561
1562 u8 dot3stats_symbol_errors_high[0x20];
1563
1564 u8 dot3stats_symbol_errors_low[0x20];
1565
1566 u8 dot3control_in_unknown_opcodes_high[0x20];
1567
1568 u8 dot3control_in_unknown_opcodes_low[0x20];
1569
1570 u8 dot3in_pause_frames_high[0x20];
1571
1572 u8 dot3in_pause_frames_low[0x20];
1573
1574 u8 dot3out_pause_frames_high[0x20];
1575
1576 u8 dot3out_pause_frames_low[0x20];
1577
b4ff3a36 1578 u8 reserved_at_400[0x3c0];
e281682b
SM		 1579};
1580
1581struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1582 u8 ether_stats_drop_events_high[0x20];
1583
1584 u8 ether_stats_drop_events_low[0x20];
1585
1586 u8 ether_stats_octets_high[0x20];
1587
1588 u8 ether_stats_octets_low[0x20];
1589
1590 u8 ether_stats_pkts_high[0x20];
1591
1592 u8 ether_stats_pkts_low[0x20];
1593
1594 u8 ether_stats_broadcast_pkts_high[0x20];
1595
1596 u8 ether_stats_broadcast_pkts_low[0x20];
1597
1598 u8 ether_stats_multicast_pkts_high[0x20];
1599
1600 u8 ether_stats_multicast_pkts_low[0x20];
1601
1602 u8 ether_stats_crc_align_errors_high[0x20];
1603
1604 u8 ether_stats_crc_align_errors_low[0x20];
1605
1606 u8 ether_stats_undersize_pkts_high[0x20];
1607
1608 u8 ether_stats_undersize_pkts_low[0x20];
1609
1610 u8 ether_stats_oversize_pkts_high[0x20];
1611
1612 u8 ether_stats_oversize_pkts_low[0x20];
1613
1614 u8 ether_stats_fragments_high[0x20];
1615
1616 u8 ether_stats_fragments_low[0x20];
1617
1618 u8 ether_stats_jabbers_high[0x20];
1619
1620 u8 ether_stats_jabbers_low[0x20];
1621
1622 u8 ether_stats_collisions_high[0x20];
1623
1624 u8 ether_stats_collisions_low[0x20];
1625
1626 u8 ether_stats_pkts64octets_high[0x20];
1627
1628 u8 ether_stats_pkts64octets_low[0x20];
1629
1630 u8 ether_stats_pkts65to127octets_high[0x20];
1631
1632 u8 ether_stats_pkts65to127octets_low[0x20];
1633
1634 u8 ether_stats_pkts128to255octets_high[0x20];
1635
1636 u8 ether_stats_pkts128to255octets_low[0x20];
1637
1638 u8 ether_stats_pkts256to511octets_high[0x20];
1639
1640 u8 ether_stats_pkts256to511octets_low[0x20];
1641
1642 u8 ether_stats_pkts512to1023octets_high[0x20];
1643
1644 u8 ether_stats_pkts512to1023octets_low[0x20];
1645
1646 u8 ether_stats_pkts1024to1518octets_high[0x20];
1647
1648 u8 ether_stats_pkts1024to1518octets_low[0x20];
1649
1650 u8 ether_stats_pkts1519to2047octets_high[0x20];
1651
1652 u8 ether_stats_pkts1519to2047octets_low[0x20];
1653
1654 u8 ether_stats_pkts2048to4095octets_high[0x20];
1655
1656 u8 ether_stats_pkts2048to4095octets_low[0x20];
1657
1658 u8 ether_stats_pkts4096to8191octets_high[0x20];
1659
1660 u8 ether_stats_pkts4096to8191octets_low[0x20];
1661
1662 u8 ether_stats_pkts8192to10239octets_high[0x20];
1663
1664 u8 ether_stats_pkts8192to10239octets_low[0x20];
1665
b4ff3a36 1666 u8 reserved_at_540[0x280];
e281682b
SM		 1667};
1668
1669struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1670 u8 if_in_octets_high[0x20];
1671
1672 u8 if_in_octets_low[0x20];
1673
1674 u8 if_in_ucast_pkts_high[0x20];
1675
1676 u8 if_in_ucast_pkts_low[0x20];
1677
1678 u8 if_in_discards_high[0x20];
1679
1680 u8 if_in_discards_low[0x20];
1681
1682 u8 if_in_errors_high[0x20];
1683
1684 u8 if_in_errors_low[0x20];
1685
1686 u8 if_in_unknown_protos_high[0x20];
1687
1688 u8 if_in_unknown_protos_low[0x20];
1689
1690 u8 if_out_octets_high[0x20];
1691
1692 u8 if_out_octets_low[0x20];
1693
1694 u8 if_out_ucast_pkts_high[0x20];
1695
1696 u8 if_out_ucast_pkts_low[0x20];
1697
1698 u8 if_out_discards_high[0x20];
1699
1700 u8 if_out_discards_low[0x20];
1701
1702 u8 if_out_errors_high[0x20];
1703
1704 u8 if_out_errors_low[0x20];
1705
1706 u8 if_in_multicast_pkts_high[0x20];
1707
1708 u8 if_in_multicast_pkts_low[0x20];
1709
1710 u8 if_in_broadcast_pkts_high[0x20];
1711
1712 u8 if_in_broadcast_pkts_low[0x20];
1713
1714 u8 if_out_multicast_pkts_high[0x20];
1715
1716 u8 if_out_multicast_pkts_low[0x20];
1717
1718 u8 if_out_broadcast_pkts_high[0x20];
1719
1720 u8 if_out_broadcast_pkts_low[0x20];
1721
b4ff3a36 1722 u8 reserved_at_340[0x480];
e281682b
SM		 1723};
1724
1725struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1726 u8 a_frames_transmitted_ok_high[0x20];
1727
1728 u8 a_frames_transmitted_ok_low[0x20];
1729
1730 u8 a_frames_received_ok_high[0x20];
1731
1732 u8 a_frames_received_ok_low[0x20];
1733
1734 u8 a_frame_check_sequence_errors_high[0x20];
1735
1736 u8 a_frame_check_sequence_errors_low[0x20];
1737
1738 u8 a_alignment_errors_high[0x20];
1739
1740 u8 a_alignment_errors_low[0x20];
1741
1742 u8 a_octets_transmitted_ok_high[0x20];
1743
1744 u8 a_octets_transmitted_ok_low[0x20];
1745
1746 u8 a_octets_received_ok_high[0x20];
1747
1748 u8 a_octets_received_ok_low[0x20];
1749
1750 u8 a_multicast_frames_xmitted_ok_high[0x20];
1751
1752 u8 a_multicast_frames_xmitted_ok_low[0x20];
1753
1754 u8 a_broadcast_frames_xmitted_ok_high[0x20];
1755
1756 u8 a_broadcast_frames_xmitted_ok_low[0x20];
1757
1758 u8 a_multicast_frames_received_ok_high[0x20];
1759
1760 u8 a_multicast_frames_received_ok_low[0x20];
1761
1762 u8 a_broadcast_frames_received_ok_high[0x20];
1763
1764 u8 a_broadcast_frames_received_ok_low[0x20];
1765
1766 u8 a_in_range_length_errors_high[0x20];
1767
1768 u8 a_in_range_length_errors_low[0x20];
1769
1770 u8 a_out_of_range_length_field_high[0x20];
1771
1772 u8 a_out_of_range_length_field_low[0x20];
1773
1774 u8 a_frame_too_long_errors_high[0x20];
1775
1776 u8 a_frame_too_long_errors_low[0x20];
1777
1778 u8 a_symbol_error_during_carrier_high[0x20];
1779
1780 u8 a_symbol_error_during_carrier_low[0x20];
1781
1782 u8 a_mac_control_frames_transmitted_high[0x20];
1783
1784 u8 a_mac_control_frames_transmitted_low[0x20];
1785
1786 u8 a_mac_control_frames_received_high[0x20];
1787
1788 u8 a_mac_control_frames_received_low[0x20];
1789
1790 u8 a_unsupported_opcodes_received_high[0x20];
1791
1792 u8 a_unsupported_opcodes_received_low[0x20];
1793
1794 u8 a_pause_mac_ctrl_frames_received_high[0x20];
1795
1796 u8 a_pause_mac_ctrl_frames_received_low[0x20];
1797
1798 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
1799
1800 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
1801
b4ff3a36 1802 u8 reserved_at_4c0[0x300];
e281682b
SM		 1803};
1804
1805struct mlx5_ifc_cmd_inter_comp_event_bits {
1806 u8 command_completion_vector[0x20];
1807
b4ff3a36 1808 u8 reserved_at_20[0xc0];
e281682b
SM		 1809};
1810
1811struct mlx5_ifc_stall_vl_event_bits {
b4ff3a36 1812 u8 reserved_at_0[0x18];
e281682b 1813 u8 port_num[0x1];
b4ff3a36 1814 u8 reserved_at_19[0x3];
e281682b
SM		 1815 u8 vl[0x4];
1816
b4ff3a36 1817 u8 reserved_at_20[0xa0];
e281682b
SM		 1818};
1819
1820struct mlx5_ifc_db_bf_congestion_event_bits {
1821 u8 event_subtype[0x8];
b4ff3a36 1822 u8 reserved_at_8[0x8];
e281682b 1823 u8 congestion_level[0x8];
b4ff3a36 1824 u8 reserved_at_18[0x8];
e281682b 1825
b4ff3a36 1826 u8 reserved_at_20[0xa0];
e281682b
SM		 1827};
1828
1829struct mlx5_ifc_gpio_event_bits {
b4ff3a36 1830 u8 reserved_at_0[0x60];
e281682b
SM		 1831
1832 u8 gpio_event_hi[0x20];
1833
1834 u8 gpio_event_lo[0x20];
1835
b4ff3a36 1836 u8 reserved_at_a0[0x40];
e281682b
SM		 1837};
1838
1839struct mlx5_ifc_port_state_change_event_bits {
b4ff3a36 1840 u8 reserved_at_0[0x40];
e281682b
SM		 1841
1842 u8 port_num[0x4];
b4ff3a36 1843 u8 reserved_at_44[0x1c];
e281682b 1844
b4ff3a36 1845 u8 reserved_at_60[0x80];
e281682b
SM		 1846};
1847
1848struct mlx5_ifc_dropped_packet_logged_bits {
b4ff3a36 1849 u8 reserved_at_0[0xe0];
e281682b
SM		 1850};
1851
1852enum {
1853 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
1854 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
1855};
1856
1857struct mlx5_ifc_cq_error_bits {
b4ff3a36 1858 u8 reserved_at_0[0x8];
e281682b
SM		 1859 u8 cqn[0x18];
1860
b4ff3a36 1861 u8 reserved_at_20[0x20];
e281682b 1862
b4ff3a36 1863 u8 reserved_at_40[0x18];
e281682b
SM		 1864 u8 syndrome[0x8];
1865
b4ff3a36 1866 u8 reserved_at_60[0x80];
e281682b
SM		 1867};
1868
1869struct mlx5_ifc_rdma_page_fault_event_bits {
1870 u8 bytes_committed[0x20];
1871
1872 u8 r_key[0x20];
1873
b4ff3a36 1874 u8 reserved_at_40[0x10];
e281682b
SM		 1875 u8 packet_len[0x10];
1876
1877 u8 rdma_op_len[0x20];
1878
1879 u8 rdma_va[0x40];
1880
b4ff3a36 1881 u8 reserved_at_c0[0x5];
e281682b
SM		 1882 u8 rdma[0x1];
1883 u8 write[0x1];
1884 u8 requestor[0x1];
1885 u8 qp_number[0x18];
1886};
1887
1888struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1889 u8 bytes_committed[0x20];
1890
b4ff3a36 1891 u8 reserved_at_20[0x10];
e281682b
SM		 1892 u8 wqe_index[0x10];
1893
b4ff3a36 1894 u8 reserved_at_40[0x10];
e281682b
SM		 1895 u8 len[0x10];
1896
b4ff3a36 1897 u8 reserved_at_60[0x60];
e281682b 1898
b4ff3a36 1899 u8 reserved_at_c0[0x5];
e281682b
SM		 1900 u8 rdma[0x1];
1901 u8 write_read[0x1];
1902 u8 requestor[0x1];
1903 u8 qpn[0x18];
1904};
1905
1906struct mlx5_ifc_qp_events_bits {
b4ff3a36 1907 u8 reserved_at_0[0xa0];
e281682b
SM		 1908
1909 u8 type[0x8];
b4ff3a36 1910 u8 reserved_at_a8[0x18];
e281682b 1911
b4ff3a36 1912 u8 reserved_at_c0[0x8];
e281682b
SM		 1913 u8 qpn_rqn_sqn[0x18];
1914};
1915
1916struct mlx5_ifc_dct_events_bits {
b4ff3a36 1917 u8 reserved_at_0[0xc0];
e281682b 1918
b4ff3a36 1919 u8 reserved_at_c0[0x8];
e281682b
SM		 1920 u8 dct_number[0x18];
1921};
1922
1923struct mlx5_ifc_comp_event_bits {
b4ff3a36 1924 u8 reserved_at_0[0xc0];
e281682b 1925
b4ff3a36 1926 u8 reserved_at_c0[0x8];
e281682b
SM		 1927 u8 cq_number[0x18];
1928};
1929
1930enum {
1931 MLX5_QPC_STATE_RST = 0x0,
1932 MLX5_QPC_STATE_INIT = 0x1,
1933 MLX5_QPC_STATE_RTR = 0x2,
1934 MLX5_QPC_STATE_RTS = 0x3,
1935 MLX5_QPC_STATE_SQER = 0x4,
1936 MLX5_QPC_STATE_ERR = 0x6,
1937 MLX5_QPC_STATE_SQD = 0x7,
1938 MLX5_QPC_STATE_SUSPENDED = 0x9,
1939};
1940
1941enum {
1942 MLX5_QPC_ST_RC = 0x0,
1943 MLX5_QPC_ST_UC = 0x1,
1944 MLX5_QPC_ST_UD = 0x2,
1945 MLX5_QPC_ST_XRC = 0x3,
1946 MLX5_QPC_ST_DCI = 0x5,
1947 MLX5_QPC_ST_QP0 = 0x7,
1948 MLX5_QPC_ST_QP1 = 0x8,
1949 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
1950 MLX5_QPC_ST_REG_UMR = 0xc,
1951};
1952
1953enum {
1954 MLX5_QPC_PM_STATE_ARMED = 0x0,
1955 MLX5_QPC_PM_STATE_REARM = 0x1,
1956 MLX5_QPC_PM_STATE_RESERVED = 0x2,
1957 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
1958};
1959
1960enum {
1961 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
1962 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
1963};
1964
1965enum {
1966 MLX5_QPC_MTU_256_BYTES = 0x1,
1967 MLX5_QPC_MTU_512_BYTES = 0x2,
1968 MLX5_QPC_MTU_1K_BYTES = 0x3,
1969 MLX5_QPC_MTU_2K_BYTES = 0x4,
1970 MLX5_QPC_MTU_4K_BYTES = 0x5,
1971 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
1972};
1973
1974enum {
1975 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
1976 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
1977 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
1978 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
1979 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
1980 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
1981 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
1982 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
1983};
1984
1985enum {
1986 MLX5_QPC_CS_REQ_DISABLE = 0x0,
1987 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
1988 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
1989};
1990
1991enum {
1992 MLX5_QPC_CS_RES_DISABLE = 0x0,
1993 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
1994 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
1995};
1996
1997struct mlx5_ifc_qpc_bits {
1998 u8 state[0x4];
84df61eb 1999 u8 lag_tx_port_affinity[0x4];
e281682b 2000 u8 st[0x8];
b4ff3a36 2001 u8 reserved_at_10[0x3];
e281682b 2002 u8 pm_state[0x2];
b4ff3a36 2003 u8 reserved_at_15[0x7];
e281682b 2004 u8 end_padding_mode[0x2];
b4ff3a36 2005 u8 reserved_at_1e[0x2];
e281682b
SM		 2006
2007 u8 wq_signature[0x1];
2008 u8 block_lb_mc[0x1];
2009 u8 atomic_like_write_en[0x1];
2010 u8 latency_sensitive[0x1];
b4ff3a36 2011 u8 reserved_at_24[0x1];
e281682b 2012 u8 drain_sigerr[0x1];
b4ff3a36 2013 u8 reserved_at_26[0x2];
e281682b
SM		 2014 u8 pd[0x18];
2015
2016 u8 mtu[0x3];
2017 u8 log_msg_max[0x5];
b4ff3a36 2018 u8 reserved_at_48[0x1];
e281682b
SM		 2019 u8 log_rq_size[0x4];
2020 u8 log_rq_stride[0x3];
2021 u8 no_sq[0x1];
2022 u8 log_sq_size[0x4];
b4ff3a36 2023 u8 reserved_at_55[0x6];
e281682b 2024 u8 rlky[0x1];
1015c2e8 2025 u8 ulp_stateless_offload_mode[0x4];
e281682b
SM		 2026
2027 u8 counter_set_id[0x8];
2028 u8 uar_page[0x18];
2029
b4ff3a36 2030 u8 reserved_at_80[0x8];
e281682b
SM		 2031 u8 user_index[0x18];
2032
b4ff3a36 2033 u8 reserved_at_a0[0x3];
e281682b
SM		 2034 u8 log_page_size[0x5];
2035 u8 remote_qpn[0x18];
2036
2037 struct mlx5_ifc_ads_bits primary_address_path;
2038
2039 struct mlx5_ifc_ads_bits secondary_address_path;
2040
2041 u8 log_ack_req_freq[0x4];
b4ff3a36 2042 u8 reserved_at_384[0x4];
e281682b 2043 u8 log_sra_max[0x3];
b4ff3a36 2044 u8 reserved_at_38b[0x2];
e281682b
SM		 2045 u8 retry_count[0x3];
2046 u8 rnr_retry[0x3];
b4ff3a36 2047 u8 reserved_at_393[0x1];
e281682b
SM		 2048 u8 fre[0x1];
2049 u8 cur_rnr_retry[0x3];
2050 u8 cur_retry_count[0x3];
b4ff3a36 2051 u8 reserved_at_39b[0x5];
e281682b 2052
b4ff3a36 2053 u8 reserved_at_3a0[0x20];
e281682b 2054
b4ff3a36 2055 u8 reserved_at_3c0[0x8];
e281682b
SM		 2056 u8 next_send_psn[0x18];
2057
b4ff3a36 2058 u8 reserved_at_3e0[0x8];
e281682b
SM		 2059 u8 cqn_snd[0x18];
2060
09a7d9ec
SM		 2061 u8 reserved_at_400[0x8];
2062 u8 deth_sqpn[0x18];
2063
2064 u8 reserved_at_420[0x20];
e281682b 2065
b4ff3a36 2066 u8 reserved_at_440[0x8];
e281682b
SM		 2067 u8 last_acked_psn[0x18];
2068
b4ff3a36 2069 u8 reserved_at_460[0x8];
e281682b
SM		 2070 u8 ssn[0x18];
2071
b4ff3a36 2072 u8 reserved_at_480[0x8];
e281682b 2073 u8 log_rra_max[0x3];
b4ff3a36 2074 u8 reserved_at_48b[0x1];
e281682b
SM		 2075 u8 atomic_mode[0x4];
2076 u8 rre[0x1];
2077 u8 rwe[0x1];
2078 u8 rae[0x1];
b4ff3a36 2079 u8 reserved_at_493[0x1];
e281682b 2080 u8 page_offset[0x6];
b4ff3a36 2081 u8 reserved_at_49a[0x3];
e281682b
SM		 2082 u8 cd_slave_receive[0x1];
2083 u8 cd_slave_send[0x1];
2084 u8 cd_master[0x1];
2085
b4ff3a36 2086 u8 reserved_at_4a0[0x3];
e281682b
SM		 2087 u8 min_rnr_nak[0x5];
2088 u8 next_rcv_psn[0x18];
2089
b4ff3a36 2090 u8 reserved_at_4c0[0x8];
e281682b
SM		 2091 u8 xrcd[0x18];
2092
b4ff3a36 2093 u8 reserved_at_4e0[0x8];
e281682b
SM		 2094 u8 cqn_rcv[0x18];
2095
2096 u8 dbr_addr[0x40];
2097
2098 u8 q_key[0x20];
2099
b4ff3a36 2100 u8 reserved_at_560[0x5];
e281682b 2101 u8 rq_type[0x3];
7486216b 2102 u8 srqn_rmpn_xrqn[0x18];
e281682b 2103
b4ff3a36 2104 u8 reserved_at_580[0x8];
e281682b
SM		 2105 u8 rmsn[0x18];
2106
2107 u8 hw_sq_wqebb_counter[0x10];
2108 u8 sw_sq_wqebb_counter[0x10];
2109
2110 u8 hw_rq_counter[0x20];
2111
2112 u8 sw_rq_counter[0x20];
2113
b4ff3a36 2114 u8 reserved_at_600[0x20];
e281682b 2115
b4ff3a36 2116 u8 reserved_at_620[0xf];
e281682b
SM		 2117 u8 cgs[0x1];
2118 u8 cs_req[0x8];
2119 u8 cs_res[0x8];
2120
2121 u8 dc_access_key[0x40];
2122
b4ff3a36 2123 u8 reserved_at_680[0xc0];
e281682b
SM		 2124};
2125
2126struct mlx5_ifc_roce_addr_layout_bits {
2127 u8 source_l3_address[16][0x8];
2128
b4ff3a36 2129 u8 reserved_at_80[0x3];
e281682b
SM		 2130 u8 vlan_valid[0x1];
2131 u8 vlan_id[0xc];
2132 u8 source_mac_47_32[0x10];
2133
2134 u8 source_mac_31_0[0x20];
2135
b4ff3a36 2136 u8 reserved_at_c0[0x14];
e281682b
SM		 2137 u8 roce_l3_type[0x4];
2138 u8 roce_version[0x8];
2139
b4ff3a36 2140 u8 reserved_at_e0[0x20];
e281682b
SM		 2141};
2142
2143union mlx5_ifc_hca_cap_union_bits {
2144 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2145 struct mlx5_ifc_odp_cap_bits odp_cap;
2146 struct mlx5_ifc_atomic_caps_bits atomic_caps;
2147 struct mlx5_ifc_roce_cap_bits roce_cap;
2148 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2149 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
495716b1 2150 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
d6666753 2151 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
3f0393a5 2152 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
7486216b 2153 struct mlx5_ifc_qos_cap_bits qos_cap;
b4ff3a36 2154 u8 reserved_at_0[0x8000];
e281682b
SM		 2155};
2156
2157enum {
2158 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
2159 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
2160 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
9dc0b289 2161 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
7adbde20
HHZ		 2162 MLX5_FLOW_CONTEXT_ACTION_ENCAP = 0x10,
2163 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
e281682b
SM		 2164};
2165
2166struct mlx5_ifc_flow_context_bits {
b4ff3a36 2167 u8 reserved_at_0[0x20];
e281682b
SM		 2168
2169 u8 group_id[0x20];
2170
b4ff3a36 2171 u8 reserved_at_40[0x8];
e281682b
SM		 2172 u8 flow_tag[0x18];
2173
b4ff3a36 2174 u8 reserved_at_60[0x10];
e281682b
SM		 2175 u8 action[0x10];
2176
b4ff3a36 2177 u8 reserved_at_80[0x8];
e281682b
SM		 2178 u8 destination_list_size[0x18];
2179
9dc0b289
AV		 2180 u8 reserved_at_a0[0x8];
2181 u8 flow_counter_list_size[0x18];
2182
7adbde20
HHZ		 2183 u8 encap_id[0x20];
2184
2185 u8 reserved_at_e0[0x120];
e281682b
SM		 2186
2187 struct mlx5_ifc_fte_match_param_bits match_value;
2188
b4ff3a36 2189 u8 reserved_at_1200[0x600];
e281682b 2190
9dc0b289 2191 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
e281682b
SM		 2192};
2193
2194enum {
2195 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
2196 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
2197};
2198
2199struct mlx5_ifc_xrc_srqc_bits {
2200 u8 state[0x4];
2201 u8 log_xrc_srq_size[0x4];
b4ff3a36 2202 u8 reserved_at_8[0x18];
e281682b
SM		 2203
2204 u8 wq_signature[0x1];
2205 u8 cont_srq[0x1];
b4ff3a36 2206 u8 reserved_at_22[0x1];
e281682b
SM		 2207 u8 rlky[0x1];
2208 u8 basic_cyclic_rcv_wqe[0x1];
2209 u8 log_rq_stride[0x3];
2210 u8 xrcd[0x18];
2211
2212 u8 page_offset[0x6];
b4ff3a36 2213 u8 reserved_at_46[0x2];
e281682b
SM		 2214 u8 cqn[0x18];
2215
b4ff3a36 2216 u8 reserved_at_60[0x20];
e281682b
SM		 2217
2218 u8 user_index_equal_xrc_srqn[0x1];
b4ff3a36 2219 u8 reserved_at_81[0x1];
e281682b
SM		 2220 u8 log_page_size[0x6];
2221 u8 user_index[0x18];
2222
b4ff3a36 2223 u8 reserved_at_a0[0x20];
e281682b 2224
b4ff3a36 2225 u8 reserved_at_c0[0x8];
e281682b
SM		 2226 u8 pd[0x18];
2227
2228 u8 lwm[0x10];
2229 u8 wqe_cnt[0x10];
2230
b4ff3a36 2231 u8 reserved_at_100[0x40];
e281682b
SM		 2232
2233 u8 db_record_addr_h[0x20];
2234
2235 u8 db_record_addr_l[0x1e];
b4ff3a36 2236 u8 reserved_at_17e[0x2];
e281682b 2237
b4ff3a36 2238 u8 reserved_at_180[0x80];
e281682b
SM		 2239};
2240
2241struct mlx5_ifc_traffic_counter_bits {
2242 u8 packets[0x40];
2243
2244 u8 octets[0x40];
2245};
2246
2247struct mlx5_ifc_tisc_bits {
84df61eb
AH		 2248 u8 strict_lag_tx_port_affinity[0x1];
2249 u8 reserved_at_1[0x3];
2250 u8 lag_tx_port_affinity[0x04];
2251
2252 u8 reserved_at_8[0x4];
e281682b 2253 u8 prio[0x4];
b4ff3a36 2254 u8 reserved_at_10[0x10];
e281682b 2255
b4ff3a36 2256 u8 reserved_at_20[0x100];
e281682b 2257
b4ff3a36 2258 u8 reserved_at_120[0x8];
e281682b
SM		 2259 u8 transport_domain[0x18];
2260
b4ff3a36 2261 u8 reserved_at_140[0x3c0];
e281682b
SM		 2262};
2263
2264enum {
2265 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2266 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2267};
2268
2269enum {
2270 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2271 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2272};
2273
2274enum {
2be6967c
SM		 2275 MLX5_RX_HASH_FN_NONE = 0x0,
2276 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
2277 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
e281682b
SM		 2278};
2279
2280enum {
2281 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1,
2282 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2,
2283};
2284
2285struct mlx5_ifc_tirc_bits {
b4ff3a36 2286 u8 reserved_at_0[0x20];
e281682b
SM		 2287
2288 u8 disp_type[0x4];
b4ff3a36 2289 u8 reserved_at_24[0x1c];
e281682b 2290
b4ff3a36 2291 u8 reserved_at_40[0x40];
e281682b 2292
b4ff3a36 2293 u8 reserved_at_80[0x4];
e281682b
SM		 2294 u8 lro_timeout_period_usecs[0x10];
2295 u8 lro_enable_mask[0x4];
2296 u8 lro_max_ip_payload_size[0x8];
2297
b4ff3a36 2298 u8 reserved_at_a0[0x40];
e281682b 2299
b4ff3a36 2300 u8 reserved_at_e0[0x8];
e281682b
SM		 2301 u8 inline_rqn[0x18];
2302
2303 u8 rx_hash_symmetric[0x1];
b4ff3a36 2304 u8 reserved_at_101[0x1];
e281682b 2305 u8 tunneled_offload_en[0x1];
b4ff3a36 2306 u8 reserved_at_103[0x5];
e281682b
SM		 2307 u8 indirect_table[0x18];
2308
2309 u8 rx_hash_fn[0x4];
b4ff3a36 2310 u8 reserved_at_124[0x2];
e281682b
SM		 2311 u8 self_lb_block[0x2];
2312 u8 transport_domain[0x18];
2313
2314 u8 rx_hash_toeplitz_key[10][0x20];
2315
2316 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2317
2318 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2319
b4ff3a36 2320 u8 reserved_at_2c0[0x4c0];
e281682b
SM		 2321};
2322
2323enum {
2324 MLX5_SRQC_STATE_GOOD = 0x0,
2325 MLX5_SRQC_STATE_ERROR = 0x1,
2326};
2327
2328struct mlx5_ifc_srqc_bits {
2329 u8 state[0x4];
2330 u8 log_srq_size[0x4];
b4ff3a36 2331 u8 reserved_at_8[0x18];
e281682b
SM		 2332
2333 u8 wq_signature[0x1];
2334 u8 cont_srq[0x1];
b4ff3a36 2335 u8 reserved_at_22[0x1];
e281682b 2336 u8 rlky[0x1];
b4ff3a36 2337 u8 reserved_at_24[0x1];
e281682b
SM		 2338 u8 log_rq_stride[0x3];
2339 u8 xrcd[0x18];
2340
2341 u8 page_offset[0x6];
b4ff3a36 2342 u8 reserved_at_46[0x2];
e281682b
SM		 2343 u8 cqn[0x18];
2344
b4ff3a36 2345 u8 reserved_at_60[0x20];
e281682b 2346
b4ff3a36 2347 u8 reserved_at_80[0x2];
e281682b 2348 u8 log_page_size[0x6];
b4ff3a36 2349 u8 reserved_at_88[0x18];
e281682b 2350
b4ff3a36 2351 u8 reserved_at_a0[0x20];
e281682b 2352
b4ff3a36 2353 u8 reserved_at_c0[0x8];
e281682b
SM		 2354 u8 pd[0x18];
2355
2356 u8 lwm[0x10];
2357 u8 wqe_cnt[0x10];
2358
b4ff3a36 2359 u8 reserved_at_100[0x40];
e281682b 2360
01949d01 2361 u8 dbr_addr[0x40];
e281682b 2362
b4ff3a36 2363 u8 reserved_at_180[0x80];
e281682b
SM		 2364};
2365
2366enum {
2367 MLX5_SQC_STATE_RST = 0x0,
2368 MLX5_SQC_STATE_RDY = 0x1,
2369 MLX5_SQC_STATE_ERR = 0x3,
2370};
2371
2372struct mlx5_ifc_sqc_bits {
2373 u8 rlky[0x1];
2374 u8 cd_master[0x1];
2375 u8 fre[0x1];
2376 u8 flush_in_error_en[0x1];
cff92d7c
HHZ		 2377 u8 reserved_at_4[0x1];
2378 u8 min_wqe_inline_mode[0x3];
e281682b 2379 u8 state[0x4];
7d5e1423
SM		 2380 u8 reg_umr[0x1];
2381 u8 reserved_at_d[0x13];
e281682b 2382
b4ff3a36 2383 u8 reserved_at_20[0x8];
e281682b
SM		 2384 u8 user_index[0x18];
2385
b4ff3a36 2386 u8 reserved_at_40[0x8];
e281682b
SM		 2387 u8 cqn[0x18];
2388
7486216b 2389 u8 reserved_at_60[0x90];
e281682b 2390
7486216b 2391 u8 packet_pacing_rate_limit_index[0x10];
e281682b 2392 u8 tis_lst_sz[0x10];
b4ff3a36 2393 u8 reserved_at_110[0x10];
e281682b 2394
b4ff3a36 2395 u8 reserved_at_120[0x40];
e281682b 2396
b4ff3a36 2397 u8 reserved_at_160[0x8];
e281682b
SM		 2398 u8 tis_num_0[0x18];
2399
2400 struct mlx5_ifc_wq_bits wq;
2401};
2402
813f8540
MHY		 2403enum {
2404 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2405 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2406 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2407 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2408};
2409
2410struct mlx5_ifc_scheduling_context_bits {
2411 u8 element_type[0x8];
2412 u8 reserved_at_8[0x18];
2413
2414 u8 element_attributes[0x20];
2415
2416 u8 parent_element_id[0x20];
2417
2418 u8 reserved_at_60[0x40];
2419
2420 u8 bw_share[0x20];
2421
2422 u8 max_average_bw[0x20];
2423
2424 u8 reserved_at_e0[0x120];
2425};
2426
e281682b 2427struct mlx5_ifc_rqtc_bits {
b4ff3a36 2428 u8 reserved_at_0[0xa0];
e281682b 2429
b4ff3a36 2430 u8 reserved_at_a0[0x10];
e281682b
SM		 2431 u8 rqt_max_size[0x10];
2432
b4ff3a36 2433 u8 reserved_at_c0[0x10];
e281682b
SM		 2434 u8 rqt_actual_size[0x10];
2435
b4ff3a36 2436 u8 reserved_at_e0[0x6a0];
e281682b
SM		 2437
2438 struct mlx5_ifc_rq_num_bits rq_num[0];
2439};
2440
2441enum {
2442 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2443 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2444};
2445
2446enum {
2447 MLX5_RQC_STATE_RST = 0x0,
2448 MLX5_RQC_STATE_RDY = 0x1,
2449 MLX5_RQC_STATE_ERR = 0x3,
2450};
2451
2452struct mlx5_ifc_rqc_bits {
2453 u8 rlky[0x1];
7d5e1423
SM		 2454 u8 reserved_at_1[0x1];
2455 u8 scatter_fcs[0x1];
e281682b
SM		 2456 u8 vsd[0x1];
2457 u8 mem_rq_type[0x4];
2458 u8 state[0x4];
b4ff3a36 2459 u8 reserved_at_c[0x1];
e281682b 2460 u8 flush_in_error_en[0x1];
b4ff3a36 2461 u8 reserved_at_e[0x12];
e281682b 2462
b4ff3a36 2463 u8 reserved_at_20[0x8];
e281682b
SM		 2464 u8 user_index[0x18];
2465
b4ff3a36 2466 u8 reserved_at_40[0x8];
e281682b
SM		 2467 u8 cqn[0x18];
2468
2469 u8 counter_set_id[0x8];
b4ff3a36 2470 u8 reserved_at_68[0x18];
e281682b 2471
b4ff3a36 2472 u8 reserved_at_80[0x8];
e281682b
SM		 2473 u8 rmpn[0x18];
2474
b4ff3a36 2475 u8 reserved_at_a0[0xe0];
e281682b
SM		 2476
2477 struct mlx5_ifc_wq_bits wq;
2478};
2479
2480enum {
2481 MLX5_RMPC_STATE_RDY = 0x1,
2482 MLX5_RMPC_STATE_ERR = 0x3,
2483};
2484
2485struct mlx5_ifc_rmpc_bits {
b4ff3a36 2486 u8 reserved_at_0[0x8];
e281682b 2487 u8 state[0x4];
b4ff3a36 2488 u8 reserved_at_c[0x14];
e281682b
SM		 2489
2490 u8 basic_cyclic_rcv_wqe[0x1];
b4ff3a36 2491 u8 reserved_at_21[0x1f];
e281682b 2492
b4ff3a36 2493 u8 reserved_at_40[0x140];
e281682b
SM		 2494
2495 struct mlx5_ifc_wq_bits wq;
2496};
2497
e281682b 2498struct mlx5_ifc_nic_vport_context_bits {
cff92d7c
HHZ		 2499 u8 reserved_at_0[0x5];
2500 u8 min_wqe_inline_mode[0x3];
2501 u8 reserved_at_8[0x17];
e281682b
SM		 2502 u8 roce_en[0x1];
2503
d82b7318 2504 u8 arm_change_event[0x1];
b4ff3a36 2505 u8 reserved_at_21[0x1a];
d82b7318
SM		 2506 u8 event_on_mtu[0x1];
2507 u8 event_on_promisc_change[0x1];
2508 u8 event_on_vlan_change[0x1];
2509 u8 event_on_mc_address_change[0x1];
2510 u8 event_on_uc_address_change[0x1];
e281682b 2511
b4ff3a36 2512 u8 reserved_at_40[0xf0];
d82b7318
SM		 2513
2514 u8 mtu[0x10];
2515
9efa7525
AS		 2516 u8 system_image_guid[0x40];
2517 u8 port_guid[0x40];
2518 u8 node_guid[0x40];
2519
b4ff3a36 2520 u8 reserved_at_200[0x140];
9efa7525 2521 u8 qkey_violation_counter[0x10];
b4ff3a36 2522 u8 reserved_at_350[0x430];
d82b7318
SM		 2523
2524 u8 promisc_uc[0x1];
2525 u8 promisc_mc[0x1];
2526 u8 promisc_all[0x1];
b4ff3a36 2527 u8 reserved_at_783[0x2];
e281682b 2528 u8 allowed_list_type[0x3];
b4ff3a36 2529 u8 reserved_at_788[0xc];
e281682b
SM		 2530 u8 allowed_list_size[0xc];
2531
2532 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2533
b4ff3a36 2534 u8 reserved_at_7e0[0x20];
e281682b
SM		 2535
2536 u8 current_uc_mac_address[0][0x40];
2537};
2538
2539enum {
2540 MLX5_MKC_ACCESS_MODE_PA = 0x0,
2541 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
2542 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
bcda1aca 2543 MLX5_MKC_ACCESS_MODE_KSM = 0x3,
e281682b
SM		 2544};
2545
2546struct mlx5_ifc_mkc_bits {
b4ff3a36 2547 u8 reserved_at_0[0x1];
e281682b 2548 u8 free[0x1];
b4ff3a36 2549 u8 reserved_at_2[0xd];
e281682b
SM		 2550 u8 small_fence_on_rdma_read_response[0x1];
2551 u8 umr_en[0x1];
2552 u8 a[0x1];
2553 u8 rw[0x1];
2554 u8 rr[0x1];
2555 u8 lw[0x1];
2556 u8 lr[0x1];
2557 u8 access_mode[0x2];
b4ff3a36 2558 u8 reserved_at_18[0x8];
e281682b
SM		 2559
2560 u8 qpn[0x18];
2561 u8 mkey_7_0[0x8];
2562
b4ff3a36 2563 u8 reserved_at_40[0x20];
e281682b
SM		 2564
2565 u8 length64[0x1];
2566 u8 bsf_en[0x1];
2567 u8 sync_umr[0x1];
b4ff3a36 2568 u8 reserved_at_63[0x2];
e281682b 2569 u8 expected_sigerr_count[0x1];
b4ff3a36 2570 u8 reserved_at_66[0x1];
e281682b
SM		 2571 u8 en_rinval[0x1];
2572 u8 pd[0x18];
2573
2574 u8 start_addr[0x40];
2575
2576 u8 len[0x40];
2577
2578 u8 bsf_octword_size[0x20];
2579
b4ff3a36 2580 u8 reserved_at_120[0x80];
e281682b
SM		 2581
2582 u8 translations_octword_size[0x20];
2583
b4ff3a36 2584 u8 reserved_at_1c0[0x1b];
e281682b
SM		 2585 u8 log_page_size[0x5];
2586
b4ff3a36 2587 u8 reserved_at_1e0[0x20];
e281682b
SM		 2588};
2589
2590struct mlx5_ifc_pkey_bits {
b4ff3a36 2591 u8 reserved_at_0[0x10];
e281682b
SM		 2592 u8 pkey[0x10];
2593};
2594
2595struct mlx5_ifc_array128_auto_bits {
2596 u8 array128_auto[16][0x8];
2597};
2598
2599struct mlx5_ifc_hca_vport_context_bits {
2600 u8 field_select[0x20];
2601
b4ff3a36 2602 u8 reserved_at_20[0xe0];
e281682b
SM		 2603
2604 u8 sm_virt_aware[0x1];
2605 u8 has_smi[0x1];
2606 u8 has_raw[0x1];
2607 u8 grh_required[0x1];
b4ff3a36 2608 u8 reserved_at_104[0xc];
707c4602
MD		 2609 u8 port_physical_state[0x4];
2610 u8 vport_state_policy[0x4];
2611 u8 port_state[0x4];
e281682b
SM		 2612 u8 vport_state[0x4];
2613
b4ff3a36 2614 u8 reserved_at_120[0x20];
707c4602
MD		 2615
2616 u8 system_image_guid[0x40];
e281682b
SM		 2617
2618 u8 port_guid[0x40];
2619
2620 u8 node_guid[0x40];
2621
2622 u8 cap_mask1[0x20];
2623
2624 u8 cap_mask1_field_select[0x20];
2625
2626 u8 cap_mask2[0x20];
2627
2628 u8 cap_mask2_field_select[0x20];
2629
b4ff3a36 2630 u8 reserved_at_280[0x80];
e281682b
SM		 2631
2632 u8 lid[0x10];
b4ff3a36 2633 u8 reserved_at_310[0x4];
e281682b
SM		 2634 u8 init_type_reply[0x4];
2635 u8 lmc[0x3];
2636 u8 subnet_timeout[0x5];
2637
2638 u8 sm_lid[0x10];
2639 u8 sm_sl[0x4];
b4ff3a36 2640 u8 reserved_at_334[0xc];
e281682b
SM		 2641
2642 u8 qkey_violation_counter[0x10];
2643 u8 pkey_violation_counter[0x10];
2644
b4ff3a36 2645 u8 reserved_at_360[0xca0];
e281682b
SM		 2646};
2647
d6666753 2648struct mlx5_ifc_esw_vport_context_bits {
b4ff3a36 2649 u8 reserved_at_0[0x3];
d6666753
SM		 2650 u8 vport_svlan_strip[0x1];
2651 u8 vport_cvlan_strip[0x1];
2652 u8 vport_svlan_insert[0x1];
2653 u8 vport_cvlan_insert[0x2];
b4ff3a36 2654 u8 reserved_at_8[0x18];
d6666753 2655
b4ff3a36 2656 u8 reserved_at_20[0x20];
d6666753
SM		 2657
2658 u8 svlan_cfi[0x1];
2659 u8 svlan_pcp[0x3];
2660 u8 svlan_id[0xc];
2661 u8 cvlan_cfi[0x1];
2662 u8 cvlan_pcp[0x3];
2663 u8 cvlan_id[0xc];
2664
b4ff3a36 2665 u8 reserved_at_60[0x7a0];
d6666753
SM		 2666};
2667
e281682b
SM		 2668enum {
2669 MLX5_EQC_STATUS_OK = 0x0,
2670 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
2671};
2672
2673enum {
2674 MLX5_EQC_ST_ARMED = 0x9,
2675 MLX5_EQC_ST_FIRED = 0xa,
2676};
2677
2678struct mlx5_ifc_eqc_bits {
2679 u8 status[0x4];
b4ff3a36 2680 u8 reserved_at_4[0x9];
e281682b
SM		 2681 u8 ec[0x1];
2682 u8 oi[0x1];
b4ff3a36 2683 u8 reserved_at_f[0x5];
e281682b 2684 u8 st[0x4];
b4ff3a36 2685 u8 reserved_at_18[0x8];
e281682b 2686
b4ff3a36 2687 u8 reserved_at_20[0x20];
e281682b 2688
b4ff3a36 2689 u8 reserved_at_40[0x14];
e281682b 2690 u8 page_offset[0x6];
b4ff3a36 2691 u8 reserved_at_5a[0x6];
e281682b 2692
b4ff3a36 2693 u8 reserved_at_60[0x3];
e281682b
SM		 2694 u8 log_eq_size[0x5];
2695 u8 uar_page[0x18];
2696
b4ff3a36 2697 u8 reserved_at_80[0x20];
e281682b 2698
b4ff3a36 2699 u8 reserved_at_a0[0x18];
e281682b
SM		 2700 u8 intr[0x8];
2701
b4ff3a36 2702 u8 reserved_at_c0[0x3];
e281682b 2703 u8 log_page_size[0x5];
b4ff3a36 2704 u8 reserved_at_c8[0x18];
e281682b 2705
b4ff3a36 2706 u8 reserved_at_e0[0x60];
e281682b 2707
b4ff3a36 2708 u8 reserved_at_140[0x8];
e281682b
SM		 2709 u8 consumer_counter[0x18];
2710
b4ff3a36 2711 u8 reserved_at_160[0x8];
e281682b
SM		 2712 u8 producer_counter[0x18];
2713
b4ff3a36 2714 u8 reserved_at_180[0x80];
e281682b
SM		 2715};
2716
2717enum {
2718 MLX5_DCTC_STATE_ACTIVE = 0x0,
2719 MLX5_DCTC_STATE_DRAINING = 0x1,
2720 MLX5_DCTC_STATE_DRAINED = 0x2,
2721};
2722
2723enum {
2724 MLX5_DCTC_CS_RES_DISABLE = 0x0,
2725 MLX5_DCTC_CS_RES_NA = 0x1,
2726 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
2727};
2728
2729enum {
2730 MLX5_DCTC_MTU_256_BYTES = 0x1,
2731 MLX5_DCTC_MTU_512_BYTES = 0x2,
2732 MLX5_DCTC_MTU_1K_BYTES = 0x3,
2733 MLX5_DCTC_MTU_2K_BYTES = 0x4,
2734 MLX5_DCTC_MTU_4K_BYTES = 0x5,
2735};
2736
2737struct mlx5_ifc_dctc_bits {
b4ff3a36 2738 u8 reserved_at_0[0x4];
e281682b 2739 u8 state[0x4];
b4ff3a36 2740 u8 reserved_at_8[0x18];
e281682b 2741
b4ff3a36 2742 u8 reserved_at_20[0x8];
e281682b
SM		 2743 u8 user_index[0x18];
2744
b4ff3a36 2745 u8 reserved_at_40[0x8];
e281682b
SM		 2746 u8 cqn[0x18];
2747
2748 u8 counter_set_id[0x8];
2749 u8 atomic_mode[0x4];
2750 u8 rre[0x1];
2751 u8 rwe[0x1];
2752 u8 rae[0x1];
2753 u8 atomic_like_write_en[0x1];
2754 u8 latency_sensitive[0x1];
2755 u8 rlky[0x1];
2756 u8 free_ar[0x1];
b4ff3a36 2757 u8 reserved_at_73[0xd];
e281682b 2758
b4ff3a36 2759 u8 reserved_at_80[0x8];
e281682b 2760 u8 cs_res[0x8];
b4ff3a36 2761 u8 reserved_at_90[0x3];
e281682b 2762 u8 min_rnr_nak[0x5];
b4ff3a36 2763 u8 reserved_at_98[0x8];
e281682b 2764
b4ff3a36 2765 u8 reserved_at_a0[0x8];
7486216b 2766 u8 srqn_xrqn[0x18];
e281682b 2767
b4ff3a36 2768 u8 reserved_at_c0[0x8];
e281682b
SM		 2769 u8 pd[0x18];
2770
2771 u8 tclass[0x8];
b4ff3a36 2772 u8 reserved_at_e8[0x4];
e281682b
SM		 2773 u8 flow_label[0x14];
2774
2775 u8 dc_access_key[0x40];
2776
b4ff3a36 2777 u8 reserved_at_140[0x5];
e281682b
SM		 2778 u8 mtu[0x3];
2779 u8 port[0x8];
2780 u8 pkey_index[0x10];
2781
b4ff3a36 2782 u8 reserved_at_160[0x8];
e281682b 2783 u8 my_addr_index[0x8];
b4ff3a36 2784 u8 reserved_at_170[0x8];
e281682b
SM		 2785 u8 hop_limit[0x8];
2786
2787 u8 dc_access_key_violation_count[0x20];
2788
b4ff3a36 2789 u8 reserved_at_1a0[0x14];
e281682b
SM		 2790 u8 dei_cfi[0x1];
2791 u8 eth_prio[0x3];
2792 u8 ecn[0x2];
2793 u8 dscp[0x6];
2794
b4ff3a36 2795 u8 reserved_at_1c0[0x40];
e281682b
SM		 2796};
2797
2798enum {
2799 MLX5_CQC_STATUS_OK = 0x0,
2800 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
2801 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
2802};
2803
2804enum {
2805 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
2806 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
2807};
2808
2809enum {
2810 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
2811 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
2812 MLX5_CQC_ST_FIRED = 0xa,
2813};
2814
7d5e1423
SM		 2815enum {
2816 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
2817 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
7486216b 2818 MLX5_CQ_PERIOD_NUM_MODES
7d5e1423
SM		 2819};
2820
e281682b
SM		 2821struct mlx5_ifc_cqc_bits {
2822 u8 status[0x4];
b4ff3a36 2823 u8 reserved_at_4[0x4];
e281682b
SM		 2824 u8 cqe_sz[0x3];
2825 u8 cc[0x1];
b4ff3a36 2826 u8 reserved_at_c[0x1];
e281682b
SM		 2827 u8 scqe_break_moderation_en[0x1];
2828 u8 oi[0x1];
7d5e1423
SM		 2829 u8 cq_period_mode[0x2];
2830 u8 cqe_comp_en[0x1];
e281682b
SM		 2831 u8 mini_cqe_res_format[0x2];
2832 u8 st[0x4];
b4ff3a36 2833 u8 reserved_at_18[0x8];
e281682b 2834
b4ff3a36 2835 u8 reserved_at_20[0x20];
e281682b 2836
b4ff3a36 2837 u8 reserved_at_40[0x14];
e281682b 2838 u8 page_offset[0x6];
b4ff3a36 2839 u8 reserved_at_5a[0x6];
e281682b 2840
b4ff3a36 2841 u8 reserved_at_60[0x3];
e281682b
SM		 2842 u8 log_cq_size[0x5];
2843 u8 uar_page[0x18];
2844
b4ff3a36 2845 u8 reserved_at_80[0x4];
e281682b
SM		 2846 u8 cq_period[0xc];
2847 u8 cq_max_count[0x10];
2848
b4ff3a36 2849 u8 reserved_at_a0[0x18];
e281682b
SM		 2850 u8 c_eqn[0x8];
2851
b4ff3a36 2852 u8 reserved_at_c0[0x3];
e281682b 2853 u8 log_page_size[0x5];
b4ff3a36 2854 u8 reserved_at_c8[0x18];
e281682b 2855
b4ff3a36 2856 u8 reserved_at_e0[0x20];
e281682b 2857
b4ff3a36 2858 u8 reserved_at_100[0x8];
e281682b
SM		 2859 u8 last_notified_index[0x18];
2860
b4ff3a36 2861 u8 reserved_at_120[0x8];
e281682b
SM		 2862 u8 last_solicit_index[0x18];
2863
b4ff3a36 2864 u8 reserved_at_140[0x8];
e281682b
SM		 2865 u8 consumer_counter[0x18];
2866
b4ff3a36 2867 u8 reserved_at_160[0x8];
e281682b
SM		 2868 u8 producer_counter[0x18];
2869
b4ff3a36 2870 u8 reserved_at_180[0x40];
e281682b
SM		 2871
2872 u8 dbr_addr[0x40];
2873};
2874
2875union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2876 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2877 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2878 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
b4ff3a36 2879 u8 reserved_at_0[0x800];
e281682b
SM		 2880};
2881
2882struct mlx5_ifc_query_adapter_param_block_bits {
b4ff3a36 2883 u8 reserved_at_0[0xc0];
e281682b 2884
b4ff3a36 2885 u8 reserved_at_c0[0x8];
211e6c80
MD		 2886 u8 ieee_vendor_id[0x18];
2887
b4ff3a36 2888 u8 reserved_at_e0[0x10];
e281682b
SM		 2889 u8 vsd_vendor_id[0x10];
2890
2891 u8 vsd[208][0x8];
2892
2893 u8 vsd_contd_psid[16][0x8];
2894};
2895
7486216b
SM		 2896enum {
2897 MLX5_XRQC_STATE_GOOD = 0x0,
2898 MLX5_XRQC_STATE_ERROR = 0x1,
2899};
2900
2901enum {
2902 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
2903 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
2904};
2905
2906enum {
2907 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
2908};
2909
2910struct mlx5_ifc_tag_matching_topology_context_bits {
2911 u8 log_matching_list_sz[0x4];
2912 u8 reserved_at_4[0xc];
2913 u8 append_next_index[0x10];
2914
2915 u8 sw_phase_cnt[0x10];
2916 u8 hw_phase_cnt[0x10];
2917
2918 u8 reserved_at_40[0x40];
2919};
2920
2921struct mlx5_ifc_xrqc_bits {
2922 u8 state[0x4];
2923 u8 rlkey[0x1];
2924 u8 reserved_at_5[0xf];
2925 u8 topology[0x4];
2926 u8 reserved_at_18[0x4];
2927 u8 offload[0x4];
2928
2929 u8 reserved_at_20[0x8];
2930 u8 user_index[0x18];
2931
2932 u8 reserved_at_40[0x8];
2933 u8 cqn[0x18];
2934
2935 u8 reserved_at_60[0xa0];
2936
2937 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
2938
5579e151 2939 u8 reserved_at_180[0x880];
7486216b
SM		 2940
2941 struct mlx5_ifc_wq_bits wq;
2942};
2943
e281682b
SM		 2944union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2945 struct mlx5_ifc_modify_field_select_bits modify_field_select;
2946 struct mlx5_ifc_resize_field_select_bits resize_field_select;
b4ff3a36 2947 u8 reserved_at_0[0x20];
e281682b
SM		 2948};
2949
2950union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2951 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2952 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2953 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
b4ff3a36 2954 u8 reserved_at_0[0x20];
e281682b
SM		 2955};
2956
2957union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
2958 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
2959 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
2960 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
2961 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
2962 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
2963 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
2964 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
1c64bf6f 2965 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b 2966 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
d8dc0508 2967 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
b4ff3a36 2968 u8 reserved_at_0[0x7c0];
e281682b
SM		 2969};
2970
2971union mlx5_ifc_event_auto_bits {
2972 struct mlx5_ifc_comp_event_bits comp_event;
2973 struct mlx5_ifc_dct_events_bits dct_events;
2974 struct mlx5_ifc_qp_events_bits qp_events;
2975 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
2976 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
2977 struct mlx5_ifc_cq_error_bits cq_error;
2978 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
2979 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
2980 struct mlx5_ifc_gpio_event_bits gpio_event;
2981 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
2982 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
2983 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
b4ff3a36 2984 u8 reserved_at_0[0xe0];
e281682b
SM		 2985};
2986
2987struct mlx5_ifc_health_buffer_bits {
b4ff3a36 2988 u8 reserved_at_0[0x100];
e281682b
SM		 2989
2990 u8 assert_existptr[0x20];
2991
2992 u8 assert_callra[0x20];
2993
b4ff3a36 2994 u8 reserved_at_140[0x40];
e281682b
SM		 2995
2996 u8 fw_version[0x20];
2997
2998 u8 hw_id[0x20];
2999
b4ff3a36 3000 u8 reserved_at_1c0[0x20];
e281682b
SM		 3001
3002 u8 irisc_index[0x8];
3003 u8 synd[0x8];
3004 u8 ext_synd[0x10];
3005};
3006
3007struct mlx5_ifc_register_loopback_control_bits {
3008 u8 no_lb[0x1];
b4ff3a36 3009 u8 reserved_at_1[0x7];
e281682b 3010 u8 port[0x8];
b4ff3a36 3011 u8 reserved_at_10[0x10];
e281682b 3012
b4ff3a36 3013 u8 reserved_at_20[0x60];
e281682b
SM		 3014};
3015
813f8540
MHY		 3016struct mlx5_ifc_vport_tc_element_bits {
3017 u8 traffic_class[0x4];
3018 u8 reserved_at_4[0xc];
3019 u8 vport_number[0x10];
3020};
3021
3022struct mlx5_ifc_vport_element_bits {
3023 u8 reserved_at_0[0x10];
3024 u8 vport_number[0x10];
3025};
3026
3027enum {
3028 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3029 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3030 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3031};
3032
3033struct mlx5_ifc_tsar_element_bits {
3034 u8 reserved_at_0[0x8];
3035 u8 tsar_type[0x8];
3036 u8 reserved_at_10[0x10];
3037};
3038
e281682b
SM		 3039struct mlx5_ifc_teardown_hca_out_bits {
3040 u8 status[0x8];
b4ff3a36 3041 u8 reserved_at_8[0x18];
e281682b
SM		 3042
3043 u8 syndrome[0x20];
3044
b4ff3a36 3045 u8 reserved_at_40[0x40];
e281682b
SM		 3046};
3047
3048enum {
3049 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
3050 MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE = 0x1,
3051};
3052
3053struct mlx5_ifc_teardown_hca_in_bits {
3054 u8 opcode[0x10];
b4ff3a36 3055 u8 reserved_at_10[0x10];
e281682b 3056
b4ff3a36 3057 u8 reserved_at_20[0x10];
e281682b
SM		 3058 u8 op_mod[0x10];
3059
b4ff3a36 3060 u8 reserved_at_40[0x10];
e281682b
SM		 3061 u8 profile[0x10];
3062
b4ff3a36 3063 u8 reserved_at_60[0x20];
e281682b
SM		 3064};
3065
3066struct mlx5_ifc_sqerr2rts_qp_out_bits {
3067 u8 status[0x8];
b4ff3a36 3068 u8 reserved_at_8[0x18];
e281682b
SM		 3069
3070 u8 syndrome[0x20];
3071
b4ff3a36 3072 u8 reserved_at_40[0x40];
e281682b
SM		 3073};
3074
3075struct mlx5_ifc_sqerr2rts_qp_in_bits {
3076 u8 opcode[0x10];
b4ff3a36 3077 u8 reserved_at_10[0x10];
e281682b 3078
b4ff3a36 3079 u8 reserved_at_20[0x10];
e281682b
SM		 3080 u8 op_mod[0x10];
3081
b4ff3a36 3082 u8 reserved_at_40[0x8];
e281682b
SM		 3083 u8 qpn[0x18];
3084
b4ff3a36 3085 u8 reserved_at_60[0x20];
e281682b
SM		 3086
3087 u8 opt_param_mask[0x20];
3088
b4ff3a36 3089 u8 reserved_at_a0[0x20];
e281682b
SM		 3090
3091 struct mlx5_ifc_qpc_bits qpc;
3092
b4ff3a36 3093 u8 reserved_at_800[0x80];
e281682b
SM		 3094};
3095
3096struct mlx5_ifc_sqd2rts_qp_out_bits {
3097 u8 status[0x8];
b4ff3a36 3098 u8 reserved_at_8[0x18];
e281682b
SM		 3099
3100 u8 syndrome[0x20];
3101
b4ff3a36 3102 u8 reserved_at_40[0x40];
e281682b
SM		 3103};
3104
3105struct mlx5_ifc_sqd2rts_qp_in_bits {
3106 u8 opcode[0x10];
b4ff3a36 3107 u8 reserved_at_10[0x10];
e281682b 3108
b4ff3a36 3109 u8 reserved_at_20[0x10];
e281682b
SM		 3110 u8 op_mod[0x10];
3111
b4ff3a36 3112 u8 reserved_at_40[0x8];
e281682b
SM		 3113 u8 qpn[0x18];
3114
b4ff3a36 3115 u8 reserved_at_60[0x20];
e281682b
SM		 3116
3117 u8 opt_param_mask[0x20];
3118
b4ff3a36 3119 u8 reserved_at_a0[0x20];
e281682b
SM		 3120
3121 struct mlx5_ifc_qpc_bits qpc;
3122
b4ff3a36 3123 u8 reserved_at_800[0x80];
e281682b
SM		 3124};
3125
3126struct mlx5_ifc_set_roce_address_out_bits {
3127 u8 status[0x8];
b4ff3a36 3128 u8 reserved_at_8[0x18];
e281682b
SM		 3129
3130 u8 syndrome[0x20];
3131
b4ff3a36 3132 u8 reserved_at_40[0x40];
e281682b
SM		 3133};
3134
3135struct mlx5_ifc_set_roce_address_in_bits {
3136 u8 opcode[0x10];
b4ff3a36 3137 u8 reserved_at_10[0x10];
e281682b 3138
b4ff3a36 3139 u8 reserved_at_20[0x10];
e281682b
SM		 3140 u8 op_mod[0x10];
3141
3142 u8 roce_address_index[0x10];
b4ff3a36 3143 u8 reserved_at_50[0x10];
e281682b 3144
b4ff3a36 3145 u8 reserved_at_60[0x20];
e281682b
SM		 3146
3147 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3148};
3149
3150struct mlx5_ifc_set_mad_demux_out_bits {
3151 u8 status[0x8];
b4ff3a36 3152 u8 reserved_at_8[0x18];
e281682b
SM		 3153
3154 u8 syndrome[0x20];
3155
b4ff3a36 3156 u8 reserved_at_40[0x40];
e281682b
SM		 3157};
3158
3159enum {
3160 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
3161 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
3162};
3163
3164struct mlx5_ifc_set_mad_demux_in_bits {
3165 u8 opcode[0x10];
b4ff3a36 3166 u8 reserved_at_10[0x10];
e281682b 3167
b4ff3a36 3168 u8 reserved_at_20[0x10];
e281682b
SM		 3169 u8 op_mod[0x10];
3170
b4ff3a36 3171 u8 reserved_at_40[0x20];
e281682b 3172
b4ff3a36 3173 u8 reserved_at_60[0x6];
e281682b 3174 u8 demux_mode[0x2];
b4ff3a36 3175 u8 reserved_at_68[0x18];
e281682b
SM		 3176};
3177
3178struct mlx5_ifc_set_l2_table_entry_out_bits {
3179 u8 status[0x8];
b4ff3a36 3180 u8 reserved_at_8[0x18];
e281682b
SM		 3181
3182 u8 syndrome[0x20];
3183
b4ff3a36 3184 u8 reserved_at_40[0x40];
e281682b
SM		 3185};
3186
3187struct mlx5_ifc_set_l2_table_entry_in_bits {
3188 u8 opcode[0x10];
b4ff3a36 3189 u8 reserved_at_10[0x10];
e281682b 3190
b4ff3a36 3191 u8 reserved_at_20[0x10];
e281682b
SM		 3192 u8 op_mod[0x10];
3193
b4ff3a36 3194 u8 reserved_at_40[0x60];
e281682b 3195
b4ff3a36 3196 u8 reserved_at_a0[0x8];
e281682b
SM		 3197 u8 table_index[0x18];
3198
b4ff3a36 3199 u8 reserved_at_c0[0x20];
e281682b 3200
b4ff3a36 3201 u8 reserved_at_e0[0x13];
e281682b
SM		 3202 u8 vlan_valid[0x1];
3203 u8 vlan[0xc];
3204
3205 struct mlx5_ifc_mac_address_layout_bits mac_address;
3206
b4ff3a36 3207 u8 reserved_at_140[0xc0];
e281682b
SM		 3208};
3209
3210struct mlx5_ifc_set_issi_out_bits {
3211 u8 status[0x8];
b4ff3a36 3212 u8 reserved_at_8[0x18];
e281682b
SM		 3213
3214 u8 syndrome[0x20];
3215
b4ff3a36 3216 u8 reserved_at_40[0x40];
e281682b
SM		 3217};
3218
3219struct mlx5_ifc_set_issi_in_bits {
3220 u8 opcode[0x10];
b4ff3a36 3221 u8 reserved_at_10[0x10];
e281682b 3222
b4ff3a36 3223 u8 reserved_at_20[0x10];
e281682b
SM		 3224 u8 op_mod[0x10];
3225
b4ff3a36 3226 u8 reserved_at_40[0x10];
e281682b
SM		 3227 u8 current_issi[0x10];
3228
b4ff3a36 3229 u8 reserved_at_60[0x20];
e281682b
SM		 3230};
3231
3232struct mlx5_ifc_set_hca_cap_out_bits {
3233 u8 status[0x8];
b4ff3a36 3234 u8 reserved_at_8[0x18];
e281682b
SM		 3235
3236 u8 syndrome[0x20];
3237
b4ff3a36 3238 u8 reserved_at_40[0x40];
e281682b
SM		 3239};
3240
3241struct mlx5_ifc_set_hca_cap_in_bits {
3242 u8 opcode[0x10];
b4ff3a36 3243 u8 reserved_at_10[0x10];
e281682b 3244
b4ff3a36 3245 u8 reserved_at_20[0x10];
e281682b
SM		 3246 u8 op_mod[0x10];
3247
b4ff3a36 3248 u8 reserved_at_40[0x40];
e281682b
SM		 3249
3250 union mlx5_ifc_hca_cap_union_bits capability;
3251};
3252
26a81453
MG		 3253enum {
3254 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
3255 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
3256 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
3257 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
3258};
3259
e281682b
SM		 3260struct mlx5_ifc_set_fte_out_bits {
3261 u8 status[0x8];
b4ff3a36 3262 u8 reserved_at_8[0x18];
e281682b
SM		 3263
3264 u8 syndrome[0x20];
3265
b4ff3a36 3266 u8 reserved_at_40[0x40];
e281682b
SM		 3267};
3268
3269struct mlx5_ifc_set_fte_in_bits {
3270 u8 opcode[0x10];
b4ff3a36 3271 u8 reserved_at_10[0x10];
e281682b 3272
b4ff3a36 3273 u8 reserved_at_20[0x10];
e281682b
SM		 3274 u8 op_mod[0x10];
3275
7d5e1423
SM		 3276 u8 other_vport[0x1];
3277 u8 reserved_at_41[0xf];
3278 u8 vport_number[0x10];
3279
3280 u8 reserved_at_60[0x20];
e281682b
SM		 3281
3282 u8 table_type[0x8];
b4ff3a36 3283 u8 reserved_at_88[0x18];
e281682b 3284
b4ff3a36 3285 u8 reserved_at_a0[0x8];
e281682b
SM		 3286 u8 table_id[0x18];
3287
b4ff3a36 3288 u8 reserved_at_c0[0x18];
26a81453
MG		 3289 u8 modify_enable_mask[0x8];
3290
b4ff3a36 3291 u8 reserved_at_e0[0x20];
e281682b
SM		 3292
3293 u8 flow_index[0x20];
3294
b4ff3a36 3295 u8 reserved_at_120[0xe0];
e281682b
SM		 3296
3297 struct mlx5_ifc_flow_context_bits flow_context;
3298};
3299
3300struct mlx5_ifc_rts2rts_qp_out_bits {
3301 u8 status[0x8];
b4ff3a36 3302 u8 reserved_at_8[0x18];
e281682b
SM		 3303
3304 u8 syndrome[0x20];
3305
b4ff3a36 3306 u8 reserved_at_40[0x40];
e281682b
SM		 3307};
3308
3309struct mlx5_ifc_rts2rts_qp_in_bits {
3310 u8 opcode[0x10];
b4ff3a36 3311 u8 reserved_at_10[0x10];
e281682b 3312
b4ff3a36 3313 u8 reserved_at_20[0x10];
e281682b
SM		 3314 u8 op_mod[0x10];
3315
b4ff3a36 3316 u8 reserved_at_40[0x8];
e281682b
SM		 3317 u8 qpn[0x18];
3318
b4ff3a36 3319 u8 reserved_at_60[0x20];
e281682b
SM		 3320
3321 u8 opt_param_mask[0x20];
3322
b4ff3a36 3323 u8 reserved_at_a0[0x20];
e281682b
SM		 3324
3325 struct mlx5_ifc_qpc_bits qpc;
3326
b4ff3a36 3327 u8 reserved_at_800[0x80];
e281682b
SM		 3328};
3329
3330struct mlx5_ifc_rtr2rts_qp_out_bits {
3331 u8 status[0x8];
b4ff3a36 3332 u8 reserved_at_8[0x18];
e281682b
SM		 3333
3334 u8 syndrome[0x20];
3335
b4ff3a36 3336 u8 reserved_at_40[0x40];
e281682b
SM		 3337};
3338
3339struct mlx5_ifc_rtr2rts_qp_in_bits {
3340 u8 opcode[0x10];
b4ff3a36 3341 u8 reserved_at_10[0x10];
e281682b 3342
b4ff3a36 3343 u8 reserved_at_20[0x10];
e281682b
SM		 3344 u8 op_mod[0x10];
3345
b4ff3a36 3346 u8 reserved_at_40[0x8];
e281682b
SM		 3347 u8 qpn[0x18];
3348
b4ff3a36 3349 u8 reserved_at_60[0x20];
e281682b
SM		 3350
3351 u8 opt_param_mask[0x20];
3352
b4ff3a36 3353 u8 reserved_at_a0[0x20];
e281682b
SM		 3354
3355 struct mlx5_ifc_qpc_bits qpc;
3356
b4ff3a36 3357 u8 reserved_at_800[0x80];
e281682b
SM		 3358};
3359
3360struct mlx5_ifc_rst2init_qp_out_bits {
3361 u8 status[0x8];
b4ff3a36 3362 u8 reserved_at_8[0x18];
e281682b
SM		 3363
3364 u8 syndrome[0x20];
3365
b4ff3a36 3366 u8 reserved_at_40[0x40];
e281682b
SM		 3367};
3368
3369struct mlx5_ifc_rst2init_qp_in_bits {
3370 u8 opcode[0x10];
b4ff3a36 3371 u8 reserved_at_10[0x10];
e281682b 3372
b4ff3a36 3373 u8 reserved_at_20[0x10];
e281682b
SM		 3374 u8 op_mod[0x10];
3375
b4ff3a36 3376 u8 reserved_at_40[0x8];
e281682b
SM		 3377 u8 qpn[0x18];
3378
b4ff3a36 3379 u8 reserved_at_60[0x20];
e281682b
SM		 3380
3381 u8 opt_param_mask[0x20];
3382
b4ff3a36 3383 u8 reserved_at_a0[0x20];
e281682b
SM		 3384
3385 struct mlx5_ifc_qpc_bits qpc;
3386
b4ff3a36 3387 u8 reserved_at_800[0x80];
e281682b
SM		 3388};
3389
7486216b
SM		 3390struct mlx5_ifc_query_xrq_out_bits {
3391 u8 status[0x8];
3392 u8 reserved_at_8[0x18];
3393
3394 u8 syndrome[0x20];
3395
3396 u8 reserved_at_40[0x40];
3397
3398 struct mlx5_ifc_xrqc_bits xrq_context;
3399};
3400
3401struct mlx5_ifc_query_xrq_in_bits {
3402 u8 opcode[0x10];
3403 u8 reserved_at_10[0x10];
3404
3405 u8 reserved_at_20[0x10];
3406 u8 op_mod[0x10];
3407
3408 u8 reserved_at_40[0x8];
3409 u8 xrqn[0x18];
3410
3411 u8 reserved_at_60[0x20];
3412};
3413
e281682b
SM		 3414struct mlx5_ifc_query_xrc_srq_out_bits {
3415 u8 status[0x8];
b4ff3a36 3416 u8 reserved_at_8[0x18];
e281682b
SM		 3417
3418 u8 syndrome[0x20];
3419
b4ff3a36 3420 u8 reserved_at_40[0x40];
e281682b
SM		 3421
3422 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3423
b4ff3a36 3424 u8 reserved_at_280[0x600];
e281682b
SM		 3425
3426 u8 pas[0][0x40];
3427};
3428
3429struct mlx5_ifc_query_xrc_srq_in_bits {
3430 u8 opcode[0x10];
b4ff3a36 3431 u8 reserved_at_10[0x10];
e281682b 3432
b4ff3a36 3433 u8 reserved_at_20[0x10];
e281682b
SM		 3434 u8 op_mod[0x10];
3435
b4ff3a36 3436 u8 reserved_at_40[0x8];
e281682b
SM		 3437 u8 xrc_srqn[0x18];
3438
b4ff3a36 3439 u8 reserved_at_60[0x20];
e281682b
SM		 3440};
3441
3442enum {
3443 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
3444 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
3445};
3446
3447struct mlx5_ifc_query_vport_state_out_bits {
3448 u8 status[0x8];
b4ff3a36 3449 u8 reserved_at_8[0x18];
e281682b
SM		 3450
3451 u8 syndrome[0x20];
3452
b4ff3a36 3453 u8 reserved_at_40[0x20];
e281682b 3454
b4ff3a36 3455 u8 reserved_at_60[0x18];
e281682b
SM		 3456 u8 admin_state[0x4];
3457 u8 state[0x4];
3458};
3459
3460enum {
3461 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0,
e7546514 3462 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1,
e281682b
SM		 3463};
3464
3465struct mlx5_ifc_query_vport_state_in_bits {
3466 u8 opcode[0x10];
b4ff3a36 3467 u8 reserved_at_10[0x10];
e281682b 3468
b4ff3a36 3469 u8 reserved_at_20[0x10];
e281682b
SM		 3470 u8 op_mod[0x10];
3471
3472 u8 other_vport[0x1];
b4ff3a36 3473 u8 reserved_at_41[0xf];
e281682b
SM		 3474 u8 vport_number[0x10];
3475
b4ff3a36 3476 u8 reserved_at_60[0x20];
e281682b
SM		 3477};
3478
3479struct mlx5_ifc_query_vport_counter_out_bits {
3480 u8 status[0x8];
b4ff3a36 3481 u8 reserved_at_8[0x18];
e281682b
SM		 3482
3483 u8 syndrome[0x20];
3484
b4ff3a36 3485 u8 reserved_at_40[0x40];
e281682b
SM		 3486
3487 struct mlx5_ifc_traffic_counter_bits received_errors;
3488
3489 struct mlx5_ifc_traffic_counter_bits transmit_errors;
3490
3491 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3492
3493 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3494
3495 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3496
3497 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3498
3499 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3500
3501 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3502
3503 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3504
3505 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3506
3507 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3508
3509 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3510
b4ff3a36 3511 u8 reserved_at_680[0xa00];
e281682b
SM		 3512};
3513
3514enum {
3515 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
3516};
3517
3518struct mlx5_ifc_query_vport_counter_in_bits {
3519 u8 opcode[0x10];
b4ff3a36 3520 u8 reserved_at_10[0x10];
e281682b 3521
b4ff3a36 3522 u8 reserved_at_20[0x10];
e281682b
SM		 3523 u8 op_mod[0x10];
3524
3525 u8 other_vport[0x1];
b54ba277
MY		 3526 u8 reserved_at_41[0xb];
3527 u8 port_num[0x4];
e281682b
SM		 3528 u8 vport_number[0x10];
3529
b4ff3a36 3530 u8 reserved_at_60[0x60];
e281682b
SM		 3531
3532 u8 clear[0x1];
b4ff3a36 3533 u8 reserved_at_c1[0x1f];
e281682b 3534
b4ff3a36 3535 u8 reserved_at_e0[0x20];
e281682b
SM		 3536};
3537
3538struct mlx5_ifc_query_tis_out_bits {
3539 u8 status[0x8];
b4ff3a36 3540 u8 reserved_at_8[0x18];
e281682b
SM		 3541
3542 u8 syndrome[0x20];
3543
b4ff3a36 3544 u8 reserved_at_40[0x40];
e281682b
SM		 3545
3546 struct mlx5_ifc_tisc_bits tis_context;
3547};
3548
3549struct mlx5_ifc_query_tis_in_bits {
3550 u8 opcode[0x10];
b4ff3a36 3551 u8 reserved_at_10[0x10];
e281682b 3552
b4ff3a36 3553 u8 reserved_at_20[0x10];
e281682b
SM		 3554 u8 op_mod[0x10];
3555
b4ff3a36 3556 u8 reserved_at_40[0x8];
e281682b
SM		 3557 u8 tisn[0x18];
3558
b4ff3a36 3559 u8 reserved_at_60[0x20];
e281682b
SM		 3560};
3561
3562struct mlx5_ifc_query_tir_out_bits {
3563 u8 status[0x8];
b4ff3a36 3564 u8 reserved_at_8[0x18];
e281682b
SM		 3565
3566 u8 syndrome[0x20];
3567
b4ff3a36 3568 u8 reserved_at_40[0xc0];
e281682b
SM		 3569
3570 struct mlx5_ifc_tirc_bits tir_context;
3571};
3572
3573struct mlx5_ifc_query_tir_in_bits {
3574 u8 opcode[0x10];
b4ff3a36 3575 u8 reserved_at_10[0x10];
e281682b 3576
b4ff3a36 3577 u8 reserved_at_20[0x10];
e281682b
SM		 3578 u8 op_mod[0x10];
3579
b4ff3a36 3580 u8 reserved_at_40[0x8];
e281682b
SM		 3581 u8 tirn[0x18];
3582
b4ff3a36 3583 u8 reserved_at_60[0x20];
e281682b
SM		 3584};
3585
3586struct mlx5_ifc_query_srq_out_bits {
3587 u8 status[0x8];
b4ff3a36 3588 u8 reserved_at_8[0x18];
e281682b
SM		 3589
3590 u8 syndrome[0x20];
3591
b4ff3a36 3592 u8 reserved_at_40[0x40];
e281682b
SM		 3593
3594 struct mlx5_ifc_srqc_bits srq_context_entry;
3595
b4ff3a36 3596 u8 reserved_at_280[0x600];
e281682b
SM		 3597
3598 u8 pas[0][0x40];
3599};
3600
3601struct mlx5_ifc_query_srq_in_bits {
3602 u8 opcode[0x10];
b4ff3a36 3603 u8 reserved_at_10[0x10];
e281682b 3604
b4ff3a36 3605 u8 reserved_at_20[0x10];
e281682b
SM		 3606 u8 op_mod[0x10];
3607
b4ff3a36 3608 u8 reserved_at_40[0x8];
e281682b
SM		 3609 u8 srqn[0x18];
3610
b4ff3a36 3611 u8 reserved_at_60[0x20];
e281682b
SM		 3612};
3613
3614struct mlx5_ifc_query_sq_out_bits {
3615 u8 status[0x8];
b4ff3a36 3616 u8 reserved_at_8[0x18];
e281682b
SM		 3617
3618 u8 syndrome[0x20];
3619
b4ff3a36 3620 u8 reserved_at_40[0xc0];
e281682b
SM		 3621
3622 struct mlx5_ifc_sqc_bits sq_context;
3623};
3624
3625struct mlx5_ifc_query_sq_in_bits {
3626 u8 opcode[0x10];
b4ff3a36 3627 u8 reserved_at_10[0x10];
e281682b 3628
b4ff3a36 3629 u8 reserved_at_20[0x10];
e281682b
SM		 3630 u8 op_mod[0x10];
3631
b4ff3a36 3632 u8 reserved_at_40[0x8];
e281682b
SM		 3633 u8 sqn[0x18];
3634
b4ff3a36 3635 u8 reserved_at_60[0x20];
e281682b
SM		 3636};
3637
3638struct mlx5_ifc_query_special_contexts_out_bits {
3639 u8 status[0x8];
b4ff3a36 3640 u8 reserved_at_8[0x18];
e281682b
SM		 3641
3642 u8 syndrome[0x20];
3643
ec22eb53 3644 u8 dump_fill_mkey[0x20];
e281682b
SM		 3645
3646 u8 resd_lkey[0x20];
bcda1aca
AK		 3647
3648 u8 null_mkey[0x20];
3649
3650 u8 reserved_at_a0[0x60];
e281682b
SM		 3651};
3652
3653struct mlx5_ifc_query_special_contexts_in_bits {
3654 u8 opcode[0x10];
b4ff3a36 3655 u8 reserved_at_10[0x10];
e281682b 3656
b4ff3a36 3657 u8 reserved_at_20[0x10];
e281682b
SM		 3658 u8 op_mod[0x10];
3659
b4ff3a36 3660 u8 reserved_at_40[0x40];
e281682b
SM		 3661};
3662
813f8540
MHY		 3663struct mlx5_ifc_query_scheduling_element_out_bits {
3664 u8 opcode[0x10];
3665 u8 reserved_at_10[0x10];
3666
3667 u8 reserved_at_20[0x10];
3668 u8 op_mod[0x10];
3669
3670 u8 reserved_at_40[0xc0];
3671
3672 struct mlx5_ifc_scheduling_context_bits scheduling_context;
3673
3674 u8 reserved_at_300[0x100];
3675};
3676
3677enum {
3678 SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
3679};
3680
3681struct mlx5_ifc_query_scheduling_element_in_bits {
3682 u8 opcode[0x10];
3683 u8 reserved_at_10[0x10];
3684
3685 u8 reserved_at_20[0x10];
3686 u8 op_mod[0x10];
3687
3688 u8 scheduling_hierarchy[0x8];
3689 u8 reserved_at_48[0x18];
3690
3691 u8 scheduling_element_id[0x20];
3692
3693 u8 reserved_at_80[0x180];
3694};
3695
e281682b
SM		 3696struct mlx5_ifc_query_rqt_out_bits {
3697 u8 status[0x8];
b4ff3a36 3698 u8 reserved_at_8[0x18];
e281682b
SM		 3699
3700 u8 syndrome[0x20];
3701
b4ff3a36 3702 u8 reserved_at_40[0xc0];
e281682b
SM		 3703
3704 struct mlx5_ifc_rqtc_bits rqt_context;
3705};
3706
3707struct mlx5_ifc_query_rqt_in_bits {
3708 u8 opcode[0x10];
b4ff3a36 3709 u8 reserved_at_10[0x10];
e281682b 3710
b4ff3a36 3711 u8 reserved_at_20[0x10];
e281682b
SM		 3712 u8 op_mod[0x10];
3713
b4ff3a36 3714 u8 reserved_at_40[0x8];
e281682b
SM		 3715 u8 rqtn[0x18];
3716
b4ff3a36 3717 u8 reserved_at_60[0x20];
e281682b
SM		 3718};
3719
3720struct mlx5_ifc_query_rq_out_bits {
3721 u8 status[0x8];
b4ff3a36 3722 u8 reserved_at_8[0x18];
e281682b
SM		 3723
3724 u8 syndrome[0x20];
3725
b4ff3a36 3726 u8 reserved_at_40[0xc0];
e281682b
SM		 3727
3728 struct mlx5_ifc_rqc_bits rq_context;
3729};
3730
3731struct mlx5_ifc_query_rq_in_bits {
3732 u8 opcode[0x10];
b4ff3a36 3733 u8 reserved_at_10[0x10];
e281682b 3734
b4ff3a36 3735 u8 reserved_at_20[0x10];
e281682b
SM		 3736 u8 op_mod[0x10];
3737
b4ff3a36 3738 u8 reserved_at_40[0x8];
e281682b
SM		 3739 u8 rqn[0x18];
3740
b4ff3a36 3741 u8 reserved_at_60[0x20];
e281682b
SM		 3742};
3743
3744struct mlx5_ifc_query_roce_address_out_bits {
3745 u8 status[0x8];
b4ff3a36 3746 u8 reserved_at_8[0x18];
e281682b
SM		 3747
3748 u8 syndrome[0x20];
3749
b4ff3a36 3750 u8 reserved_at_40[0x40];
e281682b
SM		 3751
3752 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3753};
3754
3755struct mlx5_ifc_query_roce_address_in_bits {
3756 u8 opcode[0x10];
b4ff3a36 3757 u8 reserved_at_10[0x10];
e281682b 3758
b4ff3a36 3759 u8 reserved_at_20[0x10];
e281682b
SM		 3760 u8 op_mod[0x10];
3761
3762 u8 roce_address_index[0x10];
b4ff3a36 3763 u8 reserved_at_50[0x10];
e281682b 3764
b4ff3a36 3765 u8 reserved_at_60[0x20];
e281682b
SM		 3766};
3767
3768struct mlx5_ifc_query_rmp_out_bits {
3769 u8 status[0x8];
b4ff3a36 3770 u8 reserved_at_8[0x18];
e281682b
SM		 3771
3772 u8 syndrome[0x20];
3773
b4ff3a36 3774 u8 reserved_at_40[0xc0];
e281682b
SM		 3775
3776 struct mlx5_ifc_rmpc_bits rmp_context;
3777};
3778
3779struct mlx5_ifc_query_rmp_in_bits {
3780 u8 opcode[0x10];
b4ff3a36 3781 u8 reserved_at_10[0x10];
e281682b 3782
b4ff3a36 3783 u8 reserved_at_20[0x10];
e281682b
SM		 3784 u8 op_mod[0x10];
3785
b4ff3a36 3786 u8 reserved_at_40[0x8];
e281682b
SM		 3787 u8 rmpn[0x18];
3788
b4ff3a36 3789 u8 reserved_at_60[0x20];
e281682b
SM		 3790};
3791
3792struct mlx5_ifc_query_qp_out_bits {
3793 u8 status[0x8];
b4ff3a36 3794 u8 reserved_at_8[0x18];
e281682b
SM		 3795
3796 u8 syndrome[0x20];
3797
b4ff3a36 3798 u8 reserved_at_40[0x40];
e281682b
SM		 3799
3800 u8 opt_param_mask[0x20];
3801
b4ff3a36 3802 u8 reserved_at_a0[0x20];
e281682b
SM		 3803
3804 struct mlx5_ifc_qpc_bits qpc;
3805
b4ff3a36 3806 u8 reserved_at_800[0x80];
e281682b
SM		 3807
3808 u8 pas[0][0x40];
3809};
3810
3811struct mlx5_ifc_query_qp_in_bits {
3812 u8 opcode[0x10];
b4ff3a36 3813 u8 reserved_at_10[0x10];
e281682b 3814
b4ff3a36 3815 u8 reserved_at_20[0x10];
e281682b
SM		 3816 u8 op_mod[0x10];
3817
b4ff3a36 3818 u8 reserved_at_40[0x8];
e281682b
SM		 3819 u8 qpn[0x18];
3820
b4ff3a36 3821 u8 reserved_at_60[0x20];
e281682b
SM		 3822};
3823
3824struct mlx5_ifc_query_q_counter_out_bits {
3825 u8 status[0x8];
b4ff3a36 3826 u8 reserved_at_8[0x18];
e281682b
SM		 3827
3828 u8 syndrome[0x20];
3829
b4ff3a36 3830 u8 reserved_at_40[0x40];
e281682b
SM		 3831
3832 u8 rx_write_requests[0x20];
3833
b4ff3a36 3834 u8 reserved_at_a0[0x20];
e281682b
SM		 3835
3836 u8 rx_read_requests[0x20];
3837
b4ff3a36 3838 u8 reserved_at_e0[0x20];
e281682b
SM		 3839
3840 u8 rx_atomic_requests[0x20];
3841
b4ff3a36 3842 u8 reserved_at_120[0x20];
e281682b
SM		 3843
3844 u8 rx_dct_connect[0x20];
3845
b4ff3a36 3846 u8 reserved_at_160[0x20];
e281682b
SM		 3847
3848 u8 out_of_buffer[0x20];
3849
b4ff3a36 3850 u8 reserved_at_1a0[0x20];
e281682b
SM		 3851
3852 u8 out_of_sequence[0x20];
3853
7486216b
SM		 3854 u8 reserved_at_1e0[0x20];
3855
3856 u8 duplicate_request[0x20];
3857
3858 u8 reserved_at_220[0x20];
3859
3860 u8 rnr_nak_retry_err[0x20];
3861
3862 u8 reserved_at_260[0x20];
3863
3864 u8 packet_seq_err[0x20];
3865
3866 u8 reserved_at_2a0[0x20];
3867
3868 u8 implied_nak_seq_err[0x20];
3869
3870 u8 reserved_at_2e0[0x20];
3871
3872 u8 local_ack_timeout_err[0x20];
3873
3874 u8 reserved_at_320[0x4e0];
e281682b
SM		 3875};
3876
3877struct mlx5_ifc_query_q_counter_in_bits {
3878 u8 opcode[0x10];
b4ff3a36 3879 u8 reserved_at_10[0x10];
e281682b 3880
b4ff3a36 3881 u8 reserved_at_20[0x10];
e281682b
SM		 3882 u8 op_mod[0x10];
3883
b4ff3a36 3884 u8 reserved_at_40[0x80];
e281682b
SM		 3885
3886 u8 clear[0x1];
b4ff3a36 3887 u8 reserved_at_c1[0x1f];
e281682b 3888
b4ff3a36 3889 u8 reserved_at_e0[0x18];
e281682b
SM		 3890 u8 counter_set_id[0x8];
3891};
3892
3893struct mlx5_ifc_query_pages_out_bits {
3894 u8 status[0x8];
b4ff3a36 3895 u8 reserved_at_8[0x18];
e281682b
SM		 3896
3897 u8 syndrome[0x20];
3898
b4ff3a36 3899 u8 reserved_at_40[0x10];
e281682b
SM		 3900 u8 function_id[0x10];
3901
3902 u8 num_pages[0x20];
3903};
3904
3905enum {
3906 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
3907 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
3908 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
3909};
3910
3911struct mlx5_ifc_query_pages_in_bits {
3912 u8 opcode[0x10];
b4ff3a36 3913 u8 reserved_at_10[0x10];
e281682b 3914
b4ff3a36 3915 u8 reserved_at_20[0x10];
e281682b
SM		 3916 u8 op_mod[0x10];
3917
b4ff3a36 3918 u8 reserved_at_40[0x10];
e281682b
SM		 3919 u8 function_id[0x10];
3920
b4ff3a36 3921 u8 reserved_at_60[0x20];
e281682b
SM		 3922};
3923
3924struct mlx5_ifc_query_nic_vport_context_out_bits {
3925 u8 status[0x8];
b4ff3a36 3926 u8 reserved_at_8[0x18];
e281682b
SM		 3927
3928 u8 syndrome[0x20];
3929
b4ff3a36 3930 u8 reserved_at_40[0x40];
e281682b
SM		 3931
3932 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
3933};
3934
3935struct mlx5_ifc_query_nic_vport_context_in_bits {
3936 u8 opcode[0x10];
b4ff3a36 3937 u8 reserved_at_10[0x10];
e281682b 3938
b4ff3a36 3939 u8 reserved_at_20[0x10];
e281682b
SM		 3940 u8 op_mod[0x10];
3941
3942 u8 other_vport[0x1];
b4ff3a36 3943 u8 reserved_at_41[0xf];
e281682b
SM		 3944 u8 vport_number[0x10];
3945
b4ff3a36 3946 u8 reserved_at_60[0x5];
e281682b 3947 u8 allowed_list_type[0x3];
b4ff3a36 3948 u8 reserved_at_68[0x18];
e281682b
SM		 3949};
3950
3951struct mlx5_ifc_query_mkey_out_bits {
3952 u8 status[0x8];
b4ff3a36 3953 u8 reserved_at_8[0x18];
e281682b
SM		 3954
3955 u8 syndrome[0x20];
3956
b4ff3a36 3957 u8 reserved_at_40[0x40];
e281682b
SM		 3958
3959 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
3960
b4ff3a36 3961 u8 reserved_at_280[0x600];
e281682b
SM		 3962
3963 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
3964
3965 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
3966};
3967
3968struct mlx5_ifc_query_mkey_in_bits {
3969 u8 opcode[0x10];
b4ff3a36 3970 u8 reserved_at_10[0x10];
e281682b 3971
b4ff3a36 3972 u8 reserved_at_20[0x10];
e281682b
SM		 3973 u8 op_mod[0x10];
3974
b4ff3a36 3975 u8 reserved_at_40[0x8];
e281682b
SM		 3976 u8 mkey_index[0x18];
3977
3978 u8 pg_access[0x1];
b4ff3a36 3979 u8 reserved_at_61[0x1f];
e281682b
SM		 3980};
3981
3982struct mlx5_ifc_query_mad_demux_out_bits {
3983 u8 status[0x8];
b4ff3a36 3984 u8 reserved_at_8[0x18];
e281682b
SM		 3985
3986 u8 syndrome[0x20];
3987
b4ff3a36 3988 u8 reserved_at_40[0x40];
e281682b
SM		 3989
3990 u8 mad_dumux_parameters_block[0x20];
3991};
3992
3993struct mlx5_ifc_query_mad_demux_in_bits {
3994 u8 opcode[0x10];
b4ff3a36 3995 u8 reserved_at_10[0x10];
e281682b 3996
b4ff3a36 3997 u8 reserved_at_20[0x10];
e281682b
SM		 3998 u8 op_mod[0x10];
3999
b4ff3a36 4000 u8 reserved_at_40[0x40];
e281682b
SM		 4001};
4002
4003struct mlx5_ifc_query_l2_table_entry_out_bits {
4004 u8 status[0x8];
b4ff3a36 4005 u8 reserved_at_8[0x18];
e281682b
SM		 4006
4007 u8 syndrome[0x20];
4008
b4ff3a36 4009 u8 reserved_at_40[0xa0];
e281682b 4010
b4ff3a36 4011 u8 reserved_at_e0[0x13];
e281682b
SM		 4012 u8 vlan_valid[0x1];
4013 u8 vlan[0xc];
4014
4015 struct mlx5_ifc_mac_address_layout_bits mac_address;
4016
b4ff3a36 4017 u8 reserved_at_140[0xc0];
e281682b
SM		 4018};
4019
4020struct mlx5_ifc_query_l2_table_entry_in_bits {
4021 u8 opcode[0x10];
b4ff3a36 4022 u8 reserved_at_10[0x10];
e281682b 4023
b4ff3a36 4024 u8 reserved_at_20[0x10];
e281682b
SM		 4025 u8 op_mod[0x10];
4026
b4ff3a36 4027 u8 reserved_at_40[0x60];
e281682b 4028
b4ff3a36 4029 u8 reserved_at_a0[0x8];
e281682b
SM		 4030 u8 table_index[0x18];
4031
b4ff3a36 4032 u8 reserved_at_c0[0x140];
e281682b
SM		 4033};
4034
4035struct mlx5_ifc_query_issi_out_bits {
4036 u8 status[0x8];
b4ff3a36 4037 u8 reserved_at_8[0x18];
e281682b
SM		 4038
4039 u8 syndrome[0x20];
4040
b4ff3a36 4041 u8 reserved_at_40[0x10];
e281682b
SM		 4042 u8 current_issi[0x10];
4043
b4ff3a36 4044 u8 reserved_at_60[0xa0];
e281682b 4045
b4ff3a36 4046 u8 reserved_at_100[76][0x8];
e281682b
SM		 4047 u8 supported_issi_dw0[0x20];
4048};
4049
4050struct mlx5_ifc_query_issi_in_bits {
4051 u8 opcode[0x10];
b4ff3a36 4052 u8 reserved_at_10[0x10];
e281682b 4053
b4ff3a36 4054 u8 reserved_at_20[0x10];
e281682b
SM		 4055 u8 op_mod[0x10];
4056
b4ff3a36 4057 u8 reserved_at_40[0x40];
e281682b
SM		 4058};
4059
0dbc6fe0
SM		 4060struct mlx5_ifc_set_driver_version_out_bits {
4061 u8 status[0x8];
4062 u8 reserved_0[0x18];
4063
4064 u8 syndrome[0x20];
4065 u8 reserved_1[0x40];
4066};
4067
4068struct mlx5_ifc_set_driver_version_in_bits {
4069 u8 opcode[0x10];
4070 u8 reserved_0[0x10];
4071
4072 u8 reserved_1[0x10];
4073 u8 op_mod[0x10];
4074
4075 u8 reserved_2[0x40];
4076 u8 driver_version[64][0x8];
4077};
4078
e281682b
SM		 4079struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4080 u8 status[0x8];
b4ff3a36 4081 u8 reserved_at_8[0x18];
e281682b
SM		 4082
4083 u8 syndrome[0x20];
4084
b4ff3a36 4085 u8 reserved_at_40[0x40];
e281682b
SM		 4086
4087 struct mlx5_ifc_pkey_bits pkey[0];
4088};
4089
4090struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4091 u8 opcode[0x10];
b4ff3a36 4092 u8 reserved_at_10[0x10];
e281682b 4093
b4ff3a36 4094 u8 reserved_at_20[0x10];
e281682b
SM		 4095 u8 op_mod[0x10];
4096
4097 u8 other_vport[0x1];
b4ff3a36 4098 u8 reserved_at_41[0xb];
707c4602 4099 u8 port_num[0x4];
e281682b
SM		 4100 u8 vport_number[0x10];
4101
b4ff3a36 4102 u8 reserved_at_60[0x10];
e281682b
SM		 4103 u8 pkey_index[0x10];
4104};
4105
eff901d3
EC		 4106enum {
4107 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
4108 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
4109 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4110};
4111
e281682b
SM		 4112struct mlx5_ifc_query_hca_vport_gid_out_bits {
4113 u8 status[0x8];
b4ff3a36 4114 u8 reserved_at_8[0x18];
e281682b
SM		 4115
4116 u8 syndrome[0x20];
4117
b4ff3a36 4118 u8 reserved_at_40[0x20];
e281682b
SM		 4119
4120 u8 gids_num[0x10];
b4ff3a36 4121 u8 reserved_at_70[0x10];
e281682b
SM		 4122
4123 struct mlx5_ifc_array128_auto_bits gid[0];
4124};
4125
4126struct mlx5_ifc_query_hca_vport_gid_in_bits {
4127 u8 opcode[0x10];
b4ff3a36 4128 u8 reserved_at_10[0x10];
e281682b 4129
b4ff3a36 4130 u8 reserved_at_20[0x10];
e281682b
SM		 4131 u8 op_mod[0x10];
4132
4133 u8 other_vport[0x1];
b4ff3a36 4134 u8 reserved_at_41[0xb];
707c4602 4135 u8 port_num[0x4];
e281682b
SM		 4136 u8 vport_number[0x10];
4137
b4ff3a36 4138 u8 reserved_at_60[0x10];
e281682b
SM		 4139 u8 gid_index[0x10];
4140};
4141
4142struct mlx5_ifc_query_hca_vport_context_out_bits {
4143 u8 status[0x8];
b4ff3a36 4144 u8 reserved_at_8[0x18];
e281682b
SM		 4145
4146 u8 syndrome[0x20];
4147
b4ff3a36 4148 u8 reserved_at_40[0x40];
e281682b
SM		 4149
4150 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4151};
4152
4153struct mlx5_ifc_query_hca_vport_context_in_bits {
4154 u8 opcode[0x10];
b4ff3a36 4155 u8 reserved_at_10[0x10];
e281682b 4156
b4ff3a36 4157 u8 reserved_at_20[0x10];
e281682b
SM		 4158 u8 op_mod[0x10];
4159
4160 u8 other_vport[0x1];
b4ff3a36 4161 u8 reserved_at_41[0xb];
707c4602 4162 u8 port_num[0x4];
e281682b
SM		 4163 u8 vport_number[0x10];
4164
b4ff3a36 4165 u8 reserved_at_60[0x20];
e281682b
SM		 4166};
4167
4168struct mlx5_ifc_query_hca_cap_out_bits {
4169 u8 status[0x8];
b4ff3a36 4170 u8 reserved_at_8[0x18];
e281682b
SM		 4171
4172 u8 syndrome[0x20];
4173
b4ff3a36 4174 u8 reserved_at_40[0x40];
e281682b
SM		 4175
4176 union mlx5_ifc_hca_cap_union_bits capability;
4177};
4178
4179struct mlx5_ifc_query_hca_cap_in_bits {
4180 u8 opcode[0x10];
b4ff3a36 4181 u8 reserved_at_10[0x10];
e281682b 4182
b4ff3a36 4183 u8 reserved_at_20[0x10];
e281682b
SM		 4184 u8 op_mod[0x10];
4185
b4ff3a36 4186 u8 reserved_at_40[0x40];
e281682b
SM		 4187};
4188
4189struct mlx5_ifc_query_flow_table_out_bits {
4190 u8 status[0x8];
b4ff3a36 4191 u8 reserved_at_8[0x18];
e281682b
SM		 4192
4193 u8 syndrome[0x20];
4194
b4ff3a36 4195 u8 reserved_at_40[0x80];
e281682b 4196
b4ff3a36 4197 u8 reserved_at_c0[0x8];
e281682b 4198 u8 level[0x8];
b4ff3a36 4199 u8 reserved_at_d0[0x8];
e281682b
SM		 4200 u8 log_size[0x8];
4201
b4ff3a36 4202 u8 reserved_at_e0[0x120];
e281682b
SM		 4203};
4204
4205struct mlx5_ifc_query_flow_table_in_bits {
4206 u8 opcode[0x10];
b4ff3a36 4207 u8 reserved_at_10[0x10];
e281682b 4208
b4ff3a36 4209 u8 reserved_at_20[0x10];
e281682b
SM		 4210 u8 op_mod[0x10];
4211
b4ff3a36 4212 u8 reserved_at_40[0x40];
e281682b
SM		 4213
4214 u8 table_type[0x8];
b4ff3a36 4215 u8 reserved_at_88[0x18];
e281682b 4216
b4ff3a36 4217 u8 reserved_at_a0[0x8];
e281682b
SM		 4218 u8 table_id[0x18];
4219
b4ff3a36 4220 u8 reserved_at_c0[0x140];
e281682b
SM		 4221};
4222
4223struct mlx5_ifc_query_fte_out_bits {
4224 u8 status[0x8];
b4ff3a36 4225 u8 reserved_at_8[0x18];
e281682b
SM		 4226
4227 u8 syndrome[0x20];
4228
b4ff3a36 4229 u8 reserved_at_40[0x1c0];
e281682b
SM		 4230
4231 struct mlx5_ifc_flow_context_bits flow_context;
4232};
4233
4234struct mlx5_ifc_query_fte_in_bits {
4235 u8 opcode[0x10];
b4ff3a36 4236 u8 reserved_at_10[0x10];
e281682b 4237
b4ff3a36 4238 u8 reserved_at_20[0x10];
e281682b
SM		 4239 u8 op_mod[0x10];
4240
b4ff3a36 4241 u8 reserved_at_40[0x40];
e281682b
SM		 4242
4243 u8 table_type[0x8];
b4ff3a36 4244 u8 reserved_at_88[0x18];
e281682b 4245
b4ff3a36 4246 u8 reserved_at_a0[0x8];
e281682b
SM		 4247 u8 table_id[0x18];
4248
b4ff3a36 4249 u8 reserved_at_c0[0x40];
e281682b
SM		 4250
4251 u8 flow_index[0x20];
4252
b4ff3a36 4253 u8 reserved_at_120[0xe0];
e281682b
SM		 4254};
4255
4256enum {
4257 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
4258 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
4259 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
4260};
4261
4262struct mlx5_ifc_query_flow_group_out_bits {
4263 u8 status[0x8];
b4ff3a36 4264 u8 reserved_at_8[0x18];
e281682b
SM		 4265
4266 u8 syndrome[0x20];
4267
b4ff3a36 4268 u8 reserved_at_40[0xa0];
e281682b
SM		 4269
4270 u8 start_flow_index[0x20];
4271
b4ff3a36 4272 u8 reserved_at_100[0x20];
e281682b
SM		 4273
4274 u8 end_flow_index[0x20];
4275
b4ff3a36 4276 u8 reserved_at_140[0xa0];
e281682b 4277
b4ff3a36 4278 u8 reserved_at_1e0[0x18];
e281682b
SM		 4279 u8 match_criteria_enable[0x8];
4280
4281 struct mlx5_ifc_fte_match_param_bits match_criteria;
4282
b4ff3a36 4283 u8 reserved_at_1200[0xe00];
e281682b
SM		 4284};
4285
4286struct mlx5_ifc_query_flow_group_in_bits {
4287 u8 opcode[0x10];
b4ff3a36 4288 u8 reserved_at_10[0x10];
e281682b 4289
b4ff3a36 4290 u8 reserved_at_20[0x10];
e281682b
SM		 4291 u8 op_mod[0x10];
4292
b4ff3a36 4293 u8 reserved_at_40[0x40];
e281682b
SM		 4294
4295 u8 table_type[0x8];
b4ff3a36 4296 u8 reserved_at_88[0x18];
e281682b 4297
b4ff3a36 4298 u8 reserved_at_a0[0x8];
e281682b
SM		 4299 u8 table_id[0x18];
4300
4301 u8 group_id[0x20];
4302
b4ff3a36 4303 u8 reserved_at_e0[0x120];
e281682b
SM		 4304};
4305
9dc0b289
AV		 4306struct mlx5_ifc_query_flow_counter_out_bits {
4307 u8 status[0x8];
4308 u8 reserved_at_8[0x18];
4309
4310 u8 syndrome[0x20];
4311
4312 u8 reserved_at_40[0x40];
4313
4314 struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4315};
4316
4317struct mlx5_ifc_query_flow_counter_in_bits {
4318 u8 opcode[0x10];
4319 u8 reserved_at_10[0x10];
4320
4321 u8 reserved_at_20[0x10];
4322 u8 op_mod[0x10];
4323
4324 u8 reserved_at_40[0x80];
4325
4326 u8 clear[0x1];
4327 u8 reserved_at_c1[0xf];
4328 u8 num_of_counters[0x10];
4329
4330 u8 reserved_at_e0[0x10];
4331 u8 flow_counter_id[0x10];
4332};
4333
d6666753
SM		 4334struct mlx5_ifc_query_esw_vport_context_out_bits {
4335 u8 status[0x8];
b4ff3a36 4336 u8 reserved_at_8[0x18];
d6666753
SM		 4337
4338 u8 syndrome[0x20];
4339
b4ff3a36 4340 u8 reserved_at_40[0x40];
d6666753
SM		 4341
4342 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4343};
4344
4345struct mlx5_ifc_query_esw_vport_context_in_bits {
4346 u8 opcode[0x10];
b4ff3a36 4347 u8 reserved_at_10[0x10];
d6666753 4348
b4ff3a36 4349 u8 reserved_at_20[0x10];
d6666753
SM		 4350 u8 op_mod[0x10];
4351
4352 u8 other_vport[0x1];
b4ff3a36 4353 u8 reserved_at_41[0xf];
d6666753
SM		 4354 u8 vport_number[0x10];
4355
b4ff3a36 4356 u8 reserved_at_60[0x20];
d6666753
SM		 4357};
4358
4359struct mlx5_ifc_modify_esw_vport_context_out_bits {
4360 u8 status[0x8];
b4ff3a36 4361 u8 reserved_at_8[0x18];
d6666753
SM		 4362
4363 u8 syndrome[0x20];
4364
b4ff3a36 4365 u8 reserved_at_40[0x40];
d6666753
SM		 4366};
4367
4368struct mlx5_ifc_esw_vport_context_fields_select_bits {
b4ff3a36 4369 u8 reserved_at_0[0x1c];
d6666753
SM		 4370 u8 vport_cvlan_insert[0x1];
4371 u8 vport_svlan_insert[0x1];
4372 u8 vport_cvlan_strip[0x1];
4373 u8 vport_svlan_strip[0x1];
4374};
4375
4376struct mlx5_ifc_modify_esw_vport_context_in_bits {
4377 u8 opcode[0x10];
b4ff3a36 4378 u8 reserved_at_10[0x10];
d6666753 4379
b4ff3a36 4380 u8 reserved_at_20[0x10];
d6666753
SM		 4381 u8 op_mod[0x10];
4382
4383 u8 other_vport[0x1];
b4ff3a36 4384 u8 reserved_at_41[0xf];
d6666753
SM		 4385 u8 vport_number[0x10];
4386
4387 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4388
4389 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4390};
4391
e281682b
SM		 4392struct mlx5_ifc_query_eq_out_bits {
4393 u8 status[0x8];
b4ff3a36 4394 u8 reserved_at_8[0x18];
e281682b
SM		 4395
4396 u8 syndrome[0x20];
4397
b4ff3a36 4398 u8 reserved_at_40[0x40];
e281682b
SM		 4399
4400 struct mlx5_ifc_eqc_bits eq_context_entry;
4401
b4ff3a36 4402 u8 reserved_at_280[0x40];
e281682b
SM		 4403
4404 u8 event_bitmask[0x40];
4405
b4ff3a36 4406 u8 reserved_at_300[0x580];
e281682b
SM		 4407
4408 u8 pas[0][0x40];
4409};
4410
4411struct mlx5_ifc_query_eq_in_bits {
4412 u8 opcode[0x10];
b4ff3a36 4413 u8 reserved_at_10[0x10];
e281682b 4414
b4ff3a36 4415 u8 reserved_at_20[0x10];
e281682b
SM		 4416 u8 op_mod[0x10];
4417
b4ff3a36 4418 u8 reserved_at_40[0x18];
e281682b
SM		 4419 u8 eq_number[0x8];
4420
b4ff3a36 4421 u8 reserved_at_60[0x20];
e281682b
SM		 4422};
4423
7adbde20
HHZ		 4424struct mlx5_ifc_encap_header_in_bits {
4425 u8 reserved_at_0[0x5];
4426 u8 header_type[0x3];
4427 u8 reserved_at_8[0xe];
4428 u8 encap_header_size[0xa];
4429
4430 u8 reserved_at_20[0x10];
4431 u8 encap_header[2][0x8];
4432
4433 u8 more_encap_header[0][0x8];
4434};
4435
4436struct mlx5_ifc_query_encap_header_out_bits {
4437 u8 status[0x8];
4438 u8 reserved_at_8[0x18];
4439
4440 u8 syndrome[0x20];
4441
4442 u8 reserved_at_40[0xa0];
4443
4444 struct mlx5_ifc_encap_header_in_bits encap_header[0];
4445};
4446
4447struct mlx5_ifc_query_encap_header_in_bits {
4448 u8 opcode[0x10];
4449 u8 reserved_at_10[0x10];
4450
4451 u8 reserved_at_20[0x10];
4452 u8 op_mod[0x10];
4453
4454 u8 encap_id[0x20];
4455
4456 u8 reserved_at_60[0xa0];
4457};
4458
4459struct mlx5_ifc_alloc_encap_header_out_bits {
4460 u8 status[0x8];
4461 u8 reserved_at_8[0x18];
4462
4463 u8 syndrome[0x20];
4464
4465 u8 encap_id[0x20];
4466
4467 u8 reserved_at_60[0x20];
4468};
4469
4470struct mlx5_ifc_alloc_encap_header_in_bits {
4471 u8 opcode[0x10];
4472 u8 reserved_at_10[0x10];
4473
4474 u8 reserved_at_20[0x10];
4475 u8 op_mod[0x10];
4476
4477 u8 reserved_at_40[0xa0];
4478
4479 struct mlx5_ifc_encap_header_in_bits encap_header;
4480};
4481
4482struct mlx5_ifc_dealloc_encap_header_out_bits {
4483 u8 status[0x8];
4484 u8 reserved_at_8[0x18];
4485
4486 u8 syndrome[0x20];
4487
4488 u8 reserved_at_40[0x40];
4489};
4490
4491struct mlx5_ifc_dealloc_encap_header_in_bits {
4492 u8 opcode[0x10];
4493 u8 reserved_at_10[0x10];
4494
4495 u8 reserved_20[0x10];
4496 u8 op_mod[0x10];
4497
4498 u8 encap_id[0x20];
4499
4500 u8 reserved_60[0x20];
4501};
4502
e281682b
SM		 4503struct mlx5_ifc_query_dct_out_bits {
4504 u8 status[0x8];
b4ff3a36 4505 u8 reserved_at_8[0x18];
e281682b
SM		 4506
4507 u8 syndrome[0x20];
4508
b4ff3a36 4509 u8 reserved_at_40[0x40];
e281682b
SM		 4510
4511 struct mlx5_ifc_dctc_bits dct_context_entry;
4512
b4ff3a36 4513 u8 reserved_at_280[0x180];
e281682b
SM		 4514};
4515
4516struct mlx5_ifc_query_dct_in_bits {
4517 u8 opcode[0x10];
b4ff3a36 4518 u8 reserved_at_10[0x10];
e281682b 4519
b4ff3a36 4520 u8 reserved_at_20[0x10];
e281682b
SM		 4521 u8 op_mod[0x10];
4522
b4ff3a36 4523 u8 reserved_at_40[0x8];
e281682b
SM		 4524 u8 dctn[0x18];
4525
b4ff3a36 4526 u8 reserved_at_60[0x20];
e281682b
SM		 4527};
4528
4529struct mlx5_ifc_query_cq_out_bits {
4530 u8 status[0x8];
b4ff3a36 4531 u8 reserved_at_8[0x18];
e281682b
SM		 4532
4533 u8 syndrome[0x20];
4534
b4ff3a36 4535 u8 reserved_at_40[0x40];
e281682b
SM		 4536
4537 struct mlx5_ifc_cqc_bits cq_context;
4538
b4ff3a36 4539 u8 reserved_at_280[0x600];
e281682b
SM		 4540
4541 u8 pas[0][0x40];
4542};
4543
4544struct mlx5_ifc_query_cq_in_bits {
4545 u8 opcode[0x10];
b4ff3a36 4546 u8 reserved_at_10[0x10];
e281682b 4547
b4ff3a36 4548 u8 reserved_at_20[0x10];
e281682b
SM		 4549 u8 op_mod[0x10];
4550
b4ff3a36 4551 u8 reserved_at_40[0x8];
e281682b
SM		 4552 u8 cqn[0x18];
4553
b4ff3a36 4554 u8 reserved_at_60[0x20];
e281682b
SM		 4555};
4556
4557struct mlx5_ifc_query_cong_status_out_bits {
4558 u8 status[0x8];
b4ff3a36 4559 u8 reserved_at_8[0x18];
e281682b
SM		 4560
4561 u8 syndrome[0x20];
4562
b4ff3a36 4563 u8 reserved_at_40[0x20];
e281682b
SM		 4564
4565 u8 enable[0x1];
4566 u8 tag_enable[0x1];
b4ff3a36 4567 u8 reserved_at_62[0x1e];
e281682b
SM		 4568};
4569
4570struct mlx5_ifc_query_cong_status_in_bits {
4571 u8 opcode[0x10];
b4ff3a36 4572 u8 reserved_at_10[0x10];
e281682b 4573
b4ff3a36 4574 u8 reserved_at_20[0x10];
e281682b
SM		 4575 u8 op_mod[0x10];
4576
b4ff3a36 4577 u8 reserved_at_40[0x18];
e281682b
SM		 4578 u8 priority[0x4];
4579 u8 cong_protocol[0x4];
4580
b4ff3a36 4581 u8 reserved_at_60[0x20];
e281682b
SM		 4582};
4583
4584struct mlx5_ifc_query_cong_statistics_out_bits {
4585 u8 status[0x8];
b4ff3a36 4586 u8 reserved_at_8[0x18];
e281682b
SM		 4587
4588 u8 syndrome[0x20];
4589
b4ff3a36 4590 u8 reserved_at_40[0x40];
e281682b
SM		 4591
4592 u8 cur_flows[0x20];
4593
4594 u8 sum_flows[0x20];
4595
4596 u8 cnp_ignored_high[0x20];
4597
4598 u8 cnp_ignored_low[0x20];
4599
4600 u8 cnp_handled_high[0x20];
4601
4602 u8 cnp_handled_low[0x20];
4603
b4ff3a36 4604 u8 reserved_at_140[0x100];
e281682b
SM		 4605
4606 u8 time_stamp_high[0x20];
4607
4608 u8 time_stamp_low[0x20];
4609
4610 u8 accumulators_period[0x20];
4611
4612 u8 ecn_marked_roce_packets_high[0x20];
4613
4614 u8 ecn_marked_roce_packets_low[0x20];
4615
4616 u8 cnps_sent_high[0x20];
4617
4618 u8 cnps_sent_low[0x20];
4619
b4ff3a36 4620 u8 reserved_at_320[0x560];
e281682b
SM		 4621};
4622
4623struct mlx5_ifc_query_cong_statistics_in_bits {
4624 u8 opcode[0x10];
b4ff3a36 4625 u8 reserved_at_10[0x10];
e281682b 4626
b4ff3a36 4627 u8 reserved_at_20[0x10];
e281682b
SM		 4628 u8 op_mod[0x10];
4629
4630 u8 clear[0x1];
b4ff3a36 4631 u8 reserved_at_41[0x1f];
e281682b 4632
b4ff3a36 4633 u8 reserved_at_60[0x20];
e281682b
SM		 4634};
4635
4636struct mlx5_ifc_query_cong_params_out_bits {
4637 u8 status[0x8];
b4ff3a36 4638 u8 reserved_at_8[0x18];
e281682b
SM		 4639
4640 u8 syndrome[0x20];
4641
b4ff3a36 4642 u8 reserved_at_40[0x40];
e281682b
SM		 4643
4644 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4645};
4646
4647struct mlx5_ifc_query_cong_params_in_bits {
4648 u8 opcode[0x10];
b4ff3a36 4649 u8 reserved_at_10[0x10];
e281682b 4650
b4ff3a36 4651 u8 reserved_at_20[0x10];
e281682b
SM		 4652 u8 op_mod[0x10];
4653
b4ff3a36 4654 u8 reserved_at_40[0x1c];
e281682b
SM		 4655 u8 cong_protocol[0x4];
4656
b4ff3a36 4657 u8 reserved_at_60[0x20];
e281682b
SM		 4658};
4659
4660struct mlx5_ifc_query_adapter_out_bits {
4661 u8 status[0x8];
b4ff3a36 4662 u8 reserved_at_8[0x18];
e281682b
SM		 4663
4664 u8 syndrome[0x20];
4665
b4ff3a36 4666 u8 reserved_at_40[0x40];
e281682b
SM		 4667
4668 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4669};
4670
4671struct mlx5_ifc_query_adapter_in_bits {
4672 u8 opcode[0x10];
b4ff3a36 4673 u8 reserved_at_10[0x10];
e281682b 4674
b4ff3a36 4675 u8 reserved_at_20[0x10];
e281682b
SM		 4676 u8 op_mod[0x10];
4677
b4ff3a36 4678 u8 reserved_at_40[0x40];
e281682b
SM		 4679};
4680
4681struct mlx5_ifc_qp_2rst_out_bits {
4682 u8 status[0x8];
b4ff3a36 4683 u8 reserved_at_8[0x18];
e281682b
SM		 4684
4685 u8 syndrome[0x20];
4686
b4ff3a36 4687 u8 reserved_at_40[0x40];
e281682b
SM		 4688};
4689
4690struct mlx5_ifc_qp_2rst_in_bits {
4691 u8 opcode[0x10];
b4ff3a36 4692 u8 reserved_at_10[0x10];
e281682b 4693
b4ff3a36 4694 u8 reserved_at_20[0x10];
e281682b
SM		 4695 u8 op_mod[0x10];
4696
b4ff3a36 4697 u8 reserved_at_40[0x8];
e281682b
SM		 4698 u8 qpn[0x18];
4699
b4ff3a36 4700 u8 reserved_at_60[0x20];
e281682b
SM		 4701};
4702
4703struct mlx5_ifc_qp_2err_out_bits {
4704 u8 status[0x8];
b4ff3a36 4705 u8 reserved_at_8[0x18];
e281682b
SM		 4706
4707 u8 syndrome[0x20];
4708
b4ff3a36 4709 u8 reserved_at_40[0x40];
e281682b
SM		 4710};
4711
4712struct mlx5_ifc_qp_2err_in_bits {
4713 u8 opcode[0x10];
b4ff3a36 4714 u8 reserved_at_10[0x10];
e281682b 4715
b4ff3a36 4716 u8 reserved_at_20[0x10];
e281682b
SM		 4717 u8 op_mod[0x10];
4718
b4ff3a36 4719 u8 reserved_at_40[0x8];
e281682b
SM		 4720 u8 qpn[0x18];
4721
b4ff3a36 4722 u8 reserved_at_60[0x20];
e281682b
SM		 4723};
4724
4725struct mlx5_ifc_page_fault_resume_out_bits {
4726 u8 status[0x8];
b4ff3a36 4727 u8 reserved_at_8[0x18];
e281682b
SM		 4728
4729 u8 syndrome[0x20];
4730
b4ff3a36 4731 u8 reserved_at_40[0x40];
e281682b
SM		 4732};
4733
4734struct mlx5_ifc_page_fault_resume_in_bits {
4735 u8 opcode[0x10];
b4ff3a36 4736 u8 reserved_at_10[0x10];
e281682b 4737
b4ff3a36 4738 u8 reserved_at_20[0x10];
e281682b
SM		 4739 u8 op_mod[0x10];
4740
4741 u8 error[0x1];
b4ff3a36 4742 u8 reserved_at_41[0x4];
223cdc72
AK		 4743 u8 page_fault_type[0x3];
4744 u8 wq_number[0x18];
e281682b 4745
223cdc72
AK		 4746 u8 reserved_at_60[0x8];
4747 u8 token[0x18];
e281682b
SM		 4748};
4749
4750struct mlx5_ifc_nop_out_bits {
4751 u8 status[0x8];
b4ff3a36 4752 u8 reserved_at_8[0x18];
e281682b
SM		 4753
4754 u8 syndrome[0x20];
4755
b4ff3a36 4756 u8 reserved_at_40[0x40];
e281682b
SM		 4757};
4758
4759struct mlx5_ifc_nop_in_bits {
4760 u8 opcode[0x10];
b4ff3a36 4761 u8 reserved_at_10[0x10];
e281682b 4762
b4ff3a36 4763 u8 reserved_at_20[0x10];
e281682b
SM		 4764 u8 op_mod[0x10];
4765
b4ff3a36 4766 u8 reserved_at_40[0x40];
e281682b
SM		 4767};
4768
4769struct mlx5_ifc_modify_vport_state_out_bits {
4770 u8 status[0x8];
b4ff3a36 4771 u8 reserved_at_8[0x18];
e281682b
SM		 4772
4773 u8 syndrome[0x20];
4774
b4ff3a36 4775 u8 reserved_at_40[0x40];
e281682b
SM		 4776};
4777
4778struct mlx5_ifc_modify_vport_state_in_bits {
4779 u8 opcode[0x10];
b4ff3a36 4780 u8 reserved_at_10[0x10];
e281682b 4781
b4ff3a36 4782 u8 reserved_at_20[0x10];
e281682b
SM		 4783 u8 op_mod[0x10];
4784
4785 u8 other_vport[0x1];
b4ff3a36 4786 u8 reserved_at_41[0xf];
e281682b
SM		 4787 u8 vport_number[0x10];
4788
b4ff3a36 4789 u8 reserved_at_60[0x18];
e281682b 4790 u8 admin_state[0x4];
b4ff3a36 4791 u8 reserved_at_7c[0x4];
e281682b
SM		 4792};
4793
4794struct mlx5_ifc_modify_tis_out_bits {
4795 u8 status[0x8];
b4ff3a36 4796 u8 reserved_at_8[0x18];
e281682b
SM		 4797
4798 u8 syndrome[0x20];
4799
b4ff3a36 4800 u8 reserved_at_40[0x40];
e281682b
SM		 4801};
4802
75850d0b 4803struct mlx5_ifc_modify_tis_bitmask_bits {
b4ff3a36 4804 u8 reserved_at_0[0x20];
75850d0b 4805
84df61eb
AH		 4806 u8 reserved_at_20[0x1d];
4807 u8 lag_tx_port_affinity[0x1];
4808 u8 strict_lag_tx_port_affinity[0x1];
75850d0b 4809 u8 prio[0x1];
4810};
4811
e281682b
SM		 4812struct mlx5_ifc_modify_tis_in_bits {
4813 u8 opcode[0x10];
b4ff3a36 4814 u8 reserved_at_10[0x10];
e281682b 4815
b4ff3a36 4816 u8 reserved_at_20[0x10];
e281682b
SM		 4817 u8 op_mod[0x10];
4818
b4ff3a36 4819 u8 reserved_at_40[0x8];
e281682b
SM		 4820 u8 tisn[0x18];
4821
b4ff3a36 4822 u8 reserved_at_60[0x20];
e281682b 4823
75850d0b 4824 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
e281682b 4825
b4ff3a36 4826 u8 reserved_at_c0[0x40];
e281682b
SM		 4827
4828 struct mlx5_ifc_tisc_bits ctx;
4829};
4830
d9eea403 4831struct mlx5_ifc_modify_tir_bitmask_bits {
b4ff3a36 4832 u8 reserved_at_0[0x20];
d9eea403 4833
b4ff3a36 4834 u8 reserved_at_20[0x1b];
66189961 4835 u8 self_lb_en[0x1];
bdfc028d
TT		 4836 u8 reserved_at_3c[0x1];
4837 u8 hash[0x1];
4838 u8 reserved_at_3e[0x1];
d9eea403
AS		 4839 u8 lro[0x1];
4840};
4841
e281682b
SM		 4842struct mlx5_ifc_modify_tir_out_bits {
4843 u8 status[0x8];
b4ff3a36 4844 u8 reserved_at_8[0x18];
e281682b
SM		 4845
4846 u8 syndrome[0x20];
4847
b4ff3a36 4848 u8 reserved_at_40[0x40];
e281682b
SM		 4849};
4850
4851struct mlx5_ifc_modify_tir_in_bits {
4852 u8 opcode[0x10];
b4ff3a36 4853 u8 reserved_at_10[0x10];
e281682b 4854
b4ff3a36 4855 u8 reserved_at_20[0x10];
e281682b
SM		 4856 u8 op_mod[0x10];
4857
b4ff3a36 4858 u8 reserved_at_40[0x8];
e281682b
SM		 4859 u8 tirn[0x18];
4860
b4ff3a36 4861 u8 reserved_at_60[0x20];
e281682b 4862
d9eea403 4863 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
e281682b 4864
b4ff3a36 4865 u8 reserved_at_c0[0x40];
e281682b
SM		 4866
4867 struct mlx5_ifc_tirc_bits ctx;
4868};
4869
4870struct mlx5_ifc_modify_sq_out_bits {
4871 u8 status[0x8];
b4ff3a36 4872 u8 reserved_at_8[0x18];
e281682b
SM		 4873
4874 u8 syndrome[0x20];
4875
b4ff3a36 4876 u8 reserved_at_40[0x40];
e281682b
SM		 4877};
4878
4879struct mlx5_ifc_modify_sq_in_bits {
4880 u8 opcode[0x10];
b4ff3a36 4881 u8 reserved_at_10[0x10];
e281682b 4882
b4ff3a36 4883 u8 reserved_at_20[0x10];
e281682b
SM		 4884 u8 op_mod[0x10];
4885
4886 u8 sq_state[0x4];
b4ff3a36 4887 u8 reserved_at_44[0x4];
e281682b
SM		 4888 u8 sqn[0x18];
4889
b4ff3a36 4890 u8 reserved_at_60[0x20];
e281682b
SM		 4891
4892 u8 modify_bitmask[0x40];
4893
b4ff3a36 4894 u8 reserved_at_c0[0x40];
e281682b
SM		 4895
4896 struct mlx5_ifc_sqc_bits ctx;
4897};
4898
813f8540
MHY		 4899struct mlx5_ifc_modify_scheduling_element_out_bits {
4900 u8 status[0x8];
4901 u8 reserved_at_8[0x18];
4902
4903 u8 syndrome[0x20];
4904
4905 u8 reserved_at_40[0x1c0];
4906};
4907
4908enum {
4909 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
4910 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
4911};
4912
4913struct mlx5_ifc_modify_scheduling_element_in_bits {
4914 u8 opcode[0x10];
4915 u8 reserved_at_10[0x10];
4916
4917 u8 reserved_at_20[0x10];
4918 u8 op_mod[0x10];
4919
4920 u8 scheduling_hierarchy[0x8];
4921 u8 reserved_at_48[0x18];
4922
4923 u8 scheduling_element_id[0x20];
4924
4925 u8 reserved_at_80[0x20];
4926
4927 u8 modify_bitmask[0x20];
4928
4929 u8 reserved_at_c0[0x40];
4930
4931 struct mlx5_ifc_scheduling_context_bits scheduling_context;
4932
4933 u8 reserved_at_300[0x100];
4934};
4935
e281682b
SM		 4936struct mlx5_ifc_modify_rqt_out_bits {
4937 u8 status[0x8];
b4ff3a36 4938 u8 reserved_at_8[0x18];
e281682b
SM		 4939
4940 u8 syndrome[0x20];
4941
b4ff3a36 4942 u8 reserved_at_40[0x40];
e281682b
SM		 4943};
4944
5c50368f 4945struct mlx5_ifc_rqt_bitmask_bits {
b4ff3a36 4946 u8 reserved_at_0[0x20];
5c50368f 4947
b4ff3a36 4948 u8 reserved_at_20[0x1f];
5c50368f
AS		 4949 u8 rqn_list[0x1];
4950};
4951
e281682b
SM		 4952struct mlx5_ifc_modify_rqt_in_bits {
4953 u8 opcode[0x10];
b4ff3a36 4954 u8 reserved_at_10[0x10];
e281682b 4955
b4ff3a36 4956 u8 reserved_at_20[0x10];
e281682b
SM		 4957 u8 op_mod[0x10];
4958
b4ff3a36 4959 u8 reserved_at_40[0x8];
e281682b
SM		 4960 u8 rqtn[0x18];
4961
b4ff3a36 4962 u8 reserved_at_60[0x20];
e281682b 4963
5c50368f 4964 struct mlx5_ifc_rqt_bitmask_bits bitmask;
e281682b 4965
b4ff3a36 4966 u8 reserved_at_c0[0x40];
e281682b
SM		 4967
4968 struct mlx5_ifc_rqtc_bits ctx;
4969};
4970
4971struct mlx5_ifc_modify_rq_out_bits {
4972 u8 status[0x8];
b4ff3a36 4973 u8 reserved_at_8[0x18];
e281682b
SM		 4974
4975 u8 syndrome[0x20];
4976
b4ff3a36 4977 u8 reserved_at_40[0x40];
e281682b
SM		 4978};
4979
83b502a1
AV		 4980enum {
4981 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
4982 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID = 1ULL << 3,
4983};
4984
e281682b
SM		 4985struct mlx5_ifc_modify_rq_in_bits {
4986 u8 opcode[0x10];
b4ff3a36 4987 u8 reserved_at_10[0x10];
e281682b 4988
b4ff3a36 4989 u8 reserved_at_20[0x10];
e281682b
SM		 4990 u8 op_mod[0x10];
4991
4992 u8 rq_state[0x4];
b4ff3a36 4993 u8 reserved_at_44[0x4];
e281682b
SM		 4994 u8 rqn[0x18];
4995
b4ff3a36 4996 u8 reserved_at_60[0x20];
e281682b
SM		 4997
4998 u8 modify_bitmask[0x40];
4999
b4ff3a36 5000 u8 reserved_at_c0[0x40];
e281682b
SM		 5001
5002 struct mlx5_ifc_rqc_bits ctx;
5003};
5004
5005struct mlx5_ifc_modify_rmp_out_bits {
5006 u8 status[0x8];
b4ff3a36 5007 u8 reserved_at_8[0x18];
e281682b
SM		 5008
5009 u8 syndrome[0x20];
5010
b4ff3a36 5011 u8 reserved_at_40[0x40];
e281682b
SM		 5012};
5013
01949d01 5014struct mlx5_ifc_rmp_bitmask_bits {
b4ff3a36 5015 u8 reserved_at_0[0x20];
01949d01 5016
b4ff3a36 5017 u8 reserved_at_20[0x1f];
01949d01
HA		 5018 u8 lwm[0x1];
5019};
5020
e281682b
SM		 5021struct mlx5_ifc_modify_rmp_in_bits {
5022 u8 opcode[0x10];
b4ff3a36 5023 u8 reserved_at_10[0x10];
e281682b 5024
b4ff3a36 5025 u8 reserved_at_20[0x10];
e281682b
SM		 5026 u8 op_mod[0x10];
5027
5028 u8 rmp_state[0x4];
b4ff3a36 5029 u8 reserved_at_44[0x4];
e281682b
SM		 5030 u8 rmpn[0x18];
5031
b4ff3a36 5032 u8 reserved_at_60[0x20];
e281682b 5033
01949d01 5034 struct mlx5_ifc_rmp_bitmask_bits bitmask;
e281682b 5035
b4ff3a36 5036 u8 reserved_at_c0[0x40];
e281682b
SM		 5037
5038 struct mlx5_ifc_rmpc_bits ctx;
5039};
5040
5041struct mlx5_ifc_modify_nic_vport_context_out_bits {
5042 u8 status[0x8];
b4ff3a36 5043 u8 reserved_at_8[0x18];
e281682b
SM		 5044
5045 u8 syndrome[0x20];
5046
b4ff3a36 5047 u8 reserved_at_40[0x40];
e281682b
SM		 5048};
5049
5050struct mlx5_ifc_modify_nic_vport_field_select_bits {
23898c76
NO		 5051 u8 reserved_at_0[0x16];
5052 u8 node_guid[0x1];
5053 u8 port_guid[0x1];
9def7121 5054 u8 min_inline[0x1];
d82b7318
SM		 5055 u8 mtu[0x1];
5056 u8 change_event[0x1];
5057 u8 promisc[0x1];
e281682b
SM		 5058 u8 permanent_address[0x1];
5059 u8 addresses_list[0x1];
5060 u8 roce_en[0x1];
b4ff3a36 5061 u8 reserved_at_1f[0x1];
e281682b
SM		 5062};
5063
5064struct mlx5_ifc_modify_nic_vport_context_in_bits {
5065 u8 opcode[0x10];
b4ff3a36 5066 u8 reserved_at_10[0x10];
e281682b 5067
b4ff3a36 5068 u8 reserved_at_20[0x10];
e281682b
SM		 5069 u8 op_mod[0x10];
5070
5071 u8 other_vport[0x1];
b4ff3a36 5072 u8 reserved_at_41[0xf];
e281682b
SM		 5073 u8 vport_number[0x10];
5074
5075 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5076
b4ff3a36 5077 u8 reserved_at_80[0x780];
e281682b
SM		 5078
5079 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5080};
5081
5082struct mlx5_ifc_modify_hca_vport_context_out_bits {
5083 u8 status[0x8];
b4ff3a36 5084 u8 reserved_at_8[0x18];
e281682b
SM		 5085
5086 u8 syndrome[0x20];
5087
b4ff3a36 5088 u8 reserved_at_40[0x40];
e281682b
SM		 5089};
5090
5091struct mlx5_ifc_modify_hca_vport_context_in_bits {
5092 u8 opcode[0x10];
b4ff3a36 5093 u8 reserved_at_10[0x10];
e281682b 5094
b4ff3a36 5095 u8 reserved_at_20[0x10];
e281682b
SM		 5096 u8 op_mod[0x10];
5097
5098 u8 other_vport[0x1];
b4ff3a36 5099 u8 reserved_at_41[0xb];
707c4602 5100 u8 port_num[0x4];
e281682b
SM		 5101 u8 vport_number[0x10];
5102
b4ff3a36 5103 u8 reserved_at_60[0x20];
e281682b
SM		 5104
5105 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5106};
5107
5108struct mlx5_ifc_modify_cq_out_bits {
5109 u8 status[0x8];
b4ff3a36 5110 u8 reserved_at_8[0x18];
e281682b
SM		 5111
5112 u8 syndrome[0x20];
5113
b4ff3a36 5114 u8 reserved_at_40[0x40];
e281682b
SM		 5115};
5116
5117enum {
5118 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
5119 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
5120};
5121
5122struct mlx5_ifc_modify_cq_in_bits {
5123 u8 opcode[0x10];
b4ff3a36 5124 u8 reserved_at_10[0x10];
e281682b 5125
b4ff3a36 5126 u8 reserved_at_20[0x10];
e281682b
SM		 5127 u8 op_mod[0x10];
5128
b4ff3a36 5129 u8 reserved_at_40[0x8];
e281682b
SM		 5130 u8 cqn[0x18];
5131
5132 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5133
5134 struct mlx5_ifc_cqc_bits cq_context;
5135
b4ff3a36 5136 u8 reserved_at_280[0x600];
e281682b
SM		 5137
5138 u8 pas[0][0x40];
5139};
5140
5141struct mlx5_ifc_modify_cong_status_out_bits {
5142 u8 status[0x8];
b4ff3a36 5143 u8 reserved_at_8[0x18];
e281682b
SM		 5144
5145 u8 syndrome[0x20];
5146
b4ff3a36 5147 u8 reserved_at_40[0x40];
e281682b
SM		 5148};
5149
5150struct mlx5_ifc_modify_cong_status_in_bits {
5151 u8 opcode[0x10];
b4ff3a36 5152 u8 reserved_at_10[0x10];
e281682b 5153
b4ff3a36 5154 u8 reserved_at_20[0x10];
e281682b
SM		 5155 u8 op_mod[0x10];
5156
b4ff3a36 5157 u8 reserved_at_40[0x18];
e281682b
SM		 5158 u8 priority[0x4];
5159 u8 cong_protocol[0x4];
5160
5161 u8 enable[0x1];
5162 u8 tag_enable[0x1];
b4ff3a36 5163 u8 reserved_at_62[0x1e];
e281682b
SM		 5164};
5165
5166struct mlx5_ifc_modify_cong_params_out_bits {
5167 u8 status[0x8];
b4ff3a36 5168 u8 reserved_at_8[0x18];
e281682b
SM		 5169
5170 u8 syndrome[0x20];
5171
b4ff3a36 5172 u8 reserved_at_40[0x40];
e281682b
SM		 5173};
5174
5175struct mlx5_ifc_modify_cong_params_in_bits {
5176 u8 opcode[0x10];
b4ff3a36 5177 u8 reserved_at_10[0x10];
e281682b 5178
b4ff3a36 5179 u8 reserved_at_20[0x10];
e281682b
SM		 5180 u8 op_mod[0x10];
5181
b4ff3a36 5182 u8 reserved_at_40[0x1c];
e281682b
SM		 5183 u8 cong_protocol[0x4];
5184
5185 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5186
b4ff3a36 5187 u8 reserved_at_80[0x80];
e281682b
SM		 5188
5189 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5190};
5191
5192struct mlx5_ifc_manage_pages_out_bits {
5193 u8 status[0x8];
b4ff3a36 5194 u8 reserved_at_8[0x18];
e281682b
SM		 5195
5196 u8 syndrome[0x20];
5197
5198 u8 output_num_entries[0x20];
5199
b4ff3a36 5200 u8 reserved_at_60[0x20];
e281682b
SM		 5201
5202 u8 pas[0][0x40];
5203};
5204
5205enum {
5206 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
5207 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
5208 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
5209};
5210
5211struct mlx5_ifc_manage_pages_in_bits {
5212 u8 opcode[0x10];
b4ff3a36 5213 u8 reserved_at_10[0x10];
e281682b 5214
b4ff3a36 5215 u8 reserved_at_20[0x10];
e281682b
SM		 5216 u8 op_mod[0x10];
5217
b4ff3a36 5218 u8 reserved_at_40[0x10];
e281682b
SM		 5219 u8 function_id[0x10];
5220
5221 u8 input_num_entries[0x20];
5222
5223 u8 pas[0][0x40];
5224};
5225
5226struct mlx5_ifc_mad_ifc_out_bits {
5227 u8 status[0x8];
b4ff3a36 5228 u8 reserved_at_8[0x18];
e281682b
SM		 5229
5230 u8 syndrome[0x20];
5231
b4ff3a36 5232 u8 reserved_at_40[0x40];
e281682b
SM		 5233
5234 u8 response_mad_packet[256][0x8];
5235};
5236
5237struct mlx5_ifc_mad_ifc_in_bits {
5238 u8 opcode[0x10];
b4ff3a36 5239 u8 reserved_at_10[0x10];
e281682b 5240
b4ff3a36 5241 u8 reserved_at_20[0x10];
e281682b
SM		 5242 u8 op_mod[0x10];
5243
5244 u8 remote_lid[0x10];
b4ff3a36 5245 u8 reserved_at_50[0x8];
e281682b
SM		 5246 u8 port[0x8];
5247
b4ff3a36 5248 u8 reserved_at_60[0x20];
e281682b
SM		 5249
5250 u8 mad[256][0x8];
5251};
5252
5253struct mlx5_ifc_init_hca_out_bits {
5254 u8 status[0x8];
b4ff3a36 5255 u8 reserved_at_8[0x18];
e281682b
SM		 5256
5257 u8 syndrome[0x20];
5258
b4ff3a36 5259 u8 reserved_at_40[0x40];
e281682b
SM		 5260};
5261
5262struct mlx5_ifc_init_hca_in_bits {
5263 u8 opcode[0x10];
b4ff3a36 5264 u8 reserved_at_10[0x10];
e281682b 5265
b4ff3a36 5266 u8 reserved_at_20[0x10];
e281682b
SM		 5267 u8 op_mod[0x10];
5268
b4ff3a36 5269 u8 reserved_at_40[0x40];
e281682b
SM		 5270};
5271
5272struct mlx5_ifc_init2rtr_qp_out_bits {
5273 u8 status[0x8];
b4ff3a36 5274 u8 reserved_at_8[0x18];
e281682b
SM		 5275
5276 u8 syndrome[0x20];
5277
b4ff3a36 5278 u8 reserved_at_40[0x40];
e281682b
SM		 5279};
5280
5281struct mlx5_ifc_init2rtr_qp_in_bits {
5282 u8 opcode[0x10];
b4ff3a36 5283 u8 reserved_at_10[0x10];
e281682b 5284
b4ff3a36 5285 u8 reserved_at_20[0x10];
e281682b
SM		 5286 u8 op_mod[0x10];
5287
b4ff3a36 5288 u8 reserved_at_40[0x8];
e281682b
SM		 5289 u8 qpn[0x18];
5290
b4ff3a36 5291 u8 reserved_at_60[0x20];
e281682b
SM		 5292
5293 u8 opt_param_mask[0x20];
5294
b4ff3a36 5295 u8 reserved_at_a0[0x20];
e281682b
SM		 5296
5297 struct mlx5_ifc_qpc_bits qpc;
5298
b4ff3a36 5299 u8 reserved_at_800[0x80];
e281682b
SM		 5300};
5301
5302struct mlx5_ifc_init2init_qp_out_bits {
5303 u8 status[0x8];
b4ff3a36 5304 u8 reserved_at_8[0x18];
e281682b
SM		 5305
5306 u8 syndrome[0x20];
5307
b4ff3a36 5308 u8 reserved_at_40[0x40];
e281682b
SM		 5309};
5310
5311struct mlx5_ifc_init2init_qp_in_bits {
5312 u8 opcode[0x10];
b4ff3a36 5313 u8 reserved_at_10[0x10];
e281682b 5314
b4ff3a36 5315 u8 reserved_at_20[0x10];
e281682b
SM		 5316 u8 op_mod[0x10];
5317
b4ff3a36 5318 u8 reserved_at_40[0x8];
e281682b
SM		 5319 u8 qpn[0x18];
5320
b4ff3a36 5321 u8 reserved_at_60[0x20];
e281682b
SM		 5322
5323 u8 opt_param_mask[0x20];
5324
b4ff3a36 5325 u8 reserved_at_a0[0x20];
e281682b
SM		 5326
5327 struct mlx5_ifc_qpc_bits qpc;
5328
b4ff3a36 5329 u8 reserved_at_800[0x80];
e281682b
SM		 5330};
5331
5332struct mlx5_ifc_get_dropped_packet_log_out_bits {
5333 u8 status[0x8];
b4ff3a36 5334 u8 reserved_at_8[0x18];
e281682b
SM		 5335
5336 u8 syndrome[0x20];
5337
b4ff3a36 5338 u8 reserved_at_40[0x40];
e281682b
SM		 5339
5340 u8 packet_headers_log[128][0x8];
5341
5342 u8 packet_syndrome[64][0x8];
5343};
5344
5345struct mlx5_ifc_get_dropped_packet_log_in_bits {
5346 u8 opcode[0x10];
b4ff3a36 5347 u8 reserved_at_10[0x10];
e281682b 5348
b4ff3a36 5349 u8 reserved_at_20[0x10];
e281682b
SM		 5350 u8 op_mod[0x10];
5351
b4ff3a36 5352 u8 reserved_at_40[0x40];
e281682b
SM		 5353};
5354
5355struct mlx5_ifc_gen_eqe_in_bits {
5356 u8 opcode[0x10];
b4ff3a36 5357 u8 reserved_at_10[0x10];
e281682b 5358
b4ff3a36 5359 u8 reserved_at_20[0x10];
e281682b
SM		 5360 u8 op_mod[0x10];
5361
b4ff3a36 5362 u8 reserved_at_40[0x18];
e281682b
SM		 5363 u8 eq_number[0x8];
5364
b4ff3a36 5365 u8 reserved_at_60[0x20];
e281682b
SM		 5366
5367 u8 eqe[64][0x8];
5368};
5369
5370struct mlx5_ifc_gen_eq_out_bits {
5371 u8 status[0x8];
b4ff3a36 5372 u8 reserved_at_8[0x18];
e281682b
SM		 5373
5374 u8 syndrome[0x20];
5375
b4ff3a36 5376 u8 reserved_at_40[0x40];
e281682b
SM		 5377};
5378
5379struct mlx5_ifc_enable_hca_out_bits {
5380 u8 status[0x8];
b4ff3a36 5381 u8 reserved_at_8[0x18];
e281682b
SM		 5382
5383 u8 syndrome[0x20];
5384
b4ff3a36 5385 u8 reserved_at_40[0x20];
e281682b
SM		 5386};
5387
5388struct mlx5_ifc_enable_hca_in_bits {
5389 u8 opcode[0x10];
b4ff3a36 5390 u8 reserved_at_10[0x10];
e281682b 5391
b4ff3a36 5392 u8 reserved_at_20[0x10];
e281682b
SM		 5393 u8 op_mod[0x10];
5394
b4ff3a36 5395 u8 reserved_at_40[0x10];
e281682b
SM		 5396 u8 function_id[0x10];
5397
b4ff3a36 5398 u8 reserved_at_60[0x20];
e281682b
SM		 5399};
5400
5401struct mlx5_ifc_drain_dct_out_bits {
5402 u8 status[0x8];
b4ff3a36 5403 u8 reserved_at_8[0x18];
e281682b
SM		 5404
5405 u8 syndrome[0x20];
5406
b4ff3a36 5407 u8 reserved_at_40[0x40];
e281682b
SM		 5408};
5409
5410struct mlx5_ifc_drain_dct_in_bits {
5411 u8 opcode[0x10];
b4ff3a36 5412 u8 reserved_at_10[0x10];
e281682b 5413
b4ff3a36 5414 u8 reserved_at_20[0x10];
e281682b
SM		 5415 u8 op_mod[0x10];
5416
b4ff3a36 5417 u8 reserved_at_40[0x8];
e281682b
SM		 5418 u8 dctn[0x18];
5419
b4ff3a36 5420 u8 reserved_at_60[0x20];
e281682b
SM		 5421};
5422
5423struct mlx5_ifc_disable_hca_out_bits {
5424 u8 status[0x8];
b4ff3a36 5425 u8 reserved_at_8[0x18];
e281682b
SM		 5426
5427 u8 syndrome[0x20];
5428
b4ff3a36 5429 u8 reserved_at_40[0x20];
e281682b
SM		 5430};
5431
5432struct mlx5_ifc_disable_hca_in_bits {
5433 u8 opcode[0x10];
b4ff3a36 5434 u8 reserved_at_10[0x10];
e281682b 5435
b4ff3a36 5436 u8 reserved_at_20[0x10];
e281682b
SM		 5437 u8 op_mod[0x10];
5438
b4ff3a36 5439 u8 reserved_at_40[0x10];
e281682b
SM		 5440 u8 function_id[0x10];
5441
b4ff3a36 5442 u8 reserved_at_60[0x20];
e281682b
SM		 5443};
5444
5445struct mlx5_ifc_detach_from_mcg_out_bits {
5446 u8 status[0x8];
b4ff3a36 5447 u8 reserved_at_8[0x18];
e281682b
SM		 5448
5449 u8 syndrome[0x20];
5450
b4ff3a36 5451 u8 reserved_at_40[0x40];
e281682b
SM		 5452};
5453
5454struct mlx5_ifc_detach_from_mcg_in_bits {
5455 u8 opcode[0x10];
b4ff3a36 5456 u8 reserved_at_10[0x10];
e281682b 5457
b4ff3a36 5458 u8 reserved_at_20[0x10];
e281682b
SM		 5459 u8 op_mod[0x10];
5460
b4ff3a36 5461 u8 reserved_at_40[0x8];
e281682b
SM		 5462 u8 qpn[0x18];
5463
b4ff3a36 5464 u8 reserved_at_60[0x20];
e281682b
SM		 5465
5466 u8 multicast_gid[16][0x8];
5467};
5468
7486216b
SM		 5469struct mlx5_ifc_destroy_xrq_out_bits {
5470 u8 status[0x8];
5471 u8 reserved_at_8[0x18];
5472
5473 u8 syndrome[0x20];
5474
5475 u8 reserved_at_40[0x40];
5476};
5477
5478struct mlx5_ifc_destroy_xrq_in_bits {
5479 u8 opcode[0x10];
5480 u8 reserved_at_10[0x10];
5481
5482 u8 reserved_at_20[0x10];
5483 u8 op_mod[0x10];
5484
5485 u8 reserved_at_40[0x8];
5486 u8 xrqn[0x18];
5487
5488 u8 reserved_at_60[0x20];
5489};
5490
e281682b
SM		 5491struct mlx5_ifc_destroy_xrc_srq_out_bits {
5492 u8 status[0x8];
b4ff3a36 5493 u8 reserved_at_8[0x18];
e281682b
SM		 5494
5495 u8 syndrome[0x20];
5496
b4ff3a36 5497 u8 reserved_at_40[0x40];
e281682b
SM		 5498};
5499
5500struct mlx5_ifc_destroy_xrc_srq_in_bits {
5501 u8 opcode[0x10];
b4ff3a36 5502 u8 reserved_at_10[0x10];
e281682b 5503
b4ff3a36 5504 u8 reserved_at_20[0x10];
e281682b
SM		 5505 u8 op_mod[0x10];
5506
b4ff3a36 5507 u8 reserved_at_40[0x8];
e281682b
SM		 5508 u8 xrc_srqn[0x18];
5509
b4ff3a36 5510 u8 reserved_at_60[0x20];
e281682b
SM		 5511};
5512
5513struct mlx5_ifc_destroy_tis_out_bits {
5514 u8 status[0x8];
b4ff3a36 5515 u8 reserved_at_8[0x18];
e281682b
SM		 5516
5517 u8 syndrome[0x20];
5518
b4ff3a36 5519 u8 reserved_at_40[0x40];
e281682b
SM		 5520};
5521
5522struct mlx5_ifc_destroy_tis_in_bits {
5523 u8 opcode[0x10];
b4ff3a36 5524 u8 reserved_at_10[0x10];
e281682b 5525
b4ff3a36 5526 u8 reserved_at_20[0x10];
e281682b
SM		 5527 u8 op_mod[0x10];
5528
b4ff3a36 5529 u8 reserved_at_40[0x8];
e281682b
SM		 5530 u8 tisn[0x18];
5531
b4ff3a36 5532 u8 reserved_at_60[0x20];
e281682b
SM		 5533};
5534
5535struct mlx5_ifc_destroy_tir_out_bits {
5536 u8 status[0x8];
b4ff3a36 5537 u8 reserved_at_8[0x18];
e281682b
SM		 5538
5539 u8 syndrome[0x20];
5540
b4ff3a36 5541 u8 reserved_at_40[0x40];
e281682b
SM		 5542};
5543
5544struct mlx5_ifc_destroy_tir_in_bits {
5545 u8 opcode[0x10];
b4ff3a36 5546 u8 reserved_at_10[0x10];
e281682b 5547
b4ff3a36 5548 u8 reserved_at_20[0x10];
e281682b
SM		 5549 u8 op_mod[0x10];
5550
b4ff3a36 5551 u8 reserved_at_40[0x8];
e281682b
SM		 5552 u8 tirn[0x18];
5553
b4ff3a36 5554 u8 reserved_at_60[0x20];
e281682b
SM		 5555};
5556
5557struct mlx5_ifc_destroy_srq_out_bits {
5558 u8 status[0x8];
b4ff3a36 5559 u8 reserved_at_8[0x18];
e281682b
SM		 5560
5561 u8 syndrome[0x20];
5562
b4ff3a36 5563 u8 reserved_at_40[0x40];
e281682b
SM		 5564};
5565
5566struct mlx5_ifc_destroy_srq_in_bits {
5567 u8 opcode[0x10];
b4ff3a36 5568 u8 reserved_at_10[0x10];
e281682b 5569
b4ff3a36 5570 u8 reserved_at_20[0x10];
e281682b
SM		 5571 u8 op_mod[0x10];
5572
b4ff3a36 5573 u8 reserved_at_40[0x8];
e281682b
SM		 5574 u8 srqn[0x18];
5575
b4ff3a36 5576 u8 reserved_at_60[0x20];
e281682b
SM		 5577};
5578
5579struct mlx5_ifc_destroy_sq_out_bits {
5580 u8 status[0x8];
b4ff3a36 5581 u8 reserved_at_8[0x18];
e281682b
SM		 5582
5583 u8 syndrome[0x20];
5584
b4ff3a36 5585 u8 reserved_at_40[0x40];
e281682b
SM		 5586};
5587
5588struct mlx5_ifc_destroy_sq_in_bits {
5589 u8 opcode[0x10];
b4ff3a36 5590 u8 reserved_at_10[0x10];
e281682b 5591
b4ff3a36 5592 u8 reserved_at_20[0x10];
e281682b
SM		 5593 u8 op_mod[0x10];
5594
b4ff3a36 5595 u8 reserved_at_40[0x8];
e281682b
SM		 5596 u8 sqn[0x18];
5597
b4ff3a36 5598 u8 reserved_at_60[0x20];
e281682b
SM		 5599};
5600
813f8540
MHY		 5601struct mlx5_ifc_destroy_scheduling_element_out_bits {
5602 u8 status[0x8];
5603 u8 reserved_at_8[0x18];
5604
5605 u8 syndrome[0x20];
5606
5607 u8 reserved_at_40[0x1c0];
5608};
5609
5610struct mlx5_ifc_destroy_scheduling_element_in_bits {
5611 u8 opcode[0x10];
5612 u8 reserved_at_10[0x10];
5613
5614 u8 reserved_at_20[0x10];
5615 u8 op_mod[0x10];
5616
5617 u8 scheduling_hierarchy[0x8];
5618 u8 reserved_at_48[0x18];
5619
5620 u8 scheduling_element_id[0x20];
5621
5622 u8 reserved_at_80[0x180];
5623};
5624
e281682b
SM		 5625struct mlx5_ifc_destroy_rqt_out_bits {
5626 u8 status[0x8];
b4ff3a36 5627 u8 reserved_at_8[0x18];
e281682b
SM		 5628
5629 u8 syndrome[0x20];
5630
b4ff3a36 5631 u8 reserved_at_40[0x40];
e281682b
SM		 5632};
5633
5634struct mlx5_ifc_destroy_rqt_in_bits {
5635 u8 opcode[0x10];
b4ff3a36 5636 u8 reserved_at_10[0x10];
e281682b 5637
b4ff3a36 5638 u8 reserved_at_20[0x10];
e281682b
SM		 5639 u8 op_mod[0x10];
5640
b4ff3a36 5641 u8 reserved_at_40[0x8];
e281682b
SM		 5642 u8 rqtn[0x18];
5643
b4ff3a36 5644 u8 reserved_at_60[0x20];
e281682b
SM		 5645};
5646
5647struct mlx5_ifc_destroy_rq_out_bits {
5648 u8 status[0x8];
b4ff3a36 5649 u8 reserved_at_8[0x18];
e281682b
SM		 5650
5651 u8 syndrome[0x20];
5652
b4ff3a36 5653 u8 reserved_at_40[0x40];
e281682b
SM		 5654};
5655
5656struct mlx5_ifc_destroy_rq_in_bits {
5657 u8 opcode[0x10];
b4ff3a36 5658 u8 reserved_at_10[0x10];
e281682b 5659
b4ff3a36 5660 u8 reserved_at_20[0x10];
e281682b
SM		 5661 u8 op_mod[0x10];
5662
b4ff3a36 5663 u8 reserved_at_40[0x8];
e281682b
SM		 5664 u8 rqn[0x18];
5665
b4ff3a36 5666 u8 reserved_at_60[0x20];
e281682b
SM		 5667};
5668
5669struct mlx5_ifc_destroy_rmp_out_bits {
5670 u8 status[0x8];
b4ff3a36 5671 u8 reserved_at_8[0x18];
e281682b
SM		 5672
5673 u8 syndrome[0x20];
5674
b4ff3a36 5675 u8 reserved_at_40[0x40];
e281682b
SM		 5676};
5677
5678struct mlx5_ifc_destroy_rmp_in_bits {
5679 u8 opcode[0x10];
b4ff3a36 5680 u8 reserved_at_10[0x10];
e281682b 5681
b4ff3a36 5682 u8 reserved_at_20[0x10];
e281682b
SM		 5683 u8 op_mod[0x10];
5684
b4ff3a36 5685 u8 reserved_at_40[0x8];
e281682b
SM		 5686 u8 rmpn[0x18];
5687
b4ff3a36 5688 u8 reserved_at_60[0x20];
e281682b
SM		 5689};
5690
5691struct mlx5_ifc_destroy_qp_out_bits {
5692 u8 status[0x8];
b4ff3a36 5693 u8 reserved_at_8[0x18];
e281682b
SM		 5694
5695 u8 syndrome[0x20];
5696
b4ff3a36 5697 u8 reserved_at_40[0x40];
e281682b
SM		 5698};
5699
5700struct mlx5_ifc_destroy_qp_in_bits {
5701 u8 opcode[0x10];
b4ff3a36 5702 u8 reserved_at_10[0x10];
e281682b 5703
b4ff3a36 5704 u8 reserved_at_20[0x10];
e281682b
SM		 5705 u8 op_mod[0x10];
5706
b4ff3a36 5707 u8 reserved_at_40[0x8];
e281682b
SM		 5708 u8 qpn[0x18];
5709
b4ff3a36 5710 u8 reserved_at_60[0x20];
e281682b
SM		 5711};
5712
5713struct mlx5_ifc_destroy_psv_out_bits {
5714 u8 status[0x8];
b4ff3a36 5715 u8 reserved_at_8[0x18];
e281682b
SM		 5716
5717 u8 syndrome[0x20];
5718
b4ff3a36 5719 u8 reserved_at_40[0x40];
e281682b
SM		 5720};
5721
5722struct mlx5_ifc_destroy_psv_in_bits {
5723 u8 opcode[0x10];
b4ff3a36 5724 u8 reserved_at_10[0x10];
e281682b 5725
b4ff3a36 5726 u8 reserved_at_20[0x10];
e281682b
SM		 5727 u8 op_mod[0x10];
5728
b4ff3a36 5729 u8 reserved_at_40[0x8];
e281682b
SM		 5730 u8 psvn[0x18];
5731
b4ff3a36 5732 u8 reserved_at_60[0x20];
e281682b
SM		 5733};
5734
5735struct mlx5_ifc_destroy_mkey_out_bits {
5736 u8 status[0x8];
b4ff3a36 5737 u8 reserved_at_8[0x18];
e281682b
SM		 5738
5739 u8 syndrome[0x20];
5740
b4ff3a36 5741 u8 reserved_at_40[0x40];
e281682b
SM		 5742};
5743
5744struct mlx5_ifc_destroy_mkey_in_bits {
5745 u8 opcode[0x10];
b4ff3a36 5746 u8 reserved_at_10[0x10];
e281682b 5747
b4ff3a36 5748 u8 reserved_at_20[0x10];
e281682b
SM		 5749 u8 op_mod[0x10];
5750
b4ff3a36 5751 u8 reserved_at_40[0x8];
e281682b
SM		 5752 u8 mkey_index[0x18];
5753
b4ff3a36 5754 u8 reserved_at_60[0x20];
e281682b
SM		 5755};
5756
5757struct mlx5_ifc_destroy_flow_table_out_bits {
5758 u8 status[0x8];
b4ff3a36 5759 u8 reserved_at_8[0x18];
e281682b
SM		 5760
5761 u8 syndrome[0x20];
5762
b4ff3a36 5763 u8 reserved_at_40[0x40];
e281682b
SM		 5764};
5765
5766struct mlx5_ifc_destroy_flow_table_in_bits {
5767 u8 opcode[0x10];
b4ff3a36 5768 u8 reserved_at_10[0x10];
e281682b 5769
b4ff3a36 5770 u8 reserved_at_20[0x10];
e281682b
SM		 5771 u8 op_mod[0x10];
5772
7d5e1423
SM		 5773 u8 other_vport[0x1];
5774 u8 reserved_at_41[0xf];
5775 u8 vport_number[0x10];
5776
5777 u8 reserved_at_60[0x20];
e281682b
SM		 5778
5779 u8 table_type[0x8];
b4ff3a36 5780 u8 reserved_at_88[0x18];
e281682b 5781
b4ff3a36 5782 u8 reserved_at_a0[0x8];
e281682b
SM		 5783 u8 table_id[0x18];
5784
b4ff3a36 5785 u8 reserved_at_c0[0x140];
e281682b
SM		 5786};
5787
5788struct mlx5_ifc_destroy_flow_group_out_bits {
5789 u8 status[0x8];
b4ff3a36 5790 u8 reserved_at_8[0x18];
e281682b
SM		 5791
5792 u8 syndrome[0x20];
5793
b4ff3a36 5794 u8 reserved_at_40[0x40];
e281682b
SM		 5795};
5796
5797struct mlx5_ifc_destroy_flow_group_in_bits {
5798 u8 opcode[0x10];
b4ff3a36 5799 u8 reserved_at_10[0x10];
e281682b 5800
b4ff3a36 5801 u8 reserved_at_20[0x10];
e281682b
SM		 5802 u8 op_mod[0x10];
5803
7d5e1423
SM		 5804 u8 other_vport[0x1];
5805 u8 reserved_at_41[0xf];
5806 u8 vport_number[0x10];
5807
5808 u8 reserved_at_60[0x20];
e281682b
SM		 5809
5810 u8 table_type[0x8];
b4ff3a36 5811 u8 reserved_at_88[0x18];
e281682b 5812
b4ff3a36 5813 u8 reserved_at_a0[0x8];
e281682b
SM		 5814 u8 table_id[0x18];
5815
5816 u8 group_id[0x20];
5817
b4ff3a36 5818 u8 reserved_at_e0[0x120];
e281682b
SM		 5819};
5820
5821struct mlx5_ifc_destroy_eq_out_bits {
5822 u8 status[0x8];
b4ff3a36 5823 u8 reserved_at_8[0x18];
e281682b
SM		 5824
5825 u8 syndrome[0x20];
5826
b4ff3a36 5827 u8 reserved_at_40[0x40];
e281682b
SM		 5828};
5829
5830struct mlx5_ifc_destroy_eq_in_bits {
5831 u8 opcode[0x10];
b4ff3a36 5832 u8 reserved_at_10[0x10];
e281682b 5833
b4ff3a36 5834 u8 reserved_at_20[0x10];
e281682b
SM		 5835 u8 op_mod[0x10];
5836
b4ff3a36 5837 u8 reserved_at_40[0x18];
e281682b
SM		 5838 u8 eq_number[0x8];
5839
b4ff3a36 5840 u8 reserved_at_60[0x20];
e281682b
SM		 5841};
5842
5843struct mlx5_ifc_destroy_dct_out_bits {
5844 u8 status[0x8];
b4ff3a36 5845 u8 reserved_at_8[0x18];
e281682b
SM		 5846
5847 u8 syndrome[0x20];
5848
b4ff3a36 5849 u8 reserved_at_40[0x40];
e281682b
SM		 5850};
5851
5852struct mlx5_ifc_destroy_dct_in_bits {
5853 u8 opcode[0x10];
b4ff3a36 5854 u8 reserved_at_10[0x10];
e281682b 5855
b4ff3a36 5856 u8 reserved_at_20[0x10];
e281682b
SM		 5857 u8 op_mod[0x10];
5858
b4ff3a36 5859 u8 reserved_at_40[0x8];
e281682b
SM		 5860 u8 dctn[0x18];
5861
b4ff3a36 5862 u8 reserved_at_60[0x20];
e281682b
SM		 5863};
5864
5865struct mlx5_ifc_destroy_cq_out_bits {
5866 u8 status[0x8];
b4ff3a36 5867 u8 reserved_at_8[0x18];
e281682b
SM		 5868
5869 u8 syndrome[0x20];
5870
b4ff3a36 5871 u8 reserved_at_40[0x40];
e281682b
SM		 5872};
5873
5874struct mlx5_ifc_destroy_cq_in_bits {
5875 u8 opcode[0x10];
b4ff3a36 5876 u8 reserved_at_10[0x10];
e281682b 5877
b4ff3a36 5878 u8 reserved_at_20[0x10];
e281682b
SM		 5879 u8 op_mod[0x10];
5880
b4ff3a36 5881 u8 reserved_at_40[0x8];
e281682b
SM		 5882 u8 cqn[0x18];
5883
b4ff3a36 5884 u8 reserved_at_60[0x20];
e281682b
SM		 5885};
5886
5887struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
5888 u8 status[0x8];
b4ff3a36 5889 u8 reserved_at_8[0x18];
e281682b
SM		 5890
5891 u8 syndrome[0x20];
5892
b4ff3a36 5893 u8 reserved_at_40[0x40];
e281682b
SM		 5894};
5895
5896struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
5897 u8 opcode[0x10];
b4ff3a36 5898 u8 reserved_at_10[0x10];
e281682b 5899
b4ff3a36 5900 u8 reserved_at_20[0x10];
e281682b
SM		 5901 u8 op_mod[0x10];
5902
b4ff3a36 5903 u8 reserved_at_40[0x20];
e281682b 5904
b4ff3a36 5905 u8 reserved_at_60[0x10];
e281682b
SM		 5906 u8 vxlan_udp_port[0x10];
5907};
5908
5909struct mlx5_ifc_delete_l2_table_entry_out_bits {
5910 u8 status[0x8];
b4ff3a36 5911 u8 reserved_at_8[0x18];
e281682b
SM		 5912
5913 u8 syndrome[0x20];
5914
b4ff3a36 5915 u8 reserved_at_40[0x40];
e281682b
SM		 5916};
5917
5918struct mlx5_ifc_delete_l2_table_entry_in_bits {
5919 u8 opcode[0x10];
b4ff3a36 5920 u8 reserved_at_10[0x10];
e281682b 5921
b4ff3a36 5922 u8 reserved_at_20[0x10];
e281682b
SM		 5923 u8 op_mod[0x10];
5924
b4ff3a36 5925 u8 reserved_at_40[0x60];
e281682b 5926
b4ff3a36 5927 u8 reserved_at_a0[0x8];
e281682b
SM		 5928 u8 table_index[0x18];
5929
b4ff3a36 5930 u8 reserved_at_c0[0x140];
e281682b
SM		 5931};
5932
5933struct mlx5_ifc_delete_fte_out_bits {
5934 u8 status[0x8];
b4ff3a36 5935 u8 reserved_at_8[0x18];
e281682b
SM		 5936
5937 u8 syndrome[0x20];
5938
b4ff3a36 5939 u8 reserved_at_40[0x40];
e281682b
SM		 5940};
5941
5942struct mlx5_ifc_delete_fte_in_bits {
5943 u8 opcode[0x10];
b4ff3a36 5944 u8 reserved_at_10[0x10];
e281682b 5945
b4ff3a36 5946 u8 reserved_at_20[0x10];
e281682b
SM		 5947 u8 op_mod[0x10];
5948
7d5e1423
SM		 5949 u8 other_vport[0x1];
5950 u8 reserved_at_41[0xf];
5951 u8 vport_number[0x10];
5952
5953 u8 reserved_at_60[0x20];
e281682b
SM		 5954
5955 u8 table_type[0x8];
b4ff3a36 5956 u8 reserved_at_88[0x18];
e281682b 5957
b4ff3a36 5958 u8 reserved_at_a0[0x8];
e281682b
SM		 5959 u8 table_id[0x18];
5960
b4ff3a36 5961 u8 reserved_at_c0[0x40];
e281682b
SM		 5962
5963 u8 flow_index[0x20];
5964
b4ff3a36 5965 u8 reserved_at_120[0xe0];
e281682b
SM		 5966};
5967
5968struct mlx5_ifc_dealloc_xrcd_out_bits {
5969 u8 status[0x8];
b4ff3a36 5970 u8 reserved_at_8[0x18];
e281682b
SM		 5971
5972 u8 syndrome[0x20];
5973
b4ff3a36 5974 u8 reserved_at_40[0x40];
e281682b
SM		 5975};
5976
5977struct mlx5_ifc_dealloc_xrcd_in_bits {
5978 u8 opcode[0x10];
b4ff3a36 5979 u8 reserved_at_10[0x10];
e281682b 5980
b4ff3a36 5981 u8 reserved_at_20[0x10];
e281682b
SM		 5982 u8 op_mod[0x10];
5983
b4ff3a36 5984 u8 reserved_at_40[0x8];
e281682b
SM		 5985 u8 xrcd[0x18];
5986
b4ff3a36 5987 u8 reserved_at_60[0x20];
e281682b
SM		 5988};
5989
5990struct mlx5_ifc_dealloc_uar_out_bits {
5991 u8 status[0x8];
b4ff3a36 5992 u8 reserved_at_8[0x18];
e281682b
SM		 5993
5994 u8 syndrome[0x20];
5995
b4ff3a36 5996 u8 reserved_at_40[0x40];
e281682b
SM		 5997};
5998
5999struct mlx5_ifc_dealloc_uar_in_bits {
6000 u8 opcode[0x10];
b4ff3a36 6001 u8 reserved_at_10[0x10];
e281682b 6002
b4ff3a36 6003 u8 reserved_at_20[0x10];
e281682b
SM		 6004 u8 op_mod[0x10];
6005
b4ff3a36 6006 u8 reserved_at_40[0x8];
e281682b
SM		 6007 u8 uar[0x18];
6008
b4ff3a36 6009 u8 reserved_at_60[0x20];
e281682b
SM		 6010};
6011
6012struct mlx5_ifc_dealloc_transport_domain_out_bits {
6013 u8 status[0x8];
b4ff3a36 6014 u8 reserved_at_8[0x18];
e281682b
SM		 6015
6016 u8 syndrome[0x20];
6017
b4ff3a36 6018 u8 reserved_at_40[0x40];
e281682b
SM		 6019};
6020
6021struct mlx5_ifc_dealloc_transport_domain_in_bits {
6022 u8 opcode[0x10];
b4ff3a36 6023 u8 reserved_at_10[0x10];
e281682b 6024
b4ff3a36 6025 u8 reserved_at_20[0x10];
e281682b
SM		 6026 u8 op_mod[0x10];
6027
b4ff3a36 6028 u8 reserved_at_40[0x8];
e281682b
SM		 6029 u8 transport_domain[0x18];
6030
b4ff3a36 6031 u8 reserved_at_60[0x20];
e281682b
SM		 6032};
6033
6034struct mlx5_ifc_dealloc_q_counter_out_bits {
6035 u8 status[0x8];
b4ff3a36 6036 u8 reserved_at_8[0x18];
e281682b
SM		 6037
6038 u8 syndrome[0x20];
6039
b4ff3a36 6040 u8 reserved_at_40[0x40];
e281682b
SM		 6041};
6042
6043struct mlx5_ifc_dealloc_q_counter_in_bits {
6044 u8 opcode[0x10];
b4ff3a36 6045 u8 reserved_at_10[0x10];
e281682b 6046
b4ff3a36 6047 u8 reserved_at_20[0x10];
e281682b
SM		 6048 u8 op_mod[0x10];
6049
b4ff3a36 6050 u8 reserved_at_40[0x18];
e281682b
SM		 6051 u8 counter_set_id[0x8];
6052
b4ff3a36 6053 u8 reserved_at_60[0x20];
e281682b
SM		 6054};
6055
6056struct mlx5_ifc_dealloc_pd_out_bits {
6057 u8 status[0x8];
b4ff3a36 6058 u8 reserved_at_8[0x18];
e281682b
SM		 6059
6060 u8 syndrome[0x20];
6061
b4ff3a36 6062 u8 reserved_at_40[0x40];
e281682b
SM		 6063};
6064
6065struct mlx5_ifc_dealloc_pd_in_bits {
6066 u8 opcode[0x10];
b4ff3a36 6067 u8 reserved_at_10[0x10];
e281682b 6068
b4ff3a36 6069 u8 reserved_at_20[0x10];
e281682b
SM		 6070 u8 op_mod[0x10];
6071
b4ff3a36 6072 u8 reserved_at_40[0x8];
e281682b
SM		 6073 u8 pd[0x18];
6074
b4ff3a36 6075 u8 reserved_at_60[0x20];
e281682b
SM		 6076};
6077
9dc0b289
AV		 6078struct mlx5_ifc_dealloc_flow_counter_out_bits {
6079 u8 status[0x8];
6080 u8 reserved_at_8[0x18];
6081
6082 u8 syndrome[0x20];
6083
6084 u8 reserved_at_40[0x40];
6085};
6086
6087struct mlx5_ifc_dealloc_flow_counter_in_bits {
6088 u8 opcode[0x10];
6089 u8 reserved_at_10[0x10];
6090
6091 u8 reserved_at_20[0x10];
6092 u8 op_mod[0x10];
6093
6094 u8 reserved_at_40[0x10];
6095 u8 flow_counter_id[0x10];
6096
6097 u8 reserved_at_60[0x20];
6098};
6099
7486216b
SM		 6100struct mlx5_ifc_create_xrq_out_bits {
6101 u8 status[0x8];
6102 u8 reserved_at_8[0x18];
6103
6104 u8 syndrome[0x20];
6105
6106 u8 reserved_at_40[0x8];
6107 u8 xrqn[0x18];
6108
6109 u8 reserved_at_60[0x20];
6110};
6111
6112struct mlx5_ifc_create_xrq_in_bits {
6113 u8 opcode[0x10];
6114 u8 reserved_at_10[0x10];
6115
6116 u8 reserved_at_20[0x10];
6117 u8 op_mod[0x10];
6118
6119 u8 reserved_at_40[0x40];
6120
6121 struct mlx5_ifc_xrqc_bits xrq_context;
6122};
6123
e281682b
SM		 6124struct mlx5_ifc_create_xrc_srq_out_bits {
6125 u8 status[0x8];
b4ff3a36 6126 u8 reserved_at_8[0x18];
e281682b
SM		 6127
6128 u8 syndrome[0x20];
6129
b4ff3a36 6130 u8 reserved_at_40[0x8];
e281682b
SM		 6131 u8 xrc_srqn[0x18];
6132
b4ff3a36 6133 u8 reserved_at_60[0x20];
e281682b
SM		 6134};
6135
6136struct mlx5_ifc_create_xrc_srq_in_bits {
6137 u8 opcode[0x10];
b4ff3a36 6138 u8 reserved_at_10[0x10];
e281682b 6139
b4ff3a36 6140 u8 reserved_at_20[0x10];
e281682b
SM		 6141 u8 op_mod[0x10];
6142
b4ff3a36 6143 u8 reserved_at_40[0x40];
e281682b
SM		 6144
6145 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6146
b4ff3a36 6147 u8 reserved_at_280[0x600];
e281682b
SM		 6148
6149 u8 pas[0][0x40];
6150};
6151
6152struct mlx5_ifc_create_tis_out_bits {
6153 u8 status[0x8];
b4ff3a36 6154 u8 reserved_at_8[0x18];
e281682b
SM		 6155
6156 u8 syndrome[0x20];
6157
b4ff3a36 6158 u8 reserved_at_40[0x8];
e281682b
SM		 6159 u8 tisn[0x18];
6160
b4ff3a36 6161 u8 reserved_at_60[0x20];
e281682b
SM		 6162};
6163
6164struct mlx5_ifc_create_tis_in_bits {
6165 u8 opcode[0x10];
b4ff3a36 6166 u8 reserved_at_10[0x10];
e281682b 6167
b4ff3a36 6168 u8 reserved_at_20[0x10];
e281682b
SM		 6169 u8 op_mod[0x10];
6170
b4ff3a36 6171 u8 reserved_at_40[0xc0];
e281682b
SM		 6172
6173 struct mlx5_ifc_tisc_bits ctx;
6174};
6175
6176struct mlx5_ifc_create_tir_out_bits {
6177 u8 status[0x8];
b4ff3a36 6178 u8 reserved_at_8[0x18];
e281682b
SM		 6179
6180 u8 syndrome[0x20];
6181
b4ff3a36 6182 u8 reserved_at_40[0x8];
e281682b
SM		 6183 u8 tirn[0x18];
6184
b4ff3a36 6185 u8 reserved_at_60[0x20];
e281682b
SM		 6186};
6187
6188struct mlx5_ifc_create_tir_in_bits {
6189 u8 opcode[0x10];
b4ff3a36 6190 u8 reserved_at_10[0x10];
e281682b 6191
b4ff3a36 6192 u8 reserved_at_20[0x10];
e281682b
SM		 6193 u8 op_mod[0x10];
6194
b4ff3a36 6195 u8 reserved_at_40[0xc0];
e281682b
SM		 6196
6197 struct mlx5_ifc_tirc_bits ctx;
6198};
6199
6200struct mlx5_ifc_create_srq_out_bits {
6201 u8 status[0x8];
b4ff3a36 6202 u8 reserved_at_8[0x18];
e281682b
SM		 6203
6204 u8 syndrome[0x20];
6205
b4ff3a36 6206 u8 reserved_at_40[0x8];
e281682b
SM		 6207 u8 srqn[0x18];
6208
b4ff3a36 6209 u8 reserved_at_60[0x20];
e281682b
SM		 6210};
6211
6212struct mlx5_ifc_create_srq_in_bits {
6213 u8 opcode[0x10];
b4ff3a36 6214 u8 reserved_at_10[0x10];
e281682b 6215
b4ff3a36 6216 u8 reserved_at_20[0x10];
e281682b
SM		 6217 u8 op_mod[0x10];
6218
b4ff3a36 6219 u8 reserved_at_40[0x40];
e281682b
SM		 6220
6221 struct mlx5_ifc_srqc_bits srq_context_entry;
6222
b4ff3a36 6223 u8 reserved_at_280[0x600];
e281682b
SM		 6224
6225 u8 pas[0][0x40];
6226};
6227
6228struct mlx5_ifc_create_sq_out_bits {
6229 u8 status[0x8];
b4ff3a36 6230 u8 reserved_at_8[0x18];
e281682b
SM		 6231
6232 u8 syndrome[0x20];
6233
b4ff3a36 6234 u8 reserved_at_40[0x8];
e281682b
SM		 6235 u8 sqn[0x18];
6236
b4ff3a36 6237 u8 reserved_at_60[0x20];
e281682b
SM		 6238};
6239
6240struct mlx5_ifc_create_sq_in_bits {
6241 u8 opcode[0x10];
b4ff3a36 6242 u8 reserved_at_10[0x10];
e281682b 6243
b4ff3a36 6244 u8 reserved_at_20[0x10];
e281682b
SM		 6245 u8 op_mod[0x10];
6246
b4ff3a36 6247 u8 reserved_at_40[0xc0];
e281682b
SM		 6248
6249 struct mlx5_ifc_sqc_bits ctx;
6250};
6251
813f8540
MHY		 6252struct mlx5_ifc_create_scheduling_element_out_bits {
6253 u8 status[0x8];
6254 u8 reserved_at_8[0x18];
6255
6256 u8 syndrome[0x20];
6257
6258 u8 reserved_at_40[0x40];
6259
6260 u8 scheduling_element_id[0x20];
6261
6262 u8 reserved_at_a0[0x160];
6263};
6264
6265struct mlx5_ifc_create_scheduling_element_in_bits {
6266 u8 opcode[0x10];
6267 u8 reserved_at_10[0x10];
6268
6269 u8 reserved_at_20[0x10];
6270 u8 op_mod[0x10];
6271
6272 u8 scheduling_hierarchy[0x8];
6273 u8 reserved_at_48[0x18];
6274
6275 u8 reserved_at_60[0xa0];
6276
6277 struct mlx5_ifc_scheduling_context_bits scheduling_context;
6278
6279 u8 reserved_at_300[0x100];
6280};
6281
e281682b
SM		 6282struct mlx5_ifc_create_rqt_out_bits {
6283 u8 status[0x8];
b4ff3a36 6284 u8 reserved_at_8[0x18];
e281682b
SM		 6285
6286 u8 syndrome[0x20];
6287
b4ff3a36 6288 u8 reserved_at_40[0x8];
e281682b
SM		 6289 u8 rqtn[0x18];
6290
b4ff3a36 6291 u8 reserved_at_60[0x20];
e281682b
SM		 6292};
6293
6294struct mlx5_ifc_create_rqt_in_bits {
6295 u8 opcode[0x10];
b4ff3a36 6296 u8 reserved_at_10[0x10];
e281682b 6297
b4ff3a36 6298 u8 reserved_at_20[0x10];
e281682b
SM		 6299 u8 op_mod[0x10];
6300
b4ff3a36 6301 u8 reserved_at_40[0xc0];
e281682b
SM		 6302
6303 struct mlx5_ifc_rqtc_bits rqt_context;
6304};
6305
6306struct mlx5_ifc_create_rq_out_bits {
6307 u8 status[0x8];
b4ff3a36 6308 u8 reserved_at_8[0x18];
e281682b
SM		 6309
6310 u8 syndrome[0x20];
6311
b4ff3a36 6312 u8 reserved_at_40[0x8];
e281682b
SM		 6313 u8 rqn[0x18];
6314
b4ff3a36 6315 u8 reserved_at_60[0x20];
e281682b
SM		 6316};
6317
6318struct mlx5_ifc_create_rq_in_bits {
6319 u8 opcode[0x10];
b4ff3a36 6320 u8 reserved_at_10[0x10];
e281682b 6321
b4ff3a36 6322 u8 reserved_at_20[0x10];
e281682b
SM		 6323 u8 op_mod[0x10];
6324
b4ff3a36 6325 u8 reserved_at_40[0xc0];
e281682b
SM		 6326
6327 struct mlx5_ifc_rqc_bits ctx;
6328};
6329
6330struct mlx5_ifc_create_rmp_out_bits {
6331 u8 status[0x8];
b4ff3a36 6332 u8 reserved_at_8[0x18];
e281682b
SM		 6333
6334 u8 syndrome[0x20];
6335
b4ff3a36 6336 u8 reserved_at_40[0x8];
e281682b
SM		 6337 u8 rmpn[0x18];
6338
b4ff3a36 6339 u8 reserved_at_60[0x20];
e281682b
SM		 6340};
6341
6342struct mlx5_ifc_create_rmp_in_bits {
6343 u8 opcode[0x10];
b4ff3a36 6344 u8 reserved_at_10[0x10];
e281682b 6345
b4ff3a36 6346 u8 reserved_at_20[0x10];
e281682b
SM		 6347 u8 op_mod[0x10];
6348
b4ff3a36 6349 u8 reserved_at_40[0xc0];
e281682b
SM		 6350
6351 struct mlx5_ifc_rmpc_bits ctx;
6352};
6353
6354struct mlx5_ifc_create_qp_out_bits {
6355 u8 status[0x8];
b4ff3a36 6356 u8 reserved_at_8[0x18];
e281682b
SM		 6357
6358 u8 syndrome[0x20];
6359
b4ff3a36 6360 u8 reserved_at_40[0x8];
e281682b
SM		 6361 u8 qpn[0x18];
6362
b4ff3a36 6363 u8 reserved_at_60[0x20];
e281682b
SM		 6364};
6365
6366struct mlx5_ifc_create_qp_in_bits {
6367 u8 opcode[0x10];
b4ff3a36 6368 u8 reserved_at_10[0x10];
e281682b 6369
b4ff3a36 6370 u8 reserved_at_20[0x10];
e281682b
SM		 6371 u8 op_mod[0x10];
6372
b4ff3a36 6373 u8 reserved_at_40[0x40];
e281682b
SM		 6374
6375 u8 opt_param_mask[0x20];
6376
b4ff3a36 6377 u8 reserved_at_a0[0x20];
e281682b
SM		 6378
6379 struct mlx5_ifc_qpc_bits qpc;
6380
b4ff3a36 6381 u8 reserved_at_800[0x80];
e281682b
SM		 6382
6383 u8 pas[0][0x40];
6384};
6385
6386struct mlx5_ifc_create_psv_out_bits {
6387 u8 status[0x8];
b4ff3a36 6388 u8 reserved_at_8[0x18];
e281682b
SM		 6389
6390 u8 syndrome[0x20];
6391
b4ff3a36 6392 u8 reserved_at_40[0x40];
e281682b 6393
b4ff3a36 6394 u8 reserved_at_80[0x8];
e281682b
SM		 6395 u8 psv0_index[0x18];
6396
b4ff3a36 6397 u8 reserved_at_a0[0x8];
e281682b
SM		 6398 u8 psv1_index[0x18];
6399
b4ff3a36 6400 u8 reserved_at_c0[0x8];
e281682b
SM		 6401 u8 psv2_index[0x18];
6402
b4ff3a36 6403 u8 reserved_at_e0[0x8];
e281682b
SM		 6404 u8 psv3_index[0x18];
6405};
6406
6407struct mlx5_ifc_create_psv_in_bits {
6408 u8 opcode[0x10];
b4ff3a36 6409 u8 reserved_at_10[0x10];
e281682b 6410
b4ff3a36 6411 u8 reserved_at_20[0x10];
e281682b
SM		 6412 u8 op_mod[0x10];
6413
6414 u8 num_psv[0x4];
b4ff3a36 6415 u8 reserved_at_44[0x4];
e281682b
SM		 6416 u8 pd[0x18];
6417
b4ff3a36 6418 u8 reserved_at_60[0x20];
e281682b
SM		 6419};
6420
6421struct mlx5_ifc_create_mkey_out_bits {
6422 u8 status[0x8];
b4ff3a36 6423 u8 reserved_at_8[0x18];
e281682b
SM		 6424
6425 u8 syndrome[0x20];
6426
b4ff3a36 6427 u8 reserved_at_40[0x8];
e281682b
SM		 6428 u8 mkey_index[0x18];
6429
b4ff3a36 6430 u8 reserved_at_60[0x20];
e281682b
SM		 6431};
6432
6433struct mlx5_ifc_create_mkey_in_bits {
6434 u8 opcode[0x10];
b4ff3a36 6435 u8 reserved_at_10[0x10];
e281682b 6436
b4ff3a36 6437 u8 reserved_at_20[0x10];
e281682b
SM		 6438 u8 op_mod[0x10];
6439
b4ff3a36 6440 u8 reserved_at_40[0x20];
e281682b
SM		 6441
6442 u8 pg_access[0x1];
b4ff3a36 6443 u8 reserved_at_61[0x1f];
e281682b
SM		 6444
6445 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6446
b4ff3a36 6447 u8 reserved_at_280[0x80];
e281682b
SM		 6448
6449 u8 translations_octword_actual_size[0x20];
6450
b4ff3a36 6451 u8 reserved_at_320[0x560];
e281682b
SM		 6452
6453 u8 klm_pas_mtt[0][0x20];
6454};
6455
6456struct mlx5_ifc_create_flow_table_out_bits {
6457 u8 status[0x8];
b4ff3a36 6458 u8 reserved_at_8[0x18];
e281682b
SM		 6459
6460 u8 syndrome[0x20];
6461
b4ff3a36 6462 u8 reserved_at_40[0x8];
e281682b
SM		 6463 u8 table_id[0x18];
6464
b4ff3a36 6465 u8 reserved_at_60[0x20];
e281682b
SM		 6466};
6467
6468struct mlx5_ifc_create_flow_table_in_bits {
6469 u8 opcode[0x10];
b4ff3a36 6470 u8 reserved_at_10[0x10];
e281682b 6471
b4ff3a36 6472 u8 reserved_at_20[0x10];
e281682b
SM		 6473 u8 op_mod[0x10];
6474
7d5e1423
SM		 6475 u8 other_vport[0x1];
6476 u8 reserved_at_41[0xf];
6477 u8 vport_number[0x10];
6478
6479 u8 reserved_at_60[0x20];
e281682b
SM		 6480
6481 u8 table_type[0x8];
b4ff3a36 6482 u8 reserved_at_88[0x18];
e281682b 6483
b4ff3a36 6484 u8 reserved_at_a0[0x20];
e281682b 6485
7adbde20
HHZ		 6486 u8 encap_en[0x1];
6487 u8 decap_en[0x1];
6488 u8 reserved_at_c2[0x2];
34a40e68 6489 u8 table_miss_mode[0x4];
e281682b 6490 u8 level[0x8];
b4ff3a36 6491 u8 reserved_at_d0[0x8];
e281682b
SM		 6492 u8 log_size[0x8];
6493
b4ff3a36 6494 u8 reserved_at_e0[0x8];
34a40e68
MG		 6495 u8 table_miss_id[0x18];
6496
84df61eb
AH		 6497 u8 reserved_at_100[0x8];
6498 u8 lag_master_next_table_id[0x18];
6499
6500 u8 reserved_at_120[0x80];
e281682b
SM		 6501};
6502
6503struct mlx5_ifc_create_flow_group_out_bits {
6504 u8 status[0x8];
b4ff3a36 6505 u8 reserved_at_8[0x18];
e281682b
SM		 6506
6507 u8 syndrome[0x20];
6508
b4ff3a36 6509 u8 reserved_at_40[0x8];
e281682b
SM		 6510 u8 group_id[0x18];
6511
b4ff3a36 6512 u8 reserved_at_60[0x20];
e281682b
SM		 6513};
6514
6515enum {
6516 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
6517 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
6518 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
6519};
6520
6521struct mlx5_ifc_create_flow_group_in_bits {
6522 u8 opcode[0x10];
b4ff3a36 6523 u8 reserved_at_10[0x10];
e281682b 6524
b4ff3a36 6525 u8 reserved_at_20[0x10];
e281682b
SM		 6526 u8 op_mod[0x10];
6527
7d5e1423
SM		 6528 u8 other_vport[0x1];
6529 u8 reserved_at_41[0xf];
6530 u8 vport_number[0x10];
6531
6532 u8 reserved_at_60[0x20];
e281682b
SM		 6533
6534 u8 table_type[0x8];
b4ff3a36 6535 u8 reserved_at_88[0x18];
e281682b 6536
b4ff3a36 6537 u8 reserved_at_a0[0x8];
e281682b
SM		 6538 u8 table_id[0x18];
6539
b4ff3a36 6540 u8 reserved_at_c0[0x20];
e281682b
SM		 6541
6542 u8 start_flow_index[0x20];
6543
b4ff3a36 6544 u8 reserved_at_100[0x20];
e281682b
SM		 6545
6546 u8 end_flow_index[0x20];
6547
b4ff3a36 6548 u8 reserved_at_140[0xa0];
e281682b 6549
b4ff3a36 6550 u8 reserved_at_1e0[0x18];
e281682b
SM		 6551 u8 match_criteria_enable[0x8];
6552
6553 struct mlx5_ifc_fte_match_param_bits match_criteria;
6554
b4ff3a36 6555 u8 reserved_at_1200[0xe00];
e281682b
SM		 6556};
6557
6558struct mlx5_ifc_create_eq_out_bits {
6559 u8 status[0x8];
b4ff3a36 6560 u8 reserved_at_8[0x18];
e281682b
SM		 6561
6562 u8 syndrome[0x20];
6563
b4ff3a36 6564 u8 reserved_at_40[0x18];
e281682b
SM		 6565 u8 eq_number[0x8];
6566
b4ff3a36 6567 u8 reserved_at_60[0x20];
e281682b
SM		 6568};
6569
6570struct mlx5_ifc_create_eq_in_bits {
6571 u8 opcode[0x10];
b4ff3a36 6572 u8 reserved_at_10[0x10];
e281682b 6573
b4ff3a36 6574 u8 reserved_at_20[0x10];
e281682b
SM		 6575 u8 op_mod[0x10];
6576
b4ff3a36 6577 u8 reserved_at_40[0x40];
e281682b
SM		 6578
6579 struct mlx5_ifc_eqc_bits eq_context_entry;
6580
b4ff3a36 6581 u8 reserved_at_280[0x40];
e281682b
SM		 6582
6583 u8 event_bitmask[0x40];
6584
b4ff3a36 6585 u8 reserved_at_300[0x580];
e281682b
SM		 6586
6587 u8 pas[0][0x40];
6588};
6589
6590struct mlx5_ifc_create_dct_out_bits {
6591 u8 status[0x8];
b4ff3a36 6592 u8 reserved_at_8[0x18];
e281682b
SM		 6593
6594 u8 syndrome[0x20];
6595
b4ff3a36 6596 u8 reserved_at_40[0x8];
e281682b
SM		 6597 u8 dctn[0x18];
6598
b4ff3a36 6599 u8 reserved_at_60[0x20];
e281682b
SM		 6600};
6601
6602struct mlx5_ifc_create_dct_in_bits {
6603 u8 opcode[0x10];
b4ff3a36 6604 u8 reserved_at_10[0x10];
e281682b 6605
b4ff3a36 6606 u8 reserved_at_20[0x10];
e281682b
SM		 6607 u8 op_mod[0x10];
6608
b4ff3a36 6609 u8 reserved_at_40[0x40];
e281682b
SM		 6610
6611 struct mlx5_ifc_dctc_bits dct_context_entry;
6612
b4ff3a36 6613 u8 reserved_at_280[0x180];
e281682b
SM		 6614};
6615
6616struct mlx5_ifc_create_cq_out_bits {
6617 u8 status[0x8];
b4ff3a36 6618 u8 reserved_at_8[0x18];
e281682b
SM		 6619
6620 u8 syndrome[0x20];
6621
b4ff3a36 6622 u8 reserved_at_40[0x8];
e281682b
SM		 6623 u8 cqn[0x18];
6624
b4ff3a36 6625 u8 reserved_at_60[0x20];
e281682b
SM		 6626};
6627
6628struct mlx5_ifc_create_cq_in_bits {
6629 u8 opcode[0x10];
b4ff3a36 6630 u8 reserved_at_10[0x10];
e281682b 6631
b4ff3a36 6632 u8 reserved_at_20[0x10];
e281682b
SM		 6633 u8 op_mod[0x10];
6634
b4ff3a36 6635 u8 reserved_at_40[0x40];
e281682b
SM		 6636
6637 struct mlx5_ifc_cqc_bits cq_context;
6638
b4ff3a36 6639 u8 reserved_at_280[0x600];
e281682b
SM		 6640
6641 u8 pas[0][0x40];
6642};
6643
6644struct mlx5_ifc_config_int_moderation_out_bits {
6645 u8 status[0x8];
b4ff3a36 6646 u8 reserved_at_8[0x18];
e281682b
SM		 6647
6648 u8 syndrome[0x20];
6649
b4ff3a36 6650 u8 reserved_at_40[0x4];
e281682b
SM		 6651 u8 min_delay[0xc];
6652 u8 int_vector[0x10];
6653
b4ff3a36 6654 u8 reserved_at_60[0x20];
e281682b
SM		 6655};
6656
6657enum {
6658 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
6659 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
6660};
6661
6662struct mlx5_ifc_config_int_moderation_in_bits {
6663 u8 opcode[0x10];
b4ff3a36 6664 u8 reserved_at_10[0x10];
e281682b 6665
b4ff3a36 6666 u8 reserved_at_20[0x10];
e281682b
SM		 6667 u8 op_mod[0x10];
6668
b4ff3a36 6669 u8 reserved_at_40[0x4];
e281682b
SM		 6670 u8 min_delay[0xc];
6671 u8 int_vector[0x10];
6672
b4ff3a36 6673 u8 reserved_at_60[0x20];
e281682b
SM		 6674};
6675
6676struct mlx5_ifc_attach_to_mcg_out_bits {
6677 u8 status[0x8];
b4ff3a36 6678 u8 reserved_at_8[0x18];
e281682b
SM		 6679
6680 u8 syndrome[0x20];
6681
b4ff3a36 6682 u8 reserved_at_40[0x40];
e281682b
SM		 6683};
6684
6685struct mlx5_ifc_attach_to_mcg_in_bits {
6686 u8 opcode[0x10];
b4ff3a36 6687 u8 reserved_at_10[0x10];
e281682b 6688
b4ff3a36 6689 u8 reserved_at_20[0x10];
e281682b
SM		 6690 u8 op_mod[0x10];
6691
b4ff3a36 6692 u8 reserved_at_40[0x8];
e281682b
SM		 6693 u8 qpn[0x18];
6694
b4ff3a36 6695 u8 reserved_at_60[0x20];
e281682b
SM		 6696
6697 u8 multicast_gid[16][0x8];
6698};
6699
7486216b
SM		 6700struct mlx5_ifc_arm_xrq_out_bits {
6701 u8 status[0x8];
6702 u8 reserved_at_8[0x18];
6703
6704 u8 syndrome[0x20];
6705
6706 u8 reserved_at_40[0x40];
6707};
6708
6709struct mlx5_ifc_arm_xrq_in_bits {
6710 u8 opcode[0x10];
6711 u8 reserved_at_10[0x10];
6712
6713 u8 reserved_at_20[0x10];
6714 u8 op_mod[0x10];
6715
6716 u8 reserved_at_40[0x8];
6717 u8 xrqn[0x18];
6718
6719 u8 reserved_at_60[0x10];
6720 u8 lwm[0x10];
6721};
6722
e281682b
SM		 6723struct mlx5_ifc_arm_xrc_srq_out_bits {
6724 u8 status[0x8];
b4ff3a36 6725 u8 reserved_at_8[0x18];
e281682b
SM		 6726
6727 u8 syndrome[0x20];
6728
b4ff3a36 6729 u8 reserved_at_40[0x40];
e281682b
SM		 6730};
6731
6732enum {
6733 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
6734};
6735
6736struct mlx5_ifc_arm_xrc_srq_in_bits {
6737 u8 opcode[0x10];
b4ff3a36 6738 u8 reserved_at_10[0x10];
e281682b 6739
b4ff3a36 6740 u8 reserved_at_20[0x10];
e281682b
SM		 6741 u8 op_mod[0x10];
6742
b4ff3a36 6743 u8 reserved_at_40[0x8];
e281682b
SM		 6744 u8 xrc_srqn[0x18];
6745
b4ff3a36 6746 u8 reserved_at_60[0x10];
e281682b
SM		 6747 u8 lwm[0x10];
6748};
6749
6750struct mlx5_ifc_arm_rq_out_bits {
6751 u8 status[0x8];
b4ff3a36 6752 u8 reserved_at_8[0x18];
e281682b
SM		 6753
6754 u8 syndrome[0x20];
6755
b4ff3a36 6756 u8 reserved_at_40[0x40];
e281682b
SM		 6757};
6758
6759enum {
7486216b
SM		 6760 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
6761 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
e281682b
SM		 6762};
6763
6764struct mlx5_ifc_arm_rq_in_bits {
6765 u8 opcode[0x10];
b4ff3a36 6766 u8 reserved_at_10[0x10];
e281682b 6767
b4ff3a36 6768 u8 reserved_at_20[0x10];
e281682b
SM		 6769 u8 op_mod[0x10];
6770
b4ff3a36 6771 u8 reserved_at_40[0x8];
e281682b
SM		 6772 u8 srq_number[0x18];
6773
b4ff3a36 6774 u8 reserved_at_60[0x10];
e281682b
SM		 6775 u8 lwm[0x10];
6776};
6777
6778struct mlx5_ifc_arm_dct_out_bits {
6779 u8 status[0x8];
b4ff3a36 6780 u8 reserved_at_8[0x18];
e281682b
SM		 6781
6782 u8 syndrome[0x20];
6783
b4ff3a36 6784 u8 reserved_at_40[0x40];
e281682b
SM		 6785};
6786
6787struct mlx5_ifc_arm_dct_in_bits {
6788 u8 opcode[0x10];
b4ff3a36 6789 u8 reserved_at_10[0x10];
e281682b 6790
b4ff3a36 6791 u8 reserved_at_20[0x10];
e281682b
SM		 6792 u8 op_mod[0x10];
6793
b4ff3a36 6794 u8 reserved_at_40[0x8];
e281682b
SM		 6795 u8 dct_number[0x18];
6796
b4ff3a36 6797 u8 reserved_at_60[0x20];
e281682b
SM		 6798};
6799
6800struct mlx5_ifc_alloc_xrcd_out_bits {
6801 u8 status[0x8];
b4ff3a36 6802 u8 reserved_at_8[0x18];
e281682b
SM		 6803
6804 u8 syndrome[0x20];
6805
b4ff3a36 6806 u8 reserved_at_40[0x8];
e281682b
SM		 6807 u8 xrcd[0x18];
6808
b4ff3a36 6809 u8 reserved_at_60[0x20];
e281682b
SM		 6810};
6811
6812struct mlx5_ifc_alloc_xrcd_in_bits {
6813 u8 opcode[0x10];
b4ff3a36 6814 u8 reserved_at_10[0x10];
e281682b 6815
b4ff3a36 6816 u8 reserved_at_20[0x10];
e281682b
SM		 6817 u8 op_mod[0x10];
6818
b4ff3a36 6819 u8 reserved_at_40[0x40];
e281682b
SM		 6820};
6821
6822struct mlx5_ifc_alloc_uar_out_bits {
6823 u8 status[0x8];
b4ff3a36 6824 u8 reserved_at_8[0x18];
e281682b
SM		 6825
6826 u8 syndrome[0x20];
6827
b4ff3a36 6828 u8 reserved_at_40[0x8];
e281682b
SM		 6829 u8 uar[0x18];
6830
b4ff3a36 6831 u8 reserved_at_60[0x20];
e281682b
SM		 6832};
6833
6834struct mlx5_ifc_alloc_uar_in_bits {
6835 u8 opcode[0x10];
b4ff3a36 6836 u8 reserved_at_10[0x10];
e281682b 6837
b4ff3a36 6838 u8 reserved_at_20[0x10];
e281682b
SM		 6839 u8 op_mod[0x10];
6840
b4ff3a36 6841 u8 reserved_at_40[0x40];
e281682b
SM		 6842};
6843
6844struct mlx5_ifc_alloc_transport_domain_out_bits {
6845 u8 status[0x8];
b4ff3a36 6846 u8 reserved_at_8[0x18];
e281682b
SM		 6847
6848 u8 syndrome[0x20];
6849
b4ff3a36 6850 u8 reserved_at_40[0x8];
e281682b
SM		 6851 u8 transport_domain[0x18];
6852
b4ff3a36 6853 u8 reserved_at_60[0x20];
e281682b
SM		 6854};
6855
6856struct mlx5_ifc_alloc_transport_domain_in_bits {
6857 u8 opcode[0x10];
b4ff3a36 6858 u8 reserved_at_10[0x10];
e281682b 6859
b4ff3a36 6860 u8 reserved_at_20[0x10];
e281682b
SM		 6861 u8 op_mod[0x10];
6862
b4ff3a36 6863 u8 reserved_at_40[0x40];
e281682b
SM		 6864};
6865
6866struct mlx5_ifc_alloc_q_counter_out_bits {
6867 u8 status[0x8];
b4ff3a36 6868 u8 reserved_at_8[0x18];
e281682b
SM		 6869
6870 u8 syndrome[0x20];
6871
b4ff3a36 6872 u8 reserved_at_40[0x18];
e281682b
SM		 6873 u8 counter_set_id[0x8];
6874
b4ff3a36 6875 u8 reserved_at_60[0x20];
e281682b
SM		 6876};
6877
6878struct mlx5_ifc_alloc_q_counter_in_bits {
6879 u8 opcode[0x10];
b4ff3a36 6880 u8 reserved_at_10[0x10];
e281682b 6881
b4ff3a36 6882 u8 reserved_at_20[0x10];
e281682b
SM		 6883 u8 op_mod[0x10];
6884
b4ff3a36 6885 u8 reserved_at_40[0x40];
e281682b
SM		 6886};
6887
6888struct mlx5_ifc_alloc_pd_out_bits {
6889 u8 status[0x8];
b4ff3a36 6890 u8 reserved_at_8[0x18];
e281682b
SM		 6891
6892 u8 syndrome[0x20];
6893
b4ff3a36 6894 u8 reserved_at_40[0x8];
e281682b
SM		 6895 u8 pd[0x18];
6896
b4ff3a36 6897 u8 reserved_at_60[0x20];
e281682b
SM		 6898};
6899
6900struct mlx5_ifc_alloc_pd_in_bits {
9dc0b289
AV		 6901 u8 opcode[0x10];
6902 u8 reserved_at_10[0x10];
6903
6904 u8 reserved_at_20[0x10];
6905 u8 op_mod[0x10];
6906
6907 u8 reserved_at_40[0x40];
6908};
6909
6910struct mlx5_ifc_alloc_flow_counter_out_bits {
6911 u8 status[0x8];
6912 u8 reserved_at_8[0x18];
6913
6914 u8 syndrome[0x20];
6915
6916 u8 reserved_at_40[0x10];
6917 u8 flow_counter_id[0x10];
6918
6919 u8 reserved_at_60[0x20];
6920};
6921
6922struct mlx5_ifc_alloc_flow_counter_in_bits {
e281682b 6923 u8 opcode[0x10];
b4ff3a36 6924 u8 reserved_at_10[0x10];
e281682b 6925
b4ff3a36 6926 u8 reserved_at_20[0x10];
e281682b
SM		 6927 u8 op_mod[0x10];
6928
b4ff3a36 6929 u8 reserved_at_40[0x40];
e281682b
SM		 6930};
6931
6932struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
6933 u8 status[0x8];
b4ff3a36 6934 u8 reserved_at_8[0x18];
e281682b
SM		 6935
6936 u8 syndrome[0x20];
6937
b4ff3a36 6938 u8 reserved_at_40[0x40];
e281682b
SM		 6939};
6940
6941struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
6942 u8 opcode[0x10];
b4ff3a36 6943 u8 reserved_at_10[0x10];
e281682b 6944
b4ff3a36 6945 u8 reserved_at_20[0x10];
e281682b
SM		 6946 u8 op_mod[0x10];
6947
b4ff3a36 6948 u8 reserved_at_40[0x20];
e281682b 6949
b4ff3a36 6950 u8 reserved_at_60[0x10];
e281682b
SM		 6951 u8 vxlan_udp_port[0x10];
6952};
6953
7486216b
SM		 6954struct mlx5_ifc_set_rate_limit_out_bits {
6955 u8 status[0x8];
6956 u8 reserved_at_8[0x18];
6957
6958 u8 syndrome[0x20];
6959
6960 u8 reserved_at_40[0x40];
6961};
6962
6963struct mlx5_ifc_set_rate_limit_in_bits {
6964 u8 opcode[0x10];
6965 u8 reserved_at_10[0x10];
6966
6967 u8 reserved_at_20[0x10];
6968 u8 op_mod[0x10];
6969
6970 u8 reserved_at_40[0x10];
6971 u8 rate_limit_index[0x10];
6972
6973 u8 reserved_at_60[0x20];
6974
6975 u8 rate_limit[0x20];
6976};
6977
e281682b
SM		 6978struct mlx5_ifc_access_register_out_bits {
6979 u8 status[0x8];
b4ff3a36 6980 u8 reserved_at_8[0x18];
e281682b
SM		 6981
6982 u8 syndrome[0x20];
6983
b4ff3a36 6984 u8 reserved_at_40[0x40];
e281682b
SM		 6985
6986 u8 register_data[0][0x20];
6987};
6988
6989enum {
6990 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
6991 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
6992};
6993
6994struct mlx5_ifc_access_register_in_bits {
6995 u8 opcode[0x10];
b4ff3a36 6996 u8 reserved_at_10[0x10];
e281682b 6997
b4ff3a36 6998 u8 reserved_at_20[0x10];
e281682b
SM		 6999 u8 op_mod[0x10];
7000
b4ff3a36 7001 u8 reserved_at_40[0x10];
e281682b
SM		 7002 u8 register_id[0x10];
7003
7004 u8 argument[0x20];
7005
7006 u8 register_data[0][0x20];
7007};
7008
7009struct mlx5_ifc_sltp_reg_bits {
7010 u8 status[0x4];
7011 u8 version[0x4];
7012 u8 local_port[0x8];
7013 u8 pnat[0x2];
b4ff3a36 7014 u8 reserved_at_12[0x2];
e281682b 7015 u8 lane[0x4];
b4ff3a36 7016 u8 reserved_at_18[0x8];
e281682b 7017
b4ff3a36 7018 u8 reserved_at_20[0x20];
e281682b 7019
b4ff3a36 7020 u8 reserved_at_40[0x7];
e281682b
SM		 7021 u8 polarity[0x1];
7022 u8 ob_tap0[0x8];
7023 u8 ob_tap1[0x8];
7024 u8 ob_tap2[0x8];
7025
b4ff3a36 7026 u8 reserved_at_60[0xc];
e281682b
SM		 7027 u8 ob_preemp_mode[0x4];
7028 u8 ob_reg[0x8];
7029 u8 ob_bias[0x8];
7030
b4ff3a36 7031 u8 reserved_at_80[0x20];
e281682b
SM		 7032};
7033
7034struct mlx5_ifc_slrg_reg_bits {
7035 u8 status[0x4];
7036 u8 version[0x4];
7037 u8 local_port[0x8];
7038 u8 pnat[0x2];
b4ff3a36 7039 u8 reserved_at_12[0x2];
e281682b 7040 u8 lane[0x4];
b4ff3a36 7041 u8 reserved_at_18[0x8];
e281682b
SM		 7042
7043 u8 time_to_link_up[0x10];
b4ff3a36 7044 u8 reserved_at_30[0xc];
e281682b
SM		 7045 u8 grade_lane_speed[0x4];
7046
7047 u8 grade_version[0x8];
7048 u8 grade[0x18];
7049
b4ff3a36 7050 u8 reserved_at_60[0x4];
e281682b
SM		 7051 u8 height_grade_type[0x4];
7052 u8 height_grade[0x18];
7053
7054 u8 height_dz[0x10];
7055 u8 height_dv[0x10];
7056
b4ff3a36 7057 u8 reserved_at_a0[0x10];
e281682b
SM		 7058 u8 height_sigma[0x10];
7059
b4ff3a36 7060 u8 reserved_at_c0[0x20];
e281682b 7061
b4ff3a36 7062 u8 reserved_at_e0[0x4];
e281682b
SM		 7063 u8 phase_grade_type[0x4];
7064 u8 phase_grade[0x18];
7065
b4ff3a36 7066 u8 reserved_at_100[0x8];
e281682b 7067 u8 phase_eo_pos[0x8];
b4ff3a36 7068 u8 reserved_at_110[0x8];
e281682b
SM		 7069 u8 phase_eo_neg[0x8];
7070
7071 u8 ffe_set_tested[0x10];
7072 u8 test_errors_per_lane[0x10];
7073};
7074
7075struct mlx5_ifc_pvlc_reg_bits {
b4ff3a36 7076 u8 reserved_at_0[0x8];
e281682b 7077 u8 local_port[0x8];
b4ff3a36 7078 u8 reserved_at_10[0x10];
e281682b 7079
b4ff3a36 7080 u8 reserved_at_20[0x1c];
e281682b
SM		 7081 u8 vl_hw_cap[0x4];
7082
b4ff3a36 7083 u8 reserved_at_40[0x1c];
e281682b
SM		 7084 u8 vl_admin[0x4];
7085
b4ff3a36 7086 u8 reserved_at_60[0x1c];
e281682b
SM		 7087 u8 vl_operational[0x4];
7088};
7089
7090struct mlx5_ifc_pude_reg_bits {
7091 u8 swid[0x8];
7092 u8 local_port[0x8];
b4ff3a36 7093 u8 reserved_at_10[0x4];
e281682b 7094 u8 admin_status[0x4];
b4ff3a36 7095 u8 reserved_at_18[0x4];
e281682b
SM		 7096 u8 oper_status[0x4];
7097
b4ff3a36 7098 u8 reserved_at_20[0x60];
e281682b
SM		 7099};
7100
7101struct mlx5_ifc_ptys_reg_bits {
e7e31ca4 7102 u8 reserved_at_0[0x1];
7486216b 7103 u8 an_disable_admin[0x1];
e7e31ca4
BW		 7104 u8 an_disable_cap[0x1];
7105 u8 reserved_at_3[0x5];
e281682b 7106 u8 local_port[0x8];
b4ff3a36 7107 u8 reserved_at_10[0xd];
e281682b
SM		 7108 u8 proto_mask[0x3];
7109
7486216b
SM		 7110 u8 an_status[0x4];
7111 u8 reserved_at_24[0x3c];
e281682b
SM		 7112
7113 u8 eth_proto_capability[0x20];
7114
7115 u8 ib_link_width_capability[0x10];
7116 u8 ib_proto_capability[0x10];
7117
b4ff3a36 7118 u8 reserved_at_a0[0x20];
e281682b
SM		 7119
7120 u8 eth_proto_admin[0x20];
7121
7122 u8 ib_link_width_admin[0x10];
7123 u8 ib_proto_admin[0x10];
7124
b4ff3a36 7125 u8 reserved_at_100[0x20];
e281682b
SM		 7126
7127 u8 eth_proto_oper[0x20];
7128
7129 u8 ib_link_width_oper[0x10];
7130 u8 ib_proto_oper[0x10];
7131
b4ff3a36 7132 u8 reserved_at_160[0x20];
e281682b
SM		 7133
7134 u8 eth_proto_lp_advertise[0x20];
7135
b4ff3a36 7136 u8 reserved_at_1a0[0x60];
e281682b
SM		 7137};
7138
7d5e1423
SM		 7139struct mlx5_ifc_mlcr_reg_bits {
7140 u8 reserved_at_0[0x8];
7141 u8 local_port[0x8];
7142 u8 reserved_at_10[0x20];
7143
7144 u8 beacon_duration[0x10];
7145 u8 reserved_at_40[0x10];
7146
7147 u8 beacon_remain[0x10];
7148};
7149
e281682b 7150struct mlx5_ifc_ptas_reg_bits {
b4ff3a36 7151 u8 reserved_at_0[0x20];
e281682b
SM		 7152
7153 u8 algorithm_options[0x10];
b4ff3a36 7154 u8 reserved_at_30[0x4];
e281682b
SM		 7155 u8 repetitions_mode[0x4];
7156 u8 num_of_repetitions[0x8];
7157
7158 u8 grade_version[0x8];
7159 u8 height_grade_type[0x4];
7160 u8 phase_grade_type[0x4];
7161 u8 height_grade_weight[0x8];
7162 u8 phase_grade_weight[0x8];
7163
7164 u8 gisim_measure_bits[0x10];
7165 u8 adaptive_tap_measure_bits[0x10];
7166
7167 u8 ber_bath_high_error_threshold[0x10];
7168 u8 ber_bath_mid_error_threshold[0x10];
7169
7170 u8 ber_bath_low_error_threshold[0x10];
7171 u8 one_ratio_high_threshold[0x10];
7172
7173 u8 one_ratio_high_mid_threshold[0x10];
7174 u8 one_ratio_low_mid_threshold[0x10];
7175
7176 u8 one_ratio_low_threshold[0x10];
7177 u8 ndeo_error_threshold[0x10];
7178
7179 u8 mixer_offset_step_size[0x10];
b4ff3a36 7180 u8 reserved_at_110[0x8];
e281682b
SM		 7181 u8 mix90_phase_for_voltage_bath[0x8];
7182
7183 u8 mixer_offset_start[0x10];
7184 u8 mixer_offset_end[0x10];
7185
b4ff3a36 7186 u8 reserved_at_140[0x15];
e281682b
SM		 7187 u8 ber_test_time[0xb];
7188};
7189
7190struct mlx5_ifc_pspa_reg_bits {
7191 u8 swid[0x8];
7192 u8 local_port[0x8];
7193 u8 sub_port[0x8];
b4ff3a36 7194 u8 reserved_at_18[0x8];
e281682b 7195
b4ff3a36 7196 u8 reserved_at_20[0x20];
e281682b
SM		 7197};
7198
7199struct mlx5_ifc_pqdr_reg_bits {
b4ff3a36 7200 u8 reserved_at_0[0x8];
e281682b 7201 u8 local_port[0x8];
b4ff3a36 7202 u8 reserved_at_10[0x5];
e281682b 7203 u8 prio[0x3];
b4ff3a36 7204 u8 reserved_at_18[0x6];
e281682b
SM		 7205 u8 mode[0x2];
7206
b4ff3a36 7207 u8 reserved_at_20[0x20];
e281682b 7208
b4ff3a36 7209 u8 reserved_at_40[0x10];
e281682b
SM		 7210 u8 min_threshold[0x10];
7211
b4ff3a36 7212 u8 reserved_at_60[0x10];
e281682b
SM		 7213 u8 max_threshold[0x10];
7214
b4ff3a36 7215 u8 reserved_at_80[0x10];
e281682b
SM		 7216 u8 mark_probability_denominator[0x10];
7217
b4ff3a36 7218 u8 reserved_at_a0[0x60];
e281682b
SM		 7219};
7220
7221struct mlx5_ifc_ppsc_reg_bits {
b4ff3a36 7222 u8 reserved_at_0[0x8];
e281682b 7223 u8 local_port[0x8];
b4ff3a36 7224 u8 reserved_at_10[0x10];
e281682b 7225
b4ff3a36 7226 u8 reserved_at_20[0x60];
e281682b 7227
b4ff3a36 7228 u8 reserved_at_80[0x1c];
e281682b
SM		 7229 u8 wrps_admin[0x4];
7230
b4ff3a36 7231 u8 reserved_at_a0[0x1c];
e281682b
SM		 7232 u8 wrps_status[0x4];
7233
b4ff3a36 7234 u8 reserved_at_c0[0x8];
e281682b 7235 u8 up_threshold[0x8];
b4ff3a36 7236 u8 reserved_at_d0[0x8];
e281682b
SM		 7237 u8 down_threshold[0x8];
7238
b4ff3a36 7239 u8 reserved_at_e0[0x20];
e281682b 7240
b4ff3a36 7241 u8 reserved_at_100[0x1c];
e281682b
SM		 7242 u8 srps_admin[0x4];
7243
b4ff3a36 7244 u8 reserved_at_120[0x1c];
e281682b
SM		 7245 u8 srps_status[0x4];
7246
b4ff3a36 7247 u8 reserved_at_140[0x40];
e281682b
SM		 7248};
7249
7250struct mlx5_ifc_pplr_reg_bits {
b4ff3a36 7251 u8 reserved_at_0[0x8];
e281682b 7252 u8 local_port[0x8];
b4ff3a36 7253 u8 reserved_at_10[0x10];
e281682b 7254
b4ff3a36 7255 u8 reserved_at_20[0x8];
e281682b 7256 u8 lb_cap[0x8];
b4ff3a36 7257 u8 reserved_at_30[0x8];
e281682b
SM		 7258 u8 lb_en[0x8];
7259};
7260
7261struct mlx5_ifc_pplm_reg_bits {
b4ff3a36 7262 u8 reserved_at_0[0x8];
e281682b 7263 u8 local_port[0x8];
b4ff3a36 7264 u8 reserved_at_10[0x10];
e281682b 7265
b4ff3a36 7266 u8 reserved_at_20[0x20];
e281682b
SM		 7267
7268 u8 port_profile_mode[0x8];
7269 u8 static_port_profile[0x8];
7270 u8 active_port_profile[0x8];
b4ff3a36 7271 u8 reserved_at_58[0x8];
e281682b
SM		 7272
7273 u8 retransmission_active[0x8];
7274 u8 fec_mode_active[0x18];
7275
b4ff3a36 7276 u8 reserved_at_80[0x20];
e281682b
SM		 7277};
7278
7279struct mlx5_ifc_ppcnt_reg_bits {
7280 u8 swid[0x8];
7281 u8 local_port[0x8];
7282 u8 pnat[0x2];
b4ff3a36 7283 u8 reserved_at_12[0x8];
e281682b
SM		 7284 u8 grp[0x6];
7285
7286 u8 clr[0x1];
b4ff3a36 7287 u8 reserved_at_21[0x1c];
e281682b
SM		 7288 u8 prio_tc[0x3];
7289
7290 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
7291};
7292
7293struct mlx5_ifc_ppad_reg_bits {
b4ff3a36 7294 u8 reserved_at_0[0x3];
e281682b 7295 u8 single_mac[0x1];
b4ff3a36 7296 u8 reserved_at_4[0x4];
e281682b
SM		 7297 u8 local_port[0x8];
7298 u8 mac_47_32[0x10];
7299
7300 u8 mac_31_0[0x20];
7301
b4ff3a36 7302 u8 reserved_at_40[0x40];
e281682b
SM		 7303};
7304
7305struct mlx5_ifc_pmtu_reg_bits {
b4ff3a36 7306 u8 reserved_at_0[0x8];
e281682b 7307 u8 local_port[0x8];
b4ff3a36 7308 u8 reserved_at_10[0x10];
e281682b
SM		 7309
7310 u8 max_mtu[0x10];
b4ff3a36 7311 u8 reserved_at_30[0x10];
e281682b
SM		 7312
7313 u8 admin_mtu[0x10];
b4ff3a36 7314 u8 reserved_at_50[0x10];
e281682b
SM		 7315
7316 u8 oper_mtu[0x10];
b4ff3a36 7317 u8 reserved_at_70[0x10];
e281682b
SM		 7318};
7319
7320struct mlx5_ifc_pmpr_reg_bits {
b4ff3a36 7321 u8 reserved_at_0[0x8];
e281682b 7322 u8 module[0x8];
b4ff3a36 7323 u8 reserved_at_10[0x10];
e281682b 7324
b4ff3a36 7325 u8 reserved_at_20[0x18];
e281682b
SM		 7326 u8 attenuation_5g[0x8];
7327
b4ff3a36 7328 u8 reserved_at_40[0x18];
e281682b
SM		 7329 u8 attenuation_7g[0x8];
7330
b4ff3a36 7331 u8 reserved_at_60[0x18];
e281682b
SM		 7332 u8 attenuation_12g[0x8];
7333};
7334
7335struct mlx5_ifc_pmpe_reg_bits {
b4ff3a36 7336 u8 reserved_at_0[0x8];
e281682b 7337 u8 module[0x8];
b4ff3a36 7338 u8 reserved_at_10[0xc];
e281682b
SM		 7339 u8 module_status[0x4];
7340
b4ff3a36 7341 u8 reserved_at_20[0x60];
e281682b
SM		 7342};
7343
7344struct mlx5_ifc_pmpc_reg_bits {
7345 u8 module_state_updated[32][0x8];
7346};
7347
7348struct mlx5_ifc_pmlpn_reg_bits {
b4ff3a36 7349 u8 reserved_at_0[0x4];
e281682b
SM		 7350 u8 mlpn_status[0x4];
7351 u8 local_port[0x8];
b4ff3a36 7352 u8 reserved_at_10[0x10];
e281682b
SM		 7353
7354 u8 e[0x1];
b4ff3a36 7355 u8 reserved_at_21[0x1f];
e281682b
SM		 7356};
7357
7358struct mlx5_ifc_pmlp_reg_bits {
7359 u8 rxtx[0x1];
b4ff3a36 7360 u8 reserved_at_1[0x7];
e281682b 7361 u8 local_port[0x8];
b4ff3a36 7362 u8 reserved_at_10[0x8];
e281682b
SM		 7363 u8 width[0x8];
7364
7365 u8 lane0_module_mapping[0x20];
7366
7367 u8 lane1_module_mapping[0x20];
7368
7369 u8 lane2_module_mapping[0x20];
7370
7371 u8 lane3_module_mapping[0x20];
7372
b4ff3a36 7373 u8 reserved_at_a0[0x160];
e281682b
SM		 7374};
7375
7376struct mlx5_ifc_pmaos_reg_bits {
b4ff3a36 7377 u8 reserved_at_0[0x8];
e281682b 7378 u8 module[0x8];
b4ff3a36 7379 u8 reserved_at_10[0x4];
e281682b 7380 u8 admin_status[0x4];
b4ff3a36 7381 u8 reserved_at_18[0x4];
e281682b
SM		 7382 u8 oper_status[0x4];
7383
7384 u8 ase[0x1];
7385 u8 ee[0x1];
b4ff3a36 7386 u8 reserved_at_22[0x1c];
e281682b
SM		 7387 u8 e[0x2];
7388
b4ff3a36 7389 u8 reserved_at_40[0x40];
e281682b
SM		 7390};
7391
7392struct mlx5_ifc_plpc_reg_bits {
b4ff3a36 7393 u8 reserved_at_0[0x4];
e281682b 7394 u8 profile_id[0xc];
b4ff3a36 7395 u8 reserved_at_10[0x4];
e281682b 7396 u8 proto_mask[0x4];
b4ff3a36 7397 u8 reserved_at_18[0x8];
e281682b 7398
b4ff3a36 7399 u8 reserved_at_20[0x10];
e281682b
SM		 7400 u8 lane_speed[0x10];
7401
b4ff3a36 7402 u8 reserved_at_40[0x17];
e281682b
SM		 7403 u8 lpbf[0x1];
7404 u8 fec_mode_policy[0x8];
7405
7406 u8 retransmission_capability[0x8];
7407 u8 fec_mode_capability[0x18];
7408
7409 u8 retransmission_support_admin[0x8];
7410 u8 fec_mode_support_admin[0x18];
7411
7412 u8 retransmission_request_admin[0x8];
7413 u8 fec_mode_request_admin[0x18];
7414
b4ff3a36 7415 u8 reserved_at_c0[0x80];
e281682b
SM		 7416};
7417
7418struct mlx5_ifc_plib_reg_bits {
b4ff3a36 7419 u8 reserved_at_0[0x8];
e281682b 7420 u8 local_port[0x8];
b4ff3a36 7421 u8 reserved_at_10[0x8];
e281682b
SM		 7422 u8 ib_port[0x8];
7423
b4ff3a36 7424 u8 reserved_at_20[0x60];
e281682b
SM		 7425};
7426
7427struct mlx5_ifc_plbf_reg_bits {
b4ff3a36 7428 u8 reserved_at_0[0x8];
e281682b 7429 u8 local_port[0x8];
b4ff3a36 7430 u8 reserved_at_10[0xd];
e281682b
SM		 7431 u8 lbf_mode[0x3];
7432
b4ff3a36 7433 u8 reserved_at_20[0x20];
e281682b
SM		 7434};
7435
7436struct mlx5_ifc_pipg_reg_bits {
b4ff3a36 7437 u8 reserved_at_0[0x8];
e281682b 7438 u8 local_port[0x8];
b4ff3a36 7439 u8 reserved_at_10[0x10];
e281682b
SM		 7440
7441 u8 dic[0x1];
b4ff3a36 7442 u8 reserved_at_21[0x19];
e281682b 7443 u8 ipg[0x4];
b4ff3a36 7444 u8 reserved_at_3e[0x2];
e281682b
SM		 7445};
7446
7447struct mlx5_ifc_pifr_reg_bits {
b4ff3a36 7448 u8 reserved_at_0[0x8];
e281682b 7449 u8 local_port[0x8];
b4ff3a36 7450 u8 reserved_at_10[0x10];
e281682b 7451
b4ff3a36 7452 u8 reserved_at_20[0xe0];
e281682b
SM		 7453
7454 u8 port_filter[8][0x20];
7455
7456 u8 port_filter_update_en[8][0x20];
7457};
7458
7459struct mlx5_ifc_pfcc_reg_bits {
b4ff3a36 7460 u8 reserved_at_0[0x8];
e281682b 7461 u8 local_port[0x8];
b4ff3a36 7462 u8 reserved_at_10[0x10];
e281682b
SM		 7463
7464 u8 ppan[0x4];
b4ff3a36 7465 u8 reserved_at_24[0x4];
e281682b 7466 u8 prio_mask_tx[0x8];
b4ff3a36 7467 u8 reserved_at_30[0x8];
e281682b
SM		 7468 u8 prio_mask_rx[0x8];
7469
7470 u8 pptx[0x1];
7471 u8 aptx[0x1];
b4ff3a36 7472 u8 reserved_at_42[0x6];
e281682b 7473 u8 pfctx[0x8];
b4ff3a36 7474 u8 reserved_at_50[0x10];
e281682b
SM		 7475
7476 u8 pprx[0x1];
7477 u8 aprx[0x1];
b4ff3a36 7478 u8 reserved_at_62[0x6];
e281682b 7479 u8 pfcrx[0x8];
b4ff3a36 7480 u8 reserved_at_70[0x10];
e281682b 7481
b4ff3a36 7482 u8 reserved_at_80[0x80];
e281682b
SM		 7483};
7484
7485struct mlx5_ifc_pelc_reg_bits {
7486 u8 op[0x4];
b4ff3a36 7487 u8 reserved_at_4[0x4];
e281682b 7488 u8 local_port[0x8];
b4ff3a36 7489 u8 reserved_at_10[0x10];
e281682b
SM		 7490
7491 u8 op_admin[0x8];
7492 u8 op_capability[0x8];
7493 u8 op_request[0x8];
7494 u8 op_active[0x8];
7495
7496 u8 admin[0x40];
7497
7498 u8 capability[0x40];
7499
7500 u8 request[0x40];
7501
7502 u8 active[0x40];
7503
b4ff3a36 7504 u8 reserved_at_140[0x80];
e281682b
SM		 7505};
7506
7507struct mlx5_ifc_peir_reg_bits {
b4ff3a36 7508 u8 reserved_at_0[0x8];
e281682b 7509 u8 local_port[0x8];
b4ff3a36 7510 u8 reserved_at_10[0x10];
e281682b 7511
b4ff3a36 7512 u8 reserved_at_20[0xc];
e281682b 7513 u8 error_count[0x4];
b4ff3a36 7514 u8 reserved_at_30[0x10];
e281682b 7515
b4ff3a36 7516 u8 reserved_at_40[0xc];
e281682b 7517 u8 lane[0x4];
b4ff3a36 7518 u8 reserved_at_50[0x8];
e281682b
SM		 7519 u8 error_type[0x8];
7520};
7521
cfdcbcea
GP		 7522struct mlx5_ifc_pcam_enhanced_features_bits {
7523 u8 reserved_at_0[0x7e];
7524
7525 u8 ppcnt_discard_group[0x1];
7526 u8 ppcnt_statistical_group[0x1];
7527};
7528
7529struct mlx5_ifc_pcam_reg_bits {
7530 u8 reserved_at_0[0x8];
7531 u8 feature_group[0x8];
7532 u8 reserved_at_10[0x8];
7533 u8 access_reg_group[0x8];
7534
7535 u8 reserved_at_20[0x20];
7536
7537 union {
7538 u8 reserved_at_0[0x80];
7539 } port_access_reg_cap_mask;
7540
7541 u8 reserved_at_c0[0x80];
7542
7543 union {
7544 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
7545 u8 reserved_at_0[0x80];
7546 } feature_cap_mask;
7547
7548 u8 reserved_at_1c0[0xc0];
7549};
7550
7551struct mlx5_ifc_mcam_enhanced_features_bits {
7552 u8 reserved_at_0[0x7f];
7553
7554 u8 pcie_performance_group[0x1];
7555};
7556
7557struct mlx5_ifc_mcam_reg_bits {
7558 u8 reserved_at_0[0x8];
7559 u8 feature_group[0x8];
7560 u8 reserved_at_10[0x8];
7561 u8 access_reg_group[0x8];
7562
7563 u8 reserved_at_20[0x20];
7564
7565 union {
7566 u8 reserved_at_0[0x80];
7567 } mng_access_reg_cap_mask;
7568
7569 u8 reserved_at_c0[0x80];
7570
7571 union {
7572 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
7573 u8 reserved_at_0[0x80];
7574 } mng_feature_cap_mask;
7575
7576 u8 reserved_at_1c0[0x80];
7577};
7578
e281682b 7579struct mlx5_ifc_pcap_reg_bits {
b4ff3a36 7580 u8 reserved_at_0[0x8];
e281682b 7581 u8 local_port[0x8];
b4ff3a36 7582 u8 reserved_at_10[0x10];
e281682b
SM		 7583
7584 u8 port_capability_mask[4][0x20];
7585};
7586
7587struct mlx5_ifc_paos_reg_bits {
7588 u8 swid[0x8];
7589 u8 local_port[0x8];
b4ff3a36 7590 u8 reserved_at_10[0x4];
e281682b 7591 u8 admin_status[0x4];
b4ff3a36 7592 u8 reserved_at_18[0x4];
e281682b
SM		 7593 u8 oper_status[0x4];
7594
7595 u8 ase[0x1];
7596 u8 ee[0x1];
b4ff3a36 7597 u8 reserved_at_22[0x1c];
e281682b
SM		 7598 u8 e[0x2];
7599
b4ff3a36 7600 u8 reserved_at_40[0x40];
e281682b
SM		 7601};
7602
7603struct mlx5_ifc_pamp_reg_bits {
b4ff3a36 7604 u8 reserved_at_0[0x8];
e281682b 7605 u8 opamp_group[0x8];
b4ff3a36 7606 u8 reserved_at_10[0xc];
e281682b
SM		 7607 u8 opamp_group_type[0x4];
7608
7609 u8 start_index[0x10];
b4ff3a36 7610 u8 reserved_at_30[0x4];
e281682b
SM		 7611 u8 num_of_indices[0xc];
7612
7613 u8 index_data[18][0x10];
7614};
7615
7d5e1423
SM		 7616struct mlx5_ifc_pcmr_reg_bits {
7617 u8 reserved_at_0[0x8];
7618 u8 local_port[0x8];
7619 u8 reserved_at_10[0x2e];
7620 u8 fcs_cap[0x1];
7621 u8 reserved_at_3f[0x1f];
7622 u8 fcs_chk[0x1];
7623 u8 reserved_at_5f[0x1];
7624};
7625
e281682b 7626struct mlx5_ifc_lane_2_module_mapping_bits {
b4ff3a36 7627 u8 reserved_at_0[0x6];
e281682b 7628 u8 rx_lane[0x2];
b4ff3a36 7629 u8 reserved_at_8[0x6];
e281682b 7630 u8 tx_lane[0x2];
b4ff3a36 7631 u8 reserved_at_10[0x8];
e281682b
SM		 7632 u8 module[0x8];
7633};
7634
7635struct mlx5_ifc_bufferx_reg_bits {
b4ff3a36 7636 u8 reserved_at_0[0x6];
e281682b
SM		 7637 u8 lossy[0x1];
7638 u8 epsb[0x1];
b4ff3a36 7639 u8 reserved_at_8[0xc];
e281682b
SM		 7640 u8 size[0xc];
7641
7642 u8 xoff_threshold[0x10];
7643 u8 xon_threshold[0x10];
7644};
7645
7646struct mlx5_ifc_set_node_in_bits {
7647 u8 node_description[64][0x8];
7648};
7649
7650struct mlx5_ifc_register_power_settings_bits {
b4ff3a36 7651 u8 reserved_at_0[0x18];
e281682b
SM		 7652 u8 power_settings_level[0x8];
7653
b4ff3a36 7654 u8 reserved_at_20[0x60];
e281682b
SM		 7655};
7656
7657struct mlx5_ifc_register_host_endianness_bits {
7658 u8 he[0x1];
b4ff3a36 7659 u8 reserved_at_1[0x1f];
e281682b 7660
b4ff3a36 7661 u8 reserved_at_20[0x60];
e281682b
SM		 7662};
7663
7664struct mlx5_ifc_umr_pointer_desc_argument_bits {
b4ff3a36 7665 u8 reserved_at_0[0x20];
e281682b
SM		 7666
7667 u8 mkey[0x20];
7668
7669 u8 addressh_63_32[0x20];
7670
7671 u8 addressl_31_0[0x20];
7672};
7673
7674struct mlx5_ifc_ud_adrs_vector_bits {
7675 u8 dc_key[0x40];
7676
7677 u8 ext[0x1];
b4ff3a36 7678 u8 reserved_at_41[0x7];
e281682b
SM		 7679 u8 destination_qp_dct[0x18];
7680
7681 u8 static_rate[0x4];
7682 u8 sl_eth_prio[0x4];
7683 u8 fl[0x1];
7684 u8 mlid[0x7];
7685 u8 rlid_udp_sport[0x10];
7686
b4ff3a36 7687 u8 reserved_at_80[0x20];
e281682b
SM		 7688
7689 u8 rmac_47_16[0x20];
7690
7691 u8 rmac_15_0[0x10];
7692 u8 tclass[0x8];
7693 u8 hop_limit[0x8];
7694
b4ff3a36 7695 u8 reserved_at_e0[0x1];
e281682b 7696 u8 grh[0x1];
b4ff3a36 7697 u8 reserved_at_e2[0x2];
e281682b
SM		 7698 u8 src_addr_index[0x8];
7699 u8 flow_label[0x14];
7700
7701 u8 rgid_rip[16][0x8];
7702};
7703
7704struct mlx5_ifc_pages_req_event_bits {
b4ff3a36 7705 u8 reserved_at_0[0x10];
e281682b
SM		 7706 u8 function_id[0x10];
7707
7708 u8 num_pages[0x20];
7709
b4ff3a36 7710 u8 reserved_at_40[0xa0];
e281682b
SM		 7711};
7712
7713struct mlx5_ifc_eqe_bits {
b4ff3a36 7714 u8 reserved_at_0[0x8];
e281682b 7715 u8 event_type[0x8];
b4ff3a36 7716 u8 reserved_at_10[0x8];
e281682b
SM		 7717 u8 event_sub_type[0x8];
7718
b4ff3a36 7719 u8 reserved_at_20[0xe0];
e281682b
SM		 7720
7721 union mlx5_ifc_event_auto_bits event_data;
7722
b4ff3a36 7723 u8 reserved_at_1e0[0x10];
e281682b 7724 u8 signature[0x8];
b4ff3a36 7725 u8 reserved_at_1f8[0x7];
e281682b
SM		 7726 u8 owner[0x1];
7727};
7728
7729enum {
7730 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
7731};
7732
7733struct mlx5_ifc_cmd_queue_entry_bits {
7734 u8 type[0x8];
b4ff3a36 7735 u8 reserved_at_8[0x18];
e281682b
SM		 7736
7737 u8 input_length[0x20];
7738
7739 u8 input_mailbox_pointer_63_32[0x20];
7740
7741 u8 input_mailbox_pointer_31_9[0x17];
b4ff3a36 7742 u8 reserved_at_77[0x9];
e281682b
SM		 7743
7744 u8 command_input_inline_data[16][0x8];
7745
7746 u8 command_output_inline_data[16][0x8];
7747
7748 u8 output_mailbox_pointer_63_32[0x20];
7749
7750 u8 output_mailbox_pointer_31_9[0x17];
b4ff3a36 7751 u8 reserved_at_1b7[0x9];
e281682b
SM		 7752
7753 u8 output_length[0x20];
7754
7755 u8 token[0x8];
7756 u8 signature[0x8];
b4ff3a36 7757 u8 reserved_at_1f0[0x8];
e281682b
SM		 7758 u8 status[0x7];
7759 u8 ownership[0x1];
7760};
7761
7762struct mlx5_ifc_cmd_out_bits {
7763 u8 status[0x8];
b4ff3a36 7764 u8 reserved_at_8[0x18];
e281682b
SM		 7765
7766 u8 syndrome[0x20];
7767
7768 u8 command_output[0x20];
7769};
7770
7771struct mlx5_ifc_cmd_in_bits {
7772 u8 opcode[0x10];
b4ff3a36 7773 u8 reserved_at_10[0x10];
e281682b 7774
b4ff3a36 7775 u8 reserved_at_20[0x10];
e281682b
SM		 7776 u8 op_mod[0x10];
7777
7778 u8 command[0][0x20];
7779};
7780
7781struct mlx5_ifc_cmd_if_box_bits {
7782 u8 mailbox_data[512][0x8];
7783
b4ff3a36 7784 u8 reserved_at_1000[0x180];
e281682b
SM		 7785
7786 u8 next_pointer_63_32[0x20];
7787
7788 u8 next_pointer_31_10[0x16];
b4ff3a36 7789 u8 reserved_at_11b6[0xa];
e281682b
SM		 7790
7791 u8 block_number[0x20];
7792
b4ff3a36 7793 u8 reserved_at_11e0[0x8];
e281682b
SM		 7794 u8 token[0x8];
7795 u8 ctrl_signature[0x8];
7796 u8 signature[0x8];
7797};
7798
7799struct mlx5_ifc_mtt_bits {
7800 u8 ptag_63_32[0x20];
7801
7802 u8 ptag_31_8[0x18];
b4ff3a36 7803 u8 reserved_at_38[0x6];
e281682b
SM		 7804 u8 wr_en[0x1];
7805 u8 rd_en[0x1];
7806};
7807
928cfe87
TT		 7808struct mlx5_ifc_query_wol_rol_out_bits {
7809 u8 status[0x8];
7810 u8 reserved_at_8[0x18];
7811
7812 u8 syndrome[0x20];
7813
7814 u8 reserved_at_40[0x10];
7815 u8 rol_mode[0x8];
7816 u8 wol_mode[0x8];
7817
7818 u8 reserved_at_60[0x20];
7819};
7820
7821struct mlx5_ifc_query_wol_rol_in_bits {
7822 u8 opcode[0x10];
7823 u8 reserved_at_10[0x10];
7824
7825 u8 reserved_at_20[0x10];
7826 u8 op_mod[0x10];
7827
7828 u8 reserved_at_40[0x40];
7829};
7830
7831struct mlx5_ifc_set_wol_rol_out_bits {
7832 u8 status[0x8];
7833 u8 reserved_at_8[0x18];
7834
7835 u8 syndrome[0x20];
7836
7837 u8 reserved_at_40[0x40];
7838};
7839
7840struct mlx5_ifc_set_wol_rol_in_bits {
7841 u8 opcode[0x10];
7842 u8 reserved_at_10[0x10];
7843
7844 u8 reserved_at_20[0x10];
7845 u8 op_mod[0x10];
7846
7847 u8 rol_mode_valid[0x1];
7848 u8 wol_mode_valid[0x1];
7849 u8 reserved_at_42[0xe];
7850 u8 rol_mode[0x8];
7851 u8 wol_mode[0x8];
7852
7853 u8 reserved_at_60[0x20];
7854};
7855
e281682b
SM		 7856enum {
7857 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
7858 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
7859 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
7860};
7861
7862enum {
7863 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
7864 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
7865 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
7866};
7867
7868enum {
7869 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
7870 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
7871 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
7872 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
7873 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
7874 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
7875 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
7876 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
7877 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
7878 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
7879 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
7880};
7881
7882struct mlx5_ifc_initial_seg_bits {
7883 u8 fw_rev_minor[0x10];
7884 u8 fw_rev_major[0x10];
7885
7886 u8 cmd_interface_rev[0x10];
7887 u8 fw_rev_subminor[0x10];
7888
b4ff3a36 7889 u8 reserved_at_40[0x40];
e281682b
SM		 7890
7891 u8 cmdq_phy_addr_63_32[0x20];
7892
7893 u8 cmdq_phy_addr_31_12[0x14];
b4ff3a36 7894 u8 reserved_at_b4[0x2];
e281682b
SM		 7895 u8 nic_interface[0x2];
7896 u8 log_cmdq_size[0x4];
7897 u8 log_cmdq_stride[0x4];
7898
7899 u8 command_doorbell_vector[0x20];
7900
b4ff3a36 7901 u8 reserved_at_e0[0xf00];
e281682b
SM		 7902
7903 u8 initializing[0x1];
b4ff3a36 7904 u8 reserved_at_fe1[0x4];
e281682b 7905 u8 nic_interface_supported[0x3];
b4ff3a36 7906 u8 reserved_at_fe8[0x18];
e281682b
SM		 7907
7908 struct mlx5_ifc_health_buffer_bits health_buffer;
7909
7910 u8 no_dram_nic_offset[0x20];
7911
b4ff3a36 7912 u8 reserved_at_1220[0x6e40];
e281682b 7913
b4ff3a36 7914 u8 reserved_at_8060[0x1f];
e281682b
SM		 7915 u8 clear_int[0x1];
7916
7917 u8 health_syndrome[0x8];
7918 u8 health_counter[0x18];
7919
b4ff3a36 7920 u8 reserved_at_80a0[0x17fc0];
e281682b
SM		 7921};
7922
f9a1ef72
EE		 7923struct mlx5_ifc_mtpps_reg_bits {
7924 u8 reserved_at_0[0xc];
7925 u8 cap_number_of_pps_pins[0x4];
7926 u8 reserved_at_10[0x4];
7927 u8 cap_max_num_of_pps_in_pins[0x4];
7928 u8 reserved_at_18[0x4];
7929 u8 cap_max_num_of_pps_out_pins[0x4];
7930
7931 u8 reserved_at_20[0x24];
7932 u8 cap_pin_3_mode[0x4];
7933 u8 reserved_at_48[0x4];
7934 u8 cap_pin_2_mode[0x4];
7935 u8 reserved_at_50[0x4];
7936 u8 cap_pin_1_mode[0x4];
7937 u8 reserved_at_58[0x4];
7938 u8 cap_pin_0_mode[0x4];
7939
7940 u8 reserved_at_60[0x4];
7941 u8 cap_pin_7_mode[0x4];
7942 u8 reserved_at_68[0x4];
7943 u8 cap_pin_6_mode[0x4];
7944 u8 reserved_at_70[0x4];
7945 u8 cap_pin_5_mode[0x4];
7946 u8 reserved_at_78[0x4];
7947 u8 cap_pin_4_mode[0x4];
7948
7949 u8 reserved_at_80[0x80];
7950
7951 u8 enable[0x1];
7952 u8 reserved_at_101[0xb];
7953 u8 pattern[0x4];
7954 u8 reserved_at_110[0x4];
7955 u8 pin_mode[0x4];
7956 u8 pin[0x8];
7957
7958 u8 reserved_at_120[0x20];
7959
7960 u8 time_stamp[0x40];
7961
7962 u8 out_pulse_duration[0x10];
7963 u8 out_periodic_adjustment[0x10];
7964
7965 u8 reserved_at_1a0[0x60];
7966};
7967
7968struct mlx5_ifc_mtppse_reg_bits {
7969 u8 reserved_at_0[0x18];
7970 u8 pin[0x8];
7971 u8 event_arm[0x1];
7972 u8 reserved_at_21[0x1b];
7973 u8 event_generation_mode[0x4];
7974 u8 reserved_at_40[0x40];
7975};
7976
e281682b
SM		 7977union mlx5_ifc_ports_control_registers_document_bits {
7978 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
7979 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
7980 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
7981 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
7982 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
7983 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
7984 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
7985 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
7986 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
7987 struct mlx5_ifc_pamp_reg_bits pamp_reg;
7988 struct mlx5_ifc_paos_reg_bits paos_reg;
7989 struct mlx5_ifc_pcap_reg_bits pcap_reg;
7990 struct mlx5_ifc_peir_reg_bits peir_reg;
7991 struct mlx5_ifc_pelc_reg_bits pelc_reg;
7992 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
1c64bf6f 7993 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b
SM		 7994 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
7995 struct mlx5_ifc_pifr_reg_bits pifr_reg;
7996 struct mlx5_ifc_pipg_reg_bits pipg_reg;
7997 struct mlx5_ifc_plbf_reg_bits plbf_reg;
7998 struct mlx5_ifc_plib_reg_bits plib_reg;
7999 struct mlx5_ifc_plpc_reg_bits plpc_reg;
8000 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
8001 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
8002 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
8003 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
8004 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
8005 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
8006 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
8007 struct mlx5_ifc_ppad_reg_bits ppad_reg;
8008 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
8009 struct mlx5_ifc_pplm_reg_bits pplm_reg;
8010 struct mlx5_ifc_pplr_reg_bits pplr_reg;
8011 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
8012 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
8013 struct mlx5_ifc_pspa_reg_bits pspa_reg;
8014 struct mlx5_ifc_ptas_reg_bits ptas_reg;
8015 struct mlx5_ifc_ptys_reg_bits ptys_reg;
7d5e1423 8016 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
e281682b
SM		 8017 struct mlx5_ifc_pude_reg_bits pude_reg;
8018 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
8019 struct mlx5_ifc_slrg_reg_bits slrg_reg;
8020 struct mlx5_ifc_sltp_reg_bits sltp_reg;
f9a1ef72
EE		 8021 struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
8022 struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
b4ff3a36 8023 u8 reserved_at_0[0x60e0];
e281682b
SM		 8024};
8025
8026union mlx5_ifc_debug_enhancements_document_bits {
8027 struct mlx5_ifc_health_buffer_bits health_buffer;
b4ff3a36 8028 u8 reserved_at_0[0x200];
e281682b
SM		 8029};
8030
8031union mlx5_ifc_uplink_pci_interface_document_bits {
8032 struct mlx5_ifc_initial_seg_bits initial_seg;
b4ff3a36 8033 u8 reserved_at_0[0x20060];
b775516b
EC		 8034};
8035
2cc43b49
MG		 8036struct mlx5_ifc_set_flow_table_root_out_bits {
8037 u8 status[0x8];
b4ff3a36 8038 u8 reserved_at_8[0x18];
2cc43b49
MG		 8039
8040 u8 syndrome[0x20];
8041
b4ff3a36 8042 u8 reserved_at_40[0x40];
2cc43b49
MG		 8043};
8044
8045struct mlx5_ifc_set_flow_table_root_in_bits {
8046 u8 opcode[0x10];
b4ff3a36 8047 u8 reserved_at_10[0x10];
2cc43b49 8048
b4ff3a36 8049 u8 reserved_at_20[0x10];
2cc43b49
MG		 8050 u8 op_mod[0x10];
8051
7d5e1423
SM		 8052 u8 other_vport[0x1];
8053 u8 reserved_at_41[0xf];
8054 u8 vport_number[0x10];
8055
8056 u8 reserved_at_60[0x20];
2cc43b49
MG		 8057
8058 u8 table_type[0x8];
b4ff3a36 8059 u8 reserved_at_88[0x18];
2cc43b49 8060
b4ff3a36 8061 u8 reserved_at_a0[0x8];
2cc43b49
MG		 8062 u8 table_id[0x18];
8063
b4ff3a36 8064 u8 reserved_at_c0[0x140];
2cc43b49
MG		 8065};
8066
34a40e68 8067enum {
84df61eb
AH		 8068 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
8069 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
34a40e68
MG		 8070};
8071
8072struct mlx5_ifc_modify_flow_table_out_bits {
8073 u8 status[0x8];
b4ff3a36 8074 u8 reserved_at_8[0x18];
34a40e68
MG		 8075
8076 u8 syndrome[0x20];
8077
b4ff3a36 8078 u8 reserved_at_40[0x40];
34a40e68
MG		 8079};
8080
8081struct mlx5_ifc_modify_flow_table_in_bits {
8082 u8 opcode[0x10];
b4ff3a36 8083 u8 reserved_at_10[0x10];
34a40e68 8084
b4ff3a36 8085 u8 reserved_at_20[0x10];
34a40e68
MG		 8086 u8 op_mod[0x10];
8087
7d5e1423
SM		 8088 u8 other_vport[0x1];
8089 u8 reserved_at_41[0xf];
8090 u8 vport_number[0x10];
34a40e68 8091
b4ff3a36 8092 u8 reserved_at_60[0x10];
34a40e68
MG		 8093 u8 modify_field_select[0x10];
8094
8095 u8 table_type[0x8];
b4ff3a36 8096 u8 reserved_at_88[0x18];
34a40e68 8097
b4ff3a36 8098 u8 reserved_at_a0[0x8];
34a40e68
MG		 8099 u8 table_id[0x18];
8100
b4ff3a36 8101 u8 reserved_at_c0[0x4];
34a40e68 8102 u8 table_miss_mode[0x4];
b4ff3a36 8103 u8 reserved_at_c8[0x18];
34a40e68 8104
b4ff3a36 8105 u8 reserved_at_e0[0x8];
34a40e68
MG		 8106 u8 table_miss_id[0x18];
8107
84df61eb
AH		 8108 u8 reserved_at_100[0x8];
8109 u8 lag_master_next_table_id[0x18];
8110
8111 u8 reserved_at_120[0x80];
34a40e68
MG		 8112};
8113
4f3961ee
SM		 8114struct mlx5_ifc_ets_tcn_config_reg_bits {
8115 u8 g[0x1];
8116 u8 b[0x1];
8117 u8 r[0x1];
8118 u8 reserved_at_3[0x9];
8119 u8 group[0x4];
8120 u8 reserved_at_10[0x9];
8121 u8 bw_allocation[0x7];
8122
8123 u8 reserved_at_20[0xc];
8124 u8 max_bw_units[0x4];
8125 u8 reserved_at_30[0x8];
8126 u8 max_bw_value[0x8];
8127};
8128
8129struct mlx5_ifc_ets_global_config_reg_bits {
8130 u8 reserved_at_0[0x2];
8131 u8 r[0x1];
8132 u8 reserved_at_3[0x1d];
8133
8134 u8 reserved_at_20[0xc];
8135 u8 max_bw_units[0x4];
8136 u8 reserved_at_30[0x8];
8137 u8 max_bw_value[0x8];
8138};
8139
8140struct mlx5_ifc_qetc_reg_bits {
8141 u8 reserved_at_0[0x8];
8142 u8 port_number[0x8];
8143 u8 reserved_at_10[0x30];
8144
8145 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
8146 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
8147};
8148
8149struct mlx5_ifc_qtct_reg_bits {
8150 u8 reserved_at_0[0x8];
8151 u8 port_number[0x8];
8152 u8 reserved_at_10[0xd];
8153 u8 prio[0x3];
8154
8155 u8 reserved_at_20[0x1d];
8156 u8 tclass[0x3];
8157};
8158
7d5e1423
SM		 8159struct mlx5_ifc_mcia_reg_bits {
8160 u8 l[0x1];
8161 u8 reserved_at_1[0x7];
8162 u8 module[0x8];
8163 u8 reserved_at_10[0x8];
8164 u8 status[0x8];
8165
8166 u8 i2c_device_address[0x8];
8167 u8 page_number[0x8];
8168 u8 device_address[0x10];
8169
8170 u8 reserved_at_40[0x10];
8171 u8 size[0x10];
8172
8173 u8 reserved_at_60[0x20];
8174
8175 u8 dword_0[0x20];
8176 u8 dword_1[0x20];
8177 u8 dword_2[0x20];
8178 u8 dword_3[0x20];
8179 u8 dword_4[0x20];
8180 u8 dword_5[0x20];
8181 u8 dword_6[0x20];
8182 u8 dword_7[0x20];
8183 u8 dword_8[0x20];
8184 u8 dword_9[0x20];
8185 u8 dword_10[0x20];
8186 u8 dword_11[0x20];
8187};
8188
7486216b
SM		 8189struct mlx5_ifc_dcbx_param_bits {
8190 u8 dcbx_cee_cap[0x1];
8191 u8 dcbx_ieee_cap[0x1];
8192 u8 dcbx_standby_cap[0x1];
8193 u8 reserved_at_0[0x5];
8194 u8 port_number[0x8];
8195 u8 reserved_at_10[0xa];
8196 u8 max_application_table_size[6];
8197 u8 reserved_at_20[0x15];
8198 u8 version_oper[0x3];
8199 u8 reserved_at_38[5];
8200 u8 version_admin[0x3];
8201 u8 willing_admin[0x1];
8202 u8 reserved_at_41[0x3];
8203 u8 pfc_cap_oper[0x4];
8204 u8 reserved_at_48[0x4];
8205 u8 pfc_cap_admin[0x4];
8206 u8 reserved_at_50[0x4];
8207 u8 num_of_tc_oper[0x4];
8208 u8 reserved_at_58[0x4];
8209 u8 num_of_tc_admin[0x4];
8210 u8 remote_willing[0x1];
8211 u8 reserved_at_61[3];
8212 u8 remote_pfc_cap[4];
8213 u8 reserved_at_68[0x14];
8214 u8 remote_num_of_tc[0x4];
8215 u8 reserved_at_80[0x18];
8216 u8 error[0x8];
8217 u8 reserved_at_a0[0x160];
8218};
84df61eb
AH		 8219
8220struct mlx5_ifc_lagc_bits {
8221 u8 reserved_at_0[0x1d];
8222 u8 lag_state[0x3];
8223
8224 u8 reserved_at_20[0x14];
8225 u8 tx_remap_affinity_2[0x4];
8226 u8 reserved_at_38[0x4];
8227 u8 tx_remap_affinity_1[0x4];
8228};
8229
8230struct mlx5_ifc_create_lag_out_bits {
8231 u8 status[0x8];
8232 u8 reserved_at_8[0x18];
8233
8234 u8 syndrome[0x20];
8235
8236 u8 reserved_at_40[0x40];
8237};
8238
8239struct mlx5_ifc_create_lag_in_bits {
8240 u8 opcode[0x10];
8241 u8 reserved_at_10[0x10];
8242
8243 u8 reserved_at_20[0x10];
8244 u8 op_mod[0x10];
8245
8246 struct mlx5_ifc_lagc_bits ctx;
8247};
8248
8249struct mlx5_ifc_modify_lag_out_bits {
8250 u8 status[0x8];
8251 u8 reserved_at_8[0x18];
8252
8253 u8 syndrome[0x20];
8254
8255 u8 reserved_at_40[0x40];
8256};
8257
8258struct mlx5_ifc_modify_lag_in_bits {
8259 u8 opcode[0x10];
8260 u8 reserved_at_10[0x10];
8261
8262 u8 reserved_at_20[0x10];
8263 u8 op_mod[0x10];
8264
8265 u8 reserved_at_40[0x20];
8266 u8 field_select[0x20];
8267
8268 struct mlx5_ifc_lagc_bits ctx;
8269};
8270
8271struct mlx5_ifc_query_lag_out_bits {
8272 u8 status[0x8];
8273 u8 reserved_at_8[0x18];
8274
8275 u8 syndrome[0x20];
8276
8277 u8 reserved_at_40[0x40];
8278
8279 struct mlx5_ifc_lagc_bits ctx;
8280};
8281
8282struct mlx5_ifc_query_lag_in_bits {
8283 u8 opcode[0x10];
8284 u8 reserved_at_10[0x10];
8285
8286 u8 reserved_at_20[0x10];
8287 u8 op_mod[0x10];
8288
8289 u8 reserved_at_40[0x40];
8290};
8291
8292struct mlx5_ifc_destroy_lag_out_bits {
8293 u8 status[0x8];
8294 u8 reserved_at_8[0x18];
8295
8296 u8 syndrome[0x20];
8297
8298 u8 reserved_at_40[0x40];
8299};
8300
8301struct mlx5_ifc_destroy_lag_in_bits {
8302 u8 opcode[0x10];
8303 u8 reserved_at_10[0x10];
8304
8305 u8 reserved_at_20[0x10];
8306 u8 op_mod[0x10];
8307
8308 u8 reserved_at_40[0x40];
8309};
8310
8311struct mlx5_ifc_create_vport_lag_out_bits {
8312 u8 status[0x8];
8313 u8 reserved_at_8[0x18];
8314
8315 u8 syndrome[0x20];
8316
8317 u8 reserved_at_40[0x40];
8318};
8319
8320struct mlx5_ifc_create_vport_lag_in_bits {
8321 u8 opcode[0x10];
8322 u8 reserved_at_10[0x10];
8323
8324 u8 reserved_at_20[0x10];
8325 u8 op_mod[0x10];
8326
8327 u8 reserved_at_40[0x40];
8328};
8329
8330struct mlx5_ifc_destroy_vport_lag_out_bits {
8331 u8 status[0x8];
8332 u8 reserved_at_8[0x18];
8333
8334 u8 syndrome[0x20];
8335
8336 u8 reserved_at_40[0x40];
8337};
8338
8339struct mlx5_ifc_destroy_vport_lag_in_bits {
8340 u8 opcode[0x10];
8341 u8 reserved_at_10[0x10];
8342
8343 u8 reserved_at_20[0x10];
8344 u8 op_mod[0x10];
8345
8346 u8 reserved_at_40[0x40];
8347};
8348
d29b796a 8349#endif /* MLX5_IFC_H */
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