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net/mlx5: Add MLX5_SET16 and MLX5_GET16
[mirror_ubuntu-bionic-kernel.git] / include / linux / mlx5 / mlx5_ifc.h
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d29b796a 1/*
e281682b 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
d29b796a
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
e281682b 31*/
d29b796a
EC		 32#ifndef MLX5_IFC_H
33#define MLX5_IFC_H
34
e29341fb
IT		 35#include "mlx5_ifc_fpga.h"
36
e281682b
SM		 37enum {
38 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
39 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
40 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
41 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
42 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
43 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
44 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
45 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
46 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
47 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
48 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
49 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
50 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
51 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
52 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
53 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
54 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
55 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
56 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
57 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
58 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
59 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
60 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
e29341fb
IT		 61 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb,
62 MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20,
e281682b
SM		 63};
64
65enum {
66 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
67 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
68 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
69 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
70};
71
f91e6d89
EBE		 72enum {
73 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
74 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
75};
76
d29b796a
EC		 77enum {
78 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
79 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
80 MLX5_CMD_OP_INIT_HCA = 0x102,
81 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
82 MLX5_CMD_OP_ENABLE_HCA = 0x104,
83 MLX5_CMD_OP_DISABLE_HCA = 0x105,
84 MLX5_CMD_OP_QUERY_PAGES = 0x107,
85 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
86 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
e281682b
SM		 87 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
88 MLX5_CMD_OP_SET_ISSI = 0x10b,
0dbc6fe0 89 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
d29b796a
EC		 90 MLX5_CMD_OP_CREATE_MKEY = 0x200,
91 MLX5_CMD_OP_QUERY_MKEY = 0x201,
92 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
93 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
94 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
95 MLX5_CMD_OP_CREATE_EQ = 0x301,
96 MLX5_CMD_OP_DESTROY_EQ = 0x302,
97 MLX5_CMD_OP_QUERY_EQ = 0x303,
98 MLX5_CMD_OP_GEN_EQE = 0x304,
99 MLX5_CMD_OP_CREATE_CQ = 0x400,
100 MLX5_CMD_OP_DESTROY_CQ = 0x401,
101 MLX5_CMD_OP_QUERY_CQ = 0x402,
102 MLX5_CMD_OP_MODIFY_CQ = 0x403,
103 MLX5_CMD_OP_CREATE_QP = 0x500,
104 MLX5_CMD_OP_DESTROY_QP = 0x501,
105 MLX5_CMD_OP_RST2INIT_QP = 0x502,
106 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
107 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
108 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
109 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
110 MLX5_CMD_OP_2ERR_QP = 0x507,
111 MLX5_CMD_OP_2RST_QP = 0x50a,
112 MLX5_CMD_OP_QUERY_QP = 0x50b,
e281682b 113 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
d29b796a
EC		 114 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
115 MLX5_CMD_OP_CREATE_PSV = 0x600,
116 MLX5_CMD_OP_DESTROY_PSV = 0x601,
117 MLX5_CMD_OP_CREATE_SRQ = 0x700,
118 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
119 MLX5_CMD_OP_QUERY_SRQ = 0x702,
120 MLX5_CMD_OP_ARM_RQ = 0x703,
e281682b
SM		 121 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
122 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
123 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
124 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
d29b796a
EC		 125 MLX5_CMD_OP_CREATE_DCT = 0x710,
126 MLX5_CMD_OP_DESTROY_DCT = 0x711,
127 MLX5_CMD_OP_DRAIN_DCT = 0x712,
128 MLX5_CMD_OP_QUERY_DCT = 0x713,
129 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
7486216b
SM		 130 MLX5_CMD_OP_CREATE_XRQ = 0x717,
131 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
132 MLX5_CMD_OP_QUERY_XRQ = 0x719,
133 MLX5_CMD_OP_ARM_XRQ = 0x71a,
d29b796a
EC		 134 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
135 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
136 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
137 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
138 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
139 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
e281682b 140 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
d29b796a 141 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
e281682b
SM		 142 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
143 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
144 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
145 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
d29b796a
EC		 146 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
147 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
148 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
149 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
7486216b
SM		 150 MLX5_CMD_OP_SET_RATE_LIMIT = 0x780,
151 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
813f8540
MHY		 152 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
153 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
154 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
155 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
156 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
157 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
d29b796a
EC		 158 MLX5_CMD_OP_ALLOC_PD = 0x800,
159 MLX5_CMD_OP_DEALLOC_PD = 0x801,
160 MLX5_CMD_OP_ALLOC_UAR = 0x802,
161 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
162 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
163 MLX5_CMD_OP_ACCESS_REG = 0x805,
164 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
20bb566b 165 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
d29b796a
EC		 166 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
167 MLX5_CMD_OP_MAD_IFC = 0x50d,
168 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
169 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
170 MLX5_CMD_OP_NOP = 0x80d,
171 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
172 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
e281682b
SM		 173 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
174 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
175 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
176 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
177 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
178 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
179 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
180 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
181 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
182 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
183 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
184 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
928cfe87
TT		 185 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
186 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
84df61eb
AH		 187 MLX5_CMD_OP_CREATE_LAG = 0x840,
188 MLX5_CMD_OP_MODIFY_LAG = 0x841,
189 MLX5_CMD_OP_QUERY_LAG = 0x842,
190 MLX5_CMD_OP_DESTROY_LAG = 0x843,
191 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
192 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
d29b796a
EC		 193 MLX5_CMD_OP_CREATE_TIR = 0x900,
194 MLX5_CMD_OP_MODIFY_TIR = 0x901,
195 MLX5_CMD_OP_DESTROY_TIR = 0x902,
196 MLX5_CMD_OP_QUERY_TIR = 0x903,
d29b796a
EC		 197 MLX5_CMD_OP_CREATE_SQ = 0x904,
198 MLX5_CMD_OP_MODIFY_SQ = 0x905,
199 MLX5_CMD_OP_DESTROY_SQ = 0x906,
200 MLX5_CMD_OP_QUERY_SQ = 0x907,
201 MLX5_CMD_OP_CREATE_RQ = 0x908,
202 MLX5_CMD_OP_MODIFY_RQ = 0x909,
c1e0bfc1 203 MLX5_CMD_OP_SET_DELAY_DROP_PARAMS = 0x910,
d29b796a
EC		 204 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
205 MLX5_CMD_OP_QUERY_RQ = 0x90b,
206 MLX5_CMD_OP_CREATE_RMP = 0x90c,
207 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
208 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
209 MLX5_CMD_OP_QUERY_RMP = 0x90f,
e281682b
SM		 210 MLX5_CMD_OP_CREATE_TIS = 0x912,
211 MLX5_CMD_OP_MODIFY_TIS = 0x913,
212 MLX5_CMD_OP_DESTROY_TIS = 0x914,
213 MLX5_CMD_OP_QUERY_TIS = 0x915,
214 MLX5_CMD_OP_CREATE_RQT = 0x916,
215 MLX5_CMD_OP_MODIFY_RQT = 0x917,
216 MLX5_CMD_OP_DESTROY_RQT = 0x918,
217 MLX5_CMD_OP_QUERY_RQT = 0x919,
2cc43b49 218 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
e281682b
SM		 219 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
220 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
221 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
222 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
223 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
224 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
225 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
226 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
34a40e68 227 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
9dc0b289
AV		 228 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
229 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
230 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
86d56a1a 231 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
7adbde20
HHZ		 232 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d,
233 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e,
2a69cb9f
OG		 234 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940,
235 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
6062118d
IT		 236 MLX5_CMD_OP_FPGA_CREATE_QP = 0x960,
237 MLX5_CMD_OP_FPGA_MODIFY_QP = 0x961,
238 MLX5_CMD_OP_FPGA_QUERY_QP = 0x962,
239 MLX5_CMD_OP_FPGA_DESTROY_QP = 0x963,
240 MLX5_CMD_OP_FPGA_QUERY_QP_COUNTERS = 0x964,
86d56a1a 241 MLX5_CMD_OP_MAX
e281682b
SM		 242};
243
244struct mlx5_ifc_flow_table_fields_supported_bits {
245 u8 outer_dmac[0x1];
246 u8 outer_smac[0x1];
247 u8 outer_ether_type[0x1];
19cc7524 248 u8 outer_ip_version[0x1];
e281682b
SM		 249 u8 outer_first_prio[0x1];
250 u8 outer_first_cfi[0x1];
251 u8 outer_first_vid[0x1];
a8ade55f 252 u8 outer_ipv4_ttl[0x1];
e281682b
SM		 253 u8 outer_second_prio[0x1];
254 u8 outer_second_cfi[0x1];
255 u8 outer_second_vid[0x1];
b4ff3a36 256 u8 reserved_at_b[0x1];
e281682b
SM		 257 u8 outer_sip[0x1];
258 u8 outer_dip[0x1];
259 u8 outer_frag[0x1];
260 u8 outer_ip_protocol[0x1];
261 u8 outer_ip_ecn[0x1];
262 u8 outer_ip_dscp[0x1];
263 u8 outer_udp_sport[0x1];
264 u8 outer_udp_dport[0x1];
265 u8 outer_tcp_sport[0x1];
266 u8 outer_tcp_dport[0x1];
267 u8 outer_tcp_flags[0x1];
268 u8 outer_gre_protocol[0x1];
269 u8 outer_gre_key[0x1];
270 u8 outer_vxlan_vni[0x1];
b4ff3a36 271 u8 reserved_at_1a[0x5];
e281682b
SM		 272 u8 source_eswitch_port[0x1];
273
274 u8 inner_dmac[0x1];
275 u8 inner_smac[0x1];
276 u8 inner_ether_type[0x1];
19cc7524 277 u8 inner_ip_version[0x1];
e281682b
SM		 278 u8 inner_first_prio[0x1];
279 u8 inner_first_cfi[0x1];
280 u8 inner_first_vid[0x1];
b4ff3a36 281 u8 reserved_at_27[0x1];
e281682b
SM		 282 u8 inner_second_prio[0x1];
283 u8 inner_second_cfi[0x1];
284 u8 inner_second_vid[0x1];
b4ff3a36 285 u8 reserved_at_2b[0x1];
e281682b
SM		 286 u8 inner_sip[0x1];
287 u8 inner_dip[0x1];
288 u8 inner_frag[0x1];
289 u8 inner_ip_protocol[0x1];
290 u8 inner_ip_ecn[0x1];
291 u8 inner_ip_dscp[0x1];
292 u8 inner_udp_sport[0x1];
293 u8 inner_udp_dport[0x1];
294 u8 inner_tcp_sport[0x1];
295 u8 inner_tcp_dport[0x1];
296 u8 inner_tcp_flags[0x1];
b4ff3a36 297 u8 reserved_at_37[0x9];
a550ddfc
YH		 298 u8 reserved_at_40[0x1a];
299 u8 bth_dst_qp[0x1];
e281682b 300
a550ddfc 301 u8 reserved_at_5b[0x25];
e281682b
SM		 302};
303
304struct mlx5_ifc_flow_table_prop_layout_bits {
305 u8 ft_support[0x1];
9dc0b289
AV		 306 u8 reserved_at_1[0x1];
307 u8 flow_counter[0x1];
26a81453 308 u8 flow_modify_en[0x1];
2cc43b49 309 u8 modify_root[0x1];
34a40e68
MG		 310 u8 identified_miss_table_mode[0x1];
311 u8 flow_table_modify[0x1];
7adbde20
HHZ		 312 u8 encap[0x1];
313 u8 decap[0x1];
314 u8 reserved_at_9[0x17];
e281682b 315
b4ff3a36 316 u8 reserved_at_20[0x2];
e281682b 317 u8 log_max_ft_size[0x6];
2a69cb9f
OG		 318 u8 log_max_modify_header_context[0x8];
319 u8 max_modify_header_actions[0x8];
e281682b
SM		 320 u8 max_ft_level[0x8];
321
b4ff3a36 322 u8 reserved_at_40[0x20];
e281682b 323
b4ff3a36 324 u8 reserved_at_60[0x18];
e281682b
SM		 325 u8 log_max_ft_num[0x8];
326
b4ff3a36 327 u8 reserved_at_80[0x18];
e281682b
SM		 328 u8 log_max_destination[0x8];
329
16f1c5bb
RS		 330 u8 log_max_flow_counter[0x8];
331 u8 reserved_at_a8[0x10];
e281682b
SM		 332 u8 log_max_flow[0x8];
333
b4ff3a36 334 u8 reserved_at_c0[0x40];
e281682b
SM		 335
336 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
337
338 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
339};
340
341struct mlx5_ifc_odp_per_transport_service_cap_bits {
342 u8 send[0x1];
343 u8 receive[0x1];
344 u8 write[0x1];
345 u8 read[0x1];
17d2f88f 346 u8 atomic[0x1];
e281682b 347 u8 srq_receive[0x1];
b4ff3a36 348 u8 reserved_at_6[0x1a];
e281682b
SM		 349};
350
b4d1f032 351struct mlx5_ifc_ipv4_layout_bits {
b4ff3a36 352 u8 reserved_at_0[0x60];
b4d1f032
MG		 353
354 u8 ipv4[0x20];
355};
356
357struct mlx5_ifc_ipv6_layout_bits {
358 u8 ipv6[16][0x8];
359};
360
361union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
362 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
363 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
b4ff3a36 364 u8 reserved_at_0[0x80];
b4d1f032
MG		 365};
366
e281682b
SM		 367struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
368 u8 smac_47_16[0x20];
369
370 u8 smac_15_0[0x10];
371 u8 ethertype[0x10];
372
373 u8 dmac_47_16[0x20];
374
375 u8 dmac_15_0[0x10];
376 u8 first_prio[0x3];
377 u8 first_cfi[0x1];
378 u8 first_vid[0xc];
379
380 u8 ip_protocol[0x8];
381 u8 ip_dscp[0x6];
382 u8 ip_ecn[0x2];
10543365
MHY		 383 u8 cvlan_tag[0x1];
384 u8 svlan_tag[0x1];
e281682b 385 u8 frag[0x1];
19cc7524 386 u8 ip_version[0x4];
e281682b
SM		 387 u8 tcp_flags[0x9];
388
389 u8 tcp_sport[0x10];
390 u8 tcp_dport[0x10];
391
a8ade55f
OG		 392 u8 reserved_at_c0[0x18];
393 u8 ttl_hoplimit[0x8];
e281682b
SM		 394
395 u8 udp_sport[0x10];
396 u8 udp_dport[0x10];
397
b4d1f032 398 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
e281682b 399
b4d1f032 400 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
e281682b
SM		 401};
402
403struct mlx5_ifc_fte_match_set_misc_bits {
7486216b
SM		 404 u8 reserved_at_0[0x8];
405 u8 source_sqn[0x18];
e281682b 406
b4ff3a36 407 u8 reserved_at_20[0x10];
e281682b
SM		 408 u8 source_port[0x10];
409
410 u8 outer_second_prio[0x3];
411 u8 outer_second_cfi[0x1];
412 u8 outer_second_vid[0xc];
413 u8 inner_second_prio[0x3];
414 u8 inner_second_cfi[0x1];
415 u8 inner_second_vid[0xc];
416
10543365
MHY		 417 u8 outer_second_cvlan_tag[0x1];
418 u8 inner_second_cvlan_tag[0x1];
419 u8 outer_second_svlan_tag[0x1];
420 u8 inner_second_svlan_tag[0x1];
421 u8 reserved_at_64[0xc];
e281682b
SM		 422 u8 gre_protocol[0x10];
423
424 u8 gre_key_h[0x18];
425 u8 gre_key_l[0x8];
426
427 u8 vxlan_vni[0x18];
b4ff3a36 428 u8 reserved_at_b8[0x8];
e281682b 429
b4ff3a36 430 u8 reserved_at_c0[0x20];
e281682b 431
b4ff3a36 432 u8 reserved_at_e0[0xc];
e281682b
SM		 433 u8 outer_ipv6_flow_label[0x14];
434
b4ff3a36 435 u8 reserved_at_100[0xc];
e281682b
SM		 436 u8 inner_ipv6_flow_label[0x14];
437
a550ddfc
YH		 438 u8 reserved_at_120[0x28];
439 u8 bth_dst_qp[0x18];
440 u8 reserved_at_160[0xa0];
e281682b
SM		 441};
442
443struct mlx5_ifc_cmd_pas_bits {
444 u8 pa_h[0x20];
445
446 u8 pa_l[0x14];
b4ff3a36 447 u8 reserved_at_34[0xc];
e281682b
SM		 448};
449
450struct mlx5_ifc_uint64_bits {
451 u8 hi[0x20];
452
453 u8 lo[0x20];
454};
455
456enum {
457 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
458 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
459 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
460 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
461 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
462 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
463 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
464 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
465 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
466 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
467};
468
469struct mlx5_ifc_ads_bits {
470 u8 fl[0x1];
471 u8 free_ar[0x1];
b4ff3a36 472 u8 reserved_at_2[0xe];
e281682b
SM		 473 u8 pkey_index[0x10];
474
b4ff3a36 475 u8 reserved_at_20[0x8];
e281682b
SM		 476 u8 grh[0x1];
477 u8 mlid[0x7];
478 u8 rlid[0x10];
479
480 u8 ack_timeout[0x5];
b4ff3a36 481 u8 reserved_at_45[0x3];
e281682b 482 u8 src_addr_index[0x8];
b4ff3a36 483 u8 reserved_at_50[0x4];
e281682b
SM		 484 u8 stat_rate[0x4];
485 u8 hop_limit[0x8];
486
b4ff3a36 487 u8 reserved_at_60[0x4];
e281682b
SM		 488 u8 tclass[0x8];
489 u8 flow_label[0x14];
490
491 u8 rgid_rip[16][0x8];
492
b4ff3a36 493 u8 reserved_at_100[0x4];
e281682b
SM		 494 u8 f_dscp[0x1];
495 u8 f_ecn[0x1];
b4ff3a36 496 u8 reserved_at_106[0x1];
e281682b
SM		 497 u8 f_eth_prio[0x1];
498 u8 ecn[0x2];
499 u8 dscp[0x6];
500 u8 udp_sport[0x10];
501
502 u8 dei_cfi[0x1];
503 u8 eth_prio[0x3];
504 u8 sl[0x4];
505 u8 port[0x8];
506 u8 rmac_47_32[0x10];
507
508 u8 rmac_31_0[0x20];
509};
510
511struct mlx5_ifc_flow_table_nic_cap_bits {
b3638e1a 512 u8 nic_rx_multi_path_tirs[0x1];
cea824d4
MG		 513 u8 nic_rx_multi_path_tirs_fts[0x1];
514 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
515 u8 reserved_at_3[0x1fd];
e281682b
SM		 516
517 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
518
b4ff3a36 519 u8 reserved_at_400[0x200];
e281682b
SM		 520
521 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
522
523 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
524
b4ff3a36 525 u8 reserved_at_a00[0x200];
e281682b
SM		 526
527 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
528
b4ff3a36 529 u8 reserved_at_e00[0x7200];
e281682b
SM		 530};
531
495716b1 532struct mlx5_ifc_flow_table_eswitch_cap_bits {
b4ff3a36 533 u8 reserved_at_0[0x200];
495716b1
SM		 534
535 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
536
537 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
538
539 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
540
b4ff3a36 541 u8 reserved_at_800[0x7800];
495716b1
SM		 542};
543
d6666753
SM		 544struct mlx5_ifc_e_switch_cap_bits {
545 u8 vport_svlan_strip[0x1];
546 u8 vport_cvlan_strip[0x1];
547 u8 vport_svlan_insert[0x1];
548 u8 vport_cvlan_insert_if_not_exist[0x1];
549 u8 vport_cvlan_insert_overwrite[0x1];
23898c76
NO		 550 u8 reserved_at_5[0x19];
551 u8 nic_vport_node_guid_modify[0x1];
552 u8 nic_vport_port_guid_modify[0x1];
d6666753 553
7adbde20
HHZ		 554 u8 vxlan_encap_decap[0x1];
555 u8 nvgre_encap_decap[0x1];
556 u8 reserved_at_22[0x9];
557 u8 log_max_encap_headers[0x5];
558 u8 reserved_2b[0x6];
559 u8 max_encap_header_size[0xa];
560
561 u8 reserved_40[0x7c0];
562
d6666753
SM		 563};
564
7486216b
SM		 565struct mlx5_ifc_qos_cap_bits {
566 u8 packet_pacing[0x1];
813f8540 567 u8 esw_scheduling[0x1];
c9497c98
MHY		 568 u8 esw_bw_share[0x1];
569 u8 esw_rate_limit[0x1];
570 u8 reserved_at_4[0x1c];
813f8540
MHY		 571
572 u8 reserved_at_20[0x20];
573
7486216b 574 u8 packet_pacing_max_rate[0x20];
813f8540 575
7486216b 576 u8 packet_pacing_min_rate[0x20];
813f8540
MHY		 577
578 u8 reserved_at_80[0x10];
7486216b 579 u8 packet_pacing_rate_table_size[0x10];
813f8540
MHY		 580
581 u8 esw_element_type[0x10];
582 u8 esw_tsar_type[0x10];
583
584 u8 reserved_at_c0[0x10];
585 u8 max_qos_para_vport[0x10];
586
587 u8 max_tsar_bw_share[0x20];
588
589 u8 reserved_at_100[0x700];
7486216b
SM		 590};
591
e281682b
SM		 592struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
593 u8 csum_cap[0x1];
594 u8 vlan_cap[0x1];
595 u8 lro_cap[0x1];
596 u8 lro_psh_flag[0x1];
597 u8 lro_time_stamp[0x1];
2b31f7ae
SM		 598 u8 reserved_at_5[0x2];
599 u8 wqe_vlan_insert[0x1];
66189961 600 u8 self_lb_en_modifiable[0x1];
b4ff3a36 601 u8 reserved_at_9[0x2];
e281682b 602 u8 max_lso_cap[0x5];
c226dc22 603 u8 multi_pkt_send_wqe[0x2];
cff92d7c 604 u8 wqe_inline_mode[0x2];
e281682b 605 u8 rss_ind_tbl_cap[0x4];
7d5e1423
SM		 606 u8 reg_umr_sq[0x1];
607 u8 scatter_fcs[0x1];
050da902 608 u8 enhanced_multi_pkt_send_wqe[0x1];
e281682b 609 u8 tunnel_lso_const_out_ip_id[0x1];
b4ff3a36 610 u8 reserved_at_1c[0x2];
27299841 611 u8 tunnel_stateless_gre[0x1];
e281682b
SM		 612 u8 tunnel_stateless_vxlan[0x1];
613
547eede0
IT		 614 u8 swp[0x1];
615 u8 swp_csum[0x1];
616 u8 swp_lso[0x1];
617 u8 reserved_at_23[0x1d];
e281682b 618
b4ff3a36 619 u8 reserved_at_40[0x10];
e281682b
SM		 620 u8 lro_min_mss_size[0x10];
621
b4ff3a36 622 u8 reserved_at_60[0x120];
e281682b
SM		 623
624 u8 lro_timer_supported_periods[4][0x20];
625
b4ff3a36 626 u8 reserved_at_200[0x600];
e281682b
SM		 627};
628
629struct mlx5_ifc_roce_cap_bits {
630 u8 roce_apm[0x1];
b4ff3a36 631 u8 reserved_at_1[0x1f];
e281682b 632
b4ff3a36 633 u8 reserved_at_20[0x60];
e281682b 634
b4ff3a36 635 u8 reserved_at_80[0xc];
e281682b 636 u8 l3_type[0x4];
b4ff3a36 637 u8 reserved_at_90[0x8];
e281682b
SM		 638 u8 roce_version[0x8];
639
b4ff3a36 640 u8 reserved_at_a0[0x10];
e281682b
SM		 641 u8 r_roce_dest_udp_port[0x10];
642
643 u8 r_roce_max_src_udp_port[0x10];
644 u8 r_roce_min_src_udp_port[0x10];
645
b4ff3a36 646 u8 reserved_at_e0[0x10];
e281682b
SM		 647 u8 roce_address_table_size[0x10];
648
b4ff3a36 649 u8 reserved_at_100[0x700];
e281682b
SM		 650};
651
652enum {
653 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
654 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
655 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
656 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
657 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
658 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
659 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
660 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
661 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
662};
663
664enum {
665 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
666 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
667 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
668 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
669 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
670 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
671 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
672 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
673 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
674};
675
676struct mlx5_ifc_atomic_caps_bits {
b4ff3a36 677 u8 reserved_at_0[0x40];
e281682b 678
bd10838a 679 u8 atomic_req_8B_endianness_mode[0x2];
b4ff3a36 680 u8 reserved_at_42[0x4];
bd10838a 681 u8 supported_atomic_req_8B_endianness_mode_1[0x1];
e281682b 682
b4ff3a36 683 u8 reserved_at_47[0x19];
e281682b 684
b4ff3a36 685 u8 reserved_at_60[0x20];
e281682b 686
b4ff3a36 687 u8 reserved_at_80[0x10];
f91e6d89 688 u8 atomic_operations[0x10];
e281682b 689
b4ff3a36 690 u8 reserved_at_a0[0x10];
f91e6d89
EBE		 691 u8 atomic_size_qp[0x10];
692
b4ff3a36 693 u8 reserved_at_c0[0x10];
e281682b
SM		 694 u8 atomic_size_dc[0x10];
695
b4ff3a36 696 u8 reserved_at_e0[0x720];
e281682b
SM		 697};
698
699struct mlx5_ifc_odp_cap_bits {
b4ff3a36 700 u8 reserved_at_0[0x40];
e281682b
SM		 701
702 u8 sig[0x1];
b4ff3a36 703 u8 reserved_at_41[0x1f];
e281682b 704
b4ff3a36 705 u8 reserved_at_60[0x20];
e281682b
SM		 706
707 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
708
709 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
710
711 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
712
b4ff3a36 713 u8 reserved_at_e0[0x720];
e281682b
SM		 714};
715
3f0393a5
SG		 716struct mlx5_ifc_calc_op {
717 u8 reserved_at_0[0x10];
718 u8 reserved_at_10[0x9];
719 u8 op_swap_endianness[0x1];
720 u8 op_min[0x1];
721 u8 op_xor[0x1];
722 u8 op_or[0x1];
723 u8 op_and[0x1];
724 u8 op_max[0x1];
725 u8 op_add[0x1];
726};
727
728struct mlx5_ifc_vector_calc_cap_bits {
729 u8 calc_matrix[0x1];
730 u8 reserved_at_1[0x1f];
731 u8 reserved_at_20[0x8];
732 u8 max_vec_count[0x8];
733 u8 reserved_at_30[0xd];
734 u8 max_chunk_size[0x3];
735 struct mlx5_ifc_calc_op calc0;
736 struct mlx5_ifc_calc_op calc1;
737 struct mlx5_ifc_calc_op calc2;
738 struct mlx5_ifc_calc_op calc3;
739
740 u8 reserved_at_e0[0x720];
741};
742
e281682b
SM		 743enum {
744 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
745 MLX5_WQ_TYPE_CYCLIC = 0x1,
7d5e1423 746 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
e281682b
SM		 747};
748
749enum {
750 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
751 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
752};
753
754enum {
755 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
756 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
757 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
758 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
759 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
760};
761
762enum {
763 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
764 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
765 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
766 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
767 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
768 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
769};
770
771enum {
772 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
773 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
774};
775
776enum {
777 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
778 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
779 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
780};
781
782enum {
783 MLX5_CAP_PORT_TYPE_IB = 0x0,
784 MLX5_CAP_PORT_TYPE_ETH = 0x1,
d29b796a
EC		 785};
786
1410a90a
MG		 787enum {
788 MLX5_CAP_UMR_FENCE_STRONG = 0x0,
789 MLX5_CAP_UMR_FENCE_SMALL = 0x1,
790 MLX5_CAP_UMR_FENCE_NONE = 0x2,
791};
792
b775516b 793struct mlx5_ifc_cmd_hca_cap_bits {
b4ff3a36 794 u8 reserved_at_0[0x80];
b775516b
EC		 795
796 u8 log_max_srq_sz[0x8];
797 u8 log_max_qp_sz[0x8];
b4ff3a36 798 u8 reserved_at_90[0xb];
b775516b
EC		 799 u8 log_max_qp[0x5];
800
b4ff3a36 801 u8 reserved_at_a0[0xb];
e281682b 802 u8 log_max_srq[0x5];
b4ff3a36 803 u8 reserved_at_b0[0x10];
b775516b 804
b4ff3a36 805 u8 reserved_at_c0[0x8];
b775516b 806 u8 log_max_cq_sz[0x8];
b4ff3a36 807 u8 reserved_at_d0[0xb];
b775516b
EC		 808 u8 log_max_cq[0x5];
809
810 u8 log_max_eq_sz[0x8];
b4ff3a36 811 u8 reserved_at_e8[0x2];
b775516b 812 u8 log_max_mkey[0x6];
b4ff3a36 813 u8 reserved_at_f0[0xc];
b775516b
EC		 814 u8 log_max_eq[0x4];
815
816 u8 max_indirection[0x8];
bcda1aca 817 u8 fixed_buffer_size[0x1];
b775516b 818 u8 log_max_mrw_sz[0x7];
8812c24d
MD		 819 u8 force_teardown[0x1];
820 u8 reserved_at_111[0x1];
b775516b 821 u8 log_max_bsf_list_size[0x6];
bcda1aca
AK		 822 u8 umr_extended_translation_offset[0x1];
823 u8 null_mkey[0x1];
b775516b
EC		 824 u8 log_max_klm_list_size[0x6];
825
b4ff3a36 826 u8 reserved_at_120[0xa];
b775516b 827 u8 log_max_ra_req_dc[0x6];
b4ff3a36 828 u8 reserved_at_130[0xa];
b775516b
EC		 829 u8 log_max_ra_res_dc[0x6];
830
b4ff3a36 831 u8 reserved_at_140[0xa];
b775516b 832 u8 log_max_ra_req_qp[0x6];
b4ff3a36 833 u8 reserved_at_150[0xa];
b775516b
EC		 834 u8 log_max_ra_res_qp[0x6];
835
f32f5bd2 836 u8 end_pad[0x1];
b775516b
EC		 837 u8 cc_query_allowed[0x1];
838 u8 cc_modify_allowed[0x1];
f32f5bd2
DJ		 839 u8 start_pad[0x1];
840 u8 cache_line_128byte[0x1];
c02762eb
HN		 841 u8 reserved_at_165[0xa];
842 u8 qcam_reg[0x1];
e281682b 843 u8 gid_table_size[0x10];
b775516b 844
e281682b
SM		 845 u8 out_of_seq_cnt[0x1];
846 u8 vport_counters[0x1];
7486216b 847 u8 retransmission_q_counters[0x1];
83b502a1
AV		 848 u8 reserved_at_183[0x1];
849 u8 modify_rq_counter_set_id[0x1];
c1e0bfc1 850 u8 rq_delay_drop[0x1];
b775516b
EC		 851 u8 max_qp_cnt[0xa];
852 u8 pkey_table_size[0x10];
853
e281682b
SM		 854 u8 vport_group_manager[0x1];
855 u8 vhca_group_manager[0x1];
856 u8 ib_virt[0x1];
857 u8 eth_virt[0x1];
b4ff3a36 858 u8 reserved_at_1a4[0x1];
e281682b
SM		 859 u8 ets[0x1];
860 u8 nic_flow_table[0x1];
54f0a411 861 u8 eswitch_flow_table[0x1];
e1c9c62b 862 u8 early_vf_enable[0x1];
cfdcbcea
GP		 863 u8 mcam_reg[0x1];
864 u8 pcam_reg[0x1];
b775516b 865 u8 local_ca_ack_delay[0x5];
4ce3bf2f 866 u8 port_module_event[0x1];
58dcb60a 867 u8 enhanced_error_q_counters[0x1];
7d5e1423 868 u8 ports_check[0x1];
7b13558f 869 u8 reserved_at_1b3[0x1];
7d5e1423
SM		 870 u8 disable_link_up[0x1];
871 u8 beacon_led[0x1];
e281682b 872 u8 port_type[0x2];
b775516b
EC		 873 u8 num_ports[0x8];
874
f9a1ef72
EE		 875 u8 reserved_at_1c0[0x1];
876 u8 pps[0x1];
877 u8 pps_modify[0x1];
b775516b 878 u8 log_max_msg[0x5];
e1c9c62b 879 u8 reserved_at_1c8[0x4];
4f3961ee 880 u8 max_tc[0x4];
7486216b
SM		 881 u8 reserved_at_1d0[0x1];
882 u8 dcbx[0x1];
246ac981
MG		 883 u8 general_notification_event[0x1];
884 u8 reserved_at_1d3[0x2];
e29341fb 885 u8 fpga[0x1];
928cfe87
TT		 886 u8 rol_s[0x1];
887 u8 rol_g[0x1];
e1c9c62b 888 u8 reserved_at_1d8[0x1];
928cfe87
TT		 889 u8 wol_s[0x1];
890 u8 wol_g[0x1];
891 u8 wol_a[0x1];
892 u8 wol_b[0x1];
893 u8 wol_m[0x1];
894 u8 wol_u[0x1];
895 u8 wol_p[0x1];
b775516b
EC		 896
897 u8 stat_rate_support[0x10];
e1c9c62b 898 u8 reserved_at_1f0[0xc];
e281682b 899 u8 cqe_version[0x4];
b775516b 900
e281682b 901 u8 compact_address_vector[0x1];
7d5e1423 902 u8 striding_rq[0x1];
500a3d0d
ES		 903 u8 reserved_at_202[0x1];
904 u8 ipoib_enhanced_offloads[0x1];
1015c2e8 905 u8 ipoib_basic_offloads[0x1];
1410a90a
MG		 906 u8 reserved_at_205[0x5];
907 u8 umr_fence[0x2];
908 u8 reserved_at_20c[0x3];
e281682b 909 u8 drain_sigerr[0x1];
b775516b
EC		 910 u8 cmdif_checksum[0x2];
911 u8 sigerr_cqe[0x1];
e1c9c62b 912 u8 reserved_at_213[0x1];
b775516b
EC		 913 u8 wq_signature[0x1];
914 u8 sctr_data_cqe[0x1];
e1c9c62b 915 u8 reserved_at_216[0x1];
b775516b
EC		 916 u8 sho[0x1];
917 u8 tph[0x1];
918 u8 rf[0x1];
e281682b 919 u8 dct[0x1];
7486216b 920 u8 qos[0x1];
e281682b 921 u8 eth_net_offloads[0x1];
b775516b
EC		 922 u8 roce[0x1];
923 u8 atomic[0x1];
e1c9c62b 924 u8 reserved_at_21f[0x1];
b775516b
EC		 925
926 u8 cq_oi[0x1];
927 u8 cq_resize[0x1];
928 u8 cq_moderation[0x1];
e1c9c62b 929 u8 reserved_at_223[0x3];
e281682b 930 u8 cq_eq_remap[0x1];
b775516b
EC		 931 u8 pg[0x1];
932 u8 block_lb_mc[0x1];
e1c9c62b 933 u8 reserved_at_229[0x1];
e281682b 934 u8 scqe_break_moderation[0x1];
7d5e1423 935 u8 cq_period_start_from_cqe[0x1];
b775516b 936 u8 cd[0x1];
e1c9c62b 937 u8 reserved_at_22d[0x1];
b775516b 938 u8 apm[0x1];
3f0393a5 939 u8 vector_calc[0x1];
7d5e1423 940 u8 umr_ptr_rlky[0x1];
d2370e0a 941 u8 imaicl[0x1];
e1c9c62b 942 u8 reserved_at_232[0x4];
b775516b
EC		 943 u8 qkv[0x1];
944 u8 pkv[0x1];
b11a4f9c
HE		 945 u8 set_deth_sqpn[0x1];
946 u8 reserved_at_239[0x3];
b775516b
EC		 947 u8 xrc[0x1];
948 u8 ud[0x1];
949 u8 uc[0x1];
950 u8 rc[0x1];
951
a6d51b68
EC		 952 u8 uar_4k[0x1];
953 u8 reserved_at_241[0x9];
b775516b 954 u8 uar_sz[0x6];
e1c9c62b 955 u8 reserved_at_250[0x8];
b775516b
EC		 956 u8 log_pg_sz[0x8];
957
958 u8 bf[0x1];
0dbc6fe0 959 u8 driver_version[0x1];
e281682b 960 u8 pad_tx_eth_packet[0x1];
e1c9c62b 961 u8 reserved_at_263[0x8];
b775516b 962 u8 log_bf_reg_size[0x5];
84df61eb
AH		 963
964 u8 reserved_at_270[0xb];
965 u8 lag_master[0x1];
966 u8 num_lag_ports[0x4];
b775516b 967
e1c9c62b 968 u8 reserved_at_280[0x10];
b775516b
EC		 969 u8 max_wqe_sz_sq[0x10];
970
e1c9c62b 971 u8 reserved_at_2a0[0x10];
b775516b
EC		 972 u8 max_wqe_sz_rq[0x10];
973
a8ffcc74 974 u8 max_flow_counter_31_16[0x10];
b775516b
EC		 975 u8 max_wqe_sz_sq_dc[0x10];
976
e1c9c62b 977 u8 reserved_at_2e0[0x7];
b775516b
EC		 978 u8 max_qp_mcg[0x19];
979
e1c9c62b 980 u8 reserved_at_300[0x18];
b775516b
EC		 981 u8 log_max_mcg[0x8];
982
e1c9c62b 983 u8 reserved_at_320[0x3];
e281682b 984 u8 log_max_transport_domain[0x5];
e1c9c62b 985 u8 reserved_at_328[0x3];
b775516b 986 u8 log_max_pd[0x5];
e1c9c62b 987 u8 reserved_at_330[0xb];
b775516b
EC		 988 u8 log_max_xrcd[0x5];
989
a351a1b0
AV		 990 u8 reserved_at_340[0x8];
991 u8 log_max_flow_counter_bulk[0x8];
a8ffcc74 992 u8 max_flow_counter_15_0[0x10];
a351a1b0 993
b775516b 994
e1c9c62b 995 u8 reserved_at_360[0x3];
b775516b 996 u8 log_max_rq[0x5];
e1c9c62b 997 u8 reserved_at_368[0x3];
b775516b 998 u8 log_max_sq[0x5];
e1c9c62b 999 u8 reserved_at_370[0x3];
b775516b 1000 u8 log_max_tir[0x5];
e1c9c62b 1001 u8 reserved_at_378[0x3];
b775516b
EC		 1002 u8 log_max_tis[0x5];
1003
e281682b 1004 u8 basic_cyclic_rcv_wqe[0x1];
e1c9c62b 1005 u8 reserved_at_381[0x2];
e281682b 1006 u8 log_max_rmp[0x5];
e1c9c62b 1007 u8 reserved_at_388[0x3];
e281682b 1008 u8 log_max_rqt[0x5];
e1c9c62b 1009 u8 reserved_at_390[0x3];
e281682b 1010 u8 log_max_rqt_size[0x5];
e1c9c62b 1011 u8 reserved_at_398[0x3];
b775516b
EC		 1012 u8 log_max_tis_per_sq[0x5];
1013
e1c9c62b 1014 u8 reserved_at_3a0[0x3];
e281682b 1015 u8 log_max_stride_sz_rq[0x5];
e1c9c62b 1016 u8 reserved_at_3a8[0x3];
e281682b 1017 u8 log_min_stride_sz_rq[0x5];
e1c9c62b 1018 u8 reserved_at_3b0[0x3];
e281682b 1019 u8 log_max_stride_sz_sq[0x5];
e1c9c62b 1020 u8 reserved_at_3b8[0x3];
e281682b
SM		 1021 u8 log_min_stride_sz_sq[0x5];
1022
e1c9c62b 1023 u8 reserved_at_3c0[0x1b];
e281682b
SM		 1024 u8 log_max_wq_sz[0x5];
1025
54f0a411 1026 u8 nic_vport_change_event[0x1];
bded747b
HN		 1027 u8 disable_local_lb[0x1];
1028 u8 reserved_at_3e2[0x9];
54f0a411 1029 u8 log_max_vlan_list[0x5];
e1c9c62b 1030 u8 reserved_at_3f0[0x3];
54f0a411 1031 u8 log_max_current_mc_list[0x5];
e1c9c62b 1032 u8 reserved_at_3f8[0x3];
54f0a411
SM		 1033 u8 log_max_current_uc_list[0x5];
1034
e1c9c62b 1035 u8 reserved_at_400[0x80];
54f0a411 1036
e1c9c62b 1037 u8 reserved_at_480[0x3];
e281682b 1038 u8 log_max_l2_table[0x5];
e1c9c62b 1039 u8 reserved_at_488[0x8];
b775516b
EC		 1040 u8 log_uar_page_sz[0x10];
1041
e1c9c62b 1042 u8 reserved_at_4a0[0x20];
048ccca8 1043 u8 device_frequency_mhz[0x20];
b0844444 1044 u8 device_frequency_khz[0x20];
e1c9c62b 1045
a6d51b68
EC		 1046 u8 reserved_at_500[0x20];
1047 u8 num_of_uars_per_page[0x20];
1048 u8 reserved_at_540[0x40];
e1c9c62b
TT		 1049
1050 u8 reserved_at_580[0x3f];
7d5e1423 1051 u8 cqe_compression[0x1];
b775516b 1052
7d5e1423
SM		 1053 u8 cqe_compression_timeout[0x10];
1054 u8 cqe_compression_max_num[0x10];
b775516b 1055
7486216b
SM		 1056 u8 reserved_at_5e0[0x10];
1057 u8 tag_matching[0x1];
1058 u8 rndv_offload_rc[0x1];
1059 u8 rndv_offload_dc[0x1];
1060 u8 log_tag_matching_list_sz[0x5];
7b13558f 1061 u8 reserved_at_5f8[0x3];
7486216b
SM		 1062 u8 log_max_xrq[0x5];
1063
7b13558f 1064 u8 reserved_at_600[0x200];
b775516b
EC		 1065};
1066
81848731
SM		 1067enum mlx5_flow_destination_type {
1068 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1069 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1070 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
bd5251db
AV		 1071
1072 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
e281682b 1073};
b775516b 1074
e281682b
SM		 1075struct mlx5_ifc_dest_format_struct_bits {
1076 u8 destination_type[0x8];
1077 u8 destination_id[0x18];
b775516b 1078
b4ff3a36 1079 u8 reserved_at_20[0x20];
e281682b
SM		 1080};
1081
9dc0b289 1082struct mlx5_ifc_flow_counter_list_bits {
a8ffcc74 1083 u8 flow_counter_id[0x20];
9dc0b289
AV		 1084
1085 u8 reserved_at_20[0x20];
1086};
1087
1088union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1089 struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1090 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1091 u8 reserved_at_0[0x40];
1092};
1093
e281682b
SM		 1094struct mlx5_ifc_fte_match_param_bits {
1095 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1096
1097 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1098
1099 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
b775516b 1100
b4ff3a36 1101 u8 reserved_at_600[0xa00];
b775516b
EC		 1102};
1103
e281682b
SM		 1104enum {
1105 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1106 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1107 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1108 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1109 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1110};
b775516b 1111
e281682b
SM		 1112struct mlx5_ifc_rx_hash_field_select_bits {
1113 u8 l3_prot_type[0x1];
1114 u8 l4_prot_type[0x1];
1115 u8 selected_fields[0x1e];
1116};
b775516b 1117
e281682b
SM		 1118enum {
1119 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
1120 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
b775516b
EC		 1121};
1122
e281682b
SM		 1123enum {
1124 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
1125 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
1126};
1127
1128struct mlx5_ifc_wq_bits {
1129 u8 wq_type[0x4];
1130 u8 wq_signature[0x1];
1131 u8 end_padding_mode[0x2];
1132 u8 cd_slave[0x1];
b4ff3a36 1133 u8 reserved_at_8[0x18];
b775516b 1134
e281682b
SM		 1135 u8 hds_skip_first_sge[0x1];
1136 u8 log2_hds_buf_size[0x3];
b4ff3a36 1137 u8 reserved_at_24[0x7];
e281682b
SM		 1138 u8 page_offset[0x5];
1139 u8 lwm[0x10];
b775516b 1140
b4ff3a36 1141 u8 reserved_at_40[0x8];
e281682b
SM		 1142 u8 pd[0x18];
1143
b4ff3a36 1144 u8 reserved_at_60[0x8];
e281682b
SM		 1145 u8 uar_page[0x18];
1146
1147 u8 dbr_addr[0x40];
1148
1149 u8 hw_counter[0x20];
1150
1151 u8 sw_counter[0x20];
1152
b4ff3a36 1153 u8 reserved_at_100[0xc];
e281682b 1154 u8 log_wq_stride[0x4];
b4ff3a36 1155 u8 reserved_at_110[0x3];
e281682b 1156 u8 log_wq_pg_sz[0x5];
b4ff3a36 1157 u8 reserved_at_118[0x3];
e281682b
SM		 1158 u8 log_wq_sz[0x5];
1159
7d5e1423
SM		 1160 u8 reserved_at_120[0x15];
1161 u8 log_wqe_num_of_strides[0x3];
1162 u8 two_byte_shift_en[0x1];
1163 u8 reserved_at_139[0x4];
1164 u8 log_wqe_stride_size[0x3];
1165
1166 u8 reserved_at_140[0x4c0];
b775516b 1167
e281682b 1168 struct mlx5_ifc_cmd_pas_bits pas[0];
b775516b
EC		 1169};
1170
e281682b 1171struct mlx5_ifc_rq_num_bits {
b4ff3a36 1172 u8 reserved_at_0[0x8];
e281682b
SM		 1173 u8 rq_num[0x18];
1174};
b775516b 1175
e281682b 1176struct mlx5_ifc_mac_address_layout_bits {
b4ff3a36 1177 u8 reserved_at_0[0x10];
e281682b 1178 u8 mac_addr_47_32[0x10];
b775516b 1179
e281682b
SM		 1180 u8 mac_addr_31_0[0x20];
1181};
1182
c0046cf7 1183struct mlx5_ifc_vlan_layout_bits {
b4ff3a36 1184 u8 reserved_at_0[0x14];
c0046cf7
SM		 1185 u8 vlan[0x0c];
1186
b4ff3a36 1187 u8 reserved_at_20[0x20];
c0046cf7
SM		 1188};
1189
e281682b 1190struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
b4ff3a36 1191 u8 reserved_at_0[0xa0];
e281682b
SM		 1192
1193 u8 min_time_between_cnps[0x20];
1194
b4ff3a36 1195 u8 reserved_at_c0[0x12];
e281682b 1196 u8 cnp_dscp[0x6];
4a2da0b8
PP		 1197 u8 reserved_at_d8[0x4];
1198 u8 cnp_prio_mode[0x1];
e281682b
SM		 1199 u8 cnp_802p_prio[0x3];
1200
b4ff3a36 1201 u8 reserved_at_e0[0x720];
e281682b
SM		 1202};
1203
1204struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
b4ff3a36 1205 u8 reserved_at_0[0x60];
e281682b 1206
b4ff3a36 1207 u8 reserved_at_60[0x4];
e281682b 1208 u8 clamp_tgt_rate[0x1];
b4ff3a36 1209 u8 reserved_at_65[0x3];
e281682b 1210 u8 clamp_tgt_rate_after_time_inc[0x1];
b4ff3a36 1211 u8 reserved_at_69[0x17];
e281682b 1212
b4ff3a36 1213 u8 reserved_at_80[0x20];
e281682b
SM		 1214
1215 u8 rpg_time_reset[0x20];
1216
1217 u8 rpg_byte_reset[0x20];
1218
1219 u8 rpg_threshold[0x20];
1220
1221 u8 rpg_max_rate[0x20];
1222
1223 u8 rpg_ai_rate[0x20];
1224
1225 u8 rpg_hai_rate[0x20];
1226
1227 u8 rpg_gd[0x20];
1228
1229 u8 rpg_min_dec_fac[0x20];
1230
1231 u8 rpg_min_rate[0x20];
1232
b4ff3a36 1233 u8 reserved_at_1c0[0xe0];
e281682b
SM		 1234
1235 u8 rate_to_set_on_first_cnp[0x20];
1236
1237 u8 dce_tcp_g[0x20];
1238
1239 u8 dce_tcp_rtt[0x20];
1240
1241 u8 rate_reduce_monitor_period[0x20];
1242
b4ff3a36 1243 u8 reserved_at_320[0x20];
e281682b
SM		 1244
1245 u8 initial_alpha_value[0x20];
1246
b4ff3a36 1247 u8 reserved_at_360[0x4a0];
e281682b
SM		 1248};
1249
1250struct mlx5_ifc_cong_control_802_1qau_rp_bits {
b4ff3a36 1251 u8 reserved_at_0[0x80];
e281682b
SM		 1252
1253 u8 rppp_max_rps[0x20];
1254
1255 u8 rpg_time_reset[0x20];
1256
1257 u8 rpg_byte_reset[0x20];
1258
1259 u8 rpg_threshold[0x20];
1260
1261 u8 rpg_max_rate[0x20];
1262
1263 u8 rpg_ai_rate[0x20];
1264
1265 u8 rpg_hai_rate[0x20];
1266
1267 u8 rpg_gd[0x20];
1268
1269 u8 rpg_min_dec_fac[0x20];
1270
1271 u8 rpg_min_rate[0x20];
1272
b4ff3a36 1273 u8 reserved_at_1c0[0x640];
e281682b
SM		 1274};
1275
1276enum {
1277 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1278 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1279 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1280};
1281
1282struct mlx5_ifc_resize_field_select_bits {
1283 u8 resize_field_select[0x20];
1284};
1285
1286enum {
1287 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1288 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1289 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1290 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1291};
1292
1293struct mlx5_ifc_modify_field_select_bits {
1294 u8 modify_field_select[0x20];
1295};
1296
1297struct mlx5_ifc_field_select_r_roce_np_bits {
1298 u8 field_select_r_roce_np[0x20];
1299};
1300
1301struct mlx5_ifc_field_select_r_roce_rp_bits {
1302 u8 field_select_r_roce_rp[0x20];
1303};
1304
1305enum {
1306 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1307 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1308 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1309 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1310 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1311 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1312 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1313 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1314 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1315 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1316};
1317
1318struct mlx5_ifc_field_select_802_1qau_rp_bits {
1319 u8 field_select_8021qaurp[0x20];
1320};
1321
1322struct mlx5_ifc_phys_layer_cntrs_bits {
1323 u8 time_since_last_clear_high[0x20];
1324
1325 u8 time_since_last_clear_low[0x20];
1326
1327 u8 symbol_errors_high[0x20];
1328
1329 u8 symbol_errors_low[0x20];
1330
1331 u8 sync_headers_errors_high[0x20];
1332
1333 u8 sync_headers_errors_low[0x20];
1334
1335 u8 edpl_bip_errors_lane0_high[0x20];
1336
1337 u8 edpl_bip_errors_lane0_low[0x20];
1338
1339 u8 edpl_bip_errors_lane1_high[0x20];
1340
1341 u8 edpl_bip_errors_lane1_low[0x20];
1342
1343 u8 edpl_bip_errors_lane2_high[0x20];
1344
1345 u8 edpl_bip_errors_lane2_low[0x20];
1346
1347 u8 edpl_bip_errors_lane3_high[0x20];
1348
1349 u8 edpl_bip_errors_lane3_low[0x20];
1350
1351 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1352
1353 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1354
1355 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1356
1357 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1358
1359 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1360
1361 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1362
1363 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1364
1365 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1366
1367 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1368
1369 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1370
1371 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1372
1373 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1374
1375 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1376
1377 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1378
1379 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1380
1381 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1382
1383 u8 rs_fec_corrected_blocks_high[0x20];
1384
1385 u8 rs_fec_corrected_blocks_low[0x20];
1386
1387 u8 rs_fec_uncorrectable_blocks_high[0x20];
1388
1389 u8 rs_fec_uncorrectable_blocks_low[0x20];
1390
1391 u8 rs_fec_no_errors_blocks_high[0x20];
1392
1393 u8 rs_fec_no_errors_blocks_low[0x20];
1394
1395 u8 rs_fec_single_error_blocks_high[0x20];
1396
1397 u8 rs_fec_single_error_blocks_low[0x20];
1398
1399 u8 rs_fec_corrected_symbols_total_high[0x20];
1400
1401 u8 rs_fec_corrected_symbols_total_low[0x20];
1402
1403 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1404
1405 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1406
1407 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1408
1409 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1410
1411 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1412
1413 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1414
1415 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1416
1417 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1418
1419 u8 link_down_events[0x20];
1420
1421 u8 successful_recovery_events[0x20];
1422
b4ff3a36 1423 u8 reserved_at_640[0x180];
e281682b
SM		 1424};
1425
d8dc0508
GP		 1426struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1427 u8 time_since_last_clear_high[0x20];
1428
1429 u8 time_since_last_clear_low[0x20];
1430
1431 u8 phy_received_bits_high[0x20];
1432
1433 u8 phy_received_bits_low[0x20];
1434
1435 u8 phy_symbol_errors_high[0x20];
1436
1437 u8 phy_symbol_errors_low[0x20];
1438
1439 u8 phy_corrected_bits_high[0x20];
1440
1441 u8 phy_corrected_bits_low[0x20];
1442
1443 u8 phy_corrected_bits_lane0_high[0x20];
1444
1445 u8 phy_corrected_bits_lane0_low[0x20];
1446
1447 u8 phy_corrected_bits_lane1_high[0x20];
1448
1449 u8 phy_corrected_bits_lane1_low[0x20];
1450
1451 u8 phy_corrected_bits_lane2_high[0x20];
1452
1453 u8 phy_corrected_bits_lane2_low[0x20];
1454
1455 u8 phy_corrected_bits_lane3_high[0x20];
1456
1457 u8 phy_corrected_bits_lane3_low[0x20];
1458
1459 u8 reserved_at_200[0x5c0];
1460};
1461
1c64bf6f
MY		 1462struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1463 u8 symbol_error_counter[0x10];
1464
1465 u8 link_error_recovery_counter[0x8];
1466
1467 u8 link_downed_counter[0x8];
1468
1469 u8 port_rcv_errors[0x10];
1470
1471 u8 port_rcv_remote_physical_errors[0x10];
1472
1473 u8 port_rcv_switch_relay_errors[0x10];
1474
1475 u8 port_xmit_discards[0x10];
1476
1477 u8 port_xmit_constraint_errors[0x8];
1478
1479 u8 port_rcv_constraint_errors[0x8];
1480
1481 u8 reserved_at_70[0x8];
1482
1483 u8 link_overrun_errors[0x8];
1484
1485 u8 reserved_at_80[0x10];
1486
1487 u8 vl_15_dropped[0x10];
1488
133bea04
TW		 1489 u8 reserved_at_a0[0x80];
1490
1491 u8 port_xmit_wait[0x20];
1c64bf6f
MY		 1492};
1493
e281682b
SM		 1494struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1495 u8 transmit_queue_high[0x20];
1496
1497 u8 transmit_queue_low[0x20];
1498
b4ff3a36 1499 u8 reserved_at_40[0x780];
e281682b
SM		 1500};
1501
1502struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1503 u8 rx_octets_high[0x20];
1504
1505 u8 rx_octets_low[0x20];
1506
b4ff3a36 1507 u8 reserved_at_40[0xc0];
e281682b
SM		 1508
1509 u8 rx_frames_high[0x20];
1510
1511 u8 rx_frames_low[0x20];
1512
1513 u8 tx_octets_high[0x20];
1514
1515 u8 tx_octets_low[0x20];
1516
b4ff3a36 1517 u8 reserved_at_180[0xc0];
e281682b
SM		 1518
1519 u8 tx_frames_high[0x20];
1520
1521 u8 tx_frames_low[0x20];
1522
1523 u8 rx_pause_high[0x20];
1524
1525 u8 rx_pause_low[0x20];
1526
1527 u8 rx_pause_duration_high[0x20];
1528
1529 u8 rx_pause_duration_low[0x20];
1530
1531 u8 tx_pause_high[0x20];
1532
1533 u8 tx_pause_low[0x20];
1534
1535 u8 tx_pause_duration_high[0x20];
1536
1537 u8 tx_pause_duration_low[0x20];
1538
1539 u8 rx_pause_transition_high[0x20];
1540
1541 u8 rx_pause_transition_low[0x20];
1542
b4ff3a36 1543 u8 reserved_at_3c0[0x400];
e281682b
SM		 1544};
1545
1546struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1547 u8 port_transmit_wait_high[0x20];
1548
1549 u8 port_transmit_wait_low[0x20];
1550
2dba0797
GP		 1551 u8 reserved_at_40[0x100];
1552
1553 u8 rx_buffer_almost_full_high[0x20];
1554
1555 u8 rx_buffer_almost_full_low[0x20];
1556
1557 u8 rx_buffer_full_high[0x20];
1558
1559 u8 rx_buffer_full_low[0x20];
1560
1561 u8 reserved_at_1c0[0x600];
e281682b
SM		 1562};
1563
1564struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1565 u8 dot3stats_alignment_errors_high[0x20];
1566
1567 u8 dot3stats_alignment_errors_low[0x20];
1568
1569 u8 dot3stats_fcs_errors_high[0x20];
1570
1571 u8 dot3stats_fcs_errors_low[0x20];
1572
1573 u8 dot3stats_single_collision_frames_high[0x20];
1574
1575 u8 dot3stats_single_collision_frames_low[0x20];
1576
1577 u8 dot3stats_multiple_collision_frames_high[0x20];
1578
1579 u8 dot3stats_multiple_collision_frames_low[0x20];
1580
1581 u8 dot3stats_sqe_test_errors_high[0x20];
1582
1583 u8 dot3stats_sqe_test_errors_low[0x20];
1584
1585 u8 dot3stats_deferred_transmissions_high[0x20];
1586
1587 u8 dot3stats_deferred_transmissions_low[0x20];
1588
1589 u8 dot3stats_late_collisions_high[0x20];
1590
1591 u8 dot3stats_late_collisions_low[0x20];
1592
1593 u8 dot3stats_excessive_collisions_high[0x20];
1594
1595 u8 dot3stats_excessive_collisions_low[0x20];
1596
1597 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1598
1599 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1600
1601 u8 dot3stats_carrier_sense_errors_high[0x20];
1602
1603 u8 dot3stats_carrier_sense_errors_low[0x20];
1604
1605 u8 dot3stats_frame_too_longs_high[0x20];
1606
1607 u8 dot3stats_frame_too_longs_low[0x20];
1608
1609 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1610
1611 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1612
1613 u8 dot3stats_symbol_errors_high[0x20];
1614
1615 u8 dot3stats_symbol_errors_low[0x20];
1616
1617 u8 dot3control_in_unknown_opcodes_high[0x20];
1618
1619 u8 dot3control_in_unknown_opcodes_low[0x20];
1620
1621 u8 dot3in_pause_frames_high[0x20];
1622
1623 u8 dot3in_pause_frames_low[0x20];
1624
1625 u8 dot3out_pause_frames_high[0x20];
1626
1627 u8 dot3out_pause_frames_low[0x20];
1628
b4ff3a36 1629 u8 reserved_at_400[0x3c0];
e281682b
SM		 1630};
1631
1632struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1633 u8 ether_stats_drop_events_high[0x20];
1634
1635 u8 ether_stats_drop_events_low[0x20];
1636
1637 u8 ether_stats_octets_high[0x20];
1638
1639 u8 ether_stats_octets_low[0x20];
1640
1641 u8 ether_stats_pkts_high[0x20];
1642
1643 u8 ether_stats_pkts_low[0x20];
1644
1645 u8 ether_stats_broadcast_pkts_high[0x20];
1646
1647 u8 ether_stats_broadcast_pkts_low[0x20];
1648
1649 u8 ether_stats_multicast_pkts_high[0x20];
1650
1651 u8 ether_stats_multicast_pkts_low[0x20];
1652
1653 u8 ether_stats_crc_align_errors_high[0x20];
1654
1655 u8 ether_stats_crc_align_errors_low[0x20];
1656
1657 u8 ether_stats_undersize_pkts_high[0x20];
1658
1659 u8 ether_stats_undersize_pkts_low[0x20];
1660
1661 u8 ether_stats_oversize_pkts_high[0x20];
1662
1663 u8 ether_stats_oversize_pkts_low[0x20];
1664
1665 u8 ether_stats_fragments_high[0x20];
1666
1667 u8 ether_stats_fragments_low[0x20];
1668
1669 u8 ether_stats_jabbers_high[0x20];
1670
1671 u8 ether_stats_jabbers_low[0x20];
1672
1673 u8 ether_stats_collisions_high[0x20];
1674
1675 u8 ether_stats_collisions_low[0x20];
1676
1677 u8 ether_stats_pkts64octets_high[0x20];
1678
1679 u8 ether_stats_pkts64octets_low[0x20];
1680
1681 u8 ether_stats_pkts65to127octets_high[0x20];
1682
1683 u8 ether_stats_pkts65to127octets_low[0x20];
1684
1685 u8 ether_stats_pkts128to255octets_high[0x20];
1686
1687 u8 ether_stats_pkts128to255octets_low[0x20];
1688
1689 u8 ether_stats_pkts256to511octets_high[0x20];
1690
1691 u8 ether_stats_pkts256to511octets_low[0x20];
1692
1693 u8 ether_stats_pkts512to1023octets_high[0x20];
1694
1695 u8 ether_stats_pkts512to1023octets_low[0x20];
1696
1697 u8 ether_stats_pkts1024to1518octets_high[0x20];
1698
1699 u8 ether_stats_pkts1024to1518octets_low[0x20];
1700
1701 u8 ether_stats_pkts1519to2047octets_high[0x20];
1702
1703 u8 ether_stats_pkts1519to2047octets_low[0x20];
1704
1705 u8 ether_stats_pkts2048to4095octets_high[0x20];
1706
1707 u8 ether_stats_pkts2048to4095octets_low[0x20];
1708
1709 u8 ether_stats_pkts4096to8191octets_high[0x20];
1710
1711 u8 ether_stats_pkts4096to8191octets_low[0x20];
1712
1713 u8 ether_stats_pkts8192to10239octets_high[0x20];
1714
1715 u8 ether_stats_pkts8192to10239octets_low[0x20];
1716
b4ff3a36 1717 u8 reserved_at_540[0x280];
e281682b
SM		 1718};
1719
1720struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1721 u8 if_in_octets_high[0x20];
1722
1723 u8 if_in_octets_low[0x20];
1724
1725 u8 if_in_ucast_pkts_high[0x20];
1726
1727 u8 if_in_ucast_pkts_low[0x20];
1728
1729 u8 if_in_discards_high[0x20];
1730
1731 u8 if_in_discards_low[0x20];
1732
1733 u8 if_in_errors_high[0x20];
1734
1735 u8 if_in_errors_low[0x20];
1736
1737 u8 if_in_unknown_protos_high[0x20];
1738
1739 u8 if_in_unknown_protos_low[0x20];
1740
1741 u8 if_out_octets_high[0x20];
1742
1743 u8 if_out_octets_low[0x20];
1744
1745 u8 if_out_ucast_pkts_high[0x20];
1746
1747 u8 if_out_ucast_pkts_low[0x20];
1748
1749 u8 if_out_discards_high[0x20];
1750
1751 u8 if_out_discards_low[0x20];
1752
1753 u8 if_out_errors_high[0x20];
1754
1755 u8 if_out_errors_low[0x20];
1756
1757 u8 if_in_multicast_pkts_high[0x20];
1758
1759 u8 if_in_multicast_pkts_low[0x20];
1760
1761 u8 if_in_broadcast_pkts_high[0x20];
1762
1763 u8 if_in_broadcast_pkts_low[0x20];
1764
1765 u8 if_out_multicast_pkts_high[0x20];
1766
1767 u8 if_out_multicast_pkts_low[0x20];
1768
1769 u8 if_out_broadcast_pkts_high[0x20];
1770
1771 u8 if_out_broadcast_pkts_low[0x20];
1772
b4ff3a36 1773 u8 reserved_at_340[0x480];
e281682b
SM		 1774};
1775
1776struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1777 u8 a_frames_transmitted_ok_high[0x20];
1778
1779 u8 a_frames_transmitted_ok_low[0x20];
1780
1781 u8 a_frames_received_ok_high[0x20];
1782
1783 u8 a_frames_received_ok_low[0x20];
1784
1785 u8 a_frame_check_sequence_errors_high[0x20];
1786
1787 u8 a_frame_check_sequence_errors_low[0x20];
1788
1789 u8 a_alignment_errors_high[0x20];
1790
1791 u8 a_alignment_errors_low[0x20];
1792
1793 u8 a_octets_transmitted_ok_high[0x20];
1794
1795 u8 a_octets_transmitted_ok_low[0x20];
1796
1797 u8 a_octets_received_ok_high[0x20];
1798
1799 u8 a_octets_received_ok_low[0x20];
1800
1801 u8 a_multicast_frames_xmitted_ok_high[0x20];
1802
1803 u8 a_multicast_frames_xmitted_ok_low[0x20];
1804
1805 u8 a_broadcast_frames_xmitted_ok_high[0x20];
1806
1807 u8 a_broadcast_frames_xmitted_ok_low[0x20];
1808
1809 u8 a_multicast_frames_received_ok_high[0x20];
1810
1811 u8 a_multicast_frames_received_ok_low[0x20];
1812
1813 u8 a_broadcast_frames_received_ok_high[0x20];
1814
1815 u8 a_broadcast_frames_received_ok_low[0x20];
1816
1817 u8 a_in_range_length_errors_high[0x20];
1818
1819 u8 a_in_range_length_errors_low[0x20];
1820
1821 u8 a_out_of_range_length_field_high[0x20];
1822
1823 u8 a_out_of_range_length_field_low[0x20];
1824
1825 u8 a_frame_too_long_errors_high[0x20];
1826
1827 u8 a_frame_too_long_errors_low[0x20];
1828
1829 u8 a_symbol_error_during_carrier_high[0x20];
1830
1831 u8 a_symbol_error_during_carrier_low[0x20];
1832
1833 u8 a_mac_control_frames_transmitted_high[0x20];
1834
1835 u8 a_mac_control_frames_transmitted_low[0x20];
1836
1837 u8 a_mac_control_frames_received_high[0x20];
1838
1839 u8 a_mac_control_frames_received_low[0x20];
1840
1841 u8 a_unsupported_opcodes_received_high[0x20];
1842
1843 u8 a_unsupported_opcodes_received_low[0x20];
1844
1845 u8 a_pause_mac_ctrl_frames_received_high[0x20];
1846
1847 u8 a_pause_mac_ctrl_frames_received_low[0x20];
1848
1849 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
1850
1851 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
1852
b4ff3a36 1853 u8 reserved_at_4c0[0x300];
e281682b
SM		 1854};
1855
8ed1a630
GP		 1856struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
1857 u8 life_time_counter_high[0x20];
1858
1859 u8 life_time_counter_low[0x20];
1860
1861 u8 rx_errors[0x20];
1862
1863 u8 tx_errors[0x20];
1864
1865 u8 l0_to_recovery_eieos[0x20];
1866
1867 u8 l0_to_recovery_ts[0x20];
1868
1869 u8 l0_to_recovery_framing[0x20];
1870
1871 u8 l0_to_recovery_retrain[0x20];
1872
1873 u8 crc_error_dllp[0x20];
1874
1875 u8 crc_error_tlp[0x20];
1876
efae7f78
EBE		 1877 u8 tx_overflow_buffer_pkt_high[0x20];
1878
1879 u8 tx_overflow_buffer_pkt_low[0x20];
5405fa26
GP		 1880
1881 u8 outbound_stalled_reads[0x20];
1882
1883 u8 outbound_stalled_writes[0x20];
1884
1885 u8 outbound_stalled_reads_events[0x20];
1886
1887 u8 outbound_stalled_writes_events[0x20];
1888
1889 u8 reserved_at_200[0x5c0];
8ed1a630
GP		 1890};
1891
e281682b
SM		 1892struct mlx5_ifc_cmd_inter_comp_event_bits {
1893 u8 command_completion_vector[0x20];
1894
b4ff3a36 1895 u8 reserved_at_20[0xc0];
e281682b
SM		 1896};
1897
1898struct mlx5_ifc_stall_vl_event_bits {
b4ff3a36 1899 u8 reserved_at_0[0x18];
e281682b 1900 u8 port_num[0x1];
b4ff3a36 1901 u8 reserved_at_19[0x3];
e281682b
SM		 1902 u8 vl[0x4];
1903
b4ff3a36 1904 u8 reserved_at_20[0xa0];
e281682b
SM		 1905};
1906
1907struct mlx5_ifc_db_bf_congestion_event_bits {
1908 u8 event_subtype[0x8];
b4ff3a36 1909 u8 reserved_at_8[0x8];
e281682b 1910 u8 congestion_level[0x8];
b4ff3a36 1911 u8 reserved_at_18[0x8];
e281682b 1912
b4ff3a36 1913 u8 reserved_at_20[0xa0];
e281682b
SM		 1914};
1915
1916struct mlx5_ifc_gpio_event_bits {
b4ff3a36 1917 u8 reserved_at_0[0x60];
e281682b
SM		 1918
1919 u8 gpio_event_hi[0x20];
1920
1921 u8 gpio_event_lo[0x20];
1922
b4ff3a36 1923 u8 reserved_at_a0[0x40];
e281682b
SM		 1924};
1925
1926struct mlx5_ifc_port_state_change_event_bits {
b4ff3a36 1927 u8 reserved_at_0[0x40];
e281682b
SM		 1928
1929 u8 port_num[0x4];
b4ff3a36 1930 u8 reserved_at_44[0x1c];
e281682b 1931
b4ff3a36 1932 u8 reserved_at_60[0x80];
e281682b
SM		 1933};
1934
1935struct mlx5_ifc_dropped_packet_logged_bits {
b4ff3a36 1936 u8 reserved_at_0[0xe0];
e281682b
SM		 1937};
1938
1939enum {
1940 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
1941 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
1942};
1943
1944struct mlx5_ifc_cq_error_bits {
b4ff3a36 1945 u8 reserved_at_0[0x8];
e281682b
SM		 1946 u8 cqn[0x18];
1947
b4ff3a36 1948 u8 reserved_at_20[0x20];
e281682b 1949
b4ff3a36 1950 u8 reserved_at_40[0x18];
e281682b
SM		 1951 u8 syndrome[0x8];
1952
b4ff3a36 1953 u8 reserved_at_60[0x80];
e281682b
SM		 1954};
1955
1956struct mlx5_ifc_rdma_page_fault_event_bits {
1957 u8 bytes_committed[0x20];
1958
1959 u8 r_key[0x20];
1960
b4ff3a36 1961 u8 reserved_at_40[0x10];
e281682b
SM		 1962 u8 packet_len[0x10];
1963
1964 u8 rdma_op_len[0x20];
1965
1966 u8 rdma_va[0x40];
1967
b4ff3a36 1968 u8 reserved_at_c0[0x5];
e281682b
SM		 1969 u8 rdma[0x1];
1970 u8 write[0x1];
1971 u8 requestor[0x1];
1972 u8 qp_number[0x18];
1973};
1974
1975struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1976 u8 bytes_committed[0x20];
1977
b4ff3a36 1978 u8 reserved_at_20[0x10];
e281682b
SM		 1979 u8 wqe_index[0x10];
1980
b4ff3a36 1981 u8 reserved_at_40[0x10];
e281682b
SM		 1982 u8 len[0x10];
1983
b4ff3a36 1984 u8 reserved_at_60[0x60];
e281682b 1985
b4ff3a36 1986 u8 reserved_at_c0[0x5];
e281682b
SM		 1987 u8 rdma[0x1];
1988 u8 write_read[0x1];
1989 u8 requestor[0x1];
1990 u8 qpn[0x18];
1991};
1992
1993struct mlx5_ifc_qp_events_bits {
b4ff3a36 1994 u8 reserved_at_0[0xa0];
e281682b
SM		 1995
1996 u8 type[0x8];
b4ff3a36 1997 u8 reserved_at_a8[0x18];
e281682b 1998
b4ff3a36 1999 u8 reserved_at_c0[0x8];
e281682b
SM		 2000 u8 qpn_rqn_sqn[0x18];
2001};
2002
2003struct mlx5_ifc_dct_events_bits {
b4ff3a36 2004 u8 reserved_at_0[0xc0];
e281682b 2005
b4ff3a36 2006 u8 reserved_at_c0[0x8];
e281682b
SM		 2007 u8 dct_number[0x18];
2008};
2009
2010struct mlx5_ifc_comp_event_bits {
b4ff3a36 2011 u8 reserved_at_0[0xc0];
e281682b 2012
b4ff3a36 2013 u8 reserved_at_c0[0x8];
e281682b
SM		 2014 u8 cq_number[0x18];
2015};
2016
2017enum {
2018 MLX5_QPC_STATE_RST = 0x0,
2019 MLX5_QPC_STATE_INIT = 0x1,
2020 MLX5_QPC_STATE_RTR = 0x2,
2021 MLX5_QPC_STATE_RTS = 0x3,
2022 MLX5_QPC_STATE_SQER = 0x4,
2023 MLX5_QPC_STATE_ERR = 0x6,
2024 MLX5_QPC_STATE_SQD = 0x7,
2025 MLX5_QPC_STATE_SUSPENDED = 0x9,
2026};
2027
2028enum {
2029 MLX5_QPC_ST_RC = 0x0,
2030 MLX5_QPC_ST_UC = 0x1,
2031 MLX5_QPC_ST_UD = 0x2,
2032 MLX5_QPC_ST_XRC = 0x3,
2033 MLX5_QPC_ST_DCI = 0x5,
2034 MLX5_QPC_ST_QP0 = 0x7,
2035 MLX5_QPC_ST_QP1 = 0x8,
2036 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
2037 MLX5_QPC_ST_REG_UMR = 0xc,
2038};
2039
2040enum {
2041 MLX5_QPC_PM_STATE_ARMED = 0x0,
2042 MLX5_QPC_PM_STATE_REARM = 0x1,
2043 MLX5_QPC_PM_STATE_RESERVED = 0x2,
2044 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
2045};
2046
6e44636a
AK		 2047enum {
2048 MLX5_QPC_OFFLOAD_TYPE_RNDV = 0x1,
2049};
2050
e281682b
SM		 2051enum {
2052 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
2053 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
2054};
2055
2056enum {
2057 MLX5_QPC_MTU_256_BYTES = 0x1,
2058 MLX5_QPC_MTU_512_BYTES = 0x2,
2059 MLX5_QPC_MTU_1K_BYTES = 0x3,
2060 MLX5_QPC_MTU_2K_BYTES = 0x4,
2061 MLX5_QPC_MTU_4K_BYTES = 0x5,
2062 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
2063};
2064
2065enum {
2066 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
2067 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
2068 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
2069 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
2070 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
2071 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
2072 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
2073 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
2074};
2075
2076enum {
2077 MLX5_QPC_CS_REQ_DISABLE = 0x0,
2078 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
2079 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
2080};
2081
2082enum {
2083 MLX5_QPC_CS_RES_DISABLE = 0x0,
2084 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
2085 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
2086};
2087
2088struct mlx5_ifc_qpc_bits {
2089 u8 state[0x4];
84df61eb 2090 u8 lag_tx_port_affinity[0x4];
e281682b 2091 u8 st[0x8];
b4ff3a36 2092 u8 reserved_at_10[0x3];
e281682b 2093 u8 pm_state[0x2];
6e44636a
AK		 2094 u8 reserved_at_15[0x3];
2095 u8 offload_type[0x4];
e281682b 2096 u8 end_padding_mode[0x2];
b4ff3a36 2097 u8 reserved_at_1e[0x2];
e281682b
SM		 2098
2099 u8 wq_signature[0x1];
2100 u8 block_lb_mc[0x1];
2101 u8 atomic_like_write_en[0x1];
2102 u8 latency_sensitive[0x1];
b4ff3a36 2103 u8 reserved_at_24[0x1];
e281682b 2104 u8 drain_sigerr[0x1];
b4ff3a36 2105 u8 reserved_at_26[0x2];
e281682b
SM		 2106 u8 pd[0x18];
2107
2108 u8 mtu[0x3];
2109 u8 log_msg_max[0x5];
b4ff3a36 2110 u8 reserved_at_48[0x1];
e281682b
SM		 2111 u8 log_rq_size[0x4];
2112 u8 log_rq_stride[0x3];
2113 u8 no_sq[0x1];
2114 u8 log_sq_size[0x4];
b4ff3a36 2115 u8 reserved_at_55[0x6];
e281682b 2116 u8 rlky[0x1];
1015c2e8 2117 u8 ulp_stateless_offload_mode[0x4];
e281682b
SM		 2118
2119 u8 counter_set_id[0x8];
2120 u8 uar_page[0x18];
2121
b4ff3a36 2122 u8 reserved_at_80[0x8];
e281682b
SM		 2123 u8 user_index[0x18];
2124
b4ff3a36 2125 u8 reserved_at_a0[0x3];
e281682b
SM		 2126 u8 log_page_size[0x5];
2127 u8 remote_qpn[0x18];
2128
2129 struct mlx5_ifc_ads_bits primary_address_path;
2130
2131 struct mlx5_ifc_ads_bits secondary_address_path;
2132
2133 u8 log_ack_req_freq[0x4];
b4ff3a36 2134 u8 reserved_at_384[0x4];
e281682b 2135 u8 log_sra_max[0x3];
b4ff3a36 2136 u8 reserved_at_38b[0x2];
e281682b
SM		 2137 u8 retry_count[0x3];
2138 u8 rnr_retry[0x3];
b4ff3a36 2139 u8 reserved_at_393[0x1];
e281682b
SM		 2140 u8 fre[0x1];
2141 u8 cur_rnr_retry[0x3];
2142 u8 cur_retry_count[0x3];
b4ff3a36 2143 u8 reserved_at_39b[0x5];
e281682b 2144
b4ff3a36 2145 u8 reserved_at_3a0[0x20];
e281682b 2146
b4ff3a36 2147 u8 reserved_at_3c0[0x8];
e281682b
SM		 2148 u8 next_send_psn[0x18];
2149
b4ff3a36 2150 u8 reserved_at_3e0[0x8];
e281682b
SM		 2151 u8 cqn_snd[0x18];
2152
09a7d9ec
SM		 2153 u8 reserved_at_400[0x8];
2154 u8 deth_sqpn[0x18];
2155
2156 u8 reserved_at_420[0x20];
e281682b 2157
b4ff3a36 2158 u8 reserved_at_440[0x8];
e281682b
SM		 2159 u8 last_acked_psn[0x18];
2160
b4ff3a36 2161 u8 reserved_at_460[0x8];
e281682b
SM		 2162 u8 ssn[0x18];
2163
b4ff3a36 2164 u8 reserved_at_480[0x8];
e281682b 2165 u8 log_rra_max[0x3];
b4ff3a36 2166 u8 reserved_at_48b[0x1];
e281682b
SM		 2167 u8 atomic_mode[0x4];
2168 u8 rre[0x1];
2169 u8 rwe[0x1];
2170 u8 rae[0x1];
b4ff3a36 2171 u8 reserved_at_493[0x1];
e281682b 2172 u8 page_offset[0x6];
b4ff3a36 2173 u8 reserved_at_49a[0x3];
e281682b
SM		 2174 u8 cd_slave_receive[0x1];
2175 u8 cd_slave_send[0x1];
2176 u8 cd_master[0x1];
2177
b4ff3a36 2178 u8 reserved_at_4a0[0x3];
e281682b
SM		 2179 u8 min_rnr_nak[0x5];
2180 u8 next_rcv_psn[0x18];
2181
b4ff3a36 2182 u8 reserved_at_4c0[0x8];
e281682b
SM		 2183 u8 xrcd[0x18];
2184
b4ff3a36 2185 u8 reserved_at_4e0[0x8];
e281682b
SM		 2186 u8 cqn_rcv[0x18];
2187
2188 u8 dbr_addr[0x40];
2189
2190 u8 q_key[0x20];
2191
b4ff3a36 2192 u8 reserved_at_560[0x5];
e281682b 2193 u8 rq_type[0x3];
7486216b 2194 u8 srqn_rmpn_xrqn[0x18];
e281682b 2195
b4ff3a36 2196 u8 reserved_at_580[0x8];
e281682b
SM		 2197 u8 rmsn[0x18];
2198
2199 u8 hw_sq_wqebb_counter[0x10];
2200 u8 sw_sq_wqebb_counter[0x10];
2201
2202 u8 hw_rq_counter[0x20];
2203
2204 u8 sw_rq_counter[0x20];
2205
b4ff3a36 2206 u8 reserved_at_600[0x20];
e281682b 2207
b4ff3a36 2208 u8 reserved_at_620[0xf];
e281682b
SM		 2209 u8 cgs[0x1];
2210 u8 cs_req[0x8];
2211 u8 cs_res[0x8];
2212
2213 u8 dc_access_key[0x40];
2214
b4ff3a36 2215 u8 reserved_at_680[0xc0];
e281682b
SM		 2216};
2217
2218struct mlx5_ifc_roce_addr_layout_bits {
2219 u8 source_l3_address[16][0x8];
2220
b4ff3a36 2221 u8 reserved_at_80[0x3];
e281682b
SM		 2222 u8 vlan_valid[0x1];
2223 u8 vlan_id[0xc];
2224 u8 source_mac_47_32[0x10];
2225
2226 u8 source_mac_31_0[0x20];
2227
b4ff3a36 2228 u8 reserved_at_c0[0x14];
e281682b
SM		 2229 u8 roce_l3_type[0x4];
2230 u8 roce_version[0x8];
2231
b4ff3a36 2232 u8 reserved_at_e0[0x20];
e281682b
SM		 2233};
2234
2235union mlx5_ifc_hca_cap_union_bits {
2236 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2237 struct mlx5_ifc_odp_cap_bits odp_cap;
2238 struct mlx5_ifc_atomic_caps_bits atomic_caps;
2239 struct mlx5_ifc_roce_cap_bits roce_cap;
2240 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2241 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
495716b1 2242 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
d6666753 2243 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
3f0393a5 2244 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
7486216b 2245 struct mlx5_ifc_qos_cap_bits qos_cap;
e29341fb 2246 struct mlx5_ifc_fpga_cap_bits fpga_cap;
b4ff3a36 2247 u8 reserved_at_0[0x8000];
e281682b
SM		 2248};
2249
2250enum {
2251 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
2252 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
2253 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
9dc0b289 2254 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
7adbde20
HHZ		 2255 MLX5_FLOW_CONTEXT_ACTION_ENCAP = 0x10,
2256 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
2a69cb9f 2257 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40,
e281682b
SM		 2258};
2259
2260struct mlx5_ifc_flow_context_bits {
b4ff3a36 2261 u8 reserved_at_0[0x20];
e281682b
SM		 2262
2263 u8 group_id[0x20];
2264
b4ff3a36 2265 u8 reserved_at_40[0x8];
e281682b
SM		 2266 u8 flow_tag[0x18];
2267
b4ff3a36 2268 u8 reserved_at_60[0x10];
e281682b
SM		 2269 u8 action[0x10];
2270
b4ff3a36 2271 u8 reserved_at_80[0x8];
e281682b
SM		 2272 u8 destination_list_size[0x18];
2273
9dc0b289
AV		 2274 u8 reserved_at_a0[0x8];
2275 u8 flow_counter_list_size[0x18];
2276
7adbde20
HHZ		 2277 u8 encap_id[0x20];
2278
2a69cb9f
OG		 2279 u8 modify_header_id[0x20];
2280
2281 u8 reserved_at_100[0x100];
e281682b
SM		 2282
2283 struct mlx5_ifc_fte_match_param_bits match_value;
2284
b4ff3a36 2285 u8 reserved_at_1200[0x600];
e281682b 2286
9dc0b289 2287 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
e281682b
SM		 2288};
2289
2290enum {
2291 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
2292 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
2293};
2294
2295struct mlx5_ifc_xrc_srqc_bits {
2296 u8 state[0x4];
2297 u8 log_xrc_srq_size[0x4];
b4ff3a36 2298 u8 reserved_at_8[0x18];
e281682b
SM		 2299
2300 u8 wq_signature[0x1];
2301 u8 cont_srq[0x1];
b4ff3a36 2302 u8 reserved_at_22[0x1];
e281682b
SM		 2303 u8 rlky[0x1];
2304 u8 basic_cyclic_rcv_wqe[0x1];
2305 u8 log_rq_stride[0x3];
2306 u8 xrcd[0x18];
2307
2308 u8 page_offset[0x6];
b4ff3a36 2309 u8 reserved_at_46[0x2];
e281682b
SM		 2310 u8 cqn[0x18];
2311
b4ff3a36 2312 u8 reserved_at_60[0x20];
e281682b
SM		 2313
2314 u8 user_index_equal_xrc_srqn[0x1];
b4ff3a36 2315 u8 reserved_at_81[0x1];
e281682b
SM		 2316 u8 log_page_size[0x6];
2317 u8 user_index[0x18];
2318
b4ff3a36 2319 u8 reserved_at_a0[0x20];
e281682b 2320
b4ff3a36 2321 u8 reserved_at_c0[0x8];
e281682b
SM		 2322 u8 pd[0x18];
2323
2324 u8 lwm[0x10];
2325 u8 wqe_cnt[0x10];
2326
b4ff3a36 2327 u8 reserved_at_100[0x40];
e281682b
SM		 2328
2329 u8 db_record_addr_h[0x20];
2330
2331 u8 db_record_addr_l[0x1e];
b4ff3a36 2332 u8 reserved_at_17e[0x2];
e281682b 2333
b4ff3a36 2334 u8 reserved_at_180[0x80];
e281682b
SM		 2335};
2336
2337struct mlx5_ifc_traffic_counter_bits {
2338 u8 packets[0x40];
2339
2340 u8 octets[0x40];
2341};
2342
2343struct mlx5_ifc_tisc_bits {
84df61eb
AH		 2344 u8 strict_lag_tx_port_affinity[0x1];
2345 u8 reserved_at_1[0x3];
2346 u8 lag_tx_port_affinity[0x04];
2347
2348 u8 reserved_at_8[0x4];
e281682b 2349 u8 prio[0x4];
b4ff3a36 2350 u8 reserved_at_10[0x10];
e281682b 2351
b4ff3a36 2352 u8 reserved_at_20[0x100];
e281682b 2353
b4ff3a36 2354 u8 reserved_at_120[0x8];
e281682b
SM		 2355 u8 transport_domain[0x18];
2356
500a3d0d
ES		 2357 u8 reserved_at_140[0x8];
2358 u8 underlay_qpn[0x18];
2359 u8 reserved_at_160[0x3a0];
e281682b
SM		 2360};
2361
2362enum {
2363 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2364 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2365};
2366
2367enum {
2368 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2369 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2370};
2371
2372enum {
2be6967c
SM		 2373 MLX5_RX_HASH_FN_NONE = 0x0,
2374 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
2375 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
e281682b
SM		 2376};
2377
2378enum {
2379 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1,
2380 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2,
2381};
2382
2383struct mlx5_ifc_tirc_bits {
b4ff3a36 2384 u8 reserved_at_0[0x20];
e281682b
SM		 2385
2386 u8 disp_type[0x4];
b4ff3a36 2387 u8 reserved_at_24[0x1c];
e281682b 2388
b4ff3a36 2389 u8 reserved_at_40[0x40];
e281682b 2390
b4ff3a36 2391 u8 reserved_at_80[0x4];
e281682b
SM		 2392 u8 lro_timeout_period_usecs[0x10];
2393 u8 lro_enable_mask[0x4];
2394 u8 lro_max_ip_payload_size[0x8];
2395
b4ff3a36 2396 u8 reserved_at_a0[0x40];
e281682b 2397
b4ff3a36 2398 u8 reserved_at_e0[0x8];
e281682b
SM		 2399 u8 inline_rqn[0x18];
2400
2401 u8 rx_hash_symmetric[0x1];
b4ff3a36 2402 u8 reserved_at_101[0x1];
e281682b 2403 u8 tunneled_offload_en[0x1];
b4ff3a36 2404 u8 reserved_at_103[0x5];
e281682b
SM		 2405 u8 indirect_table[0x18];
2406
2407 u8 rx_hash_fn[0x4];
b4ff3a36 2408 u8 reserved_at_124[0x2];
e281682b
SM		 2409 u8 self_lb_block[0x2];
2410 u8 transport_domain[0x18];
2411
2412 u8 rx_hash_toeplitz_key[10][0x20];
2413
2414 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2415
2416 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2417
b4ff3a36 2418 u8 reserved_at_2c0[0x4c0];
e281682b
SM		 2419};
2420
2421enum {
2422 MLX5_SRQC_STATE_GOOD = 0x0,
2423 MLX5_SRQC_STATE_ERROR = 0x1,
2424};
2425
2426struct mlx5_ifc_srqc_bits {
2427 u8 state[0x4];
2428 u8 log_srq_size[0x4];
b4ff3a36 2429 u8 reserved_at_8[0x18];
e281682b
SM		 2430
2431 u8 wq_signature[0x1];
2432 u8 cont_srq[0x1];
b4ff3a36 2433 u8 reserved_at_22[0x1];
e281682b 2434 u8 rlky[0x1];
b4ff3a36 2435 u8 reserved_at_24[0x1];
e281682b
SM		 2436 u8 log_rq_stride[0x3];
2437 u8 xrcd[0x18];
2438
2439 u8 page_offset[0x6];
b4ff3a36 2440 u8 reserved_at_46[0x2];
e281682b
SM		 2441 u8 cqn[0x18];
2442
b4ff3a36 2443 u8 reserved_at_60[0x20];
e281682b 2444
b4ff3a36 2445 u8 reserved_at_80[0x2];
e281682b 2446 u8 log_page_size[0x6];
b4ff3a36 2447 u8 reserved_at_88[0x18];
e281682b 2448
b4ff3a36 2449 u8 reserved_at_a0[0x20];
e281682b 2450
b4ff3a36 2451 u8 reserved_at_c0[0x8];
e281682b
SM		 2452 u8 pd[0x18];
2453
2454 u8 lwm[0x10];
2455 u8 wqe_cnt[0x10];
2456
b4ff3a36 2457 u8 reserved_at_100[0x40];
e281682b 2458
01949d01 2459 u8 dbr_addr[0x40];
e281682b 2460
b4ff3a36 2461 u8 reserved_at_180[0x80];
e281682b
SM		 2462};
2463
2464enum {
2465 MLX5_SQC_STATE_RST = 0x0,
2466 MLX5_SQC_STATE_RDY = 0x1,
2467 MLX5_SQC_STATE_ERR = 0x3,
2468};
2469
2470struct mlx5_ifc_sqc_bits {
2471 u8 rlky[0x1];
2472 u8 cd_master[0x1];
2473 u8 fre[0x1];
2474 u8 flush_in_error_en[0x1];
795b609c 2475 u8 allow_multi_pkt_send_wqe[0x1];
cff92d7c 2476 u8 min_wqe_inline_mode[0x3];
e281682b 2477 u8 state[0x4];
7d5e1423 2478 u8 reg_umr[0x1];
547eede0
IT		 2479 u8 allow_swp[0x1];
2480 u8 reserved_at_e[0x12];
e281682b 2481
b4ff3a36 2482 u8 reserved_at_20[0x8];
e281682b
SM		 2483 u8 user_index[0x18];
2484
b4ff3a36 2485 u8 reserved_at_40[0x8];
e281682b
SM		 2486 u8 cqn[0x18];
2487
7486216b 2488 u8 reserved_at_60[0x90];
e281682b 2489
7486216b 2490 u8 packet_pacing_rate_limit_index[0x10];
e281682b 2491 u8 tis_lst_sz[0x10];
b4ff3a36 2492 u8 reserved_at_110[0x10];
e281682b 2493
b4ff3a36 2494 u8 reserved_at_120[0x40];
e281682b 2495
b4ff3a36 2496 u8 reserved_at_160[0x8];
e281682b
SM		 2497 u8 tis_num_0[0x18];
2498
2499 struct mlx5_ifc_wq_bits wq;
2500};
2501
813f8540
MHY		 2502enum {
2503 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2504 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2505 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2506 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2507};
2508
2509struct mlx5_ifc_scheduling_context_bits {
2510 u8 element_type[0x8];
2511 u8 reserved_at_8[0x18];
2512
2513 u8 element_attributes[0x20];
2514
2515 u8 parent_element_id[0x20];
2516
2517 u8 reserved_at_60[0x40];
2518
2519 u8 bw_share[0x20];
2520
2521 u8 max_average_bw[0x20];
2522
2523 u8 reserved_at_e0[0x120];
2524};
2525
e281682b 2526struct mlx5_ifc_rqtc_bits {
b4ff3a36 2527 u8 reserved_at_0[0xa0];
e281682b 2528
b4ff3a36 2529 u8 reserved_at_a0[0x10];
e281682b
SM		 2530 u8 rqt_max_size[0x10];
2531
b4ff3a36 2532 u8 reserved_at_c0[0x10];
e281682b
SM		 2533 u8 rqt_actual_size[0x10];
2534
b4ff3a36 2535 u8 reserved_at_e0[0x6a0];
e281682b
SM		 2536
2537 struct mlx5_ifc_rq_num_bits rq_num[0];
2538};
2539
2540enum {
2541 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2542 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2543};
2544
2545enum {
2546 MLX5_RQC_STATE_RST = 0x0,
2547 MLX5_RQC_STATE_RDY = 0x1,
2548 MLX5_RQC_STATE_ERR = 0x3,
2549};
2550
2551struct mlx5_ifc_rqc_bits {
2552 u8 rlky[0x1];
03404e8a 2553 u8 delay_drop_en[0x1];
7d5e1423 2554 u8 scatter_fcs[0x1];
e281682b
SM		 2555 u8 vsd[0x1];
2556 u8 mem_rq_type[0x4];
2557 u8 state[0x4];
b4ff3a36 2558 u8 reserved_at_c[0x1];
e281682b 2559 u8 flush_in_error_en[0x1];
b4ff3a36 2560 u8 reserved_at_e[0x12];
e281682b 2561
b4ff3a36 2562 u8 reserved_at_20[0x8];
e281682b
SM		 2563 u8 user_index[0x18];
2564
b4ff3a36 2565 u8 reserved_at_40[0x8];
e281682b
SM		 2566 u8 cqn[0x18];
2567
2568 u8 counter_set_id[0x8];
b4ff3a36 2569 u8 reserved_at_68[0x18];
e281682b 2570
b4ff3a36 2571 u8 reserved_at_80[0x8];
e281682b
SM		 2572 u8 rmpn[0x18];
2573
b4ff3a36 2574 u8 reserved_at_a0[0xe0];
e281682b
SM		 2575
2576 struct mlx5_ifc_wq_bits wq;
2577};
2578
2579enum {
2580 MLX5_RMPC_STATE_RDY = 0x1,
2581 MLX5_RMPC_STATE_ERR = 0x3,
2582};
2583
2584struct mlx5_ifc_rmpc_bits {
b4ff3a36 2585 u8 reserved_at_0[0x8];
e281682b 2586 u8 state[0x4];
b4ff3a36 2587 u8 reserved_at_c[0x14];
e281682b
SM		 2588
2589 u8 basic_cyclic_rcv_wqe[0x1];
b4ff3a36 2590 u8 reserved_at_21[0x1f];
e281682b 2591
b4ff3a36 2592 u8 reserved_at_40[0x140];
e281682b
SM		 2593
2594 struct mlx5_ifc_wq_bits wq;
2595};
2596
e281682b 2597struct mlx5_ifc_nic_vport_context_bits {
cff92d7c
HHZ		 2598 u8 reserved_at_0[0x5];
2599 u8 min_wqe_inline_mode[0x3];
bded747b
HN		 2600 u8 reserved_at_8[0x15];
2601 u8 disable_mc_local_lb[0x1];
2602 u8 disable_uc_local_lb[0x1];
e281682b
SM		 2603 u8 roce_en[0x1];
2604
d82b7318 2605 u8 arm_change_event[0x1];
b4ff3a36 2606 u8 reserved_at_21[0x1a];
d82b7318
SM		 2607 u8 event_on_mtu[0x1];
2608 u8 event_on_promisc_change[0x1];
2609 u8 event_on_vlan_change[0x1];
2610 u8 event_on_mc_address_change[0x1];
2611 u8 event_on_uc_address_change[0x1];
e281682b 2612
b4ff3a36 2613 u8 reserved_at_40[0xf0];
d82b7318
SM		 2614
2615 u8 mtu[0x10];
2616
9efa7525
AS		 2617 u8 system_image_guid[0x40];
2618 u8 port_guid[0x40];
2619 u8 node_guid[0x40];
2620
b4ff3a36 2621 u8 reserved_at_200[0x140];
9efa7525 2622 u8 qkey_violation_counter[0x10];
b4ff3a36 2623 u8 reserved_at_350[0x430];
d82b7318
SM		 2624
2625 u8 promisc_uc[0x1];
2626 u8 promisc_mc[0x1];
2627 u8 promisc_all[0x1];
b4ff3a36 2628 u8 reserved_at_783[0x2];
e281682b 2629 u8 allowed_list_type[0x3];
b4ff3a36 2630 u8 reserved_at_788[0xc];
e281682b
SM		 2631 u8 allowed_list_size[0xc];
2632
2633 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2634
b4ff3a36 2635 u8 reserved_at_7e0[0x20];
e281682b
SM		 2636
2637 u8 current_uc_mac_address[0][0x40];
2638};
2639
2640enum {
2641 MLX5_MKC_ACCESS_MODE_PA = 0x0,
2642 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
2643 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
bcda1aca 2644 MLX5_MKC_ACCESS_MODE_KSM = 0x3,
e281682b
SM		 2645};
2646
2647struct mlx5_ifc_mkc_bits {
b4ff3a36 2648 u8 reserved_at_0[0x1];
e281682b 2649 u8 free[0x1];
b4ff3a36 2650 u8 reserved_at_2[0xd];
e281682b
SM		 2651 u8 small_fence_on_rdma_read_response[0x1];
2652 u8 umr_en[0x1];
2653 u8 a[0x1];
2654 u8 rw[0x1];
2655 u8 rr[0x1];
2656 u8 lw[0x1];
2657 u8 lr[0x1];
2658 u8 access_mode[0x2];
b4ff3a36 2659 u8 reserved_at_18[0x8];
e281682b
SM		 2660
2661 u8 qpn[0x18];
2662 u8 mkey_7_0[0x8];
2663
b4ff3a36 2664 u8 reserved_at_40[0x20];
e281682b
SM		 2665
2666 u8 length64[0x1];
2667 u8 bsf_en[0x1];
2668 u8 sync_umr[0x1];
b4ff3a36 2669 u8 reserved_at_63[0x2];
e281682b 2670 u8 expected_sigerr_count[0x1];
b4ff3a36 2671 u8 reserved_at_66[0x1];
e281682b
SM		 2672 u8 en_rinval[0x1];
2673 u8 pd[0x18];
2674
2675 u8 start_addr[0x40];
2676
2677 u8 len[0x40];
2678
2679 u8 bsf_octword_size[0x20];
2680
b4ff3a36 2681 u8 reserved_at_120[0x80];
e281682b
SM		 2682
2683 u8 translations_octword_size[0x20];
2684
b4ff3a36 2685 u8 reserved_at_1c0[0x1b];
e281682b
SM		 2686 u8 log_page_size[0x5];
2687
b4ff3a36 2688 u8 reserved_at_1e0[0x20];
e281682b
SM		 2689};
2690
2691struct mlx5_ifc_pkey_bits {
b4ff3a36 2692 u8 reserved_at_0[0x10];
e281682b
SM		 2693 u8 pkey[0x10];
2694};
2695
2696struct mlx5_ifc_array128_auto_bits {
2697 u8 array128_auto[16][0x8];
2698};
2699
2700struct mlx5_ifc_hca_vport_context_bits {
2701 u8 field_select[0x20];
2702
b4ff3a36 2703 u8 reserved_at_20[0xe0];
e281682b
SM		 2704
2705 u8 sm_virt_aware[0x1];
2706 u8 has_smi[0x1];
2707 u8 has_raw[0x1];
2708 u8 grh_required[0x1];
b4ff3a36 2709 u8 reserved_at_104[0xc];
707c4602
MD		 2710 u8 port_physical_state[0x4];
2711 u8 vport_state_policy[0x4];
2712 u8 port_state[0x4];
e281682b
SM		 2713 u8 vport_state[0x4];
2714
b4ff3a36 2715 u8 reserved_at_120[0x20];
707c4602
MD		 2716
2717 u8 system_image_guid[0x40];
e281682b
SM		 2718
2719 u8 port_guid[0x40];
2720
2721 u8 node_guid[0x40];
2722
2723 u8 cap_mask1[0x20];
2724
2725 u8 cap_mask1_field_select[0x20];
2726
2727 u8 cap_mask2[0x20];
2728
2729 u8 cap_mask2_field_select[0x20];
2730
b4ff3a36 2731 u8 reserved_at_280[0x80];
e281682b
SM		 2732
2733 u8 lid[0x10];
b4ff3a36 2734 u8 reserved_at_310[0x4];
e281682b
SM		 2735 u8 init_type_reply[0x4];
2736 u8 lmc[0x3];
2737 u8 subnet_timeout[0x5];
2738
2739 u8 sm_lid[0x10];
2740 u8 sm_sl[0x4];
b4ff3a36 2741 u8 reserved_at_334[0xc];
e281682b
SM		 2742
2743 u8 qkey_violation_counter[0x10];
2744 u8 pkey_violation_counter[0x10];
2745
b4ff3a36 2746 u8 reserved_at_360[0xca0];
e281682b
SM		 2747};
2748
d6666753 2749struct mlx5_ifc_esw_vport_context_bits {
b4ff3a36 2750 u8 reserved_at_0[0x3];
d6666753
SM		 2751 u8 vport_svlan_strip[0x1];
2752 u8 vport_cvlan_strip[0x1];
2753 u8 vport_svlan_insert[0x1];
2754 u8 vport_cvlan_insert[0x2];
b4ff3a36 2755 u8 reserved_at_8[0x18];
d6666753 2756
b4ff3a36 2757 u8 reserved_at_20[0x20];
d6666753
SM		 2758
2759 u8 svlan_cfi[0x1];
2760 u8 svlan_pcp[0x3];
2761 u8 svlan_id[0xc];
2762 u8 cvlan_cfi[0x1];
2763 u8 cvlan_pcp[0x3];
2764 u8 cvlan_id[0xc];
2765
b4ff3a36 2766 u8 reserved_at_60[0x7a0];
d6666753
SM		 2767};
2768
e281682b
SM		 2769enum {
2770 MLX5_EQC_STATUS_OK = 0x0,
2771 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
2772};
2773
2774enum {
2775 MLX5_EQC_ST_ARMED = 0x9,
2776 MLX5_EQC_ST_FIRED = 0xa,
2777};
2778
2779struct mlx5_ifc_eqc_bits {
2780 u8 status[0x4];
b4ff3a36 2781 u8 reserved_at_4[0x9];
e281682b
SM		 2782 u8 ec[0x1];
2783 u8 oi[0x1];
b4ff3a36 2784 u8 reserved_at_f[0x5];
e281682b 2785 u8 st[0x4];
b4ff3a36 2786 u8 reserved_at_18[0x8];
e281682b 2787
b4ff3a36 2788 u8 reserved_at_20[0x20];
e281682b 2789
b4ff3a36 2790 u8 reserved_at_40[0x14];
e281682b 2791 u8 page_offset[0x6];
b4ff3a36 2792 u8 reserved_at_5a[0x6];
e281682b 2793
b4ff3a36 2794 u8 reserved_at_60[0x3];
e281682b
SM		 2795 u8 log_eq_size[0x5];
2796 u8 uar_page[0x18];
2797
b4ff3a36 2798 u8 reserved_at_80[0x20];
e281682b 2799
b4ff3a36 2800 u8 reserved_at_a0[0x18];
e281682b
SM		 2801 u8 intr[0x8];
2802
b4ff3a36 2803 u8 reserved_at_c0[0x3];
e281682b 2804 u8 log_page_size[0x5];
b4ff3a36 2805 u8 reserved_at_c8[0x18];
e281682b 2806
b4ff3a36 2807 u8 reserved_at_e0[0x60];
e281682b 2808
b4ff3a36 2809 u8 reserved_at_140[0x8];
e281682b
SM		 2810 u8 consumer_counter[0x18];
2811
b4ff3a36 2812 u8 reserved_at_160[0x8];
e281682b
SM		 2813 u8 producer_counter[0x18];
2814
b4ff3a36 2815 u8 reserved_at_180[0x80];
e281682b
SM		 2816};
2817
2818enum {
2819 MLX5_DCTC_STATE_ACTIVE = 0x0,
2820 MLX5_DCTC_STATE_DRAINING = 0x1,
2821 MLX5_DCTC_STATE_DRAINED = 0x2,
2822};
2823
2824enum {
2825 MLX5_DCTC_CS_RES_DISABLE = 0x0,
2826 MLX5_DCTC_CS_RES_NA = 0x1,
2827 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
2828};
2829
2830enum {
2831 MLX5_DCTC_MTU_256_BYTES = 0x1,
2832 MLX5_DCTC_MTU_512_BYTES = 0x2,
2833 MLX5_DCTC_MTU_1K_BYTES = 0x3,
2834 MLX5_DCTC_MTU_2K_BYTES = 0x4,
2835 MLX5_DCTC_MTU_4K_BYTES = 0x5,
2836};
2837
2838struct mlx5_ifc_dctc_bits {
b4ff3a36 2839 u8 reserved_at_0[0x4];
e281682b 2840 u8 state[0x4];
b4ff3a36 2841 u8 reserved_at_8[0x18];
e281682b 2842
b4ff3a36 2843 u8 reserved_at_20[0x8];
e281682b
SM		 2844 u8 user_index[0x18];
2845
b4ff3a36 2846 u8 reserved_at_40[0x8];
e281682b
SM		 2847 u8 cqn[0x18];
2848
2849 u8 counter_set_id[0x8];
2850 u8 atomic_mode[0x4];
2851 u8 rre[0x1];
2852 u8 rwe[0x1];
2853 u8 rae[0x1];
2854 u8 atomic_like_write_en[0x1];
2855 u8 latency_sensitive[0x1];
2856 u8 rlky[0x1];
2857 u8 free_ar[0x1];
b4ff3a36 2858 u8 reserved_at_73[0xd];
e281682b 2859
b4ff3a36 2860 u8 reserved_at_80[0x8];
e281682b 2861 u8 cs_res[0x8];
b4ff3a36 2862 u8 reserved_at_90[0x3];
e281682b 2863 u8 min_rnr_nak[0x5];
b4ff3a36 2864 u8 reserved_at_98[0x8];
e281682b 2865
b4ff3a36 2866 u8 reserved_at_a0[0x8];
7486216b 2867 u8 srqn_xrqn[0x18];
e281682b 2868
b4ff3a36 2869 u8 reserved_at_c0[0x8];
e281682b
SM		 2870 u8 pd[0x18];
2871
2872 u8 tclass[0x8];
b4ff3a36 2873 u8 reserved_at_e8[0x4];
e281682b
SM		 2874 u8 flow_label[0x14];
2875
2876 u8 dc_access_key[0x40];
2877
b4ff3a36 2878 u8 reserved_at_140[0x5];
e281682b
SM		 2879 u8 mtu[0x3];
2880 u8 port[0x8];
2881 u8 pkey_index[0x10];
2882
b4ff3a36 2883 u8 reserved_at_160[0x8];
e281682b 2884 u8 my_addr_index[0x8];
b4ff3a36 2885 u8 reserved_at_170[0x8];
e281682b
SM		 2886 u8 hop_limit[0x8];
2887
2888 u8 dc_access_key_violation_count[0x20];
2889
b4ff3a36 2890 u8 reserved_at_1a0[0x14];
e281682b
SM		 2891 u8 dei_cfi[0x1];
2892 u8 eth_prio[0x3];
2893 u8 ecn[0x2];
2894 u8 dscp[0x6];
2895
b4ff3a36 2896 u8 reserved_at_1c0[0x40];
e281682b
SM		 2897};
2898
2899enum {
2900 MLX5_CQC_STATUS_OK = 0x0,
2901 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
2902 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
2903};
2904
2905enum {
2906 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
2907 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
2908};
2909
2910enum {
2911 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
2912 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
2913 MLX5_CQC_ST_FIRED = 0xa,
2914};
2915
7d5e1423
SM		 2916enum {
2917 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
2918 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
7486216b 2919 MLX5_CQ_PERIOD_NUM_MODES
7d5e1423
SM		 2920};
2921
e281682b
SM		 2922struct mlx5_ifc_cqc_bits {
2923 u8 status[0x4];
b4ff3a36 2924 u8 reserved_at_4[0x4];
e281682b
SM		 2925 u8 cqe_sz[0x3];
2926 u8 cc[0x1];
b4ff3a36 2927 u8 reserved_at_c[0x1];
e281682b
SM		 2928 u8 scqe_break_moderation_en[0x1];
2929 u8 oi[0x1];
7d5e1423
SM		 2930 u8 cq_period_mode[0x2];
2931 u8 cqe_comp_en[0x1];
e281682b
SM		 2932 u8 mini_cqe_res_format[0x2];
2933 u8 st[0x4];
b4ff3a36 2934 u8 reserved_at_18[0x8];
e281682b 2935
b4ff3a36 2936 u8 reserved_at_20[0x20];
e281682b 2937
b4ff3a36 2938 u8 reserved_at_40[0x14];
e281682b 2939 u8 page_offset[0x6];
b4ff3a36 2940 u8 reserved_at_5a[0x6];
e281682b 2941
b4ff3a36 2942 u8 reserved_at_60[0x3];
e281682b
SM		 2943 u8 log_cq_size[0x5];
2944 u8 uar_page[0x18];
2945
b4ff3a36 2946 u8 reserved_at_80[0x4];
e281682b
SM		 2947 u8 cq_period[0xc];
2948 u8 cq_max_count[0x10];
2949
b4ff3a36 2950 u8 reserved_at_a0[0x18];
e281682b
SM		 2951 u8 c_eqn[0x8];
2952
b4ff3a36 2953 u8 reserved_at_c0[0x3];
e281682b 2954 u8 log_page_size[0x5];
b4ff3a36 2955 u8 reserved_at_c8[0x18];
e281682b 2956
b4ff3a36 2957 u8 reserved_at_e0[0x20];
e281682b 2958
b4ff3a36 2959 u8 reserved_at_100[0x8];
e281682b
SM		 2960 u8 last_notified_index[0x18];
2961
b4ff3a36 2962 u8 reserved_at_120[0x8];
e281682b
SM		 2963 u8 last_solicit_index[0x18];
2964
b4ff3a36 2965 u8 reserved_at_140[0x8];
e281682b
SM		 2966 u8 consumer_counter[0x18];
2967
b4ff3a36 2968 u8 reserved_at_160[0x8];
e281682b
SM		 2969 u8 producer_counter[0x18];
2970
b4ff3a36 2971 u8 reserved_at_180[0x40];
e281682b
SM		 2972
2973 u8 dbr_addr[0x40];
2974};
2975
2976union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2977 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2978 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2979 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
b4ff3a36 2980 u8 reserved_at_0[0x800];
e281682b
SM		 2981};
2982
2983struct mlx5_ifc_query_adapter_param_block_bits {
b4ff3a36 2984 u8 reserved_at_0[0xc0];
e281682b 2985
b4ff3a36 2986 u8 reserved_at_c0[0x8];
211e6c80
MD		 2987 u8 ieee_vendor_id[0x18];
2988
b4ff3a36 2989 u8 reserved_at_e0[0x10];
e281682b
SM		 2990 u8 vsd_vendor_id[0x10];
2991
2992 u8 vsd[208][0x8];
2993
2994 u8 vsd_contd_psid[16][0x8];
2995};
2996
7486216b
SM		 2997enum {
2998 MLX5_XRQC_STATE_GOOD = 0x0,
2999 MLX5_XRQC_STATE_ERROR = 0x1,
3000};
3001
3002enum {
3003 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
3004 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
3005};
3006
3007enum {
3008 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
3009};
3010
3011struct mlx5_ifc_tag_matching_topology_context_bits {
3012 u8 log_matching_list_sz[0x4];
3013 u8 reserved_at_4[0xc];
3014 u8 append_next_index[0x10];
3015
3016 u8 sw_phase_cnt[0x10];
3017 u8 hw_phase_cnt[0x10];
3018
3019 u8 reserved_at_40[0x40];
3020};
3021
3022struct mlx5_ifc_xrqc_bits {
3023 u8 state[0x4];
3024 u8 rlkey[0x1];
3025 u8 reserved_at_5[0xf];
3026 u8 topology[0x4];
3027 u8 reserved_at_18[0x4];
3028 u8 offload[0x4];
3029
3030 u8 reserved_at_20[0x8];
3031 u8 user_index[0x18];
3032
3033 u8 reserved_at_40[0x8];
3034 u8 cqn[0x18];
3035
3036 u8 reserved_at_60[0xa0];
3037
3038 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
3039
6e44636a 3040 u8 reserved_at_180[0x280];
7486216b
SM		 3041
3042 struct mlx5_ifc_wq_bits wq;
3043};
3044
e281682b
SM		 3045union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
3046 struct mlx5_ifc_modify_field_select_bits modify_field_select;
3047 struct mlx5_ifc_resize_field_select_bits resize_field_select;
b4ff3a36 3048 u8 reserved_at_0[0x20];
e281682b
SM		 3049};
3050
3051union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
3052 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
3053 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
3054 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
b4ff3a36 3055 u8 reserved_at_0[0x20];
e281682b
SM		 3056};
3057
3058union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
3059 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
3060 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
3061 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
3062 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3063 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3064 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3065 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
1c64bf6f 3066 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b 3067 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
d8dc0508 3068 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
b4ff3a36 3069 u8 reserved_at_0[0x7c0];
e281682b
SM		 3070};
3071
8ed1a630
GP		 3072union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3073 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3074 u8 reserved_at_0[0x7c0];
3075};
3076
e281682b
SM		 3077union mlx5_ifc_event_auto_bits {
3078 struct mlx5_ifc_comp_event_bits comp_event;
3079 struct mlx5_ifc_dct_events_bits dct_events;
3080 struct mlx5_ifc_qp_events_bits qp_events;
3081 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3082 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3083 struct mlx5_ifc_cq_error_bits cq_error;
3084 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3085 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3086 struct mlx5_ifc_gpio_event_bits gpio_event;
3087 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3088 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3089 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
b4ff3a36 3090 u8 reserved_at_0[0xe0];
e281682b
SM		 3091};
3092
3093struct mlx5_ifc_health_buffer_bits {
b4ff3a36 3094 u8 reserved_at_0[0x100];
e281682b
SM		 3095
3096 u8 assert_existptr[0x20];
3097
3098 u8 assert_callra[0x20];
3099
b4ff3a36 3100 u8 reserved_at_140[0x40];
e281682b
SM		 3101
3102 u8 fw_version[0x20];
3103
3104 u8 hw_id[0x20];
3105
b4ff3a36 3106 u8 reserved_at_1c0[0x20];
e281682b
SM		 3107
3108 u8 irisc_index[0x8];
3109 u8 synd[0x8];
3110 u8 ext_synd[0x10];
3111};
3112
3113struct mlx5_ifc_register_loopback_control_bits {
3114 u8 no_lb[0x1];
b4ff3a36 3115 u8 reserved_at_1[0x7];
e281682b 3116 u8 port[0x8];
b4ff3a36 3117 u8 reserved_at_10[0x10];
e281682b 3118
b4ff3a36 3119 u8 reserved_at_20[0x60];
e281682b
SM		 3120};
3121
813f8540
MHY		 3122struct mlx5_ifc_vport_tc_element_bits {
3123 u8 traffic_class[0x4];
3124 u8 reserved_at_4[0xc];
3125 u8 vport_number[0x10];
3126};
3127
3128struct mlx5_ifc_vport_element_bits {
3129 u8 reserved_at_0[0x10];
3130 u8 vport_number[0x10];
3131};
3132
3133enum {
3134 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3135 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3136 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3137};
3138
3139struct mlx5_ifc_tsar_element_bits {
3140 u8 reserved_at_0[0x8];
3141 u8 tsar_type[0x8];
3142 u8 reserved_at_10[0x10];
3143};
3144
8812c24d
MD		 3145enum {
3146 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0,
3147 MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1,
3148};
3149
e281682b
SM		 3150struct mlx5_ifc_teardown_hca_out_bits {
3151 u8 status[0x8];
b4ff3a36 3152 u8 reserved_at_8[0x18];
e281682b
SM		 3153
3154 u8 syndrome[0x20];
3155
8812c24d
MD		 3156 u8 reserved_at_40[0x3f];
3157
3158 u8 force_state[0x1];
e281682b
SM		 3159};
3160
3161enum {
3162 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
8812c24d 3163 MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1,
e281682b
SM		 3164};
3165
3166struct mlx5_ifc_teardown_hca_in_bits {
3167 u8 opcode[0x10];
b4ff3a36 3168 u8 reserved_at_10[0x10];
e281682b 3169
b4ff3a36 3170 u8 reserved_at_20[0x10];
e281682b
SM		 3171 u8 op_mod[0x10];
3172
b4ff3a36 3173 u8 reserved_at_40[0x10];
e281682b
SM		 3174 u8 profile[0x10];
3175
b4ff3a36 3176 u8 reserved_at_60[0x20];
e281682b
SM		 3177};
3178
3179struct mlx5_ifc_sqerr2rts_qp_out_bits {
3180 u8 status[0x8];
b4ff3a36 3181 u8 reserved_at_8[0x18];
e281682b
SM		 3182
3183 u8 syndrome[0x20];
3184
b4ff3a36 3185 u8 reserved_at_40[0x40];
e281682b
SM		 3186};
3187
3188struct mlx5_ifc_sqerr2rts_qp_in_bits {
3189 u8 opcode[0x10];
b4ff3a36 3190 u8 reserved_at_10[0x10];
e281682b 3191
b4ff3a36 3192 u8 reserved_at_20[0x10];
e281682b
SM		 3193 u8 op_mod[0x10];
3194
b4ff3a36 3195 u8 reserved_at_40[0x8];
e281682b
SM		 3196 u8 qpn[0x18];
3197
b4ff3a36 3198 u8 reserved_at_60[0x20];
e281682b
SM		 3199
3200 u8 opt_param_mask[0x20];
3201
b4ff3a36 3202 u8 reserved_at_a0[0x20];
e281682b
SM		 3203
3204 struct mlx5_ifc_qpc_bits qpc;
3205
b4ff3a36 3206 u8 reserved_at_800[0x80];
e281682b
SM		 3207};
3208
3209struct mlx5_ifc_sqd2rts_qp_out_bits {
3210 u8 status[0x8];
b4ff3a36 3211 u8 reserved_at_8[0x18];
e281682b
SM		 3212
3213 u8 syndrome[0x20];
3214
b4ff3a36 3215 u8 reserved_at_40[0x40];
e281682b
SM		 3216};
3217
3218struct mlx5_ifc_sqd2rts_qp_in_bits {
3219 u8 opcode[0x10];
b4ff3a36 3220 u8 reserved_at_10[0x10];
e281682b 3221
b4ff3a36 3222 u8 reserved_at_20[0x10];
e281682b
SM		 3223 u8 op_mod[0x10];
3224
b4ff3a36 3225 u8 reserved_at_40[0x8];
e281682b
SM		 3226 u8 qpn[0x18];
3227
b4ff3a36 3228 u8 reserved_at_60[0x20];
e281682b
SM		 3229
3230 u8 opt_param_mask[0x20];
3231
b4ff3a36 3232 u8 reserved_at_a0[0x20];
e281682b
SM		 3233
3234 struct mlx5_ifc_qpc_bits qpc;
3235
b4ff3a36 3236 u8 reserved_at_800[0x80];
e281682b
SM		 3237};
3238
3239struct mlx5_ifc_set_roce_address_out_bits {
3240 u8 status[0x8];
b4ff3a36 3241 u8 reserved_at_8[0x18];
e281682b
SM		 3242
3243 u8 syndrome[0x20];
3244
b4ff3a36 3245 u8 reserved_at_40[0x40];
e281682b
SM		 3246};
3247
3248struct mlx5_ifc_set_roce_address_in_bits {
3249 u8 opcode[0x10];
b4ff3a36 3250 u8 reserved_at_10[0x10];
e281682b 3251
b4ff3a36 3252 u8 reserved_at_20[0x10];
e281682b
SM		 3253 u8 op_mod[0x10];
3254
3255 u8 roce_address_index[0x10];
b4ff3a36 3256 u8 reserved_at_50[0x10];
e281682b 3257
b4ff3a36 3258 u8 reserved_at_60[0x20];
e281682b
SM		 3259
3260 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3261};
3262
3263struct mlx5_ifc_set_mad_demux_out_bits {
3264 u8 status[0x8];
b4ff3a36 3265 u8 reserved_at_8[0x18];
e281682b
SM		 3266
3267 u8 syndrome[0x20];
3268
b4ff3a36 3269 u8 reserved_at_40[0x40];
e281682b
SM		 3270};
3271
3272enum {
3273 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
3274 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
3275};
3276
3277struct mlx5_ifc_set_mad_demux_in_bits {
3278 u8 opcode[0x10];
b4ff3a36 3279 u8 reserved_at_10[0x10];
e281682b 3280
b4ff3a36 3281 u8 reserved_at_20[0x10];
e281682b
SM		 3282 u8 op_mod[0x10];
3283
b4ff3a36 3284 u8 reserved_at_40[0x20];
e281682b 3285
b4ff3a36 3286 u8 reserved_at_60[0x6];
e281682b 3287 u8 demux_mode[0x2];
b4ff3a36 3288 u8 reserved_at_68[0x18];
e281682b
SM		 3289};
3290
3291struct mlx5_ifc_set_l2_table_entry_out_bits {
3292 u8 status[0x8];
b4ff3a36 3293 u8 reserved_at_8[0x18];
e281682b
SM		 3294
3295 u8 syndrome[0x20];
3296
b4ff3a36 3297 u8 reserved_at_40[0x40];
e281682b
SM		 3298};
3299
3300struct mlx5_ifc_set_l2_table_entry_in_bits {
3301 u8 opcode[0x10];
b4ff3a36 3302 u8 reserved_at_10[0x10];
e281682b 3303
b4ff3a36 3304 u8 reserved_at_20[0x10];
e281682b
SM		 3305 u8 op_mod[0x10];
3306
b4ff3a36 3307 u8 reserved_at_40[0x60];
e281682b 3308
b4ff3a36 3309 u8 reserved_at_a0[0x8];
e281682b
SM		 3310 u8 table_index[0x18];
3311
b4ff3a36 3312 u8 reserved_at_c0[0x20];
e281682b 3313
b4ff3a36 3314 u8 reserved_at_e0[0x13];
e281682b
SM		 3315 u8 vlan_valid[0x1];
3316 u8 vlan[0xc];
3317
3318 struct mlx5_ifc_mac_address_layout_bits mac_address;
3319
b4ff3a36 3320 u8 reserved_at_140[0xc0];
e281682b
SM		 3321};
3322
3323struct mlx5_ifc_set_issi_out_bits {
3324 u8 status[0x8];
b4ff3a36 3325 u8 reserved_at_8[0x18];
e281682b
SM		 3326
3327 u8 syndrome[0x20];
3328
b4ff3a36 3329 u8 reserved_at_40[0x40];
e281682b
SM		 3330};
3331
3332struct mlx5_ifc_set_issi_in_bits {
3333 u8 opcode[0x10];
b4ff3a36 3334 u8 reserved_at_10[0x10];
e281682b 3335
b4ff3a36 3336 u8 reserved_at_20[0x10];
e281682b
SM		 3337 u8 op_mod[0x10];
3338
b4ff3a36 3339 u8 reserved_at_40[0x10];
e281682b
SM		 3340 u8 current_issi[0x10];
3341
b4ff3a36 3342 u8 reserved_at_60[0x20];
e281682b
SM		 3343};
3344
3345struct mlx5_ifc_set_hca_cap_out_bits {
3346 u8 status[0x8];
b4ff3a36 3347 u8 reserved_at_8[0x18];
e281682b
SM		 3348
3349 u8 syndrome[0x20];
3350
b4ff3a36 3351 u8 reserved_at_40[0x40];
e281682b
SM		 3352};
3353
3354struct mlx5_ifc_set_hca_cap_in_bits {
3355 u8 opcode[0x10];
b4ff3a36 3356 u8 reserved_at_10[0x10];
e281682b 3357
b4ff3a36 3358 u8 reserved_at_20[0x10];
e281682b
SM		 3359 u8 op_mod[0x10];
3360
b4ff3a36 3361 u8 reserved_at_40[0x40];
e281682b
SM		 3362
3363 union mlx5_ifc_hca_cap_union_bits capability;
3364};
3365
26a81453
MG		 3366enum {
3367 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
3368 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
3369 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
3370 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
3371};
3372
e281682b
SM		 3373struct mlx5_ifc_set_fte_out_bits {
3374 u8 status[0x8];
b4ff3a36 3375 u8 reserved_at_8[0x18];
e281682b
SM		 3376
3377 u8 syndrome[0x20];
3378
b4ff3a36 3379 u8 reserved_at_40[0x40];
e281682b
SM		 3380};
3381
3382struct mlx5_ifc_set_fte_in_bits {
3383 u8 opcode[0x10];
b4ff3a36 3384 u8 reserved_at_10[0x10];
e281682b 3385
b4ff3a36 3386 u8 reserved_at_20[0x10];
e281682b
SM		 3387 u8 op_mod[0x10];
3388
7d5e1423
SM		 3389 u8 other_vport[0x1];
3390 u8 reserved_at_41[0xf];
3391 u8 vport_number[0x10];
3392
3393 u8 reserved_at_60[0x20];
e281682b
SM		 3394
3395 u8 table_type[0x8];
b4ff3a36 3396 u8 reserved_at_88[0x18];
e281682b 3397
b4ff3a36 3398 u8 reserved_at_a0[0x8];
e281682b
SM		 3399 u8 table_id[0x18];
3400
b4ff3a36 3401 u8 reserved_at_c0[0x18];
26a81453
MG		 3402 u8 modify_enable_mask[0x8];
3403
b4ff3a36 3404 u8 reserved_at_e0[0x20];
e281682b
SM		 3405
3406 u8 flow_index[0x20];
3407
b4ff3a36 3408 u8 reserved_at_120[0xe0];
e281682b
SM		 3409
3410 struct mlx5_ifc_flow_context_bits flow_context;
3411};
3412
3413struct mlx5_ifc_rts2rts_qp_out_bits {
3414 u8 status[0x8];
b4ff3a36 3415 u8 reserved_at_8[0x18];
e281682b
SM		 3416
3417 u8 syndrome[0x20];
3418
b4ff3a36 3419 u8 reserved_at_40[0x40];
e281682b
SM		 3420};
3421
3422struct mlx5_ifc_rts2rts_qp_in_bits {
3423 u8 opcode[0x10];
b4ff3a36 3424 u8 reserved_at_10[0x10];
e281682b 3425
b4ff3a36 3426 u8 reserved_at_20[0x10];
e281682b
SM		 3427 u8 op_mod[0x10];
3428
b4ff3a36 3429 u8 reserved_at_40[0x8];
e281682b
SM		 3430 u8 qpn[0x18];
3431
b4ff3a36 3432 u8 reserved_at_60[0x20];
e281682b
SM		 3433
3434 u8 opt_param_mask[0x20];
3435
b4ff3a36 3436 u8 reserved_at_a0[0x20];
e281682b
SM		 3437
3438 struct mlx5_ifc_qpc_bits qpc;
3439
b4ff3a36 3440 u8 reserved_at_800[0x80];
e281682b
SM		 3441};
3442
3443struct mlx5_ifc_rtr2rts_qp_out_bits {
3444 u8 status[0x8];
b4ff3a36 3445 u8 reserved_at_8[0x18];
e281682b
SM		 3446
3447 u8 syndrome[0x20];
3448
b4ff3a36 3449 u8 reserved_at_40[0x40];
e281682b
SM		 3450};
3451
3452struct mlx5_ifc_rtr2rts_qp_in_bits {
3453 u8 opcode[0x10];
b4ff3a36 3454 u8 reserved_at_10[0x10];
e281682b 3455
b4ff3a36 3456 u8 reserved_at_20[0x10];
e281682b
SM		 3457 u8 op_mod[0x10];
3458
b4ff3a36 3459 u8 reserved_at_40[0x8];
e281682b
SM		 3460 u8 qpn[0x18];
3461
b4ff3a36 3462 u8 reserved_at_60[0x20];
e281682b
SM		 3463
3464 u8 opt_param_mask[0x20];
3465
b4ff3a36 3466 u8 reserved_at_a0[0x20];
e281682b
SM		 3467
3468 struct mlx5_ifc_qpc_bits qpc;
3469
b4ff3a36 3470 u8 reserved_at_800[0x80];
e281682b
SM		 3471};
3472
3473struct mlx5_ifc_rst2init_qp_out_bits {
3474 u8 status[0x8];
b4ff3a36 3475 u8 reserved_at_8[0x18];
e281682b
SM		 3476
3477 u8 syndrome[0x20];
3478
b4ff3a36 3479 u8 reserved_at_40[0x40];
e281682b
SM		 3480};
3481
3482struct mlx5_ifc_rst2init_qp_in_bits {
3483 u8 opcode[0x10];
b4ff3a36 3484 u8 reserved_at_10[0x10];
e281682b 3485
b4ff3a36 3486 u8 reserved_at_20[0x10];
e281682b
SM		 3487 u8 op_mod[0x10];
3488
b4ff3a36 3489 u8 reserved_at_40[0x8];
e281682b
SM		 3490 u8 qpn[0x18];
3491
b4ff3a36 3492 u8 reserved_at_60[0x20];
e281682b
SM		 3493
3494 u8 opt_param_mask[0x20];
3495
b4ff3a36 3496 u8 reserved_at_a0[0x20];
e281682b
SM		 3497
3498 struct mlx5_ifc_qpc_bits qpc;
3499
b4ff3a36 3500 u8 reserved_at_800[0x80];
e281682b
SM		 3501};
3502
7486216b
SM		 3503struct mlx5_ifc_query_xrq_out_bits {
3504 u8 status[0x8];
3505 u8 reserved_at_8[0x18];
3506
3507 u8 syndrome[0x20];
3508
3509 u8 reserved_at_40[0x40];
3510
3511 struct mlx5_ifc_xrqc_bits xrq_context;
3512};
3513
3514struct mlx5_ifc_query_xrq_in_bits {
3515 u8 opcode[0x10];
3516 u8 reserved_at_10[0x10];
3517
3518 u8 reserved_at_20[0x10];
3519 u8 op_mod[0x10];
3520
3521 u8 reserved_at_40[0x8];
3522 u8 xrqn[0x18];
3523
3524 u8 reserved_at_60[0x20];
3525};
3526
e281682b
SM		 3527struct mlx5_ifc_query_xrc_srq_out_bits {
3528 u8 status[0x8];
b4ff3a36 3529 u8 reserved_at_8[0x18];
e281682b
SM		 3530
3531 u8 syndrome[0x20];
3532
b4ff3a36 3533 u8 reserved_at_40[0x40];
e281682b
SM		 3534
3535 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3536
b4ff3a36 3537 u8 reserved_at_280[0x600];
e281682b
SM		 3538
3539 u8 pas[0][0x40];
3540};
3541
3542struct mlx5_ifc_query_xrc_srq_in_bits {
3543 u8 opcode[0x10];
b4ff3a36 3544 u8 reserved_at_10[0x10];
e281682b 3545
b4ff3a36 3546 u8 reserved_at_20[0x10];
e281682b
SM		 3547 u8 op_mod[0x10];
3548
b4ff3a36 3549 u8 reserved_at_40[0x8];
e281682b
SM		 3550 u8 xrc_srqn[0x18];
3551
b4ff3a36 3552 u8 reserved_at_60[0x20];
e281682b
SM		 3553};
3554
3555enum {
3556 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
3557 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
3558};
3559
3560struct mlx5_ifc_query_vport_state_out_bits {
3561 u8 status[0x8];
b4ff3a36 3562 u8 reserved_at_8[0x18];
e281682b
SM		 3563
3564 u8 syndrome[0x20];
3565
b4ff3a36 3566 u8 reserved_at_40[0x20];
e281682b 3567
b4ff3a36 3568 u8 reserved_at_60[0x18];
e281682b
SM		 3569 u8 admin_state[0x4];
3570 u8 state[0x4];
3571};
3572
3573enum {
3574 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0,
e7546514 3575 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1,
e281682b
SM		 3576};
3577
3578struct mlx5_ifc_query_vport_state_in_bits {
3579 u8 opcode[0x10];
b4ff3a36 3580 u8 reserved_at_10[0x10];
e281682b 3581
b4ff3a36 3582 u8 reserved_at_20[0x10];
e281682b
SM		 3583 u8 op_mod[0x10];
3584
3585 u8 other_vport[0x1];
b4ff3a36 3586 u8 reserved_at_41[0xf];
e281682b
SM		 3587 u8 vport_number[0x10];
3588
b4ff3a36 3589 u8 reserved_at_60[0x20];
e281682b
SM		 3590};
3591
3592struct mlx5_ifc_query_vport_counter_out_bits {
3593 u8 status[0x8];
b4ff3a36 3594 u8 reserved_at_8[0x18];
e281682b
SM		 3595
3596 u8 syndrome[0x20];
3597
b4ff3a36 3598 u8 reserved_at_40[0x40];
e281682b
SM		 3599
3600 struct mlx5_ifc_traffic_counter_bits received_errors;
3601
3602 struct mlx5_ifc_traffic_counter_bits transmit_errors;
3603
3604 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3605
3606 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3607
3608 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3609
3610 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3611
3612 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3613
3614 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3615
3616 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3617
3618 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3619
3620 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3621
3622 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3623
b4ff3a36 3624 u8 reserved_at_680[0xa00];
e281682b
SM		 3625};
3626
3627enum {
3628 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
3629};
3630
3631struct mlx5_ifc_query_vport_counter_in_bits {
3632 u8 opcode[0x10];
b4ff3a36 3633 u8 reserved_at_10[0x10];
e281682b 3634
b4ff3a36 3635 u8 reserved_at_20[0x10];
e281682b
SM		 3636 u8 op_mod[0x10];
3637
3638 u8 other_vport[0x1];
b54ba277
MY		 3639 u8 reserved_at_41[0xb];
3640 u8 port_num[0x4];
e281682b
SM		 3641 u8 vport_number[0x10];
3642
b4ff3a36 3643 u8 reserved_at_60[0x60];
e281682b
SM		 3644
3645 u8 clear[0x1];
b4ff3a36 3646 u8 reserved_at_c1[0x1f];
e281682b 3647
b4ff3a36 3648 u8 reserved_at_e0[0x20];
e281682b
SM		 3649};
3650
3651struct mlx5_ifc_query_tis_out_bits {
3652 u8 status[0x8];
b4ff3a36 3653 u8 reserved_at_8[0x18];
e281682b
SM		 3654
3655 u8 syndrome[0x20];
3656
b4ff3a36 3657 u8 reserved_at_40[0x40];
e281682b
SM		 3658
3659 struct mlx5_ifc_tisc_bits tis_context;
3660};
3661
3662struct mlx5_ifc_query_tis_in_bits {
3663 u8 opcode[0x10];
b4ff3a36 3664 u8 reserved_at_10[0x10];
e281682b 3665
b4ff3a36 3666 u8 reserved_at_20[0x10];
e281682b
SM		 3667 u8 op_mod[0x10];
3668
b4ff3a36 3669 u8 reserved_at_40[0x8];
e281682b
SM		 3670 u8 tisn[0x18];
3671
b4ff3a36 3672 u8 reserved_at_60[0x20];
e281682b
SM		 3673};
3674
3675struct mlx5_ifc_query_tir_out_bits {
3676 u8 status[0x8];
b4ff3a36 3677 u8 reserved_at_8[0x18];
e281682b
SM		 3678
3679 u8 syndrome[0x20];
3680
b4ff3a36 3681 u8 reserved_at_40[0xc0];
e281682b
SM		 3682
3683 struct mlx5_ifc_tirc_bits tir_context;
3684};
3685
3686struct mlx5_ifc_query_tir_in_bits {
3687 u8 opcode[0x10];
b4ff3a36 3688 u8 reserved_at_10[0x10];
e281682b 3689
b4ff3a36 3690 u8 reserved_at_20[0x10];
e281682b
SM		 3691 u8 op_mod[0x10];
3692
b4ff3a36 3693 u8 reserved_at_40[0x8];
e281682b
SM		 3694 u8 tirn[0x18];
3695
b4ff3a36 3696 u8 reserved_at_60[0x20];
e281682b
SM		 3697};
3698
3699struct mlx5_ifc_query_srq_out_bits {
3700 u8 status[0x8];
b4ff3a36 3701 u8 reserved_at_8[0x18];
e281682b
SM		 3702
3703 u8 syndrome[0x20];
3704
b4ff3a36 3705 u8 reserved_at_40[0x40];
e281682b
SM		 3706
3707 struct mlx5_ifc_srqc_bits srq_context_entry;
3708
b4ff3a36 3709 u8 reserved_at_280[0x600];
e281682b
SM		 3710
3711 u8 pas[0][0x40];
3712};
3713
3714struct mlx5_ifc_query_srq_in_bits {
3715 u8 opcode[0x10];
b4ff3a36 3716 u8 reserved_at_10[0x10];
e281682b 3717
b4ff3a36 3718 u8 reserved_at_20[0x10];
e281682b
SM		 3719 u8 op_mod[0x10];
3720
b4ff3a36 3721 u8 reserved_at_40[0x8];
e281682b
SM		 3722 u8 srqn[0x18];
3723
b4ff3a36 3724 u8 reserved_at_60[0x20];
e281682b
SM		 3725};
3726
3727struct mlx5_ifc_query_sq_out_bits {
3728 u8 status[0x8];
b4ff3a36 3729 u8 reserved_at_8[0x18];
e281682b
SM		 3730
3731 u8 syndrome[0x20];
3732
b4ff3a36 3733 u8 reserved_at_40[0xc0];
e281682b
SM		 3734
3735 struct mlx5_ifc_sqc_bits sq_context;
3736};
3737
3738struct mlx5_ifc_query_sq_in_bits {
3739 u8 opcode[0x10];
b4ff3a36 3740 u8 reserved_at_10[0x10];
e281682b 3741
b4ff3a36 3742 u8 reserved_at_20[0x10];
e281682b
SM		 3743 u8 op_mod[0x10];
3744
b4ff3a36 3745 u8 reserved_at_40[0x8];
e281682b
SM		 3746 u8 sqn[0x18];
3747
b4ff3a36 3748 u8 reserved_at_60[0x20];
e281682b
SM		 3749};
3750
3751struct mlx5_ifc_query_special_contexts_out_bits {
3752 u8 status[0x8];
b4ff3a36 3753 u8 reserved_at_8[0x18];
e281682b
SM		 3754
3755 u8 syndrome[0x20];
3756
ec22eb53 3757 u8 dump_fill_mkey[0x20];
e281682b
SM		 3758
3759 u8 resd_lkey[0x20];
bcda1aca
AK		 3760
3761 u8 null_mkey[0x20];
3762
3763 u8 reserved_at_a0[0x60];
e281682b
SM		 3764};
3765
3766struct mlx5_ifc_query_special_contexts_in_bits {
3767 u8 opcode[0x10];
b4ff3a36 3768 u8 reserved_at_10[0x10];
e281682b 3769
b4ff3a36 3770 u8 reserved_at_20[0x10];
e281682b
SM		 3771 u8 op_mod[0x10];
3772
b4ff3a36 3773 u8 reserved_at_40[0x40];
e281682b
SM		 3774};
3775
813f8540
MHY		 3776struct mlx5_ifc_query_scheduling_element_out_bits {
3777 u8 opcode[0x10];
3778 u8 reserved_at_10[0x10];
3779
3780 u8 reserved_at_20[0x10];
3781 u8 op_mod[0x10];
3782
3783 u8 reserved_at_40[0xc0];
3784
3785 struct mlx5_ifc_scheduling_context_bits scheduling_context;
3786
3787 u8 reserved_at_300[0x100];
3788};
3789
3790enum {
3791 SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
3792};
3793
3794struct mlx5_ifc_query_scheduling_element_in_bits {
3795 u8 opcode[0x10];
3796 u8 reserved_at_10[0x10];
3797
3798 u8 reserved_at_20[0x10];
3799 u8 op_mod[0x10];
3800
3801 u8 scheduling_hierarchy[0x8];
3802 u8 reserved_at_48[0x18];
3803
3804 u8 scheduling_element_id[0x20];
3805
3806 u8 reserved_at_80[0x180];
3807};
3808
e281682b
SM		 3809struct mlx5_ifc_query_rqt_out_bits {
3810 u8 status[0x8];
b4ff3a36 3811 u8 reserved_at_8[0x18];
e281682b
SM		 3812
3813 u8 syndrome[0x20];
3814
b4ff3a36 3815 u8 reserved_at_40[0xc0];
e281682b
SM		 3816
3817 struct mlx5_ifc_rqtc_bits rqt_context;
3818};
3819
3820struct mlx5_ifc_query_rqt_in_bits {
3821 u8 opcode[0x10];
b4ff3a36 3822 u8 reserved_at_10[0x10];
e281682b 3823
b4ff3a36 3824 u8 reserved_at_20[0x10];
e281682b
SM		 3825 u8 op_mod[0x10];
3826
b4ff3a36 3827 u8 reserved_at_40[0x8];
e281682b
SM		 3828 u8 rqtn[0x18];
3829
b4ff3a36 3830 u8 reserved_at_60[0x20];
e281682b
SM		 3831};
3832
3833struct mlx5_ifc_query_rq_out_bits {
3834 u8 status[0x8];
b4ff3a36 3835 u8 reserved_at_8[0x18];
e281682b
SM		 3836
3837 u8 syndrome[0x20];
3838
b4ff3a36 3839 u8 reserved_at_40[0xc0];
e281682b
SM		 3840
3841 struct mlx5_ifc_rqc_bits rq_context;
3842};
3843
3844struct mlx5_ifc_query_rq_in_bits {
3845 u8 opcode[0x10];
b4ff3a36 3846 u8 reserved_at_10[0x10];
e281682b 3847
b4ff3a36 3848 u8 reserved_at_20[0x10];
e281682b
SM		 3849 u8 op_mod[0x10];
3850
b4ff3a36 3851 u8 reserved_at_40[0x8];
e281682b
SM		 3852 u8 rqn[0x18];
3853
b4ff3a36 3854 u8 reserved_at_60[0x20];
e281682b
SM		 3855};
3856
3857struct mlx5_ifc_query_roce_address_out_bits {
3858 u8 status[0x8];
b4ff3a36 3859 u8 reserved_at_8[0x18];
e281682b
SM		 3860
3861 u8 syndrome[0x20];
3862
b4ff3a36 3863 u8 reserved_at_40[0x40];
e281682b
SM		 3864
3865 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3866};
3867
3868struct mlx5_ifc_query_roce_address_in_bits {
3869 u8 opcode[0x10];
b4ff3a36 3870 u8 reserved_at_10[0x10];
e281682b 3871
b4ff3a36 3872 u8 reserved_at_20[0x10];
e281682b
SM		 3873 u8 op_mod[0x10];
3874
3875 u8 roce_address_index[0x10];
b4ff3a36 3876 u8 reserved_at_50[0x10];
e281682b 3877
b4ff3a36 3878 u8 reserved_at_60[0x20];
e281682b
SM		 3879};
3880
3881struct mlx5_ifc_query_rmp_out_bits {
3882 u8 status[0x8];
b4ff3a36 3883 u8 reserved_at_8[0x18];
e281682b
SM		 3884
3885 u8 syndrome[0x20];
3886
b4ff3a36 3887 u8 reserved_at_40[0xc0];
e281682b
SM		 3888
3889 struct mlx5_ifc_rmpc_bits rmp_context;
3890};
3891
3892struct mlx5_ifc_query_rmp_in_bits {
3893 u8 opcode[0x10];
b4ff3a36 3894 u8 reserved_at_10[0x10];
e281682b 3895
b4ff3a36 3896 u8 reserved_at_20[0x10];
e281682b
SM		 3897 u8 op_mod[0x10];
3898
b4ff3a36 3899 u8 reserved_at_40[0x8];
e281682b
SM		 3900 u8 rmpn[0x18];
3901
b4ff3a36 3902 u8 reserved_at_60[0x20];
e281682b
SM		 3903};
3904
3905struct mlx5_ifc_query_qp_out_bits {
3906 u8 status[0x8];
b4ff3a36 3907 u8 reserved_at_8[0x18];
e281682b
SM		 3908
3909 u8 syndrome[0x20];
3910
b4ff3a36 3911 u8 reserved_at_40[0x40];
e281682b
SM		 3912
3913 u8 opt_param_mask[0x20];
3914
b4ff3a36 3915 u8 reserved_at_a0[0x20];
e281682b
SM		 3916
3917 struct mlx5_ifc_qpc_bits qpc;
3918
b4ff3a36 3919 u8 reserved_at_800[0x80];
e281682b
SM		 3920
3921 u8 pas[0][0x40];
3922};
3923
3924struct mlx5_ifc_query_qp_in_bits {
3925 u8 opcode[0x10];
b4ff3a36 3926 u8 reserved_at_10[0x10];
e281682b 3927
b4ff3a36 3928 u8 reserved_at_20[0x10];
e281682b
SM		 3929 u8 op_mod[0x10];
3930
b4ff3a36 3931 u8 reserved_at_40[0x8];
e281682b
SM		 3932 u8 qpn[0x18];
3933
b4ff3a36 3934 u8 reserved_at_60[0x20];
e281682b
SM		 3935};
3936
3937struct mlx5_ifc_query_q_counter_out_bits {
3938 u8 status[0x8];
b4ff3a36 3939 u8 reserved_at_8[0x18];
e281682b
SM		 3940
3941 u8 syndrome[0x20];
3942
b4ff3a36 3943 u8 reserved_at_40[0x40];
e281682b
SM		 3944
3945 u8 rx_write_requests[0x20];
3946
b4ff3a36 3947 u8 reserved_at_a0[0x20];
e281682b
SM		 3948
3949 u8 rx_read_requests[0x20];
3950
b4ff3a36 3951 u8 reserved_at_e0[0x20];
e281682b
SM		 3952
3953 u8 rx_atomic_requests[0x20];
3954
b4ff3a36 3955 u8 reserved_at_120[0x20];
e281682b
SM		 3956
3957 u8 rx_dct_connect[0x20];
3958
b4ff3a36 3959 u8 reserved_at_160[0x20];
e281682b
SM		 3960
3961 u8 out_of_buffer[0x20];
3962
b4ff3a36 3963 u8 reserved_at_1a0[0x20];
e281682b
SM		 3964
3965 u8 out_of_sequence[0x20];
3966
7486216b
SM		 3967 u8 reserved_at_1e0[0x20];
3968
3969 u8 duplicate_request[0x20];
3970
3971 u8 reserved_at_220[0x20];
3972
3973 u8 rnr_nak_retry_err[0x20];
3974
3975 u8 reserved_at_260[0x20];
3976
3977 u8 packet_seq_err[0x20];
3978
3979 u8 reserved_at_2a0[0x20];
3980
3981 u8 implied_nak_seq_err[0x20];
3982
3983 u8 reserved_at_2e0[0x20];
3984
3985 u8 local_ack_timeout_err[0x20];
3986
58dcb60a
PP		 3987 u8 reserved_at_320[0xa0];
3988
3989 u8 resp_local_length_error[0x20];
3990
3991 u8 req_local_length_error[0x20];
3992
3993 u8 resp_local_qp_error[0x20];
3994
3995 u8 local_operation_error[0x20];
3996
3997 u8 resp_local_protection[0x20];
3998
3999 u8 req_local_protection[0x20];
4000
4001 u8 resp_cqe_error[0x20];
4002
4003 u8 req_cqe_error[0x20];
4004
4005 u8 req_mw_binding[0x20];
4006
4007 u8 req_bad_response[0x20];
4008
4009 u8 req_remote_invalid_request[0x20];
4010
4011 u8 resp_remote_invalid_request[0x20];
4012
4013 u8 req_remote_access_errors[0x20];
4014
4015 u8 resp_remote_access_errors[0x20];
4016
4017 u8 req_remote_operation_errors[0x20];
4018
4019 u8 req_transport_retries_exceeded[0x20];
4020
4021 u8 cq_overflow[0x20];
4022
4023 u8 resp_cqe_flush_error[0x20];
4024
4025 u8 req_cqe_flush_error[0x20];
4026
4027 u8 reserved_at_620[0x1e0];
e281682b
SM		 4028};
4029
4030struct mlx5_ifc_query_q_counter_in_bits {
4031 u8 opcode[0x10];
b4ff3a36 4032 u8 reserved_at_10[0x10];
e281682b 4033
b4ff3a36 4034 u8 reserved_at_20[0x10];
e281682b
SM		 4035 u8 op_mod[0x10];
4036
b4ff3a36 4037 u8 reserved_at_40[0x80];
e281682b
SM		 4038
4039 u8 clear[0x1];
b4ff3a36 4040 u8 reserved_at_c1[0x1f];
e281682b 4041
b4ff3a36 4042 u8 reserved_at_e0[0x18];
e281682b
SM		 4043 u8 counter_set_id[0x8];
4044};
4045
4046struct mlx5_ifc_query_pages_out_bits {
4047 u8 status[0x8];
b4ff3a36 4048 u8 reserved_at_8[0x18];
e281682b
SM		 4049
4050 u8 syndrome[0x20];
4051
b4ff3a36 4052 u8 reserved_at_40[0x10];
e281682b
SM		 4053 u8 function_id[0x10];
4054
4055 u8 num_pages[0x20];
4056};
4057
4058enum {
4059 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
4060 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
4061 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
4062};
4063
4064struct mlx5_ifc_query_pages_in_bits {
4065 u8 opcode[0x10];
b4ff3a36 4066 u8 reserved_at_10[0x10];
e281682b 4067
b4ff3a36 4068 u8 reserved_at_20[0x10];
e281682b
SM		 4069 u8 op_mod[0x10];
4070
b4ff3a36 4071 u8 reserved_at_40[0x10];
e281682b
SM		 4072 u8 function_id[0x10];
4073
b4ff3a36 4074 u8 reserved_at_60[0x20];
e281682b
SM		 4075};
4076
4077struct mlx5_ifc_query_nic_vport_context_out_bits {
4078 u8 status[0x8];
b4ff3a36 4079 u8 reserved_at_8[0x18];
e281682b
SM		 4080
4081 u8 syndrome[0x20];
4082
b4ff3a36 4083 u8 reserved_at_40[0x40];
e281682b
SM		 4084
4085 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4086};
4087
4088struct mlx5_ifc_query_nic_vport_context_in_bits {
4089 u8 opcode[0x10];
b4ff3a36 4090 u8 reserved_at_10[0x10];
e281682b 4091
b4ff3a36 4092 u8 reserved_at_20[0x10];
e281682b
SM		 4093 u8 op_mod[0x10];
4094
4095 u8 other_vport[0x1];
b4ff3a36 4096 u8 reserved_at_41[0xf];
e281682b
SM		 4097 u8 vport_number[0x10];
4098
b4ff3a36 4099 u8 reserved_at_60[0x5];
e281682b 4100 u8 allowed_list_type[0x3];
b4ff3a36 4101 u8 reserved_at_68[0x18];
e281682b
SM		 4102};
4103
4104struct mlx5_ifc_query_mkey_out_bits {
4105 u8 status[0x8];
b4ff3a36 4106 u8 reserved_at_8[0x18];
e281682b
SM		 4107
4108 u8 syndrome[0x20];
4109
b4ff3a36 4110 u8 reserved_at_40[0x40];
e281682b
SM		 4111
4112 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4113
b4ff3a36 4114 u8 reserved_at_280[0x600];
e281682b
SM		 4115
4116 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
4117
4118 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
4119};
4120
4121struct mlx5_ifc_query_mkey_in_bits {
4122 u8 opcode[0x10];
b4ff3a36 4123 u8 reserved_at_10[0x10];
e281682b 4124
b4ff3a36 4125 u8 reserved_at_20[0x10];
e281682b
SM		 4126 u8 op_mod[0x10];
4127
b4ff3a36 4128 u8 reserved_at_40[0x8];
e281682b
SM		 4129 u8 mkey_index[0x18];
4130
4131 u8 pg_access[0x1];
b4ff3a36 4132 u8 reserved_at_61[0x1f];
e281682b
SM		 4133};
4134
4135struct mlx5_ifc_query_mad_demux_out_bits {
4136 u8 status[0x8];
b4ff3a36 4137 u8 reserved_at_8[0x18];
e281682b
SM		 4138
4139 u8 syndrome[0x20];
4140
b4ff3a36 4141 u8 reserved_at_40[0x40];
e281682b
SM		 4142
4143 u8 mad_dumux_parameters_block[0x20];
4144};
4145
4146struct mlx5_ifc_query_mad_demux_in_bits {
4147 u8 opcode[0x10];
b4ff3a36 4148 u8 reserved_at_10[0x10];
e281682b 4149
b4ff3a36 4150 u8 reserved_at_20[0x10];
e281682b
SM		 4151 u8 op_mod[0x10];
4152
b4ff3a36 4153 u8 reserved_at_40[0x40];
e281682b
SM		 4154};
4155
4156struct mlx5_ifc_query_l2_table_entry_out_bits {
4157 u8 status[0x8];
b4ff3a36 4158 u8 reserved_at_8[0x18];
e281682b
SM		 4159
4160 u8 syndrome[0x20];
4161
b4ff3a36 4162 u8 reserved_at_40[0xa0];
e281682b 4163
b4ff3a36 4164 u8 reserved_at_e0[0x13];
e281682b
SM		 4165 u8 vlan_valid[0x1];
4166 u8 vlan[0xc];
4167
4168 struct mlx5_ifc_mac_address_layout_bits mac_address;
4169
b4ff3a36 4170 u8 reserved_at_140[0xc0];
e281682b
SM		 4171};
4172
4173struct mlx5_ifc_query_l2_table_entry_in_bits {
4174 u8 opcode[0x10];
b4ff3a36 4175 u8 reserved_at_10[0x10];
e281682b 4176
b4ff3a36 4177 u8 reserved_at_20[0x10];
e281682b
SM		 4178 u8 op_mod[0x10];
4179
b4ff3a36 4180 u8 reserved_at_40[0x60];
e281682b 4181
b4ff3a36 4182 u8 reserved_at_a0[0x8];
e281682b
SM		 4183 u8 table_index[0x18];
4184
b4ff3a36 4185 u8 reserved_at_c0[0x140];
e281682b
SM		 4186};
4187
4188struct mlx5_ifc_query_issi_out_bits {
4189 u8 status[0x8];
b4ff3a36 4190 u8 reserved_at_8[0x18];
e281682b
SM		 4191
4192 u8 syndrome[0x20];
4193
b4ff3a36 4194 u8 reserved_at_40[0x10];
e281682b
SM		 4195 u8 current_issi[0x10];
4196
b4ff3a36 4197 u8 reserved_at_60[0xa0];
e281682b 4198
b4ff3a36 4199 u8 reserved_at_100[76][0x8];
e281682b
SM		 4200 u8 supported_issi_dw0[0x20];
4201};
4202
4203struct mlx5_ifc_query_issi_in_bits {
4204 u8 opcode[0x10];
b4ff3a36 4205 u8 reserved_at_10[0x10];
e281682b 4206
b4ff3a36 4207 u8 reserved_at_20[0x10];
e281682b
SM		 4208 u8 op_mod[0x10];
4209
b4ff3a36 4210 u8 reserved_at_40[0x40];
e281682b
SM		 4211};
4212
0dbc6fe0
SM		 4213struct mlx5_ifc_set_driver_version_out_bits {
4214 u8 status[0x8];
4215 u8 reserved_0[0x18];
4216
4217 u8 syndrome[0x20];
4218 u8 reserved_1[0x40];
4219};
4220
4221struct mlx5_ifc_set_driver_version_in_bits {
4222 u8 opcode[0x10];
4223 u8 reserved_0[0x10];
4224
4225 u8 reserved_1[0x10];
4226 u8 op_mod[0x10];
4227
4228 u8 reserved_2[0x40];
4229 u8 driver_version[64][0x8];
4230};
4231
e281682b
SM		 4232struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4233 u8 status[0x8];
b4ff3a36 4234 u8 reserved_at_8[0x18];
e281682b
SM		 4235
4236 u8 syndrome[0x20];
4237
b4ff3a36 4238 u8 reserved_at_40[0x40];
e281682b
SM		 4239
4240 struct mlx5_ifc_pkey_bits pkey[0];
4241};
4242
4243struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4244 u8 opcode[0x10];
b4ff3a36 4245 u8 reserved_at_10[0x10];
e281682b 4246
b4ff3a36 4247 u8 reserved_at_20[0x10];
e281682b
SM		 4248 u8 op_mod[0x10];
4249
4250 u8 other_vport[0x1];
b4ff3a36 4251 u8 reserved_at_41[0xb];
707c4602 4252 u8 port_num[0x4];
e281682b
SM		 4253 u8 vport_number[0x10];
4254
b4ff3a36 4255 u8 reserved_at_60[0x10];
e281682b
SM		 4256 u8 pkey_index[0x10];
4257};
4258
eff901d3
EC		 4259enum {
4260 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
4261 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
4262 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4263};
4264
e281682b
SM		 4265struct mlx5_ifc_query_hca_vport_gid_out_bits {
4266 u8 status[0x8];
b4ff3a36 4267 u8 reserved_at_8[0x18];
e281682b
SM		 4268
4269 u8 syndrome[0x20];
4270
b4ff3a36 4271 u8 reserved_at_40[0x20];
e281682b
SM		 4272
4273 u8 gids_num[0x10];
b4ff3a36 4274 u8 reserved_at_70[0x10];
e281682b
SM		 4275
4276 struct mlx5_ifc_array128_auto_bits gid[0];
4277};
4278
4279struct mlx5_ifc_query_hca_vport_gid_in_bits {
4280 u8 opcode[0x10];
b4ff3a36 4281 u8 reserved_at_10[0x10];
e281682b 4282
b4ff3a36 4283 u8 reserved_at_20[0x10];
e281682b
SM		 4284 u8 op_mod[0x10];
4285
4286 u8 other_vport[0x1];
b4ff3a36 4287 u8 reserved_at_41[0xb];
707c4602 4288 u8 port_num[0x4];
e281682b
SM		 4289 u8 vport_number[0x10];
4290
b4ff3a36 4291 u8 reserved_at_60[0x10];
e281682b
SM		 4292 u8 gid_index[0x10];
4293};
4294
4295struct mlx5_ifc_query_hca_vport_context_out_bits {
4296 u8 status[0x8];
b4ff3a36 4297 u8 reserved_at_8[0x18];
e281682b
SM		 4298
4299 u8 syndrome[0x20];
4300
b4ff3a36 4301 u8 reserved_at_40[0x40];
e281682b
SM		 4302
4303 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4304};
4305
4306struct mlx5_ifc_query_hca_vport_context_in_bits {
4307 u8 opcode[0x10];
b4ff3a36 4308 u8 reserved_at_10[0x10];
e281682b 4309
b4ff3a36 4310 u8 reserved_at_20[0x10];
e281682b
SM		 4311 u8 op_mod[0x10];
4312
4313 u8 other_vport[0x1];
b4ff3a36 4314 u8 reserved_at_41[0xb];
707c4602 4315 u8 port_num[0x4];
e281682b
SM		 4316 u8 vport_number[0x10];
4317
b4ff3a36 4318 u8 reserved_at_60[0x20];
e281682b
SM		 4319};
4320
4321struct mlx5_ifc_query_hca_cap_out_bits {
4322 u8 status[0x8];
b4ff3a36 4323 u8 reserved_at_8[0x18];
e281682b
SM		 4324
4325 u8 syndrome[0x20];
4326
b4ff3a36 4327 u8 reserved_at_40[0x40];
e281682b
SM		 4328
4329 union mlx5_ifc_hca_cap_union_bits capability;
4330};
4331
4332struct mlx5_ifc_query_hca_cap_in_bits {
4333 u8 opcode[0x10];
b4ff3a36 4334 u8 reserved_at_10[0x10];
e281682b 4335
b4ff3a36 4336 u8 reserved_at_20[0x10];
e281682b
SM		 4337 u8 op_mod[0x10];
4338
b4ff3a36 4339 u8 reserved_at_40[0x40];
e281682b
SM		 4340};
4341
4342struct mlx5_ifc_query_flow_table_out_bits {
4343 u8 status[0x8];
b4ff3a36 4344 u8 reserved_at_8[0x18];
e281682b
SM		 4345
4346 u8 syndrome[0x20];
4347
b4ff3a36 4348 u8 reserved_at_40[0x80];
e281682b 4349
b4ff3a36 4350 u8 reserved_at_c0[0x8];
e281682b 4351 u8 level[0x8];
b4ff3a36 4352 u8 reserved_at_d0[0x8];
e281682b
SM		 4353 u8 log_size[0x8];
4354
b4ff3a36 4355 u8 reserved_at_e0[0x120];
e281682b
SM		 4356};
4357
4358struct mlx5_ifc_query_flow_table_in_bits {
4359 u8 opcode[0x10];
b4ff3a36 4360 u8 reserved_at_10[0x10];
e281682b 4361
b4ff3a36 4362 u8 reserved_at_20[0x10];
e281682b
SM		 4363 u8 op_mod[0x10];
4364
b4ff3a36 4365 u8 reserved_at_40[0x40];
e281682b
SM		 4366
4367 u8 table_type[0x8];
b4ff3a36 4368 u8 reserved_at_88[0x18];
e281682b 4369
b4ff3a36 4370 u8 reserved_at_a0[0x8];
e281682b
SM		 4371 u8 table_id[0x18];
4372
b4ff3a36 4373 u8 reserved_at_c0[0x140];
e281682b
SM		 4374};
4375
4376struct mlx5_ifc_query_fte_out_bits {
4377 u8 status[0x8];
b4ff3a36 4378 u8 reserved_at_8[0x18];
e281682b
SM		 4379
4380 u8 syndrome[0x20];
4381
b4ff3a36 4382 u8 reserved_at_40[0x1c0];
e281682b
SM		 4383
4384 struct mlx5_ifc_flow_context_bits flow_context;
4385};
4386
4387struct mlx5_ifc_query_fte_in_bits {
4388 u8 opcode[0x10];
b4ff3a36 4389 u8 reserved_at_10[0x10];
e281682b 4390
b4ff3a36 4391 u8 reserved_at_20[0x10];
e281682b
SM		 4392 u8 op_mod[0x10];
4393
b4ff3a36 4394 u8 reserved_at_40[0x40];
e281682b
SM		 4395
4396 u8 table_type[0x8];
b4ff3a36 4397 u8 reserved_at_88[0x18];
e281682b 4398
b4ff3a36 4399 u8 reserved_at_a0[0x8];
e281682b
SM		 4400 u8 table_id[0x18];
4401
b4ff3a36 4402 u8 reserved_at_c0[0x40];
e281682b
SM		 4403
4404 u8 flow_index[0x20];
4405
b4ff3a36 4406 u8 reserved_at_120[0xe0];
e281682b
SM		 4407};
4408
4409enum {
4410 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
4411 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
4412 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
4413};
4414
4415struct mlx5_ifc_query_flow_group_out_bits {
4416 u8 status[0x8];
b4ff3a36 4417 u8 reserved_at_8[0x18];
e281682b
SM		 4418
4419 u8 syndrome[0x20];
4420
b4ff3a36 4421 u8 reserved_at_40[0xa0];
e281682b
SM		 4422
4423 u8 start_flow_index[0x20];
4424
b4ff3a36 4425 u8 reserved_at_100[0x20];
e281682b
SM		 4426
4427 u8 end_flow_index[0x20];
4428
b4ff3a36 4429 u8 reserved_at_140[0xa0];
e281682b 4430
b4ff3a36 4431 u8 reserved_at_1e0[0x18];
e281682b
SM		 4432 u8 match_criteria_enable[0x8];
4433
4434 struct mlx5_ifc_fte_match_param_bits match_criteria;
4435
b4ff3a36 4436 u8 reserved_at_1200[0xe00];
e281682b
SM		 4437};
4438
4439struct mlx5_ifc_query_flow_group_in_bits {
4440 u8 opcode[0x10];
b4ff3a36 4441 u8 reserved_at_10[0x10];
e281682b 4442
b4ff3a36 4443 u8 reserved_at_20[0x10];
e281682b
SM		 4444 u8 op_mod[0x10];
4445
b4ff3a36 4446 u8 reserved_at_40[0x40];
e281682b
SM		 4447
4448 u8 table_type[0x8];
b4ff3a36 4449 u8 reserved_at_88[0x18];
e281682b 4450
b4ff3a36 4451 u8 reserved_at_a0[0x8];
e281682b
SM		 4452 u8 table_id[0x18];
4453
4454 u8 group_id[0x20];
4455
b4ff3a36 4456 u8 reserved_at_e0[0x120];
e281682b
SM		 4457};
4458
9dc0b289
AV		 4459struct mlx5_ifc_query_flow_counter_out_bits {
4460 u8 status[0x8];
4461 u8 reserved_at_8[0x18];
4462
4463 u8 syndrome[0x20];
4464
4465 u8 reserved_at_40[0x40];
4466
4467 struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4468};
4469
4470struct mlx5_ifc_query_flow_counter_in_bits {
4471 u8 opcode[0x10];
4472 u8 reserved_at_10[0x10];
4473
4474 u8 reserved_at_20[0x10];
4475 u8 op_mod[0x10];
4476
4477 u8 reserved_at_40[0x80];
4478
4479 u8 clear[0x1];
4480 u8 reserved_at_c1[0xf];
4481 u8 num_of_counters[0x10];
4482
a8ffcc74 4483 u8 flow_counter_id[0x20];
9dc0b289
AV		 4484};
4485
d6666753
SM		 4486struct mlx5_ifc_query_esw_vport_context_out_bits {
4487 u8 status[0x8];
b4ff3a36 4488 u8 reserved_at_8[0x18];
d6666753
SM		 4489
4490 u8 syndrome[0x20];
4491
b4ff3a36 4492 u8 reserved_at_40[0x40];
d6666753
SM		 4493
4494 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4495};
4496
4497struct mlx5_ifc_query_esw_vport_context_in_bits {
4498 u8 opcode[0x10];
b4ff3a36 4499 u8 reserved_at_10[0x10];
d6666753 4500
b4ff3a36 4501 u8 reserved_at_20[0x10];
d6666753
SM		 4502 u8 op_mod[0x10];
4503
4504 u8 other_vport[0x1];
b4ff3a36 4505 u8 reserved_at_41[0xf];
d6666753
SM		 4506 u8 vport_number[0x10];
4507
b4ff3a36 4508 u8 reserved_at_60[0x20];
d6666753
SM		 4509};
4510
4511struct mlx5_ifc_modify_esw_vport_context_out_bits {
4512 u8 status[0x8];
b4ff3a36 4513 u8 reserved_at_8[0x18];
d6666753
SM		 4514
4515 u8 syndrome[0x20];
4516
b4ff3a36 4517 u8 reserved_at_40[0x40];
d6666753
SM		 4518};
4519
4520struct mlx5_ifc_esw_vport_context_fields_select_bits {
b4ff3a36 4521 u8 reserved_at_0[0x1c];
d6666753
SM		 4522 u8 vport_cvlan_insert[0x1];
4523 u8 vport_svlan_insert[0x1];
4524 u8 vport_cvlan_strip[0x1];
4525 u8 vport_svlan_strip[0x1];
4526};
4527
4528struct mlx5_ifc_modify_esw_vport_context_in_bits {
4529 u8 opcode[0x10];
b4ff3a36 4530 u8 reserved_at_10[0x10];
d6666753 4531
b4ff3a36 4532 u8 reserved_at_20[0x10];
d6666753
SM		 4533 u8 op_mod[0x10];
4534
4535 u8 other_vport[0x1];
b4ff3a36 4536 u8 reserved_at_41[0xf];
d6666753
SM		 4537 u8 vport_number[0x10];
4538
4539 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4540
4541 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4542};
4543
e281682b
SM		 4544struct mlx5_ifc_query_eq_out_bits {
4545 u8 status[0x8];
b4ff3a36 4546 u8 reserved_at_8[0x18];
e281682b
SM		 4547
4548 u8 syndrome[0x20];
4549
b4ff3a36 4550 u8 reserved_at_40[0x40];
e281682b
SM		 4551
4552 struct mlx5_ifc_eqc_bits eq_context_entry;
4553
b4ff3a36 4554 u8 reserved_at_280[0x40];
e281682b
SM		 4555
4556 u8 event_bitmask[0x40];
4557
b4ff3a36 4558 u8 reserved_at_300[0x580];
e281682b
SM		 4559
4560 u8 pas[0][0x40];
4561};
4562
4563struct mlx5_ifc_query_eq_in_bits {
4564 u8 opcode[0x10];
b4ff3a36 4565 u8 reserved_at_10[0x10];
e281682b 4566
b4ff3a36 4567 u8 reserved_at_20[0x10];
e281682b
SM		 4568 u8 op_mod[0x10];
4569
b4ff3a36 4570 u8 reserved_at_40[0x18];
e281682b
SM		 4571 u8 eq_number[0x8];
4572
b4ff3a36 4573 u8 reserved_at_60[0x20];
e281682b
SM		 4574};
4575
7adbde20
HHZ		 4576struct mlx5_ifc_encap_header_in_bits {
4577 u8 reserved_at_0[0x5];
4578 u8 header_type[0x3];
4579 u8 reserved_at_8[0xe];
4580 u8 encap_header_size[0xa];
4581
4582 u8 reserved_at_20[0x10];
4583 u8 encap_header[2][0x8];
4584
4585 u8 more_encap_header[0][0x8];
4586};
4587
4588struct mlx5_ifc_query_encap_header_out_bits {
4589 u8 status[0x8];
4590 u8 reserved_at_8[0x18];
4591
4592 u8 syndrome[0x20];
4593
4594 u8 reserved_at_40[0xa0];
4595
4596 struct mlx5_ifc_encap_header_in_bits encap_header[0];
4597};
4598
4599struct mlx5_ifc_query_encap_header_in_bits {
4600 u8 opcode[0x10];
4601 u8 reserved_at_10[0x10];
4602
4603 u8 reserved_at_20[0x10];
4604 u8 op_mod[0x10];
4605
4606 u8 encap_id[0x20];
4607
4608 u8 reserved_at_60[0xa0];
4609};
4610
4611struct mlx5_ifc_alloc_encap_header_out_bits {
4612 u8 status[0x8];
4613 u8 reserved_at_8[0x18];
4614
4615 u8 syndrome[0x20];
4616
4617 u8 encap_id[0x20];
4618
4619 u8 reserved_at_60[0x20];
4620};
4621
4622struct mlx5_ifc_alloc_encap_header_in_bits {
4623 u8 opcode[0x10];
4624 u8 reserved_at_10[0x10];
4625
4626 u8 reserved_at_20[0x10];
4627 u8 op_mod[0x10];
4628
4629 u8 reserved_at_40[0xa0];
4630
4631 struct mlx5_ifc_encap_header_in_bits encap_header;
4632};
4633
4634struct mlx5_ifc_dealloc_encap_header_out_bits {
4635 u8 status[0x8];
4636 u8 reserved_at_8[0x18];
4637
4638 u8 syndrome[0x20];
4639
4640 u8 reserved_at_40[0x40];
4641};
4642
4643struct mlx5_ifc_dealloc_encap_header_in_bits {
4644 u8 opcode[0x10];
4645 u8 reserved_at_10[0x10];
4646
4647 u8 reserved_20[0x10];
4648 u8 op_mod[0x10];
4649
4650 u8 encap_id[0x20];
4651
4652 u8 reserved_60[0x20];
4653};
4654
2a69cb9f
OG		 4655struct mlx5_ifc_set_action_in_bits {
4656 u8 action_type[0x4];
4657 u8 field[0xc];
4658 u8 reserved_at_10[0x3];
4659 u8 offset[0x5];
4660 u8 reserved_at_18[0x3];
4661 u8 length[0x5];
4662
4663 u8 data[0x20];
4664};
4665
4666struct mlx5_ifc_add_action_in_bits {
4667 u8 action_type[0x4];
4668 u8 field[0xc];
4669 u8 reserved_at_10[0x10];
4670
4671 u8 data[0x20];
4672};
4673
4674union mlx5_ifc_set_action_in_add_action_in_auto_bits {
4675 struct mlx5_ifc_set_action_in_bits set_action_in;
4676 struct mlx5_ifc_add_action_in_bits add_action_in;
4677 u8 reserved_at_0[0x40];
4678};
4679
4680enum {
4681 MLX5_ACTION_TYPE_SET = 0x1,
4682 MLX5_ACTION_TYPE_ADD = 0x2,
4683};
4684
4685enum {
4686 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1,
4687 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2,
4688 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3,
4689 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4,
4690 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5,
4691 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6,
4692 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7,
4693 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8,
4694 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9,
4695 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa,
4696 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb,
4697 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc,
4698 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd,
4699 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe,
4700 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf,
4701 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10,
4702 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11,
4703 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12,
4704 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13,
4705 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14,
4706 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15,
4707 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16,
0c0316f5 4708 MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47,
2a69cb9f
OG		 4709};
4710
4711struct mlx5_ifc_alloc_modify_header_context_out_bits {
4712 u8 status[0x8];
4713 u8 reserved_at_8[0x18];
4714
4715 u8 syndrome[0x20];
4716
4717 u8 modify_header_id[0x20];
4718
4719 u8 reserved_at_60[0x20];
4720};
4721
4722struct mlx5_ifc_alloc_modify_header_context_in_bits {
4723 u8 opcode[0x10];
4724 u8 reserved_at_10[0x10];
4725
4726 u8 reserved_at_20[0x10];
4727 u8 op_mod[0x10];
4728
4729 u8 reserved_at_40[0x20];
4730
4731 u8 table_type[0x8];
4732 u8 reserved_at_68[0x10];
4733 u8 num_of_actions[0x8];
4734
4735 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
4736};
4737
4738struct mlx5_ifc_dealloc_modify_header_context_out_bits {
4739 u8 status[0x8];
4740 u8 reserved_at_8[0x18];
4741
4742 u8 syndrome[0x20];
4743
4744 u8 reserved_at_40[0x40];
4745};
4746
4747struct mlx5_ifc_dealloc_modify_header_context_in_bits {
4748 u8 opcode[0x10];
4749 u8 reserved_at_10[0x10];
4750
4751 u8 reserved_at_20[0x10];
4752 u8 op_mod[0x10];
4753
4754 u8 modify_header_id[0x20];
4755
4756 u8 reserved_at_60[0x20];
4757};
4758
e281682b
SM		 4759struct mlx5_ifc_query_dct_out_bits {
4760 u8 status[0x8];
b4ff3a36 4761 u8 reserved_at_8[0x18];
e281682b
SM		 4762
4763 u8 syndrome[0x20];
4764
b4ff3a36 4765 u8 reserved_at_40[0x40];
e281682b
SM		 4766
4767 struct mlx5_ifc_dctc_bits dct_context_entry;
4768
b4ff3a36 4769 u8 reserved_at_280[0x180];
e281682b
SM		 4770};
4771
4772struct mlx5_ifc_query_dct_in_bits {
4773 u8 opcode[0x10];
b4ff3a36 4774 u8 reserved_at_10[0x10];
e281682b 4775
b4ff3a36 4776 u8 reserved_at_20[0x10];
e281682b
SM		 4777 u8 op_mod[0x10];
4778
b4ff3a36 4779 u8 reserved_at_40[0x8];
e281682b
SM		 4780 u8 dctn[0x18];
4781
b4ff3a36 4782 u8 reserved_at_60[0x20];
e281682b
SM		 4783};
4784
4785struct mlx5_ifc_query_cq_out_bits {
4786 u8 status[0x8];
b4ff3a36 4787 u8 reserved_at_8[0x18];
e281682b
SM		 4788
4789 u8 syndrome[0x20];
4790
b4ff3a36 4791 u8 reserved_at_40[0x40];
e281682b
SM		 4792
4793 struct mlx5_ifc_cqc_bits cq_context;
4794
b4ff3a36 4795 u8 reserved_at_280[0x600];
e281682b
SM		 4796
4797 u8 pas[0][0x40];
4798};
4799
4800struct mlx5_ifc_query_cq_in_bits {
4801 u8 opcode[0x10];
b4ff3a36 4802 u8 reserved_at_10[0x10];
e281682b 4803
b4ff3a36 4804 u8 reserved_at_20[0x10];
e281682b
SM		 4805 u8 op_mod[0x10];
4806
b4ff3a36 4807 u8 reserved_at_40[0x8];
e281682b
SM		 4808 u8 cqn[0x18];
4809
b4ff3a36 4810 u8 reserved_at_60[0x20];
e281682b
SM		 4811};
4812
4813struct mlx5_ifc_query_cong_status_out_bits {
4814 u8 status[0x8];
b4ff3a36 4815 u8 reserved_at_8[0x18];
e281682b
SM		 4816
4817 u8 syndrome[0x20];
4818
b4ff3a36 4819 u8 reserved_at_40[0x20];
e281682b
SM		 4820
4821 u8 enable[0x1];
4822 u8 tag_enable[0x1];
b4ff3a36 4823 u8 reserved_at_62[0x1e];
e281682b
SM		 4824};
4825
4826struct mlx5_ifc_query_cong_status_in_bits {
4827 u8 opcode[0x10];
b4ff3a36 4828 u8 reserved_at_10[0x10];
e281682b 4829
b4ff3a36 4830 u8 reserved_at_20[0x10];
e281682b
SM		 4831 u8 op_mod[0x10];
4832
b4ff3a36 4833 u8 reserved_at_40[0x18];
e281682b
SM		 4834 u8 priority[0x4];
4835 u8 cong_protocol[0x4];
4836
b4ff3a36 4837 u8 reserved_at_60[0x20];
e281682b
SM		 4838};
4839
4840struct mlx5_ifc_query_cong_statistics_out_bits {
4841 u8 status[0x8];
b4ff3a36 4842 u8 reserved_at_8[0x18];
e281682b
SM		 4843
4844 u8 syndrome[0x20];
4845
b4ff3a36 4846 u8 reserved_at_40[0x40];
e281682b 4847
e1f24a79 4848 u8 rp_cur_flows[0x20];
e281682b
SM		 4849
4850 u8 sum_flows[0x20];
4851
e1f24a79 4852 u8 rp_cnp_ignored_high[0x20];
e281682b 4853
e1f24a79 4854 u8 rp_cnp_ignored_low[0x20];
e281682b 4855
e1f24a79 4856 u8 rp_cnp_handled_high[0x20];
e281682b 4857
e1f24a79 4858 u8 rp_cnp_handled_low[0x20];
e281682b 4859
b4ff3a36 4860 u8 reserved_at_140[0x100];
e281682b
SM		 4861
4862 u8 time_stamp_high[0x20];
4863
4864 u8 time_stamp_low[0x20];
4865
4866 u8 accumulators_period[0x20];
4867
e1f24a79 4868 u8 np_ecn_marked_roce_packets_high[0x20];
e281682b 4869
e1f24a79 4870 u8 np_ecn_marked_roce_packets_low[0x20];
e281682b 4871
e1f24a79 4872 u8 np_cnp_sent_high[0x20];
e281682b 4873
e1f24a79 4874 u8 np_cnp_sent_low[0x20];
e281682b 4875
b4ff3a36 4876 u8 reserved_at_320[0x560];
e281682b
SM		 4877};
4878
4879struct mlx5_ifc_query_cong_statistics_in_bits {
4880 u8 opcode[0x10];
b4ff3a36 4881 u8 reserved_at_10[0x10];
e281682b 4882
b4ff3a36 4883 u8 reserved_at_20[0x10];
e281682b
SM		 4884 u8 op_mod[0x10];
4885
4886 u8 clear[0x1];
b4ff3a36 4887 u8 reserved_at_41[0x1f];
e281682b 4888
b4ff3a36 4889 u8 reserved_at_60[0x20];
e281682b
SM		 4890};
4891
4892struct mlx5_ifc_query_cong_params_out_bits {
4893 u8 status[0x8];
b4ff3a36 4894 u8 reserved_at_8[0x18];
e281682b
SM		 4895
4896 u8 syndrome[0x20];
4897
b4ff3a36 4898 u8 reserved_at_40[0x40];
e281682b
SM		 4899
4900 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4901};
4902
4903struct mlx5_ifc_query_cong_params_in_bits {
4904 u8 opcode[0x10];
b4ff3a36 4905 u8 reserved_at_10[0x10];
e281682b 4906
b4ff3a36 4907 u8 reserved_at_20[0x10];
e281682b
SM		 4908 u8 op_mod[0x10];
4909
b4ff3a36 4910 u8 reserved_at_40[0x1c];
e281682b
SM		 4911 u8 cong_protocol[0x4];
4912
b4ff3a36 4913 u8 reserved_at_60[0x20];
e281682b
SM		 4914};
4915
4916struct mlx5_ifc_query_adapter_out_bits {
4917 u8 status[0x8];
b4ff3a36 4918 u8 reserved_at_8[0x18];
e281682b
SM		 4919
4920 u8 syndrome[0x20];
4921
b4ff3a36 4922 u8 reserved_at_40[0x40];
e281682b
SM		 4923
4924 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4925};
4926
4927struct mlx5_ifc_query_adapter_in_bits {
4928 u8 opcode[0x10];
b4ff3a36 4929 u8 reserved_at_10[0x10];
e281682b 4930
b4ff3a36 4931 u8 reserved_at_20[0x10];
e281682b
SM		 4932 u8 op_mod[0x10];
4933
b4ff3a36 4934 u8 reserved_at_40[0x40];
e281682b
SM		 4935};
4936
4937struct mlx5_ifc_qp_2rst_out_bits {
4938 u8 status[0x8];
b4ff3a36 4939 u8 reserved_at_8[0x18];
e281682b
SM		 4940
4941 u8 syndrome[0x20];
4942
b4ff3a36 4943 u8 reserved_at_40[0x40];
e281682b
SM		 4944};
4945
4946struct mlx5_ifc_qp_2rst_in_bits {
4947 u8 opcode[0x10];
b4ff3a36 4948 u8 reserved_at_10[0x10];
e281682b 4949
b4ff3a36 4950 u8 reserved_at_20[0x10];
e281682b
SM		 4951 u8 op_mod[0x10];
4952
b4ff3a36 4953 u8 reserved_at_40[0x8];
e281682b
SM		 4954 u8 qpn[0x18];
4955
b4ff3a36 4956 u8 reserved_at_60[0x20];
e281682b
SM		 4957};
4958
4959struct mlx5_ifc_qp_2err_out_bits {
4960 u8 status[0x8];
b4ff3a36 4961 u8 reserved_at_8[0x18];
e281682b
SM		 4962
4963 u8 syndrome[0x20];
4964
b4ff3a36 4965 u8 reserved_at_40[0x40];
e281682b
SM		 4966};
4967
4968struct mlx5_ifc_qp_2err_in_bits {
4969 u8 opcode[0x10];
b4ff3a36 4970 u8 reserved_at_10[0x10];
e281682b 4971
b4ff3a36 4972 u8 reserved_at_20[0x10];
e281682b
SM		 4973 u8 op_mod[0x10];
4974
b4ff3a36 4975 u8 reserved_at_40[0x8];
e281682b
SM		 4976 u8 qpn[0x18];
4977
b4ff3a36 4978 u8 reserved_at_60[0x20];
e281682b
SM		 4979};
4980
4981struct mlx5_ifc_page_fault_resume_out_bits {
4982 u8 status[0x8];
b4ff3a36 4983 u8 reserved_at_8[0x18];
e281682b
SM		 4984
4985 u8 syndrome[0x20];
4986
b4ff3a36 4987 u8 reserved_at_40[0x40];
e281682b
SM		 4988};
4989
4990struct mlx5_ifc_page_fault_resume_in_bits {
4991 u8 opcode[0x10];
b4ff3a36 4992 u8 reserved_at_10[0x10];
e281682b 4993
b4ff3a36 4994 u8 reserved_at_20[0x10];
e281682b
SM		 4995 u8 op_mod[0x10];
4996
4997 u8 error[0x1];
b4ff3a36 4998 u8 reserved_at_41[0x4];
223cdc72
AK		 4999 u8 page_fault_type[0x3];
5000 u8 wq_number[0x18];
e281682b 5001
223cdc72
AK		 5002 u8 reserved_at_60[0x8];
5003 u8 token[0x18];
e281682b
SM		 5004};
5005
5006struct mlx5_ifc_nop_out_bits {
5007 u8 status[0x8];
b4ff3a36 5008 u8 reserved_at_8[0x18];
e281682b
SM		 5009
5010 u8 syndrome[0x20];
5011
b4ff3a36 5012 u8 reserved_at_40[0x40];
e281682b
SM		 5013};
5014
5015struct mlx5_ifc_nop_in_bits {
5016 u8 opcode[0x10];
b4ff3a36 5017 u8 reserved_at_10[0x10];
e281682b 5018
b4ff3a36 5019 u8 reserved_at_20[0x10];
e281682b
SM		 5020 u8 op_mod[0x10];
5021
b4ff3a36 5022 u8 reserved_at_40[0x40];
e281682b
SM		 5023};
5024
5025struct mlx5_ifc_modify_vport_state_out_bits {
5026 u8 status[0x8];
b4ff3a36 5027 u8 reserved_at_8[0x18];
e281682b
SM		 5028
5029 u8 syndrome[0x20];
5030
b4ff3a36 5031 u8 reserved_at_40[0x40];
e281682b
SM		 5032};
5033
5034struct mlx5_ifc_modify_vport_state_in_bits {
5035 u8 opcode[0x10];
b4ff3a36 5036 u8 reserved_at_10[0x10];
e281682b 5037
b4ff3a36 5038 u8 reserved_at_20[0x10];
e281682b
SM		 5039 u8 op_mod[0x10];
5040
5041 u8 other_vport[0x1];
b4ff3a36 5042 u8 reserved_at_41[0xf];
e281682b
SM		 5043 u8 vport_number[0x10];
5044
b4ff3a36 5045 u8 reserved_at_60[0x18];
e281682b 5046 u8 admin_state[0x4];
b4ff3a36 5047 u8 reserved_at_7c[0x4];
e281682b
SM		 5048};
5049
5050struct mlx5_ifc_modify_tis_out_bits {
5051 u8 status[0x8];
b4ff3a36 5052 u8 reserved_at_8[0x18];
e281682b
SM		 5053
5054 u8 syndrome[0x20];
5055
b4ff3a36 5056 u8 reserved_at_40[0x40];
e281682b
SM		 5057};
5058
75850d0b 5059struct mlx5_ifc_modify_tis_bitmask_bits {
b4ff3a36 5060 u8 reserved_at_0[0x20];
75850d0b 5061
84df61eb
AH		 5062 u8 reserved_at_20[0x1d];
5063 u8 lag_tx_port_affinity[0x1];
5064 u8 strict_lag_tx_port_affinity[0x1];
75850d0b 5065 u8 prio[0x1];
5066};
5067
e281682b
SM		 5068struct mlx5_ifc_modify_tis_in_bits {
5069 u8 opcode[0x10];
b4ff3a36 5070 u8 reserved_at_10[0x10];
e281682b 5071
b4ff3a36 5072 u8 reserved_at_20[0x10];
e281682b
SM		 5073 u8 op_mod[0x10];
5074
b4ff3a36 5075 u8 reserved_at_40[0x8];
e281682b
SM		 5076 u8 tisn[0x18];
5077
b4ff3a36 5078 u8 reserved_at_60[0x20];
e281682b 5079
75850d0b 5080 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
e281682b 5081
b4ff3a36 5082 u8 reserved_at_c0[0x40];
e281682b
SM		 5083
5084 struct mlx5_ifc_tisc_bits ctx;
5085};
5086
d9eea403 5087struct mlx5_ifc_modify_tir_bitmask_bits {
b4ff3a36 5088 u8 reserved_at_0[0x20];
d9eea403 5089
b4ff3a36 5090 u8 reserved_at_20[0x1b];
66189961 5091 u8 self_lb_en[0x1];
bdfc028d
TT		 5092 u8 reserved_at_3c[0x1];
5093 u8 hash[0x1];
5094 u8 reserved_at_3e[0x1];
d9eea403
AS		 5095 u8 lro[0x1];
5096};
5097
e281682b
SM		 5098struct mlx5_ifc_modify_tir_out_bits {
5099 u8 status[0x8];
b4ff3a36 5100 u8 reserved_at_8[0x18];
e281682b
SM		 5101
5102 u8 syndrome[0x20];
5103
b4ff3a36 5104 u8 reserved_at_40[0x40];
e281682b
SM		 5105};
5106
5107struct mlx5_ifc_modify_tir_in_bits {
5108 u8 opcode[0x10];
b4ff3a36 5109 u8 reserved_at_10[0x10];
e281682b 5110
b4ff3a36 5111 u8 reserved_at_20[0x10];
e281682b
SM		 5112 u8 op_mod[0x10];
5113
b4ff3a36 5114 u8 reserved_at_40[0x8];
e281682b
SM		 5115 u8 tirn[0x18];
5116
b4ff3a36 5117 u8 reserved_at_60[0x20];
e281682b 5118
d9eea403 5119 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
e281682b 5120
b4ff3a36 5121 u8 reserved_at_c0[0x40];
e281682b
SM		 5122
5123 struct mlx5_ifc_tirc_bits ctx;
5124};
5125
5126struct mlx5_ifc_modify_sq_out_bits {
5127 u8 status[0x8];
b4ff3a36 5128 u8 reserved_at_8[0x18];
e281682b
SM		 5129
5130 u8 syndrome[0x20];
5131
b4ff3a36 5132 u8 reserved_at_40[0x40];
e281682b
SM		 5133};
5134
5135struct mlx5_ifc_modify_sq_in_bits {
5136 u8 opcode[0x10];
b4ff3a36 5137 u8 reserved_at_10[0x10];
e281682b 5138
b4ff3a36 5139 u8 reserved_at_20[0x10];
e281682b
SM		 5140 u8 op_mod[0x10];
5141
5142 u8 sq_state[0x4];
b4ff3a36 5143 u8 reserved_at_44[0x4];
e281682b
SM		 5144 u8 sqn[0x18];
5145
b4ff3a36 5146 u8 reserved_at_60[0x20];
e281682b
SM		 5147
5148 u8 modify_bitmask[0x40];
5149
b4ff3a36 5150 u8 reserved_at_c0[0x40];
e281682b
SM		 5151
5152 struct mlx5_ifc_sqc_bits ctx;
5153};
5154
813f8540
MHY		 5155struct mlx5_ifc_modify_scheduling_element_out_bits {
5156 u8 status[0x8];
5157 u8 reserved_at_8[0x18];
5158
5159 u8 syndrome[0x20];
5160
5161 u8 reserved_at_40[0x1c0];
5162};
5163
5164enum {
5165 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
5166 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
5167};
5168
5169struct mlx5_ifc_modify_scheduling_element_in_bits {
5170 u8 opcode[0x10];
5171 u8 reserved_at_10[0x10];
5172
5173 u8 reserved_at_20[0x10];
5174 u8 op_mod[0x10];
5175
5176 u8 scheduling_hierarchy[0x8];
5177 u8 reserved_at_48[0x18];
5178
5179 u8 scheduling_element_id[0x20];
5180
5181 u8 reserved_at_80[0x20];
5182
5183 u8 modify_bitmask[0x20];
5184
5185 u8 reserved_at_c0[0x40];
5186
5187 struct mlx5_ifc_scheduling_context_bits scheduling_context;
5188
5189 u8 reserved_at_300[0x100];
5190};
5191
e281682b
SM		 5192struct mlx5_ifc_modify_rqt_out_bits {
5193 u8 status[0x8];
b4ff3a36 5194 u8 reserved_at_8[0x18];
e281682b
SM		 5195
5196 u8 syndrome[0x20];
5197
b4ff3a36 5198 u8 reserved_at_40[0x40];
e281682b
SM		 5199};
5200
5c50368f 5201struct mlx5_ifc_rqt_bitmask_bits {
b4ff3a36 5202 u8 reserved_at_0[0x20];
5c50368f 5203
b4ff3a36 5204 u8 reserved_at_20[0x1f];
5c50368f
AS		 5205 u8 rqn_list[0x1];
5206};
5207
e281682b
SM		 5208struct mlx5_ifc_modify_rqt_in_bits {
5209 u8 opcode[0x10];
b4ff3a36 5210 u8 reserved_at_10[0x10];
e281682b 5211
b4ff3a36 5212 u8 reserved_at_20[0x10];
e281682b
SM		 5213 u8 op_mod[0x10];
5214
b4ff3a36 5215 u8 reserved_at_40[0x8];
e281682b
SM		 5216 u8 rqtn[0x18];
5217
b4ff3a36 5218 u8 reserved_at_60[0x20];
e281682b 5219
5c50368f 5220 struct mlx5_ifc_rqt_bitmask_bits bitmask;
e281682b 5221
b4ff3a36 5222 u8 reserved_at_c0[0x40];
e281682b
SM		 5223
5224 struct mlx5_ifc_rqtc_bits ctx;
5225};
5226
5227struct mlx5_ifc_modify_rq_out_bits {
5228 u8 status[0x8];
b4ff3a36 5229 u8 reserved_at_8[0x18];
e281682b
SM		 5230
5231 u8 syndrome[0x20];
5232
b4ff3a36 5233 u8 reserved_at_40[0x40];
e281682b
SM		 5234};
5235
83b502a1
AV		 5236enum {
5237 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
102722fc 5238 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
23a6964e 5239 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
83b502a1
AV		 5240};
5241
e281682b
SM		 5242struct mlx5_ifc_modify_rq_in_bits {
5243 u8 opcode[0x10];
b4ff3a36 5244 u8 reserved_at_10[0x10];
e281682b 5245
b4ff3a36 5246 u8 reserved_at_20[0x10];
e281682b
SM		 5247 u8 op_mod[0x10];
5248
5249 u8 rq_state[0x4];
b4ff3a36 5250 u8 reserved_at_44[0x4];
e281682b
SM		 5251 u8 rqn[0x18];
5252
b4ff3a36 5253 u8 reserved_at_60[0x20];
e281682b
SM		 5254
5255 u8 modify_bitmask[0x40];
5256
b4ff3a36 5257 u8 reserved_at_c0[0x40];
e281682b
SM		 5258
5259 struct mlx5_ifc_rqc_bits ctx;
5260};
5261
5262struct mlx5_ifc_modify_rmp_out_bits {
5263 u8 status[0x8];
b4ff3a36 5264 u8 reserved_at_8[0x18];
e281682b
SM		 5265
5266 u8 syndrome[0x20];
5267
b4ff3a36 5268 u8 reserved_at_40[0x40];
e281682b
SM		 5269};
5270
01949d01 5271struct mlx5_ifc_rmp_bitmask_bits {
b4ff3a36 5272 u8 reserved_at_0[0x20];
01949d01 5273
b4ff3a36 5274 u8 reserved_at_20[0x1f];
01949d01
HA		 5275 u8 lwm[0x1];
5276};
5277
e281682b
SM		 5278struct mlx5_ifc_modify_rmp_in_bits {
5279 u8 opcode[0x10];
b4ff3a36 5280 u8 reserved_at_10[0x10];
e281682b 5281
b4ff3a36 5282 u8 reserved_at_20[0x10];
e281682b
SM		 5283 u8 op_mod[0x10];
5284
5285 u8 rmp_state[0x4];
b4ff3a36 5286 u8 reserved_at_44[0x4];
e281682b
SM		 5287 u8 rmpn[0x18];
5288
b4ff3a36 5289 u8 reserved_at_60[0x20];
e281682b 5290
01949d01 5291 struct mlx5_ifc_rmp_bitmask_bits bitmask;
e281682b 5292
b4ff3a36 5293 u8 reserved_at_c0[0x40];
e281682b
SM		 5294
5295 struct mlx5_ifc_rmpc_bits ctx;
5296};
5297
5298struct mlx5_ifc_modify_nic_vport_context_out_bits {
5299 u8 status[0x8];
b4ff3a36 5300 u8 reserved_at_8[0x18];
e281682b
SM		 5301
5302 u8 syndrome[0x20];
5303
b4ff3a36 5304 u8 reserved_at_40[0x40];
e281682b
SM		 5305};
5306
5307struct mlx5_ifc_modify_nic_vport_field_select_bits {
bded747b
HN		 5308 u8 reserved_at_0[0x14];
5309 u8 disable_uc_local_lb[0x1];
5310 u8 disable_mc_local_lb[0x1];
23898c76
NO		 5311 u8 node_guid[0x1];
5312 u8 port_guid[0x1];
9def7121 5313 u8 min_inline[0x1];
d82b7318
SM		 5314 u8 mtu[0x1];
5315 u8 change_event[0x1];
5316 u8 promisc[0x1];
e281682b
SM		 5317 u8 permanent_address[0x1];
5318 u8 addresses_list[0x1];
5319 u8 roce_en[0x1];
b4ff3a36 5320 u8 reserved_at_1f[0x1];
e281682b
SM		 5321};
5322
5323struct mlx5_ifc_modify_nic_vport_context_in_bits {
5324 u8 opcode[0x10];
b4ff3a36 5325 u8 reserved_at_10[0x10];
e281682b 5326
b4ff3a36 5327 u8 reserved_at_20[0x10];
e281682b
SM		 5328 u8 op_mod[0x10];
5329
5330 u8 other_vport[0x1];
b4ff3a36 5331 u8 reserved_at_41[0xf];
e281682b
SM		 5332 u8 vport_number[0x10];
5333
5334 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5335
b4ff3a36 5336 u8 reserved_at_80[0x780];
e281682b
SM		 5337
5338 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5339};
5340
5341struct mlx5_ifc_modify_hca_vport_context_out_bits {
5342 u8 status[0x8];
b4ff3a36 5343 u8 reserved_at_8[0x18];
e281682b
SM		 5344
5345 u8 syndrome[0x20];
5346
b4ff3a36 5347 u8 reserved_at_40[0x40];
e281682b
SM		 5348};
5349
5350struct mlx5_ifc_modify_hca_vport_context_in_bits {
5351 u8 opcode[0x10];
b4ff3a36 5352 u8 reserved_at_10[0x10];
e281682b 5353
b4ff3a36 5354 u8 reserved_at_20[0x10];
e281682b
SM		 5355 u8 op_mod[0x10];
5356
5357 u8 other_vport[0x1];
b4ff3a36 5358 u8 reserved_at_41[0xb];
707c4602 5359 u8 port_num[0x4];
e281682b
SM		 5360 u8 vport_number[0x10];
5361
b4ff3a36 5362 u8 reserved_at_60[0x20];
e281682b
SM		 5363
5364 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5365};
5366
5367struct mlx5_ifc_modify_cq_out_bits {
5368 u8 status[0x8];
b4ff3a36 5369 u8 reserved_at_8[0x18];
e281682b
SM		 5370
5371 u8 syndrome[0x20];
5372
b4ff3a36 5373 u8 reserved_at_40[0x40];
e281682b
SM		 5374};
5375
5376enum {
5377 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
5378 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
5379};
5380
5381struct mlx5_ifc_modify_cq_in_bits {
5382 u8 opcode[0x10];
b4ff3a36 5383 u8 reserved_at_10[0x10];
e281682b 5384
b4ff3a36 5385 u8 reserved_at_20[0x10];
e281682b
SM		 5386 u8 op_mod[0x10];
5387
b4ff3a36 5388 u8 reserved_at_40[0x8];
e281682b
SM		 5389 u8 cqn[0x18];
5390
5391 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5392
5393 struct mlx5_ifc_cqc_bits cq_context;
5394
b4ff3a36 5395 u8 reserved_at_280[0x600];
e281682b
SM		 5396
5397 u8 pas[0][0x40];
5398};
5399
5400struct mlx5_ifc_modify_cong_status_out_bits {
5401 u8 status[0x8];
b4ff3a36 5402 u8 reserved_at_8[0x18];
e281682b
SM		 5403
5404 u8 syndrome[0x20];
5405
b4ff3a36 5406 u8 reserved_at_40[0x40];
e281682b
SM		 5407};
5408
5409struct mlx5_ifc_modify_cong_status_in_bits {
5410 u8 opcode[0x10];
b4ff3a36 5411 u8 reserved_at_10[0x10];
e281682b 5412
b4ff3a36 5413 u8 reserved_at_20[0x10];
e281682b
SM		 5414 u8 op_mod[0x10];
5415
b4ff3a36 5416 u8 reserved_at_40[0x18];
e281682b
SM		 5417 u8 priority[0x4];
5418 u8 cong_protocol[0x4];
5419
5420 u8 enable[0x1];
5421 u8 tag_enable[0x1];
b4ff3a36 5422 u8 reserved_at_62[0x1e];
e281682b
SM		 5423};
5424
5425struct mlx5_ifc_modify_cong_params_out_bits {
5426 u8 status[0x8];
b4ff3a36 5427 u8 reserved_at_8[0x18];
e281682b
SM		 5428
5429 u8 syndrome[0x20];
5430
b4ff3a36 5431 u8 reserved_at_40[0x40];
e281682b
SM		 5432};
5433
5434struct mlx5_ifc_modify_cong_params_in_bits {
5435 u8 opcode[0x10];
b4ff3a36 5436 u8 reserved_at_10[0x10];
e281682b 5437
b4ff3a36 5438 u8 reserved_at_20[0x10];
e281682b
SM		 5439 u8 op_mod[0x10];
5440
b4ff3a36 5441 u8 reserved_at_40[0x1c];
e281682b
SM		 5442 u8 cong_protocol[0x4];
5443
5444 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5445
b4ff3a36 5446 u8 reserved_at_80[0x80];
e281682b
SM		 5447
5448 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5449};
5450
5451struct mlx5_ifc_manage_pages_out_bits {
5452 u8 status[0x8];
b4ff3a36 5453 u8 reserved_at_8[0x18];
e281682b
SM		 5454
5455 u8 syndrome[0x20];
5456
5457 u8 output_num_entries[0x20];
5458
b4ff3a36 5459 u8 reserved_at_60[0x20];
e281682b
SM		 5460
5461 u8 pas[0][0x40];
5462};
5463
5464enum {
5465 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
5466 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
5467 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
5468};
5469
5470struct mlx5_ifc_manage_pages_in_bits {
5471 u8 opcode[0x10];
b4ff3a36 5472 u8 reserved_at_10[0x10];
e281682b 5473
b4ff3a36 5474 u8 reserved_at_20[0x10];
e281682b
SM		 5475 u8 op_mod[0x10];
5476
b4ff3a36 5477 u8 reserved_at_40[0x10];
e281682b
SM		 5478 u8 function_id[0x10];
5479
5480 u8 input_num_entries[0x20];
5481
5482 u8 pas[0][0x40];
5483};
5484
5485struct mlx5_ifc_mad_ifc_out_bits {
5486 u8 status[0x8];
b4ff3a36 5487 u8 reserved_at_8[0x18];
e281682b
SM		 5488
5489 u8 syndrome[0x20];
5490
b4ff3a36 5491 u8 reserved_at_40[0x40];
e281682b
SM		 5492
5493 u8 response_mad_packet[256][0x8];
5494};
5495
5496struct mlx5_ifc_mad_ifc_in_bits {
5497 u8 opcode[0x10];
b4ff3a36 5498 u8 reserved_at_10[0x10];
e281682b 5499
b4ff3a36 5500 u8 reserved_at_20[0x10];
e281682b
SM		 5501 u8 op_mod[0x10];
5502
5503 u8 remote_lid[0x10];
b4ff3a36 5504 u8 reserved_at_50[0x8];
e281682b
SM		 5505 u8 port[0x8];
5506
b4ff3a36 5507 u8 reserved_at_60[0x20];
e281682b
SM		 5508
5509 u8 mad[256][0x8];
5510};
5511
5512struct mlx5_ifc_init_hca_out_bits {
5513 u8 status[0x8];
b4ff3a36 5514 u8 reserved_at_8[0x18];
e281682b
SM		 5515
5516 u8 syndrome[0x20];
5517
b4ff3a36 5518 u8 reserved_at_40[0x40];
e281682b
SM		 5519};
5520
5521struct mlx5_ifc_init_hca_in_bits {
5522 u8 opcode[0x10];
b4ff3a36 5523 u8 reserved_at_10[0x10];
e281682b 5524
b4ff3a36 5525 u8 reserved_at_20[0x10];
e281682b
SM		 5526 u8 op_mod[0x10];
5527
b4ff3a36 5528 u8 reserved_at_40[0x40];
e281682b
SM		 5529};
5530
5531struct mlx5_ifc_init2rtr_qp_out_bits {
5532 u8 status[0x8];
b4ff3a36 5533 u8 reserved_at_8[0x18];
e281682b
SM		 5534
5535 u8 syndrome[0x20];
5536
b4ff3a36 5537 u8 reserved_at_40[0x40];
e281682b
SM		 5538};
5539
5540struct mlx5_ifc_init2rtr_qp_in_bits {
5541 u8 opcode[0x10];
b4ff3a36 5542 u8 reserved_at_10[0x10];
e281682b 5543
b4ff3a36 5544 u8 reserved_at_20[0x10];
e281682b
SM		 5545 u8 op_mod[0x10];
5546
b4ff3a36 5547 u8 reserved_at_40[0x8];
e281682b
SM		 5548 u8 qpn[0x18];
5549
b4ff3a36 5550 u8 reserved_at_60[0x20];
e281682b
SM		 5551
5552 u8 opt_param_mask[0x20];
5553
b4ff3a36 5554 u8 reserved_at_a0[0x20];
e281682b
SM		 5555
5556 struct mlx5_ifc_qpc_bits qpc;
5557
b4ff3a36 5558 u8 reserved_at_800[0x80];
e281682b
SM		 5559};
5560
5561struct mlx5_ifc_init2init_qp_out_bits {
5562 u8 status[0x8];
b4ff3a36 5563 u8 reserved_at_8[0x18];
e281682b
SM		 5564
5565 u8 syndrome[0x20];
5566
b4ff3a36 5567 u8 reserved_at_40[0x40];
e281682b
SM		 5568};
5569
5570struct mlx5_ifc_init2init_qp_in_bits {
5571 u8 opcode[0x10];
b4ff3a36 5572 u8 reserved_at_10[0x10];
e281682b 5573
b4ff3a36 5574 u8 reserved_at_20[0x10];
e281682b
SM		 5575 u8 op_mod[0x10];
5576
b4ff3a36 5577 u8 reserved_at_40[0x8];
e281682b
SM		 5578 u8 qpn[0x18];
5579
b4ff3a36 5580 u8 reserved_at_60[0x20];
e281682b
SM		 5581
5582 u8 opt_param_mask[0x20];
5583
b4ff3a36 5584 u8 reserved_at_a0[0x20];
e281682b
SM		 5585
5586 struct mlx5_ifc_qpc_bits qpc;
5587
b4ff3a36 5588 u8 reserved_at_800[0x80];
e281682b
SM		 5589};
5590
5591struct mlx5_ifc_get_dropped_packet_log_out_bits {
5592 u8 status[0x8];
b4ff3a36 5593 u8 reserved_at_8[0x18];
e281682b
SM		 5594
5595 u8 syndrome[0x20];
5596
b4ff3a36 5597 u8 reserved_at_40[0x40];
e281682b
SM		 5598
5599 u8 packet_headers_log[128][0x8];
5600
5601 u8 packet_syndrome[64][0x8];
5602};
5603
5604struct mlx5_ifc_get_dropped_packet_log_in_bits {
5605 u8 opcode[0x10];
b4ff3a36 5606 u8 reserved_at_10[0x10];
e281682b 5607
b4ff3a36 5608 u8 reserved_at_20[0x10];
e281682b
SM		 5609 u8 op_mod[0x10];
5610
b4ff3a36 5611 u8 reserved_at_40[0x40];
e281682b
SM		 5612};
5613
5614struct mlx5_ifc_gen_eqe_in_bits {
5615 u8 opcode[0x10];
b4ff3a36 5616 u8 reserved_at_10[0x10];
e281682b 5617
b4ff3a36 5618 u8 reserved_at_20[0x10];
e281682b
SM		 5619 u8 op_mod[0x10];
5620
b4ff3a36 5621 u8 reserved_at_40[0x18];
e281682b
SM		 5622 u8 eq_number[0x8];
5623
b4ff3a36 5624 u8 reserved_at_60[0x20];
e281682b
SM		 5625
5626 u8 eqe[64][0x8];
5627};
5628
5629struct mlx5_ifc_gen_eq_out_bits {
5630 u8 status[0x8];
b4ff3a36 5631 u8 reserved_at_8[0x18];
e281682b
SM		 5632
5633 u8 syndrome[0x20];
5634
b4ff3a36 5635 u8 reserved_at_40[0x40];
e281682b
SM		 5636};
5637
5638struct mlx5_ifc_enable_hca_out_bits {
5639 u8 status[0x8];
b4ff3a36 5640 u8 reserved_at_8[0x18];
e281682b
SM		 5641
5642 u8 syndrome[0x20];
5643
b4ff3a36 5644 u8 reserved_at_40[0x20];
e281682b
SM		 5645};
5646
5647struct mlx5_ifc_enable_hca_in_bits {
5648 u8 opcode[0x10];
b4ff3a36 5649 u8 reserved_at_10[0x10];
e281682b 5650
b4ff3a36 5651 u8 reserved_at_20[0x10];
e281682b
SM		 5652 u8 op_mod[0x10];
5653
b4ff3a36 5654 u8 reserved_at_40[0x10];
e281682b
SM		 5655 u8 function_id[0x10];
5656
b4ff3a36 5657 u8 reserved_at_60[0x20];
e281682b
SM		 5658};
5659
5660struct mlx5_ifc_drain_dct_out_bits {
5661 u8 status[0x8];
b4ff3a36 5662 u8 reserved_at_8[0x18];
e281682b
SM		 5663
5664 u8 syndrome[0x20];
5665
b4ff3a36 5666 u8 reserved_at_40[0x40];
e281682b
SM		 5667};
5668
5669struct mlx5_ifc_drain_dct_in_bits {
5670 u8 opcode[0x10];
b4ff3a36 5671 u8 reserved_at_10[0x10];
e281682b 5672
b4ff3a36 5673 u8 reserved_at_20[0x10];
e281682b
SM		 5674 u8 op_mod[0x10];
5675
b4ff3a36 5676 u8 reserved_at_40[0x8];
e281682b
SM		 5677 u8 dctn[0x18];
5678
b4ff3a36 5679 u8 reserved_at_60[0x20];
e281682b
SM		 5680};
5681
5682struct mlx5_ifc_disable_hca_out_bits {
5683 u8 status[0x8];
b4ff3a36 5684 u8 reserved_at_8[0x18];
e281682b
SM		 5685
5686 u8 syndrome[0x20];
5687
b4ff3a36 5688 u8 reserved_at_40[0x20];
e281682b
SM		 5689};
5690
5691struct mlx5_ifc_disable_hca_in_bits {
5692 u8 opcode[0x10];
b4ff3a36 5693 u8 reserved_at_10[0x10];
e281682b 5694
b4ff3a36 5695 u8 reserved_at_20[0x10];
e281682b
SM		 5696 u8 op_mod[0x10];
5697
b4ff3a36 5698 u8 reserved_at_40[0x10];
e281682b
SM		 5699 u8 function_id[0x10];
5700
b4ff3a36 5701 u8 reserved_at_60[0x20];
e281682b
SM		 5702};
5703
5704struct mlx5_ifc_detach_from_mcg_out_bits {
5705 u8 status[0x8];
b4ff3a36 5706 u8 reserved_at_8[0x18];
e281682b
SM		 5707
5708 u8 syndrome[0x20];
5709
b4ff3a36 5710 u8 reserved_at_40[0x40];
e281682b
SM		 5711};
5712
5713struct mlx5_ifc_detach_from_mcg_in_bits {
5714 u8 opcode[0x10];
b4ff3a36 5715 u8 reserved_at_10[0x10];
e281682b 5716
b4ff3a36 5717 u8 reserved_at_20[0x10];
e281682b
SM		 5718 u8 op_mod[0x10];
5719
b4ff3a36 5720 u8 reserved_at_40[0x8];
e281682b
SM		 5721 u8 qpn[0x18];
5722
b4ff3a36 5723 u8 reserved_at_60[0x20];
e281682b
SM		 5724
5725 u8 multicast_gid[16][0x8];
5726};
5727
7486216b
SM		 5728struct mlx5_ifc_destroy_xrq_out_bits {
5729 u8 status[0x8];
5730 u8 reserved_at_8[0x18];
5731
5732 u8 syndrome[0x20];
5733
5734 u8 reserved_at_40[0x40];
5735};
5736
5737struct mlx5_ifc_destroy_xrq_in_bits {
5738 u8 opcode[0x10];
5739 u8 reserved_at_10[0x10];
5740
5741 u8 reserved_at_20[0x10];
5742 u8 op_mod[0x10];
5743
5744 u8 reserved_at_40[0x8];
5745 u8 xrqn[0x18];
5746
5747 u8 reserved_at_60[0x20];
5748};
5749
e281682b
SM		 5750struct mlx5_ifc_destroy_xrc_srq_out_bits {
5751 u8 status[0x8];
b4ff3a36 5752 u8 reserved_at_8[0x18];
e281682b
SM		 5753
5754 u8 syndrome[0x20];
5755
b4ff3a36 5756 u8 reserved_at_40[0x40];
e281682b
SM		 5757};
5758
5759struct mlx5_ifc_destroy_xrc_srq_in_bits {
5760 u8 opcode[0x10];
b4ff3a36 5761 u8 reserved_at_10[0x10];
e281682b 5762
b4ff3a36 5763 u8 reserved_at_20[0x10];
e281682b
SM		 5764 u8 op_mod[0x10];
5765
b4ff3a36 5766 u8 reserved_at_40[0x8];
e281682b
SM		 5767 u8 xrc_srqn[0x18];
5768
b4ff3a36 5769 u8 reserved_at_60[0x20];
e281682b
SM		 5770};
5771
5772struct mlx5_ifc_destroy_tis_out_bits {
5773 u8 status[0x8];
b4ff3a36 5774 u8 reserved_at_8[0x18];
e281682b
SM		 5775
5776 u8 syndrome[0x20];
5777
b4ff3a36 5778 u8 reserved_at_40[0x40];
e281682b
SM		 5779};
5780
5781struct mlx5_ifc_destroy_tis_in_bits {
5782 u8 opcode[0x10];
b4ff3a36 5783 u8 reserved_at_10[0x10];
e281682b 5784
b4ff3a36 5785 u8 reserved_at_20[0x10];
e281682b
SM		 5786 u8 op_mod[0x10];
5787
b4ff3a36 5788 u8 reserved_at_40[0x8];
e281682b
SM		 5789 u8 tisn[0x18];
5790
b4ff3a36 5791 u8 reserved_at_60[0x20];
e281682b
SM		 5792};
5793
5794struct mlx5_ifc_destroy_tir_out_bits {
5795 u8 status[0x8];
b4ff3a36 5796 u8 reserved_at_8[0x18];
e281682b
SM		 5797
5798 u8 syndrome[0x20];
5799
b4ff3a36 5800 u8 reserved_at_40[0x40];
e281682b
SM		 5801};
5802
5803struct mlx5_ifc_destroy_tir_in_bits {
5804 u8 opcode[0x10];
b4ff3a36 5805 u8 reserved_at_10[0x10];
e281682b 5806
b4ff3a36 5807 u8 reserved_at_20[0x10];
e281682b
SM		 5808 u8 op_mod[0x10];
5809
b4ff3a36 5810 u8 reserved_at_40[0x8];
e281682b
SM		 5811 u8 tirn[0x18];
5812
b4ff3a36 5813 u8 reserved_at_60[0x20];
e281682b
SM		 5814};
5815
5816struct mlx5_ifc_destroy_srq_out_bits {
5817 u8 status[0x8];
b4ff3a36 5818 u8 reserved_at_8[0x18];
e281682b
SM		 5819
5820 u8 syndrome[0x20];
5821
b4ff3a36 5822 u8 reserved_at_40[0x40];
e281682b
SM		 5823};
5824
5825struct mlx5_ifc_destroy_srq_in_bits {
5826 u8 opcode[0x10];
b4ff3a36 5827 u8 reserved_at_10[0x10];
e281682b 5828
b4ff3a36 5829 u8 reserved_at_20[0x10];
e281682b
SM		 5830 u8 op_mod[0x10];
5831
b4ff3a36 5832 u8 reserved_at_40[0x8];
e281682b
SM		 5833 u8 srqn[0x18];
5834
b4ff3a36 5835 u8 reserved_at_60[0x20];
e281682b
SM		 5836};
5837
5838struct mlx5_ifc_destroy_sq_out_bits {
5839 u8 status[0x8];
b4ff3a36 5840 u8 reserved_at_8[0x18];
e281682b
SM		 5841
5842 u8 syndrome[0x20];
5843
b4ff3a36 5844 u8 reserved_at_40[0x40];
e281682b
SM		 5845};
5846
5847struct mlx5_ifc_destroy_sq_in_bits {
5848 u8 opcode[0x10];
b4ff3a36 5849 u8 reserved_at_10[0x10];
e281682b 5850
b4ff3a36 5851 u8 reserved_at_20[0x10];
e281682b
SM		 5852 u8 op_mod[0x10];
5853
b4ff3a36 5854 u8 reserved_at_40[0x8];
e281682b
SM		 5855 u8 sqn[0x18];
5856
b4ff3a36 5857 u8 reserved_at_60[0x20];
e281682b
SM		 5858};
5859
813f8540
MHY		 5860struct mlx5_ifc_destroy_scheduling_element_out_bits {
5861 u8 status[0x8];
5862 u8 reserved_at_8[0x18];
5863
5864 u8 syndrome[0x20];
5865
5866 u8 reserved_at_40[0x1c0];
5867};
5868
5869struct mlx5_ifc_destroy_scheduling_element_in_bits {
5870 u8 opcode[0x10];
5871 u8 reserved_at_10[0x10];
5872
5873 u8 reserved_at_20[0x10];
5874 u8 op_mod[0x10];
5875
5876 u8 scheduling_hierarchy[0x8];
5877 u8 reserved_at_48[0x18];
5878
5879 u8 scheduling_element_id[0x20];
5880
5881 u8 reserved_at_80[0x180];
5882};
5883
e281682b
SM		 5884struct mlx5_ifc_destroy_rqt_out_bits {
5885 u8 status[0x8];
b4ff3a36 5886 u8 reserved_at_8[0x18];
e281682b
SM		 5887
5888 u8 syndrome[0x20];
5889
b4ff3a36 5890 u8 reserved_at_40[0x40];
e281682b
SM		 5891};
5892
5893struct mlx5_ifc_destroy_rqt_in_bits {
5894 u8 opcode[0x10];
b4ff3a36 5895 u8 reserved_at_10[0x10];
e281682b 5896
b4ff3a36 5897 u8 reserved_at_20[0x10];
e281682b
SM		 5898 u8 op_mod[0x10];
5899
b4ff3a36 5900 u8 reserved_at_40[0x8];
e281682b
SM		 5901 u8 rqtn[0x18];
5902
b4ff3a36 5903 u8 reserved_at_60[0x20];
e281682b
SM		 5904};
5905
5906struct mlx5_ifc_destroy_rq_out_bits {
5907 u8 status[0x8];
b4ff3a36 5908 u8 reserved_at_8[0x18];
e281682b
SM		 5909
5910 u8 syndrome[0x20];
5911
b4ff3a36 5912 u8 reserved_at_40[0x40];
e281682b
SM		 5913};
5914
5915struct mlx5_ifc_destroy_rq_in_bits {
5916 u8 opcode[0x10];
b4ff3a36 5917 u8 reserved_at_10[0x10];
e281682b 5918
b4ff3a36 5919 u8 reserved_at_20[0x10];
e281682b
SM		 5920 u8 op_mod[0x10];
5921
b4ff3a36 5922 u8 reserved_at_40[0x8];
e281682b
SM		 5923 u8 rqn[0x18];
5924
b4ff3a36 5925 u8 reserved_at_60[0x20];
e281682b
SM		 5926};
5927
c1e0bfc1
MG		 5928struct mlx5_ifc_set_delay_drop_params_in_bits {
5929 u8 opcode[0x10];
5930 u8 reserved_at_10[0x10];
5931
5932 u8 reserved_at_20[0x10];
5933 u8 op_mod[0x10];
5934
5935 u8 reserved_at_40[0x20];
5936
5937 u8 reserved_at_60[0x10];
5938 u8 delay_drop_timeout[0x10];
5939};
5940
5941struct mlx5_ifc_set_delay_drop_params_out_bits {
5942 u8 status[0x8];
5943 u8 reserved_at_8[0x18];
5944
5945 u8 syndrome[0x20];
5946
5947 u8 reserved_at_40[0x40];
5948};
5949
e281682b
SM		 5950struct mlx5_ifc_destroy_rmp_out_bits {
5951 u8 status[0x8];
b4ff3a36 5952 u8 reserved_at_8[0x18];
e281682b
SM		 5953
5954 u8 syndrome[0x20];
5955
b4ff3a36 5956 u8 reserved_at_40[0x40];
e281682b
SM		 5957};
5958
5959struct mlx5_ifc_destroy_rmp_in_bits {
5960 u8 opcode[0x10];
b4ff3a36 5961 u8 reserved_at_10[0x10];
e281682b 5962
b4ff3a36 5963 u8 reserved_at_20[0x10];
e281682b
SM		 5964 u8 op_mod[0x10];
5965
b4ff3a36 5966 u8 reserved_at_40[0x8];
e281682b
SM		 5967 u8 rmpn[0x18];
5968
b4ff3a36 5969 u8 reserved_at_60[0x20];
e281682b
SM		 5970};
5971
5972struct mlx5_ifc_destroy_qp_out_bits {
5973 u8 status[0x8];
b4ff3a36 5974 u8 reserved_at_8[0x18];
e281682b
SM		 5975
5976 u8 syndrome[0x20];
5977
b4ff3a36 5978 u8 reserved_at_40[0x40];
e281682b
SM		 5979};
5980
5981struct mlx5_ifc_destroy_qp_in_bits {
5982 u8 opcode[0x10];
b4ff3a36 5983 u8 reserved_at_10[0x10];
e281682b 5984
b4ff3a36 5985 u8 reserved_at_20[0x10];
e281682b
SM		 5986 u8 op_mod[0x10];
5987
b4ff3a36 5988 u8 reserved_at_40[0x8];
e281682b
SM		 5989 u8 qpn[0x18];
5990
b4ff3a36 5991 u8 reserved_at_60[0x20];
e281682b
SM		 5992};
5993
5994struct mlx5_ifc_destroy_psv_out_bits {
5995 u8 status[0x8];
b4ff3a36 5996 u8 reserved_at_8[0x18];
e281682b
SM		 5997
5998 u8 syndrome[0x20];
5999
b4ff3a36 6000 u8 reserved_at_40[0x40];
e281682b
SM		 6001};
6002
6003struct mlx5_ifc_destroy_psv_in_bits {
6004 u8 opcode[0x10];
b4ff3a36 6005 u8 reserved_at_10[0x10];
e281682b 6006
b4ff3a36 6007 u8 reserved_at_20[0x10];
e281682b
SM		 6008 u8 op_mod[0x10];
6009
b4ff3a36 6010 u8 reserved_at_40[0x8];
e281682b
SM		 6011 u8 psvn[0x18];
6012
b4ff3a36 6013 u8 reserved_at_60[0x20];
e281682b
SM		 6014};
6015
6016struct mlx5_ifc_destroy_mkey_out_bits {
6017 u8 status[0x8];
b4ff3a36 6018 u8 reserved_at_8[0x18];
e281682b
SM		 6019
6020 u8 syndrome[0x20];
6021
b4ff3a36 6022 u8 reserved_at_40[0x40];
e281682b
SM		 6023};
6024
6025struct mlx5_ifc_destroy_mkey_in_bits {
6026 u8 opcode[0x10];
b4ff3a36 6027 u8 reserved_at_10[0x10];
e281682b 6028
b4ff3a36 6029 u8 reserved_at_20[0x10];
e281682b
SM		 6030 u8 op_mod[0x10];
6031
b4ff3a36 6032 u8 reserved_at_40[0x8];
e281682b
SM		 6033 u8 mkey_index[0x18];
6034
b4ff3a36 6035 u8 reserved_at_60[0x20];
e281682b
SM		 6036};
6037
6038struct mlx5_ifc_destroy_flow_table_out_bits {
6039 u8 status[0x8];
b4ff3a36 6040 u8 reserved_at_8[0x18];
e281682b
SM		 6041
6042 u8 syndrome[0x20];
6043
b4ff3a36 6044 u8 reserved_at_40[0x40];
e281682b
SM		 6045};
6046
6047struct mlx5_ifc_destroy_flow_table_in_bits {
6048 u8 opcode[0x10];
b4ff3a36 6049 u8 reserved_at_10[0x10];
e281682b 6050
b4ff3a36 6051 u8 reserved_at_20[0x10];
e281682b
SM		 6052 u8 op_mod[0x10];
6053
7d5e1423
SM		 6054 u8 other_vport[0x1];
6055 u8 reserved_at_41[0xf];
6056 u8 vport_number[0x10];
6057
6058 u8 reserved_at_60[0x20];
e281682b
SM		 6059
6060 u8 table_type[0x8];
b4ff3a36 6061 u8 reserved_at_88[0x18];
e281682b 6062
b4ff3a36 6063 u8 reserved_at_a0[0x8];
e281682b
SM		 6064 u8 table_id[0x18];
6065
b4ff3a36 6066 u8 reserved_at_c0[0x140];
e281682b
SM		 6067};
6068
6069struct mlx5_ifc_destroy_flow_group_out_bits {
6070 u8 status[0x8];
b4ff3a36 6071 u8 reserved_at_8[0x18];
e281682b
SM		 6072
6073 u8 syndrome[0x20];
6074
b4ff3a36 6075 u8 reserved_at_40[0x40];
e281682b
SM		 6076};
6077
6078struct mlx5_ifc_destroy_flow_group_in_bits {
6079 u8 opcode[0x10];
b4ff3a36 6080 u8 reserved_at_10[0x10];
e281682b 6081
b4ff3a36 6082 u8 reserved_at_20[0x10];
e281682b
SM		 6083 u8 op_mod[0x10];
6084
7d5e1423
SM		 6085 u8 other_vport[0x1];
6086 u8 reserved_at_41[0xf];
6087 u8 vport_number[0x10];
6088
6089 u8 reserved_at_60[0x20];
e281682b
SM		 6090
6091 u8 table_type[0x8];
b4ff3a36 6092 u8 reserved_at_88[0x18];
e281682b 6093
b4ff3a36 6094 u8 reserved_at_a0[0x8];
e281682b
SM		 6095 u8 table_id[0x18];
6096
6097 u8 group_id[0x20];
6098
b4ff3a36 6099 u8 reserved_at_e0[0x120];
e281682b
SM		 6100};
6101
6102struct mlx5_ifc_destroy_eq_out_bits {
6103 u8 status[0x8];
b4ff3a36 6104 u8 reserved_at_8[0x18];
e281682b
SM		 6105
6106 u8 syndrome[0x20];
6107
b4ff3a36 6108 u8 reserved_at_40[0x40];
e281682b
SM		 6109};
6110
6111struct mlx5_ifc_destroy_eq_in_bits {
6112 u8 opcode[0x10];
b4ff3a36 6113 u8 reserved_at_10[0x10];
e281682b 6114
b4ff3a36 6115 u8 reserved_at_20[0x10];
e281682b
SM		 6116 u8 op_mod[0x10];
6117
b4ff3a36 6118 u8 reserved_at_40[0x18];
e281682b
SM		 6119 u8 eq_number[0x8];
6120
b4ff3a36 6121 u8 reserved_at_60[0x20];
e281682b
SM		 6122};
6123
6124struct mlx5_ifc_destroy_dct_out_bits {
6125 u8 status[0x8];
b4ff3a36 6126 u8 reserved_at_8[0x18];
e281682b
SM		 6127
6128 u8 syndrome[0x20];
6129
b4ff3a36 6130 u8 reserved_at_40[0x40];
e281682b
SM		 6131};
6132
6133struct mlx5_ifc_destroy_dct_in_bits {
6134 u8 opcode[0x10];
b4ff3a36 6135 u8 reserved_at_10[0x10];
e281682b 6136
b4ff3a36 6137 u8 reserved_at_20[0x10];
e281682b
SM		 6138 u8 op_mod[0x10];
6139
b4ff3a36 6140 u8 reserved_at_40[0x8];
e281682b
SM		 6141 u8 dctn[0x18];
6142
b4ff3a36 6143 u8 reserved_at_60[0x20];
e281682b
SM		 6144};
6145
6146struct mlx5_ifc_destroy_cq_out_bits {
6147 u8 status[0x8];
b4ff3a36 6148 u8 reserved_at_8[0x18];
e281682b
SM		 6149
6150 u8 syndrome[0x20];
6151
b4ff3a36 6152 u8 reserved_at_40[0x40];
e281682b
SM		 6153};
6154
6155struct mlx5_ifc_destroy_cq_in_bits {
6156 u8 opcode[0x10];
b4ff3a36 6157 u8 reserved_at_10[0x10];
e281682b 6158
b4ff3a36 6159 u8 reserved_at_20[0x10];
e281682b
SM		 6160 u8 op_mod[0x10];
6161
b4ff3a36 6162 u8 reserved_at_40[0x8];
e281682b
SM		 6163 u8 cqn[0x18];
6164
b4ff3a36 6165 u8 reserved_at_60[0x20];
e281682b
SM		 6166};
6167
6168struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6169 u8 status[0x8];
b4ff3a36 6170 u8 reserved_at_8[0x18];
e281682b
SM		 6171
6172 u8 syndrome[0x20];
6173
b4ff3a36 6174 u8 reserved_at_40[0x40];
e281682b
SM		 6175};
6176
6177struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6178 u8 opcode[0x10];
b4ff3a36 6179 u8 reserved_at_10[0x10];
e281682b 6180
b4ff3a36 6181 u8 reserved_at_20[0x10];
e281682b
SM		 6182 u8 op_mod[0x10];
6183
b4ff3a36 6184 u8 reserved_at_40[0x20];
e281682b 6185
b4ff3a36 6186 u8 reserved_at_60[0x10];
e281682b
SM		 6187 u8 vxlan_udp_port[0x10];
6188};
6189
6190struct mlx5_ifc_delete_l2_table_entry_out_bits {
6191 u8 status[0x8];
b4ff3a36 6192 u8 reserved_at_8[0x18];
e281682b
SM		 6193
6194 u8 syndrome[0x20];
6195
b4ff3a36 6196 u8 reserved_at_40[0x40];
e281682b
SM		 6197};
6198
6199struct mlx5_ifc_delete_l2_table_entry_in_bits {
6200 u8 opcode[0x10];
b4ff3a36 6201 u8 reserved_at_10[0x10];
e281682b 6202
b4ff3a36 6203 u8 reserved_at_20[0x10];
e281682b
SM		 6204 u8 op_mod[0x10];
6205
b4ff3a36 6206 u8 reserved_at_40[0x60];
e281682b 6207
b4ff3a36 6208 u8 reserved_at_a0[0x8];
e281682b
SM		 6209 u8 table_index[0x18];
6210
b4ff3a36 6211 u8 reserved_at_c0[0x140];
e281682b
SM		 6212};
6213
6214struct mlx5_ifc_delete_fte_out_bits {
6215 u8 status[0x8];
b4ff3a36 6216 u8 reserved_at_8[0x18];
e281682b
SM		 6217
6218 u8 syndrome[0x20];
6219
b4ff3a36 6220 u8 reserved_at_40[0x40];
e281682b
SM		 6221};
6222
6223struct mlx5_ifc_delete_fte_in_bits {
6224 u8 opcode[0x10];
b4ff3a36 6225 u8 reserved_at_10[0x10];
e281682b 6226
b4ff3a36 6227 u8 reserved_at_20[0x10];
e281682b
SM		 6228 u8 op_mod[0x10];
6229
7d5e1423
SM		 6230 u8 other_vport[0x1];
6231 u8 reserved_at_41[0xf];
6232 u8 vport_number[0x10];
6233
6234 u8 reserved_at_60[0x20];
e281682b
SM		 6235
6236 u8 table_type[0x8];
b4ff3a36 6237 u8 reserved_at_88[0x18];
e281682b 6238
b4ff3a36 6239 u8 reserved_at_a0[0x8];
e281682b
SM		 6240 u8 table_id[0x18];
6241
b4ff3a36 6242 u8 reserved_at_c0[0x40];
e281682b
SM		 6243
6244 u8 flow_index[0x20];
6245
b4ff3a36 6246 u8 reserved_at_120[0xe0];
e281682b
SM		 6247};
6248
6249struct mlx5_ifc_dealloc_xrcd_out_bits {
6250 u8 status[0x8];
b4ff3a36 6251 u8 reserved_at_8[0x18];
e281682b
SM		 6252
6253 u8 syndrome[0x20];
6254
b4ff3a36 6255 u8 reserved_at_40[0x40];
e281682b
SM		 6256};
6257
6258struct mlx5_ifc_dealloc_xrcd_in_bits {
6259 u8 opcode[0x10];
b4ff3a36 6260 u8 reserved_at_10[0x10];
e281682b 6261
b4ff3a36 6262 u8 reserved_at_20[0x10];
e281682b
SM		 6263 u8 op_mod[0x10];
6264
b4ff3a36 6265 u8 reserved_at_40[0x8];
e281682b
SM		 6266 u8 xrcd[0x18];
6267
b4ff3a36 6268 u8 reserved_at_60[0x20];
e281682b
SM		 6269};
6270
6271struct mlx5_ifc_dealloc_uar_out_bits {
6272 u8 status[0x8];
b4ff3a36 6273 u8 reserved_at_8[0x18];
e281682b
SM		 6274
6275 u8 syndrome[0x20];
6276
b4ff3a36 6277 u8 reserved_at_40[0x40];
e281682b
SM		 6278};
6279
6280struct mlx5_ifc_dealloc_uar_in_bits {
6281 u8 opcode[0x10];
b4ff3a36 6282 u8 reserved_at_10[0x10];
e281682b 6283
b4ff3a36 6284 u8 reserved_at_20[0x10];
e281682b
SM		 6285 u8 op_mod[0x10];
6286
b4ff3a36 6287 u8 reserved_at_40[0x8];
e281682b
SM		 6288 u8 uar[0x18];
6289
b4ff3a36 6290 u8 reserved_at_60[0x20];
e281682b
SM		 6291};
6292
6293struct mlx5_ifc_dealloc_transport_domain_out_bits {
6294 u8 status[0x8];
b4ff3a36 6295 u8 reserved_at_8[0x18];
e281682b
SM		 6296
6297 u8 syndrome[0x20];
6298
b4ff3a36 6299 u8 reserved_at_40[0x40];
e281682b
SM		 6300};
6301
6302struct mlx5_ifc_dealloc_transport_domain_in_bits {
6303 u8 opcode[0x10];
b4ff3a36 6304 u8 reserved_at_10[0x10];
e281682b 6305
b4ff3a36 6306 u8 reserved_at_20[0x10];
e281682b
SM		 6307 u8 op_mod[0x10];
6308
b4ff3a36 6309 u8 reserved_at_40[0x8];
e281682b
SM		 6310 u8 transport_domain[0x18];
6311
b4ff3a36 6312 u8 reserved_at_60[0x20];
e281682b
SM		 6313};
6314
6315struct mlx5_ifc_dealloc_q_counter_out_bits {
6316 u8 status[0x8];
b4ff3a36 6317 u8 reserved_at_8[0x18];
e281682b
SM		 6318
6319 u8 syndrome[0x20];
6320
b4ff3a36 6321 u8 reserved_at_40[0x40];
e281682b
SM		 6322};
6323
6324struct mlx5_ifc_dealloc_q_counter_in_bits {
6325 u8 opcode[0x10];
b4ff3a36 6326 u8 reserved_at_10[0x10];
e281682b 6327
b4ff3a36 6328 u8 reserved_at_20[0x10];
e281682b
SM		 6329 u8 op_mod[0x10];
6330
b4ff3a36 6331 u8 reserved_at_40[0x18];
e281682b
SM		 6332 u8 counter_set_id[0x8];
6333
b4ff3a36 6334 u8 reserved_at_60[0x20];
e281682b
SM		 6335};
6336
6337struct mlx5_ifc_dealloc_pd_out_bits {
6338 u8 status[0x8];
b4ff3a36 6339 u8 reserved_at_8[0x18];
e281682b
SM		 6340
6341 u8 syndrome[0x20];
6342
b4ff3a36 6343 u8 reserved_at_40[0x40];
e281682b
SM		 6344};
6345
6346struct mlx5_ifc_dealloc_pd_in_bits {
6347 u8 opcode[0x10];
b4ff3a36 6348 u8 reserved_at_10[0x10];
e281682b 6349
b4ff3a36 6350 u8 reserved_at_20[0x10];
e281682b
SM		 6351 u8 op_mod[0x10];
6352
b4ff3a36 6353 u8 reserved_at_40[0x8];
e281682b
SM		 6354 u8 pd[0x18];
6355
b4ff3a36 6356 u8 reserved_at_60[0x20];
e281682b
SM		 6357};
6358
9dc0b289
AV		 6359struct mlx5_ifc_dealloc_flow_counter_out_bits {
6360 u8 status[0x8];
6361 u8 reserved_at_8[0x18];
6362
6363 u8 syndrome[0x20];
6364
6365 u8 reserved_at_40[0x40];
6366};
6367
6368struct mlx5_ifc_dealloc_flow_counter_in_bits {
6369 u8 opcode[0x10];
6370 u8 reserved_at_10[0x10];
6371
6372 u8 reserved_at_20[0x10];
6373 u8 op_mod[0x10];
6374
a8ffcc74 6375 u8 flow_counter_id[0x20];
9dc0b289
AV		 6376
6377 u8 reserved_at_60[0x20];
6378};
6379
7486216b
SM		 6380struct mlx5_ifc_create_xrq_out_bits {
6381 u8 status[0x8];
6382 u8 reserved_at_8[0x18];
6383
6384 u8 syndrome[0x20];
6385
6386 u8 reserved_at_40[0x8];
6387 u8 xrqn[0x18];
6388
6389 u8 reserved_at_60[0x20];
6390};
6391
6392struct mlx5_ifc_create_xrq_in_bits {
6393 u8 opcode[0x10];
6394 u8 reserved_at_10[0x10];
6395
6396 u8 reserved_at_20[0x10];
6397 u8 op_mod[0x10];
6398
6399 u8 reserved_at_40[0x40];
6400
6401 struct mlx5_ifc_xrqc_bits xrq_context;
6402};
6403
e281682b
SM		 6404struct mlx5_ifc_create_xrc_srq_out_bits {
6405 u8 status[0x8];
b4ff3a36 6406 u8 reserved_at_8[0x18];
e281682b
SM		 6407
6408 u8 syndrome[0x20];
6409
b4ff3a36 6410 u8 reserved_at_40[0x8];
e281682b
SM		 6411 u8 xrc_srqn[0x18];
6412
b4ff3a36 6413 u8 reserved_at_60[0x20];
e281682b
SM		 6414};
6415
6416struct mlx5_ifc_create_xrc_srq_in_bits {
6417 u8 opcode[0x10];
b4ff3a36 6418 u8 reserved_at_10[0x10];
e281682b 6419
b4ff3a36 6420 u8 reserved_at_20[0x10];
e281682b
SM		 6421 u8 op_mod[0x10];
6422
b4ff3a36 6423 u8 reserved_at_40[0x40];
e281682b
SM		 6424
6425 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6426
b4ff3a36 6427 u8 reserved_at_280[0x600];
e281682b
SM		 6428
6429 u8 pas[0][0x40];
6430};
6431
6432struct mlx5_ifc_create_tis_out_bits {
6433 u8 status[0x8];
b4ff3a36 6434 u8 reserved_at_8[0x18];
e281682b
SM		 6435
6436 u8 syndrome[0x20];
6437
b4ff3a36 6438 u8 reserved_at_40[0x8];
e281682b
SM		 6439 u8 tisn[0x18];
6440
b4ff3a36 6441 u8 reserved_at_60[0x20];
e281682b
SM		 6442};
6443
6444struct mlx5_ifc_create_tis_in_bits {
6445 u8 opcode[0x10];
b4ff3a36 6446 u8 reserved_at_10[0x10];
e281682b 6447
b4ff3a36 6448 u8 reserved_at_20[0x10];
e281682b
SM		 6449 u8 op_mod[0x10];
6450
b4ff3a36 6451 u8 reserved_at_40[0xc0];
e281682b
SM		 6452
6453 struct mlx5_ifc_tisc_bits ctx;
6454};
6455
6456struct mlx5_ifc_create_tir_out_bits {
6457 u8 status[0x8];
b4ff3a36 6458 u8 reserved_at_8[0x18];
e281682b
SM		 6459
6460 u8 syndrome[0x20];
6461
b4ff3a36 6462 u8 reserved_at_40[0x8];
e281682b
SM		 6463 u8 tirn[0x18];
6464
b4ff3a36 6465 u8 reserved_at_60[0x20];
e281682b
SM		 6466};
6467
6468struct mlx5_ifc_create_tir_in_bits {
6469 u8 opcode[0x10];
b4ff3a36 6470 u8 reserved_at_10[0x10];
e281682b 6471
b4ff3a36 6472 u8 reserved_at_20[0x10];
e281682b
SM		 6473 u8 op_mod[0x10];
6474
b4ff3a36 6475 u8 reserved_at_40[0xc0];
e281682b
SM		 6476
6477 struct mlx5_ifc_tirc_bits ctx;
6478};
6479
6480struct mlx5_ifc_create_srq_out_bits {
6481 u8 status[0x8];
b4ff3a36 6482 u8 reserved_at_8[0x18];
e281682b
SM		 6483
6484 u8 syndrome[0x20];
6485
b4ff3a36 6486 u8 reserved_at_40[0x8];
e281682b
SM		 6487 u8 srqn[0x18];
6488
b4ff3a36 6489 u8 reserved_at_60[0x20];
e281682b
SM		 6490};
6491
6492struct mlx5_ifc_create_srq_in_bits {
6493 u8 opcode[0x10];
b4ff3a36 6494 u8 reserved_at_10[0x10];
e281682b 6495
b4ff3a36 6496 u8 reserved_at_20[0x10];
e281682b
SM		 6497 u8 op_mod[0x10];
6498
b4ff3a36 6499 u8 reserved_at_40[0x40];
e281682b
SM		 6500
6501 struct mlx5_ifc_srqc_bits srq_context_entry;
6502
b4ff3a36 6503 u8 reserved_at_280[0x600];
e281682b
SM		 6504
6505 u8 pas[0][0x40];
6506};
6507
6508struct mlx5_ifc_create_sq_out_bits {
6509 u8 status[0x8];
b4ff3a36 6510 u8 reserved_at_8[0x18];
e281682b
SM		 6511
6512 u8 syndrome[0x20];
6513
b4ff3a36 6514 u8 reserved_at_40[0x8];
e281682b
SM		 6515 u8 sqn[0x18];
6516
b4ff3a36 6517 u8 reserved_at_60[0x20];
e281682b
SM		 6518};
6519
6520struct mlx5_ifc_create_sq_in_bits {
6521 u8 opcode[0x10];
b4ff3a36 6522 u8 reserved_at_10[0x10];
e281682b 6523
b4ff3a36 6524 u8 reserved_at_20[0x10];
e281682b
SM		 6525 u8 op_mod[0x10];
6526
b4ff3a36 6527 u8 reserved_at_40[0xc0];
e281682b
SM		 6528
6529 struct mlx5_ifc_sqc_bits ctx;
6530};
6531
813f8540
MHY		 6532struct mlx5_ifc_create_scheduling_element_out_bits {
6533 u8 status[0x8];
6534 u8 reserved_at_8[0x18];
6535
6536 u8 syndrome[0x20];
6537
6538 u8 reserved_at_40[0x40];
6539
6540 u8 scheduling_element_id[0x20];
6541
6542 u8 reserved_at_a0[0x160];
6543};
6544
6545struct mlx5_ifc_create_scheduling_element_in_bits {
6546 u8 opcode[0x10];
6547 u8 reserved_at_10[0x10];
6548
6549 u8 reserved_at_20[0x10];
6550 u8 op_mod[0x10];
6551
6552 u8 scheduling_hierarchy[0x8];
6553 u8 reserved_at_48[0x18];
6554
6555 u8 reserved_at_60[0xa0];
6556
6557 struct mlx5_ifc_scheduling_context_bits scheduling_context;
6558
6559 u8 reserved_at_300[0x100];
6560};
6561
e281682b
SM		 6562struct mlx5_ifc_create_rqt_out_bits {
6563 u8 status[0x8];
b4ff3a36 6564 u8 reserved_at_8[0x18];
e281682b
SM		 6565
6566 u8 syndrome[0x20];
6567
b4ff3a36 6568 u8 reserved_at_40[0x8];
e281682b
SM		 6569 u8 rqtn[0x18];
6570
b4ff3a36 6571 u8 reserved_at_60[0x20];
e281682b
SM		 6572};
6573
6574struct mlx5_ifc_create_rqt_in_bits {
6575 u8 opcode[0x10];
b4ff3a36 6576 u8 reserved_at_10[0x10];
e281682b 6577
b4ff3a36 6578 u8 reserved_at_20[0x10];
e281682b
SM		 6579 u8 op_mod[0x10];
6580
b4ff3a36 6581 u8 reserved_at_40[0xc0];
e281682b
SM		 6582
6583 struct mlx5_ifc_rqtc_bits rqt_context;
6584};
6585
6586struct mlx5_ifc_create_rq_out_bits {
6587 u8 status[0x8];
b4ff3a36 6588 u8 reserved_at_8[0x18];
e281682b
SM		 6589
6590 u8 syndrome[0x20];
6591
b4ff3a36 6592 u8 reserved_at_40[0x8];
e281682b
SM		 6593 u8 rqn[0x18];
6594
b4ff3a36 6595 u8 reserved_at_60[0x20];
e281682b
SM		 6596};
6597
6598struct mlx5_ifc_create_rq_in_bits {
6599 u8 opcode[0x10];
b4ff3a36 6600 u8 reserved_at_10[0x10];
e281682b 6601
b4ff3a36 6602 u8 reserved_at_20[0x10];
e281682b
SM		 6603 u8 op_mod[0x10];
6604
b4ff3a36 6605 u8 reserved_at_40[0xc0];
e281682b
SM		 6606
6607 struct mlx5_ifc_rqc_bits ctx;
6608};
6609
6610struct mlx5_ifc_create_rmp_out_bits {
6611 u8 status[0x8];
b4ff3a36 6612 u8 reserved_at_8[0x18];
e281682b
SM		 6613
6614 u8 syndrome[0x20];
6615
b4ff3a36 6616 u8 reserved_at_40[0x8];
e281682b
SM		 6617 u8 rmpn[0x18];
6618
b4ff3a36 6619 u8 reserved_at_60[0x20];
e281682b
SM		 6620};
6621
6622struct mlx5_ifc_create_rmp_in_bits {
6623 u8 opcode[0x10];
b4ff3a36 6624 u8 reserved_at_10[0x10];
e281682b 6625
b4ff3a36 6626 u8 reserved_at_20[0x10];
e281682b
SM		 6627 u8 op_mod[0x10];
6628
b4ff3a36 6629 u8 reserved_at_40[0xc0];
e281682b
SM		 6630
6631 struct mlx5_ifc_rmpc_bits ctx;
6632};
6633
6634struct mlx5_ifc_create_qp_out_bits {
6635 u8 status[0x8];
b4ff3a36 6636 u8 reserved_at_8[0x18];
e281682b
SM		 6637
6638 u8 syndrome[0x20];
6639
b4ff3a36 6640 u8 reserved_at_40[0x8];
e281682b
SM		 6641 u8 qpn[0x18];
6642
b4ff3a36 6643 u8 reserved_at_60[0x20];
e281682b
SM		 6644};
6645
6646struct mlx5_ifc_create_qp_in_bits {
6647 u8 opcode[0x10];
b4ff3a36 6648 u8 reserved_at_10[0x10];
e281682b 6649
b4ff3a36 6650 u8 reserved_at_20[0x10];
e281682b
SM		 6651 u8 op_mod[0x10];
6652
b4ff3a36 6653 u8 reserved_at_40[0x40];
e281682b
SM		 6654
6655 u8 opt_param_mask[0x20];
6656
b4ff3a36 6657 u8 reserved_at_a0[0x20];
e281682b
SM		 6658
6659 struct mlx5_ifc_qpc_bits qpc;
6660
b4ff3a36 6661 u8 reserved_at_800[0x80];
e281682b
SM		 6662
6663 u8 pas[0][0x40];
6664};
6665
6666struct mlx5_ifc_create_psv_out_bits {
6667 u8 status[0x8];
b4ff3a36 6668 u8 reserved_at_8[0x18];
e281682b
SM		 6669
6670 u8 syndrome[0x20];
6671
b4ff3a36 6672 u8 reserved_at_40[0x40];
e281682b 6673
b4ff3a36 6674 u8 reserved_at_80[0x8];
e281682b
SM		 6675 u8 psv0_index[0x18];
6676
b4ff3a36 6677 u8 reserved_at_a0[0x8];
e281682b
SM		 6678 u8 psv1_index[0x18];
6679
b4ff3a36 6680 u8 reserved_at_c0[0x8];
e281682b
SM		 6681 u8 psv2_index[0x18];
6682
b4ff3a36 6683 u8 reserved_at_e0[0x8];
e281682b
SM		 6684 u8 psv3_index[0x18];
6685};
6686
6687struct mlx5_ifc_create_psv_in_bits {
6688 u8 opcode[0x10];
b4ff3a36 6689 u8 reserved_at_10[0x10];
e281682b 6690
b4ff3a36 6691 u8 reserved_at_20[0x10];
e281682b
SM		 6692 u8 op_mod[0x10];
6693
6694 u8 num_psv[0x4];
b4ff3a36 6695 u8 reserved_at_44[0x4];
e281682b
SM		 6696 u8 pd[0x18];
6697
b4ff3a36 6698 u8 reserved_at_60[0x20];
e281682b
SM		 6699};
6700
6701struct mlx5_ifc_create_mkey_out_bits {
6702 u8 status[0x8];
b4ff3a36 6703 u8 reserved_at_8[0x18];
e281682b
SM		 6704
6705 u8 syndrome[0x20];
6706
b4ff3a36 6707 u8 reserved_at_40[0x8];
e281682b
SM		 6708 u8 mkey_index[0x18];
6709
b4ff3a36 6710 u8 reserved_at_60[0x20];
e281682b
SM		 6711};
6712
6713struct mlx5_ifc_create_mkey_in_bits {
6714 u8 opcode[0x10];
b4ff3a36 6715 u8 reserved_at_10[0x10];
e281682b 6716
b4ff3a36 6717 u8 reserved_at_20[0x10];
e281682b
SM		 6718 u8 op_mod[0x10];
6719
b4ff3a36 6720 u8 reserved_at_40[0x20];
e281682b
SM		 6721
6722 u8 pg_access[0x1];
b4ff3a36 6723 u8 reserved_at_61[0x1f];
e281682b
SM		 6724
6725 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6726
b4ff3a36 6727 u8 reserved_at_280[0x80];
e281682b
SM		 6728
6729 u8 translations_octword_actual_size[0x20];
6730
b4ff3a36 6731 u8 reserved_at_320[0x560];
e281682b
SM		 6732
6733 u8 klm_pas_mtt[0][0x20];
6734};
6735
6736struct mlx5_ifc_create_flow_table_out_bits {
6737 u8 status[0x8];
b4ff3a36 6738 u8 reserved_at_8[0x18];
e281682b
SM		 6739
6740 u8 syndrome[0x20];
6741
b4ff3a36 6742 u8 reserved_at_40[0x8];
e281682b
SM		 6743 u8 table_id[0x18];
6744
b4ff3a36 6745 u8 reserved_at_60[0x20];
e281682b
SM		 6746};
6747
0c90e9c6
MG		 6748struct mlx5_ifc_flow_table_context_bits {
6749 u8 encap_en[0x1];
6750 u8 decap_en[0x1];
6751 u8 reserved_at_2[0x2];
6752 u8 table_miss_action[0x4];
6753 u8 level[0x8];
6754 u8 reserved_at_10[0x8];
6755 u8 log_size[0x8];
6756
6757 u8 reserved_at_20[0x8];
6758 u8 table_miss_id[0x18];
6759
6760 u8 reserved_at_40[0x8];
6761 u8 lag_master_next_table_id[0x18];
6762
6763 u8 reserved_at_60[0xe0];
6764};
6765
e281682b
SM		 6766struct mlx5_ifc_create_flow_table_in_bits {
6767 u8 opcode[0x10];
b4ff3a36 6768 u8 reserved_at_10[0x10];
e281682b 6769
b4ff3a36 6770 u8 reserved_at_20[0x10];
e281682b
SM		 6771 u8 op_mod[0x10];
6772
7d5e1423
SM		 6773 u8 other_vport[0x1];
6774 u8 reserved_at_41[0xf];
6775 u8 vport_number[0x10];
6776
6777 u8 reserved_at_60[0x20];
e281682b
SM		 6778
6779 u8 table_type[0x8];
b4ff3a36 6780 u8 reserved_at_88[0x18];
e281682b 6781
b4ff3a36 6782 u8 reserved_at_a0[0x20];
e281682b 6783
0c90e9c6 6784 struct mlx5_ifc_flow_table_context_bits flow_table_context;
e281682b
SM		 6785};
6786
6787struct mlx5_ifc_create_flow_group_out_bits {
6788 u8 status[0x8];
b4ff3a36 6789 u8 reserved_at_8[0x18];
e281682b
SM		 6790
6791 u8 syndrome[0x20];
6792
b4ff3a36 6793 u8 reserved_at_40[0x8];
e281682b
SM		 6794 u8 group_id[0x18];
6795
b4ff3a36 6796 u8 reserved_at_60[0x20];
e281682b
SM		 6797};
6798
6799enum {
6800 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
6801 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
6802 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
6803};
6804
6805struct mlx5_ifc_create_flow_group_in_bits {
6806 u8 opcode[0x10];
b4ff3a36 6807 u8 reserved_at_10[0x10];
e281682b 6808
b4ff3a36 6809 u8 reserved_at_20[0x10];
e281682b
SM		 6810 u8 op_mod[0x10];
6811
7d5e1423
SM		 6812 u8 other_vport[0x1];
6813 u8 reserved_at_41[0xf];
6814 u8 vport_number[0x10];
6815
6816 u8 reserved_at_60[0x20];
e281682b
SM		 6817
6818 u8 table_type[0x8];
b4ff3a36 6819 u8 reserved_at_88[0x18];
e281682b 6820
b4ff3a36 6821 u8 reserved_at_a0[0x8];
e281682b
SM		 6822 u8 table_id[0x18];
6823
b4ff3a36 6824 u8 reserved_at_c0[0x20];
e281682b
SM		 6825
6826 u8 start_flow_index[0x20];
6827
b4ff3a36 6828 u8 reserved_at_100[0x20];
e281682b
SM		 6829
6830 u8 end_flow_index[0x20];
6831
b4ff3a36 6832 u8 reserved_at_140[0xa0];
e281682b 6833
b4ff3a36 6834 u8 reserved_at_1e0[0x18];
e281682b
SM		 6835 u8 match_criteria_enable[0x8];
6836
6837 struct mlx5_ifc_fte_match_param_bits match_criteria;
6838
b4ff3a36 6839 u8 reserved_at_1200[0xe00];
e281682b
SM		 6840};
6841
6842struct mlx5_ifc_create_eq_out_bits {
6843 u8 status[0x8];
b4ff3a36 6844 u8 reserved_at_8[0x18];
e281682b
SM		 6845
6846 u8 syndrome[0x20];
6847
b4ff3a36 6848 u8 reserved_at_40[0x18];
e281682b
SM		 6849 u8 eq_number[0x8];
6850
b4ff3a36 6851 u8 reserved_at_60[0x20];
e281682b
SM		 6852};
6853
6854struct mlx5_ifc_create_eq_in_bits {
6855 u8 opcode[0x10];
b4ff3a36 6856 u8 reserved_at_10[0x10];
e281682b 6857
b4ff3a36 6858 u8 reserved_at_20[0x10];
e281682b
SM		 6859 u8 op_mod[0x10];
6860
b4ff3a36 6861 u8 reserved_at_40[0x40];
e281682b
SM		 6862
6863 struct mlx5_ifc_eqc_bits eq_context_entry;
6864
b4ff3a36 6865 u8 reserved_at_280[0x40];
e281682b
SM		 6866
6867 u8 event_bitmask[0x40];
6868
b4ff3a36 6869 u8 reserved_at_300[0x580];
e281682b
SM		 6870
6871 u8 pas[0][0x40];
6872};
6873
6874struct mlx5_ifc_create_dct_out_bits {
6875 u8 status[0x8];
b4ff3a36 6876 u8 reserved_at_8[0x18];
e281682b
SM		 6877
6878 u8 syndrome[0x20];
6879
b4ff3a36 6880 u8 reserved_at_40[0x8];
e281682b
SM		 6881 u8 dctn[0x18];
6882
b4ff3a36 6883 u8 reserved_at_60[0x20];
e281682b
SM		 6884};
6885
6886struct mlx5_ifc_create_dct_in_bits {
6887 u8 opcode[0x10];
b4ff3a36 6888 u8 reserved_at_10[0x10];
e281682b 6889
b4ff3a36 6890 u8 reserved_at_20[0x10];
e281682b
SM		 6891 u8 op_mod[0x10];
6892
b4ff3a36 6893 u8 reserved_at_40[0x40];
e281682b
SM		 6894
6895 struct mlx5_ifc_dctc_bits dct_context_entry;
6896
b4ff3a36 6897 u8 reserved_at_280[0x180];
e281682b
SM		 6898};
6899
6900struct mlx5_ifc_create_cq_out_bits {
6901 u8 status[0x8];
b4ff3a36 6902 u8 reserved_at_8[0x18];
e281682b
SM		 6903
6904 u8 syndrome[0x20];
6905
b4ff3a36 6906 u8 reserved_at_40[0x8];
e281682b
SM		 6907 u8 cqn[0x18];
6908
b4ff3a36 6909 u8 reserved_at_60[0x20];
e281682b
SM		 6910};
6911
6912struct mlx5_ifc_create_cq_in_bits {
6913 u8 opcode[0x10];
b4ff3a36 6914 u8 reserved_at_10[0x10];
e281682b 6915
b4ff3a36 6916 u8 reserved_at_20[0x10];
e281682b
SM		 6917 u8 op_mod[0x10];
6918
b4ff3a36 6919 u8 reserved_at_40[0x40];
e281682b
SM		 6920
6921 struct mlx5_ifc_cqc_bits cq_context;
6922
b4ff3a36 6923 u8 reserved_at_280[0x600];
e281682b
SM		 6924
6925 u8 pas[0][0x40];
6926};
6927
6928struct mlx5_ifc_config_int_moderation_out_bits {
6929 u8 status[0x8];
b4ff3a36 6930 u8 reserved_at_8[0x18];
e281682b
SM		 6931
6932 u8 syndrome[0x20];
6933
b4ff3a36 6934 u8 reserved_at_40[0x4];
e281682b
SM		 6935 u8 min_delay[0xc];
6936 u8 int_vector[0x10];
6937
b4ff3a36 6938 u8 reserved_at_60[0x20];
e281682b
SM		 6939};
6940
6941enum {
6942 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
6943 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
6944};
6945
6946struct mlx5_ifc_config_int_moderation_in_bits {
6947 u8 opcode[0x10];
b4ff3a36 6948 u8 reserved_at_10[0x10];
e281682b 6949
b4ff3a36 6950 u8 reserved_at_20[0x10];
e281682b
SM		 6951 u8 op_mod[0x10];
6952
b4ff3a36 6953 u8 reserved_at_40[0x4];
e281682b
SM		 6954 u8 min_delay[0xc];
6955 u8 int_vector[0x10];
6956
b4ff3a36 6957 u8 reserved_at_60[0x20];
e281682b
SM		 6958};
6959
6960struct mlx5_ifc_attach_to_mcg_out_bits {
6961 u8 status[0x8];
b4ff3a36 6962 u8 reserved_at_8[0x18];
e281682b
SM		 6963
6964 u8 syndrome[0x20];
6965
b4ff3a36 6966 u8 reserved_at_40[0x40];
e281682b
SM		 6967};
6968
6969struct mlx5_ifc_attach_to_mcg_in_bits {
6970 u8 opcode[0x10];
b4ff3a36 6971 u8 reserved_at_10[0x10];
e281682b 6972
b4ff3a36 6973 u8 reserved_at_20[0x10];
e281682b
SM		 6974 u8 op_mod[0x10];
6975
b4ff3a36 6976 u8 reserved_at_40[0x8];
e281682b
SM		 6977 u8 qpn[0x18];
6978
b4ff3a36 6979 u8 reserved_at_60[0x20];
e281682b
SM		 6980
6981 u8 multicast_gid[16][0x8];
6982};
6983
7486216b
SM		 6984struct mlx5_ifc_arm_xrq_out_bits {
6985 u8 status[0x8];
6986 u8 reserved_at_8[0x18];
6987
6988 u8 syndrome[0x20];
6989
6990 u8 reserved_at_40[0x40];
6991};
6992
6993struct mlx5_ifc_arm_xrq_in_bits {
6994 u8 opcode[0x10];
6995 u8 reserved_at_10[0x10];
6996
6997 u8 reserved_at_20[0x10];
6998 u8 op_mod[0x10];
6999
7000 u8 reserved_at_40[0x8];
7001 u8 xrqn[0x18];
7002
7003 u8 reserved_at_60[0x10];
7004 u8 lwm[0x10];
7005};
7006
e281682b
SM		 7007struct mlx5_ifc_arm_xrc_srq_out_bits {
7008 u8 status[0x8];
b4ff3a36 7009 u8 reserved_at_8[0x18];
e281682b
SM		 7010
7011 u8 syndrome[0x20];
7012
b4ff3a36 7013 u8 reserved_at_40[0x40];
e281682b
SM		 7014};
7015
7016enum {
7017 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
7018};
7019
7020struct mlx5_ifc_arm_xrc_srq_in_bits {
7021 u8 opcode[0x10];
b4ff3a36 7022 u8 reserved_at_10[0x10];
e281682b 7023
b4ff3a36 7024 u8 reserved_at_20[0x10];
e281682b
SM		 7025 u8 op_mod[0x10];
7026
b4ff3a36 7027 u8 reserved_at_40[0x8];
e281682b
SM		 7028 u8 xrc_srqn[0x18];
7029
b4ff3a36 7030 u8 reserved_at_60[0x10];
e281682b
SM		 7031 u8 lwm[0x10];
7032};
7033
7034struct mlx5_ifc_arm_rq_out_bits {
7035 u8 status[0x8];
b4ff3a36 7036 u8 reserved_at_8[0x18];
e281682b
SM		 7037
7038 u8 syndrome[0x20];
7039
b4ff3a36 7040 u8 reserved_at_40[0x40];
e281682b
SM		 7041};
7042
7043enum {
7486216b
SM		 7044 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
7045 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
e281682b
SM		 7046};
7047
7048struct mlx5_ifc_arm_rq_in_bits {
7049 u8 opcode[0x10];
b4ff3a36 7050 u8 reserved_at_10[0x10];
e281682b 7051
b4ff3a36 7052 u8 reserved_at_20[0x10];
e281682b
SM		 7053 u8 op_mod[0x10];
7054
b4ff3a36 7055 u8 reserved_at_40[0x8];
e281682b
SM		 7056 u8 srq_number[0x18];
7057
b4ff3a36 7058 u8 reserved_at_60[0x10];
e281682b
SM		 7059 u8 lwm[0x10];
7060};
7061
7062struct mlx5_ifc_arm_dct_out_bits {
7063 u8 status[0x8];
b4ff3a36 7064 u8 reserved_at_8[0x18];
e281682b
SM		 7065
7066 u8 syndrome[0x20];
7067
b4ff3a36 7068 u8 reserved_at_40[0x40];
e281682b
SM		 7069};
7070
7071struct mlx5_ifc_arm_dct_in_bits {
7072 u8 opcode[0x10];
b4ff3a36 7073 u8 reserved_at_10[0x10];
e281682b 7074
b4ff3a36 7075 u8 reserved_at_20[0x10];
e281682b
SM		 7076 u8 op_mod[0x10];
7077
b4ff3a36 7078 u8 reserved_at_40[0x8];
e281682b
SM		 7079 u8 dct_number[0x18];
7080
b4ff3a36 7081 u8 reserved_at_60[0x20];
e281682b
SM		 7082};
7083
7084struct mlx5_ifc_alloc_xrcd_out_bits {
7085 u8 status[0x8];
b4ff3a36 7086 u8 reserved_at_8[0x18];
e281682b
SM		 7087
7088 u8 syndrome[0x20];
7089
b4ff3a36 7090 u8 reserved_at_40[0x8];
e281682b
SM		 7091 u8 xrcd[0x18];
7092
b4ff3a36 7093 u8 reserved_at_60[0x20];
e281682b
SM		 7094};
7095
7096struct mlx5_ifc_alloc_xrcd_in_bits {
7097 u8 opcode[0x10];
b4ff3a36 7098 u8 reserved_at_10[0x10];
e281682b 7099
b4ff3a36 7100 u8 reserved_at_20[0x10];
e281682b
SM		 7101 u8 op_mod[0x10];
7102
b4ff3a36 7103 u8 reserved_at_40[0x40];
e281682b
SM		 7104};
7105
7106struct mlx5_ifc_alloc_uar_out_bits {
7107 u8 status[0x8];
b4ff3a36 7108 u8 reserved_at_8[0x18];
e281682b
SM		 7109
7110 u8 syndrome[0x20];
7111
b4ff3a36 7112 u8 reserved_at_40[0x8];
e281682b
SM		 7113 u8 uar[0x18];
7114
b4ff3a36 7115 u8 reserved_at_60[0x20];
e281682b
SM		 7116};
7117
7118struct mlx5_ifc_alloc_uar_in_bits {
7119 u8 opcode[0x10];
b4ff3a36 7120 u8 reserved_at_10[0x10];
e281682b 7121
b4ff3a36 7122 u8 reserved_at_20[0x10];
e281682b
SM		 7123 u8 op_mod[0x10];
7124
b4ff3a36 7125 u8 reserved_at_40[0x40];
e281682b
SM		 7126};
7127
7128struct mlx5_ifc_alloc_transport_domain_out_bits {
7129 u8 status[0x8];
b4ff3a36 7130 u8 reserved_at_8[0x18];
e281682b
SM		 7131
7132 u8 syndrome[0x20];
7133
b4ff3a36 7134 u8 reserved_at_40[0x8];
e281682b
SM		 7135 u8 transport_domain[0x18];
7136
b4ff3a36 7137 u8 reserved_at_60[0x20];
e281682b
SM		 7138};
7139
7140struct mlx5_ifc_alloc_transport_domain_in_bits {
7141 u8 opcode[0x10];
b4ff3a36 7142 u8 reserved_at_10[0x10];
e281682b 7143
b4ff3a36 7144 u8 reserved_at_20[0x10];
e281682b
SM		 7145 u8 op_mod[0x10];
7146
b4ff3a36 7147 u8 reserved_at_40[0x40];
e281682b
SM		 7148};
7149
7150struct mlx5_ifc_alloc_q_counter_out_bits {
7151 u8 status[0x8];
b4ff3a36 7152 u8 reserved_at_8[0x18];
e281682b
SM		 7153
7154 u8 syndrome[0x20];
7155
b4ff3a36 7156 u8 reserved_at_40[0x18];
e281682b
SM		 7157 u8 counter_set_id[0x8];
7158
b4ff3a36 7159 u8 reserved_at_60[0x20];
e281682b
SM		 7160};
7161
7162struct mlx5_ifc_alloc_q_counter_in_bits {
7163 u8 opcode[0x10];
b4ff3a36 7164 u8 reserved_at_10[0x10];
e281682b 7165
b4ff3a36 7166 u8 reserved_at_20[0x10];
e281682b
SM		 7167 u8 op_mod[0x10];
7168
b4ff3a36 7169 u8 reserved_at_40[0x40];
e281682b
SM		 7170};
7171
7172struct mlx5_ifc_alloc_pd_out_bits {
7173 u8 status[0x8];
b4ff3a36 7174 u8 reserved_at_8[0x18];
e281682b
SM		 7175
7176 u8 syndrome[0x20];
7177
b4ff3a36 7178 u8 reserved_at_40[0x8];
e281682b
SM		 7179 u8 pd[0x18];
7180
b4ff3a36 7181 u8 reserved_at_60[0x20];
e281682b
SM		 7182};
7183
7184struct mlx5_ifc_alloc_pd_in_bits {
9dc0b289
AV		 7185 u8 opcode[0x10];
7186 u8 reserved_at_10[0x10];
7187
7188 u8 reserved_at_20[0x10];
7189 u8 op_mod[0x10];
7190
7191 u8 reserved_at_40[0x40];
7192};
7193
7194struct mlx5_ifc_alloc_flow_counter_out_bits {
7195 u8 status[0x8];
7196 u8 reserved_at_8[0x18];
7197
7198 u8 syndrome[0x20];
7199
a8ffcc74 7200 u8 flow_counter_id[0x20];
9dc0b289
AV		 7201
7202 u8 reserved_at_60[0x20];
7203};
7204
7205struct mlx5_ifc_alloc_flow_counter_in_bits {
e281682b 7206 u8 opcode[0x10];
b4ff3a36 7207 u8 reserved_at_10[0x10];
e281682b 7208
b4ff3a36 7209 u8 reserved_at_20[0x10];
e281682b
SM		 7210 u8 op_mod[0x10];
7211
b4ff3a36 7212 u8 reserved_at_40[0x40];
e281682b
SM		 7213};
7214
7215struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7216 u8 status[0x8];
b4ff3a36 7217 u8 reserved_at_8[0x18];
e281682b
SM		 7218
7219 u8 syndrome[0x20];
7220
b4ff3a36 7221 u8 reserved_at_40[0x40];
e281682b
SM		 7222};
7223
7224struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7225 u8 opcode[0x10];
b4ff3a36 7226 u8 reserved_at_10[0x10];
e281682b 7227
b4ff3a36 7228 u8 reserved_at_20[0x10];
e281682b
SM		 7229 u8 op_mod[0x10];
7230
b4ff3a36 7231 u8 reserved_at_40[0x20];
e281682b 7232
b4ff3a36 7233 u8 reserved_at_60[0x10];
e281682b
SM		 7234 u8 vxlan_udp_port[0x10];
7235};
7236
7486216b
SM		 7237struct mlx5_ifc_set_rate_limit_out_bits {
7238 u8 status[0x8];
7239 u8 reserved_at_8[0x18];
7240
7241 u8 syndrome[0x20];
7242
7243 u8 reserved_at_40[0x40];
7244};
7245
7246struct mlx5_ifc_set_rate_limit_in_bits {
7247 u8 opcode[0x10];
7248 u8 reserved_at_10[0x10];
7249
7250 u8 reserved_at_20[0x10];
7251 u8 op_mod[0x10];
7252
7253 u8 reserved_at_40[0x10];
7254 u8 rate_limit_index[0x10];
7255
7256 u8 reserved_at_60[0x20];
7257
7258 u8 rate_limit[0x20];
7259};
7260
e281682b
SM		 7261struct mlx5_ifc_access_register_out_bits {
7262 u8 status[0x8];
b4ff3a36 7263 u8 reserved_at_8[0x18];
e281682b
SM		 7264
7265 u8 syndrome[0x20];
7266
b4ff3a36 7267 u8 reserved_at_40[0x40];
e281682b
SM		 7268
7269 u8 register_data[0][0x20];
7270};
7271
7272enum {
7273 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
7274 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
7275};
7276
7277struct mlx5_ifc_access_register_in_bits {
7278 u8 opcode[0x10];
b4ff3a36 7279 u8 reserved_at_10[0x10];
e281682b 7280
b4ff3a36 7281 u8 reserved_at_20[0x10];
e281682b
SM		 7282 u8 op_mod[0x10];
7283
b4ff3a36 7284 u8 reserved_at_40[0x10];
e281682b
SM		 7285 u8 register_id[0x10];
7286
7287 u8 argument[0x20];
7288
7289 u8 register_data[0][0x20];
7290};
7291
7292struct mlx5_ifc_sltp_reg_bits {
7293 u8 status[0x4];
7294 u8 version[0x4];
7295 u8 local_port[0x8];
7296 u8 pnat[0x2];
b4ff3a36 7297 u8 reserved_at_12[0x2];
e281682b 7298 u8 lane[0x4];
b4ff3a36 7299 u8 reserved_at_18[0x8];
e281682b 7300
b4ff3a36 7301 u8 reserved_at_20[0x20];
e281682b 7302
b4ff3a36 7303 u8 reserved_at_40[0x7];
e281682b
SM		 7304 u8 polarity[0x1];
7305 u8 ob_tap0[0x8];
7306 u8 ob_tap1[0x8];
7307 u8 ob_tap2[0x8];
7308
b4ff3a36 7309 u8 reserved_at_60[0xc];
e281682b
SM		 7310 u8 ob_preemp_mode[0x4];
7311 u8 ob_reg[0x8];
7312 u8 ob_bias[0x8];
7313
b4ff3a36 7314 u8 reserved_at_80[0x20];
e281682b
SM		 7315};
7316
7317struct mlx5_ifc_slrg_reg_bits {
7318 u8 status[0x4];
7319 u8 version[0x4];
7320 u8 local_port[0x8];
7321 u8 pnat[0x2];
b4ff3a36 7322 u8 reserved_at_12[0x2];
e281682b 7323 u8 lane[0x4];
b4ff3a36 7324 u8 reserved_at_18[0x8];
e281682b
SM		 7325
7326 u8 time_to_link_up[0x10];
b4ff3a36 7327 u8 reserved_at_30[0xc];
e281682b
SM		 7328 u8 grade_lane_speed[0x4];
7329
7330 u8 grade_version[0x8];
7331 u8 grade[0x18];
7332
b4ff3a36 7333 u8 reserved_at_60[0x4];
e281682b
SM		 7334 u8 height_grade_type[0x4];
7335 u8 height_grade[0x18];
7336
7337 u8 height_dz[0x10];
7338 u8 height_dv[0x10];
7339
b4ff3a36 7340 u8 reserved_at_a0[0x10];
e281682b
SM		 7341 u8 height_sigma[0x10];
7342
b4ff3a36 7343 u8 reserved_at_c0[0x20];
e281682b 7344
b4ff3a36 7345 u8 reserved_at_e0[0x4];
e281682b
SM		 7346 u8 phase_grade_type[0x4];
7347 u8 phase_grade[0x18];
7348
b4ff3a36 7349 u8 reserved_at_100[0x8];
e281682b 7350 u8 phase_eo_pos[0x8];
b4ff3a36 7351 u8 reserved_at_110[0x8];
e281682b
SM		 7352 u8 phase_eo_neg[0x8];
7353
7354 u8 ffe_set_tested[0x10];
7355 u8 test_errors_per_lane[0x10];
7356};
7357
7358struct mlx5_ifc_pvlc_reg_bits {
b4ff3a36 7359 u8 reserved_at_0[0x8];
e281682b 7360 u8 local_port[0x8];
b4ff3a36 7361 u8 reserved_at_10[0x10];
e281682b 7362
b4ff3a36 7363 u8 reserved_at_20[0x1c];
e281682b
SM		 7364 u8 vl_hw_cap[0x4];
7365
b4ff3a36 7366 u8 reserved_at_40[0x1c];
e281682b
SM		 7367 u8 vl_admin[0x4];
7368
b4ff3a36 7369 u8 reserved_at_60[0x1c];
e281682b
SM		 7370 u8 vl_operational[0x4];
7371};
7372
7373struct mlx5_ifc_pude_reg_bits {
7374 u8 swid[0x8];
7375 u8 local_port[0x8];
b4ff3a36 7376 u8 reserved_at_10[0x4];
e281682b 7377 u8 admin_status[0x4];
b4ff3a36 7378 u8 reserved_at_18[0x4];
e281682b
SM		 7379 u8 oper_status[0x4];
7380
b4ff3a36 7381 u8 reserved_at_20[0x60];
e281682b
SM		 7382};
7383
7384struct mlx5_ifc_ptys_reg_bits {
e7e31ca4 7385 u8 reserved_at_0[0x1];
7486216b 7386 u8 an_disable_admin[0x1];
e7e31ca4
BW		 7387 u8 an_disable_cap[0x1];
7388 u8 reserved_at_3[0x5];
e281682b 7389 u8 local_port[0x8];
b4ff3a36 7390 u8 reserved_at_10[0xd];
e281682b
SM		 7391 u8 proto_mask[0x3];
7392
7486216b
SM		 7393 u8 an_status[0x4];
7394 u8 reserved_at_24[0x3c];
e281682b
SM		 7395
7396 u8 eth_proto_capability[0x20];
7397
7398 u8 ib_link_width_capability[0x10];
7399 u8 ib_proto_capability[0x10];
7400
b4ff3a36 7401 u8 reserved_at_a0[0x20];
e281682b
SM		 7402
7403 u8 eth_proto_admin[0x20];
7404
7405 u8 ib_link_width_admin[0x10];
7406 u8 ib_proto_admin[0x10];
7407
b4ff3a36 7408 u8 reserved_at_100[0x20];
e281682b
SM		 7409
7410 u8 eth_proto_oper[0x20];
7411
7412 u8 ib_link_width_oper[0x10];
7413 u8 ib_proto_oper[0x10];
7414
5b4793f8
EBE		 7415 u8 reserved_at_160[0x1c];
7416 u8 connector_type[0x4];
e281682b
SM		 7417
7418 u8 eth_proto_lp_advertise[0x20];
7419
b4ff3a36 7420 u8 reserved_at_1a0[0x60];
e281682b
SM		 7421};
7422
7d5e1423
SM		 7423struct mlx5_ifc_mlcr_reg_bits {
7424 u8 reserved_at_0[0x8];
7425 u8 local_port[0x8];
7426 u8 reserved_at_10[0x20];
7427
7428 u8 beacon_duration[0x10];
7429 u8 reserved_at_40[0x10];
7430
7431 u8 beacon_remain[0x10];
7432};
7433
e281682b 7434struct mlx5_ifc_ptas_reg_bits {
b4ff3a36 7435 u8 reserved_at_0[0x20];
e281682b
SM		 7436
7437 u8 algorithm_options[0x10];
b4ff3a36 7438 u8 reserved_at_30[0x4];
e281682b
SM		 7439 u8 repetitions_mode[0x4];
7440 u8 num_of_repetitions[0x8];
7441
7442 u8 grade_version[0x8];
7443 u8 height_grade_type[0x4];
7444 u8 phase_grade_type[0x4];
7445 u8 height_grade_weight[0x8];
7446 u8 phase_grade_weight[0x8];
7447
7448 u8 gisim_measure_bits[0x10];
7449 u8 adaptive_tap_measure_bits[0x10];
7450
7451 u8 ber_bath_high_error_threshold[0x10];
7452 u8 ber_bath_mid_error_threshold[0x10];
7453
7454 u8 ber_bath_low_error_threshold[0x10];
7455 u8 one_ratio_high_threshold[0x10];
7456
7457 u8 one_ratio_high_mid_threshold[0x10];
7458 u8 one_ratio_low_mid_threshold[0x10];
7459
7460 u8 one_ratio_low_threshold[0x10];
7461 u8 ndeo_error_threshold[0x10];
7462
7463 u8 mixer_offset_step_size[0x10];
b4ff3a36 7464 u8 reserved_at_110[0x8];
e281682b
SM		 7465 u8 mix90_phase_for_voltage_bath[0x8];
7466
7467 u8 mixer_offset_start[0x10];
7468 u8 mixer_offset_end[0x10];
7469
b4ff3a36 7470 u8 reserved_at_140[0x15];
e281682b
SM		 7471 u8 ber_test_time[0xb];
7472};
7473
7474struct mlx5_ifc_pspa_reg_bits {
7475 u8 swid[0x8];
7476 u8 local_port[0x8];
7477 u8 sub_port[0x8];
b4ff3a36 7478 u8 reserved_at_18[0x8];
e281682b 7479
b4ff3a36 7480 u8 reserved_at_20[0x20];
e281682b
SM		 7481};
7482
7483struct mlx5_ifc_pqdr_reg_bits {
b4ff3a36 7484 u8 reserved_at_0[0x8];
e281682b 7485 u8 local_port[0x8];
b4ff3a36 7486 u8 reserved_at_10[0x5];
e281682b 7487 u8 prio[0x3];
b4ff3a36 7488 u8 reserved_at_18[0x6];
e281682b
SM		 7489 u8 mode[0x2];
7490
b4ff3a36 7491 u8 reserved_at_20[0x20];
e281682b 7492
b4ff3a36 7493 u8 reserved_at_40[0x10];
e281682b
SM		 7494 u8 min_threshold[0x10];
7495
b4ff3a36 7496 u8 reserved_at_60[0x10];
e281682b
SM		 7497 u8 max_threshold[0x10];
7498
b4ff3a36 7499 u8 reserved_at_80[0x10];
e281682b
SM		 7500 u8 mark_probability_denominator[0x10];
7501
b4ff3a36 7502 u8 reserved_at_a0[0x60];
e281682b
SM		 7503};
7504
7505struct mlx5_ifc_ppsc_reg_bits {
b4ff3a36 7506 u8 reserved_at_0[0x8];
e281682b 7507 u8 local_port[0x8];
b4ff3a36 7508 u8 reserved_at_10[0x10];
e281682b 7509
b4ff3a36 7510 u8 reserved_at_20[0x60];
e281682b 7511
b4ff3a36 7512 u8 reserved_at_80[0x1c];
e281682b
SM		 7513 u8 wrps_admin[0x4];
7514
b4ff3a36 7515 u8 reserved_at_a0[0x1c];
e281682b
SM		 7516 u8 wrps_status[0x4];
7517
b4ff3a36 7518 u8 reserved_at_c0[0x8];
e281682b 7519 u8 up_threshold[0x8];
b4ff3a36 7520 u8 reserved_at_d0[0x8];
e281682b
SM		 7521 u8 down_threshold[0x8];
7522
b4ff3a36 7523 u8 reserved_at_e0[0x20];
e281682b 7524
b4ff3a36 7525 u8 reserved_at_100[0x1c];
e281682b
SM		 7526 u8 srps_admin[0x4];
7527
b4ff3a36 7528 u8 reserved_at_120[0x1c];
e281682b
SM		 7529 u8 srps_status[0x4];
7530
b4ff3a36 7531 u8 reserved_at_140[0x40];
e281682b
SM		 7532};
7533
7534struct mlx5_ifc_pplr_reg_bits {
b4ff3a36 7535 u8 reserved_at_0[0x8];
e281682b 7536 u8 local_port[0x8];
b4ff3a36 7537 u8 reserved_at_10[0x10];
e281682b 7538
b4ff3a36 7539 u8 reserved_at_20[0x8];
e281682b 7540 u8 lb_cap[0x8];
b4ff3a36 7541 u8 reserved_at_30[0x8];
e281682b
SM		 7542 u8 lb_en[0x8];
7543};
7544
7545struct mlx5_ifc_pplm_reg_bits {
b4ff3a36 7546 u8 reserved_at_0[0x8];
e281682b 7547 u8 local_port[0x8];
b4ff3a36 7548 u8 reserved_at_10[0x10];
e281682b 7549
b4ff3a36 7550 u8 reserved_at_20[0x20];
e281682b
SM		 7551
7552 u8 port_profile_mode[0x8];
7553 u8 static_port_profile[0x8];
7554 u8 active_port_profile[0x8];
b4ff3a36 7555 u8 reserved_at_58[0x8];
e281682b
SM		 7556
7557 u8 retransmission_active[0x8];
7558 u8 fec_mode_active[0x18];
7559
b4ff3a36 7560 u8 reserved_at_80[0x20];
e281682b
SM		 7561};
7562
7563struct mlx5_ifc_ppcnt_reg_bits {
7564 u8 swid[0x8];
7565 u8 local_port[0x8];
7566 u8 pnat[0x2];
b4ff3a36 7567 u8 reserved_at_12[0x8];
e281682b
SM		 7568 u8 grp[0x6];
7569
7570 u8 clr[0x1];
b4ff3a36 7571 u8 reserved_at_21[0x1c];
e281682b
SM		 7572 u8 prio_tc[0x3];
7573
7574 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
7575};
7576
8ed1a630
GP		 7577struct mlx5_ifc_mpcnt_reg_bits {
7578 u8 reserved_at_0[0x8];
7579 u8 pcie_index[0x8];
7580 u8 reserved_at_10[0xa];
7581 u8 grp[0x6];
7582
7583 u8 clr[0x1];
7584 u8 reserved_at_21[0x1f];
7585
7586 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
7587};
7588
e281682b 7589struct mlx5_ifc_ppad_reg_bits {
b4ff3a36 7590 u8 reserved_at_0[0x3];
e281682b 7591 u8 single_mac[0x1];
b4ff3a36 7592 u8 reserved_at_4[0x4];
e281682b
SM		 7593 u8 local_port[0x8];
7594 u8 mac_47_32[0x10];
7595
7596 u8 mac_31_0[0x20];
7597
b4ff3a36 7598 u8 reserved_at_40[0x40];
e281682b
SM		 7599};
7600
7601struct mlx5_ifc_pmtu_reg_bits {
b4ff3a36 7602 u8 reserved_at_0[0x8];
e281682b 7603 u8 local_port[0x8];
b4ff3a36 7604 u8 reserved_at_10[0x10];
e281682b
SM		 7605
7606 u8 max_mtu[0x10];
b4ff3a36 7607 u8 reserved_at_30[0x10];
e281682b
SM		 7608
7609 u8 admin_mtu[0x10];
b4ff3a36 7610 u8 reserved_at_50[0x10];
e281682b
SM		 7611
7612 u8 oper_mtu[0x10];
b4ff3a36 7613 u8 reserved_at_70[0x10];
e281682b
SM		 7614};
7615
7616struct mlx5_ifc_pmpr_reg_bits {
b4ff3a36 7617 u8 reserved_at_0[0x8];
e281682b 7618 u8 module[0x8];
b4ff3a36 7619 u8 reserved_at_10[0x10];
e281682b 7620
b4ff3a36 7621 u8 reserved_at_20[0x18];
e281682b
SM		 7622 u8 attenuation_5g[0x8];
7623
b4ff3a36 7624 u8 reserved_at_40[0x18];
e281682b
SM		 7625 u8 attenuation_7g[0x8];
7626
b4ff3a36 7627 u8 reserved_at_60[0x18];
e281682b
SM		 7628 u8 attenuation_12g[0x8];
7629};
7630
7631struct mlx5_ifc_pmpe_reg_bits {
b4ff3a36 7632 u8 reserved_at_0[0x8];
e281682b 7633 u8 module[0x8];
b4ff3a36 7634 u8 reserved_at_10[0xc];
e281682b
SM		 7635 u8 module_status[0x4];
7636
b4ff3a36 7637 u8 reserved_at_20[0x60];
e281682b
SM		 7638};
7639
7640struct mlx5_ifc_pmpc_reg_bits {
7641 u8 module_state_updated[32][0x8];
7642};
7643
7644struct mlx5_ifc_pmlpn_reg_bits {
b4ff3a36 7645 u8 reserved_at_0[0x4];
e281682b
SM		 7646 u8 mlpn_status[0x4];
7647 u8 local_port[0x8];
b4ff3a36 7648 u8 reserved_at_10[0x10];
e281682b
SM		 7649
7650 u8 e[0x1];
b4ff3a36 7651 u8 reserved_at_21[0x1f];
e281682b
SM		 7652};
7653
7654struct mlx5_ifc_pmlp_reg_bits {
7655 u8 rxtx[0x1];
b4ff3a36 7656 u8 reserved_at_1[0x7];
e281682b 7657 u8 local_port[0x8];
b4ff3a36 7658 u8 reserved_at_10[0x8];
e281682b
SM		 7659 u8 width[0x8];
7660
7661 u8 lane0_module_mapping[0x20];
7662
7663 u8 lane1_module_mapping[0x20];
7664
7665 u8 lane2_module_mapping[0x20];
7666
7667 u8 lane3_module_mapping[0x20];
7668
b4ff3a36 7669 u8 reserved_at_a0[0x160];
e281682b
SM		 7670};
7671
7672struct mlx5_ifc_pmaos_reg_bits {
b4ff3a36 7673 u8 reserved_at_0[0x8];
e281682b 7674 u8 module[0x8];
b4ff3a36 7675 u8 reserved_at_10[0x4];
e281682b 7676 u8 admin_status[0x4];
b4ff3a36 7677 u8 reserved_at_18[0x4];
e281682b
SM		 7678 u8 oper_status[0x4];
7679
7680 u8 ase[0x1];
7681 u8 ee[0x1];
b4ff3a36 7682 u8 reserved_at_22[0x1c];
e281682b
SM		 7683 u8 e[0x2];
7684
b4ff3a36 7685 u8 reserved_at_40[0x40];
e281682b
SM		 7686};
7687
7688struct mlx5_ifc_plpc_reg_bits {
b4ff3a36 7689 u8 reserved_at_0[0x4];
e281682b 7690 u8 profile_id[0xc];
b4ff3a36 7691 u8 reserved_at_10[0x4];
e281682b 7692 u8 proto_mask[0x4];
b4ff3a36 7693 u8 reserved_at_18[0x8];
e281682b 7694
b4ff3a36 7695 u8 reserved_at_20[0x10];
e281682b
SM		 7696 u8 lane_speed[0x10];
7697
b4ff3a36 7698 u8 reserved_at_40[0x17];
e281682b
SM		 7699 u8 lpbf[0x1];
7700 u8 fec_mode_policy[0x8];
7701
7702 u8 retransmission_capability[0x8];
7703 u8 fec_mode_capability[0x18];
7704
7705 u8 retransmission_support_admin[0x8];
7706 u8 fec_mode_support_admin[0x18];
7707
7708 u8 retransmission_request_admin[0x8];
7709 u8 fec_mode_request_admin[0x18];
7710
b4ff3a36 7711 u8 reserved_at_c0[0x80];
e281682b
SM		 7712};
7713
7714struct mlx5_ifc_plib_reg_bits {
b4ff3a36 7715 u8 reserved_at_0[0x8];
e281682b 7716 u8 local_port[0x8];
b4ff3a36 7717 u8 reserved_at_10[0x8];
e281682b
SM		 7718 u8 ib_port[0x8];
7719
b4ff3a36 7720 u8 reserved_at_20[0x60];
e281682b
SM		 7721};
7722
7723struct mlx5_ifc_plbf_reg_bits {
b4ff3a36 7724 u8 reserved_at_0[0x8];
e281682b 7725 u8 local_port[0x8];
b4ff3a36 7726 u8 reserved_at_10[0xd];
e281682b
SM		 7727 u8 lbf_mode[0x3];
7728
b4ff3a36 7729 u8 reserved_at_20[0x20];
e281682b
SM		 7730};
7731
7732struct mlx5_ifc_pipg_reg_bits {
b4ff3a36 7733 u8 reserved_at_0[0x8];
e281682b 7734 u8 local_port[0x8];
b4ff3a36 7735 u8 reserved_at_10[0x10];
e281682b
SM		 7736
7737 u8 dic[0x1];
b4ff3a36 7738 u8 reserved_at_21[0x19];
e281682b 7739 u8 ipg[0x4];
b4ff3a36 7740 u8 reserved_at_3e[0x2];
e281682b
SM		 7741};
7742
7743struct mlx5_ifc_pifr_reg_bits {
b4ff3a36 7744 u8 reserved_at_0[0x8];
e281682b 7745 u8 local_port[0x8];
b4ff3a36 7746 u8 reserved_at_10[0x10];
e281682b 7747
b4ff3a36 7748 u8 reserved_at_20[0xe0];
e281682b
SM		 7749
7750 u8 port_filter[8][0x20];
7751
7752 u8 port_filter_update_en[8][0x20];
7753};
7754
7755struct mlx5_ifc_pfcc_reg_bits {
b4ff3a36 7756 u8 reserved_at_0[0x8];
e281682b 7757 u8 local_port[0x8];
b4ff3a36 7758 u8 reserved_at_10[0x10];
e281682b
SM		 7759
7760 u8 ppan[0x4];
b4ff3a36 7761 u8 reserved_at_24[0x4];
e281682b 7762 u8 prio_mask_tx[0x8];
b4ff3a36 7763 u8 reserved_at_30[0x8];
e281682b
SM		 7764 u8 prio_mask_rx[0x8];
7765
7766 u8 pptx[0x1];
7767 u8 aptx[0x1];
b4ff3a36 7768 u8 reserved_at_42[0x6];
e281682b 7769 u8 pfctx[0x8];
b4ff3a36 7770 u8 reserved_at_50[0x10];
e281682b
SM		 7771
7772 u8 pprx[0x1];
7773 u8 aprx[0x1];
b4ff3a36 7774 u8 reserved_at_62[0x6];
e281682b 7775 u8 pfcrx[0x8];
b4ff3a36 7776 u8 reserved_at_70[0x10];
e281682b 7777
b4ff3a36 7778 u8 reserved_at_80[0x80];
e281682b
SM		 7779};
7780
7781struct mlx5_ifc_pelc_reg_bits {
7782 u8 op[0x4];
b4ff3a36 7783 u8 reserved_at_4[0x4];
e281682b 7784 u8 local_port[0x8];
b4ff3a36 7785 u8 reserved_at_10[0x10];
e281682b
SM		 7786
7787 u8 op_admin[0x8];
7788 u8 op_capability[0x8];
7789 u8 op_request[0x8];
7790 u8 op_active[0x8];
7791
7792 u8 admin[0x40];
7793
7794 u8 capability[0x40];
7795
7796 u8 request[0x40];
7797
7798 u8 active[0x40];
7799
b4ff3a36 7800 u8 reserved_at_140[0x80];
e281682b
SM		 7801};
7802
7803struct mlx5_ifc_peir_reg_bits {
b4ff3a36 7804 u8 reserved_at_0[0x8];
e281682b 7805 u8 local_port[0x8];
b4ff3a36 7806 u8 reserved_at_10[0x10];
e281682b 7807
b4ff3a36 7808 u8 reserved_at_20[0xc];
e281682b 7809 u8 error_count[0x4];
b4ff3a36 7810 u8 reserved_at_30[0x10];
e281682b 7811
b4ff3a36 7812 u8 reserved_at_40[0xc];
e281682b 7813 u8 lane[0x4];
b4ff3a36 7814 u8 reserved_at_50[0x8];
e281682b
SM		 7815 u8 error_type[0x8];
7816};
7817
cfdcbcea 7818struct mlx5_ifc_pcam_enhanced_features_bits {
2dba0797 7819 u8 reserved_at_0[0x7b];
cfdcbcea 7820
2dba0797 7821 u8 rx_buffer_fullness_counters[0x1];
5b4793f8
EBE		 7822 u8 ptys_connector_type[0x1];
7823 u8 reserved_at_7d[0x1];
cfdcbcea
GP		 7824 u8 ppcnt_discard_group[0x1];
7825 u8 ppcnt_statistical_group[0x1];
7826};
7827
7828struct mlx5_ifc_pcam_reg_bits {
7829 u8 reserved_at_0[0x8];
7830 u8 feature_group[0x8];
7831 u8 reserved_at_10[0x8];
7832 u8 access_reg_group[0x8];
7833
7834 u8 reserved_at_20[0x20];
7835
7836 union {
7837 u8 reserved_at_0[0x80];
7838 } port_access_reg_cap_mask;
7839
7840 u8 reserved_at_c0[0x80];
7841
7842 union {
7843 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
7844 u8 reserved_at_0[0x80];
7845 } feature_cap_mask;
7846
7847 u8 reserved_at_1c0[0xc0];
7848};
7849
7850struct mlx5_ifc_mcam_enhanced_features_bits {
5405fa26
GP		 7851 u8 reserved_at_0[0x7b];
7852 u8 pcie_outbound_stalled[0x1];
efae7f78 7853 u8 tx_overflow_buffer_pkt[0x1];
fa367688
EE		 7854 u8 mtpps_enh_out_per_adj[0x1];
7855 u8 mtpps_fs[0x1];
cfdcbcea
GP		 7856 u8 pcie_performance_group[0x1];
7857};
7858
0ab87743
OG		 7859struct mlx5_ifc_mcam_access_reg_bits {
7860 u8 reserved_at_0[0x1c];
7861 u8 mcda[0x1];
7862 u8 mcc[0x1];
7863 u8 mcqi[0x1];
7864 u8 reserved_at_1f[0x1];
7865
7866 u8 regs_95_to_64[0x20];
7867 u8 regs_63_to_32[0x20];
7868 u8 regs_31_to_0[0x20];
7869};
7870
cfdcbcea
GP		 7871struct mlx5_ifc_mcam_reg_bits {
7872 u8 reserved_at_0[0x8];
7873 u8 feature_group[0x8];
7874 u8 reserved_at_10[0x8];
7875 u8 access_reg_group[0x8];
7876
7877 u8 reserved_at_20[0x20];
7878
7879 union {
0ab87743 7880 struct mlx5_ifc_mcam_access_reg_bits access_regs;
cfdcbcea
GP		 7881 u8 reserved_at_0[0x80];
7882 } mng_access_reg_cap_mask;
7883
7884 u8 reserved_at_c0[0x80];
7885
7886 union {
7887 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
7888 u8 reserved_at_0[0x80];
7889 } mng_feature_cap_mask;
7890
7891 u8 reserved_at_1c0[0x80];
7892};
7893
c02762eb
HN		 7894struct mlx5_ifc_qcam_access_reg_cap_mask {
7895 u8 qcam_access_reg_cap_mask_127_to_20[0x6C];
7896 u8 qpdpm[0x1];
7897 u8 qcam_access_reg_cap_mask_18_to_4[0x0F];
7898 u8 qdpm[0x1];
7899 u8 qpts[0x1];
7900 u8 qcap[0x1];
7901 u8 qcam_access_reg_cap_mask_0[0x1];
7902};
7903
7904struct mlx5_ifc_qcam_qos_feature_cap_mask {
7905 u8 qcam_qos_feature_cap_mask_127_to_1[0x7F];
7906 u8 qpts_trust_both[0x1];
7907};
7908
7909struct mlx5_ifc_qcam_reg_bits {
7910 u8 reserved_at_0[0x8];
7911 u8 feature_group[0x8];
7912 u8 reserved_at_10[0x8];
7913 u8 access_reg_group[0x8];
7914 u8 reserved_at_20[0x20];
7915
7916 union {
7917 struct mlx5_ifc_qcam_access_reg_cap_mask reg_cap;
7918 u8 reserved_at_0[0x80];
7919 } qos_access_reg_cap_mask;
7920
7921 u8 reserved_at_c0[0x80];
7922
7923 union {
7924 struct mlx5_ifc_qcam_qos_feature_cap_mask feature_cap;
7925 u8 reserved_at_0[0x80];
7926 } qos_feature_cap_mask;
7927
7928 u8 reserved_at_1c0[0x80];
7929};
7930
e281682b 7931struct mlx5_ifc_pcap_reg_bits {
b4ff3a36 7932 u8 reserved_at_0[0x8];
e281682b 7933 u8 local_port[0x8];
b4ff3a36 7934 u8 reserved_at_10[0x10];
e281682b
SM		 7935
7936 u8 port_capability_mask[4][0x20];
7937};
7938
7939struct mlx5_ifc_paos_reg_bits {
7940 u8 swid[0x8];
7941 u8 local_port[0x8];
b4ff3a36 7942 u8 reserved_at_10[0x4];
e281682b 7943 u8 admin_status[0x4];
b4ff3a36 7944 u8 reserved_at_18[0x4];
e281682b
SM		 7945 u8 oper_status[0x4];
7946
7947 u8 ase[0x1];
7948 u8 ee[0x1];
b4ff3a36 7949 u8 reserved_at_22[0x1c];
e281682b
SM		 7950 u8 e[0x2];
7951
b4ff3a36 7952 u8 reserved_at_40[0x40];
e281682b
SM		 7953};
7954
7955struct mlx5_ifc_pamp_reg_bits {
b4ff3a36 7956 u8 reserved_at_0[0x8];
e281682b 7957 u8 opamp_group[0x8];
b4ff3a36 7958 u8 reserved_at_10[0xc];
e281682b
SM		 7959 u8 opamp_group_type[0x4];
7960
7961 u8 start_index[0x10];
b4ff3a36 7962 u8 reserved_at_30[0x4];
e281682b
SM		 7963 u8 num_of_indices[0xc];
7964
7965 u8 index_data[18][0x10];
7966};
7967
7d5e1423
SM		 7968struct mlx5_ifc_pcmr_reg_bits {
7969 u8 reserved_at_0[0x8];
7970 u8 local_port[0x8];
7971 u8 reserved_at_10[0x2e];
7972 u8 fcs_cap[0x1];
7973 u8 reserved_at_3f[0x1f];
7974 u8 fcs_chk[0x1];
7975 u8 reserved_at_5f[0x1];
7976};
7977
e281682b 7978struct mlx5_ifc_lane_2_module_mapping_bits {
b4ff3a36 7979 u8 reserved_at_0[0x6];
e281682b 7980 u8 rx_lane[0x2];
b4ff3a36 7981 u8 reserved_at_8[0x6];
e281682b 7982 u8 tx_lane[0x2];
b4ff3a36 7983 u8 reserved_at_10[0x8];
e281682b
SM		 7984 u8 module[0x8];
7985};
7986
7987struct mlx5_ifc_bufferx_reg_bits {
b4ff3a36 7988 u8 reserved_at_0[0x6];
e281682b
SM		 7989 u8 lossy[0x1];
7990 u8 epsb[0x1];
b4ff3a36 7991 u8 reserved_at_8[0xc];
e281682b
SM		 7992 u8 size[0xc];
7993
7994 u8 xoff_threshold[0x10];
7995 u8 xon_threshold[0x10];
7996};
7997
7998struct mlx5_ifc_set_node_in_bits {
7999 u8 node_description[64][0x8];
8000};
8001
8002struct mlx5_ifc_register_power_settings_bits {
b4ff3a36 8003 u8 reserved_at_0[0x18];
e281682b
SM		 8004 u8 power_settings_level[0x8];
8005
b4ff3a36 8006 u8 reserved_at_20[0x60];
e281682b
SM		 8007};
8008
8009struct mlx5_ifc_register_host_endianness_bits {
8010 u8 he[0x1];
b4ff3a36 8011 u8 reserved_at_1[0x1f];
e281682b 8012
b4ff3a36 8013 u8 reserved_at_20[0x60];
e281682b
SM		 8014};
8015
8016struct mlx5_ifc_umr_pointer_desc_argument_bits {
b4ff3a36 8017 u8 reserved_at_0[0x20];
e281682b
SM		 8018
8019 u8 mkey[0x20];
8020
8021 u8 addressh_63_32[0x20];
8022
8023 u8 addressl_31_0[0x20];
8024};
8025
8026struct mlx5_ifc_ud_adrs_vector_bits {
8027 u8 dc_key[0x40];
8028
8029 u8 ext[0x1];
b4ff3a36 8030 u8 reserved_at_41[0x7];
e281682b
SM		 8031 u8 destination_qp_dct[0x18];
8032
8033 u8 static_rate[0x4];
8034 u8 sl_eth_prio[0x4];
8035 u8 fl[0x1];
8036 u8 mlid[0x7];
8037 u8 rlid_udp_sport[0x10];
8038
b4ff3a36 8039 u8 reserved_at_80[0x20];
e281682b
SM		 8040
8041 u8 rmac_47_16[0x20];
8042
8043 u8 rmac_15_0[0x10];
8044 u8 tclass[0x8];
8045 u8 hop_limit[0x8];
8046
b4ff3a36 8047 u8 reserved_at_e0[0x1];
e281682b 8048 u8 grh[0x1];
b4ff3a36 8049 u8 reserved_at_e2[0x2];
e281682b
SM		 8050 u8 src_addr_index[0x8];
8051 u8 flow_label[0x14];
8052
8053 u8 rgid_rip[16][0x8];
8054};
8055
8056struct mlx5_ifc_pages_req_event_bits {
b4ff3a36 8057 u8 reserved_at_0[0x10];
e281682b
SM		 8058 u8 function_id[0x10];
8059
8060 u8 num_pages[0x20];
8061
b4ff3a36 8062 u8 reserved_at_40[0xa0];
e281682b
SM		 8063};
8064
8065struct mlx5_ifc_eqe_bits {
b4ff3a36 8066 u8 reserved_at_0[0x8];
e281682b 8067 u8 event_type[0x8];
b4ff3a36 8068 u8 reserved_at_10[0x8];
e281682b
SM		 8069 u8 event_sub_type[0x8];
8070
b4ff3a36 8071 u8 reserved_at_20[0xe0];
e281682b
SM		 8072
8073 union mlx5_ifc_event_auto_bits event_data;
8074
b4ff3a36 8075 u8 reserved_at_1e0[0x10];
e281682b 8076 u8 signature[0x8];
b4ff3a36 8077 u8 reserved_at_1f8[0x7];
e281682b
SM		 8078 u8 owner[0x1];
8079};
8080
8081enum {
8082 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
8083};
8084
8085struct mlx5_ifc_cmd_queue_entry_bits {
8086 u8 type[0x8];
b4ff3a36 8087 u8 reserved_at_8[0x18];
e281682b
SM		 8088
8089 u8 input_length[0x20];
8090
8091 u8 input_mailbox_pointer_63_32[0x20];
8092
8093 u8 input_mailbox_pointer_31_9[0x17];
b4ff3a36 8094 u8 reserved_at_77[0x9];
e281682b
SM		 8095
8096 u8 command_input_inline_data[16][0x8];
8097
8098 u8 command_output_inline_data[16][0x8];
8099
8100 u8 output_mailbox_pointer_63_32[0x20];
8101
8102 u8 output_mailbox_pointer_31_9[0x17];
b4ff3a36 8103 u8 reserved_at_1b7[0x9];
e281682b
SM		 8104
8105 u8 output_length[0x20];
8106
8107 u8 token[0x8];
8108 u8 signature[0x8];
b4ff3a36 8109 u8 reserved_at_1f0[0x8];
e281682b
SM		 8110 u8 status[0x7];
8111 u8 ownership[0x1];
8112};
8113
8114struct mlx5_ifc_cmd_out_bits {
8115 u8 status[0x8];
b4ff3a36 8116 u8 reserved_at_8[0x18];
e281682b
SM		 8117
8118 u8 syndrome[0x20];
8119
8120 u8 command_output[0x20];
8121};
8122
8123struct mlx5_ifc_cmd_in_bits {
8124 u8 opcode[0x10];
b4ff3a36 8125 u8 reserved_at_10[0x10];
e281682b 8126
b4ff3a36 8127 u8 reserved_at_20[0x10];
e281682b
SM		 8128 u8 op_mod[0x10];
8129
8130 u8 command[0][0x20];
8131};
8132
8133struct mlx5_ifc_cmd_if_box_bits {
8134 u8 mailbox_data[512][0x8];
8135
b4ff3a36 8136 u8 reserved_at_1000[0x180];
e281682b
SM		 8137
8138 u8 next_pointer_63_32[0x20];
8139
8140 u8 next_pointer_31_10[0x16];
b4ff3a36 8141 u8 reserved_at_11b6[0xa];
e281682b
SM		 8142
8143 u8 block_number[0x20];
8144
b4ff3a36 8145 u8 reserved_at_11e0[0x8];
e281682b
SM		 8146 u8 token[0x8];
8147 u8 ctrl_signature[0x8];
8148 u8 signature[0x8];
8149};
8150
8151struct mlx5_ifc_mtt_bits {
8152 u8 ptag_63_32[0x20];
8153
8154 u8 ptag_31_8[0x18];
b4ff3a36 8155 u8 reserved_at_38[0x6];
e281682b
SM		 8156 u8 wr_en[0x1];
8157 u8 rd_en[0x1];
8158};
8159
928cfe87
TT		 8160struct mlx5_ifc_query_wol_rol_out_bits {
8161 u8 status[0x8];
8162 u8 reserved_at_8[0x18];
8163
8164 u8 syndrome[0x20];
8165
8166 u8 reserved_at_40[0x10];
8167 u8 rol_mode[0x8];
8168 u8 wol_mode[0x8];
8169
8170 u8 reserved_at_60[0x20];
8171};
8172
8173struct mlx5_ifc_query_wol_rol_in_bits {
8174 u8 opcode[0x10];
8175 u8 reserved_at_10[0x10];
8176
8177 u8 reserved_at_20[0x10];
8178 u8 op_mod[0x10];
8179
8180 u8 reserved_at_40[0x40];
8181};
8182
8183struct mlx5_ifc_set_wol_rol_out_bits {
8184 u8 status[0x8];
8185 u8 reserved_at_8[0x18];
8186
8187 u8 syndrome[0x20];
8188
8189 u8 reserved_at_40[0x40];
8190};
8191
8192struct mlx5_ifc_set_wol_rol_in_bits {
8193 u8 opcode[0x10];
8194 u8 reserved_at_10[0x10];
8195
8196 u8 reserved_at_20[0x10];
8197 u8 op_mod[0x10];
8198
8199 u8 rol_mode_valid[0x1];
8200 u8 wol_mode_valid[0x1];
8201 u8 reserved_at_42[0xe];
8202 u8 rol_mode[0x8];
8203 u8 wol_mode[0x8];
8204
8205 u8 reserved_at_60[0x20];
8206};
8207
e281682b
SM		 8208enum {
8209 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
8210 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
8211 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
8212};
8213
8214enum {
8215 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
8216 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
8217 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
8218};
8219
8220enum {
8221 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
8222 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
8223 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
8224 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
8225 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
8226 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
8227 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
8228 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
8229 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
8230 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
8231 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
8232};
8233
8234struct mlx5_ifc_initial_seg_bits {
8235 u8 fw_rev_minor[0x10];
8236 u8 fw_rev_major[0x10];
8237
8238 u8 cmd_interface_rev[0x10];
8239 u8 fw_rev_subminor[0x10];
8240
b4ff3a36 8241 u8 reserved_at_40[0x40];
e281682b
SM		 8242
8243 u8 cmdq_phy_addr_63_32[0x20];
8244
8245 u8 cmdq_phy_addr_31_12[0x14];
b4ff3a36 8246 u8 reserved_at_b4[0x2];
e281682b
SM		 8247 u8 nic_interface[0x2];
8248 u8 log_cmdq_size[0x4];
8249 u8 log_cmdq_stride[0x4];
8250
8251 u8 command_doorbell_vector[0x20];
8252
b4ff3a36 8253 u8 reserved_at_e0[0xf00];
e281682b
SM		 8254
8255 u8 initializing[0x1];
b4ff3a36 8256 u8 reserved_at_fe1[0x4];
e281682b 8257 u8 nic_interface_supported[0x3];
b4ff3a36 8258 u8 reserved_at_fe8[0x18];
e281682b
SM		 8259
8260 struct mlx5_ifc_health_buffer_bits health_buffer;
8261
8262 u8 no_dram_nic_offset[0x20];
8263
b4ff3a36 8264 u8 reserved_at_1220[0x6e40];
e281682b 8265
b4ff3a36 8266 u8 reserved_at_8060[0x1f];
e281682b
SM		 8267 u8 clear_int[0x1];
8268
8269 u8 health_syndrome[0x8];
8270 u8 health_counter[0x18];
8271
b4ff3a36 8272 u8 reserved_at_80a0[0x17fc0];
e281682b
SM		 8273};
8274
f9a1ef72
EE		 8275struct mlx5_ifc_mtpps_reg_bits {
8276 u8 reserved_at_0[0xc];
8277 u8 cap_number_of_pps_pins[0x4];
8278 u8 reserved_at_10[0x4];
8279 u8 cap_max_num_of_pps_in_pins[0x4];
8280 u8 reserved_at_18[0x4];
8281 u8 cap_max_num_of_pps_out_pins[0x4];
8282
8283 u8 reserved_at_20[0x24];
8284 u8 cap_pin_3_mode[0x4];
8285 u8 reserved_at_48[0x4];
8286 u8 cap_pin_2_mode[0x4];
8287 u8 reserved_at_50[0x4];
8288 u8 cap_pin_1_mode[0x4];
8289 u8 reserved_at_58[0x4];
8290 u8 cap_pin_0_mode[0x4];
8291
8292 u8 reserved_at_60[0x4];
8293 u8 cap_pin_7_mode[0x4];
8294 u8 reserved_at_68[0x4];
8295 u8 cap_pin_6_mode[0x4];
8296 u8 reserved_at_70[0x4];
8297 u8 cap_pin_5_mode[0x4];
8298 u8 reserved_at_78[0x4];
8299 u8 cap_pin_4_mode[0x4];
8300
fa367688
EE		 8301 u8 field_select[0x20];
8302 u8 reserved_at_a0[0x60];
f9a1ef72
EE		 8303
8304 u8 enable[0x1];
8305 u8 reserved_at_101[0xb];
8306 u8 pattern[0x4];
8307 u8 reserved_at_110[0x4];
8308 u8 pin_mode[0x4];
8309 u8 pin[0x8];
8310
8311 u8 reserved_at_120[0x20];
8312
8313 u8 time_stamp[0x40];
8314
8315 u8 out_pulse_duration[0x10];
8316 u8 out_periodic_adjustment[0x10];
fa367688 8317 u8 enhanced_out_periodic_adjustment[0x20];
f9a1ef72 8318
fa367688 8319 u8 reserved_at_1c0[0x20];
f9a1ef72
EE		 8320};
8321
8322struct mlx5_ifc_mtppse_reg_bits {
8323 u8 reserved_at_0[0x18];
8324 u8 pin[0x8];
8325 u8 event_arm[0x1];
8326 u8 reserved_at_21[0x1b];
8327 u8 event_generation_mode[0x4];
8328 u8 reserved_at_40[0x40];
8329};
8330
47176289
OG		 8331struct mlx5_ifc_mcqi_cap_bits {
8332 u8 supported_info_bitmask[0x20];
8333
8334 u8 component_size[0x20];
8335
8336 u8 max_component_size[0x20];
8337
8338 u8 log_mcda_word_size[0x4];
8339 u8 reserved_at_64[0xc];
8340 u8 mcda_max_write_size[0x10];
8341
8342 u8 rd_en[0x1];
8343 u8 reserved_at_81[0x1];
8344 u8 match_chip_id[0x1];
8345 u8 match_psid[0x1];
8346 u8 check_user_timestamp[0x1];
8347 u8 match_base_guid_mac[0x1];
8348 u8 reserved_at_86[0x1a];
8349};
8350
8351struct mlx5_ifc_mcqi_reg_bits {
8352 u8 read_pending_component[0x1];
8353 u8 reserved_at_1[0xf];
8354 u8 component_index[0x10];
8355
8356 u8 reserved_at_20[0x20];
8357
8358 u8 reserved_at_40[0x1b];
8359 u8 info_type[0x5];
8360
8361 u8 info_size[0x20];
8362
8363 u8 offset[0x20];
8364
8365 u8 reserved_at_a0[0x10];
8366 u8 data_size[0x10];
8367
8368 u8 data[0][0x20];
8369};
8370
8371struct mlx5_ifc_mcc_reg_bits {
8372 u8 reserved_at_0[0x4];
8373 u8 time_elapsed_since_last_cmd[0xc];
8374 u8 reserved_at_10[0x8];
8375 u8 instruction[0x8];
8376
8377 u8 reserved_at_20[0x10];
8378 u8 component_index[0x10];
8379
8380 u8 reserved_at_40[0x8];
8381 u8 update_handle[0x18];
8382
8383 u8 handle_owner_type[0x4];
8384 u8 handle_owner_host_id[0x4];
8385 u8 reserved_at_68[0x1];
8386 u8 control_progress[0x7];
8387 u8 error_code[0x8];
8388 u8 reserved_at_78[0x4];
8389 u8 control_state[0x4];
8390
8391 u8 component_size[0x20];
8392
8393 u8 reserved_at_a0[0x60];
8394};
8395
8396struct mlx5_ifc_mcda_reg_bits {
8397 u8 reserved_at_0[0x8];
8398 u8 update_handle[0x18];
8399
8400 u8 offset[0x20];
8401
8402 u8 reserved_at_40[0x10];
8403 u8 size[0x10];
8404
8405 u8 reserved_at_60[0x20];
8406
8407 u8 data[0][0x20];
8408};
8409
e281682b
SM		 8410union mlx5_ifc_ports_control_registers_document_bits {
8411 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
8412 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
8413 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
8414 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
8415 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
8416 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
8417 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
8418 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
8419 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
8420 struct mlx5_ifc_pamp_reg_bits pamp_reg;
8421 struct mlx5_ifc_paos_reg_bits paos_reg;
8422 struct mlx5_ifc_pcap_reg_bits pcap_reg;
8423 struct mlx5_ifc_peir_reg_bits peir_reg;
8424 struct mlx5_ifc_pelc_reg_bits pelc_reg;
8425 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
1c64bf6f 8426 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b
SM		 8427 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
8428 struct mlx5_ifc_pifr_reg_bits pifr_reg;
8429 struct mlx5_ifc_pipg_reg_bits pipg_reg;
8430 struct mlx5_ifc_plbf_reg_bits plbf_reg;
8431 struct mlx5_ifc_plib_reg_bits plib_reg;
8432 struct mlx5_ifc_plpc_reg_bits plpc_reg;
8433 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
8434 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
8435 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
8436 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
8437 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
8438 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
8439 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
8440 struct mlx5_ifc_ppad_reg_bits ppad_reg;
8441 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
8ed1a630 8442 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
e281682b
SM		 8443 struct mlx5_ifc_pplm_reg_bits pplm_reg;
8444 struct mlx5_ifc_pplr_reg_bits pplr_reg;
8445 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
8446 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
8447 struct mlx5_ifc_pspa_reg_bits pspa_reg;
8448 struct mlx5_ifc_ptas_reg_bits ptas_reg;
8449 struct mlx5_ifc_ptys_reg_bits ptys_reg;
7d5e1423 8450 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
e281682b
SM		 8451 struct mlx5_ifc_pude_reg_bits pude_reg;
8452 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
8453 struct mlx5_ifc_slrg_reg_bits slrg_reg;
8454 struct mlx5_ifc_sltp_reg_bits sltp_reg;
f9a1ef72
EE		 8455 struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
8456 struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
a9956d35 8457 struct mlx5_ifc_fpga_access_reg_bits fpga_access_reg;
e29341fb
IT		 8458 struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits;
8459 struct mlx5_ifc_fpga_cap_bits fpga_cap_bits;
47176289
OG		 8460 struct mlx5_ifc_mcqi_reg_bits mcqi_reg;
8461 struct mlx5_ifc_mcc_reg_bits mcc_reg;
8462 struct mlx5_ifc_mcda_reg_bits mcda_reg;
b4ff3a36 8463 u8 reserved_at_0[0x60e0];
e281682b
SM		 8464};
8465
8466union mlx5_ifc_debug_enhancements_document_bits {
8467 struct mlx5_ifc_health_buffer_bits health_buffer;
b4ff3a36 8468 u8 reserved_at_0[0x200];
e281682b
SM		 8469};
8470
8471union mlx5_ifc_uplink_pci_interface_document_bits {
8472 struct mlx5_ifc_initial_seg_bits initial_seg;
b4ff3a36 8473 u8 reserved_at_0[0x20060];
b775516b
EC		 8474};
8475
2cc43b49
MG		 8476struct mlx5_ifc_set_flow_table_root_out_bits {
8477 u8 status[0x8];
b4ff3a36 8478 u8 reserved_at_8[0x18];
2cc43b49
MG		 8479
8480 u8 syndrome[0x20];
8481
b4ff3a36 8482 u8 reserved_at_40[0x40];
2cc43b49
MG		 8483};
8484
8485struct mlx5_ifc_set_flow_table_root_in_bits {
8486 u8 opcode[0x10];
b4ff3a36 8487 u8 reserved_at_10[0x10];
2cc43b49 8488
b4ff3a36 8489 u8 reserved_at_20[0x10];
2cc43b49
MG		 8490 u8 op_mod[0x10];
8491
7d5e1423
SM		 8492 u8 other_vport[0x1];
8493 u8 reserved_at_41[0xf];
8494 u8 vport_number[0x10];
8495
8496 u8 reserved_at_60[0x20];
2cc43b49
MG		 8497
8498 u8 table_type[0x8];
b4ff3a36 8499 u8 reserved_at_88[0x18];
2cc43b49 8500
b4ff3a36 8501 u8 reserved_at_a0[0x8];
2cc43b49
MG		 8502 u8 table_id[0x18];
8503
500a3d0d
ES		 8504 u8 reserved_at_c0[0x8];
8505 u8 underlay_qpn[0x18];
8506 u8 reserved_at_e0[0x120];
2cc43b49
MG		 8507};
8508
34a40e68 8509enum {
84df61eb
AH		 8510 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
8511 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
34a40e68
MG		 8512};
8513
8514struct mlx5_ifc_modify_flow_table_out_bits {
8515 u8 status[0x8];
b4ff3a36 8516 u8 reserved_at_8[0x18];
34a40e68
MG		 8517
8518 u8 syndrome[0x20];
8519
b4ff3a36 8520 u8 reserved_at_40[0x40];
34a40e68
MG		 8521};
8522
8523struct mlx5_ifc_modify_flow_table_in_bits {
8524 u8 opcode[0x10];
b4ff3a36 8525 u8 reserved_at_10[0x10];
34a40e68 8526
b4ff3a36 8527 u8 reserved_at_20[0x10];
34a40e68
MG		 8528 u8 op_mod[0x10];
8529
7d5e1423
SM		 8530 u8 other_vport[0x1];
8531 u8 reserved_at_41[0xf];
8532 u8 vport_number[0x10];
34a40e68 8533
b4ff3a36 8534 u8 reserved_at_60[0x10];
34a40e68
MG		 8535 u8 modify_field_select[0x10];
8536
8537 u8 table_type[0x8];
b4ff3a36 8538 u8 reserved_at_88[0x18];
34a40e68 8539
b4ff3a36 8540 u8 reserved_at_a0[0x8];
34a40e68
MG		 8541 u8 table_id[0x18];
8542
0c90e9c6 8543 struct mlx5_ifc_flow_table_context_bits flow_table_context;
34a40e68
MG		 8544};
8545
4f3961ee
SM		 8546struct mlx5_ifc_ets_tcn_config_reg_bits {
8547 u8 g[0x1];
8548 u8 b[0x1];
8549 u8 r[0x1];
8550 u8 reserved_at_3[0x9];
8551 u8 group[0x4];
8552 u8 reserved_at_10[0x9];
8553 u8 bw_allocation[0x7];
8554
8555 u8 reserved_at_20[0xc];
8556 u8 max_bw_units[0x4];
8557 u8 reserved_at_30[0x8];
8558 u8 max_bw_value[0x8];
8559};
8560
8561struct mlx5_ifc_ets_global_config_reg_bits {
8562 u8 reserved_at_0[0x2];
8563 u8 r[0x1];
8564 u8 reserved_at_3[0x1d];
8565
8566 u8 reserved_at_20[0xc];
8567 u8 max_bw_units[0x4];
8568 u8 reserved_at_30[0x8];
8569 u8 max_bw_value[0x8];
8570};
8571
8572struct mlx5_ifc_qetc_reg_bits {
8573 u8 reserved_at_0[0x8];
8574 u8 port_number[0x8];
8575 u8 reserved_at_10[0x30];
8576
8577 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
8578 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
8579};
8580
8581struct mlx5_ifc_qtct_reg_bits {
8582 u8 reserved_at_0[0x8];
8583 u8 port_number[0x8];
8584 u8 reserved_at_10[0xd];
8585 u8 prio[0x3];
8586
8587 u8 reserved_at_20[0x1d];
8588 u8 tclass[0x3];
8589};
8590
7d5e1423
SM		 8591struct mlx5_ifc_mcia_reg_bits {
8592 u8 l[0x1];
8593 u8 reserved_at_1[0x7];
8594 u8 module[0x8];
8595 u8 reserved_at_10[0x8];
8596 u8 status[0x8];
8597
8598 u8 i2c_device_address[0x8];
8599 u8 page_number[0x8];
8600 u8 device_address[0x10];
8601
8602 u8 reserved_at_40[0x10];
8603 u8 size[0x10];
8604
8605 u8 reserved_at_60[0x20];
8606
8607 u8 dword_0[0x20];
8608 u8 dword_1[0x20];
8609 u8 dword_2[0x20];
8610 u8 dword_3[0x20];
8611 u8 dword_4[0x20];
8612 u8 dword_5[0x20];
8613 u8 dword_6[0x20];
8614 u8 dword_7[0x20];
8615 u8 dword_8[0x20];
8616 u8 dword_9[0x20];
8617 u8 dword_10[0x20];
8618 u8 dword_11[0x20];
8619};
8620
7486216b
SM		 8621struct mlx5_ifc_dcbx_param_bits {
8622 u8 dcbx_cee_cap[0x1];
8623 u8 dcbx_ieee_cap[0x1];
8624 u8 dcbx_standby_cap[0x1];
8625 u8 reserved_at_0[0x5];
8626 u8 port_number[0x8];
8627 u8 reserved_at_10[0xa];
8628 u8 max_application_table_size[6];
8629 u8 reserved_at_20[0x15];
8630 u8 version_oper[0x3];
8631 u8 reserved_at_38[5];
8632 u8 version_admin[0x3];
8633 u8 willing_admin[0x1];
8634 u8 reserved_at_41[0x3];
8635 u8 pfc_cap_oper[0x4];
8636 u8 reserved_at_48[0x4];
8637 u8 pfc_cap_admin[0x4];
8638 u8 reserved_at_50[0x4];
8639 u8 num_of_tc_oper[0x4];
8640 u8 reserved_at_58[0x4];
8641 u8 num_of_tc_admin[0x4];
8642 u8 remote_willing[0x1];
8643 u8 reserved_at_61[3];
8644 u8 remote_pfc_cap[4];
8645 u8 reserved_at_68[0x14];
8646 u8 remote_num_of_tc[0x4];
8647 u8 reserved_at_80[0x18];
8648 u8 error[0x8];
8649 u8 reserved_at_a0[0x160];
8650};
84df61eb
AH		 8651
8652struct mlx5_ifc_lagc_bits {
8653 u8 reserved_at_0[0x1d];
8654 u8 lag_state[0x3];
8655
8656 u8 reserved_at_20[0x14];
8657 u8 tx_remap_affinity_2[0x4];
8658 u8 reserved_at_38[0x4];
8659 u8 tx_remap_affinity_1[0x4];
8660};
8661
8662struct mlx5_ifc_create_lag_out_bits {
8663 u8 status[0x8];
8664 u8 reserved_at_8[0x18];
8665
8666 u8 syndrome[0x20];
8667
8668 u8 reserved_at_40[0x40];
8669};
8670
8671struct mlx5_ifc_create_lag_in_bits {
8672 u8 opcode[0x10];
8673 u8 reserved_at_10[0x10];
8674
8675 u8 reserved_at_20[0x10];
8676 u8 op_mod[0x10];
8677
8678 struct mlx5_ifc_lagc_bits ctx;
8679};
8680
8681struct mlx5_ifc_modify_lag_out_bits {
8682 u8 status[0x8];
8683 u8 reserved_at_8[0x18];
8684
8685 u8 syndrome[0x20];
8686
8687 u8 reserved_at_40[0x40];
8688};
8689
8690struct mlx5_ifc_modify_lag_in_bits {
8691 u8 opcode[0x10];
8692 u8 reserved_at_10[0x10];
8693
8694 u8 reserved_at_20[0x10];
8695 u8 op_mod[0x10];
8696
8697 u8 reserved_at_40[0x20];
8698 u8 field_select[0x20];
8699
8700 struct mlx5_ifc_lagc_bits ctx;
8701};
8702
8703struct mlx5_ifc_query_lag_out_bits {
8704 u8 status[0x8];
8705 u8 reserved_at_8[0x18];
8706
8707 u8 syndrome[0x20];
8708
8709 u8 reserved_at_40[0x40];
8710
8711 struct mlx5_ifc_lagc_bits ctx;
8712};
8713
8714struct mlx5_ifc_query_lag_in_bits {
8715 u8 opcode[0x10];
8716 u8 reserved_at_10[0x10];
8717
8718 u8 reserved_at_20[0x10];
8719 u8 op_mod[0x10];
8720
8721 u8 reserved_at_40[0x40];
8722};
8723
8724struct mlx5_ifc_destroy_lag_out_bits {
8725 u8 status[0x8];
8726 u8 reserved_at_8[0x18];
8727
8728 u8 syndrome[0x20];
8729
8730 u8 reserved_at_40[0x40];
8731};
8732
8733struct mlx5_ifc_destroy_lag_in_bits {
8734 u8 opcode[0x10];
8735 u8 reserved_at_10[0x10];
8736
8737 u8 reserved_at_20[0x10];
8738 u8 op_mod[0x10];
8739
8740 u8 reserved_at_40[0x40];
8741};
8742
8743struct mlx5_ifc_create_vport_lag_out_bits {
8744 u8 status[0x8];
8745 u8 reserved_at_8[0x18];
8746
8747 u8 syndrome[0x20];
8748
8749 u8 reserved_at_40[0x40];
8750};
8751
8752struct mlx5_ifc_create_vport_lag_in_bits {
8753 u8 opcode[0x10];
8754 u8 reserved_at_10[0x10];
8755
8756 u8 reserved_at_20[0x10];
8757 u8 op_mod[0x10];
8758
8759 u8 reserved_at_40[0x40];
8760};
8761
8762struct mlx5_ifc_destroy_vport_lag_out_bits {
8763 u8 status[0x8];
8764 u8 reserved_at_8[0x18];
8765
8766 u8 syndrome[0x20];
8767
8768 u8 reserved_at_40[0x40];
8769};
8770
8771struct mlx5_ifc_destroy_vport_lag_in_bits {
8772 u8 opcode[0x10];
8773 u8 reserved_at_10[0x10];
8774
8775 u8 reserved_at_20[0x10];
8776 u8 op_mod[0x10];
8777
8778 u8 reserved_at_40[0x40];
8779};
8780
d29b796a 8781#endif /* MLX5_IFC_H */
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