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IB/mlx5: Add MR cache for large UMR regions
[mirror_ubuntu-artful-kernel.git] / include / linux / mlx5 / mlx5_ifc.h
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d29b796a 1/*
e281682b 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
d29b796a
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
e281682b 31*/
d29b796a
EC		 32#ifndef MLX5_IFC_H
33#define MLX5_IFC_H
34
e281682b
SM		 35enum {
36 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
37 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
38 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
39 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
40 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
41 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
42 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
43 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
44 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
45 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
46 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
47 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
48 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
49 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
50 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
51 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
52 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
53 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
54 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
55 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
56 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
57 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
58 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
59 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb
60};
61
62enum {
63 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
64 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
65 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
66 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
67};
68
f91e6d89
EBE		 69enum {
70 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
71 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
72};
73
d29b796a
EC		 74enum {
75 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
76 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
77 MLX5_CMD_OP_INIT_HCA = 0x102,
78 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
79 MLX5_CMD_OP_ENABLE_HCA = 0x104,
80 MLX5_CMD_OP_DISABLE_HCA = 0x105,
81 MLX5_CMD_OP_QUERY_PAGES = 0x107,
82 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
83 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
e281682b
SM		 84 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
85 MLX5_CMD_OP_SET_ISSI = 0x10b,
0dbc6fe0 86 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
d29b796a
EC		 87 MLX5_CMD_OP_CREATE_MKEY = 0x200,
88 MLX5_CMD_OP_QUERY_MKEY = 0x201,
89 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
90 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
91 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
92 MLX5_CMD_OP_CREATE_EQ = 0x301,
93 MLX5_CMD_OP_DESTROY_EQ = 0x302,
94 MLX5_CMD_OP_QUERY_EQ = 0x303,
95 MLX5_CMD_OP_GEN_EQE = 0x304,
96 MLX5_CMD_OP_CREATE_CQ = 0x400,
97 MLX5_CMD_OP_DESTROY_CQ = 0x401,
98 MLX5_CMD_OP_QUERY_CQ = 0x402,
99 MLX5_CMD_OP_MODIFY_CQ = 0x403,
100 MLX5_CMD_OP_CREATE_QP = 0x500,
101 MLX5_CMD_OP_DESTROY_QP = 0x501,
102 MLX5_CMD_OP_RST2INIT_QP = 0x502,
103 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
104 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
105 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
106 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
107 MLX5_CMD_OP_2ERR_QP = 0x507,
108 MLX5_CMD_OP_2RST_QP = 0x50a,
109 MLX5_CMD_OP_QUERY_QP = 0x50b,
e281682b 110 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
d29b796a
EC		 111 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
112 MLX5_CMD_OP_CREATE_PSV = 0x600,
113 MLX5_CMD_OP_DESTROY_PSV = 0x601,
114 MLX5_CMD_OP_CREATE_SRQ = 0x700,
115 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
116 MLX5_CMD_OP_QUERY_SRQ = 0x702,
117 MLX5_CMD_OP_ARM_RQ = 0x703,
e281682b
SM		 118 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
119 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
120 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
121 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
d29b796a
EC		 122 MLX5_CMD_OP_CREATE_DCT = 0x710,
123 MLX5_CMD_OP_DESTROY_DCT = 0x711,
124 MLX5_CMD_OP_DRAIN_DCT = 0x712,
125 MLX5_CMD_OP_QUERY_DCT = 0x713,
126 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
7486216b
SM		 127 MLX5_CMD_OP_CREATE_XRQ = 0x717,
128 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
129 MLX5_CMD_OP_QUERY_XRQ = 0x719,
130 MLX5_CMD_OP_ARM_XRQ = 0x71a,
d29b796a
EC		 131 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
132 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
133 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
134 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
135 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
136 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
e281682b 137 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
d29b796a 138 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
e281682b
SM		 139 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
140 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
141 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
142 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
d29b796a
EC		 143 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
144 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
145 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
146 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
7486216b
SM		 147 MLX5_CMD_OP_SET_RATE_LIMIT = 0x780,
148 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
813f8540
MHY		 149 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
150 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
151 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
152 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
153 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
154 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
d29b796a
EC		 155 MLX5_CMD_OP_ALLOC_PD = 0x800,
156 MLX5_CMD_OP_DEALLOC_PD = 0x801,
157 MLX5_CMD_OP_ALLOC_UAR = 0x802,
158 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
159 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
160 MLX5_CMD_OP_ACCESS_REG = 0x805,
161 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
20bb566b 162 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
d29b796a
EC		 163 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
164 MLX5_CMD_OP_MAD_IFC = 0x50d,
165 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
166 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
167 MLX5_CMD_OP_NOP = 0x80d,
168 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
169 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
e281682b
SM		 170 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
171 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
172 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
173 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
174 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
175 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
176 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
177 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
178 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
179 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
180 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
181 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
928cfe87
TT		 182 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
183 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
84df61eb
AH		 184 MLX5_CMD_OP_CREATE_LAG = 0x840,
185 MLX5_CMD_OP_MODIFY_LAG = 0x841,
186 MLX5_CMD_OP_QUERY_LAG = 0x842,
187 MLX5_CMD_OP_DESTROY_LAG = 0x843,
188 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
189 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
d29b796a
EC		 190 MLX5_CMD_OP_CREATE_TIR = 0x900,
191 MLX5_CMD_OP_MODIFY_TIR = 0x901,
192 MLX5_CMD_OP_DESTROY_TIR = 0x902,
193 MLX5_CMD_OP_QUERY_TIR = 0x903,
d29b796a
EC		 194 MLX5_CMD_OP_CREATE_SQ = 0x904,
195 MLX5_CMD_OP_MODIFY_SQ = 0x905,
196 MLX5_CMD_OP_DESTROY_SQ = 0x906,
197 MLX5_CMD_OP_QUERY_SQ = 0x907,
198 MLX5_CMD_OP_CREATE_RQ = 0x908,
199 MLX5_CMD_OP_MODIFY_RQ = 0x909,
200 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
201 MLX5_CMD_OP_QUERY_RQ = 0x90b,
202 MLX5_CMD_OP_CREATE_RMP = 0x90c,
203 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
204 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
205 MLX5_CMD_OP_QUERY_RMP = 0x90f,
e281682b
SM		 206 MLX5_CMD_OP_CREATE_TIS = 0x912,
207 MLX5_CMD_OP_MODIFY_TIS = 0x913,
208 MLX5_CMD_OP_DESTROY_TIS = 0x914,
209 MLX5_CMD_OP_QUERY_TIS = 0x915,
210 MLX5_CMD_OP_CREATE_RQT = 0x916,
211 MLX5_CMD_OP_MODIFY_RQT = 0x917,
212 MLX5_CMD_OP_DESTROY_RQT = 0x918,
213 MLX5_CMD_OP_QUERY_RQT = 0x919,
2cc43b49 214 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
e281682b
SM		 215 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
216 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
217 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
218 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
219 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
220 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
221 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
222 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
34a40e68 223 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
9dc0b289
AV		 224 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
225 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
226 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
86d56a1a 227 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
7adbde20
HHZ		 228 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d,
229 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e,
86d56a1a 230 MLX5_CMD_OP_MAX
e281682b
SM		 231};
232
233struct mlx5_ifc_flow_table_fields_supported_bits {
234 u8 outer_dmac[0x1];
235 u8 outer_smac[0x1];
236 u8 outer_ether_type[0x1];
b4ff3a36 237 u8 reserved_at_3[0x1];
e281682b
SM		 238 u8 outer_first_prio[0x1];
239 u8 outer_first_cfi[0x1];
240 u8 outer_first_vid[0x1];
b4ff3a36 241 u8 reserved_at_7[0x1];
e281682b
SM		 242 u8 outer_second_prio[0x1];
243 u8 outer_second_cfi[0x1];
244 u8 outer_second_vid[0x1];
b4ff3a36 245 u8 reserved_at_b[0x1];
e281682b
SM		 246 u8 outer_sip[0x1];
247 u8 outer_dip[0x1];
248 u8 outer_frag[0x1];
249 u8 outer_ip_protocol[0x1];
250 u8 outer_ip_ecn[0x1];
251 u8 outer_ip_dscp[0x1];
252 u8 outer_udp_sport[0x1];
253 u8 outer_udp_dport[0x1];
254 u8 outer_tcp_sport[0x1];
255 u8 outer_tcp_dport[0x1];
256 u8 outer_tcp_flags[0x1];
257 u8 outer_gre_protocol[0x1];
258 u8 outer_gre_key[0x1];
259 u8 outer_vxlan_vni[0x1];
b4ff3a36 260 u8 reserved_at_1a[0x5];
e281682b
SM		 261 u8 source_eswitch_port[0x1];
262
263 u8 inner_dmac[0x1];
264 u8 inner_smac[0x1];
265 u8 inner_ether_type[0x1];
b4ff3a36 266 u8 reserved_at_23[0x1];
e281682b
SM		 267 u8 inner_first_prio[0x1];
268 u8 inner_first_cfi[0x1];
269 u8 inner_first_vid[0x1];
b4ff3a36 270 u8 reserved_at_27[0x1];
e281682b
SM		 271 u8 inner_second_prio[0x1];
272 u8 inner_second_cfi[0x1];
273 u8 inner_second_vid[0x1];
b4ff3a36 274 u8 reserved_at_2b[0x1];
e281682b
SM		 275 u8 inner_sip[0x1];
276 u8 inner_dip[0x1];
277 u8 inner_frag[0x1];
278 u8 inner_ip_protocol[0x1];
279 u8 inner_ip_ecn[0x1];
280 u8 inner_ip_dscp[0x1];
281 u8 inner_udp_sport[0x1];
282 u8 inner_udp_dport[0x1];
283 u8 inner_tcp_sport[0x1];
284 u8 inner_tcp_dport[0x1];
285 u8 inner_tcp_flags[0x1];
b4ff3a36 286 u8 reserved_at_37[0x9];
e281682b 287
b4ff3a36 288 u8 reserved_at_40[0x40];
e281682b
SM		 289};
290
291struct mlx5_ifc_flow_table_prop_layout_bits {
292 u8 ft_support[0x1];
9dc0b289
AV		 293 u8 reserved_at_1[0x1];
294 u8 flow_counter[0x1];
26a81453 295 u8 flow_modify_en[0x1];
2cc43b49 296 u8 modify_root[0x1];
34a40e68
MG		 297 u8 identified_miss_table_mode[0x1];
298 u8 flow_table_modify[0x1];
7adbde20
HHZ		 299 u8 encap[0x1];
300 u8 decap[0x1];
301 u8 reserved_at_9[0x17];
e281682b 302
b4ff3a36 303 u8 reserved_at_20[0x2];
e281682b 304 u8 log_max_ft_size[0x6];
b4ff3a36 305 u8 reserved_at_28[0x10];
e281682b
SM		 306 u8 max_ft_level[0x8];
307
b4ff3a36 308 u8 reserved_at_40[0x20];
e281682b 309
b4ff3a36 310 u8 reserved_at_60[0x18];
e281682b
SM		 311 u8 log_max_ft_num[0x8];
312
b4ff3a36 313 u8 reserved_at_80[0x18];
e281682b
SM		 314 u8 log_max_destination[0x8];
315
b4ff3a36 316 u8 reserved_at_a0[0x18];
e281682b
SM		 317 u8 log_max_flow[0x8];
318
b4ff3a36 319 u8 reserved_at_c0[0x40];
e281682b
SM		 320
321 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
322
323 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
324};
325
326struct mlx5_ifc_odp_per_transport_service_cap_bits {
327 u8 send[0x1];
328 u8 receive[0x1];
329 u8 write[0x1];
330 u8 read[0x1];
b4ff3a36 331 u8 reserved_at_4[0x1];
e281682b 332 u8 srq_receive[0x1];
b4ff3a36 333 u8 reserved_at_6[0x1a];
e281682b
SM		 334};
335
b4d1f032 336struct mlx5_ifc_ipv4_layout_bits {
b4ff3a36 337 u8 reserved_at_0[0x60];
b4d1f032
MG		 338
339 u8 ipv4[0x20];
340};
341
342struct mlx5_ifc_ipv6_layout_bits {
343 u8 ipv6[16][0x8];
344};
345
346union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
347 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
348 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
b4ff3a36 349 u8 reserved_at_0[0x80];
b4d1f032
MG		 350};
351
e281682b
SM		 352struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
353 u8 smac_47_16[0x20];
354
355 u8 smac_15_0[0x10];
356 u8 ethertype[0x10];
357
358 u8 dmac_47_16[0x20];
359
360 u8 dmac_15_0[0x10];
361 u8 first_prio[0x3];
362 u8 first_cfi[0x1];
363 u8 first_vid[0xc];
364
365 u8 ip_protocol[0x8];
366 u8 ip_dscp[0x6];
367 u8 ip_ecn[0x2];
368 u8 vlan_tag[0x1];
b4ff3a36 369 u8 reserved_at_91[0x1];
e281682b 370 u8 frag[0x1];
b4ff3a36 371 u8 reserved_at_93[0x4];
e281682b
SM		 372 u8 tcp_flags[0x9];
373
374 u8 tcp_sport[0x10];
375 u8 tcp_dport[0x10];
376
b4ff3a36 377 u8 reserved_at_c0[0x20];
e281682b
SM		 378
379 u8 udp_sport[0x10];
380 u8 udp_dport[0x10];
381
b4d1f032 382 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
e281682b 383
b4d1f032 384 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
e281682b
SM		 385};
386
387struct mlx5_ifc_fte_match_set_misc_bits {
7486216b
SM		 388 u8 reserved_at_0[0x8];
389 u8 source_sqn[0x18];
e281682b 390
b4ff3a36 391 u8 reserved_at_20[0x10];
e281682b
SM		 392 u8 source_port[0x10];
393
394 u8 outer_second_prio[0x3];
395 u8 outer_second_cfi[0x1];
396 u8 outer_second_vid[0xc];
397 u8 inner_second_prio[0x3];
398 u8 inner_second_cfi[0x1];
399 u8 inner_second_vid[0xc];
400
401 u8 outer_second_vlan_tag[0x1];
402 u8 inner_second_vlan_tag[0x1];
b4ff3a36 403 u8 reserved_at_62[0xe];
e281682b
SM		 404 u8 gre_protocol[0x10];
405
406 u8 gre_key_h[0x18];
407 u8 gre_key_l[0x8];
408
409 u8 vxlan_vni[0x18];
b4ff3a36 410 u8 reserved_at_b8[0x8];
e281682b 411
b4ff3a36 412 u8 reserved_at_c0[0x20];
e281682b 413
b4ff3a36 414 u8 reserved_at_e0[0xc];
e281682b
SM		 415 u8 outer_ipv6_flow_label[0x14];
416
b4ff3a36 417 u8 reserved_at_100[0xc];
e281682b
SM		 418 u8 inner_ipv6_flow_label[0x14];
419
b4ff3a36 420 u8 reserved_at_120[0xe0];
e281682b
SM		 421};
422
423struct mlx5_ifc_cmd_pas_bits {
424 u8 pa_h[0x20];
425
426 u8 pa_l[0x14];
b4ff3a36 427 u8 reserved_at_34[0xc];
e281682b
SM		 428};
429
430struct mlx5_ifc_uint64_bits {
431 u8 hi[0x20];
432
433 u8 lo[0x20];
434};
435
436enum {
437 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
438 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
439 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
440 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
441 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
442 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
443 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
444 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
445 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
446 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
447};
448
449struct mlx5_ifc_ads_bits {
450 u8 fl[0x1];
451 u8 free_ar[0x1];
b4ff3a36 452 u8 reserved_at_2[0xe];
e281682b
SM		 453 u8 pkey_index[0x10];
454
b4ff3a36 455 u8 reserved_at_20[0x8];
e281682b
SM		 456 u8 grh[0x1];
457 u8 mlid[0x7];
458 u8 rlid[0x10];
459
460 u8 ack_timeout[0x5];
b4ff3a36 461 u8 reserved_at_45[0x3];
e281682b 462 u8 src_addr_index[0x8];
b4ff3a36 463 u8 reserved_at_50[0x4];
e281682b
SM		 464 u8 stat_rate[0x4];
465 u8 hop_limit[0x8];
466
b4ff3a36 467 u8 reserved_at_60[0x4];
e281682b
SM		 468 u8 tclass[0x8];
469 u8 flow_label[0x14];
470
471 u8 rgid_rip[16][0x8];
472
b4ff3a36 473 u8 reserved_at_100[0x4];
e281682b
SM		 474 u8 f_dscp[0x1];
475 u8 f_ecn[0x1];
b4ff3a36 476 u8 reserved_at_106[0x1];
e281682b
SM		 477 u8 f_eth_prio[0x1];
478 u8 ecn[0x2];
479 u8 dscp[0x6];
480 u8 udp_sport[0x10];
481
482 u8 dei_cfi[0x1];
483 u8 eth_prio[0x3];
484 u8 sl[0x4];
485 u8 port[0x8];
486 u8 rmac_47_32[0x10];
487
488 u8 rmac_31_0[0x20];
489};
490
491struct mlx5_ifc_flow_table_nic_cap_bits {
b3638e1a 492 u8 nic_rx_multi_path_tirs[0x1];
cea824d4
MG		 493 u8 nic_rx_multi_path_tirs_fts[0x1];
494 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
495 u8 reserved_at_3[0x1fd];
e281682b
SM		 496
497 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
498
b4ff3a36 499 u8 reserved_at_400[0x200];
e281682b
SM		 500
501 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
502
503 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
504
b4ff3a36 505 u8 reserved_at_a00[0x200];
e281682b
SM		 506
507 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
508
b4ff3a36 509 u8 reserved_at_e00[0x7200];
e281682b
SM		 510};
511
495716b1 512struct mlx5_ifc_flow_table_eswitch_cap_bits {
b4ff3a36 513 u8 reserved_at_0[0x200];
495716b1
SM		 514
515 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
516
517 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
518
519 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
520
b4ff3a36 521 u8 reserved_at_800[0x7800];
495716b1
SM		 522};
523
d6666753
SM		 524struct mlx5_ifc_e_switch_cap_bits {
525 u8 vport_svlan_strip[0x1];
526 u8 vport_cvlan_strip[0x1];
527 u8 vport_svlan_insert[0x1];
528 u8 vport_cvlan_insert_if_not_exist[0x1];
529 u8 vport_cvlan_insert_overwrite[0x1];
23898c76
NO		 530 u8 reserved_at_5[0x19];
531 u8 nic_vport_node_guid_modify[0x1];
532 u8 nic_vport_port_guid_modify[0x1];
d6666753 533
7adbde20
HHZ		 534 u8 vxlan_encap_decap[0x1];
535 u8 nvgre_encap_decap[0x1];
536 u8 reserved_at_22[0x9];
537 u8 log_max_encap_headers[0x5];
538 u8 reserved_2b[0x6];
539 u8 max_encap_header_size[0xa];
540
541 u8 reserved_40[0x7c0];
542
d6666753
SM		 543};
544
7486216b
SM		 545struct mlx5_ifc_qos_cap_bits {
546 u8 packet_pacing[0x1];
813f8540
MHY		 547 u8 esw_scheduling[0x1];
548 u8 reserved_at_2[0x1e];
549
550 u8 reserved_at_20[0x20];
551
7486216b 552 u8 packet_pacing_max_rate[0x20];
813f8540 553
7486216b 554 u8 packet_pacing_min_rate[0x20];
813f8540
MHY		 555
556 u8 reserved_at_80[0x10];
7486216b 557 u8 packet_pacing_rate_table_size[0x10];
813f8540
MHY		 558
559 u8 esw_element_type[0x10];
560 u8 esw_tsar_type[0x10];
561
562 u8 reserved_at_c0[0x10];
563 u8 max_qos_para_vport[0x10];
564
565 u8 max_tsar_bw_share[0x20];
566
567 u8 reserved_at_100[0x700];
7486216b
SM		 568};
569
e281682b
SM		 570struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
571 u8 csum_cap[0x1];
572 u8 vlan_cap[0x1];
573 u8 lro_cap[0x1];
574 u8 lro_psh_flag[0x1];
575 u8 lro_time_stamp[0x1];
b4ff3a36 576 u8 reserved_at_5[0x3];
66189961 577 u8 self_lb_en_modifiable[0x1];
b4ff3a36 578 u8 reserved_at_9[0x2];
e281682b 579 u8 max_lso_cap[0x5];
c226dc22 580 u8 multi_pkt_send_wqe[0x2];
cff92d7c 581 u8 wqe_inline_mode[0x2];
e281682b 582 u8 rss_ind_tbl_cap[0x4];
7d5e1423
SM		 583 u8 reg_umr_sq[0x1];
584 u8 scatter_fcs[0x1];
585 u8 reserved_at_1a[0x1];
e281682b 586 u8 tunnel_lso_const_out_ip_id[0x1];
b4ff3a36 587 u8 reserved_at_1c[0x2];
e281682b
SM		 588 u8 tunnel_statless_gre[0x1];
589 u8 tunnel_stateless_vxlan[0x1];
590
b4ff3a36 591 u8 reserved_at_20[0x20];
e281682b 592
b4ff3a36 593 u8 reserved_at_40[0x10];
e281682b
SM		 594 u8 lro_min_mss_size[0x10];
595
b4ff3a36 596 u8 reserved_at_60[0x120];
e281682b
SM		 597
598 u8 lro_timer_supported_periods[4][0x20];
599
b4ff3a36 600 u8 reserved_at_200[0x600];
e281682b
SM		 601};
602
603struct mlx5_ifc_roce_cap_bits {
604 u8 roce_apm[0x1];
b4ff3a36 605 u8 reserved_at_1[0x1f];
e281682b 606
b4ff3a36 607 u8 reserved_at_20[0x60];
e281682b 608
b4ff3a36 609 u8 reserved_at_80[0xc];
e281682b 610 u8 l3_type[0x4];
b4ff3a36 611 u8 reserved_at_90[0x8];
e281682b
SM		 612 u8 roce_version[0x8];
613
b4ff3a36 614 u8 reserved_at_a0[0x10];
e281682b
SM		 615 u8 r_roce_dest_udp_port[0x10];
616
617 u8 r_roce_max_src_udp_port[0x10];
618 u8 r_roce_min_src_udp_port[0x10];
619
b4ff3a36 620 u8 reserved_at_e0[0x10];
e281682b
SM		 621 u8 roce_address_table_size[0x10];
622
b4ff3a36 623 u8 reserved_at_100[0x700];
e281682b
SM		 624};
625
626enum {
627 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
628 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
629 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
630 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
631 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
632 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
633 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
634 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
635 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
636};
637
638enum {
639 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
640 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
641 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
642 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
643 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
644 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
645 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
646 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
647 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
648};
649
650struct mlx5_ifc_atomic_caps_bits {
b4ff3a36 651 u8 reserved_at_0[0x40];
e281682b 652
f91e6d89 653 u8 atomic_req_8B_endianess_mode[0x2];
b4ff3a36 654 u8 reserved_at_42[0x4];
f91e6d89 655 u8 supported_atomic_req_8B_endianess_mode_1[0x1];
e281682b 656
b4ff3a36 657 u8 reserved_at_47[0x19];
e281682b 658
b4ff3a36 659 u8 reserved_at_60[0x20];
e281682b 660
b4ff3a36 661 u8 reserved_at_80[0x10];
f91e6d89 662 u8 atomic_operations[0x10];
e281682b 663
b4ff3a36 664 u8 reserved_at_a0[0x10];
f91e6d89
EBE		 665 u8 atomic_size_qp[0x10];
666
b4ff3a36 667 u8 reserved_at_c0[0x10];
e281682b
SM		 668 u8 atomic_size_dc[0x10];
669
b4ff3a36 670 u8 reserved_at_e0[0x720];
e281682b
SM		 671};
672
673struct mlx5_ifc_odp_cap_bits {
b4ff3a36 674 u8 reserved_at_0[0x40];
e281682b
SM		 675
676 u8 sig[0x1];
b4ff3a36 677 u8 reserved_at_41[0x1f];
e281682b 678
b4ff3a36 679 u8 reserved_at_60[0x20];
e281682b
SM		 680
681 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
682
683 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
684
685 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
686
b4ff3a36 687 u8 reserved_at_e0[0x720];
e281682b
SM		 688};
689
3f0393a5
SG		 690struct mlx5_ifc_calc_op {
691 u8 reserved_at_0[0x10];
692 u8 reserved_at_10[0x9];
693 u8 op_swap_endianness[0x1];
694 u8 op_min[0x1];
695 u8 op_xor[0x1];
696 u8 op_or[0x1];
697 u8 op_and[0x1];
698 u8 op_max[0x1];
699 u8 op_add[0x1];
700};
701
702struct mlx5_ifc_vector_calc_cap_bits {
703 u8 calc_matrix[0x1];
704 u8 reserved_at_1[0x1f];
705 u8 reserved_at_20[0x8];
706 u8 max_vec_count[0x8];
707 u8 reserved_at_30[0xd];
708 u8 max_chunk_size[0x3];
709 struct mlx5_ifc_calc_op calc0;
710 struct mlx5_ifc_calc_op calc1;
711 struct mlx5_ifc_calc_op calc2;
712 struct mlx5_ifc_calc_op calc3;
713
714 u8 reserved_at_e0[0x720];
715};
716
e281682b
SM		 717enum {
718 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
719 MLX5_WQ_TYPE_CYCLIC = 0x1,
7d5e1423 720 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
e281682b
SM		 721};
722
723enum {
724 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
725 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
726};
727
728enum {
729 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
730 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
731 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
732 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
733 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
734};
735
736enum {
737 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
738 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
739 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
740 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
741 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
742 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
743};
744
745enum {
746 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
747 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
748};
749
750enum {
751 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
752 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
753 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
754};
755
756enum {
757 MLX5_CAP_PORT_TYPE_IB = 0x0,
758 MLX5_CAP_PORT_TYPE_ETH = 0x1,
d29b796a
EC		 759};
760
b775516b 761struct mlx5_ifc_cmd_hca_cap_bits {
b4ff3a36 762 u8 reserved_at_0[0x80];
b775516b
EC		 763
764 u8 log_max_srq_sz[0x8];
765 u8 log_max_qp_sz[0x8];
b4ff3a36 766 u8 reserved_at_90[0xb];
b775516b
EC		 767 u8 log_max_qp[0x5];
768
b4ff3a36 769 u8 reserved_at_a0[0xb];
e281682b 770 u8 log_max_srq[0x5];
b4ff3a36 771 u8 reserved_at_b0[0x10];
b775516b 772
b4ff3a36 773 u8 reserved_at_c0[0x8];
b775516b 774 u8 log_max_cq_sz[0x8];
b4ff3a36 775 u8 reserved_at_d0[0xb];
b775516b
EC		 776 u8 log_max_cq[0x5];
777
778 u8 log_max_eq_sz[0x8];
b4ff3a36 779 u8 reserved_at_e8[0x2];
b775516b 780 u8 log_max_mkey[0x6];
b4ff3a36 781 u8 reserved_at_f0[0xc];
b775516b
EC		 782 u8 log_max_eq[0x4];
783
784 u8 max_indirection[0x8];
bcda1aca 785 u8 fixed_buffer_size[0x1];
b775516b 786 u8 log_max_mrw_sz[0x7];
b4ff3a36 787 u8 reserved_at_110[0x2];
b775516b 788 u8 log_max_bsf_list_size[0x6];
bcda1aca
AK		 789 u8 umr_extended_translation_offset[0x1];
790 u8 null_mkey[0x1];
b775516b
EC		 791 u8 log_max_klm_list_size[0x6];
792
b4ff3a36 793 u8 reserved_at_120[0xa];
b775516b 794 u8 log_max_ra_req_dc[0x6];
b4ff3a36 795 u8 reserved_at_130[0xa];
b775516b
EC		 796 u8 log_max_ra_res_dc[0x6];
797
b4ff3a36 798 u8 reserved_at_140[0xa];
b775516b 799 u8 log_max_ra_req_qp[0x6];
b4ff3a36 800 u8 reserved_at_150[0xa];
b775516b
EC		 801 u8 log_max_ra_res_qp[0x6];
802
803 u8 pad_cap[0x1];
804 u8 cc_query_allowed[0x1];
805 u8 cc_modify_allowed[0x1];
b4ff3a36 806 u8 reserved_at_163[0xd];
e281682b 807 u8 gid_table_size[0x10];
b775516b 808
e281682b
SM		 809 u8 out_of_seq_cnt[0x1];
810 u8 vport_counters[0x1];
7486216b 811 u8 retransmission_q_counters[0x1];
83b502a1
AV		 812 u8 reserved_at_183[0x1];
813 u8 modify_rq_counter_set_id[0x1];
814 u8 reserved_at_185[0x1];
b775516b
EC		 815 u8 max_qp_cnt[0xa];
816 u8 pkey_table_size[0x10];
817
e281682b
SM		 818 u8 vport_group_manager[0x1];
819 u8 vhca_group_manager[0x1];
820 u8 ib_virt[0x1];
821 u8 eth_virt[0x1];
b4ff3a36 822 u8 reserved_at_1a4[0x1];
e281682b
SM		 823 u8 ets[0x1];
824 u8 nic_flow_table[0x1];
54f0a411 825 u8 eswitch_flow_table[0x1];
e1c9c62b
TT		 826 u8 early_vf_enable[0x1];
827 u8 reserved_at_1a9[0x2];
b775516b 828 u8 local_ca_ack_delay[0x5];
4ce3bf2f 829 u8 port_module_event[0x1];
7b13558f 830 u8 reserved_at_1b1[0x1];
7d5e1423 831 u8 ports_check[0x1];
7b13558f 832 u8 reserved_at_1b3[0x1];
7d5e1423
SM		 833 u8 disable_link_up[0x1];
834 u8 beacon_led[0x1];
e281682b 835 u8 port_type[0x2];
b775516b
EC		 836 u8 num_ports[0x8];
837
e1c9c62b 838 u8 reserved_at_1c0[0x3];
b775516b 839 u8 log_max_msg[0x5];
e1c9c62b 840 u8 reserved_at_1c8[0x4];
4f3961ee 841 u8 max_tc[0x4];
7486216b
SM		 842 u8 reserved_at_1d0[0x1];
843 u8 dcbx[0x1];
844 u8 reserved_at_1d2[0x4];
928cfe87
TT		 845 u8 rol_s[0x1];
846 u8 rol_g[0x1];
e1c9c62b 847 u8 reserved_at_1d8[0x1];
928cfe87
TT		 848 u8 wol_s[0x1];
849 u8 wol_g[0x1];
850 u8 wol_a[0x1];
851 u8 wol_b[0x1];
852 u8 wol_m[0x1];
853 u8 wol_u[0x1];
854 u8 wol_p[0x1];
b775516b
EC		 855
856 u8 stat_rate_support[0x10];
e1c9c62b 857 u8 reserved_at_1f0[0xc];
e281682b 858 u8 cqe_version[0x4];
b775516b 859
e281682b 860 u8 compact_address_vector[0x1];
7d5e1423 861 u8 striding_rq[0x1];
7b13558f 862 u8 reserved_at_202[0x2];
1015c2e8 863 u8 ipoib_basic_offloads[0x1];
e1c9c62b 864 u8 reserved_at_205[0xa];
e281682b 865 u8 drain_sigerr[0x1];
b775516b
EC		 866 u8 cmdif_checksum[0x2];
867 u8 sigerr_cqe[0x1];
e1c9c62b 868 u8 reserved_at_213[0x1];
b775516b
EC		 869 u8 wq_signature[0x1];
870 u8 sctr_data_cqe[0x1];
e1c9c62b 871 u8 reserved_at_216[0x1];
b775516b
EC		 872 u8 sho[0x1];
873 u8 tph[0x1];
874 u8 rf[0x1];
e281682b 875 u8 dct[0x1];
7486216b 876 u8 qos[0x1];
e281682b 877 u8 eth_net_offloads[0x1];
b775516b
EC		 878 u8 roce[0x1];
879 u8 atomic[0x1];
e1c9c62b 880 u8 reserved_at_21f[0x1];
b775516b
EC		 881
882 u8 cq_oi[0x1];
883 u8 cq_resize[0x1];
884 u8 cq_moderation[0x1];
e1c9c62b 885 u8 reserved_at_223[0x3];
e281682b 886 u8 cq_eq_remap[0x1];
b775516b
EC		 887 u8 pg[0x1];
888 u8 block_lb_mc[0x1];
e1c9c62b 889 u8 reserved_at_229[0x1];
e281682b 890 u8 scqe_break_moderation[0x1];
7d5e1423 891 u8 cq_period_start_from_cqe[0x1];
b775516b 892 u8 cd[0x1];
e1c9c62b 893 u8 reserved_at_22d[0x1];
b775516b 894 u8 apm[0x1];
3f0393a5 895 u8 vector_calc[0x1];
7d5e1423 896 u8 umr_ptr_rlky[0x1];
d2370e0a 897 u8 imaicl[0x1];
e1c9c62b 898 u8 reserved_at_232[0x4];
b775516b
EC		 899 u8 qkv[0x1];
900 u8 pkv[0x1];
b11a4f9c
HE		 901 u8 set_deth_sqpn[0x1];
902 u8 reserved_at_239[0x3];
b775516b
EC		 903 u8 xrc[0x1];
904 u8 ud[0x1];
905 u8 uc[0x1];
906 u8 rc[0x1];
907
e1c9c62b 908 u8 reserved_at_240[0xa];
b775516b 909 u8 uar_sz[0x6];
e1c9c62b 910 u8 reserved_at_250[0x8];
b775516b
EC		 911 u8 log_pg_sz[0x8];
912
913 u8 bf[0x1];
0dbc6fe0 914 u8 driver_version[0x1];
e281682b 915 u8 pad_tx_eth_packet[0x1];
e1c9c62b 916 u8 reserved_at_263[0x8];
b775516b 917 u8 log_bf_reg_size[0x5];
84df61eb
AH		 918
919 u8 reserved_at_270[0xb];
920 u8 lag_master[0x1];
921 u8 num_lag_ports[0x4];
b775516b 922
e1c9c62b 923 u8 reserved_at_280[0x10];
b775516b
EC		 924 u8 max_wqe_sz_sq[0x10];
925
e1c9c62b 926 u8 reserved_at_2a0[0x10];
b775516b
EC		 927 u8 max_wqe_sz_rq[0x10];
928
e1c9c62b 929 u8 reserved_at_2c0[0x10];
b775516b
EC		 930 u8 max_wqe_sz_sq_dc[0x10];
931
e1c9c62b 932 u8 reserved_at_2e0[0x7];
b775516b
EC		 933 u8 max_qp_mcg[0x19];
934
e1c9c62b 935 u8 reserved_at_300[0x18];
b775516b
EC		 936 u8 log_max_mcg[0x8];
937
e1c9c62b 938 u8 reserved_at_320[0x3];
e281682b 939 u8 log_max_transport_domain[0x5];
e1c9c62b 940 u8 reserved_at_328[0x3];
b775516b 941 u8 log_max_pd[0x5];
e1c9c62b 942 u8 reserved_at_330[0xb];
b775516b
EC		 943 u8 log_max_xrcd[0x5];
944
a351a1b0
AV		 945 u8 reserved_at_340[0x8];
946 u8 log_max_flow_counter_bulk[0x8];
947 u8 max_flow_counter[0x10];
948
b775516b 949
e1c9c62b 950 u8 reserved_at_360[0x3];
b775516b 951 u8 log_max_rq[0x5];
e1c9c62b 952 u8 reserved_at_368[0x3];
b775516b 953 u8 log_max_sq[0x5];
e1c9c62b 954 u8 reserved_at_370[0x3];
b775516b 955 u8 log_max_tir[0x5];
e1c9c62b 956 u8 reserved_at_378[0x3];
b775516b
EC		 957 u8 log_max_tis[0x5];
958
e281682b 959 u8 basic_cyclic_rcv_wqe[0x1];
e1c9c62b 960 u8 reserved_at_381[0x2];
e281682b 961 u8 log_max_rmp[0x5];
e1c9c62b 962 u8 reserved_at_388[0x3];
e281682b 963 u8 log_max_rqt[0x5];
e1c9c62b 964 u8 reserved_at_390[0x3];
e281682b 965 u8 log_max_rqt_size[0x5];
e1c9c62b 966 u8 reserved_at_398[0x3];
b775516b
EC		 967 u8 log_max_tis_per_sq[0x5];
968
e1c9c62b 969 u8 reserved_at_3a0[0x3];
e281682b 970 u8 log_max_stride_sz_rq[0x5];
e1c9c62b 971 u8 reserved_at_3a8[0x3];
e281682b 972 u8 log_min_stride_sz_rq[0x5];
e1c9c62b 973 u8 reserved_at_3b0[0x3];
e281682b 974 u8 log_max_stride_sz_sq[0x5];
e1c9c62b 975 u8 reserved_at_3b8[0x3];
e281682b
SM		 976 u8 log_min_stride_sz_sq[0x5];
977
e1c9c62b 978 u8 reserved_at_3c0[0x1b];
e281682b
SM		 979 u8 log_max_wq_sz[0x5];
980
54f0a411 981 u8 nic_vport_change_event[0x1];
e1c9c62b 982 u8 reserved_at_3e1[0xa];
54f0a411 983 u8 log_max_vlan_list[0x5];
e1c9c62b 984 u8 reserved_at_3f0[0x3];
54f0a411 985 u8 log_max_current_mc_list[0x5];
e1c9c62b 986 u8 reserved_at_3f8[0x3];
54f0a411
SM		 987 u8 log_max_current_uc_list[0x5];
988
e1c9c62b 989 u8 reserved_at_400[0x80];
54f0a411 990
e1c9c62b 991 u8 reserved_at_480[0x3];
e281682b 992 u8 log_max_l2_table[0x5];
e1c9c62b 993 u8 reserved_at_488[0x8];
b775516b
EC		 994 u8 log_uar_page_sz[0x10];
995
e1c9c62b 996 u8 reserved_at_4a0[0x20];
048ccca8 997 u8 device_frequency_mhz[0x20];
b0844444 998 u8 device_frequency_khz[0x20];
e1c9c62b
TT		 999
1000 u8 reserved_at_500[0x80];
1001
1002 u8 reserved_at_580[0x3f];
7d5e1423 1003 u8 cqe_compression[0x1];
b775516b 1004
7d5e1423
SM		 1005 u8 cqe_compression_timeout[0x10];
1006 u8 cqe_compression_max_num[0x10];
b775516b 1007
7486216b
SM		 1008 u8 reserved_at_5e0[0x10];
1009 u8 tag_matching[0x1];
1010 u8 rndv_offload_rc[0x1];
1011 u8 rndv_offload_dc[0x1];
1012 u8 log_tag_matching_list_sz[0x5];
7b13558f 1013 u8 reserved_at_5f8[0x3];
7486216b
SM		 1014 u8 log_max_xrq[0x5];
1015
7b13558f 1016 u8 reserved_at_600[0x200];
b775516b
EC		 1017};
1018
81848731
SM		 1019enum mlx5_flow_destination_type {
1020 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1021 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1022 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
bd5251db
AV		 1023
1024 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
e281682b 1025};
b775516b 1026
e281682b
SM		 1027struct mlx5_ifc_dest_format_struct_bits {
1028 u8 destination_type[0x8];
1029 u8 destination_id[0x18];
b775516b 1030
b4ff3a36 1031 u8 reserved_at_20[0x20];
e281682b
SM		 1032};
1033
9dc0b289 1034struct mlx5_ifc_flow_counter_list_bits {
a351a1b0
AV		 1035 u8 clear[0x1];
1036 u8 num_of_counters[0xf];
9dc0b289
AV		 1037 u8 flow_counter_id[0x10];
1038
1039 u8 reserved_at_20[0x20];
1040};
1041
1042union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1043 struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1044 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1045 u8 reserved_at_0[0x40];
1046};
1047
e281682b
SM		 1048struct mlx5_ifc_fte_match_param_bits {
1049 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1050
1051 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1052
1053 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
b775516b 1054
b4ff3a36 1055 u8 reserved_at_600[0xa00];
b775516b
EC		 1056};
1057
e281682b
SM		 1058enum {
1059 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1060 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1061 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1062 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1063 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1064};
b775516b 1065
e281682b
SM		 1066struct mlx5_ifc_rx_hash_field_select_bits {
1067 u8 l3_prot_type[0x1];
1068 u8 l4_prot_type[0x1];
1069 u8 selected_fields[0x1e];
1070};
b775516b 1071
e281682b
SM		 1072enum {
1073 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
1074 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
b775516b
EC		 1075};
1076
e281682b
SM		 1077enum {
1078 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
1079 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
1080};
1081
1082struct mlx5_ifc_wq_bits {
1083 u8 wq_type[0x4];
1084 u8 wq_signature[0x1];
1085 u8 end_padding_mode[0x2];
1086 u8 cd_slave[0x1];
b4ff3a36 1087 u8 reserved_at_8[0x18];
b775516b 1088
e281682b
SM		 1089 u8 hds_skip_first_sge[0x1];
1090 u8 log2_hds_buf_size[0x3];
b4ff3a36 1091 u8 reserved_at_24[0x7];
e281682b
SM		 1092 u8 page_offset[0x5];
1093 u8 lwm[0x10];
b775516b 1094
b4ff3a36 1095 u8 reserved_at_40[0x8];
e281682b
SM		 1096 u8 pd[0x18];
1097
b4ff3a36 1098 u8 reserved_at_60[0x8];
e281682b
SM		 1099 u8 uar_page[0x18];
1100
1101 u8 dbr_addr[0x40];
1102
1103 u8 hw_counter[0x20];
1104
1105 u8 sw_counter[0x20];
1106
b4ff3a36 1107 u8 reserved_at_100[0xc];
e281682b 1108 u8 log_wq_stride[0x4];
b4ff3a36 1109 u8 reserved_at_110[0x3];
e281682b 1110 u8 log_wq_pg_sz[0x5];
b4ff3a36 1111 u8 reserved_at_118[0x3];
e281682b
SM		 1112 u8 log_wq_sz[0x5];
1113
7d5e1423
SM		 1114 u8 reserved_at_120[0x15];
1115 u8 log_wqe_num_of_strides[0x3];
1116 u8 two_byte_shift_en[0x1];
1117 u8 reserved_at_139[0x4];
1118 u8 log_wqe_stride_size[0x3];
1119
1120 u8 reserved_at_140[0x4c0];
b775516b 1121
e281682b 1122 struct mlx5_ifc_cmd_pas_bits pas[0];
b775516b
EC		 1123};
1124
e281682b 1125struct mlx5_ifc_rq_num_bits {
b4ff3a36 1126 u8 reserved_at_0[0x8];
e281682b
SM		 1127 u8 rq_num[0x18];
1128};
b775516b 1129
e281682b 1130struct mlx5_ifc_mac_address_layout_bits {
b4ff3a36 1131 u8 reserved_at_0[0x10];
e281682b 1132 u8 mac_addr_47_32[0x10];
b775516b 1133
e281682b
SM		 1134 u8 mac_addr_31_0[0x20];
1135};
1136
c0046cf7 1137struct mlx5_ifc_vlan_layout_bits {
b4ff3a36 1138 u8 reserved_at_0[0x14];
c0046cf7
SM		 1139 u8 vlan[0x0c];
1140
b4ff3a36 1141 u8 reserved_at_20[0x20];
c0046cf7
SM		 1142};
1143
e281682b 1144struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
b4ff3a36 1145 u8 reserved_at_0[0xa0];
e281682b
SM		 1146
1147 u8 min_time_between_cnps[0x20];
1148
b4ff3a36 1149 u8 reserved_at_c0[0x12];
e281682b 1150 u8 cnp_dscp[0x6];
b4ff3a36 1151 u8 reserved_at_d8[0x5];
e281682b
SM		 1152 u8 cnp_802p_prio[0x3];
1153
b4ff3a36 1154 u8 reserved_at_e0[0x720];
e281682b
SM		 1155};
1156
1157struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
b4ff3a36 1158 u8 reserved_at_0[0x60];
e281682b 1159
b4ff3a36 1160 u8 reserved_at_60[0x4];
e281682b 1161 u8 clamp_tgt_rate[0x1];
b4ff3a36 1162 u8 reserved_at_65[0x3];
e281682b 1163 u8 clamp_tgt_rate_after_time_inc[0x1];
b4ff3a36 1164 u8 reserved_at_69[0x17];
e281682b 1165
b4ff3a36 1166 u8 reserved_at_80[0x20];
e281682b
SM		 1167
1168 u8 rpg_time_reset[0x20];
1169
1170 u8 rpg_byte_reset[0x20];
1171
1172 u8 rpg_threshold[0x20];
1173
1174 u8 rpg_max_rate[0x20];
1175
1176 u8 rpg_ai_rate[0x20];
1177
1178 u8 rpg_hai_rate[0x20];
1179
1180 u8 rpg_gd[0x20];
1181
1182 u8 rpg_min_dec_fac[0x20];
1183
1184 u8 rpg_min_rate[0x20];
1185
b4ff3a36 1186 u8 reserved_at_1c0[0xe0];
e281682b
SM		 1187
1188 u8 rate_to_set_on_first_cnp[0x20];
1189
1190 u8 dce_tcp_g[0x20];
1191
1192 u8 dce_tcp_rtt[0x20];
1193
1194 u8 rate_reduce_monitor_period[0x20];
1195
b4ff3a36 1196 u8 reserved_at_320[0x20];
e281682b
SM		 1197
1198 u8 initial_alpha_value[0x20];
1199
b4ff3a36 1200 u8 reserved_at_360[0x4a0];
e281682b
SM		 1201};
1202
1203struct mlx5_ifc_cong_control_802_1qau_rp_bits {
b4ff3a36 1204 u8 reserved_at_0[0x80];
e281682b
SM		 1205
1206 u8 rppp_max_rps[0x20];
1207
1208 u8 rpg_time_reset[0x20];
1209
1210 u8 rpg_byte_reset[0x20];
1211
1212 u8 rpg_threshold[0x20];
1213
1214 u8 rpg_max_rate[0x20];
1215
1216 u8 rpg_ai_rate[0x20];
1217
1218 u8 rpg_hai_rate[0x20];
1219
1220 u8 rpg_gd[0x20];
1221
1222 u8 rpg_min_dec_fac[0x20];
1223
1224 u8 rpg_min_rate[0x20];
1225
b4ff3a36 1226 u8 reserved_at_1c0[0x640];
e281682b
SM		 1227};
1228
1229enum {
1230 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1231 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1232 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1233};
1234
1235struct mlx5_ifc_resize_field_select_bits {
1236 u8 resize_field_select[0x20];
1237};
1238
1239enum {
1240 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1241 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1242 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1243 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1244};
1245
1246struct mlx5_ifc_modify_field_select_bits {
1247 u8 modify_field_select[0x20];
1248};
1249
1250struct mlx5_ifc_field_select_r_roce_np_bits {
1251 u8 field_select_r_roce_np[0x20];
1252};
1253
1254struct mlx5_ifc_field_select_r_roce_rp_bits {
1255 u8 field_select_r_roce_rp[0x20];
1256};
1257
1258enum {
1259 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1260 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1261 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1262 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1263 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1264 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1265 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1266 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1267 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1268 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1269};
1270
1271struct mlx5_ifc_field_select_802_1qau_rp_bits {
1272 u8 field_select_8021qaurp[0x20];
1273};
1274
1275struct mlx5_ifc_phys_layer_cntrs_bits {
1276 u8 time_since_last_clear_high[0x20];
1277
1278 u8 time_since_last_clear_low[0x20];
1279
1280 u8 symbol_errors_high[0x20];
1281
1282 u8 symbol_errors_low[0x20];
1283
1284 u8 sync_headers_errors_high[0x20];
1285
1286 u8 sync_headers_errors_low[0x20];
1287
1288 u8 edpl_bip_errors_lane0_high[0x20];
1289
1290 u8 edpl_bip_errors_lane0_low[0x20];
1291
1292 u8 edpl_bip_errors_lane1_high[0x20];
1293
1294 u8 edpl_bip_errors_lane1_low[0x20];
1295
1296 u8 edpl_bip_errors_lane2_high[0x20];
1297
1298 u8 edpl_bip_errors_lane2_low[0x20];
1299
1300 u8 edpl_bip_errors_lane3_high[0x20];
1301
1302 u8 edpl_bip_errors_lane3_low[0x20];
1303
1304 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1305
1306 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1307
1308 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1309
1310 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1311
1312 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1313
1314 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1315
1316 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1317
1318 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1319
1320 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1321
1322 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1323
1324 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1325
1326 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1327
1328 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1329
1330 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1331
1332 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1333
1334 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1335
1336 u8 rs_fec_corrected_blocks_high[0x20];
1337
1338 u8 rs_fec_corrected_blocks_low[0x20];
1339
1340 u8 rs_fec_uncorrectable_blocks_high[0x20];
1341
1342 u8 rs_fec_uncorrectable_blocks_low[0x20];
1343
1344 u8 rs_fec_no_errors_blocks_high[0x20];
1345
1346 u8 rs_fec_no_errors_blocks_low[0x20];
1347
1348 u8 rs_fec_single_error_blocks_high[0x20];
1349
1350 u8 rs_fec_single_error_blocks_low[0x20];
1351
1352 u8 rs_fec_corrected_symbols_total_high[0x20];
1353
1354 u8 rs_fec_corrected_symbols_total_low[0x20];
1355
1356 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1357
1358 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1359
1360 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1361
1362 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1363
1364 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1365
1366 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1367
1368 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1369
1370 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1371
1372 u8 link_down_events[0x20];
1373
1374 u8 successful_recovery_events[0x20];
1375
b4ff3a36 1376 u8 reserved_at_640[0x180];
e281682b
SM		 1377};
1378
1c64bf6f
MY		 1379struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1380 u8 symbol_error_counter[0x10];
1381
1382 u8 link_error_recovery_counter[0x8];
1383
1384 u8 link_downed_counter[0x8];
1385
1386 u8 port_rcv_errors[0x10];
1387
1388 u8 port_rcv_remote_physical_errors[0x10];
1389
1390 u8 port_rcv_switch_relay_errors[0x10];
1391
1392 u8 port_xmit_discards[0x10];
1393
1394 u8 port_xmit_constraint_errors[0x8];
1395
1396 u8 port_rcv_constraint_errors[0x8];
1397
1398 u8 reserved_at_70[0x8];
1399
1400 u8 link_overrun_errors[0x8];
1401
1402 u8 reserved_at_80[0x10];
1403
1404 u8 vl_15_dropped[0x10];
1405
1406 u8 reserved_at_a0[0xa0];
1407};
1408
e281682b
SM		 1409struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1410 u8 transmit_queue_high[0x20];
1411
1412 u8 transmit_queue_low[0x20];
1413
b4ff3a36 1414 u8 reserved_at_40[0x780];
e281682b
SM		 1415};
1416
1417struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1418 u8 rx_octets_high[0x20];
1419
1420 u8 rx_octets_low[0x20];
1421
b4ff3a36 1422 u8 reserved_at_40[0xc0];
e281682b
SM		 1423
1424 u8 rx_frames_high[0x20];
1425
1426 u8 rx_frames_low[0x20];
1427
1428 u8 tx_octets_high[0x20];
1429
1430 u8 tx_octets_low[0x20];
1431
b4ff3a36 1432 u8 reserved_at_180[0xc0];
e281682b
SM		 1433
1434 u8 tx_frames_high[0x20];
1435
1436 u8 tx_frames_low[0x20];
1437
1438 u8 rx_pause_high[0x20];
1439
1440 u8 rx_pause_low[0x20];
1441
1442 u8 rx_pause_duration_high[0x20];
1443
1444 u8 rx_pause_duration_low[0x20];
1445
1446 u8 tx_pause_high[0x20];
1447
1448 u8 tx_pause_low[0x20];
1449
1450 u8 tx_pause_duration_high[0x20];
1451
1452 u8 tx_pause_duration_low[0x20];
1453
1454 u8 rx_pause_transition_high[0x20];
1455
1456 u8 rx_pause_transition_low[0x20];
1457
b4ff3a36 1458 u8 reserved_at_3c0[0x400];
e281682b
SM		 1459};
1460
1461struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1462 u8 port_transmit_wait_high[0x20];
1463
1464 u8 port_transmit_wait_low[0x20];
1465
b4ff3a36 1466 u8 reserved_at_40[0x780];
e281682b
SM		 1467};
1468
1469struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1470 u8 dot3stats_alignment_errors_high[0x20];
1471
1472 u8 dot3stats_alignment_errors_low[0x20];
1473
1474 u8 dot3stats_fcs_errors_high[0x20];
1475
1476 u8 dot3stats_fcs_errors_low[0x20];
1477
1478 u8 dot3stats_single_collision_frames_high[0x20];
1479
1480 u8 dot3stats_single_collision_frames_low[0x20];
1481
1482 u8 dot3stats_multiple_collision_frames_high[0x20];
1483
1484 u8 dot3stats_multiple_collision_frames_low[0x20];
1485
1486 u8 dot3stats_sqe_test_errors_high[0x20];
1487
1488 u8 dot3stats_sqe_test_errors_low[0x20];
1489
1490 u8 dot3stats_deferred_transmissions_high[0x20];
1491
1492 u8 dot3stats_deferred_transmissions_low[0x20];
1493
1494 u8 dot3stats_late_collisions_high[0x20];
1495
1496 u8 dot3stats_late_collisions_low[0x20];
1497
1498 u8 dot3stats_excessive_collisions_high[0x20];
1499
1500 u8 dot3stats_excessive_collisions_low[0x20];
1501
1502 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1503
1504 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1505
1506 u8 dot3stats_carrier_sense_errors_high[0x20];
1507
1508 u8 dot3stats_carrier_sense_errors_low[0x20];
1509
1510 u8 dot3stats_frame_too_longs_high[0x20];
1511
1512 u8 dot3stats_frame_too_longs_low[0x20];
1513
1514 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1515
1516 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1517
1518 u8 dot3stats_symbol_errors_high[0x20];
1519
1520 u8 dot3stats_symbol_errors_low[0x20];
1521
1522 u8 dot3control_in_unknown_opcodes_high[0x20];
1523
1524 u8 dot3control_in_unknown_opcodes_low[0x20];
1525
1526 u8 dot3in_pause_frames_high[0x20];
1527
1528 u8 dot3in_pause_frames_low[0x20];
1529
1530 u8 dot3out_pause_frames_high[0x20];
1531
1532 u8 dot3out_pause_frames_low[0x20];
1533
b4ff3a36 1534 u8 reserved_at_400[0x3c0];
e281682b
SM		 1535};
1536
1537struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1538 u8 ether_stats_drop_events_high[0x20];
1539
1540 u8 ether_stats_drop_events_low[0x20];
1541
1542 u8 ether_stats_octets_high[0x20];
1543
1544 u8 ether_stats_octets_low[0x20];
1545
1546 u8 ether_stats_pkts_high[0x20];
1547
1548 u8 ether_stats_pkts_low[0x20];
1549
1550 u8 ether_stats_broadcast_pkts_high[0x20];
1551
1552 u8 ether_stats_broadcast_pkts_low[0x20];
1553
1554 u8 ether_stats_multicast_pkts_high[0x20];
1555
1556 u8 ether_stats_multicast_pkts_low[0x20];
1557
1558 u8 ether_stats_crc_align_errors_high[0x20];
1559
1560 u8 ether_stats_crc_align_errors_low[0x20];
1561
1562 u8 ether_stats_undersize_pkts_high[0x20];
1563
1564 u8 ether_stats_undersize_pkts_low[0x20];
1565
1566 u8 ether_stats_oversize_pkts_high[0x20];
1567
1568 u8 ether_stats_oversize_pkts_low[0x20];
1569
1570 u8 ether_stats_fragments_high[0x20];
1571
1572 u8 ether_stats_fragments_low[0x20];
1573
1574 u8 ether_stats_jabbers_high[0x20];
1575
1576 u8 ether_stats_jabbers_low[0x20];
1577
1578 u8 ether_stats_collisions_high[0x20];
1579
1580 u8 ether_stats_collisions_low[0x20];
1581
1582 u8 ether_stats_pkts64octets_high[0x20];
1583
1584 u8 ether_stats_pkts64octets_low[0x20];
1585
1586 u8 ether_stats_pkts65to127octets_high[0x20];
1587
1588 u8 ether_stats_pkts65to127octets_low[0x20];
1589
1590 u8 ether_stats_pkts128to255octets_high[0x20];
1591
1592 u8 ether_stats_pkts128to255octets_low[0x20];
1593
1594 u8 ether_stats_pkts256to511octets_high[0x20];
1595
1596 u8 ether_stats_pkts256to511octets_low[0x20];
1597
1598 u8 ether_stats_pkts512to1023octets_high[0x20];
1599
1600 u8 ether_stats_pkts512to1023octets_low[0x20];
1601
1602 u8 ether_stats_pkts1024to1518octets_high[0x20];
1603
1604 u8 ether_stats_pkts1024to1518octets_low[0x20];
1605
1606 u8 ether_stats_pkts1519to2047octets_high[0x20];
1607
1608 u8 ether_stats_pkts1519to2047octets_low[0x20];
1609
1610 u8 ether_stats_pkts2048to4095octets_high[0x20];
1611
1612 u8 ether_stats_pkts2048to4095octets_low[0x20];
1613
1614 u8 ether_stats_pkts4096to8191octets_high[0x20];
1615
1616 u8 ether_stats_pkts4096to8191octets_low[0x20];
1617
1618 u8 ether_stats_pkts8192to10239octets_high[0x20];
1619
1620 u8 ether_stats_pkts8192to10239octets_low[0x20];
1621
b4ff3a36 1622 u8 reserved_at_540[0x280];
e281682b
SM		 1623};
1624
1625struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1626 u8 if_in_octets_high[0x20];
1627
1628 u8 if_in_octets_low[0x20];
1629
1630 u8 if_in_ucast_pkts_high[0x20];
1631
1632 u8 if_in_ucast_pkts_low[0x20];
1633
1634 u8 if_in_discards_high[0x20];
1635
1636 u8 if_in_discards_low[0x20];
1637
1638 u8 if_in_errors_high[0x20];
1639
1640 u8 if_in_errors_low[0x20];
1641
1642 u8 if_in_unknown_protos_high[0x20];
1643
1644 u8 if_in_unknown_protos_low[0x20];
1645
1646 u8 if_out_octets_high[0x20];
1647
1648 u8 if_out_octets_low[0x20];
1649
1650 u8 if_out_ucast_pkts_high[0x20];
1651
1652 u8 if_out_ucast_pkts_low[0x20];
1653
1654 u8 if_out_discards_high[0x20];
1655
1656 u8 if_out_discards_low[0x20];
1657
1658 u8 if_out_errors_high[0x20];
1659
1660 u8 if_out_errors_low[0x20];
1661
1662 u8 if_in_multicast_pkts_high[0x20];
1663
1664 u8 if_in_multicast_pkts_low[0x20];
1665
1666 u8 if_in_broadcast_pkts_high[0x20];
1667
1668 u8 if_in_broadcast_pkts_low[0x20];
1669
1670 u8 if_out_multicast_pkts_high[0x20];
1671
1672 u8 if_out_multicast_pkts_low[0x20];
1673
1674 u8 if_out_broadcast_pkts_high[0x20];
1675
1676 u8 if_out_broadcast_pkts_low[0x20];
1677
b4ff3a36 1678 u8 reserved_at_340[0x480];
e281682b
SM		 1679};
1680
1681struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1682 u8 a_frames_transmitted_ok_high[0x20];
1683
1684 u8 a_frames_transmitted_ok_low[0x20];
1685
1686 u8 a_frames_received_ok_high[0x20];
1687
1688 u8 a_frames_received_ok_low[0x20];
1689
1690 u8 a_frame_check_sequence_errors_high[0x20];
1691
1692 u8 a_frame_check_sequence_errors_low[0x20];
1693
1694 u8 a_alignment_errors_high[0x20];
1695
1696 u8 a_alignment_errors_low[0x20];
1697
1698 u8 a_octets_transmitted_ok_high[0x20];
1699
1700 u8 a_octets_transmitted_ok_low[0x20];
1701
1702 u8 a_octets_received_ok_high[0x20];
1703
1704 u8 a_octets_received_ok_low[0x20];
1705
1706 u8 a_multicast_frames_xmitted_ok_high[0x20];
1707
1708 u8 a_multicast_frames_xmitted_ok_low[0x20];
1709
1710 u8 a_broadcast_frames_xmitted_ok_high[0x20];
1711
1712 u8 a_broadcast_frames_xmitted_ok_low[0x20];
1713
1714 u8 a_multicast_frames_received_ok_high[0x20];
1715
1716 u8 a_multicast_frames_received_ok_low[0x20];
1717
1718 u8 a_broadcast_frames_received_ok_high[0x20];
1719
1720 u8 a_broadcast_frames_received_ok_low[0x20];
1721
1722 u8 a_in_range_length_errors_high[0x20];
1723
1724 u8 a_in_range_length_errors_low[0x20];
1725
1726 u8 a_out_of_range_length_field_high[0x20];
1727
1728 u8 a_out_of_range_length_field_low[0x20];
1729
1730 u8 a_frame_too_long_errors_high[0x20];
1731
1732 u8 a_frame_too_long_errors_low[0x20];
1733
1734 u8 a_symbol_error_during_carrier_high[0x20];
1735
1736 u8 a_symbol_error_during_carrier_low[0x20];
1737
1738 u8 a_mac_control_frames_transmitted_high[0x20];
1739
1740 u8 a_mac_control_frames_transmitted_low[0x20];
1741
1742 u8 a_mac_control_frames_received_high[0x20];
1743
1744 u8 a_mac_control_frames_received_low[0x20];
1745
1746 u8 a_unsupported_opcodes_received_high[0x20];
1747
1748 u8 a_unsupported_opcodes_received_low[0x20];
1749
1750 u8 a_pause_mac_ctrl_frames_received_high[0x20];
1751
1752 u8 a_pause_mac_ctrl_frames_received_low[0x20];
1753
1754 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
1755
1756 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
1757
b4ff3a36 1758 u8 reserved_at_4c0[0x300];
e281682b
SM		 1759};
1760
7f503169
GP		 1761struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
1762 u8 life_time_counter_high[0x20];
1763
1764 u8 life_time_counter_low[0x20];
1765
1766 u8 rx_errors[0x20];
1767
1768 u8 tx_errors[0x20];
1769
1770 u8 l0_to_recovery_eieos[0x20];
1771
1772 u8 l0_to_recovery_ts[0x20];
1773
1774 u8 l0_to_recovery_framing[0x20];
1775
1776 u8 l0_to_recovery_retrain[0x20];
1777
1778 u8 crc_error_dllp[0x20];
1779
1780 u8 crc_error_tlp[0x20];
1781
1782 u8 reserved_at_140[0x680];
1783};
1784
1785struct mlx5_ifc_pcie_tas_cntrs_grp_data_layout_bits {
1786 u8 life_time_counter_high[0x20];
1787
1788 u8 life_time_counter_low[0x20];
1789
1790 u8 time_to_boot_image_start[0x20];
1791
1792 u8 time_to_link_image[0x20];
1793
1794 u8 calibration_time[0x20];
1795
1796 u8 time_to_first_perst[0x20];
1797
1798 u8 time_to_detect_state[0x20];
1799
1800 u8 time_to_l0[0x20];
1801
1802 u8 time_to_crs_en[0x20];
1803
1804 u8 time_to_plastic_image_start[0x20];
1805
1806 u8 time_to_iron_image_start[0x20];
1807
1808 u8 perst_handler[0x20];
1809
1810 u8 times_in_l1[0x20];
1811
1812 u8 times_in_l23[0x20];
1813
1814 u8 dl_down[0x20];
1815
1816 u8 config_cycle1usec[0x20];
1817
1818 u8 config_cycle2to7usec[0x20];
1819
1820 u8 config_cycle_8to15usec[0x20];
1821
1822 u8 config_cycle_16_to_63usec[0x20];
1823
1824 u8 config_cycle_64usec[0x20];
1825
1826 u8 correctable_err_msg_sent[0x20];
1827
1828 u8 non_fatal_err_msg_sent[0x20];
1829
1830 u8 fatal_err_msg_sent[0x20];
1831
1832 u8 reserved_at_2e0[0x4e0];
1833};
1834
e281682b
SM		 1835struct mlx5_ifc_cmd_inter_comp_event_bits {
1836 u8 command_completion_vector[0x20];
1837
b4ff3a36 1838 u8 reserved_at_20[0xc0];
e281682b
SM		 1839};
1840
1841struct mlx5_ifc_stall_vl_event_bits {
b4ff3a36 1842 u8 reserved_at_0[0x18];
e281682b 1843 u8 port_num[0x1];
b4ff3a36 1844 u8 reserved_at_19[0x3];
e281682b
SM		 1845 u8 vl[0x4];
1846
b4ff3a36 1847 u8 reserved_at_20[0xa0];
e281682b
SM		 1848};
1849
1850struct mlx5_ifc_db_bf_congestion_event_bits {
1851 u8 event_subtype[0x8];
b4ff3a36 1852 u8 reserved_at_8[0x8];
e281682b 1853 u8 congestion_level[0x8];
b4ff3a36 1854 u8 reserved_at_18[0x8];
e281682b 1855
b4ff3a36 1856 u8 reserved_at_20[0xa0];
e281682b
SM		 1857};
1858
1859struct mlx5_ifc_gpio_event_bits {
b4ff3a36 1860 u8 reserved_at_0[0x60];
e281682b
SM		 1861
1862 u8 gpio_event_hi[0x20];
1863
1864 u8 gpio_event_lo[0x20];
1865
b4ff3a36 1866 u8 reserved_at_a0[0x40];
e281682b
SM		 1867};
1868
1869struct mlx5_ifc_port_state_change_event_bits {
b4ff3a36 1870 u8 reserved_at_0[0x40];
e281682b
SM		 1871
1872 u8 port_num[0x4];
b4ff3a36 1873 u8 reserved_at_44[0x1c];
e281682b 1874
b4ff3a36 1875 u8 reserved_at_60[0x80];
e281682b
SM		 1876};
1877
1878struct mlx5_ifc_dropped_packet_logged_bits {
b4ff3a36 1879 u8 reserved_at_0[0xe0];
e281682b
SM		 1880};
1881
1882enum {
1883 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
1884 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
1885};
1886
1887struct mlx5_ifc_cq_error_bits {
b4ff3a36 1888 u8 reserved_at_0[0x8];
e281682b
SM		 1889 u8 cqn[0x18];
1890
b4ff3a36 1891 u8 reserved_at_20[0x20];
e281682b 1892
b4ff3a36 1893 u8 reserved_at_40[0x18];
e281682b
SM		 1894 u8 syndrome[0x8];
1895
b4ff3a36 1896 u8 reserved_at_60[0x80];
e281682b
SM		 1897};
1898
1899struct mlx5_ifc_rdma_page_fault_event_bits {
1900 u8 bytes_committed[0x20];
1901
1902 u8 r_key[0x20];
1903
b4ff3a36 1904 u8 reserved_at_40[0x10];
e281682b
SM		 1905 u8 packet_len[0x10];
1906
1907 u8 rdma_op_len[0x20];
1908
1909 u8 rdma_va[0x40];
1910
b4ff3a36 1911 u8 reserved_at_c0[0x5];
e281682b
SM		 1912 u8 rdma[0x1];
1913 u8 write[0x1];
1914 u8 requestor[0x1];
1915 u8 qp_number[0x18];
1916};
1917
1918struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1919 u8 bytes_committed[0x20];
1920
b4ff3a36 1921 u8 reserved_at_20[0x10];
e281682b
SM		 1922 u8 wqe_index[0x10];
1923
b4ff3a36 1924 u8 reserved_at_40[0x10];
e281682b
SM		 1925 u8 len[0x10];
1926
b4ff3a36 1927 u8 reserved_at_60[0x60];
e281682b 1928
b4ff3a36 1929 u8 reserved_at_c0[0x5];
e281682b
SM		 1930 u8 rdma[0x1];
1931 u8 write_read[0x1];
1932 u8 requestor[0x1];
1933 u8 qpn[0x18];
1934};
1935
1936struct mlx5_ifc_qp_events_bits {
b4ff3a36 1937 u8 reserved_at_0[0xa0];
e281682b
SM		 1938
1939 u8 type[0x8];
b4ff3a36 1940 u8 reserved_at_a8[0x18];
e281682b 1941
b4ff3a36 1942 u8 reserved_at_c0[0x8];
e281682b
SM		 1943 u8 qpn_rqn_sqn[0x18];
1944};
1945
1946struct mlx5_ifc_dct_events_bits {
b4ff3a36 1947 u8 reserved_at_0[0xc0];
e281682b 1948
b4ff3a36 1949 u8 reserved_at_c0[0x8];
e281682b
SM		 1950 u8 dct_number[0x18];
1951};
1952
1953struct mlx5_ifc_comp_event_bits {
b4ff3a36 1954 u8 reserved_at_0[0xc0];
e281682b 1955
b4ff3a36 1956 u8 reserved_at_c0[0x8];
e281682b
SM		 1957 u8 cq_number[0x18];
1958};
1959
1960enum {
1961 MLX5_QPC_STATE_RST = 0x0,
1962 MLX5_QPC_STATE_INIT = 0x1,
1963 MLX5_QPC_STATE_RTR = 0x2,
1964 MLX5_QPC_STATE_RTS = 0x3,
1965 MLX5_QPC_STATE_SQER = 0x4,
1966 MLX5_QPC_STATE_ERR = 0x6,
1967 MLX5_QPC_STATE_SQD = 0x7,
1968 MLX5_QPC_STATE_SUSPENDED = 0x9,
1969};
1970
1971enum {
1972 MLX5_QPC_ST_RC = 0x0,
1973 MLX5_QPC_ST_UC = 0x1,
1974 MLX5_QPC_ST_UD = 0x2,
1975 MLX5_QPC_ST_XRC = 0x3,
1976 MLX5_QPC_ST_DCI = 0x5,
1977 MLX5_QPC_ST_QP0 = 0x7,
1978 MLX5_QPC_ST_QP1 = 0x8,
1979 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
1980 MLX5_QPC_ST_REG_UMR = 0xc,
1981};
1982
1983enum {
1984 MLX5_QPC_PM_STATE_ARMED = 0x0,
1985 MLX5_QPC_PM_STATE_REARM = 0x1,
1986 MLX5_QPC_PM_STATE_RESERVED = 0x2,
1987 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
1988};
1989
1990enum {
1991 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
1992 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
1993};
1994
1995enum {
1996 MLX5_QPC_MTU_256_BYTES = 0x1,
1997 MLX5_QPC_MTU_512_BYTES = 0x2,
1998 MLX5_QPC_MTU_1K_BYTES = 0x3,
1999 MLX5_QPC_MTU_2K_BYTES = 0x4,
2000 MLX5_QPC_MTU_4K_BYTES = 0x5,
2001 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
2002};
2003
2004enum {
2005 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
2006 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
2007 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
2008 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
2009 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
2010 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
2011 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
2012 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
2013};
2014
2015enum {
2016 MLX5_QPC_CS_REQ_DISABLE = 0x0,
2017 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
2018 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
2019};
2020
2021enum {
2022 MLX5_QPC_CS_RES_DISABLE = 0x0,
2023 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
2024 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
2025};
2026
2027struct mlx5_ifc_qpc_bits {
2028 u8 state[0x4];
84df61eb 2029 u8 lag_tx_port_affinity[0x4];
e281682b 2030 u8 st[0x8];
b4ff3a36 2031 u8 reserved_at_10[0x3];
e281682b 2032 u8 pm_state[0x2];
b4ff3a36 2033 u8 reserved_at_15[0x7];
e281682b 2034 u8 end_padding_mode[0x2];
b4ff3a36 2035 u8 reserved_at_1e[0x2];
e281682b
SM		 2036
2037 u8 wq_signature[0x1];
2038 u8 block_lb_mc[0x1];
2039 u8 atomic_like_write_en[0x1];
2040 u8 latency_sensitive[0x1];
b4ff3a36 2041 u8 reserved_at_24[0x1];
e281682b 2042 u8 drain_sigerr[0x1];
b4ff3a36 2043 u8 reserved_at_26[0x2];
e281682b
SM		 2044 u8 pd[0x18];
2045
2046 u8 mtu[0x3];
2047 u8 log_msg_max[0x5];
b4ff3a36 2048 u8 reserved_at_48[0x1];
e281682b
SM		 2049 u8 log_rq_size[0x4];
2050 u8 log_rq_stride[0x3];
2051 u8 no_sq[0x1];
2052 u8 log_sq_size[0x4];
b4ff3a36 2053 u8 reserved_at_55[0x6];
e281682b 2054 u8 rlky[0x1];
1015c2e8 2055 u8 ulp_stateless_offload_mode[0x4];
e281682b
SM		 2056
2057 u8 counter_set_id[0x8];
2058 u8 uar_page[0x18];
2059
b4ff3a36 2060 u8 reserved_at_80[0x8];
e281682b
SM		 2061 u8 user_index[0x18];
2062
b4ff3a36 2063 u8 reserved_at_a0[0x3];
e281682b
SM		 2064 u8 log_page_size[0x5];
2065 u8 remote_qpn[0x18];
2066
2067 struct mlx5_ifc_ads_bits primary_address_path;
2068
2069 struct mlx5_ifc_ads_bits secondary_address_path;
2070
2071 u8 log_ack_req_freq[0x4];
b4ff3a36 2072 u8 reserved_at_384[0x4];
e281682b 2073 u8 log_sra_max[0x3];
b4ff3a36 2074 u8 reserved_at_38b[0x2];
e281682b
SM		 2075 u8 retry_count[0x3];
2076 u8 rnr_retry[0x3];
b4ff3a36 2077 u8 reserved_at_393[0x1];
e281682b
SM		 2078 u8 fre[0x1];
2079 u8 cur_rnr_retry[0x3];
2080 u8 cur_retry_count[0x3];
b4ff3a36 2081 u8 reserved_at_39b[0x5];
e281682b 2082
b4ff3a36 2083 u8 reserved_at_3a0[0x20];
e281682b 2084
b4ff3a36 2085 u8 reserved_at_3c0[0x8];
e281682b
SM		 2086 u8 next_send_psn[0x18];
2087
b4ff3a36 2088 u8 reserved_at_3e0[0x8];
e281682b
SM		 2089 u8 cqn_snd[0x18];
2090
09a7d9ec
SM		 2091 u8 reserved_at_400[0x8];
2092 u8 deth_sqpn[0x18];
2093
2094 u8 reserved_at_420[0x20];
e281682b 2095
b4ff3a36 2096 u8 reserved_at_440[0x8];
e281682b
SM		 2097 u8 last_acked_psn[0x18];
2098
b4ff3a36 2099 u8 reserved_at_460[0x8];
e281682b
SM		 2100 u8 ssn[0x18];
2101
b4ff3a36 2102 u8 reserved_at_480[0x8];
e281682b 2103 u8 log_rra_max[0x3];
b4ff3a36 2104 u8 reserved_at_48b[0x1];
e281682b
SM		 2105 u8 atomic_mode[0x4];
2106 u8 rre[0x1];
2107 u8 rwe[0x1];
2108 u8 rae[0x1];
b4ff3a36 2109 u8 reserved_at_493[0x1];
e281682b 2110 u8 page_offset[0x6];
b4ff3a36 2111 u8 reserved_at_49a[0x3];
e281682b
SM		 2112 u8 cd_slave_receive[0x1];
2113 u8 cd_slave_send[0x1];
2114 u8 cd_master[0x1];
2115
b4ff3a36 2116 u8 reserved_at_4a0[0x3];
e281682b
SM		 2117 u8 min_rnr_nak[0x5];
2118 u8 next_rcv_psn[0x18];
2119
b4ff3a36 2120 u8 reserved_at_4c0[0x8];
e281682b
SM		 2121 u8 xrcd[0x18];
2122
b4ff3a36 2123 u8 reserved_at_4e0[0x8];
e281682b
SM		 2124 u8 cqn_rcv[0x18];
2125
2126 u8 dbr_addr[0x40];
2127
2128 u8 q_key[0x20];
2129
b4ff3a36 2130 u8 reserved_at_560[0x5];
e281682b 2131 u8 rq_type[0x3];
7486216b 2132 u8 srqn_rmpn_xrqn[0x18];
e281682b 2133
b4ff3a36 2134 u8 reserved_at_580[0x8];
e281682b
SM		 2135 u8 rmsn[0x18];
2136
2137 u8 hw_sq_wqebb_counter[0x10];
2138 u8 sw_sq_wqebb_counter[0x10];
2139
2140 u8 hw_rq_counter[0x20];
2141
2142 u8 sw_rq_counter[0x20];
2143
b4ff3a36 2144 u8 reserved_at_600[0x20];
e281682b 2145
b4ff3a36 2146 u8 reserved_at_620[0xf];
e281682b
SM		 2147 u8 cgs[0x1];
2148 u8 cs_req[0x8];
2149 u8 cs_res[0x8];
2150
2151 u8 dc_access_key[0x40];
2152
b4ff3a36 2153 u8 reserved_at_680[0xc0];
e281682b
SM		 2154};
2155
2156struct mlx5_ifc_roce_addr_layout_bits {
2157 u8 source_l3_address[16][0x8];
2158
b4ff3a36 2159 u8 reserved_at_80[0x3];
e281682b
SM		 2160 u8 vlan_valid[0x1];
2161 u8 vlan_id[0xc];
2162 u8 source_mac_47_32[0x10];
2163
2164 u8 source_mac_31_0[0x20];
2165
b4ff3a36 2166 u8 reserved_at_c0[0x14];
e281682b
SM		 2167 u8 roce_l3_type[0x4];
2168 u8 roce_version[0x8];
2169
b4ff3a36 2170 u8 reserved_at_e0[0x20];
e281682b
SM		 2171};
2172
2173union mlx5_ifc_hca_cap_union_bits {
2174 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2175 struct mlx5_ifc_odp_cap_bits odp_cap;
2176 struct mlx5_ifc_atomic_caps_bits atomic_caps;
2177 struct mlx5_ifc_roce_cap_bits roce_cap;
2178 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2179 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
495716b1 2180 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
d6666753 2181 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
3f0393a5 2182 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
7486216b 2183 struct mlx5_ifc_qos_cap_bits qos_cap;
b4ff3a36 2184 u8 reserved_at_0[0x8000];
e281682b
SM		 2185};
2186
2187enum {
2188 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
2189 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
2190 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
9dc0b289 2191 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
7adbde20
HHZ		 2192 MLX5_FLOW_CONTEXT_ACTION_ENCAP = 0x10,
2193 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
e281682b
SM		 2194};
2195
2196struct mlx5_ifc_flow_context_bits {
b4ff3a36 2197 u8 reserved_at_0[0x20];
e281682b
SM		 2198
2199 u8 group_id[0x20];
2200
b4ff3a36 2201 u8 reserved_at_40[0x8];
e281682b
SM		 2202 u8 flow_tag[0x18];
2203
b4ff3a36 2204 u8 reserved_at_60[0x10];
e281682b
SM		 2205 u8 action[0x10];
2206
b4ff3a36 2207 u8 reserved_at_80[0x8];
e281682b
SM		 2208 u8 destination_list_size[0x18];
2209
9dc0b289
AV		 2210 u8 reserved_at_a0[0x8];
2211 u8 flow_counter_list_size[0x18];
2212
7adbde20
HHZ		 2213 u8 encap_id[0x20];
2214
2215 u8 reserved_at_e0[0x120];
e281682b
SM		 2216
2217 struct mlx5_ifc_fte_match_param_bits match_value;
2218
b4ff3a36 2219 u8 reserved_at_1200[0x600];
e281682b 2220
9dc0b289 2221 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
e281682b
SM		 2222};
2223
2224enum {
2225 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
2226 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
2227};
2228
2229struct mlx5_ifc_xrc_srqc_bits {
2230 u8 state[0x4];
2231 u8 log_xrc_srq_size[0x4];
b4ff3a36 2232 u8 reserved_at_8[0x18];
e281682b
SM		 2233
2234 u8 wq_signature[0x1];
2235 u8 cont_srq[0x1];
b4ff3a36 2236 u8 reserved_at_22[0x1];
e281682b
SM		 2237 u8 rlky[0x1];
2238 u8 basic_cyclic_rcv_wqe[0x1];
2239 u8 log_rq_stride[0x3];
2240 u8 xrcd[0x18];
2241
2242 u8 page_offset[0x6];
b4ff3a36 2243 u8 reserved_at_46[0x2];
e281682b
SM		 2244 u8 cqn[0x18];
2245
b4ff3a36 2246 u8 reserved_at_60[0x20];
e281682b
SM		 2247
2248 u8 user_index_equal_xrc_srqn[0x1];
b4ff3a36 2249 u8 reserved_at_81[0x1];
e281682b
SM		 2250 u8 log_page_size[0x6];
2251 u8 user_index[0x18];
2252
b4ff3a36 2253 u8 reserved_at_a0[0x20];
e281682b 2254
b4ff3a36 2255 u8 reserved_at_c0[0x8];
e281682b
SM		 2256 u8 pd[0x18];
2257
2258 u8 lwm[0x10];
2259 u8 wqe_cnt[0x10];
2260
b4ff3a36 2261 u8 reserved_at_100[0x40];
e281682b
SM		 2262
2263 u8 db_record_addr_h[0x20];
2264
2265 u8 db_record_addr_l[0x1e];
b4ff3a36 2266 u8 reserved_at_17e[0x2];
e281682b 2267
b4ff3a36 2268 u8 reserved_at_180[0x80];
e281682b
SM		 2269};
2270
2271struct mlx5_ifc_traffic_counter_bits {
2272 u8 packets[0x40];
2273
2274 u8 octets[0x40];
2275};
2276
2277struct mlx5_ifc_tisc_bits {
84df61eb
AH		 2278 u8 strict_lag_tx_port_affinity[0x1];
2279 u8 reserved_at_1[0x3];
2280 u8 lag_tx_port_affinity[0x04];
2281
2282 u8 reserved_at_8[0x4];
e281682b 2283 u8 prio[0x4];
b4ff3a36 2284 u8 reserved_at_10[0x10];
e281682b 2285
b4ff3a36 2286 u8 reserved_at_20[0x100];
e281682b 2287
b4ff3a36 2288 u8 reserved_at_120[0x8];
e281682b
SM		 2289 u8 transport_domain[0x18];
2290
b4ff3a36 2291 u8 reserved_at_140[0x3c0];
e281682b
SM		 2292};
2293
2294enum {
2295 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2296 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2297};
2298
2299enum {
2300 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2301 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2302};
2303
2304enum {
2be6967c
SM		 2305 MLX5_RX_HASH_FN_NONE = 0x0,
2306 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
2307 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
e281682b
SM		 2308};
2309
2310enum {
2311 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1,
2312 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2,
2313};
2314
2315struct mlx5_ifc_tirc_bits {
b4ff3a36 2316 u8 reserved_at_0[0x20];
e281682b
SM		 2317
2318 u8 disp_type[0x4];
b4ff3a36 2319 u8 reserved_at_24[0x1c];
e281682b 2320
b4ff3a36 2321 u8 reserved_at_40[0x40];
e281682b 2322
b4ff3a36 2323 u8 reserved_at_80[0x4];
e281682b
SM		 2324 u8 lro_timeout_period_usecs[0x10];
2325 u8 lro_enable_mask[0x4];
2326 u8 lro_max_ip_payload_size[0x8];
2327
b4ff3a36 2328 u8 reserved_at_a0[0x40];
e281682b 2329
b4ff3a36 2330 u8 reserved_at_e0[0x8];
e281682b
SM		 2331 u8 inline_rqn[0x18];
2332
2333 u8 rx_hash_symmetric[0x1];
b4ff3a36 2334 u8 reserved_at_101[0x1];
e281682b 2335 u8 tunneled_offload_en[0x1];
b4ff3a36 2336 u8 reserved_at_103[0x5];
e281682b
SM		 2337 u8 indirect_table[0x18];
2338
2339 u8 rx_hash_fn[0x4];
b4ff3a36 2340 u8 reserved_at_124[0x2];
e281682b
SM		 2341 u8 self_lb_block[0x2];
2342 u8 transport_domain[0x18];
2343
2344 u8 rx_hash_toeplitz_key[10][0x20];
2345
2346 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2347
2348 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2349
b4ff3a36 2350 u8 reserved_at_2c0[0x4c0];
e281682b
SM		 2351};
2352
2353enum {
2354 MLX5_SRQC_STATE_GOOD = 0x0,
2355 MLX5_SRQC_STATE_ERROR = 0x1,
2356};
2357
2358struct mlx5_ifc_srqc_bits {
2359 u8 state[0x4];
2360 u8 log_srq_size[0x4];
b4ff3a36 2361 u8 reserved_at_8[0x18];
e281682b
SM		 2362
2363 u8 wq_signature[0x1];
2364 u8 cont_srq[0x1];
b4ff3a36 2365 u8 reserved_at_22[0x1];
e281682b 2366 u8 rlky[0x1];
b4ff3a36 2367 u8 reserved_at_24[0x1];
e281682b
SM		 2368 u8 log_rq_stride[0x3];
2369 u8 xrcd[0x18];
2370
2371 u8 page_offset[0x6];
b4ff3a36 2372 u8 reserved_at_46[0x2];
e281682b
SM		 2373 u8 cqn[0x18];
2374
b4ff3a36 2375 u8 reserved_at_60[0x20];
e281682b 2376
b4ff3a36 2377 u8 reserved_at_80[0x2];
e281682b 2378 u8 log_page_size[0x6];
b4ff3a36 2379 u8 reserved_at_88[0x18];
e281682b 2380
b4ff3a36 2381 u8 reserved_at_a0[0x20];
e281682b 2382
b4ff3a36 2383 u8 reserved_at_c0[0x8];
e281682b
SM		 2384 u8 pd[0x18];
2385
2386 u8 lwm[0x10];
2387 u8 wqe_cnt[0x10];
2388
b4ff3a36 2389 u8 reserved_at_100[0x40];
e281682b 2390
01949d01 2391 u8 dbr_addr[0x40];
e281682b 2392
b4ff3a36 2393 u8 reserved_at_180[0x80];
e281682b
SM		 2394};
2395
2396enum {
2397 MLX5_SQC_STATE_RST = 0x0,
2398 MLX5_SQC_STATE_RDY = 0x1,
2399 MLX5_SQC_STATE_ERR = 0x3,
2400};
2401
2402struct mlx5_ifc_sqc_bits {
2403 u8 rlky[0x1];
2404 u8 cd_master[0x1];
2405 u8 fre[0x1];
2406 u8 flush_in_error_en[0x1];
cff92d7c
HHZ		 2407 u8 reserved_at_4[0x1];
2408 u8 min_wqe_inline_mode[0x3];
e281682b 2409 u8 state[0x4];
7d5e1423
SM		 2410 u8 reg_umr[0x1];
2411 u8 reserved_at_d[0x13];
e281682b 2412
b4ff3a36 2413 u8 reserved_at_20[0x8];
e281682b
SM		 2414 u8 user_index[0x18];
2415
b4ff3a36 2416 u8 reserved_at_40[0x8];
e281682b
SM		 2417 u8 cqn[0x18];
2418
7486216b 2419 u8 reserved_at_60[0x90];
e281682b 2420
7486216b 2421 u8 packet_pacing_rate_limit_index[0x10];
e281682b 2422 u8 tis_lst_sz[0x10];
b4ff3a36 2423 u8 reserved_at_110[0x10];
e281682b 2424
b4ff3a36 2425 u8 reserved_at_120[0x40];
e281682b 2426
b4ff3a36 2427 u8 reserved_at_160[0x8];
e281682b
SM		 2428 u8 tis_num_0[0x18];
2429
2430 struct mlx5_ifc_wq_bits wq;
2431};
2432
813f8540
MHY		 2433enum {
2434 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2435 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2436 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2437 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2438};
2439
2440struct mlx5_ifc_scheduling_context_bits {
2441 u8 element_type[0x8];
2442 u8 reserved_at_8[0x18];
2443
2444 u8 element_attributes[0x20];
2445
2446 u8 parent_element_id[0x20];
2447
2448 u8 reserved_at_60[0x40];
2449
2450 u8 bw_share[0x20];
2451
2452 u8 max_average_bw[0x20];
2453
2454 u8 reserved_at_e0[0x120];
2455};
2456
e281682b 2457struct mlx5_ifc_rqtc_bits {
b4ff3a36 2458 u8 reserved_at_0[0xa0];
e281682b 2459
b4ff3a36 2460 u8 reserved_at_a0[0x10];
e281682b
SM		 2461 u8 rqt_max_size[0x10];
2462
b4ff3a36 2463 u8 reserved_at_c0[0x10];
e281682b
SM		 2464 u8 rqt_actual_size[0x10];
2465
b4ff3a36 2466 u8 reserved_at_e0[0x6a0];
e281682b
SM		 2467
2468 struct mlx5_ifc_rq_num_bits rq_num[0];
2469};
2470
2471enum {
2472 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2473 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2474};
2475
2476enum {
2477 MLX5_RQC_STATE_RST = 0x0,
2478 MLX5_RQC_STATE_RDY = 0x1,
2479 MLX5_RQC_STATE_ERR = 0x3,
2480};
2481
2482struct mlx5_ifc_rqc_bits {
2483 u8 rlky[0x1];
7d5e1423
SM		 2484 u8 reserved_at_1[0x1];
2485 u8 scatter_fcs[0x1];
e281682b
SM		 2486 u8 vsd[0x1];
2487 u8 mem_rq_type[0x4];
2488 u8 state[0x4];
b4ff3a36 2489 u8 reserved_at_c[0x1];
e281682b 2490 u8 flush_in_error_en[0x1];
b4ff3a36 2491 u8 reserved_at_e[0x12];
e281682b 2492
b4ff3a36 2493 u8 reserved_at_20[0x8];
e281682b
SM		 2494 u8 user_index[0x18];
2495
b4ff3a36 2496 u8 reserved_at_40[0x8];
e281682b
SM		 2497 u8 cqn[0x18];
2498
2499 u8 counter_set_id[0x8];
b4ff3a36 2500 u8 reserved_at_68[0x18];
e281682b 2501
b4ff3a36 2502 u8 reserved_at_80[0x8];
e281682b
SM		 2503 u8 rmpn[0x18];
2504
b4ff3a36 2505 u8 reserved_at_a0[0xe0];
e281682b
SM		 2506
2507 struct mlx5_ifc_wq_bits wq;
2508};
2509
2510enum {
2511 MLX5_RMPC_STATE_RDY = 0x1,
2512 MLX5_RMPC_STATE_ERR = 0x3,
2513};
2514
2515struct mlx5_ifc_rmpc_bits {
b4ff3a36 2516 u8 reserved_at_0[0x8];
e281682b 2517 u8 state[0x4];
b4ff3a36 2518 u8 reserved_at_c[0x14];
e281682b
SM		 2519
2520 u8 basic_cyclic_rcv_wqe[0x1];
b4ff3a36 2521 u8 reserved_at_21[0x1f];
e281682b 2522
b4ff3a36 2523 u8 reserved_at_40[0x140];
e281682b
SM		 2524
2525 struct mlx5_ifc_wq_bits wq;
2526};
2527
e281682b 2528struct mlx5_ifc_nic_vport_context_bits {
cff92d7c
HHZ		 2529 u8 reserved_at_0[0x5];
2530 u8 min_wqe_inline_mode[0x3];
2531 u8 reserved_at_8[0x17];
e281682b
SM		 2532 u8 roce_en[0x1];
2533
d82b7318 2534 u8 arm_change_event[0x1];
b4ff3a36 2535 u8 reserved_at_21[0x1a];
d82b7318
SM		 2536 u8 event_on_mtu[0x1];
2537 u8 event_on_promisc_change[0x1];
2538 u8 event_on_vlan_change[0x1];
2539 u8 event_on_mc_address_change[0x1];
2540 u8 event_on_uc_address_change[0x1];
e281682b 2541
b4ff3a36 2542 u8 reserved_at_40[0xf0];
d82b7318
SM		 2543
2544 u8 mtu[0x10];
2545
9efa7525
AS		 2546 u8 system_image_guid[0x40];
2547 u8 port_guid[0x40];
2548 u8 node_guid[0x40];
2549
b4ff3a36 2550 u8 reserved_at_200[0x140];
9efa7525 2551 u8 qkey_violation_counter[0x10];
b4ff3a36 2552 u8 reserved_at_350[0x430];
d82b7318
SM		 2553
2554 u8 promisc_uc[0x1];
2555 u8 promisc_mc[0x1];
2556 u8 promisc_all[0x1];
b4ff3a36 2557 u8 reserved_at_783[0x2];
e281682b 2558 u8 allowed_list_type[0x3];
b4ff3a36 2559 u8 reserved_at_788[0xc];
e281682b
SM		 2560 u8 allowed_list_size[0xc];
2561
2562 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2563
b4ff3a36 2564 u8 reserved_at_7e0[0x20];
e281682b
SM		 2565
2566 u8 current_uc_mac_address[0][0x40];
2567};
2568
2569enum {
2570 MLX5_MKC_ACCESS_MODE_PA = 0x0,
2571 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
2572 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
bcda1aca 2573 MLX5_MKC_ACCESS_MODE_KSM = 0x3,
e281682b
SM		 2574};
2575
2576struct mlx5_ifc_mkc_bits {
b4ff3a36 2577 u8 reserved_at_0[0x1];
e281682b 2578 u8 free[0x1];
b4ff3a36 2579 u8 reserved_at_2[0xd];
e281682b
SM		 2580 u8 small_fence_on_rdma_read_response[0x1];
2581 u8 umr_en[0x1];
2582 u8 a[0x1];
2583 u8 rw[0x1];
2584 u8 rr[0x1];
2585 u8 lw[0x1];
2586 u8 lr[0x1];
2587 u8 access_mode[0x2];
b4ff3a36 2588 u8 reserved_at_18[0x8];
e281682b
SM		 2589
2590 u8 qpn[0x18];
2591 u8 mkey_7_0[0x8];
2592
b4ff3a36 2593 u8 reserved_at_40[0x20];
e281682b
SM		 2594
2595 u8 length64[0x1];
2596 u8 bsf_en[0x1];
2597 u8 sync_umr[0x1];
b4ff3a36 2598 u8 reserved_at_63[0x2];
e281682b 2599 u8 expected_sigerr_count[0x1];
b4ff3a36 2600 u8 reserved_at_66[0x1];
e281682b
SM		 2601 u8 en_rinval[0x1];
2602 u8 pd[0x18];
2603
2604 u8 start_addr[0x40];
2605
2606 u8 len[0x40];
2607
2608 u8 bsf_octword_size[0x20];
2609
b4ff3a36 2610 u8 reserved_at_120[0x80];
e281682b
SM		 2611
2612 u8 translations_octword_size[0x20];
2613
b4ff3a36 2614 u8 reserved_at_1c0[0x1b];
e281682b
SM		 2615 u8 log_page_size[0x5];
2616
b4ff3a36 2617 u8 reserved_at_1e0[0x20];
e281682b
SM		 2618};
2619
2620struct mlx5_ifc_pkey_bits {
b4ff3a36 2621 u8 reserved_at_0[0x10];
e281682b
SM		 2622 u8 pkey[0x10];
2623};
2624
2625struct mlx5_ifc_array128_auto_bits {
2626 u8 array128_auto[16][0x8];
2627};
2628
2629struct mlx5_ifc_hca_vport_context_bits {
2630 u8 field_select[0x20];
2631
b4ff3a36 2632 u8 reserved_at_20[0xe0];
e281682b
SM		 2633
2634 u8 sm_virt_aware[0x1];
2635 u8 has_smi[0x1];
2636 u8 has_raw[0x1];
2637 u8 grh_required[0x1];
b4ff3a36 2638 u8 reserved_at_104[0xc];
707c4602
MD		 2639 u8 port_physical_state[0x4];
2640 u8 vport_state_policy[0x4];
2641 u8 port_state[0x4];
e281682b
SM		 2642 u8 vport_state[0x4];
2643
b4ff3a36 2644 u8 reserved_at_120[0x20];
707c4602
MD		 2645
2646 u8 system_image_guid[0x40];
e281682b
SM		 2647
2648 u8 port_guid[0x40];
2649
2650 u8 node_guid[0x40];
2651
2652 u8 cap_mask1[0x20];
2653
2654 u8 cap_mask1_field_select[0x20];
2655
2656 u8 cap_mask2[0x20];
2657
2658 u8 cap_mask2_field_select[0x20];
2659
b4ff3a36 2660 u8 reserved_at_280[0x80];
e281682b
SM		 2661
2662 u8 lid[0x10];
b4ff3a36 2663 u8 reserved_at_310[0x4];
e281682b
SM		 2664 u8 init_type_reply[0x4];
2665 u8 lmc[0x3];
2666 u8 subnet_timeout[0x5];
2667
2668 u8 sm_lid[0x10];
2669 u8 sm_sl[0x4];
b4ff3a36 2670 u8 reserved_at_334[0xc];
e281682b
SM		 2671
2672 u8 qkey_violation_counter[0x10];
2673 u8 pkey_violation_counter[0x10];
2674
b4ff3a36 2675 u8 reserved_at_360[0xca0];
e281682b
SM		 2676};
2677
d6666753 2678struct mlx5_ifc_esw_vport_context_bits {
b4ff3a36 2679 u8 reserved_at_0[0x3];
d6666753
SM		 2680 u8 vport_svlan_strip[0x1];
2681 u8 vport_cvlan_strip[0x1];
2682 u8 vport_svlan_insert[0x1];
2683 u8 vport_cvlan_insert[0x2];
b4ff3a36 2684 u8 reserved_at_8[0x18];
d6666753 2685
b4ff3a36 2686 u8 reserved_at_20[0x20];
d6666753
SM		 2687
2688 u8 svlan_cfi[0x1];
2689 u8 svlan_pcp[0x3];
2690 u8 svlan_id[0xc];
2691 u8 cvlan_cfi[0x1];
2692 u8 cvlan_pcp[0x3];
2693 u8 cvlan_id[0xc];
2694
b4ff3a36 2695 u8 reserved_at_60[0x7a0];
d6666753
SM		 2696};
2697
e281682b
SM		 2698enum {
2699 MLX5_EQC_STATUS_OK = 0x0,
2700 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
2701};
2702
2703enum {
2704 MLX5_EQC_ST_ARMED = 0x9,
2705 MLX5_EQC_ST_FIRED = 0xa,
2706};
2707
2708struct mlx5_ifc_eqc_bits {
2709 u8 status[0x4];
b4ff3a36 2710 u8 reserved_at_4[0x9];
e281682b
SM		 2711 u8 ec[0x1];
2712 u8 oi[0x1];
b4ff3a36 2713 u8 reserved_at_f[0x5];
e281682b 2714 u8 st[0x4];
b4ff3a36 2715 u8 reserved_at_18[0x8];
e281682b 2716
b4ff3a36 2717 u8 reserved_at_20[0x20];
e281682b 2718
b4ff3a36 2719 u8 reserved_at_40[0x14];
e281682b 2720 u8 page_offset[0x6];
b4ff3a36 2721 u8 reserved_at_5a[0x6];
e281682b 2722
b4ff3a36 2723 u8 reserved_at_60[0x3];
e281682b
SM		 2724 u8 log_eq_size[0x5];
2725 u8 uar_page[0x18];
2726
b4ff3a36 2727 u8 reserved_at_80[0x20];
e281682b 2728
b4ff3a36 2729 u8 reserved_at_a0[0x18];
e281682b
SM		 2730 u8 intr[0x8];
2731
b4ff3a36 2732 u8 reserved_at_c0[0x3];
e281682b 2733 u8 log_page_size[0x5];
b4ff3a36 2734 u8 reserved_at_c8[0x18];
e281682b 2735
b4ff3a36 2736 u8 reserved_at_e0[0x60];
e281682b 2737
b4ff3a36 2738 u8 reserved_at_140[0x8];
e281682b
SM		 2739 u8 consumer_counter[0x18];
2740
b4ff3a36 2741 u8 reserved_at_160[0x8];
e281682b
SM		 2742 u8 producer_counter[0x18];
2743
b4ff3a36 2744 u8 reserved_at_180[0x80];
e281682b
SM		 2745};
2746
2747enum {
2748 MLX5_DCTC_STATE_ACTIVE = 0x0,
2749 MLX5_DCTC_STATE_DRAINING = 0x1,
2750 MLX5_DCTC_STATE_DRAINED = 0x2,
2751};
2752
2753enum {
2754 MLX5_DCTC_CS_RES_DISABLE = 0x0,
2755 MLX5_DCTC_CS_RES_NA = 0x1,
2756 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
2757};
2758
2759enum {
2760 MLX5_DCTC_MTU_256_BYTES = 0x1,
2761 MLX5_DCTC_MTU_512_BYTES = 0x2,
2762 MLX5_DCTC_MTU_1K_BYTES = 0x3,
2763 MLX5_DCTC_MTU_2K_BYTES = 0x4,
2764 MLX5_DCTC_MTU_4K_BYTES = 0x5,
2765};
2766
2767struct mlx5_ifc_dctc_bits {
b4ff3a36 2768 u8 reserved_at_0[0x4];
e281682b 2769 u8 state[0x4];
b4ff3a36 2770 u8 reserved_at_8[0x18];
e281682b 2771
b4ff3a36 2772 u8 reserved_at_20[0x8];
e281682b
SM		 2773 u8 user_index[0x18];
2774
b4ff3a36 2775 u8 reserved_at_40[0x8];
e281682b
SM		 2776 u8 cqn[0x18];
2777
2778 u8 counter_set_id[0x8];
2779 u8 atomic_mode[0x4];
2780 u8 rre[0x1];
2781 u8 rwe[0x1];
2782 u8 rae[0x1];
2783 u8 atomic_like_write_en[0x1];
2784 u8 latency_sensitive[0x1];
2785 u8 rlky[0x1];
2786 u8 free_ar[0x1];
b4ff3a36 2787 u8 reserved_at_73[0xd];
e281682b 2788
b4ff3a36 2789 u8 reserved_at_80[0x8];
e281682b 2790 u8 cs_res[0x8];
b4ff3a36 2791 u8 reserved_at_90[0x3];
e281682b 2792 u8 min_rnr_nak[0x5];
b4ff3a36 2793 u8 reserved_at_98[0x8];
e281682b 2794
b4ff3a36 2795 u8 reserved_at_a0[0x8];
7486216b 2796 u8 srqn_xrqn[0x18];
e281682b 2797
b4ff3a36 2798 u8 reserved_at_c0[0x8];
e281682b
SM		 2799 u8 pd[0x18];
2800
2801 u8 tclass[0x8];
b4ff3a36 2802 u8 reserved_at_e8[0x4];
e281682b
SM		 2803 u8 flow_label[0x14];
2804
2805 u8 dc_access_key[0x40];
2806
b4ff3a36 2807 u8 reserved_at_140[0x5];
e281682b
SM		 2808 u8 mtu[0x3];
2809 u8 port[0x8];
2810 u8 pkey_index[0x10];
2811
b4ff3a36 2812 u8 reserved_at_160[0x8];
e281682b 2813 u8 my_addr_index[0x8];
b4ff3a36 2814 u8 reserved_at_170[0x8];
e281682b
SM		 2815 u8 hop_limit[0x8];
2816
2817 u8 dc_access_key_violation_count[0x20];
2818
b4ff3a36 2819 u8 reserved_at_1a0[0x14];
e281682b
SM		 2820 u8 dei_cfi[0x1];
2821 u8 eth_prio[0x3];
2822 u8 ecn[0x2];
2823 u8 dscp[0x6];
2824
b4ff3a36 2825 u8 reserved_at_1c0[0x40];
e281682b
SM		 2826};
2827
2828enum {
2829 MLX5_CQC_STATUS_OK = 0x0,
2830 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
2831 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
2832};
2833
2834enum {
2835 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
2836 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
2837};
2838
2839enum {
2840 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
2841 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
2842 MLX5_CQC_ST_FIRED = 0xa,
2843};
2844
7d5e1423
SM		 2845enum {
2846 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
2847 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
7486216b 2848 MLX5_CQ_PERIOD_NUM_MODES
7d5e1423
SM		 2849};
2850
e281682b
SM		 2851struct mlx5_ifc_cqc_bits {
2852 u8 status[0x4];
b4ff3a36 2853 u8 reserved_at_4[0x4];
e281682b
SM		 2854 u8 cqe_sz[0x3];
2855 u8 cc[0x1];
b4ff3a36 2856 u8 reserved_at_c[0x1];
e281682b
SM		 2857 u8 scqe_break_moderation_en[0x1];
2858 u8 oi[0x1];
7d5e1423
SM		 2859 u8 cq_period_mode[0x2];
2860 u8 cqe_comp_en[0x1];
e281682b
SM		 2861 u8 mini_cqe_res_format[0x2];
2862 u8 st[0x4];
b4ff3a36 2863 u8 reserved_at_18[0x8];
e281682b 2864
b4ff3a36 2865 u8 reserved_at_20[0x20];
e281682b 2866
b4ff3a36 2867 u8 reserved_at_40[0x14];
e281682b 2868 u8 page_offset[0x6];
b4ff3a36 2869 u8 reserved_at_5a[0x6];
e281682b 2870
b4ff3a36 2871 u8 reserved_at_60[0x3];
e281682b
SM		 2872 u8 log_cq_size[0x5];
2873 u8 uar_page[0x18];
2874
b4ff3a36 2875 u8 reserved_at_80[0x4];
e281682b
SM		 2876 u8 cq_period[0xc];
2877 u8 cq_max_count[0x10];
2878
b4ff3a36 2879 u8 reserved_at_a0[0x18];
e281682b
SM		 2880 u8 c_eqn[0x8];
2881
b4ff3a36 2882 u8 reserved_at_c0[0x3];
e281682b 2883 u8 log_page_size[0x5];
b4ff3a36 2884 u8 reserved_at_c8[0x18];
e281682b 2885
b4ff3a36 2886 u8 reserved_at_e0[0x20];
e281682b 2887
b4ff3a36 2888 u8 reserved_at_100[0x8];
e281682b
SM		 2889 u8 last_notified_index[0x18];
2890
b4ff3a36 2891 u8 reserved_at_120[0x8];
e281682b
SM		 2892 u8 last_solicit_index[0x18];
2893
b4ff3a36 2894 u8 reserved_at_140[0x8];
e281682b
SM		 2895 u8 consumer_counter[0x18];
2896
b4ff3a36 2897 u8 reserved_at_160[0x8];
e281682b
SM		 2898 u8 producer_counter[0x18];
2899
b4ff3a36 2900 u8 reserved_at_180[0x40];
e281682b
SM		 2901
2902 u8 dbr_addr[0x40];
2903};
2904
2905union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2906 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2907 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2908 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
b4ff3a36 2909 u8 reserved_at_0[0x800];
e281682b
SM		 2910};
2911
2912struct mlx5_ifc_query_adapter_param_block_bits {
b4ff3a36 2913 u8 reserved_at_0[0xc0];
e281682b 2914
b4ff3a36 2915 u8 reserved_at_c0[0x8];
211e6c80
MD		 2916 u8 ieee_vendor_id[0x18];
2917
b4ff3a36 2918 u8 reserved_at_e0[0x10];
e281682b
SM		 2919 u8 vsd_vendor_id[0x10];
2920
2921 u8 vsd[208][0x8];
2922
2923 u8 vsd_contd_psid[16][0x8];
2924};
2925
7486216b
SM		 2926enum {
2927 MLX5_XRQC_STATE_GOOD = 0x0,
2928 MLX5_XRQC_STATE_ERROR = 0x1,
2929};
2930
2931enum {
2932 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
2933 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
2934};
2935
2936enum {
2937 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
2938};
2939
2940struct mlx5_ifc_tag_matching_topology_context_bits {
2941 u8 log_matching_list_sz[0x4];
2942 u8 reserved_at_4[0xc];
2943 u8 append_next_index[0x10];
2944
2945 u8 sw_phase_cnt[0x10];
2946 u8 hw_phase_cnt[0x10];
2947
2948 u8 reserved_at_40[0x40];
2949};
2950
2951struct mlx5_ifc_xrqc_bits {
2952 u8 state[0x4];
2953 u8 rlkey[0x1];
2954 u8 reserved_at_5[0xf];
2955 u8 topology[0x4];
2956 u8 reserved_at_18[0x4];
2957 u8 offload[0x4];
2958
2959 u8 reserved_at_20[0x8];
2960 u8 user_index[0x18];
2961
2962 u8 reserved_at_40[0x8];
2963 u8 cqn[0x18];
2964
2965 u8 reserved_at_60[0xa0];
2966
2967 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
2968
5579e151 2969 u8 reserved_at_180[0x880];
7486216b
SM		 2970
2971 struct mlx5_ifc_wq_bits wq;
2972};
2973
e281682b
SM		 2974union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2975 struct mlx5_ifc_modify_field_select_bits modify_field_select;
2976 struct mlx5_ifc_resize_field_select_bits resize_field_select;
b4ff3a36 2977 u8 reserved_at_0[0x20];
e281682b
SM		 2978};
2979
2980union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2981 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2982 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2983 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
b4ff3a36 2984 u8 reserved_at_0[0x20];
e281682b
SM		 2985};
2986
2987union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
2988 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
2989 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
2990 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
2991 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
2992 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
2993 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
2994 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
1c64bf6f 2995 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b 2996 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
b4ff3a36 2997 u8 reserved_at_0[0x7c0];
e281682b
SM		 2998};
2999
7f503169
GP		 3000union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3001 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3002 struct mlx5_ifc_pcie_tas_cntrs_grp_data_layout_bits pcie_tas_cntrs_grp_data_layout;
3003 u8 reserved_at_0[0x7c0];
3004};
3005
e281682b
SM		 3006union mlx5_ifc_event_auto_bits {
3007 struct mlx5_ifc_comp_event_bits comp_event;
3008 struct mlx5_ifc_dct_events_bits dct_events;
3009 struct mlx5_ifc_qp_events_bits qp_events;
3010 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3011 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3012 struct mlx5_ifc_cq_error_bits cq_error;
3013 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3014 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3015 struct mlx5_ifc_gpio_event_bits gpio_event;
3016 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3017 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3018 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
b4ff3a36 3019 u8 reserved_at_0[0xe0];
e281682b
SM		 3020};
3021
3022struct mlx5_ifc_health_buffer_bits {
b4ff3a36 3023 u8 reserved_at_0[0x100];
e281682b
SM		 3024
3025 u8 assert_existptr[0x20];
3026
3027 u8 assert_callra[0x20];
3028
b4ff3a36 3029 u8 reserved_at_140[0x40];
e281682b
SM		 3030
3031 u8 fw_version[0x20];
3032
3033 u8 hw_id[0x20];
3034
b4ff3a36 3035 u8 reserved_at_1c0[0x20];
e281682b
SM		 3036
3037 u8 irisc_index[0x8];
3038 u8 synd[0x8];
3039 u8 ext_synd[0x10];
3040};
3041
3042struct mlx5_ifc_register_loopback_control_bits {
3043 u8 no_lb[0x1];
b4ff3a36 3044 u8 reserved_at_1[0x7];
e281682b 3045 u8 port[0x8];
b4ff3a36 3046 u8 reserved_at_10[0x10];
e281682b 3047
b4ff3a36 3048 u8 reserved_at_20[0x60];
e281682b
SM		 3049};
3050
813f8540
MHY		 3051struct mlx5_ifc_vport_tc_element_bits {
3052 u8 traffic_class[0x4];
3053 u8 reserved_at_4[0xc];
3054 u8 vport_number[0x10];
3055};
3056
3057struct mlx5_ifc_vport_element_bits {
3058 u8 reserved_at_0[0x10];
3059 u8 vport_number[0x10];
3060};
3061
3062enum {
3063 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3064 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3065 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3066};
3067
3068struct mlx5_ifc_tsar_element_bits {
3069 u8 reserved_at_0[0x8];
3070 u8 tsar_type[0x8];
3071 u8 reserved_at_10[0x10];
3072};
3073
e281682b
SM		 3074struct mlx5_ifc_teardown_hca_out_bits {
3075 u8 status[0x8];
b4ff3a36 3076 u8 reserved_at_8[0x18];
e281682b
SM		 3077
3078 u8 syndrome[0x20];
3079
b4ff3a36 3080 u8 reserved_at_40[0x40];
e281682b
SM		 3081};
3082
3083enum {
3084 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
3085 MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE = 0x1,
3086};
3087
3088struct mlx5_ifc_teardown_hca_in_bits {
3089 u8 opcode[0x10];
b4ff3a36 3090 u8 reserved_at_10[0x10];
e281682b 3091
b4ff3a36 3092 u8 reserved_at_20[0x10];
e281682b
SM		 3093 u8 op_mod[0x10];
3094
b4ff3a36 3095 u8 reserved_at_40[0x10];
e281682b
SM		 3096 u8 profile[0x10];
3097
b4ff3a36 3098 u8 reserved_at_60[0x20];
e281682b
SM		 3099};
3100
3101struct mlx5_ifc_sqerr2rts_qp_out_bits {
3102 u8 status[0x8];
b4ff3a36 3103 u8 reserved_at_8[0x18];
e281682b
SM		 3104
3105 u8 syndrome[0x20];
3106
b4ff3a36 3107 u8 reserved_at_40[0x40];
e281682b
SM		 3108};
3109
3110struct mlx5_ifc_sqerr2rts_qp_in_bits {
3111 u8 opcode[0x10];
b4ff3a36 3112 u8 reserved_at_10[0x10];
e281682b 3113
b4ff3a36 3114 u8 reserved_at_20[0x10];
e281682b
SM		 3115 u8 op_mod[0x10];
3116
b4ff3a36 3117 u8 reserved_at_40[0x8];
e281682b
SM		 3118 u8 qpn[0x18];
3119
b4ff3a36 3120 u8 reserved_at_60[0x20];
e281682b
SM		 3121
3122 u8 opt_param_mask[0x20];
3123
b4ff3a36 3124 u8 reserved_at_a0[0x20];
e281682b
SM		 3125
3126 struct mlx5_ifc_qpc_bits qpc;
3127
b4ff3a36 3128 u8 reserved_at_800[0x80];
e281682b
SM		 3129};
3130
3131struct mlx5_ifc_sqd2rts_qp_out_bits {
3132 u8 status[0x8];
b4ff3a36 3133 u8 reserved_at_8[0x18];
e281682b
SM		 3134
3135 u8 syndrome[0x20];
3136
b4ff3a36 3137 u8 reserved_at_40[0x40];
e281682b
SM		 3138};
3139
3140struct mlx5_ifc_sqd2rts_qp_in_bits {
3141 u8 opcode[0x10];
b4ff3a36 3142 u8 reserved_at_10[0x10];
e281682b 3143
b4ff3a36 3144 u8 reserved_at_20[0x10];
e281682b
SM		 3145 u8 op_mod[0x10];
3146
b4ff3a36 3147 u8 reserved_at_40[0x8];
e281682b
SM		 3148 u8 qpn[0x18];
3149
b4ff3a36 3150 u8 reserved_at_60[0x20];
e281682b
SM		 3151
3152 u8 opt_param_mask[0x20];
3153
b4ff3a36 3154 u8 reserved_at_a0[0x20];
e281682b
SM		 3155
3156 struct mlx5_ifc_qpc_bits qpc;
3157
b4ff3a36 3158 u8 reserved_at_800[0x80];
e281682b
SM		 3159};
3160
3161struct mlx5_ifc_set_roce_address_out_bits {
3162 u8 status[0x8];
b4ff3a36 3163 u8 reserved_at_8[0x18];
e281682b
SM		 3164
3165 u8 syndrome[0x20];
3166
b4ff3a36 3167 u8 reserved_at_40[0x40];
e281682b
SM		 3168};
3169
3170struct mlx5_ifc_set_roce_address_in_bits {
3171 u8 opcode[0x10];
b4ff3a36 3172 u8 reserved_at_10[0x10];
e281682b 3173
b4ff3a36 3174 u8 reserved_at_20[0x10];
e281682b
SM		 3175 u8 op_mod[0x10];
3176
3177 u8 roce_address_index[0x10];
b4ff3a36 3178 u8 reserved_at_50[0x10];
e281682b 3179
b4ff3a36 3180 u8 reserved_at_60[0x20];
e281682b
SM		 3181
3182 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3183};
3184
3185struct mlx5_ifc_set_mad_demux_out_bits {
3186 u8 status[0x8];
b4ff3a36 3187 u8 reserved_at_8[0x18];
e281682b
SM		 3188
3189 u8 syndrome[0x20];
3190
b4ff3a36 3191 u8 reserved_at_40[0x40];
e281682b
SM		 3192};
3193
3194enum {
3195 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
3196 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
3197};
3198
3199struct mlx5_ifc_set_mad_demux_in_bits {
3200 u8 opcode[0x10];
b4ff3a36 3201 u8 reserved_at_10[0x10];
e281682b 3202
b4ff3a36 3203 u8 reserved_at_20[0x10];
e281682b
SM		 3204 u8 op_mod[0x10];
3205
b4ff3a36 3206 u8 reserved_at_40[0x20];
e281682b 3207
b4ff3a36 3208 u8 reserved_at_60[0x6];
e281682b 3209 u8 demux_mode[0x2];
b4ff3a36 3210 u8 reserved_at_68[0x18];
e281682b
SM		 3211};
3212
3213struct mlx5_ifc_set_l2_table_entry_out_bits {
3214 u8 status[0x8];
b4ff3a36 3215 u8 reserved_at_8[0x18];
e281682b
SM		 3216
3217 u8 syndrome[0x20];
3218
b4ff3a36 3219 u8 reserved_at_40[0x40];
e281682b
SM		 3220};
3221
3222struct mlx5_ifc_set_l2_table_entry_in_bits {
3223 u8 opcode[0x10];
b4ff3a36 3224 u8 reserved_at_10[0x10];
e281682b 3225
b4ff3a36 3226 u8 reserved_at_20[0x10];
e281682b
SM		 3227 u8 op_mod[0x10];
3228
b4ff3a36 3229 u8 reserved_at_40[0x60];
e281682b 3230
b4ff3a36 3231 u8 reserved_at_a0[0x8];
e281682b
SM		 3232 u8 table_index[0x18];
3233
b4ff3a36 3234 u8 reserved_at_c0[0x20];
e281682b 3235
b4ff3a36 3236 u8 reserved_at_e0[0x13];
e281682b
SM		 3237 u8 vlan_valid[0x1];
3238 u8 vlan[0xc];
3239
3240 struct mlx5_ifc_mac_address_layout_bits mac_address;
3241
b4ff3a36 3242 u8 reserved_at_140[0xc0];
e281682b
SM		 3243};
3244
3245struct mlx5_ifc_set_issi_out_bits {
3246 u8 status[0x8];
b4ff3a36 3247 u8 reserved_at_8[0x18];
e281682b
SM		 3248
3249 u8 syndrome[0x20];
3250
b4ff3a36 3251 u8 reserved_at_40[0x40];
e281682b
SM		 3252};
3253
3254struct mlx5_ifc_set_issi_in_bits {
3255 u8 opcode[0x10];
b4ff3a36 3256 u8 reserved_at_10[0x10];
e281682b 3257
b4ff3a36 3258 u8 reserved_at_20[0x10];
e281682b
SM		 3259 u8 op_mod[0x10];
3260
b4ff3a36 3261 u8 reserved_at_40[0x10];
e281682b
SM		 3262 u8 current_issi[0x10];
3263
b4ff3a36 3264 u8 reserved_at_60[0x20];
e281682b
SM		 3265};
3266
3267struct mlx5_ifc_set_hca_cap_out_bits {
3268 u8 status[0x8];
b4ff3a36 3269 u8 reserved_at_8[0x18];
e281682b
SM		 3270
3271 u8 syndrome[0x20];
3272
b4ff3a36 3273 u8 reserved_at_40[0x40];
e281682b
SM		 3274};
3275
3276struct mlx5_ifc_set_hca_cap_in_bits {
3277 u8 opcode[0x10];
b4ff3a36 3278 u8 reserved_at_10[0x10];
e281682b 3279
b4ff3a36 3280 u8 reserved_at_20[0x10];
e281682b
SM		 3281 u8 op_mod[0x10];
3282
b4ff3a36 3283 u8 reserved_at_40[0x40];
e281682b
SM		 3284
3285 union mlx5_ifc_hca_cap_union_bits capability;
3286};
3287
26a81453
MG		 3288enum {
3289 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
3290 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
3291 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
3292 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
3293};
3294
e281682b
SM		 3295struct mlx5_ifc_set_fte_out_bits {
3296 u8 status[0x8];
b4ff3a36 3297 u8 reserved_at_8[0x18];
e281682b
SM		 3298
3299 u8 syndrome[0x20];
3300
b4ff3a36 3301 u8 reserved_at_40[0x40];
e281682b
SM		 3302};
3303
3304struct mlx5_ifc_set_fte_in_bits {
3305 u8 opcode[0x10];
b4ff3a36 3306 u8 reserved_at_10[0x10];
e281682b 3307
b4ff3a36 3308 u8 reserved_at_20[0x10];
e281682b
SM		 3309 u8 op_mod[0x10];
3310
7d5e1423
SM		 3311 u8 other_vport[0x1];
3312 u8 reserved_at_41[0xf];
3313 u8 vport_number[0x10];
3314
3315 u8 reserved_at_60[0x20];
e281682b
SM		 3316
3317 u8 table_type[0x8];
b4ff3a36 3318 u8 reserved_at_88[0x18];
e281682b 3319
b4ff3a36 3320 u8 reserved_at_a0[0x8];
e281682b
SM		 3321 u8 table_id[0x18];
3322
b4ff3a36 3323 u8 reserved_at_c0[0x18];
26a81453
MG		 3324 u8 modify_enable_mask[0x8];
3325
b4ff3a36 3326 u8 reserved_at_e0[0x20];
e281682b
SM		 3327
3328 u8 flow_index[0x20];
3329
b4ff3a36 3330 u8 reserved_at_120[0xe0];
e281682b
SM		 3331
3332 struct mlx5_ifc_flow_context_bits flow_context;
3333};
3334
3335struct mlx5_ifc_rts2rts_qp_out_bits {
3336 u8 status[0x8];
b4ff3a36 3337 u8 reserved_at_8[0x18];
e281682b
SM		 3338
3339 u8 syndrome[0x20];
3340
b4ff3a36 3341 u8 reserved_at_40[0x40];
e281682b
SM		 3342};
3343
3344struct mlx5_ifc_rts2rts_qp_in_bits {
3345 u8 opcode[0x10];
b4ff3a36 3346 u8 reserved_at_10[0x10];
e281682b 3347
b4ff3a36 3348 u8 reserved_at_20[0x10];
e281682b
SM		 3349 u8 op_mod[0x10];
3350
b4ff3a36 3351 u8 reserved_at_40[0x8];
e281682b
SM		 3352 u8 qpn[0x18];
3353
b4ff3a36 3354 u8 reserved_at_60[0x20];
e281682b
SM		 3355
3356 u8 opt_param_mask[0x20];
3357
b4ff3a36 3358 u8 reserved_at_a0[0x20];
e281682b
SM		 3359
3360 struct mlx5_ifc_qpc_bits qpc;
3361
b4ff3a36 3362 u8 reserved_at_800[0x80];
e281682b
SM		 3363};
3364
3365struct mlx5_ifc_rtr2rts_qp_out_bits {
3366 u8 status[0x8];
b4ff3a36 3367 u8 reserved_at_8[0x18];
e281682b
SM		 3368
3369 u8 syndrome[0x20];
3370
b4ff3a36 3371 u8 reserved_at_40[0x40];
e281682b
SM		 3372};
3373
3374struct mlx5_ifc_rtr2rts_qp_in_bits {
3375 u8 opcode[0x10];
b4ff3a36 3376 u8 reserved_at_10[0x10];
e281682b 3377
b4ff3a36 3378 u8 reserved_at_20[0x10];
e281682b
SM		 3379 u8 op_mod[0x10];
3380
b4ff3a36 3381 u8 reserved_at_40[0x8];
e281682b
SM		 3382 u8 qpn[0x18];
3383
b4ff3a36 3384 u8 reserved_at_60[0x20];
e281682b
SM		 3385
3386 u8 opt_param_mask[0x20];
3387
b4ff3a36 3388 u8 reserved_at_a0[0x20];
e281682b
SM		 3389
3390 struct mlx5_ifc_qpc_bits qpc;
3391
b4ff3a36 3392 u8 reserved_at_800[0x80];
e281682b
SM		 3393};
3394
3395struct mlx5_ifc_rst2init_qp_out_bits {
3396 u8 status[0x8];
b4ff3a36 3397 u8 reserved_at_8[0x18];
e281682b
SM		 3398
3399 u8 syndrome[0x20];
3400
b4ff3a36 3401 u8 reserved_at_40[0x40];
e281682b
SM		 3402};
3403
3404struct mlx5_ifc_rst2init_qp_in_bits {
3405 u8 opcode[0x10];
b4ff3a36 3406 u8 reserved_at_10[0x10];
e281682b 3407
b4ff3a36 3408 u8 reserved_at_20[0x10];
e281682b
SM		 3409 u8 op_mod[0x10];
3410
b4ff3a36 3411 u8 reserved_at_40[0x8];
e281682b
SM		 3412 u8 qpn[0x18];
3413
b4ff3a36 3414 u8 reserved_at_60[0x20];
e281682b
SM		 3415
3416 u8 opt_param_mask[0x20];
3417
b4ff3a36 3418 u8 reserved_at_a0[0x20];
e281682b
SM		 3419
3420 struct mlx5_ifc_qpc_bits qpc;
3421
b4ff3a36 3422 u8 reserved_at_800[0x80];
e281682b
SM		 3423};
3424
7486216b
SM		 3425struct mlx5_ifc_query_xrq_out_bits {
3426 u8 status[0x8];
3427 u8 reserved_at_8[0x18];
3428
3429 u8 syndrome[0x20];
3430
3431 u8 reserved_at_40[0x40];
3432
3433 struct mlx5_ifc_xrqc_bits xrq_context;
3434};
3435
3436struct mlx5_ifc_query_xrq_in_bits {
3437 u8 opcode[0x10];
3438 u8 reserved_at_10[0x10];
3439
3440 u8 reserved_at_20[0x10];
3441 u8 op_mod[0x10];
3442
3443 u8 reserved_at_40[0x8];
3444 u8 xrqn[0x18];
3445
3446 u8 reserved_at_60[0x20];
3447};
3448
e281682b
SM		 3449struct mlx5_ifc_query_xrc_srq_out_bits {
3450 u8 status[0x8];
b4ff3a36 3451 u8 reserved_at_8[0x18];
e281682b
SM		 3452
3453 u8 syndrome[0x20];
3454
b4ff3a36 3455 u8 reserved_at_40[0x40];
e281682b
SM		 3456
3457 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3458
b4ff3a36 3459 u8 reserved_at_280[0x600];
e281682b
SM		 3460
3461 u8 pas[0][0x40];
3462};
3463
3464struct mlx5_ifc_query_xrc_srq_in_bits {
3465 u8 opcode[0x10];
b4ff3a36 3466 u8 reserved_at_10[0x10];
e281682b 3467
b4ff3a36 3468 u8 reserved_at_20[0x10];
e281682b
SM		 3469 u8 op_mod[0x10];
3470
b4ff3a36 3471 u8 reserved_at_40[0x8];
e281682b
SM		 3472 u8 xrc_srqn[0x18];
3473
b4ff3a36 3474 u8 reserved_at_60[0x20];
e281682b
SM		 3475};
3476
3477enum {
3478 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
3479 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
3480};
3481
3482struct mlx5_ifc_query_vport_state_out_bits {
3483 u8 status[0x8];
b4ff3a36 3484 u8 reserved_at_8[0x18];
e281682b
SM		 3485
3486 u8 syndrome[0x20];
3487
b4ff3a36 3488 u8 reserved_at_40[0x20];
e281682b 3489
b4ff3a36 3490 u8 reserved_at_60[0x18];
e281682b
SM		 3491 u8 admin_state[0x4];
3492 u8 state[0x4];
3493};
3494
3495enum {
3496 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0,
e7546514 3497 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1,
e281682b
SM		 3498};
3499
3500struct mlx5_ifc_query_vport_state_in_bits {
3501 u8 opcode[0x10];
b4ff3a36 3502 u8 reserved_at_10[0x10];
e281682b 3503
b4ff3a36 3504 u8 reserved_at_20[0x10];
e281682b
SM		 3505 u8 op_mod[0x10];
3506
3507 u8 other_vport[0x1];
b4ff3a36 3508 u8 reserved_at_41[0xf];
e281682b
SM		 3509 u8 vport_number[0x10];
3510
b4ff3a36 3511 u8 reserved_at_60[0x20];
e281682b
SM		 3512};
3513
3514struct mlx5_ifc_query_vport_counter_out_bits {
3515 u8 status[0x8];
b4ff3a36 3516 u8 reserved_at_8[0x18];
e281682b
SM		 3517
3518 u8 syndrome[0x20];
3519
b4ff3a36 3520 u8 reserved_at_40[0x40];
e281682b
SM		 3521
3522 struct mlx5_ifc_traffic_counter_bits received_errors;
3523
3524 struct mlx5_ifc_traffic_counter_bits transmit_errors;
3525
3526 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3527
3528 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3529
3530 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3531
3532 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3533
3534 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3535
3536 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3537
3538 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3539
3540 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3541
3542 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3543
3544 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3545
b4ff3a36 3546 u8 reserved_at_680[0xa00];
e281682b
SM		 3547};
3548
3549enum {
3550 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
3551};
3552
3553struct mlx5_ifc_query_vport_counter_in_bits {
3554 u8 opcode[0x10];
b4ff3a36 3555 u8 reserved_at_10[0x10];
e281682b 3556
b4ff3a36 3557 u8 reserved_at_20[0x10];
e281682b
SM		 3558 u8 op_mod[0x10];
3559
3560 u8 other_vport[0x1];
b54ba277
MY		 3561 u8 reserved_at_41[0xb];
3562 u8 port_num[0x4];
e281682b
SM		 3563 u8 vport_number[0x10];
3564
b4ff3a36 3565 u8 reserved_at_60[0x60];
e281682b
SM		 3566
3567 u8 clear[0x1];
b4ff3a36 3568 u8 reserved_at_c1[0x1f];
e281682b 3569
b4ff3a36 3570 u8 reserved_at_e0[0x20];
e281682b
SM		 3571};
3572
3573struct mlx5_ifc_query_tis_out_bits {
3574 u8 status[0x8];
b4ff3a36 3575 u8 reserved_at_8[0x18];
e281682b
SM		 3576
3577 u8 syndrome[0x20];
3578
b4ff3a36 3579 u8 reserved_at_40[0x40];
e281682b
SM		 3580
3581 struct mlx5_ifc_tisc_bits tis_context;
3582};
3583
3584struct mlx5_ifc_query_tis_in_bits {
3585 u8 opcode[0x10];
b4ff3a36 3586 u8 reserved_at_10[0x10];
e281682b 3587
b4ff3a36 3588 u8 reserved_at_20[0x10];
e281682b
SM		 3589 u8 op_mod[0x10];
3590
b4ff3a36 3591 u8 reserved_at_40[0x8];
e281682b
SM		 3592 u8 tisn[0x18];
3593
b4ff3a36 3594 u8 reserved_at_60[0x20];
e281682b
SM		 3595};
3596
3597struct mlx5_ifc_query_tir_out_bits {
3598 u8 status[0x8];
b4ff3a36 3599 u8 reserved_at_8[0x18];
e281682b
SM		 3600
3601 u8 syndrome[0x20];
3602
b4ff3a36 3603 u8 reserved_at_40[0xc0];
e281682b
SM		 3604
3605 struct mlx5_ifc_tirc_bits tir_context;
3606};
3607
3608struct mlx5_ifc_query_tir_in_bits {
3609 u8 opcode[0x10];
b4ff3a36 3610 u8 reserved_at_10[0x10];
e281682b 3611
b4ff3a36 3612 u8 reserved_at_20[0x10];
e281682b
SM		 3613 u8 op_mod[0x10];
3614
b4ff3a36 3615 u8 reserved_at_40[0x8];
e281682b
SM		 3616 u8 tirn[0x18];
3617
b4ff3a36 3618 u8 reserved_at_60[0x20];
e281682b
SM		 3619};
3620
3621struct mlx5_ifc_query_srq_out_bits {
3622 u8 status[0x8];
b4ff3a36 3623 u8 reserved_at_8[0x18];
e281682b
SM		 3624
3625 u8 syndrome[0x20];
3626
b4ff3a36 3627 u8 reserved_at_40[0x40];
e281682b
SM		 3628
3629 struct mlx5_ifc_srqc_bits srq_context_entry;
3630
b4ff3a36 3631 u8 reserved_at_280[0x600];
e281682b
SM		 3632
3633 u8 pas[0][0x40];
3634};
3635
3636struct mlx5_ifc_query_srq_in_bits {
3637 u8 opcode[0x10];
b4ff3a36 3638 u8 reserved_at_10[0x10];
e281682b 3639
b4ff3a36 3640 u8 reserved_at_20[0x10];
e281682b
SM		 3641 u8 op_mod[0x10];
3642
b4ff3a36 3643 u8 reserved_at_40[0x8];
e281682b
SM		 3644 u8 srqn[0x18];
3645
b4ff3a36 3646 u8 reserved_at_60[0x20];
e281682b
SM		 3647};
3648
3649struct mlx5_ifc_query_sq_out_bits {
3650 u8 status[0x8];
b4ff3a36 3651 u8 reserved_at_8[0x18];
e281682b
SM		 3652
3653 u8 syndrome[0x20];
3654
b4ff3a36 3655 u8 reserved_at_40[0xc0];
e281682b
SM		 3656
3657 struct mlx5_ifc_sqc_bits sq_context;
3658};
3659
3660struct mlx5_ifc_query_sq_in_bits {
3661 u8 opcode[0x10];
b4ff3a36 3662 u8 reserved_at_10[0x10];
e281682b 3663
b4ff3a36 3664 u8 reserved_at_20[0x10];
e281682b
SM		 3665 u8 op_mod[0x10];
3666
b4ff3a36 3667 u8 reserved_at_40[0x8];
e281682b
SM		 3668 u8 sqn[0x18];
3669
b4ff3a36 3670 u8 reserved_at_60[0x20];
e281682b
SM		 3671};
3672
3673struct mlx5_ifc_query_special_contexts_out_bits {
3674 u8 status[0x8];
b4ff3a36 3675 u8 reserved_at_8[0x18];
e281682b
SM		 3676
3677 u8 syndrome[0x20];
3678
ec22eb53 3679 u8 dump_fill_mkey[0x20];
e281682b
SM		 3680
3681 u8 resd_lkey[0x20];
bcda1aca
AK		 3682
3683 u8 null_mkey[0x20];
3684
3685 u8 reserved_at_a0[0x60];
e281682b
SM		 3686};
3687
3688struct mlx5_ifc_query_special_contexts_in_bits {
3689 u8 opcode[0x10];
b4ff3a36 3690 u8 reserved_at_10[0x10];
e281682b 3691
b4ff3a36 3692 u8 reserved_at_20[0x10];
e281682b
SM		 3693 u8 op_mod[0x10];
3694
b4ff3a36 3695 u8 reserved_at_40[0x40];
e281682b
SM		 3696};
3697
813f8540
MHY		 3698struct mlx5_ifc_query_scheduling_element_out_bits {
3699 u8 opcode[0x10];
3700 u8 reserved_at_10[0x10];
3701
3702 u8 reserved_at_20[0x10];
3703 u8 op_mod[0x10];
3704
3705 u8 reserved_at_40[0xc0];
3706
3707 struct mlx5_ifc_scheduling_context_bits scheduling_context;
3708
3709 u8 reserved_at_300[0x100];
3710};
3711
3712enum {
3713 SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
3714};
3715
3716struct mlx5_ifc_query_scheduling_element_in_bits {
3717 u8 opcode[0x10];
3718 u8 reserved_at_10[0x10];
3719
3720 u8 reserved_at_20[0x10];
3721 u8 op_mod[0x10];
3722
3723 u8 scheduling_hierarchy[0x8];
3724 u8 reserved_at_48[0x18];
3725
3726 u8 scheduling_element_id[0x20];
3727
3728 u8 reserved_at_80[0x180];
3729};
3730
e281682b
SM		 3731struct mlx5_ifc_query_rqt_out_bits {
3732 u8 status[0x8];
b4ff3a36 3733 u8 reserved_at_8[0x18];
e281682b
SM		 3734
3735 u8 syndrome[0x20];
3736
b4ff3a36 3737 u8 reserved_at_40[0xc0];
e281682b
SM		 3738
3739 struct mlx5_ifc_rqtc_bits rqt_context;
3740};
3741
3742struct mlx5_ifc_query_rqt_in_bits {
3743 u8 opcode[0x10];
b4ff3a36 3744 u8 reserved_at_10[0x10];
e281682b 3745
b4ff3a36 3746 u8 reserved_at_20[0x10];
e281682b
SM		 3747 u8 op_mod[0x10];
3748
b4ff3a36 3749 u8 reserved_at_40[0x8];
e281682b
SM		 3750 u8 rqtn[0x18];
3751
b4ff3a36 3752 u8 reserved_at_60[0x20];
e281682b
SM		 3753};
3754
3755struct mlx5_ifc_query_rq_out_bits {
3756 u8 status[0x8];
b4ff3a36 3757 u8 reserved_at_8[0x18];
e281682b
SM		 3758
3759 u8 syndrome[0x20];
3760
b4ff3a36 3761 u8 reserved_at_40[0xc0];
e281682b
SM		 3762
3763 struct mlx5_ifc_rqc_bits rq_context;
3764};
3765
3766struct mlx5_ifc_query_rq_in_bits {
3767 u8 opcode[0x10];
b4ff3a36 3768 u8 reserved_at_10[0x10];
e281682b 3769
b4ff3a36 3770 u8 reserved_at_20[0x10];
e281682b
SM		 3771 u8 op_mod[0x10];
3772
b4ff3a36 3773 u8 reserved_at_40[0x8];
e281682b
SM		 3774 u8 rqn[0x18];
3775
b4ff3a36 3776 u8 reserved_at_60[0x20];
e281682b
SM		 3777};
3778
3779struct mlx5_ifc_query_roce_address_out_bits {
3780 u8 status[0x8];
b4ff3a36 3781 u8 reserved_at_8[0x18];
e281682b
SM		 3782
3783 u8 syndrome[0x20];
3784
b4ff3a36 3785 u8 reserved_at_40[0x40];
e281682b
SM		 3786
3787 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3788};
3789
3790struct mlx5_ifc_query_roce_address_in_bits {
3791 u8 opcode[0x10];
b4ff3a36 3792 u8 reserved_at_10[0x10];
e281682b 3793
b4ff3a36 3794 u8 reserved_at_20[0x10];
e281682b
SM		 3795 u8 op_mod[0x10];
3796
3797 u8 roce_address_index[0x10];
b4ff3a36 3798 u8 reserved_at_50[0x10];
e281682b 3799
b4ff3a36 3800 u8 reserved_at_60[0x20];
e281682b
SM		 3801};
3802
3803struct mlx5_ifc_query_rmp_out_bits {
3804 u8 status[0x8];
b4ff3a36 3805 u8 reserved_at_8[0x18];
e281682b
SM		 3806
3807 u8 syndrome[0x20];
3808
b4ff3a36 3809 u8 reserved_at_40[0xc0];
e281682b
SM		 3810
3811 struct mlx5_ifc_rmpc_bits rmp_context;
3812};
3813
3814struct mlx5_ifc_query_rmp_in_bits {
3815 u8 opcode[0x10];
b4ff3a36 3816 u8 reserved_at_10[0x10];
e281682b 3817
b4ff3a36 3818 u8 reserved_at_20[0x10];
e281682b
SM		 3819 u8 op_mod[0x10];
3820
b4ff3a36 3821 u8 reserved_at_40[0x8];
e281682b
SM		 3822 u8 rmpn[0x18];
3823
b4ff3a36 3824 u8 reserved_at_60[0x20];
e281682b
SM		 3825};
3826
3827struct mlx5_ifc_query_qp_out_bits {
3828 u8 status[0x8];
b4ff3a36 3829 u8 reserved_at_8[0x18];
e281682b
SM		 3830
3831 u8 syndrome[0x20];
3832
b4ff3a36 3833 u8 reserved_at_40[0x40];
e281682b
SM		 3834
3835 u8 opt_param_mask[0x20];
3836
b4ff3a36 3837 u8 reserved_at_a0[0x20];
e281682b
SM		 3838
3839 struct mlx5_ifc_qpc_bits qpc;
3840
b4ff3a36 3841 u8 reserved_at_800[0x80];
e281682b
SM		 3842
3843 u8 pas[0][0x40];
3844};
3845
3846struct mlx5_ifc_query_qp_in_bits {
3847 u8 opcode[0x10];
b4ff3a36 3848 u8 reserved_at_10[0x10];
e281682b 3849
b4ff3a36 3850 u8 reserved_at_20[0x10];
e281682b
SM		 3851 u8 op_mod[0x10];
3852
b4ff3a36 3853 u8 reserved_at_40[0x8];
e281682b
SM		 3854 u8 qpn[0x18];
3855
b4ff3a36 3856 u8 reserved_at_60[0x20];
e281682b
SM		 3857};
3858
3859struct mlx5_ifc_query_q_counter_out_bits {
3860 u8 status[0x8];
b4ff3a36 3861 u8 reserved_at_8[0x18];
e281682b
SM		 3862
3863 u8 syndrome[0x20];
3864
b4ff3a36 3865 u8 reserved_at_40[0x40];
e281682b
SM		 3866
3867 u8 rx_write_requests[0x20];
3868
b4ff3a36 3869 u8 reserved_at_a0[0x20];
e281682b
SM		 3870
3871 u8 rx_read_requests[0x20];
3872
b4ff3a36 3873 u8 reserved_at_e0[0x20];
e281682b
SM		 3874
3875 u8 rx_atomic_requests[0x20];
3876
b4ff3a36 3877 u8 reserved_at_120[0x20];
e281682b
SM		 3878
3879 u8 rx_dct_connect[0x20];
3880
b4ff3a36 3881 u8 reserved_at_160[0x20];
e281682b
SM		 3882
3883 u8 out_of_buffer[0x20];
3884
b4ff3a36 3885 u8 reserved_at_1a0[0x20];
e281682b
SM		 3886
3887 u8 out_of_sequence[0x20];
3888
7486216b
SM		 3889 u8 reserved_at_1e0[0x20];
3890
3891 u8 duplicate_request[0x20];
3892
3893 u8 reserved_at_220[0x20];
3894
3895 u8 rnr_nak_retry_err[0x20];
3896
3897 u8 reserved_at_260[0x20];
3898
3899 u8 packet_seq_err[0x20];
3900
3901 u8 reserved_at_2a0[0x20];
3902
3903 u8 implied_nak_seq_err[0x20];
3904
3905 u8 reserved_at_2e0[0x20];
3906
3907 u8 local_ack_timeout_err[0x20];
3908
3909 u8 reserved_at_320[0x4e0];
e281682b
SM		 3910};
3911
3912struct mlx5_ifc_query_q_counter_in_bits {
3913 u8 opcode[0x10];
b4ff3a36 3914 u8 reserved_at_10[0x10];
e281682b 3915
b4ff3a36 3916 u8 reserved_at_20[0x10];
e281682b
SM		 3917 u8 op_mod[0x10];
3918
b4ff3a36 3919 u8 reserved_at_40[0x80];
e281682b
SM		 3920
3921 u8 clear[0x1];
b4ff3a36 3922 u8 reserved_at_c1[0x1f];
e281682b 3923
b4ff3a36 3924 u8 reserved_at_e0[0x18];
e281682b
SM		 3925 u8 counter_set_id[0x8];
3926};
3927
3928struct mlx5_ifc_query_pages_out_bits {
3929 u8 status[0x8];
b4ff3a36 3930 u8 reserved_at_8[0x18];
e281682b
SM		 3931
3932 u8 syndrome[0x20];
3933
b4ff3a36 3934 u8 reserved_at_40[0x10];
e281682b
SM		 3935 u8 function_id[0x10];
3936
3937 u8 num_pages[0x20];
3938};
3939
3940enum {
3941 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
3942 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
3943 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
3944};
3945
3946struct mlx5_ifc_query_pages_in_bits {
3947 u8 opcode[0x10];
b4ff3a36 3948 u8 reserved_at_10[0x10];
e281682b 3949
b4ff3a36 3950 u8 reserved_at_20[0x10];
e281682b
SM		 3951 u8 op_mod[0x10];
3952
b4ff3a36 3953 u8 reserved_at_40[0x10];
e281682b
SM		 3954 u8 function_id[0x10];
3955
b4ff3a36 3956 u8 reserved_at_60[0x20];
e281682b
SM		 3957};
3958
3959struct mlx5_ifc_query_nic_vport_context_out_bits {
3960 u8 status[0x8];
b4ff3a36 3961 u8 reserved_at_8[0x18];
e281682b
SM		 3962
3963 u8 syndrome[0x20];
3964
b4ff3a36 3965 u8 reserved_at_40[0x40];
e281682b
SM		 3966
3967 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
3968};
3969
3970struct mlx5_ifc_query_nic_vport_context_in_bits {
3971 u8 opcode[0x10];
b4ff3a36 3972 u8 reserved_at_10[0x10];
e281682b 3973
b4ff3a36 3974 u8 reserved_at_20[0x10];
e281682b
SM		 3975 u8 op_mod[0x10];
3976
3977 u8 other_vport[0x1];
b4ff3a36 3978 u8 reserved_at_41[0xf];
e281682b
SM		 3979 u8 vport_number[0x10];
3980
b4ff3a36 3981 u8 reserved_at_60[0x5];
e281682b 3982 u8 allowed_list_type[0x3];
b4ff3a36 3983 u8 reserved_at_68[0x18];
e281682b
SM		 3984};
3985
3986struct mlx5_ifc_query_mkey_out_bits {
3987 u8 status[0x8];
b4ff3a36 3988 u8 reserved_at_8[0x18];
e281682b
SM		 3989
3990 u8 syndrome[0x20];
3991
b4ff3a36 3992 u8 reserved_at_40[0x40];
e281682b
SM		 3993
3994 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
3995
b4ff3a36 3996 u8 reserved_at_280[0x600];
e281682b
SM		 3997
3998 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
3999
4000 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
4001};
4002
4003struct mlx5_ifc_query_mkey_in_bits {
4004 u8 opcode[0x10];
b4ff3a36 4005 u8 reserved_at_10[0x10];
e281682b 4006
b4ff3a36 4007 u8 reserved_at_20[0x10];
e281682b
SM		 4008 u8 op_mod[0x10];
4009
b4ff3a36 4010 u8 reserved_at_40[0x8];
e281682b
SM		 4011 u8 mkey_index[0x18];
4012
4013 u8 pg_access[0x1];
b4ff3a36 4014 u8 reserved_at_61[0x1f];
e281682b
SM		 4015};
4016
4017struct mlx5_ifc_query_mad_demux_out_bits {
4018 u8 status[0x8];
b4ff3a36 4019 u8 reserved_at_8[0x18];
e281682b
SM		 4020
4021 u8 syndrome[0x20];
4022
b4ff3a36 4023 u8 reserved_at_40[0x40];
e281682b
SM		 4024
4025 u8 mad_dumux_parameters_block[0x20];
4026};
4027
4028struct mlx5_ifc_query_mad_demux_in_bits {
4029 u8 opcode[0x10];
b4ff3a36 4030 u8 reserved_at_10[0x10];
e281682b 4031
b4ff3a36 4032 u8 reserved_at_20[0x10];
e281682b
SM		 4033 u8 op_mod[0x10];
4034
b4ff3a36 4035 u8 reserved_at_40[0x40];
e281682b
SM		 4036};
4037
4038struct mlx5_ifc_query_l2_table_entry_out_bits {
4039 u8 status[0x8];
b4ff3a36 4040 u8 reserved_at_8[0x18];
e281682b
SM		 4041
4042 u8 syndrome[0x20];
4043
b4ff3a36 4044 u8 reserved_at_40[0xa0];
e281682b 4045
b4ff3a36 4046 u8 reserved_at_e0[0x13];
e281682b
SM		 4047 u8 vlan_valid[0x1];
4048 u8 vlan[0xc];
4049
4050 struct mlx5_ifc_mac_address_layout_bits mac_address;
4051
b4ff3a36 4052 u8 reserved_at_140[0xc0];
e281682b
SM		 4053};
4054
4055struct mlx5_ifc_query_l2_table_entry_in_bits {
4056 u8 opcode[0x10];
b4ff3a36 4057 u8 reserved_at_10[0x10];
e281682b 4058
b4ff3a36 4059 u8 reserved_at_20[0x10];
e281682b
SM		 4060 u8 op_mod[0x10];
4061
b4ff3a36 4062 u8 reserved_at_40[0x60];
e281682b 4063
b4ff3a36 4064 u8 reserved_at_a0[0x8];
e281682b
SM		 4065 u8 table_index[0x18];
4066
b4ff3a36 4067 u8 reserved_at_c0[0x140];
e281682b
SM		 4068};
4069
4070struct mlx5_ifc_query_issi_out_bits {
4071 u8 status[0x8];
b4ff3a36 4072 u8 reserved_at_8[0x18];
e281682b
SM		 4073
4074 u8 syndrome[0x20];
4075
b4ff3a36 4076 u8 reserved_at_40[0x10];
e281682b
SM		 4077 u8 current_issi[0x10];
4078
b4ff3a36 4079 u8 reserved_at_60[0xa0];
e281682b 4080
b4ff3a36 4081 u8 reserved_at_100[76][0x8];
e281682b
SM		 4082 u8 supported_issi_dw0[0x20];
4083};
4084
4085struct mlx5_ifc_query_issi_in_bits {
4086 u8 opcode[0x10];
b4ff3a36 4087 u8 reserved_at_10[0x10];
e281682b 4088
b4ff3a36 4089 u8 reserved_at_20[0x10];
e281682b
SM		 4090 u8 op_mod[0x10];
4091
b4ff3a36 4092 u8 reserved_at_40[0x40];
e281682b
SM		 4093};
4094
0dbc6fe0
SM		 4095struct mlx5_ifc_set_driver_version_out_bits {
4096 u8 status[0x8];
4097 u8 reserved_0[0x18];
4098
4099 u8 syndrome[0x20];
4100 u8 reserved_1[0x40];
4101};
4102
4103struct mlx5_ifc_set_driver_version_in_bits {
4104 u8 opcode[0x10];
4105 u8 reserved_0[0x10];
4106
4107 u8 reserved_1[0x10];
4108 u8 op_mod[0x10];
4109
4110 u8 reserved_2[0x40];
4111 u8 driver_version[64][0x8];
4112};
4113
e281682b
SM		 4114struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4115 u8 status[0x8];
b4ff3a36 4116 u8 reserved_at_8[0x18];
e281682b
SM		 4117
4118 u8 syndrome[0x20];
4119
b4ff3a36 4120 u8 reserved_at_40[0x40];
e281682b
SM		 4121
4122 struct mlx5_ifc_pkey_bits pkey[0];
4123};
4124
4125struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4126 u8 opcode[0x10];
b4ff3a36 4127 u8 reserved_at_10[0x10];
e281682b 4128
b4ff3a36 4129 u8 reserved_at_20[0x10];
e281682b
SM		 4130 u8 op_mod[0x10];
4131
4132 u8 other_vport[0x1];
b4ff3a36 4133 u8 reserved_at_41[0xb];
707c4602 4134 u8 port_num[0x4];
e281682b
SM		 4135 u8 vport_number[0x10];
4136
b4ff3a36 4137 u8 reserved_at_60[0x10];
e281682b
SM		 4138 u8 pkey_index[0x10];
4139};
4140
eff901d3
EC		 4141enum {
4142 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
4143 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
4144 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4145};
4146
e281682b
SM		 4147struct mlx5_ifc_query_hca_vport_gid_out_bits {
4148 u8 status[0x8];
b4ff3a36 4149 u8 reserved_at_8[0x18];
e281682b
SM		 4150
4151 u8 syndrome[0x20];
4152
b4ff3a36 4153 u8 reserved_at_40[0x20];
e281682b
SM		 4154
4155 u8 gids_num[0x10];
b4ff3a36 4156 u8 reserved_at_70[0x10];
e281682b
SM		 4157
4158 struct mlx5_ifc_array128_auto_bits gid[0];
4159};
4160
4161struct mlx5_ifc_query_hca_vport_gid_in_bits {
4162 u8 opcode[0x10];
b4ff3a36 4163 u8 reserved_at_10[0x10];
e281682b 4164
b4ff3a36 4165 u8 reserved_at_20[0x10];
e281682b
SM		 4166 u8 op_mod[0x10];
4167
4168 u8 other_vport[0x1];
b4ff3a36 4169 u8 reserved_at_41[0xb];
707c4602 4170 u8 port_num[0x4];
e281682b
SM		 4171 u8 vport_number[0x10];
4172
b4ff3a36 4173 u8 reserved_at_60[0x10];
e281682b
SM		 4174 u8 gid_index[0x10];
4175};
4176
4177struct mlx5_ifc_query_hca_vport_context_out_bits {
4178 u8 status[0x8];
b4ff3a36 4179 u8 reserved_at_8[0x18];
e281682b
SM		 4180
4181 u8 syndrome[0x20];
4182
b4ff3a36 4183 u8 reserved_at_40[0x40];
e281682b
SM		 4184
4185 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4186};
4187
4188struct mlx5_ifc_query_hca_vport_context_in_bits {
4189 u8 opcode[0x10];
b4ff3a36 4190 u8 reserved_at_10[0x10];
e281682b 4191
b4ff3a36 4192 u8 reserved_at_20[0x10];
e281682b
SM		 4193 u8 op_mod[0x10];
4194
4195 u8 other_vport[0x1];
b4ff3a36 4196 u8 reserved_at_41[0xb];
707c4602 4197 u8 port_num[0x4];
e281682b
SM		 4198 u8 vport_number[0x10];
4199
b4ff3a36 4200 u8 reserved_at_60[0x20];
e281682b
SM		 4201};
4202
4203struct mlx5_ifc_query_hca_cap_out_bits {
4204 u8 status[0x8];
b4ff3a36 4205 u8 reserved_at_8[0x18];
e281682b
SM		 4206
4207 u8 syndrome[0x20];
4208
b4ff3a36 4209 u8 reserved_at_40[0x40];
e281682b
SM		 4210
4211 union mlx5_ifc_hca_cap_union_bits capability;
4212};
4213
4214struct mlx5_ifc_query_hca_cap_in_bits {
4215 u8 opcode[0x10];
b4ff3a36 4216 u8 reserved_at_10[0x10];
e281682b 4217
b4ff3a36 4218 u8 reserved_at_20[0x10];
e281682b
SM		 4219 u8 op_mod[0x10];
4220
b4ff3a36 4221 u8 reserved_at_40[0x40];
e281682b
SM		 4222};
4223
4224struct mlx5_ifc_query_flow_table_out_bits {
4225 u8 status[0x8];
b4ff3a36 4226 u8 reserved_at_8[0x18];
e281682b
SM		 4227
4228 u8 syndrome[0x20];
4229
b4ff3a36 4230 u8 reserved_at_40[0x80];
e281682b 4231
b4ff3a36 4232 u8 reserved_at_c0[0x8];
e281682b 4233 u8 level[0x8];
b4ff3a36 4234 u8 reserved_at_d0[0x8];
e281682b
SM		 4235 u8 log_size[0x8];
4236
b4ff3a36 4237 u8 reserved_at_e0[0x120];
e281682b
SM		 4238};
4239
4240struct mlx5_ifc_query_flow_table_in_bits {
4241 u8 opcode[0x10];
b4ff3a36 4242 u8 reserved_at_10[0x10];
e281682b 4243
b4ff3a36 4244 u8 reserved_at_20[0x10];
e281682b
SM		 4245 u8 op_mod[0x10];
4246
b4ff3a36 4247 u8 reserved_at_40[0x40];
e281682b
SM		 4248
4249 u8 table_type[0x8];
b4ff3a36 4250 u8 reserved_at_88[0x18];
e281682b 4251
b4ff3a36 4252 u8 reserved_at_a0[0x8];
e281682b
SM		 4253 u8 table_id[0x18];
4254
b4ff3a36 4255 u8 reserved_at_c0[0x140];
e281682b
SM		 4256};
4257
4258struct mlx5_ifc_query_fte_out_bits {
4259 u8 status[0x8];
b4ff3a36 4260 u8 reserved_at_8[0x18];
e281682b
SM		 4261
4262 u8 syndrome[0x20];
4263
b4ff3a36 4264 u8 reserved_at_40[0x1c0];
e281682b
SM		 4265
4266 struct mlx5_ifc_flow_context_bits flow_context;
4267};
4268
4269struct mlx5_ifc_query_fte_in_bits {
4270 u8 opcode[0x10];
b4ff3a36 4271 u8 reserved_at_10[0x10];
e281682b 4272
b4ff3a36 4273 u8 reserved_at_20[0x10];
e281682b
SM		 4274 u8 op_mod[0x10];
4275
b4ff3a36 4276 u8 reserved_at_40[0x40];
e281682b
SM		 4277
4278 u8 table_type[0x8];
b4ff3a36 4279 u8 reserved_at_88[0x18];
e281682b 4280
b4ff3a36 4281 u8 reserved_at_a0[0x8];
e281682b
SM		 4282 u8 table_id[0x18];
4283
b4ff3a36 4284 u8 reserved_at_c0[0x40];
e281682b
SM		 4285
4286 u8 flow_index[0x20];
4287
b4ff3a36 4288 u8 reserved_at_120[0xe0];
e281682b
SM		 4289};
4290
4291enum {
4292 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
4293 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
4294 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
4295};
4296
4297struct mlx5_ifc_query_flow_group_out_bits {
4298 u8 status[0x8];
b4ff3a36 4299 u8 reserved_at_8[0x18];
e281682b
SM		 4300
4301 u8 syndrome[0x20];
4302
b4ff3a36 4303 u8 reserved_at_40[0xa0];
e281682b
SM		 4304
4305 u8 start_flow_index[0x20];
4306
b4ff3a36 4307 u8 reserved_at_100[0x20];
e281682b
SM		 4308
4309 u8 end_flow_index[0x20];
4310
b4ff3a36 4311 u8 reserved_at_140[0xa0];
e281682b 4312
b4ff3a36 4313 u8 reserved_at_1e0[0x18];
e281682b
SM		 4314 u8 match_criteria_enable[0x8];
4315
4316 struct mlx5_ifc_fte_match_param_bits match_criteria;
4317
b4ff3a36 4318 u8 reserved_at_1200[0xe00];
e281682b
SM		 4319};
4320
4321struct mlx5_ifc_query_flow_group_in_bits {
4322 u8 opcode[0x10];
b4ff3a36 4323 u8 reserved_at_10[0x10];
e281682b 4324
b4ff3a36 4325 u8 reserved_at_20[0x10];
e281682b
SM		 4326 u8 op_mod[0x10];
4327
b4ff3a36 4328 u8 reserved_at_40[0x40];
e281682b
SM		 4329
4330 u8 table_type[0x8];
b4ff3a36 4331 u8 reserved_at_88[0x18];
e281682b 4332
b4ff3a36 4333 u8 reserved_at_a0[0x8];
e281682b
SM		 4334 u8 table_id[0x18];
4335
4336 u8 group_id[0x20];
4337
b4ff3a36 4338 u8 reserved_at_e0[0x120];
e281682b
SM		 4339};
4340
9dc0b289
AV		 4341struct mlx5_ifc_query_flow_counter_out_bits {
4342 u8 status[0x8];
4343 u8 reserved_at_8[0x18];
4344
4345 u8 syndrome[0x20];
4346
4347 u8 reserved_at_40[0x40];
4348
4349 struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4350};
4351
4352struct mlx5_ifc_query_flow_counter_in_bits {
4353 u8 opcode[0x10];
4354 u8 reserved_at_10[0x10];
4355
4356 u8 reserved_at_20[0x10];
4357 u8 op_mod[0x10];
4358
4359 u8 reserved_at_40[0x80];
4360
4361 u8 clear[0x1];
4362 u8 reserved_at_c1[0xf];
4363 u8 num_of_counters[0x10];
4364
4365 u8 reserved_at_e0[0x10];
4366 u8 flow_counter_id[0x10];
4367};
4368
d6666753
SM		 4369struct mlx5_ifc_query_esw_vport_context_out_bits {
4370 u8 status[0x8];
b4ff3a36 4371 u8 reserved_at_8[0x18];
d6666753
SM		 4372
4373 u8 syndrome[0x20];
4374
b4ff3a36 4375 u8 reserved_at_40[0x40];
d6666753
SM		 4376
4377 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4378};
4379
4380struct mlx5_ifc_query_esw_vport_context_in_bits {
4381 u8 opcode[0x10];
b4ff3a36 4382 u8 reserved_at_10[0x10];
d6666753 4383
b4ff3a36 4384 u8 reserved_at_20[0x10];
d6666753
SM		 4385 u8 op_mod[0x10];
4386
4387 u8 other_vport[0x1];
b4ff3a36 4388 u8 reserved_at_41[0xf];
d6666753
SM		 4389 u8 vport_number[0x10];
4390
b4ff3a36 4391 u8 reserved_at_60[0x20];
d6666753
SM		 4392};
4393
4394struct mlx5_ifc_modify_esw_vport_context_out_bits {
4395 u8 status[0x8];
b4ff3a36 4396 u8 reserved_at_8[0x18];
d6666753
SM		 4397
4398 u8 syndrome[0x20];
4399
b4ff3a36 4400 u8 reserved_at_40[0x40];
d6666753
SM		 4401};
4402
4403struct mlx5_ifc_esw_vport_context_fields_select_bits {
b4ff3a36 4404 u8 reserved_at_0[0x1c];
d6666753
SM		 4405 u8 vport_cvlan_insert[0x1];
4406 u8 vport_svlan_insert[0x1];
4407 u8 vport_cvlan_strip[0x1];
4408 u8 vport_svlan_strip[0x1];
4409};
4410
4411struct mlx5_ifc_modify_esw_vport_context_in_bits {
4412 u8 opcode[0x10];
b4ff3a36 4413 u8 reserved_at_10[0x10];
d6666753 4414
b4ff3a36 4415 u8 reserved_at_20[0x10];
d6666753
SM		 4416 u8 op_mod[0x10];
4417
4418 u8 other_vport[0x1];
b4ff3a36 4419 u8 reserved_at_41[0xf];
d6666753
SM		 4420 u8 vport_number[0x10];
4421
4422 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4423
4424 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4425};
4426
e281682b
SM		 4427struct mlx5_ifc_query_eq_out_bits {
4428 u8 status[0x8];
b4ff3a36 4429 u8 reserved_at_8[0x18];
e281682b
SM		 4430
4431 u8 syndrome[0x20];
4432
b4ff3a36 4433 u8 reserved_at_40[0x40];
e281682b
SM		 4434
4435 struct mlx5_ifc_eqc_bits eq_context_entry;
4436
b4ff3a36 4437 u8 reserved_at_280[0x40];
e281682b
SM		 4438
4439 u8 event_bitmask[0x40];
4440
b4ff3a36 4441 u8 reserved_at_300[0x580];
e281682b
SM		 4442
4443 u8 pas[0][0x40];
4444};
4445
4446struct mlx5_ifc_query_eq_in_bits {
4447 u8 opcode[0x10];
b4ff3a36 4448 u8 reserved_at_10[0x10];
e281682b 4449
b4ff3a36 4450 u8 reserved_at_20[0x10];
e281682b
SM		 4451 u8 op_mod[0x10];
4452
b4ff3a36 4453 u8 reserved_at_40[0x18];
e281682b
SM		 4454 u8 eq_number[0x8];
4455
b4ff3a36 4456 u8 reserved_at_60[0x20];
e281682b
SM		 4457};
4458
7adbde20
HHZ		 4459struct mlx5_ifc_encap_header_in_bits {
4460 u8 reserved_at_0[0x5];
4461 u8 header_type[0x3];
4462 u8 reserved_at_8[0xe];
4463 u8 encap_header_size[0xa];
4464
4465 u8 reserved_at_20[0x10];
4466 u8 encap_header[2][0x8];
4467
4468 u8 more_encap_header[0][0x8];
4469};
4470
4471struct mlx5_ifc_query_encap_header_out_bits {
4472 u8 status[0x8];
4473 u8 reserved_at_8[0x18];
4474
4475 u8 syndrome[0x20];
4476
4477 u8 reserved_at_40[0xa0];
4478
4479 struct mlx5_ifc_encap_header_in_bits encap_header[0];
4480};
4481
4482struct mlx5_ifc_query_encap_header_in_bits {
4483 u8 opcode[0x10];
4484 u8 reserved_at_10[0x10];
4485
4486 u8 reserved_at_20[0x10];
4487 u8 op_mod[0x10];
4488
4489 u8 encap_id[0x20];
4490
4491 u8 reserved_at_60[0xa0];
4492};
4493
4494struct mlx5_ifc_alloc_encap_header_out_bits {
4495 u8 status[0x8];
4496 u8 reserved_at_8[0x18];
4497
4498 u8 syndrome[0x20];
4499
4500 u8 encap_id[0x20];
4501
4502 u8 reserved_at_60[0x20];
4503};
4504
4505struct mlx5_ifc_alloc_encap_header_in_bits {
4506 u8 opcode[0x10];
4507 u8 reserved_at_10[0x10];
4508
4509 u8 reserved_at_20[0x10];
4510 u8 op_mod[0x10];
4511
4512 u8 reserved_at_40[0xa0];
4513
4514 struct mlx5_ifc_encap_header_in_bits encap_header;
4515};
4516
4517struct mlx5_ifc_dealloc_encap_header_out_bits {
4518 u8 status[0x8];
4519 u8 reserved_at_8[0x18];
4520
4521 u8 syndrome[0x20];
4522
4523 u8 reserved_at_40[0x40];
4524};
4525
4526struct mlx5_ifc_dealloc_encap_header_in_bits {
4527 u8 opcode[0x10];
4528 u8 reserved_at_10[0x10];
4529
4530 u8 reserved_20[0x10];
4531 u8 op_mod[0x10];
4532
4533 u8 encap_id[0x20];
4534
4535 u8 reserved_60[0x20];
4536};
4537
e281682b
SM		 4538struct mlx5_ifc_query_dct_out_bits {
4539 u8 status[0x8];
b4ff3a36 4540 u8 reserved_at_8[0x18];
e281682b
SM		 4541
4542 u8 syndrome[0x20];
4543
b4ff3a36 4544 u8 reserved_at_40[0x40];
e281682b
SM		 4545
4546 struct mlx5_ifc_dctc_bits dct_context_entry;
4547
b4ff3a36 4548 u8 reserved_at_280[0x180];
e281682b
SM		 4549};
4550
4551struct mlx5_ifc_query_dct_in_bits {
4552 u8 opcode[0x10];
b4ff3a36 4553 u8 reserved_at_10[0x10];
e281682b 4554
b4ff3a36 4555 u8 reserved_at_20[0x10];
e281682b
SM		 4556 u8 op_mod[0x10];
4557
b4ff3a36 4558 u8 reserved_at_40[0x8];
e281682b
SM		 4559 u8 dctn[0x18];
4560
b4ff3a36 4561 u8 reserved_at_60[0x20];
e281682b
SM		 4562};
4563
4564struct mlx5_ifc_query_cq_out_bits {
4565 u8 status[0x8];
b4ff3a36 4566 u8 reserved_at_8[0x18];
e281682b
SM		 4567
4568 u8 syndrome[0x20];
4569
b4ff3a36 4570 u8 reserved_at_40[0x40];
e281682b
SM		 4571
4572 struct mlx5_ifc_cqc_bits cq_context;
4573
b4ff3a36 4574 u8 reserved_at_280[0x600];
e281682b
SM		 4575
4576 u8 pas[0][0x40];
4577};
4578
4579struct mlx5_ifc_query_cq_in_bits {
4580 u8 opcode[0x10];
b4ff3a36 4581 u8 reserved_at_10[0x10];
e281682b 4582
b4ff3a36 4583 u8 reserved_at_20[0x10];
e281682b
SM		 4584 u8 op_mod[0x10];
4585
b4ff3a36 4586 u8 reserved_at_40[0x8];
e281682b
SM		 4587 u8 cqn[0x18];
4588
b4ff3a36 4589 u8 reserved_at_60[0x20];
e281682b
SM		 4590};
4591
4592struct mlx5_ifc_query_cong_status_out_bits {
4593 u8 status[0x8];
b4ff3a36 4594 u8 reserved_at_8[0x18];
e281682b
SM		 4595
4596 u8 syndrome[0x20];
4597
b4ff3a36 4598 u8 reserved_at_40[0x20];
e281682b
SM		 4599
4600 u8 enable[0x1];
4601 u8 tag_enable[0x1];
b4ff3a36 4602 u8 reserved_at_62[0x1e];
e281682b
SM		 4603};
4604
4605struct mlx5_ifc_query_cong_status_in_bits {
4606 u8 opcode[0x10];
b4ff3a36 4607 u8 reserved_at_10[0x10];
e281682b 4608
b4ff3a36 4609 u8 reserved_at_20[0x10];
e281682b
SM		 4610 u8 op_mod[0x10];
4611
b4ff3a36 4612 u8 reserved_at_40[0x18];
e281682b
SM		 4613 u8 priority[0x4];
4614 u8 cong_protocol[0x4];
4615
b4ff3a36 4616 u8 reserved_at_60[0x20];
e281682b
SM		 4617};
4618
4619struct mlx5_ifc_query_cong_statistics_out_bits {
4620 u8 status[0x8];
b4ff3a36 4621 u8 reserved_at_8[0x18];
e281682b
SM		 4622
4623 u8 syndrome[0x20];
4624
b4ff3a36 4625 u8 reserved_at_40[0x40];
e281682b
SM		 4626
4627 u8 cur_flows[0x20];
4628
4629 u8 sum_flows[0x20];
4630
4631 u8 cnp_ignored_high[0x20];
4632
4633 u8 cnp_ignored_low[0x20];
4634
4635 u8 cnp_handled_high[0x20];
4636
4637 u8 cnp_handled_low[0x20];
4638
b4ff3a36 4639 u8 reserved_at_140[0x100];
e281682b
SM		 4640
4641 u8 time_stamp_high[0x20];
4642
4643 u8 time_stamp_low[0x20];
4644
4645 u8 accumulators_period[0x20];
4646
4647 u8 ecn_marked_roce_packets_high[0x20];
4648
4649 u8 ecn_marked_roce_packets_low[0x20];
4650
4651 u8 cnps_sent_high[0x20];
4652
4653 u8 cnps_sent_low[0x20];
4654
b4ff3a36 4655 u8 reserved_at_320[0x560];
e281682b
SM		 4656};
4657
4658struct mlx5_ifc_query_cong_statistics_in_bits {
4659 u8 opcode[0x10];
b4ff3a36 4660 u8 reserved_at_10[0x10];
e281682b 4661
b4ff3a36 4662 u8 reserved_at_20[0x10];
e281682b
SM		 4663 u8 op_mod[0x10];
4664
4665 u8 clear[0x1];
b4ff3a36 4666 u8 reserved_at_41[0x1f];
e281682b 4667
b4ff3a36 4668 u8 reserved_at_60[0x20];
e281682b
SM		 4669};
4670
4671struct mlx5_ifc_query_cong_params_out_bits {
4672 u8 status[0x8];
b4ff3a36 4673 u8 reserved_at_8[0x18];
e281682b
SM		 4674
4675 u8 syndrome[0x20];
4676
b4ff3a36 4677 u8 reserved_at_40[0x40];
e281682b
SM		 4678
4679 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4680};
4681
4682struct mlx5_ifc_query_cong_params_in_bits {
4683 u8 opcode[0x10];
b4ff3a36 4684 u8 reserved_at_10[0x10];
e281682b 4685
b4ff3a36 4686 u8 reserved_at_20[0x10];
e281682b
SM		 4687 u8 op_mod[0x10];
4688
b4ff3a36 4689 u8 reserved_at_40[0x1c];
e281682b
SM		 4690 u8 cong_protocol[0x4];
4691
b4ff3a36 4692 u8 reserved_at_60[0x20];
e281682b
SM		 4693};
4694
4695struct mlx5_ifc_query_adapter_out_bits {
4696 u8 status[0x8];
b4ff3a36 4697 u8 reserved_at_8[0x18];
e281682b
SM		 4698
4699 u8 syndrome[0x20];
4700
b4ff3a36 4701 u8 reserved_at_40[0x40];
e281682b
SM		 4702
4703 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4704};
4705
4706struct mlx5_ifc_query_adapter_in_bits {
4707 u8 opcode[0x10];
b4ff3a36 4708 u8 reserved_at_10[0x10];
e281682b 4709
b4ff3a36 4710 u8 reserved_at_20[0x10];
e281682b
SM		 4711 u8 op_mod[0x10];
4712
b4ff3a36 4713 u8 reserved_at_40[0x40];
e281682b
SM		 4714};
4715
4716struct mlx5_ifc_qp_2rst_out_bits {
4717 u8 status[0x8];
b4ff3a36 4718 u8 reserved_at_8[0x18];
e281682b
SM		 4719
4720 u8 syndrome[0x20];
4721
b4ff3a36 4722 u8 reserved_at_40[0x40];
e281682b
SM		 4723};
4724
4725struct mlx5_ifc_qp_2rst_in_bits {
4726 u8 opcode[0x10];
b4ff3a36 4727 u8 reserved_at_10[0x10];
e281682b 4728
b4ff3a36 4729 u8 reserved_at_20[0x10];
e281682b
SM		 4730 u8 op_mod[0x10];
4731
b4ff3a36 4732 u8 reserved_at_40[0x8];
e281682b
SM		 4733 u8 qpn[0x18];
4734
b4ff3a36 4735 u8 reserved_at_60[0x20];
e281682b
SM		 4736};
4737
4738struct mlx5_ifc_qp_2err_out_bits {
4739 u8 status[0x8];
b4ff3a36 4740 u8 reserved_at_8[0x18];
e281682b
SM		 4741
4742 u8 syndrome[0x20];
4743
b4ff3a36 4744 u8 reserved_at_40[0x40];
e281682b
SM		 4745};
4746
4747struct mlx5_ifc_qp_2err_in_bits {
4748 u8 opcode[0x10];
b4ff3a36 4749 u8 reserved_at_10[0x10];
e281682b 4750
b4ff3a36 4751 u8 reserved_at_20[0x10];
e281682b
SM		 4752 u8 op_mod[0x10];
4753
b4ff3a36 4754 u8 reserved_at_40[0x8];
e281682b
SM		 4755 u8 qpn[0x18];
4756
b4ff3a36 4757 u8 reserved_at_60[0x20];
e281682b
SM		 4758};
4759
4760struct mlx5_ifc_page_fault_resume_out_bits {
4761 u8 status[0x8];
b4ff3a36 4762 u8 reserved_at_8[0x18];
e281682b
SM		 4763
4764 u8 syndrome[0x20];
4765
b4ff3a36 4766 u8 reserved_at_40[0x40];
e281682b
SM		 4767};
4768
4769struct mlx5_ifc_page_fault_resume_in_bits {
4770 u8 opcode[0x10];
b4ff3a36 4771 u8 reserved_at_10[0x10];
e281682b 4772
b4ff3a36 4773 u8 reserved_at_20[0x10];
e281682b
SM		 4774 u8 op_mod[0x10];
4775
4776 u8 error[0x1];
b4ff3a36 4777 u8 reserved_at_41[0x4];
e281682b
SM		 4778 u8 rdma[0x1];
4779 u8 read_write[0x1];
4780 u8 req_res[0x1];
4781 u8 qpn[0x18];
4782
b4ff3a36 4783 u8 reserved_at_60[0x20];
e281682b
SM		 4784};
4785
4786struct mlx5_ifc_nop_out_bits {
4787 u8 status[0x8];
b4ff3a36 4788 u8 reserved_at_8[0x18];
e281682b
SM		 4789
4790 u8 syndrome[0x20];
4791
b4ff3a36 4792 u8 reserved_at_40[0x40];
e281682b
SM		 4793};
4794
4795struct mlx5_ifc_nop_in_bits {
4796 u8 opcode[0x10];
b4ff3a36 4797 u8 reserved_at_10[0x10];
e281682b 4798
b4ff3a36 4799 u8 reserved_at_20[0x10];
e281682b
SM		 4800 u8 op_mod[0x10];
4801
b4ff3a36 4802 u8 reserved_at_40[0x40];
e281682b
SM		 4803};
4804
4805struct mlx5_ifc_modify_vport_state_out_bits {
4806 u8 status[0x8];
b4ff3a36 4807 u8 reserved_at_8[0x18];
e281682b
SM		 4808
4809 u8 syndrome[0x20];
4810
b4ff3a36 4811 u8 reserved_at_40[0x40];
e281682b
SM		 4812};
4813
4814struct mlx5_ifc_modify_vport_state_in_bits {
4815 u8 opcode[0x10];
b4ff3a36 4816 u8 reserved_at_10[0x10];
e281682b 4817
b4ff3a36 4818 u8 reserved_at_20[0x10];
e281682b
SM		 4819 u8 op_mod[0x10];
4820
4821 u8 other_vport[0x1];
b4ff3a36 4822 u8 reserved_at_41[0xf];
e281682b
SM		 4823 u8 vport_number[0x10];
4824
b4ff3a36 4825 u8 reserved_at_60[0x18];
e281682b 4826 u8 admin_state[0x4];
b4ff3a36 4827 u8 reserved_at_7c[0x4];
e281682b
SM		 4828};
4829
4830struct mlx5_ifc_modify_tis_out_bits {
4831 u8 status[0x8];
b4ff3a36 4832 u8 reserved_at_8[0x18];
e281682b
SM		 4833
4834 u8 syndrome[0x20];
4835
b4ff3a36 4836 u8 reserved_at_40[0x40];
e281682b
SM		 4837};
4838
75850d0b 4839struct mlx5_ifc_modify_tis_bitmask_bits {
b4ff3a36 4840 u8 reserved_at_0[0x20];
75850d0b 4841
84df61eb
AH		 4842 u8 reserved_at_20[0x1d];
4843 u8 lag_tx_port_affinity[0x1];
4844 u8 strict_lag_tx_port_affinity[0x1];
75850d0b 4845 u8 prio[0x1];
4846};
4847
e281682b
SM		 4848struct mlx5_ifc_modify_tis_in_bits {
4849 u8 opcode[0x10];
b4ff3a36 4850 u8 reserved_at_10[0x10];
e281682b 4851
b4ff3a36 4852 u8 reserved_at_20[0x10];
e281682b
SM		 4853 u8 op_mod[0x10];
4854
b4ff3a36 4855 u8 reserved_at_40[0x8];
e281682b
SM		 4856 u8 tisn[0x18];
4857
b4ff3a36 4858 u8 reserved_at_60[0x20];
e281682b 4859
75850d0b 4860 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
e281682b 4861
b4ff3a36 4862 u8 reserved_at_c0[0x40];
e281682b
SM		 4863
4864 struct mlx5_ifc_tisc_bits ctx;
4865};
4866
d9eea403 4867struct mlx5_ifc_modify_tir_bitmask_bits {
b4ff3a36 4868 u8 reserved_at_0[0x20];
d9eea403 4869
b4ff3a36 4870 u8 reserved_at_20[0x1b];
66189961 4871 u8 self_lb_en[0x1];
bdfc028d
TT		 4872 u8 reserved_at_3c[0x1];
4873 u8 hash[0x1];
4874 u8 reserved_at_3e[0x1];
d9eea403
AS		 4875 u8 lro[0x1];
4876};
4877
e281682b
SM		 4878struct mlx5_ifc_modify_tir_out_bits {
4879 u8 status[0x8];
b4ff3a36 4880 u8 reserved_at_8[0x18];
e281682b
SM		 4881
4882 u8 syndrome[0x20];
4883
b4ff3a36 4884 u8 reserved_at_40[0x40];
e281682b
SM		 4885};
4886
4887struct mlx5_ifc_modify_tir_in_bits {
4888 u8 opcode[0x10];
b4ff3a36 4889 u8 reserved_at_10[0x10];
e281682b 4890
b4ff3a36 4891 u8 reserved_at_20[0x10];
e281682b
SM		 4892 u8 op_mod[0x10];
4893
b4ff3a36 4894 u8 reserved_at_40[0x8];
e281682b
SM		 4895 u8 tirn[0x18];
4896
b4ff3a36 4897 u8 reserved_at_60[0x20];
e281682b 4898
d9eea403 4899 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
e281682b 4900
b4ff3a36 4901 u8 reserved_at_c0[0x40];
e281682b
SM		 4902
4903 struct mlx5_ifc_tirc_bits ctx;
4904};
4905
4906struct mlx5_ifc_modify_sq_out_bits {
4907 u8 status[0x8];
b4ff3a36 4908 u8 reserved_at_8[0x18];
e281682b
SM		 4909
4910 u8 syndrome[0x20];
4911
b4ff3a36 4912 u8 reserved_at_40[0x40];
e281682b
SM		 4913};
4914
4915struct mlx5_ifc_modify_sq_in_bits {
4916 u8 opcode[0x10];
b4ff3a36 4917 u8 reserved_at_10[0x10];
e281682b 4918
b4ff3a36 4919 u8 reserved_at_20[0x10];
e281682b
SM		 4920 u8 op_mod[0x10];
4921
4922 u8 sq_state[0x4];
b4ff3a36 4923 u8 reserved_at_44[0x4];
e281682b
SM		 4924 u8 sqn[0x18];
4925
b4ff3a36 4926 u8 reserved_at_60[0x20];
e281682b
SM		 4927
4928 u8 modify_bitmask[0x40];
4929
b4ff3a36 4930 u8 reserved_at_c0[0x40];
e281682b
SM		 4931
4932 struct mlx5_ifc_sqc_bits ctx;
4933};
4934
813f8540
MHY		 4935struct mlx5_ifc_modify_scheduling_element_out_bits {
4936 u8 status[0x8];
4937 u8 reserved_at_8[0x18];
4938
4939 u8 syndrome[0x20];
4940
4941 u8 reserved_at_40[0x1c0];
4942};
4943
4944enum {
4945 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
4946 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
4947};
4948
4949struct mlx5_ifc_modify_scheduling_element_in_bits {
4950 u8 opcode[0x10];
4951 u8 reserved_at_10[0x10];
4952
4953 u8 reserved_at_20[0x10];
4954 u8 op_mod[0x10];
4955
4956 u8 scheduling_hierarchy[0x8];
4957 u8 reserved_at_48[0x18];
4958
4959 u8 scheduling_element_id[0x20];
4960
4961 u8 reserved_at_80[0x20];
4962
4963 u8 modify_bitmask[0x20];
4964
4965 u8 reserved_at_c0[0x40];
4966
4967 struct mlx5_ifc_scheduling_context_bits scheduling_context;
4968
4969 u8 reserved_at_300[0x100];
4970};
4971
e281682b
SM		 4972struct mlx5_ifc_modify_rqt_out_bits {
4973 u8 status[0x8];
b4ff3a36 4974 u8 reserved_at_8[0x18];
e281682b
SM		 4975
4976 u8 syndrome[0x20];
4977
b4ff3a36 4978 u8 reserved_at_40[0x40];
e281682b
SM		 4979};
4980
5c50368f 4981struct mlx5_ifc_rqt_bitmask_bits {
b4ff3a36 4982 u8 reserved_at_0[0x20];
5c50368f 4983
b4ff3a36 4984 u8 reserved_at_20[0x1f];
5c50368f
AS		 4985 u8 rqn_list[0x1];
4986};
4987
e281682b
SM		 4988struct mlx5_ifc_modify_rqt_in_bits {
4989 u8 opcode[0x10];
b4ff3a36 4990 u8 reserved_at_10[0x10];
e281682b 4991
b4ff3a36 4992 u8 reserved_at_20[0x10];
e281682b
SM		 4993 u8 op_mod[0x10];
4994
b4ff3a36 4995 u8 reserved_at_40[0x8];
e281682b
SM		 4996 u8 rqtn[0x18];
4997
b4ff3a36 4998 u8 reserved_at_60[0x20];
e281682b 4999
5c50368f 5000 struct mlx5_ifc_rqt_bitmask_bits bitmask;
e281682b 5001
b4ff3a36 5002 u8 reserved_at_c0[0x40];
e281682b
SM		 5003
5004 struct mlx5_ifc_rqtc_bits ctx;
5005};
5006
5007struct mlx5_ifc_modify_rq_out_bits {
5008 u8 status[0x8];
b4ff3a36 5009 u8 reserved_at_8[0x18];
e281682b
SM		 5010
5011 u8 syndrome[0x20];
5012
b4ff3a36 5013 u8 reserved_at_40[0x40];
e281682b
SM		 5014};
5015
83b502a1
AV		 5016enum {
5017 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
5018 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID = 1ULL << 3,
5019};
5020
e281682b
SM		 5021struct mlx5_ifc_modify_rq_in_bits {
5022 u8 opcode[0x10];
b4ff3a36 5023 u8 reserved_at_10[0x10];
e281682b 5024
b4ff3a36 5025 u8 reserved_at_20[0x10];
e281682b
SM		 5026 u8 op_mod[0x10];
5027
5028 u8 rq_state[0x4];
b4ff3a36 5029 u8 reserved_at_44[0x4];
e281682b
SM		 5030 u8 rqn[0x18];
5031
b4ff3a36 5032 u8 reserved_at_60[0x20];
e281682b
SM		 5033
5034 u8 modify_bitmask[0x40];
5035
b4ff3a36 5036 u8 reserved_at_c0[0x40];
e281682b
SM		 5037
5038 struct mlx5_ifc_rqc_bits ctx;
5039};
5040
5041struct mlx5_ifc_modify_rmp_out_bits {
5042 u8 status[0x8];
b4ff3a36 5043 u8 reserved_at_8[0x18];
e281682b
SM		 5044
5045 u8 syndrome[0x20];
5046
b4ff3a36 5047 u8 reserved_at_40[0x40];
e281682b
SM		 5048};
5049
01949d01 5050struct mlx5_ifc_rmp_bitmask_bits {
b4ff3a36 5051 u8 reserved_at_0[0x20];
01949d01 5052
b4ff3a36 5053 u8 reserved_at_20[0x1f];
01949d01
HA		 5054 u8 lwm[0x1];
5055};
5056
e281682b
SM		 5057struct mlx5_ifc_modify_rmp_in_bits {
5058 u8 opcode[0x10];
b4ff3a36 5059 u8 reserved_at_10[0x10];
e281682b 5060
b4ff3a36 5061 u8 reserved_at_20[0x10];
e281682b
SM		 5062 u8 op_mod[0x10];
5063
5064 u8 rmp_state[0x4];
b4ff3a36 5065 u8 reserved_at_44[0x4];
e281682b
SM		 5066 u8 rmpn[0x18];
5067
b4ff3a36 5068 u8 reserved_at_60[0x20];
e281682b 5069
01949d01 5070 struct mlx5_ifc_rmp_bitmask_bits bitmask;
e281682b 5071
b4ff3a36 5072 u8 reserved_at_c0[0x40];
e281682b
SM		 5073
5074 struct mlx5_ifc_rmpc_bits ctx;
5075};
5076
5077struct mlx5_ifc_modify_nic_vport_context_out_bits {
5078 u8 status[0x8];
b4ff3a36 5079 u8 reserved_at_8[0x18];
e281682b
SM		 5080
5081 u8 syndrome[0x20];
5082
b4ff3a36 5083 u8 reserved_at_40[0x40];
e281682b
SM		 5084};
5085
5086struct mlx5_ifc_modify_nic_vport_field_select_bits {
23898c76
NO		 5087 u8 reserved_at_0[0x16];
5088 u8 node_guid[0x1];
5089 u8 port_guid[0x1];
9def7121 5090 u8 min_inline[0x1];
d82b7318
SM		 5091 u8 mtu[0x1];
5092 u8 change_event[0x1];
5093 u8 promisc[0x1];
e281682b
SM		 5094 u8 permanent_address[0x1];
5095 u8 addresses_list[0x1];
5096 u8 roce_en[0x1];
b4ff3a36 5097 u8 reserved_at_1f[0x1];
e281682b
SM		 5098};
5099
5100struct mlx5_ifc_modify_nic_vport_context_in_bits {
5101 u8 opcode[0x10];
b4ff3a36 5102 u8 reserved_at_10[0x10];
e281682b 5103
b4ff3a36 5104 u8 reserved_at_20[0x10];
e281682b
SM		 5105 u8 op_mod[0x10];
5106
5107 u8 other_vport[0x1];
b4ff3a36 5108 u8 reserved_at_41[0xf];
e281682b
SM		 5109 u8 vport_number[0x10];
5110
5111 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5112
b4ff3a36 5113 u8 reserved_at_80[0x780];
e281682b
SM		 5114
5115 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5116};
5117
5118struct mlx5_ifc_modify_hca_vport_context_out_bits {
5119 u8 status[0x8];
b4ff3a36 5120 u8 reserved_at_8[0x18];
e281682b
SM		 5121
5122 u8 syndrome[0x20];
5123
b4ff3a36 5124 u8 reserved_at_40[0x40];
e281682b
SM		 5125};
5126
5127struct mlx5_ifc_modify_hca_vport_context_in_bits {
5128 u8 opcode[0x10];
b4ff3a36 5129 u8 reserved_at_10[0x10];
e281682b 5130
b4ff3a36 5131 u8 reserved_at_20[0x10];
e281682b
SM		 5132 u8 op_mod[0x10];
5133
5134 u8 other_vport[0x1];
b4ff3a36 5135 u8 reserved_at_41[0xb];
707c4602 5136 u8 port_num[0x4];
e281682b
SM		 5137 u8 vport_number[0x10];
5138
b4ff3a36 5139 u8 reserved_at_60[0x20];
e281682b
SM		 5140
5141 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5142};
5143
5144struct mlx5_ifc_modify_cq_out_bits {
5145 u8 status[0x8];
b4ff3a36 5146 u8 reserved_at_8[0x18];
e281682b
SM		 5147
5148 u8 syndrome[0x20];
5149
b4ff3a36 5150 u8 reserved_at_40[0x40];
e281682b
SM		 5151};
5152
5153enum {
5154 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
5155 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
5156};
5157
5158struct mlx5_ifc_modify_cq_in_bits {
5159 u8 opcode[0x10];
b4ff3a36 5160 u8 reserved_at_10[0x10];
e281682b 5161
b4ff3a36 5162 u8 reserved_at_20[0x10];
e281682b
SM		 5163 u8 op_mod[0x10];
5164
b4ff3a36 5165 u8 reserved_at_40[0x8];
e281682b
SM		 5166 u8 cqn[0x18];
5167
5168 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5169
5170 struct mlx5_ifc_cqc_bits cq_context;
5171
b4ff3a36 5172 u8 reserved_at_280[0x600];
e281682b
SM		 5173
5174 u8 pas[0][0x40];
5175};
5176
5177struct mlx5_ifc_modify_cong_status_out_bits {
5178 u8 status[0x8];
b4ff3a36 5179 u8 reserved_at_8[0x18];
e281682b
SM		 5180
5181 u8 syndrome[0x20];
5182
b4ff3a36 5183 u8 reserved_at_40[0x40];
e281682b
SM		 5184};
5185
5186struct mlx5_ifc_modify_cong_status_in_bits {
5187 u8 opcode[0x10];
b4ff3a36 5188 u8 reserved_at_10[0x10];
e281682b 5189
b4ff3a36 5190 u8 reserved_at_20[0x10];
e281682b
SM		 5191 u8 op_mod[0x10];
5192
b4ff3a36 5193 u8 reserved_at_40[0x18];
e281682b
SM		 5194 u8 priority[0x4];
5195 u8 cong_protocol[0x4];
5196
5197 u8 enable[0x1];
5198 u8 tag_enable[0x1];
b4ff3a36 5199 u8 reserved_at_62[0x1e];
e281682b
SM		 5200};
5201
5202struct mlx5_ifc_modify_cong_params_out_bits {
5203 u8 status[0x8];
b4ff3a36 5204 u8 reserved_at_8[0x18];
e281682b
SM		 5205
5206 u8 syndrome[0x20];
5207
b4ff3a36 5208 u8 reserved_at_40[0x40];
e281682b
SM		 5209};
5210
5211struct mlx5_ifc_modify_cong_params_in_bits {
5212 u8 opcode[0x10];
b4ff3a36 5213 u8 reserved_at_10[0x10];
e281682b 5214
b4ff3a36 5215 u8 reserved_at_20[0x10];
e281682b
SM		 5216 u8 op_mod[0x10];
5217
b4ff3a36 5218 u8 reserved_at_40[0x1c];
e281682b
SM		 5219 u8 cong_protocol[0x4];
5220
5221 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5222
b4ff3a36 5223 u8 reserved_at_80[0x80];
e281682b
SM		 5224
5225 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5226};
5227
5228struct mlx5_ifc_manage_pages_out_bits {
5229 u8 status[0x8];
b4ff3a36 5230 u8 reserved_at_8[0x18];
e281682b
SM		 5231
5232 u8 syndrome[0x20];
5233
5234 u8 output_num_entries[0x20];
5235
b4ff3a36 5236 u8 reserved_at_60[0x20];
e281682b
SM		 5237
5238 u8 pas[0][0x40];
5239};
5240
5241enum {
5242 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
5243 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
5244 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
5245};
5246
5247struct mlx5_ifc_manage_pages_in_bits {
5248 u8 opcode[0x10];
b4ff3a36 5249 u8 reserved_at_10[0x10];
e281682b 5250
b4ff3a36 5251 u8 reserved_at_20[0x10];
e281682b
SM		 5252 u8 op_mod[0x10];
5253
b4ff3a36 5254 u8 reserved_at_40[0x10];
e281682b
SM		 5255 u8 function_id[0x10];
5256
5257 u8 input_num_entries[0x20];
5258
5259 u8 pas[0][0x40];
5260};
5261
5262struct mlx5_ifc_mad_ifc_out_bits {
5263 u8 status[0x8];
b4ff3a36 5264 u8 reserved_at_8[0x18];
e281682b
SM		 5265
5266 u8 syndrome[0x20];
5267
b4ff3a36 5268 u8 reserved_at_40[0x40];
e281682b
SM		 5269
5270 u8 response_mad_packet[256][0x8];
5271};
5272
5273struct mlx5_ifc_mad_ifc_in_bits {
5274 u8 opcode[0x10];
b4ff3a36 5275 u8 reserved_at_10[0x10];
e281682b 5276
b4ff3a36 5277 u8 reserved_at_20[0x10];
e281682b
SM		 5278 u8 op_mod[0x10];
5279
5280 u8 remote_lid[0x10];
b4ff3a36 5281 u8 reserved_at_50[0x8];
e281682b
SM		 5282 u8 port[0x8];
5283
b4ff3a36 5284 u8 reserved_at_60[0x20];
e281682b
SM		 5285
5286 u8 mad[256][0x8];
5287};
5288
5289struct mlx5_ifc_init_hca_out_bits {
5290 u8 status[0x8];
b4ff3a36 5291 u8 reserved_at_8[0x18];
e281682b
SM		 5292
5293 u8 syndrome[0x20];
5294
b4ff3a36 5295 u8 reserved_at_40[0x40];
e281682b
SM		 5296};
5297
5298struct mlx5_ifc_init_hca_in_bits {
5299 u8 opcode[0x10];
b4ff3a36 5300 u8 reserved_at_10[0x10];
e281682b 5301
b4ff3a36 5302 u8 reserved_at_20[0x10];
e281682b
SM		 5303 u8 op_mod[0x10];
5304
b4ff3a36 5305 u8 reserved_at_40[0x40];
e281682b
SM		 5306};
5307
5308struct mlx5_ifc_init2rtr_qp_out_bits {
5309 u8 status[0x8];
b4ff3a36 5310 u8 reserved_at_8[0x18];
e281682b
SM		 5311
5312 u8 syndrome[0x20];
5313
b4ff3a36 5314 u8 reserved_at_40[0x40];
e281682b
SM		 5315};
5316
5317struct mlx5_ifc_init2rtr_qp_in_bits {
5318 u8 opcode[0x10];
b4ff3a36 5319 u8 reserved_at_10[0x10];
e281682b 5320
b4ff3a36 5321 u8 reserved_at_20[0x10];
e281682b
SM		 5322 u8 op_mod[0x10];
5323
b4ff3a36 5324 u8 reserved_at_40[0x8];
e281682b
SM		 5325 u8 qpn[0x18];
5326
b4ff3a36 5327 u8 reserved_at_60[0x20];
e281682b
SM		 5328
5329 u8 opt_param_mask[0x20];
5330
b4ff3a36 5331 u8 reserved_at_a0[0x20];
e281682b
SM		 5332
5333 struct mlx5_ifc_qpc_bits qpc;
5334
b4ff3a36 5335 u8 reserved_at_800[0x80];
e281682b
SM		 5336};
5337
5338struct mlx5_ifc_init2init_qp_out_bits {
5339 u8 status[0x8];
b4ff3a36 5340 u8 reserved_at_8[0x18];
e281682b
SM		 5341
5342 u8 syndrome[0x20];
5343
b4ff3a36 5344 u8 reserved_at_40[0x40];
e281682b
SM		 5345};
5346
5347struct mlx5_ifc_init2init_qp_in_bits {
5348 u8 opcode[0x10];
b4ff3a36 5349 u8 reserved_at_10[0x10];
e281682b 5350
b4ff3a36 5351 u8 reserved_at_20[0x10];
e281682b
SM		 5352 u8 op_mod[0x10];
5353
b4ff3a36 5354 u8 reserved_at_40[0x8];
e281682b
SM		 5355 u8 qpn[0x18];
5356
b4ff3a36 5357 u8 reserved_at_60[0x20];
e281682b
SM		 5358
5359 u8 opt_param_mask[0x20];
5360
b4ff3a36 5361 u8 reserved_at_a0[0x20];
e281682b
SM		 5362
5363 struct mlx5_ifc_qpc_bits qpc;
5364
b4ff3a36 5365 u8 reserved_at_800[0x80];
e281682b
SM		 5366};
5367
5368struct mlx5_ifc_get_dropped_packet_log_out_bits {
5369 u8 status[0x8];
b4ff3a36 5370 u8 reserved_at_8[0x18];
e281682b
SM		 5371
5372 u8 syndrome[0x20];
5373
b4ff3a36 5374 u8 reserved_at_40[0x40];
e281682b
SM		 5375
5376 u8 packet_headers_log[128][0x8];
5377
5378 u8 packet_syndrome[64][0x8];
5379};
5380
5381struct mlx5_ifc_get_dropped_packet_log_in_bits {
5382 u8 opcode[0x10];
b4ff3a36 5383 u8 reserved_at_10[0x10];
e281682b 5384
b4ff3a36 5385 u8 reserved_at_20[0x10];
e281682b
SM		 5386 u8 op_mod[0x10];
5387
b4ff3a36 5388 u8 reserved_at_40[0x40];
e281682b
SM		 5389};
5390
5391struct mlx5_ifc_gen_eqe_in_bits {
5392 u8 opcode[0x10];
b4ff3a36 5393 u8 reserved_at_10[0x10];
e281682b 5394
b4ff3a36 5395 u8 reserved_at_20[0x10];
e281682b
SM		 5396 u8 op_mod[0x10];
5397
b4ff3a36 5398 u8 reserved_at_40[0x18];
e281682b
SM		 5399 u8 eq_number[0x8];
5400
b4ff3a36 5401 u8 reserved_at_60[0x20];
e281682b
SM		 5402
5403 u8 eqe[64][0x8];
5404};
5405
5406struct mlx5_ifc_gen_eq_out_bits {
5407 u8 status[0x8];
b4ff3a36 5408 u8 reserved_at_8[0x18];
e281682b
SM		 5409
5410 u8 syndrome[0x20];
5411
b4ff3a36 5412 u8 reserved_at_40[0x40];
e281682b
SM		 5413};
5414
5415struct mlx5_ifc_enable_hca_out_bits {
5416 u8 status[0x8];
b4ff3a36 5417 u8 reserved_at_8[0x18];
e281682b
SM		 5418
5419 u8 syndrome[0x20];
5420
b4ff3a36 5421 u8 reserved_at_40[0x20];
e281682b
SM		 5422};
5423
5424struct mlx5_ifc_enable_hca_in_bits {
5425 u8 opcode[0x10];
b4ff3a36 5426 u8 reserved_at_10[0x10];
e281682b 5427
b4ff3a36 5428 u8 reserved_at_20[0x10];
e281682b
SM		 5429 u8 op_mod[0x10];
5430
b4ff3a36 5431 u8 reserved_at_40[0x10];
e281682b
SM		 5432 u8 function_id[0x10];
5433
b4ff3a36 5434 u8 reserved_at_60[0x20];
e281682b
SM		 5435};
5436
5437struct mlx5_ifc_drain_dct_out_bits {
5438 u8 status[0x8];
b4ff3a36 5439 u8 reserved_at_8[0x18];
e281682b
SM		 5440
5441 u8 syndrome[0x20];
5442
b4ff3a36 5443 u8 reserved_at_40[0x40];
e281682b
SM		 5444};
5445
5446struct mlx5_ifc_drain_dct_in_bits {
5447 u8 opcode[0x10];
b4ff3a36 5448 u8 reserved_at_10[0x10];
e281682b 5449
b4ff3a36 5450 u8 reserved_at_20[0x10];
e281682b
SM		 5451 u8 op_mod[0x10];
5452
b4ff3a36 5453 u8 reserved_at_40[0x8];
e281682b
SM		 5454 u8 dctn[0x18];
5455
b4ff3a36 5456 u8 reserved_at_60[0x20];
e281682b
SM		 5457};
5458
5459struct mlx5_ifc_disable_hca_out_bits {
5460 u8 status[0x8];
b4ff3a36 5461 u8 reserved_at_8[0x18];
e281682b
SM		 5462
5463 u8 syndrome[0x20];
5464
b4ff3a36 5465 u8 reserved_at_40[0x20];
e281682b
SM		 5466};
5467
5468struct mlx5_ifc_disable_hca_in_bits {
5469 u8 opcode[0x10];
b4ff3a36 5470 u8 reserved_at_10[0x10];
e281682b 5471
b4ff3a36 5472 u8 reserved_at_20[0x10];
e281682b
SM		 5473 u8 op_mod[0x10];
5474
b4ff3a36 5475 u8 reserved_at_40[0x10];
e281682b
SM		 5476 u8 function_id[0x10];
5477
b4ff3a36 5478 u8 reserved_at_60[0x20];
e281682b
SM		 5479};
5480
5481struct mlx5_ifc_detach_from_mcg_out_bits {
5482 u8 status[0x8];
b4ff3a36 5483 u8 reserved_at_8[0x18];
e281682b
SM		 5484
5485 u8 syndrome[0x20];
5486
b4ff3a36 5487 u8 reserved_at_40[0x40];
e281682b
SM		 5488};
5489
5490struct mlx5_ifc_detach_from_mcg_in_bits {
5491 u8 opcode[0x10];
b4ff3a36 5492 u8 reserved_at_10[0x10];
e281682b 5493
b4ff3a36 5494 u8 reserved_at_20[0x10];
e281682b
SM		 5495 u8 op_mod[0x10];
5496
b4ff3a36 5497 u8 reserved_at_40[0x8];
e281682b
SM		 5498 u8 qpn[0x18];
5499
b4ff3a36 5500 u8 reserved_at_60[0x20];
e281682b
SM		 5501
5502 u8 multicast_gid[16][0x8];
5503};
5504
7486216b
SM		 5505struct mlx5_ifc_destroy_xrq_out_bits {
5506 u8 status[0x8];
5507 u8 reserved_at_8[0x18];
5508
5509 u8 syndrome[0x20];
5510
5511 u8 reserved_at_40[0x40];
5512};
5513
5514struct mlx5_ifc_destroy_xrq_in_bits {
5515 u8 opcode[0x10];
5516 u8 reserved_at_10[0x10];
5517
5518 u8 reserved_at_20[0x10];
5519 u8 op_mod[0x10];
5520
5521 u8 reserved_at_40[0x8];
5522 u8 xrqn[0x18];
5523
5524 u8 reserved_at_60[0x20];
5525};
5526
e281682b
SM		 5527struct mlx5_ifc_destroy_xrc_srq_out_bits {
5528 u8 status[0x8];
b4ff3a36 5529 u8 reserved_at_8[0x18];
e281682b
SM		 5530
5531 u8 syndrome[0x20];
5532
b4ff3a36 5533 u8 reserved_at_40[0x40];
e281682b
SM		 5534};
5535
5536struct mlx5_ifc_destroy_xrc_srq_in_bits {
5537 u8 opcode[0x10];
b4ff3a36 5538 u8 reserved_at_10[0x10];
e281682b 5539
b4ff3a36 5540 u8 reserved_at_20[0x10];
e281682b
SM		 5541 u8 op_mod[0x10];
5542
b4ff3a36 5543 u8 reserved_at_40[0x8];
e281682b
SM		 5544 u8 xrc_srqn[0x18];
5545
b4ff3a36 5546 u8 reserved_at_60[0x20];
e281682b
SM		 5547};
5548
5549struct mlx5_ifc_destroy_tis_out_bits {
5550 u8 status[0x8];
b4ff3a36 5551 u8 reserved_at_8[0x18];
e281682b
SM		 5552
5553 u8 syndrome[0x20];
5554
b4ff3a36 5555 u8 reserved_at_40[0x40];
e281682b
SM		 5556};
5557
5558struct mlx5_ifc_destroy_tis_in_bits {
5559 u8 opcode[0x10];
b4ff3a36 5560 u8 reserved_at_10[0x10];
e281682b 5561
b4ff3a36 5562 u8 reserved_at_20[0x10];
e281682b
SM		 5563 u8 op_mod[0x10];
5564
b4ff3a36 5565 u8 reserved_at_40[0x8];
e281682b
SM		 5566 u8 tisn[0x18];
5567
b4ff3a36 5568 u8 reserved_at_60[0x20];
e281682b
SM		 5569};
5570
5571struct mlx5_ifc_destroy_tir_out_bits {
5572 u8 status[0x8];
b4ff3a36 5573 u8 reserved_at_8[0x18];
e281682b
SM		 5574
5575 u8 syndrome[0x20];
5576
b4ff3a36 5577 u8 reserved_at_40[0x40];
e281682b
SM		 5578};
5579
5580struct mlx5_ifc_destroy_tir_in_bits {
5581 u8 opcode[0x10];
b4ff3a36 5582 u8 reserved_at_10[0x10];
e281682b 5583
b4ff3a36 5584 u8 reserved_at_20[0x10];
e281682b
SM		 5585 u8 op_mod[0x10];
5586
b4ff3a36 5587 u8 reserved_at_40[0x8];
e281682b
SM		 5588 u8 tirn[0x18];
5589
b4ff3a36 5590 u8 reserved_at_60[0x20];
e281682b
SM		 5591};
5592
5593struct mlx5_ifc_destroy_srq_out_bits {
5594 u8 status[0x8];
b4ff3a36 5595 u8 reserved_at_8[0x18];
e281682b
SM		 5596
5597 u8 syndrome[0x20];
5598
b4ff3a36 5599 u8 reserved_at_40[0x40];
e281682b
SM		 5600};
5601
5602struct mlx5_ifc_destroy_srq_in_bits {
5603 u8 opcode[0x10];
b4ff3a36 5604 u8 reserved_at_10[0x10];
e281682b 5605
b4ff3a36 5606 u8 reserved_at_20[0x10];
e281682b
SM		 5607 u8 op_mod[0x10];
5608
b4ff3a36 5609 u8 reserved_at_40[0x8];
e281682b
SM		 5610 u8 srqn[0x18];
5611
b4ff3a36 5612 u8 reserved_at_60[0x20];
e281682b
SM		 5613};
5614
5615struct mlx5_ifc_destroy_sq_out_bits {
5616 u8 status[0x8];
b4ff3a36 5617 u8 reserved_at_8[0x18];
e281682b
SM		 5618
5619 u8 syndrome[0x20];
5620
b4ff3a36 5621 u8 reserved_at_40[0x40];
e281682b
SM		 5622};
5623
5624struct mlx5_ifc_destroy_sq_in_bits {
5625 u8 opcode[0x10];
b4ff3a36 5626 u8 reserved_at_10[0x10];
e281682b 5627
b4ff3a36 5628 u8 reserved_at_20[0x10];
e281682b
SM		 5629 u8 op_mod[0x10];
5630
b4ff3a36 5631 u8 reserved_at_40[0x8];
e281682b
SM		 5632 u8 sqn[0x18];
5633
b4ff3a36 5634 u8 reserved_at_60[0x20];
e281682b
SM		 5635};
5636
813f8540
MHY		 5637struct mlx5_ifc_destroy_scheduling_element_out_bits {
5638 u8 status[0x8];
5639 u8 reserved_at_8[0x18];
5640
5641 u8 syndrome[0x20];
5642
5643 u8 reserved_at_40[0x1c0];
5644};
5645
5646struct mlx5_ifc_destroy_scheduling_element_in_bits {
5647 u8 opcode[0x10];
5648 u8 reserved_at_10[0x10];
5649
5650 u8 reserved_at_20[0x10];
5651 u8 op_mod[0x10];
5652
5653 u8 scheduling_hierarchy[0x8];
5654 u8 reserved_at_48[0x18];
5655
5656 u8 scheduling_element_id[0x20];
5657
5658 u8 reserved_at_80[0x180];
5659};
5660
e281682b
SM		 5661struct mlx5_ifc_destroy_rqt_out_bits {
5662 u8 status[0x8];
b4ff3a36 5663 u8 reserved_at_8[0x18];
e281682b
SM		 5664
5665 u8 syndrome[0x20];
5666
b4ff3a36 5667 u8 reserved_at_40[0x40];
e281682b
SM		 5668};
5669
5670struct mlx5_ifc_destroy_rqt_in_bits {
5671 u8 opcode[0x10];
b4ff3a36 5672 u8 reserved_at_10[0x10];
e281682b 5673
b4ff3a36 5674 u8 reserved_at_20[0x10];
e281682b
SM		 5675 u8 op_mod[0x10];
5676
b4ff3a36 5677 u8 reserved_at_40[0x8];
e281682b
SM		 5678 u8 rqtn[0x18];
5679
b4ff3a36 5680 u8 reserved_at_60[0x20];
e281682b
SM		 5681};
5682
5683struct mlx5_ifc_destroy_rq_out_bits {
5684 u8 status[0x8];
b4ff3a36 5685 u8 reserved_at_8[0x18];
e281682b
SM		 5686
5687 u8 syndrome[0x20];
5688
b4ff3a36 5689 u8 reserved_at_40[0x40];
e281682b
SM		 5690};
5691
5692struct mlx5_ifc_destroy_rq_in_bits {
5693 u8 opcode[0x10];
b4ff3a36 5694 u8 reserved_at_10[0x10];
e281682b 5695
b4ff3a36 5696 u8 reserved_at_20[0x10];
e281682b
SM		 5697 u8 op_mod[0x10];
5698
b4ff3a36 5699 u8 reserved_at_40[0x8];
e281682b
SM		 5700 u8 rqn[0x18];
5701
b4ff3a36 5702 u8 reserved_at_60[0x20];
e281682b
SM		 5703};
5704
5705struct mlx5_ifc_destroy_rmp_out_bits {
5706 u8 status[0x8];
b4ff3a36 5707 u8 reserved_at_8[0x18];
e281682b
SM		 5708
5709 u8 syndrome[0x20];
5710
b4ff3a36 5711 u8 reserved_at_40[0x40];
e281682b
SM		 5712};
5713
5714struct mlx5_ifc_destroy_rmp_in_bits {
5715 u8 opcode[0x10];
b4ff3a36 5716 u8 reserved_at_10[0x10];
e281682b 5717
b4ff3a36 5718 u8 reserved_at_20[0x10];
e281682b
SM		 5719 u8 op_mod[0x10];
5720
b4ff3a36 5721 u8 reserved_at_40[0x8];
e281682b
SM		 5722 u8 rmpn[0x18];
5723
b4ff3a36 5724 u8 reserved_at_60[0x20];
e281682b
SM		 5725};
5726
5727struct mlx5_ifc_destroy_qp_out_bits {
5728 u8 status[0x8];
b4ff3a36 5729 u8 reserved_at_8[0x18];
e281682b
SM		 5730
5731 u8 syndrome[0x20];
5732
b4ff3a36 5733 u8 reserved_at_40[0x40];
e281682b
SM		 5734};
5735
5736struct mlx5_ifc_destroy_qp_in_bits {
5737 u8 opcode[0x10];
b4ff3a36 5738 u8 reserved_at_10[0x10];
e281682b 5739
b4ff3a36 5740 u8 reserved_at_20[0x10];
e281682b
SM		 5741 u8 op_mod[0x10];
5742
b4ff3a36 5743 u8 reserved_at_40[0x8];
e281682b
SM		 5744 u8 qpn[0x18];
5745
b4ff3a36 5746 u8 reserved_at_60[0x20];
e281682b
SM		 5747};
5748
5749struct mlx5_ifc_destroy_psv_out_bits {
5750 u8 status[0x8];
b4ff3a36 5751 u8 reserved_at_8[0x18];
e281682b
SM		 5752
5753 u8 syndrome[0x20];
5754
b4ff3a36 5755 u8 reserved_at_40[0x40];
e281682b
SM		 5756};
5757
5758struct mlx5_ifc_destroy_psv_in_bits {
5759 u8 opcode[0x10];
b4ff3a36 5760 u8 reserved_at_10[0x10];
e281682b 5761
b4ff3a36 5762 u8 reserved_at_20[0x10];
e281682b
SM		 5763 u8 op_mod[0x10];
5764
b4ff3a36 5765 u8 reserved_at_40[0x8];
e281682b
SM		 5766 u8 psvn[0x18];
5767
b4ff3a36 5768 u8 reserved_at_60[0x20];
e281682b
SM		 5769};
5770
5771struct mlx5_ifc_destroy_mkey_out_bits {
5772 u8 status[0x8];
b4ff3a36 5773 u8 reserved_at_8[0x18];
e281682b
SM		 5774
5775 u8 syndrome[0x20];
5776
b4ff3a36 5777 u8 reserved_at_40[0x40];
e281682b
SM		 5778};
5779
5780struct mlx5_ifc_destroy_mkey_in_bits {
5781 u8 opcode[0x10];
b4ff3a36 5782 u8 reserved_at_10[0x10];
e281682b 5783
b4ff3a36 5784 u8 reserved_at_20[0x10];
e281682b
SM		 5785 u8 op_mod[0x10];
5786
b4ff3a36 5787 u8 reserved_at_40[0x8];
e281682b
SM		 5788 u8 mkey_index[0x18];
5789
b4ff3a36 5790 u8 reserved_at_60[0x20];
e281682b
SM		 5791};
5792
5793struct mlx5_ifc_destroy_flow_table_out_bits {
5794 u8 status[0x8];
b4ff3a36 5795 u8 reserved_at_8[0x18];
e281682b
SM		 5796
5797 u8 syndrome[0x20];
5798
b4ff3a36 5799 u8 reserved_at_40[0x40];
e281682b
SM		 5800};
5801
5802struct mlx5_ifc_destroy_flow_table_in_bits {
5803 u8 opcode[0x10];
b4ff3a36 5804 u8 reserved_at_10[0x10];
e281682b 5805
b4ff3a36 5806 u8 reserved_at_20[0x10];
e281682b
SM		 5807 u8 op_mod[0x10];
5808
7d5e1423
SM		 5809 u8 other_vport[0x1];
5810 u8 reserved_at_41[0xf];
5811 u8 vport_number[0x10];
5812
5813 u8 reserved_at_60[0x20];
e281682b
SM		 5814
5815 u8 table_type[0x8];
b4ff3a36 5816 u8 reserved_at_88[0x18];
e281682b 5817
b4ff3a36 5818 u8 reserved_at_a0[0x8];
e281682b
SM		 5819 u8 table_id[0x18];
5820
b4ff3a36 5821 u8 reserved_at_c0[0x140];
e281682b
SM		 5822};
5823
5824struct mlx5_ifc_destroy_flow_group_out_bits {
5825 u8 status[0x8];
b4ff3a36 5826 u8 reserved_at_8[0x18];
e281682b
SM		 5827
5828 u8 syndrome[0x20];
5829
b4ff3a36 5830 u8 reserved_at_40[0x40];
e281682b
SM		 5831};
5832
5833struct mlx5_ifc_destroy_flow_group_in_bits {
5834 u8 opcode[0x10];
b4ff3a36 5835 u8 reserved_at_10[0x10];
e281682b 5836
b4ff3a36 5837 u8 reserved_at_20[0x10];
e281682b
SM		 5838 u8 op_mod[0x10];
5839
7d5e1423
SM		 5840 u8 other_vport[0x1];
5841 u8 reserved_at_41[0xf];
5842 u8 vport_number[0x10];
5843
5844 u8 reserved_at_60[0x20];
e281682b
SM		 5845
5846 u8 table_type[0x8];
b4ff3a36 5847 u8 reserved_at_88[0x18];
e281682b 5848
b4ff3a36 5849 u8 reserved_at_a0[0x8];
e281682b
SM		 5850 u8 table_id[0x18];
5851
5852 u8 group_id[0x20];
5853
b4ff3a36 5854 u8 reserved_at_e0[0x120];
e281682b
SM		 5855};
5856
5857struct mlx5_ifc_destroy_eq_out_bits {
5858 u8 status[0x8];
b4ff3a36 5859 u8 reserved_at_8[0x18];
e281682b
SM		 5860
5861 u8 syndrome[0x20];
5862
b4ff3a36 5863 u8 reserved_at_40[0x40];
e281682b
SM		 5864};
5865
5866struct mlx5_ifc_destroy_eq_in_bits {
5867 u8 opcode[0x10];
b4ff3a36 5868 u8 reserved_at_10[0x10];
e281682b 5869
b4ff3a36 5870 u8 reserved_at_20[0x10];
e281682b
SM		 5871 u8 op_mod[0x10];
5872
b4ff3a36 5873 u8 reserved_at_40[0x18];
e281682b
SM		 5874 u8 eq_number[0x8];
5875
b4ff3a36 5876 u8 reserved_at_60[0x20];
e281682b
SM		 5877};
5878
5879struct mlx5_ifc_destroy_dct_out_bits {
5880 u8 status[0x8];
b4ff3a36 5881 u8 reserved_at_8[0x18];
e281682b
SM		 5882
5883 u8 syndrome[0x20];
5884
b4ff3a36 5885 u8 reserved_at_40[0x40];
e281682b
SM		 5886};
5887
5888struct mlx5_ifc_destroy_dct_in_bits {
5889 u8 opcode[0x10];
b4ff3a36 5890 u8 reserved_at_10[0x10];
e281682b 5891
b4ff3a36 5892 u8 reserved_at_20[0x10];
e281682b
SM		 5893 u8 op_mod[0x10];
5894
b4ff3a36 5895 u8 reserved_at_40[0x8];
e281682b
SM		 5896 u8 dctn[0x18];
5897
b4ff3a36 5898 u8 reserved_at_60[0x20];
e281682b
SM		 5899};
5900
5901struct mlx5_ifc_destroy_cq_out_bits {
5902 u8 status[0x8];
b4ff3a36 5903 u8 reserved_at_8[0x18];
e281682b
SM		 5904
5905 u8 syndrome[0x20];
5906
b4ff3a36 5907 u8 reserved_at_40[0x40];
e281682b
SM		 5908};
5909
5910struct mlx5_ifc_destroy_cq_in_bits {
5911 u8 opcode[0x10];
b4ff3a36 5912 u8 reserved_at_10[0x10];
e281682b 5913
b4ff3a36 5914 u8 reserved_at_20[0x10];
e281682b
SM		 5915 u8 op_mod[0x10];
5916
b4ff3a36 5917 u8 reserved_at_40[0x8];
e281682b
SM		 5918 u8 cqn[0x18];
5919
b4ff3a36 5920 u8 reserved_at_60[0x20];
e281682b
SM		 5921};
5922
5923struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
5924 u8 status[0x8];
b4ff3a36 5925 u8 reserved_at_8[0x18];
e281682b
SM		 5926
5927 u8 syndrome[0x20];
5928
b4ff3a36 5929 u8 reserved_at_40[0x40];
e281682b
SM		 5930};
5931
5932struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
5933 u8 opcode[0x10];
b4ff3a36 5934 u8 reserved_at_10[0x10];
e281682b 5935
b4ff3a36 5936 u8 reserved_at_20[0x10];
e281682b
SM		 5937 u8 op_mod[0x10];
5938
b4ff3a36 5939 u8 reserved_at_40[0x20];
e281682b 5940
b4ff3a36 5941 u8 reserved_at_60[0x10];
e281682b
SM		 5942 u8 vxlan_udp_port[0x10];
5943};
5944
5945struct mlx5_ifc_delete_l2_table_entry_out_bits {
5946 u8 status[0x8];
b4ff3a36 5947 u8 reserved_at_8[0x18];
e281682b
SM		 5948
5949 u8 syndrome[0x20];
5950
b4ff3a36 5951 u8 reserved_at_40[0x40];
e281682b
SM		 5952};
5953
5954struct mlx5_ifc_delete_l2_table_entry_in_bits {
5955 u8 opcode[0x10];
b4ff3a36 5956 u8 reserved_at_10[0x10];
e281682b 5957
b4ff3a36 5958 u8 reserved_at_20[0x10];
e281682b
SM		 5959 u8 op_mod[0x10];
5960
b4ff3a36 5961 u8 reserved_at_40[0x60];
e281682b 5962
b4ff3a36 5963 u8 reserved_at_a0[0x8];
e281682b
SM		 5964 u8 table_index[0x18];
5965
b4ff3a36 5966 u8 reserved_at_c0[0x140];
e281682b
SM		 5967};
5968
5969struct mlx5_ifc_delete_fte_out_bits {
5970 u8 status[0x8];
b4ff3a36 5971 u8 reserved_at_8[0x18];
e281682b
SM		 5972
5973 u8 syndrome[0x20];
5974
b4ff3a36 5975 u8 reserved_at_40[0x40];
e281682b
SM		 5976};
5977
5978struct mlx5_ifc_delete_fte_in_bits {
5979 u8 opcode[0x10];
b4ff3a36 5980 u8 reserved_at_10[0x10];
e281682b 5981
b4ff3a36 5982 u8 reserved_at_20[0x10];
e281682b
SM		 5983 u8 op_mod[0x10];
5984
7d5e1423
SM		 5985 u8 other_vport[0x1];
5986 u8 reserved_at_41[0xf];
5987 u8 vport_number[0x10];
5988
5989 u8 reserved_at_60[0x20];
e281682b
SM		 5990
5991 u8 table_type[0x8];
b4ff3a36 5992 u8 reserved_at_88[0x18];
e281682b 5993
b4ff3a36 5994 u8 reserved_at_a0[0x8];
e281682b
SM		 5995 u8 table_id[0x18];
5996
b4ff3a36 5997 u8 reserved_at_c0[0x40];
e281682b
SM		 5998
5999 u8 flow_index[0x20];
6000
b4ff3a36 6001 u8 reserved_at_120[0xe0];
e281682b
SM		 6002};
6003
6004struct mlx5_ifc_dealloc_xrcd_out_bits {
6005 u8 status[0x8];
b4ff3a36 6006 u8 reserved_at_8[0x18];
e281682b
SM		 6007
6008 u8 syndrome[0x20];
6009
b4ff3a36 6010 u8 reserved_at_40[0x40];
e281682b
SM		 6011};
6012
6013struct mlx5_ifc_dealloc_xrcd_in_bits {
6014 u8 opcode[0x10];
b4ff3a36 6015 u8 reserved_at_10[0x10];
e281682b 6016
b4ff3a36 6017 u8 reserved_at_20[0x10];
e281682b
SM		 6018 u8 op_mod[0x10];
6019
b4ff3a36 6020 u8 reserved_at_40[0x8];
e281682b
SM		 6021 u8 xrcd[0x18];
6022
b4ff3a36 6023 u8 reserved_at_60[0x20];
e281682b
SM		 6024};
6025
6026struct mlx5_ifc_dealloc_uar_out_bits {
6027 u8 status[0x8];
b4ff3a36 6028 u8 reserved_at_8[0x18];
e281682b
SM		 6029
6030 u8 syndrome[0x20];
6031
b4ff3a36 6032 u8 reserved_at_40[0x40];
e281682b
SM		 6033};
6034
6035struct mlx5_ifc_dealloc_uar_in_bits {
6036 u8 opcode[0x10];
b4ff3a36 6037 u8 reserved_at_10[0x10];
e281682b 6038
b4ff3a36 6039 u8 reserved_at_20[0x10];
e281682b
SM		 6040 u8 op_mod[0x10];
6041
b4ff3a36 6042 u8 reserved_at_40[0x8];
e281682b
SM		 6043 u8 uar[0x18];
6044
b4ff3a36 6045 u8 reserved_at_60[0x20];
e281682b
SM		 6046};
6047
6048struct mlx5_ifc_dealloc_transport_domain_out_bits {
6049 u8 status[0x8];
b4ff3a36 6050 u8 reserved_at_8[0x18];
e281682b
SM		 6051
6052 u8 syndrome[0x20];
6053
b4ff3a36 6054 u8 reserved_at_40[0x40];
e281682b
SM		 6055};
6056
6057struct mlx5_ifc_dealloc_transport_domain_in_bits {
6058 u8 opcode[0x10];
b4ff3a36 6059 u8 reserved_at_10[0x10];
e281682b 6060
b4ff3a36 6061 u8 reserved_at_20[0x10];
e281682b
SM		 6062 u8 op_mod[0x10];
6063
b4ff3a36 6064 u8 reserved_at_40[0x8];
e281682b
SM		 6065 u8 transport_domain[0x18];
6066
b4ff3a36 6067 u8 reserved_at_60[0x20];
e281682b
SM		 6068};
6069
6070struct mlx5_ifc_dealloc_q_counter_out_bits {
6071 u8 status[0x8];
b4ff3a36 6072 u8 reserved_at_8[0x18];
e281682b
SM		 6073
6074 u8 syndrome[0x20];
6075
b4ff3a36 6076 u8 reserved_at_40[0x40];
e281682b
SM		 6077};
6078
6079struct mlx5_ifc_dealloc_q_counter_in_bits {
6080 u8 opcode[0x10];
b4ff3a36 6081 u8 reserved_at_10[0x10];
e281682b 6082
b4ff3a36 6083 u8 reserved_at_20[0x10];
e281682b
SM		 6084 u8 op_mod[0x10];
6085
b4ff3a36 6086 u8 reserved_at_40[0x18];
e281682b
SM		 6087 u8 counter_set_id[0x8];
6088
b4ff3a36 6089 u8 reserved_at_60[0x20];
e281682b
SM		 6090};
6091
6092struct mlx5_ifc_dealloc_pd_out_bits {
6093 u8 status[0x8];
b4ff3a36 6094 u8 reserved_at_8[0x18];
e281682b
SM		 6095
6096 u8 syndrome[0x20];
6097
b4ff3a36 6098 u8 reserved_at_40[0x40];
e281682b
SM		 6099};
6100
6101struct mlx5_ifc_dealloc_pd_in_bits {
6102 u8 opcode[0x10];
b4ff3a36 6103 u8 reserved_at_10[0x10];
e281682b 6104
b4ff3a36 6105 u8 reserved_at_20[0x10];
e281682b
SM		 6106 u8 op_mod[0x10];
6107
b4ff3a36 6108 u8 reserved_at_40[0x8];
e281682b
SM		 6109 u8 pd[0x18];
6110
b4ff3a36 6111 u8 reserved_at_60[0x20];
e281682b
SM		 6112};
6113
9dc0b289
AV		 6114struct mlx5_ifc_dealloc_flow_counter_out_bits {
6115 u8 status[0x8];
6116 u8 reserved_at_8[0x18];
6117
6118 u8 syndrome[0x20];
6119
6120 u8 reserved_at_40[0x40];
6121};
6122
6123struct mlx5_ifc_dealloc_flow_counter_in_bits {
6124 u8 opcode[0x10];
6125 u8 reserved_at_10[0x10];
6126
6127 u8 reserved_at_20[0x10];
6128 u8 op_mod[0x10];
6129
6130 u8 reserved_at_40[0x10];
6131 u8 flow_counter_id[0x10];
6132
6133 u8 reserved_at_60[0x20];
6134};
6135
7486216b
SM		 6136struct mlx5_ifc_create_xrq_out_bits {
6137 u8 status[0x8];
6138 u8 reserved_at_8[0x18];
6139
6140 u8 syndrome[0x20];
6141
6142 u8 reserved_at_40[0x8];
6143 u8 xrqn[0x18];
6144
6145 u8 reserved_at_60[0x20];
6146};
6147
6148struct mlx5_ifc_create_xrq_in_bits {
6149 u8 opcode[0x10];
6150 u8 reserved_at_10[0x10];
6151
6152 u8 reserved_at_20[0x10];
6153 u8 op_mod[0x10];
6154
6155 u8 reserved_at_40[0x40];
6156
6157 struct mlx5_ifc_xrqc_bits xrq_context;
6158};
6159
e281682b
SM		 6160struct mlx5_ifc_create_xrc_srq_out_bits {
6161 u8 status[0x8];
b4ff3a36 6162 u8 reserved_at_8[0x18];
e281682b
SM		 6163
6164 u8 syndrome[0x20];
6165
b4ff3a36 6166 u8 reserved_at_40[0x8];
e281682b
SM		 6167 u8 xrc_srqn[0x18];
6168
b4ff3a36 6169 u8 reserved_at_60[0x20];
e281682b
SM		 6170};
6171
6172struct mlx5_ifc_create_xrc_srq_in_bits {
6173 u8 opcode[0x10];
b4ff3a36 6174 u8 reserved_at_10[0x10];
e281682b 6175
b4ff3a36 6176 u8 reserved_at_20[0x10];
e281682b
SM		 6177 u8 op_mod[0x10];
6178
b4ff3a36 6179 u8 reserved_at_40[0x40];
e281682b
SM		 6180
6181 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6182
b4ff3a36 6183 u8 reserved_at_280[0x600];
e281682b
SM		 6184
6185 u8 pas[0][0x40];
6186};
6187
6188struct mlx5_ifc_create_tis_out_bits {
6189 u8 status[0x8];
b4ff3a36 6190 u8 reserved_at_8[0x18];
e281682b
SM		 6191
6192 u8 syndrome[0x20];
6193
b4ff3a36 6194 u8 reserved_at_40[0x8];
e281682b
SM		 6195 u8 tisn[0x18];
6196
b4ff3a36 6197 u8 reserved_at_60[0x20];
e281682b
SM		 6198};
6199
6200struct mlx5_ifc_create_tis_in_bits {
6201 u8 opcode[0x10];
b4ff3a36 6202 u8 reserved_at_10[0x10];
e281682b 6203
b4ff3a36 6204 u8 reserved_at_20[0x10];
e281682b
SM		 6205 u8 op_mod[0x10];
6206
b4ff3a36 6207 u8 reserved_at_40[0xc0];
e281682b
SM		 6208
6209 struct mlx5_ifc_tisc_bits ctx;
6210};
6211
6212struct mlx5_ifc_create_tir_out_bits {
6213 u8 status[0x8];
b4ff3a36 6214 u8 reserved_at_8[0x18];
e281682b
SM		 6215
6216 u8 syndrome[0x20];
6217
b4ff3a36 6218 u8 reserved_at_40[0x8];
e281682b
SM		 6219 u8 tirn[0x18];
6220
b4ff3a36 6221 u8 reserved_at_60[0x20];
e281682b
SM		 6222};
6223
6224struct mlx5_ifc_create_tir_in_bits {
6225 u8 opcode[0x10];
b4ff3a36 6226 u8 reserved_at_10[0x10];
e281682b 6227
b4ff3a36 6228 u8 reserved_at_20[0x10];
e281682b
SM		 6229 u8 op_mod[0x10];
6230
b4ff3a36 6231 u8 reserved_at_40[0xc0];
e281682b
SM		 6232
6233 struct mlx5_ifc_tirc_bits ctx;
6234};
6235
6236struct mlx5_ifc_create_srq_out_bits {
6237 u8 status[0x8];
b4ff3a36 6238 u8 reserved_at_8[0x18];
e281682b
SM		 6239
6240 u8 syndrome[0x20];
6241
b4ff3a36 6242 u8 reserved_at_40[0x8];
e281682b
SM		 6243 u8 srqn[0x18];
6244
b4ff3a36 6245 u8 reserved_at_60[0x20];
e281682b
SM		 6246};
6247
6248struct mlx5_ifc_create_srq_in_bits {
6249 u8 opcode[0x10];
b4ff3a36 6250 u8 reserved_at_10[0x10];
e281682b 6251
b4ff3a36 6252 u8 reserved_at_20[0x10];
e281682b
SM		 6253 u8 op_mod[0x10];
6254
b4ff3a36 6255 u8 reserved_at_40[0x40];
e281682b
SM		 6256
6257 struct mlx5_ifc_srqc_bits srq_context_entry;
6258
b4ff3a36 6259 u8 reserved_at_280[0x600];
e281682b
SM		 6260
6261 u8 pas[0][0x40];
6262};
6263
6264struct mlx5_ifc_create_sq_out_bits {
6265 u8 status[0x8];
b4ff3a36 6266 u8 reserved_at_8[0x18];
e281682b
SM		 6267
6268 u8 syndrome[0x20];
6269
b4ff3a36 6270 u8 reserved_at_40[0x8];
e281682b
SM		 6271 u8 sqn[0x18];
6272
b4ff3a36 6273 u8 reserved_at_60[0x20];
e281682b
SM		 6274};
6275
6276struct mlx5_ifc_create_sq_in_bits {
6277 u8 opcode[0x10];
b4ff3a36 6278 u8 reserved_at_10[0x10];
e281682b 6279
b4ff3a36 6280 u8 reserved_at_20[0x10];
e281682b
SM		 6281 u8 op_mod[0x10];
6282
b4ff3a36 6283 u8 reserved_at_40[0xc0];
e281682b
SM		 6284
6285 struct mlx5_ifc_sqc_bits ctx;
6286};
6287
813f8540
MHY		 6288struct mlx5_ifc_create_scheduling_element_out_bits {
6289 u8 status[0x8];
6290 u8 reserved_at_8[0x18];
6291
6292 u8 syndrome[0x20];
6293
6294 u8 reserved_at_40[0x40];
6295
6296 u8 scheduling_element_id[0x20];
6297
6298 u8 reserved_at_a0[0x160];
6299};
6300
6301struct mlx5_ifc_create_scheduling_element_in_bits {
6302 u8 opcode[0x10];
6303 u8 reserved_at_10[0x10];
6304
6305 u8 reserved_at_20[0x10];
6306 u8 op_mod[0x10];
6307
6308 u8 scheduling_hierarchy[0x8];
6309 u8 reserved_at_48[0x18];
6310
6311 u8 reserved_at_60[0xa0];
6312
6313 struct mlx5_ifc_scheduling_context_bits scheduling_context;
6314
6315 u8 reserved_at_300[0x100];
6316};
6317
e281682b
SM		 6318struct mlx5_ifc_create_rqt_out_bits {
6319 u8 status[0x8];
b4ff3a36 6320 u8 reserved_at_8[0x18];
e281682b
SM		 6321
6322 u8 syndrome[0x20];
6323
b4ff3a36 6324 u8 reserved_at_40[0x8];
e281682b
SM		 6325 u8 rqtn[0x18];
6326
b4ff3a36 6327 u8 reserved_at_60[0x20];
e281682b
SM		 6328};
6329
6330struct mlx5_ifc_create_rqt_in_bits {
6331 u8 opcode[0x10];
b4ff3a36 6332 u8 reserved_at_10[0x10];
e281682b 6333
b4ff3a36 6334 u8 reserved_at_20[0x10];
e281682b
SM		 6335 u8 op_mod[0x10];
6336
b4ff3a36 6337 u8 reserved_at_40[0xc0];
e281682b
SM		 6338
6339 struct mlx5_ifc_rqtc_bits rqt_context;
6340};
6341
6342struct mlx5_ifc_create_rq_out_bits {
6343 u8 status[0x8];
b4ff3a36 6344 u8 reserved_at_8[0x18];
e281682b
SM		 6345
6346 u8 syndrome[0x20];
6347
b4ff3a36 6348 u8 reserved_at_40[0x8];
e281682b
SM		 6349 u8 rqn[0x18];
6350
b4ff3a36 6351 u8 reserved_at_60[0x20];
e281682b
SM		 6352};
6353
6354struct mlx5_ifc_create_rq_in_bits {
6355 u8 opcode[0x10];
b4ff3a36 6356 u8 reserved_at_10[0x10];
e281682b 6357
b4ff3a36 6358 u8 reserved_at_20[0x10];
e281682b
SM		 6359 u8 op_mod[0x10];
6360
b4ff3a36 6361 u8 reserved_at_40[0xc0];
e281682b
SM		 6362
6363 struct mlx5_ifc_rqc_bits ctx;
6364};
6365
6366struct mlx5_ifc_create_rmp_out_bits {
6367 u8 status[0x8];
b4ff3a36 6368 u8 reserved_at_8[0x18];
e281682b
SM		 6369
6370 u8 syndrome[0x20];
6371
b4ff3a36 6372 u8 reserved_at_40[0x8];
e281682b
SM		 6373 u8 rmpn[0x18];
6374
b4ff3a36 6375 u8 reserved_at_60[0x20];
e281682b
SM		 6376};
6377
6378struct mlx5_ifc_create_rmp_in_bits {
6379 u8 opcode[0x10];
b4ff3a36 6380 u8 reserved_at_10[0x10];
e281682b 6381
b4ff3a36 6382 u8 reserved_at_20[0x10];
e281682b
SM		 6383 u8 op_mod[0x10];
6384
b4ff3a36 6385 u8 reserved_at_40[0xc0];
e281682b
SM		 6386
6387 struct mlx5_ifc_rmpc_bits ctx;
6388};
6389
6390struct mlx5_ifc_create_qp_out_bits {
6391 u8 status[0x8];
b4ff3a36 6392 u8 reserved_at_8[0x18];
e281682b
SM		 6393
6394 u8 syndrome[0x20];
6395
b4ff3a36 6396 u8 reserved_at_40[0x8];
e281682b
SM		 6397 u8 qpn[0x18];
6398
b4ff3a36 6399 u8 reserved_at_60[0x20];
e281682b
SM		 6400};
6401
6402struct mlx5_ifc_create_qp_in_bits {
6403 u8 opcode[0x10];
b4ff3a36 6404 u8 reserved_at_10[0x10];
e281682b 6405
b4ff3a36 6406 u8 reserved_at_20[0x10];
e281682b
SM		 6407 u8 op_mod[0x10];
6408
b4ff3a36 6409 u8 reserved_at_40[0x40];
e281682b
SM		 6410
6411 u8 opt_param_mask[0x20];
6412
b4ff3a36 6413 u8 reserved_at_a0[0x20];
e281682b
SM		 6414
6415 struct mlx5_ifc_qpc_bits qpc;
6416
b4ff3a36 6417 u8 reserved_at_800[0x80];
e281682b
SM		 6418
6419 u8 pas[0][0x40];
6420};
6421
6422struct mlx5_ifc_create_psv_out_bits {
6423 u8 status[0x8];
b4ff3a36 6424 u8 reserved_at_8[0x18];
e281682b
SM		 6425
6426 u8 syndrome[0x20];
6427
b4ff3a36 6428 u8 reserved_at_40[0x40];
e281682b 6429
b4ff3a36 6430 u8 reserved_at_80[0x8];
e281682b
SM		 6431 u8 psv0_index[0x18];
6432
b4ff3a36 6433 u8 reserved_at_a0[0x8];
e281682b
SM		 6434 u8 psv1_index[0x18];
6435
b4ff3a36 6436 u8 reserved_at_c0[0x8];
e281682b
SM		 6437 u8 psv2_index[0x18];
6438
b4ff3a36 6439 u8 reserved_at_e0[0x8];
e281682b
SM		 6440 u8 psv3_index[0x18];
6441};
6442
6443struct mlx5_ifc_create_psv_in_bits {
6444 u8 opcode[0x10];
b4ff3a36 6445 u8 reserved_at_10[0x10];
e281682b 6446
b4ff3a36 6447 u8 reserved_at_20[0x10];
e281682b
SM		 6448 u8 op_mod[0x10];
6449
6450 u8 num_psv[0x4];
b4ff3a36 6451 u8 reserved_at_44[0x4];
e281682b
SM		 6452 u8 pd[0x18];
6453
b4ff3a36 6454 u8 reserved_at_60[0x20];
e281682b
SM		 6455};
6456
6457struct mlx5_ifc_create_mkey_out_bits {
6458 u8 status[0x8];
b4ff3a36 6459 u8 reserved_at_8[0x18];
e281682b
SM		 6460
6461 u8 syndrome[0x20];
6462
b4ff3a36 6463 u8 reserved_at_40[0x8];
e281682b
SM		 6464 u8 mkey_index[0x18];
6465
b4ff3a36 6466 u8 reserved_at_60[0x20];
e281682b
SM		 6467};
6468
6469struct mlx5_ifc_create_mkey_in_bits {
6470 u8 opcode[0x10];
b4ff3a36 6471 u8 reserved_at_10[0x10];
e281682b 6472
b4ff3a36 6473 u8 reserved_at_20[0x10];
e281682b
SM		 6474 u8 op_mod[0x10];
6475
b4ff3a36 6476 u8 reserved_at_40[0x20];
e281682b
SM		 6477
6478 u8 pg_access[0x1];
b4ff3a36 6479 u8 reserved_at_61[0x1f];
e281682b
SM		 6480
6481 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6482
b4ff3a36 6483 u8 reserved_at_280[0x80];
e281682b
SM		 6484
6485 u8 translations_octword_actual_size[0x20];
6486
b4ff3a36 6487 u8 reserved_at_320[0x560];
e281682b
SM		 6488
6489 u8 klm_pas_mtt[0][0x20];
6490};
6491
6492struct mlx5_ifc_create_flow_table_out_bits {
6493 u8 status[0x8];
b4ff3a36 6494 u8 reserved_at_8[0x18];
e281682b
SM		 6495
6496 u8 syndrome[0x20];
6497
b4ff3a36 6498 u8 reserved_at_40[0x8];
e281682b
SM		 6499 u8 table_id[0x18];
6500
b4ff3a36 6501 u8 reserved_at_60[0x20];
e281682b
SM		 6502};
6503
6504struct mlx5_ifc_create_flow_table_in_bits {
6505 u8 opcode[0x10];
b4ff3a36 6506 u8 reserved_at_10[0x10];
e281682b 6507
b4ff3a36 6508 u8 reserved_at_20[0x10];
e281682b
SM		 6509 u8 op_mod[0x10];
6510
7d5e1423
SM		 6511 u8 other_vport[0x1];
6512 u8 reserved_at_41[0xf];
6513 u8 vport_number[0x10];
6514
6515 u8 reserved_at_60[0x20];
e281682b
SM		 6516
6517 u8 table_type[0x8];
b4ff3a36 6518 u8 reserved_at_88[0x18];
e281682b 6519
b4ff3a36 6520 u8 reserved_at_a0[0x20];
e281682b 6521
7adbde20
HHZ		 6522 u8 encap_en[0x1];
6523 u8 decap_en[0x1];
6524 u8 reserved_at_c2[0x2];
34a40e68 6525 u8 table_miss_mode[0x4];
e281682b 6526 u8 level[0x8];
b4ff3a36 6527 u8 reserved_at_d0[0x8];
e281682b
SM		 6528 u8 log_size[0x8];
6529
b4ff3a36 6530 u8 reserved_at_e0[0x8];
34a40e68
MG		 6531 u8 table_miss_id[0x18];
6532
84df61eb
AH		 6533 u8 reserved_at_100[0x8];
6534 u8 lag_master_next_table_id[0x18];
6535
6536 u8 reserved_at_120[0x80];
e281682b
SM		 6537};
6538
6539struct mlx5_ifc_create_flow_group_out_bits {
6540 u8 status[0x8];
b4ff3a36 6541 u8 reserved_at_8[0x18];
e281682b
SM		 6542
6543 u8 syndrome[0x20];
6544
b4ff3a36 6545 u8 reserved_at_40[0x8];
e281682b
SM		 6546 u8 group_id[0x18];
6547
b4ff3a36 6548 u8 reserved_at_60[0x20];
e281682b
SM		 6549};
6550
6551enum {
6552 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
6553 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
6554 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
6555};
6556
6557struct mlx5_ifc_create_flow_group_in_bits {
6558 u8 opcode[0x10];
b4ff3a36 6559 u8 reserved_at_10[0x10];
e281682b 6560
b4ff3a36 6561 u8 reserved_at_20[0x10];
e281682b
SM		 6562 u8 op_mod[0x10];
6563
7d5e1423
SM		 6564 u8 other_vport[0x1];
6565 u8 reserved_at_41[0xf];
6566 u8 vport_number[0x10];
6567
6568 u8 reserved_at_60[0x20];
e281682b
SM		 6569
6570 u8 table_type[0x8];
b4ff3a36 6571 u8 reserved_at_88[0x18];
e281682b 6572
b4ff3a36 6573 u8 reserved_at_a0[0x8];
e281682b
SM		 6574 u8 table_id[0x18];
6575
b4ff3a36 6576 u8 reserved_at_c0[0x20];
e281682b
SM		 6577
6578 u8 start_flow_index[0x20];
6579
b4ff3a36 6580 u8 reserved_at_100[0x20];
e281682b
SM		 6581
6582 u8 end_flow_index[0x20];
6583
b4ff3a36 6584 u8 reserved_at_140[0xa0];
e281682b 6585
b4ff3a36 6586 u8 reserved_at_1e0[0x18];
e281682b
SM		 6587 u8 match_criteria_enable[0x8];
6588
6589 struct mlx5_ifc_fte_match_param_bits match_criteria;
6590
b4ff3a36 6591 u8 reserved_at_1200[0xe00];
e281682b
SM		 6592};
6593
6594struct mlx5_ifc_create_eq_out_bits {
6595 u8 status[0x8];
b4ff3a36 6596 u8 reserved_at_8[0x18];
e281682b
SM		 6597
6598 u8 syndrome[0x20];
6599
b4ff3a36 6600 u8 reserved_at_40[0x18];
e281682b
SM		 6601 u8 eq_number[0x8];
6602
b4ff3a36 6603 u8 reserved_at_60[0x20];
e281682b
SM		 6604};
6605
6606struct mlx5_ifc_create_eq_in_bits {
6607 u8 opcode[0x10];
b4ff3a36 6608 u8 reserved_at_10[0x10];
e281682b 6609
b4ff3a36 6610 u8 reserved_at_20[0x10];
e281682b
SM		 6611 u8 op_mod[0x10];
6612
b4ff3a36 6613 u8 reserved_at_40[0x40];
e281682b
SM		 6614
6615 struct mlx5_ifc_eqc_bits eq_context_entry;
6616
b4ff3a36 6617 u8 reserved_at_280[0x40];
e281682b
SM		 6618
6619 u8 event_bitmask[0x40];
6620
b4ff3a36 6621 u8 reserved_at_300[0x580];
e281682b
SM		 6622
6623 u8 pas[0][0x40];
6624};
6625
6626struct mlx5_ifc_create_dct_out_bits {
6627 u8 status[0x8];
b4ff3a36 6628 u8 reserved_at_8[0x18];
e281682b
SM		 6629
6630 u8 syndrome[0x20];
6631
b4ff3a36 6632 u8 reserved_at_40[0x8];
e281682b
SM		 6633 u8 dctn[0x18];
6634
b4ff3a36 6635 u8 reserved_at_60[0x20];
e281682b
SM		 6636};
6637
6638struct mlx5_ifc_create_dct_in_bits {
6639 u8 opcode[0x10];
b4ff3a36 6640 u8 reserved_at_10[0x10];
e281682b 6641
b4ff3a36 6642 u8 reserved_at_20[0x10];
e281682b
SM		 6643 u8 op_mod[0x10];
6644
b4ff3a36 6645 u8 reserved_at_40[0x40];
e281682b
SM		 6646
6647 struct mlx5_ifc_dctc_bits dct_context_entry;
6648
b4ff3a36 6649 u8 reserved_at_280[0x180];
e281682b
SM		 6650};
6651
6652struct mlx5_ifc_create_cq_out_bits {
6653 u8 status[0x8];
b4ff3a36 6654 u8 reserved_at_8[0x18];
e281682b
SM		 6655
6656 u8 syndrome[0x20];
6657
b4ff3a36 6658 u8 reserved_at_40[0x8];
e281682b
SM		 6659 u8 cqn[0x18];
6660
b4ff3a36 6661 u8 reserved_at_60[0x20];
e281682b
SM		 6662};
6663
6664struct mlx5_ifc_create_cq_in_bits {
6665 u8 opcode[0x10];
b4ff3a36 6666 u8 reserved_at_10[0x10];
e281682b 6667
b4ff3a36 6668 u8 reserved_at_20[0x10];
e281682b
SM		 6669 u8 op_mod[0x10];
6670
b4ff3a36 6671 u8 reserved_at_40[0x40];
e281682b
SM		 6672
6673 struct mlx5_ifc_cqc_bits cq_context;
6674
b4ff3a36 6675 u8 reserved_at_280[0x600];
e281682b
SM		 6676
6677 u8 pas[0][0x40];
6678};
6679
6680struct mlx5_ifc_config_int_moderation_out_bits {
6681 u8 status[0x8];
b4ff3a36 6682 u8 reserved_at_8[0x18];
e281682b
SM		 6683
6684 u8 syndrome[0x20];
6685
b4ff3a36 6686 u8 reserved_at_40[0x4];
e281682b
SM		 6687 u8 min_delay[0xc];
6688 u8 int_vector[0x10];
6689
b4ff3a36 6690 u8 reserved_at_60[0x20];
e281682b
SM		 6691};
6692
6693enum {
6694 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
6695 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
6696};
6697
6698struct mlx5_ifc_config_int_moderation_in_bits {
6699 u8 opcode[0x10];
b4ff3a36 6700 u8 reserved_at_10[0x10];
e281682b 6701
b4ff3a36 6702 u8 reserved_at_20[0x10];
e281682b
SM		 6703 u8 op_mod[0x10];
6704
b4ff3a36 6705 u8 reserved_at_40[0x4];
e281682b
SM		 6706 u8 min_delay[0xc];
6707 u8 int_vector[0x10];
6708
b4ff3a36 6709 u8 reserved_at_60[0x20];
e281682b
SM		 6710};
6711
6712struct mlx5_ifc_attach_to_mcg_out_bits {
6713 u8 status[0x8];
b4ff3a36 6714 u8 reserved_at_8[0x18];
e281682b
SM		 6715
6716 u8 syndrome[0x20];
6717
b4ff3a36 6718 u8 reserved_at_40[0x40];
e281682b
SM		 6719};
6720
6721struct mlx5_ifc_attach_to_mcg_in_bits {
6722 u8 opcode[0x10];
b4ff3a36 6723 u8 reserved_at_10[0x10];
e281682b 6724
b4ff3a36 6725 u8 reserved_at_20[0x10];
e281682b
SM		 6726 u8 op_mod[0x10];
6727
b4ff3a36 6728 u8 reserved_at_40[0x8];
e281682b
SM		 6729 u8 qpn[0x18];
6730
b4ff3a36 6731 u8 reserved_at_60[0x20];
e281682b
SM		 6732
6733 u8 multicast_gid[16][0x8];
6734};
6735
7486216b
SM		 6736struct mlx5_ifc_arm_xrq_out_bits {
6737 u8 status[0x8];
6738 u8 reserved_at_8[0x18];
6739
6740 u8 syndrome[0x20];
6741
6742 u8 reserved_at_40[0x40];
6743};
6744
6745struct mlx5_ifc_arm_xrq_in_bits {
6746 u8 opcode[0x10];
6747 u8 reserved_at_10[0x10];
6748
6749 u8 reserved_at_20[0x10];
6750 u8 op_mod[0x10];
6751
6752 u8 reserved_at_40[0x8];
6753 u8 xrqn[0x18];
6754
6755 u8 reserved_at_60[0x10];
6756 u8 lwm[0x10];
6757};
6758
e281682b
SM		 6759struct mlx5_ifc_arm_xrc_srq_out_bits {
6760 u8 status[0x8];
b4ff3a36 6761 u8 reserved_at_8[0x18];
e281682b
SM		 6762
6763 u8 syndrome[0x20];
6764
b4ff3a36 6765 u8 reserved_at_40[0x40];
e281682b
SM		 6766};
6767
6768enum {
6769 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
6770};
6771
6772struct mlx5_ifc_arm_xrc_srq_in_bits {
6773 u8 opcode[0x10];
b4ff3a36 6774 u8 reserved_at_10[0x10];
e281682b 6775
b4ff3a36 6776 u8 reserved_at_20[0x10];
e281682b
SM		 6777 u8 op_mod[0x10];
6778
b4ff3a36 6779 u8 reserved_at_40[0x8];
e281682b
SM		 6780 u8 xrc_srqn[0x18];
6781
b4ff3a36 6782 u8 reserved_at_60[0x10];
e281682b
SM		 6783 u8 lwm[0x10];
6784};
6785
6786struct mlx5_ifc_arm_rq_out_bits {
6787 u8 status[0x8];
b4ff3a36 6788 u8 reserved_at_8[0x18];
e281682b
SM		 6789
6790 u8 syndrome[0x20];
6791
b4ff3a36 6792 u8 reserved_at_40[0x40];
e281682b
SM		 6793};
6794
6795enum {
7486216b
SM		 6796 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
6797 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
e281682b
SM		 6798};
6799
6800struct mlx5_ifc_arm_rq_in_bits {
6801 u8 opcode[0x10];
b4ff3a36 6802 u8 reserved_at_10[0x10];
e281682b 6803
b4ff3a36 6804 u8 reserved_at_20[0x10];
e281682b
SM		 6805 u8 op_mod[0x10];
6806
b4ff3a36 6807 u8 reserved_at_40[0x8];
e281682b
SM		 6808 u8 srq_number[0x18];
6809
b4ff3a36 6810 u8 reserved_at_60[0x10];
e281682b
SM		 6811 u8 lwm[0x10];
6812};
6813
6814struct mlx5_ifc_arm_dct_out_bits {
6815 u8 status[0x8];
b4ff3a36 6816 u8 reserved_at_8[0x18];
e281682b
SM		 6817
6818 u8 syndrome[0x20];
6819
b4ff3a36 6820 u8 reserved_at_40[0x40];
e281682b
SM		 6821};
6822
6823struct mlx5_ifc_arm_dct_in_bits {
6824 u8 opcode[0x10];
b4ff3a36 6825 u8 reserved_at_10[0x10];
e281682b 6826
b4ff3a36 6827 u8 reserved_at_20[0x10];
e281682b
SM		 6828 u8 op_mod[0x10];
6829
b4ff3a36 6830 u8 reserved_at_40[0x8];
e281682b
SM		 6831 u8 dct_number[0x18];
6832
b4ff3a36 6833 u8 reserved_at_60[0x20];
e281682b
SM		 6834};
6835
6836struct mlx5_ifc_alloc_xrcd_out_bits {
6837 u8 status[0x8];
b4ff3a36 6838 u8 reserved_at_8[0x18];
e281682b
SM		 6839
6840 u8 syndrome[0x20];
6841
b4ff3a36 6842 u8 reserved_at_40[0x8];
e281682b
SM		 6843 u8 xrcd[0x18];
6844
b4ff3a36 6845 u8 reserved_at_60[0x20];
e281682b
SM		 6846};
6847
6848struct mlx5_ifc_alloc_xrcd_in_bits {
6849 u8 opcode[0x10];
b4ff3a36 6850 u8 reserved_at_10[0x10];
e281682b 6851
b4ff3a36 6852 u8 reserved_at_20[0x10];
e281682b
SM		 6853 u8 op_mod[0x10];
6854
b4ff3a36 6855 u8 reserved_at_40[0x40];
e281682b
SM		 6856};
6857
6858struct mlx5_ifc_alloc_uar_out_bits {
6859 u8 status[0x8];
b4ff3a36 6860 u8 reserved_at_8[0x18];
e281682b
SM		 6861
6862 u8 syndrome[0x20];
6863
b4ff3a36 6864 u8 reserved_at_40[0x8];
e281682b
SM		 6865 u8 uar[0x18];
6866
b4ff3a36 6867 u8 reserved_at_60[0x20];
e281682b
SM		 6868};
6869
6870struct mlx5_ifc_alloc_uar_in_bits {
6871 u8 opcode[0x10];
b4ff3a36 6872 u8 reserved_at_10[0x10];
e281682b 6873
b4ff3a36 6874 u8 reserved_at_20[0x10];
e281682b
SM		 6875 u8 op_mod[0x10];
6876
b4ff3a36 6877 u8 reserved_at_40[0x40];
e281682b
SM		 6878};
6879
6880struct mlx5_ifc_alloc_transport_domain_out_bits {
6881 u8 status[0x8];
b4ff3a36 6882 u8 reserved_at_8[0x18];
e281682b
SM		 6883
6884 u8 syndrome[0x20];
6885
b4ff3a36 6886 u8 reserved_at_40[0x8];
e281682b
SM		 6887 u8 transport_domain[0x18];
6888
b4ff3a36 6889 u8 reserved_at_60[0x20];
e281682b
SM		 6890};
6891
6892struct mlx5_ifc_alloc_transport_domain_in_bits {
6893 u8 opcode[0x10];
b4ff3a36 6894 u8 reserved_at_10[0x10];
e281682b 6895
b4ff3a36 6896 u8 reserved_at_20[0x10];
e281682b
SM		 6897 u8 op_mod[0x10];
6898
b4ff3a36 6899 u8 reserved_at_40[0x40];
e281682b
SM		 6900};
6901
6902struct mlx5_ifc_alloc_q_counter_out_bits {
6903 u8 status[0x8];
b4ff3a36 6904 u8 reserved_at_8[0x18];
e281682b
SM		 6905
6906 u8 syndrome[0x20];
6907
b4ff3a36 6908 u8 reserved_at_40[0x18];
e281682b
SM		 6909 u8 counter_set_id[0x8];
6910
b4ff3a36 6911 u8 reserved_at_60[0x20];
e281682b
SM		 6912};
6913
6914struct mlx5_ifc_alloc_q_counter_in_bits {
6915 u8 opcode[0x10];
b4ff3a36 6916 u8 reserved_at_10[0x10];
e281682b 6917
b4ff3a36 6918 u8 reserved_at_20[0x10];
e281682b
SM		 6919 u8 op_mod[0x10];
6920
b4ff3a36 6921 u8 reserved_at_40[0x40];
e281682b
SM		 6922};
6923
6924struct mlx5_ifc_alloc_pd_out_bits {
6925 u8 status[0x8];
b4ff3a36 6926 u8 reserved_at_8[0x18];
e281682b
SM		 6927
6928 u8 syndrome[0x20];
6929
b4ff3a36 6930 u8 reserved_at_40[0x8];
e281682b
SM		 6931 u8 pd[0x18];
6932
b4ff3a36 6933 u8 reserved_at_60[0x20];
e281682b
SM		 6934};
6935
6936struct mlx5_ifc_alloc_pd_in_bits {
9dc0b289
AV		 6937 u8 opcode[0x10];
6938 u8 reserved_at_10[0x10];
6939
6940 u8 reserved_at_20[0x10];
6941 u8 op_mod[0x10];
6942
6943 u8 reserved_at_40[0x40];
6944};
6945
6946struct mlx5_ifc_alloc_flow_counter_out_bits {
6947 u8 status[0x8];
6948 u8 reserved_at_8[0x18];
6949
6950 u8 syndrome[0x20];
6951
6952 u8 reserved_at_40[0x10];
6953 u8 flow_counter_id[0x10];
6954
6955 u8 reserved_at_60[0x20];
6956};
6957
6958struct mlx5_ifc_alloc_flow_counter_in_bits {
e281682b 6959 u8 opcode[0x10];
b4ff3a36 6960 u8 reserved_at_10[0x10];
e281682b 6961
b4ff3a36 6962 u8 reserved_at_20[0x10];
e281682b
SM		 6963 u8 op_mod[0x10];
6964
b4ff3a36 6965 u8 reserved_at_40[0x40];
e281682b
SM		 6966};
6967
6968struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
6969 u8 status[0x8];
b4ff3a36 6970 u8 reserved_at_8[0x18];
e281682b
SM		 6971
6972 u8 syndrome[0x20];
6973
b4ff3a36 6974 u8 reserved_at_40[0x40];
e281682b
SM		 6975};
6976
6977struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
6978 u8 opcode[0x10];
b4ff3a36 6979 u8 reserved_at_10[0x10];
e281682b 6980
b4ff3a36 6981 u8 reserved_at_20[0x10];
e281682b
SM		 6982 u8 op_mod[0x10];
6983
b4ff3a36 6984 u8 reserved_at_40[0x20];
e281682b 6985
b4ff3a36 6986 u8 reserved_at_60[0x10];
e281682b
SM		 6987 u8 vxlan_udp_port[0x10];
6988};
6989
7486216b
SM		 6990struct mlx5_ifc_set_rate_limit_out_bits {
6991 u8 status[0x8];
6992 u8 reserved_at_8[0x18];
6993
6994 u8 syndrome[0x20];
6995
6996 u8 reserved_at_40[0x40];
6997};
6998
6999struct mlx5_ifc_set_rate_limit_in_bits {
7000 u8 opcode[0x10];
7001 u8 reserved_at_10[0x10];
7002
7003 u8 reserved_at_20[0x10];
7004 u8 op_mod[0x10];
7005
7006 u8 reserved_at_40[0x10];
7007 u8 rate_limit_index[0x10];
7008
7009 u8 reserved_at_60[0x20];
7010
7011 u8 rate_limit[0x20];
7012};
7013
e281682b
SM		 7014struct mlx5_ifc_access_register_out_bits {
7015 u8 status[0x8];
b4ff3a36 7016 u8 reserved_at_8[0x18];
e281682b
SM		 7017
7018 u8 syndrome[0x20];
7019
b4ff3a36 7020 u8 reserved_at_40[0x40];
e281682b
SM		 7021
7022 u8 register_data[0][0x20];
7023};
7024
7025enum {
7026 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
7027 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
7028};
7029
7030struct mlx5_ifc_access_register_in_bits {
7031 u8 opcode[0x10];
b4ff3a36 7032 u8 reserved_at_10[0x10];
e281682b 7033
b4ff3a36 7034 u8 reserved_at_20[0x10];
e281682b
SM		 7035 u8 op_mod[0x10];
7036
b4ff3a36 7037 u8 reserved_at_40[0x10];
e281682b
SM		 7038 u8 register_id[0x10];
7039
7040 u8 argument[0x20];
7041
7042 u8 register_data[0][0x20];
7043};
7044
7045struct mlx5_ifc_sltp_reg_bits {
7046 u8 status[0x4];
7047 u8 version[0x4];
7048 u8 local_port[0x8];
7049 u8 pnat[0x2];
b4ff3a36 7050 u8 reserved_at_12[0x2];
e281682b 7051 u8 lane[0x4];
b4ff3a36 7052 u8 reserved_at_18[0x8];
e281682b 7053
b4ff3a36 7054 u8 reserved_at_20[0x20];
e281682b 7055
b4ff3a36 7056 u8 reserved_at_40[0x7];
e281682b
SM		 7057 u8 polarity[0x1];
7058 u8 ob_tap0[0x8];
7059 u8 ob_tap1[0x8];
7060 u8 ob_tap2[0x8];
7061
b4ff3a36 7062 u8 reserved_at_60[0xc];
e281682b
SM		 7063 u8 ob_preemp_mode[0x4];
7064 u8 ob_reg[0x8];
7065 u8 ob_bias[0x8];
7066
b4ff3a36 7067 u8 reserved_at_80[0x20];
e281682b
SM		 7068};
7069
7070struct mlx5_ifc_slrg_reg_bits {
7071 u8 status[0x4];
7072 u8 version[0x4];
7073 u8 local_port[0x8];
7074 u8 pnat[0x2];
b4ff3a36 7075 u8 reserved_at_12[0x2];
e281682b 7076 u8 lane[0x4];
b4ff3a36 7077 u8 reserved_at_18[0x8];
e281682b
SM		 7078
7079 u8 time_to_link_up[0x10];
b4ff3a36 7080 u8 reserved_at_30[0xc];
e281682b
SM		 7081 u8 grade_lane_speed[0x4];
7082
7083 u8 grade_version[0x8];
7084 u8 grade[0x18];
7085
b4ff3a36 7086 u8 reserved_at_60[0x4];
e281682b
SM		 7087 u8 height_grade_type[0x4];
7088 u8 height_grade[0x18];
7089
7090 u8 height_dz[0x10];
7091 u8 height_dv[0x10];
7092
b4ff3a36 7093 u8 reserved_at_a0[0x10];
e281682b
SM		 7094 u8 height_sigma[0x10];
7095
b4ff3a36 7096 u8 reserved_at_c0[0x20];
e281682b 7097
b4ff3a36 7098 u8 reserved_at_e0[0x4];
e281682b
SM		 7099 u8 phase_grade_type[0x4];
7100 u8 phase_grade[0x18];
7101
b4ff3a36 7102 u8 reserved_at_100[0x8];
e281682b 7103 u8 phase_eo_pos[0x8];
b4ff3a36 7104 u8 reserved_at_110[0x8];
e281682b
SM		 7105 u8 phase_eo_neg[0x8];
7106
7107 u8 ffe_set_tested[0x10];
7108 u8 test_errors_per_lane[0x10];
7109};
7110
7111struct mlx5_ifc_pvlc_reg_bits {
b4ff3a36 7112 u8 reserved_at_0[0x8];
e281682b 7113 u8 local_port[0x8];
b4ff3a36 7114 u8 reserved_at_10[0x10];
e281682b 7115
b4ff3a36 7116 u8 reserved_at_20[0x1c];
e281682b
SM		 7117 u8 vl_hw_cap[0x4];
7118
b4ff3a36 7119 u8 reserved_at_40[0x1c];
e281682b
SM		 7120 u8 vl_admin[0x4];
7121
b4ff3a36 7122 u8 reserved_at_60[0x1c];
e281682b
SM		 7123 u8 vl_operational[0x4];
7124};
7125
7126struct mlx5_ifc_pude_reg_bits {
7127 u8 swid[0x8];
7128 u8 local_port[0x8];
b4ff3a36 7129 u8 reserved_at_10[0x4];
e281682b 7130 u8 admin_status[0x4];
b4ff3a36 7131 u8 reserved_at_18[0x4];
e281682b
SM		 7132 u8 oper_status[0x4];
7133
b4ff3a36 7134 u8 reserved_at_20[0x60];
e281682b
SM		 7135};
7136
7137struct mlx5_ifc_ptys_reg_bits {
e7e31ca4 7138 u8 reserved_at_0[0x1];
7486216b 7139 u8 an_disable_admin[0x1];
e7e31ca4
BW		 7140 u8 an_disable_cap[0x1];
7141 u8 reserved_at_3[0x5];
e281682b 7142 u8 local_port[0x8];
b4ff3a36 7143 u8 reserved_at_10[0xd];
e281682b
SM		 7144 u8 proto_mask[0x3];
7145
7486216b
SM		 7146 u8 an_status[0x4];
7147 u8 reserved_at_24[0x3c];
e281682b
SM		 7148
7149 u8 eth_proto_capability[0x20];
7150
7151 u8 ib_link_width_capability[0x10];
7152 u8 ib_proto_capability[0x10];
7153
b4ff3a36 7154 u8 reserved_at_a0[0x20];
e281682b
SM		 7155
7156 u8 eth_proto_admin[0x20];
7157
7158 u8 ib_link_width_admin[0x10];
7159 u8 ib_proto_admin[0x10];
7160
b4ff3a36 7161 u8 reserved_at_100[0x20];
e281682b
SM		 7162
7163 u8 eth_proto_oper[0x20];
7164
7165 u8 ib_link_width_oper[0x10];
7166 u8 ib_proto_oper[0x10];
7167
b4ff3a36 7168 u8 reserved_at_160[0x20];
e281682b
SM		 7169
7170 u8 eth_proto_lp_advertise[0x20];
7171
b4ff3a36 7172 u8 reserved_at_1a0[0x60];
e281682b
SM		 7173};
7174
7d5e1423
SM		 7175struct mlx5_ifc_mlcr_reg_bits {
7176 u8 reserved_at_0[0x8];
7177 u8 local_port[0x8];
7178 u8 reserved_at_10[0x20];
7179
7180 u8 beacon_duration[0x10];
7181 u8 reserved_at_40[0x10];
7182
7183 u8 beacon_remain[0x10];
7184};
7185
e281682b 7186struct mlx5_ifc_ptas_reg_bits {
b4ff3a36 7187 u8 reserved_at_0[0x20];
e281682b
SM		 7188
7189 u8 algorithm_options[0x10];
b4ff3a36 7190 u8 reserved_at_30[0x4];
e281682b
SM		 7191 u8 repetitions_mode[0x4];
7192 u8 num_of_repetitions[0x8];
7193
7194 u8 grade_version[0x8];
7195 u8 height_grade_type[0x4];
7196 u8 phase_grade_type[0x4];
7197 u8 height_grade_weight[0x8];
7198 u8 phase_grade_weight[0x8];
7199
7200 u8 gisim_measure_bits[0x10];
7201 u8 adaptive_tap_measure_bits[0x10];
7202
7203 u8 ber_bath_high_error_threshold[0x10];
7204 u8 ber_bath_mid_error_threshold[0x10];
7205
7206 u8 ber_bath_low_error_threshold[0x10];
7207 u8 one_ratio_high_threshold[0x10];
7208
7209 u8 one_ratio_high_mid_threshold[0x10];
7210 u8 one_ratio_low_mid_threshold[0x10];
7211
7212 u8 one_ratio_low_threshold[0x10];
7213 u8 ndeo_error_threshold[0x10];
7214
7215 u8 mixer_offset_step_size[0x10];
b4ff3a36 7216 u8 reserved_at_110[0x8];
e281682b
SM		 7217 u8 mix90_phase_for_voltage_bath[0x8];
7218
7219 u8 mixer_offset_start[0x10];
7220 u8 mixer_offset_end[0x10];
7221
b4ff3a36 7222 u8 reserved_at_140[0x15];
e281682b
SM		 7223 u8 ber_test_time[0xb];
7224};
7225
7226struct mlx5_ifc_pspa_reg_bits {
7227 u8 swid[0x8];
7228 u8 local_port[0x8];
7229 u8 sub_port[0x8];
b4ff3a36 7230 u8 reserved_at_18[0x8];
e281682b 7231
b4ff3a36 7232 u8 reserved_at_20[0x20];
e281682b
SM		 7233};
7234
7235struct mlx5_ifc_pqdr_reg_bits {
b4ff3a36 7236 u8 reserved_at_0[0x8];
e281682b 7237 u8 local_port[0x8];
b4ff3a36 7238 u8 reserved_at_10[0x5];
e281682b 7239 u8 prio[0x3];
b4ff3a36 7240 u8 reserved_at_18[0x6];
e281682b
SM		 7241 u8 mode[0x2];
7242
b4ff3a36 7243 u8 reserved_at_20[0x20];
e281682b 7244
b4ff3a36 7245 u8 reserved_at_40[0x10];
e281682b
SM		 7246 u8 min_threshold[0x10];
7247
b4ff3a36 7248 u8 reserved_at_60[0x10];
e281682b
SM		 7249 u8 max_threshold[0x10];
7250
b4ff3a36 7251 u8 reserved_at_80[0x10];
e281682b
SM		 7252 u8 mark_probability_denominator[0x10];
7253
b4ff3a36 7254 u8 reserved_at_a0[0x60];
e281682b
SM		 7255};
7256
7257struct mlx5_ifc_ppsc_reg_bits {
b4ff3a36 7258 u8 reserved_at_0[0x8];
e281682b 7259 u8 local_port[0x8];
b4ff3a36 7260 u8 reserved_at_10[0x10];
e281682b 7261
b4ff3a36 7262 u8 reserved_at_20[0x60];
e281682b 7263
b4ff3a36 7264 u8 reserved_at_80[0x1c];
e281682b
SM		 7265 u8 wrps_admin[0x4];
7266
b4ff3a36 7267 u8 reserved_at_a0[0x1c];
e281682b
SM		 7268 u8 wrps_status[0x4];
7269
b4ff3a36 7270 u8 reserved_at_c0[0x8];
e281682b 7271 u8 up_threshold[0x8];
b4ff3a36 7272 u8 reserved_at_d0[0x8];
e281682b
SM		 7273 u8 down_threshold[0x8];
7274
b4ff3a36 7275 u8 reserved_at_e0[0x20];
e281682b 7276
b4ff3a36 7277 u8 reserved_at_100[0x1c];
e281682b
SM		 7278 u8 srps_admin[0x4];
7279
b4ff3a36 7280 u8 reserved_at_120[0x1c];
e281682b
SM		 7281 u8 srps_status[0x4];
7282
b4ff3a36 7283 u8 reserved_at_140[0x40];
e281682b
SM		 7284};
7285
7286struct mlx5_ifc_pplr_reg_bits {
b4ff3a36 7287 u8 reserved_at_0[0x8];
e281682b 7288 u8 local_port[0x8];
b4ff3a36 7289 u8 reserved_at_10[0x10];
e281682b 7290
b4ff3a36 7291 u8 reserved_at_20[0x8];
e281682b 7292 u8 lb_cap[0x8];
b4ff3a36 7293 u8 reserved_at_30[0x8];
e281682b
SM		 7294 u8 lb_en[0x8];
7295};
7296
7297struct mlx5_ifc_pplm_reg_bits {
b4ff3a36 7298 u8 reserved_at_0[0x8];
e281682b 7299 u8 local_port[0x8];
b4ff3a36 7300 u8 reserved_at_10[0x10];
e281682b 7301
b4ff3a36 7302 u8 reserved_at_20[0x20];
e281682b
SM		 7303
7304 u8 port_profile_mode[0x8];
7305 u8 static_port_profile[0x8];
7306 u8 active_port_profile[0x8];
b4ff3a36 7307 u8 reserved_at_58[0x8];
e281682b
SM		 7308
7309 u8 retransmission_active[0x8];
7310 u8 fec_mode_active[0x18];
7311
b4ff3a36 7312 u8 reserved_at_80[0x20];
e281682b
SM		 7313};
7314
7315struct mlx5_ifc_ppcnt_reg_bits {
7316 u8 swid[0x8];
7317 u8 local_port[0x8];
7318 u8 pnat[0x2];
b4ff3a36 7319 u8 reserved_at_12[0x8];
e281682b
SM		 7320 u8 grp[0x6];
7321
7322 u8 clr[0x1];
b4ff3a36 7323 u8 reserved_at_21[0x1c];
e281682b
SM		 7324 u8 prio_tc[0x3];
7325
7326 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
7327};
7328
7f503169
GP		 7329struct mlx5_ifc_mpcnt_reg_bits {
7330 u8 reserved_at_0[0x8];
7331 u8 pcie_index[0x8];
7332 u8 reserved_at_10[0xa];
7333 u8 grp[0x6];
7334
7335 u8 clr[0x1];
7336 u8 reserved_at_21[0x1f];
7337
7338 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
7339};
7340
e281682b 7341struct mlx5_ifc_ppad_reg_bits {
b4ff3a36 7342 u8 reserved_at_0[0x3];
e281682b 7343 u8 single_mac[0x1];
b4ff3a36 7344 u8 reserved_at_4[0x4];
e281682b
SM		 7345 u8 local_port[0x8];
7346 u8 mac_47_32[0x10];
7347
7348 u8 mac_31_0[0x20];
7349
b4ff3a36 7350 u8 reserved_at_40[0x40];
e281682b
SM		 7351};
7352
7353struct mlx5_ifc_pmtu_reg_bits {
b4ff3a36 7354 u8 reserved_at_0[0x8];
e281682b 7355 u8 local_port[0x8];
b4ff3a36 7356 u8 reserved_at_10[0x10];
e281682b
SM		 7357
7358 u8 max_mtu[0x10];
b4ff3a36 7359 u8 reserved_at_30[0x10];
e281682b
SM		 7360
7361 u8 admin_mtu[0x10];
b4ff3a36 7362 u8 reserved_at_50[0x10];
e281682b
SM		 7363
7364 u8 oper_mtu[0x10];
b4ff3a36 7365 u8 reserved_at_70[0x10];
e281682b
SM		 7366};
7367
7368struct mlx5_ifc_pmpr_reg_bits {
b4ff3a36 7369 u8 reserved_at_0[0x8];
e281682b 7370 u8 module[0x8];
b4ff3a36 7371 u8 reserved_at_10[0x10];
e281682b 7372
b4ff3a36 7373 u8 reserved_at_20[0x18];
e281682b
SM		 7374 u8 attenuation_5g[0x8];
7375
b4ff3a36 7376 u8 reserved_at_40[0x18];
e281682b
SM		 7377 u8 attenuation_7g[0x8];
7378
b4ff3a36 7379 u8 reserved_at_60[0x18];
e281682b
SM		 7380 u8 attenuation_12g[0x8];
7381};
7382
7383struct mlx5_ifc_pmpe_reg_bits {
b4ff3a36 7384 u8 reserved_at_0[0x8];
e281682b 7385 u8 module[0x8];
b4ff3a36 7386 u8 reserved_at_10[0xc];
e281682b
SM		 7387 u8 module_status[0x4];
7388
b4ff3a36 7389 u8 reserved_at_20[0x60];
e281682b
SM		 7390};
7391
7392struct mlx5_ifc_pmpc_reg_bits {
7393 u8 module_state_updated[32][0x8];
7394};
7395
7396struct mlx5_ifc_pmlpn_reg_bits {
b4ff3a36 7397 u8 reserved_at_0[0x4];
e281682b
SM		 7398 u8 mlpn_status[0x4];
7399 u8 local_port[0x8];
b4ff3a36 7400 u8 reserved_at_10[0x10];
e281682b
SM		 7401
7402 u8 e[0x1];
b4ff3a36 7403 u8 reserved_at_21[0x1f];
e281682b
SM		 7404};
7405
7406struct mlx5_ifc_pmlp_reg_bits {
7407 u8 rxtx[0x1];
b4ff3a36 7408 u8 reserved_at_1[0x7];
e281682b 7409 u8 local_port[0x8];
b4ff3a36 7410 u8 reserved_at_10[0x8];
e281682b
SM		 7411 u8 width[0x8];
7412
7413 u8 lane0_module_mapping[0x20];
7414
7415 u8 lane1_module_mapping[0x20];
7416
7417 u8 lane2_module_mapping[0x20];
7418
7419 u8 lane3_module_mapping[0x20];
7420
b4ff3a36 7421 u8 reserved_at_a0[0x160];
e281682b
SM		 7422};
7423
7424struct mlx5_ifc_pmaos_reg_bits {
b4ff3a36 7425 u8 reserved_at_0[0x8];
e281682b 7426 u8 module[0x8];
b4ff3a36 7427 u8 reserved_at_10[0x4];
e281682b 7428 u8 admin_status[0x4];
b4ff3a36 7429 u8 reserved_at_18[0x4];
e281682b
SM		 7430 u8 oper_status[0x4];
7431
7432 u8 ase[0x1];
7433 u8 ee[0x1];
b4ff3a36 7434 u8 reserved_at_22[0x1c];
e281682b
SM		 7435 u8 e[0x2];
7436
b4ff3a36 7437 u8 reserved_at_40[0x40];
e281682b
SM		 7438};
7439
7440struct mlx5_ifc_plpc_reg_bits {
b4ff3a36 7441 u8 reserved_at_0[0x4];
e281682b 7442 u8 profile_id[0xc];
b4ff3a36 7443 u8 reserved_at_10[0x4];
e281682b 7444 u8 proto_mask[0x4];
b4ff3a36 7445 u8 reserved_at_18[0x8];
e281682b 7446
b4ff3a36 7447 u8 reserved_at_20[0x10];
e281682b
SM		 7448 u8 lane_speed[0x10];
7449
b4ff3a36 7450 u8 reserved_at_40[0x17];
e281682b
SM		 7451 u8 lpbf[0x1];
7452 u8 fec_mode_policy[0x8];
7453
7454 u8 retransmission_capability[0x8];
7455 u8 fec_mode_capability[0x18];
7456
7457 u8 retransmission_support_admin[0x8];
7458 u8 fec_mode_support_admin[0x18];
7459
7460 u8 retransmission_request_admin[0x8];
7461 u8 fec_mode_request_admin[0x18];
7462
b4ff3a36 7463 u8 reserved_at_c0[0x80];
e281682b
SM		 7464};
7465
7466struct mlx5_ifc_plib_reg_bits {
b4ff3a36 7467 u8 reserved_at_0[0x8];
e281682b 7468 u8 local_port[0x8];
b4ff3a36 7469 u8 reserved_at_10[0x8];
e281682b
SM		 7470 u8 ib_port[0x8];
7471
b4ff3a36 7472 u8 reserved_at_20[0x60];
e281682b
SM		 7473};
7474
7475struct mlx5_ifc_plbf_reg_bits {
b4ff3a36 7476 u8 reserved_at_0[0x8];
e281682b 7477 u8 local_port[0x8];
b4ff3a36 7478 u8 reserved_at_10[0xd];
e281682b
SM		 7479 u8 lbf_mode[0x3];
7480
b4ff3a36 7481 u8 reserved_at_20[0x20];
e281682b
SM		 7482};
7483
7484struct mlx5_ifc_pipg_reg_bits {
b4ff3a36 7485 u8 reserved_at_0[0x8];
e281682b 7486 u8 local_port[0x8];
b4ff3a36 7487 u8 reserved_at_10[0x10];
e281682b
SM		 7488
7489 u8 dic[0x1];
b4ff3a36 7490 u8 reserved_at_21[0x19];
e281682b 7491 u8 ipg[0x4];
b4ff3a36 7492 u8 reserved_at_3e[0x2];
e281682b
SM		 7493};
7494
7495struct mlx5_ifc_pifr_reg_bits {
b4ff3a36 7496 u8 reserved_at_0[0x8];
e281682b 7497 u8 local_port[0x8];
b4ff3a36 7498 u8 reserved_at_10[0x10];
e281682b 7499
b4ff3a36 7500 u8 reserved_at_20[0xe0];
e281682b
SM		 7501
7502 u8 port_filter[8][0x20];
7503
7504 u8 port_filter_update_en[8][0x20];
7505};
7506
7507struct mlx5_ifc_pfcc_reg_bits {
b4ff3a36 7508 u8 reserved_at_0[0x8];
e281682b 7509 u8 local_port[0x8];
b4ff3a36 7510 u8 reserved_at_10[0x10];
e281682b
SM		 7511
7512 u8 ppan[0x4];
b4ff3a36 7513 u8 reserved_at_24[0x4];
e281682b 7514 u8 prio_mask_tx[0x8];
b4ff3a36 7515 u8 reserved_at_30[0x8];
e281682b
SM		 7516 u8 prio_mask_rx[0x8];
7517
7518 u8 pptx[0x1];
7519 u8 aptx[0x1];
b4ff3a36 7520 u8 reserved_at_42[0x6];
e281682b 7521 u8 pfctx[0x8];
b4ff3a36 7522 u8 reserved_at_50[0x10];
e281682b
SM		 7523
7524 u8 pprx[0x1];
7525 u8 aprx[0x1];
b4ff3a36 7526 u8 reserved_at_62[0x6];
e281682b 7527 u8 pfcrx[0x8];
b4ff3a36 7528 u8 reserved_at_70[0x10];
e281682b 7529
b4ff3a36 7530 u8 reserved_at_80[0x80];
e281682b
SM		 7531};
7532
7533struct mlx5_ifc_pelc_reg_bits {
7534 u8 op[0x4];
b4ff3a36 7535 u8 reserved_at_4[0x4];
e281682b 7536 u8 local_port[0x8];
b4ff3a36 7537 u8 reserved_at_10[0x10];
e281682b
SM		 7538
7539 u8 op_admin[0x8];
7540 u8 op_capability[0x8];
7541 u8 op_request[0x8];
7542 u8 op_active[0x8];
7543
7544 u8 admin[0x40];
7545
7546 u8 capability[0x40];
7547
7548 u8 request[0x40];
7549
7550 u8 active[0x40];
7551
b4ff3a36 7552 u8 reserved_at_140[0x80];
e281682b
SM		 7553};
7554
7555struct mlx5_ifc_peir_reg_bits {
b4ff3a36 7556 u8 reserved_at_0[0x8];
e281682b 7557 u8 local_port[0x8];
b4ff3a36 7558 u8 reserved_at_10[0x10];
e281682b 7559
b4ff3a36 7560 u8 reserved_at_20[0xc];
e281682b 7561 u8 error_count[0x4];
b4ff3a36 7562 u8 reserved_at_30[0x10];
e281682b 7563
b4ff3a36 7564 u8 reserved_at_40[0xc];
e281682b 7565 u8 lane[0x4];
b4ff3a36 7566 u8 reserved_at_50[0x8];
e281682b
SM		 7567 u8 error_type[0x8];
7568};
7569
7570struct mlx5_ifc_pcap_reg_bits {
b4ff3a36 7571 u8 reserved_at_0[0x8];
e281682b 7572 u8 local_port[0x8];
b4ff3a36 7573 u8 reserved_at_10[0x10];
e281682b
SM		 7574
7575 u8 port_capability_mask[4][0x20];
7576};
7577
7578struct mlx5_ifc_paos_reg_bits {
7579 u8 swid[0x8];
7580 u8 local_port[0x8];
b4ff3a36 7581 u8 reserved_at_10[0x4];
e281682b 7582 u8 admin_status[0x4];
b4ff3a36 7583 u8 reserved_at_18[0x4];
e281682b
SM		 7584 u8 oper_status[0x4];
7585
7586 u8 ase[0x1];
7587 u8 ee[0x1];
b4ff3a36 7588 u8 reserved_at_22[0x1c];
e281682b
SM		 7589 u8 e[0x2];
7590
b4ff3a36 7591 u8 reserved_at_40[0x40];
e281682b
SM		 7592};
7593
7594struct mlx5_ifc_pamp_reg_bits {
b4ff3a36 7595 u8 reserved_at_0[0x8];
e281682b 7596 u8 opamp_group[0x8];
b4ff3a36 7597 u8 reserved_at_10[0xc];
e281682b
SM		 7598 u8 opamp_group_type[0x4];
7599
7600 u8 start_index[0x10];
b4ff3a36 7601 u8 reserved_at_30[0x4];
e281682b
SM		 7602 u8 num_of_indices[0xc];
7603
7604 u8 index_data[18][0x10];
7605};
7606
7d5e1423
SM		 7607struct mlx5_ifc_pcmr_reg_bits {
7608 u8 reserved_at_0[0x8];
7609 u8 local_port[0x8];
7610 u8 reserved_at_10[0x2e];
7611 u8 fcs_cap[0x1];
7612 u8 reserved_at_3f[0x1f];
7613 u8 fcs_chk[0x1];
7614 u8 reserved_at_5f[0x1];
7615};
7616
e281682b 7617struct mlx5_ifc_lane_2_module_mapping_bits {
b4ff3a36 7618 u8 reserved_at_0[0x6];
e281682b 7619 u8 rx_lane[0x2];
b4ff3a36 7620 u8 reserved_at_8[0x6];
e281682b 7621 u8 tx_lane[0x2];
b4ff3a36 7622 u8 reserved_at_10[0x8];
e281682b
SM		 7623 u8 module[0x8];
7624};
7625
7626struct mlx5_ifc_bufferx_reg_bits {
b4ff3a36 7627 u8 reserved_at_0[0x6];
e281682b
SM		 7628 u8 lossy[0x1];
7629 u8 epsb[0x1];
b4ff3a36 7630 u8 reserved_at_8[0xc];
e281682b
SM		 7631 u8 size[0xc];
7632
7633 u8 xoff_threshold[0x10];
7634 u8 xon_threshold[0x10];
7635};
7636
7637struct mlx5_ifc_set_node_in_bits {
7638 u8 node_description[64][0x8];
7639};
7640
7641struct mlx5_ifc_register_power_settings_bits {
b4ff3a36 7642 u8 reserved_at_0[0x18];
e281682b
SM		 7643 u8 power_settings_level[0x8];
7644
b4ff3a36 7645 u8 reserved_at_20[0x60];
e281682b
SM		 7646};
7647
7648struct mlx5_ifc_register_host_endianness_bits {
7649 u8 he[0x1];
b4ff3a36 7650 u8 reserved_at_1[0x1f];
e281682b 7651
b4ff3a36 7652 u8 reserved_at_20[0x60];
e281682b
SM		 7653};
7654
7655struct mlx5_ifc_umr_pointer_desc_argument_bits {
b4ff3a36 7656 u8 reserved_at_0[0x20];
e281682b
SM		 7657
7658 u8 mkey[0x20];
7659
7660 u8 addressh_63_32[0x20];
7661
7662 u8 addressl_31_0[0x20];
7663};
7664
7665struct mlx5_ifc_ud_adrs_vector_bits {
7666 u8 dc_key[0x40];
7667
7668 u8 ext[0x1];
b4ff3a36 7669 u8 reserved_at_41[0x7];
e281682b
SM		 7670 u8 destination_qp_dct[0x18];
7671
7672 u8 static_rate[0x4];
7673 u8 sl_eth_prio[0x4];
7674 u8 fl[0x1];
7675 u8 mlid[0x7];
7676 u8 rlid_udp_sport[0x10];
7677
b4ff3a36 7678 u8 reserved_at_80[0x20];
e281682b
SM		 7679
7680 u8 rmac_47_16[0x20];
7681
7682 u8 rmac_15_0[0x10];
7683 u8 tclass[0x8];
7684 u8 hop_limit[0x8];
7685
b4ff3a36 7686 u8 reserved_at_e0[0x1];
e281682b 7687 u8 grh[0x1];
b4ff3a36 7688 u8 reserved_at_e2[0x2];
e281682b
SM		 7689 u8 src_addr_index[0x8];
7690 u8 flow_label[0x14];
7691
7692 u8 rgid_rip[16][0x8];
7693};
7694
7695struct mlx5_ifc_pages_req_event_bits {
b4ff3a36 7696 u8 reserved_at_0[0x10];
e281682b
SM		 7697 u8 function_id[0x10];
7698
7699 u8 num_pages[0x20];
7700
b4ff3a36 7701 u8 reserved_at_40[0xa0];
e281682b
SM		 7702};
7703
7704struct mlx5_ifc_eqe_bits {
b4ff3a36 7705 u8 reserved_at_0[0x8];
e281682b 7706 u8 event_type[0x8];
b4ff3a36 7707 u8 reserved_at_10[0x8];
e281682b
SM		 7708 u8 event_sub_type[0x8];
7709
b4ff3a36 7710 u8 reserved_at_20[0xe0];
e281682b
SM		 7711
7712 union mlx5_ifc_event_auto_bits event_data;
7713
b4ff3a36 7714 u8 reserved_at_1e0[0x10];
e281682b 7715 u8 signature[0x8];
b4ff3a36 7716 u8 reserved_at_1f8[0x7];
e281682b
SM		 7717 u8 owner[0x1];
7718};
7719
7720enum {
7721 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
7722};
7723
7724struct mlx5_ifc_cmd_queue_entry_bits {
7725 u8 type[0x8];
b4ff3a36 7726 u8 reserved_at_8[0x18];
e281682b
SM		 7727
7728 u8 input_length[0x20];
7729
7730 u8 input_mailbox_pointer_63_32[0x20];
7731
7732 u8 input_mailbox_pointer_31_9[0x17];
b4ff3a36 7733 u8 reserved_at_77[0x9];
e281682b
SM		 7734
7735 u8 command_input_inline_data[16][0x8];
7736
7737 u8 command_output_inline_data[16][0x8];
7738
7739 u8 output_mailbox_pointer_63_32[0x20];
7740
7741 u8 output_mailbox_pointer_31_9[0x17];
b4ff3a36 7742 u8 reserved_at_1b7[0x9];
e281682b
SM		 7743
7744 u8 output_length[0x20];
7745
7746 u8 token[0x8];
7747 u8 signature[0x8];
b4ff3a36 7748 u8 reserved_at_1f0[0x8];
e281682b
SM		 7749 u8 status[0x7];
7750 u8 ownership[0x1];
7751};
7752
7753struct mlx5_ifc_cmd_out_bits {
7754 u8 status[0x8];
b4ff3a36 7755 u8 reserved_at_8[0x18];
e281682b
SM		 7756
7757 u8 syndrome[0x20];
7758
7759 u8 command_output[0x20];
7760};
7761
7762struct mlx5_ifc_cmd_in_bits {
7763 u8 opcode[0x10];
b4ff3a36 7764 u8 reserved_at_10[0x10];
e281682b 7765
b4ff3a36 7766 u8 reserved_at_20[0x10];
e281682b
SM		 7767 u8 op_mod[0x10];
7768
7769 u8 command[0][0x20];
7770};
7771
7772struct mlx5_ifc_cmd_if_box_bits {
7773 u8 mailbox_data[512][0x8];
7774
b4ff3a36 7775 u8 reserved_at_1000[0x180];
e281682b
SM		 7776
7777 u8 next_pointer_63_32[0x20];
7778
7779 u8 next_pointer_31_10[0x16];
b4ff3a36 7780 u8 reserved_at_11b6[0xa];
e281682b
SM		 7781
7782 u8 block_number[0x20];
7783
b4ff3a36 7784 u8 reserved_at_11e0[0x8];
e281682b
SM		 7785 u8 token[0x8];
7786 u8 ctrl_signature[0x8];
7787 u8 signature[0x8];
7788};
7789
7790struct mlx5_ifc_mtt_bits {
7791 u8 ptag_63_32[0x20];
7792
7793 u8 ptag_31_8[0x18];
b4ff3a36 7794 u8 reserved_at_38[0x6];
e281682b
SM		 7795 u8 wr_en[0x1];
7796 u8 rd_en[0x1];
7797};
7798
928cfe87
TT		 7799struct mlx5_ifc_query_wol_rol_out_bits {
7800 u8 status[0x8];
7801 u8 reserved_at_8[0x18];
7802
7803 u8 syndrome[0x20];
7804
7805 u8 reserved_at_40[0x10];
7806 u8 rol_mode[0x8];
7807 u8 wol_mode[0x8];
7808
7809 u8 reserved_at_60[0x20];
7810};
7811
7812struct mlx5_ifc_query_wol_rol_in_bits {
7813 u8 opcode[0x10];
7814 u8 reserved_at_10[0x10];
7815
7816 u8 reserved_at_20[0x10];
7817 u8 op_mod[0x10];
7818
7819 u8 reserved_at_40[0x40];
7820};
7821
7822struct mlx5_ifc_set_wol_rol_out_bits {
7823 u8 status[0x8];
7824 u8 reserved_at_8[0x18];
7825
7826 u8 syndrome[0x20];
7827
7828 u8 reserved_at_40[0x40];
7829};
7830
7831struct mlx5_ifc_set_wol_rol_in_bits {
7832 u8 opcode[0x10];
7833 u8 reserved_at_10[0x10];
7834
7835 u8 reserved_at_20[0x10];
7836 u8 op_mod[0x10];
7837
7838 u8 rol_mode_valid[0x1];
7839 u8 wol_mode_valid[0x1];
7840 u8 reserved_at_42[0xe];
7841 u8 rol_mode[0x8];
7842 u8 wol_mode[0x8];
7843
7844 u8 reserved_at_60[0x20];
7845};
7846
e281682b
SM		 7847enum {
7848 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
7849 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
7850 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
7851};
7852
7853enum {
7854 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
7855 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
7856 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
7857};
7858
7859enum {
7860 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
7861 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
7862 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
7863 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
7864 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
7865 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
7866 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
7867 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
7868 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
7869 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
7870 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
7871};
7872
7873struct mlx5_ifc_initial_seg_bits {
7874 u8 fw_rev_minor[0x10];
7875 u8 fw_rev_major[0x10];
7876
7877 u8 cmd_interface_rev[0x10];
7878 u8 fw_rev_subminor[0x10];
7879
b4ff3a36 7880 u8 reserved_at_40[0x40];
e281682b
SM		 7881
7882 u8 cmdq_phy_addr_63_32[0x20];
7883
7884 u8 cmdq_phy_addr_31_12[0x14];
b4ff3a36 7885 u8 reserved_at_b4[0x2];
e281682b
SM		 7886 u8 nic_interface[0x2];
7887 u8 log_cmdq_size[0x4];
7888 u8 log_cmdq_stride[0x4];
7889
7890 u8 command_doorbell_vector[0x20];
7891
b4ff3a36 7892 u8 reserved_at_e0[0xf00];
e281682b
SM		 7893
7894 u8 initializing[0x1];
b4ff3a36 7895 u8 reserved_at_fe1[0x4];
e281682b 7896 u8 nic_interface_supported[0x3];
b4ff3a36 7897 u8 reserved_at_fe8[0x18];
e281682b
SM		 7898
7899 struct mlx5_ifc_health_buffer_bits health_buffer;
7900
7901 u8 no_dram_nic_offset[0x20];
7902
b4ff3a36 7903 u8 reserved_at_1220[0x6e40];
e281682b 7904
b4ff3a36 7905 u8 reserved_at_8060[0x1f];
e281682b
SM		 7906 u8 clear_int[0x1];
7907
7908 u8 health_syndrome[0x8];
7909 u8 health_counter[0x18];
7910
b4ff3a36 7911 u8 reserved_at_80a0[0x17fc0];
e281682b
SM		 7912};
7913
7914union mlx5_ifc_ports_control_registers_document_bits {
7915 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
7916 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
7917 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
7918 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
7919 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
7920 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
7921 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
7922 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
7923 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
7924 struct mlx5_ifc_pamp_reg_bits pamp_reg;
7925 struct mlx5_ifc_paos_reg_bits paos_reg;
7926 struct mlx5_ifc_pcap_reg_bits pcap_reg;
7927 struct mlx5_ifc_peir_reg_bits peir_reg;
7928 struct mlx5_ifc_pelc_reg_bits pelc_reg;
7929 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
1c64bf6f 7930 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b
SM		 7931 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
7932 struct mlx5_ifc_pifr_reg_bits pifr_reg;
7933 struct mlx5_ifc_pipg_reg_bits pipg_reg;
7934 struct mlx5_ifc_plbf_reg_bits plbf_reg;
7935 struct mlx5_ifc_plib_reg_bits plib_reg;
7936 struct mlx5_ifc_plpc_reg_bits plpc_reg;
7937 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
7938 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
7939 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
7940 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
7941 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
7942 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
7943 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
7944 struct mlx5_ifc_ppad_reg_bits ppad_reg;
7945 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
7f503169 7946 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
e281682b
SM		 7947 struct mlx5_ifc_pplm_reg_bits pplm_reg;
7948 struct mlx5_ifc_pplr_reg_bits pplr_reg;
7949 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
7950 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
7951 struct mlx5_ifc_pspa_reg_bits pspa_reg;
7952 struct mlx5_ifc_ptas_reg_bits ptas_reg;
7953 struct mlx5_ifc_ptys_reg_bits ptys_reg;
7d5e1423 7954 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
e281682b
SM		 7955 struct mlx5_ifc_pude_reg_bits pude_reg;
7956 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
7957 struct mlx5_ifc_slrg_reg_bits slrg_reg;
7958 struct mlx5_ifc_sltp_reg_bits sltp_reg;
b4ff3a36 7959 u8 reserved_at_0[0x60e0];
e281682b
SM		 7960};
7961
7962union mlx5_ifc_debug_enhancements_document_bits {
7963 struct mlx5_ifc_health_buffer_bits health_buffer;
b4ff3a36 7964 u8 reserved_at_0[0x200];
e281682b
SM		 7965};
7966
7967union mlx5_ifc_uplink_pci_interface_document_bits {
7968 struct mlx5_ifc_initial_seg_bits initial_seg;
b4ff3a36 7969 u8 reserved_at_0[0x20060];
b775516b
EC		 7970};
7971
2cc43b49
MG		 7972struct mlx5_ifc_set_flow_table_root_out_bits {
7973 u8 status[0x8];
b4ff3a36 7974 u8 reserved_at_8[0x18];
2cc43b49
MG		 7975
7976 u8 syndrome[0x20];
7977
b4ff3a36 7978 u8 reserved_at_40[0x40];
2cc43b49
MG		 7979};
7980
7981struct mlx5_ifc_set_flow_table_root_in_bits {
7982 u8 opcode[0x10];
b4ff3a36 7983 u8 reserved_at_10[0x10];
2cc43b49 7984
b4ff3a36 7985 u8 reserved_at_20[0x10];
2cc43b49
MG		 7986 u8 op_mod[0x10];
7987
7d5e1423
SM		 7988 u8 other_vport[0x1];
7989 u8 reserved_at_41[0xf];
7990 u8 vport_number[0x10];
7991
7992 u8 reserved_at_60[0x20];
2cc43b49
MG		 7993
7994 u8 table_type[0x8];
b4ff3a36 7995 u8 reserved_at_88[0x18];
2cc43b49 7996
b4ff3a36 7997 u8 reserved_at_a0[0x8];
2cc43b49
MG		 7998 u8 table_id[0x18];
7999
b4ff3a36 8000 u8 reserved_at_c0[0x140];
2cc43b49
MG		 8001};
8002
34a40e68 8003enum {
84df61eb
AH		 8004 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
8005 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
34a40e68
MG		 8006};
8007
8008struct mlx5_ifc_modify_flow_table_out_bits {
8009 u8 status[0x8];
b4ff3a36 8010 u8 reserved_at_8[0x18];
34a40e68
MG		 8011
8012 u8 syndrome[0x20];
8013
b4ff3a36 8014 u8 reserved_at_40[0x40];
34a40e68
MG		 8015};
8016
8017struct mlx5_ifc_modify_flow_table_in_bits {
8018 u8 opcode[0x10];
b4ff3a36 8019 u8 reserved_at_10[0x10];
34a40e68 8020
b4ff3a36 8021 u8 reserved_at_20[0x10];
34a40e68
MG		 8022 u8 op_mod[0x10];
8023
7d5e1423
SM		 8024 u8 other_vport[0x1];
8025 u8 reserved_at_41[0xf];
8026 u8 vport_number[0x10];
34a40e68 8027
b4ff3a36 8028 u8 reserved_at_60[0x10];
34a40e68
MG		 8029 u8 modify_field_select[0x10];
8030
8031 u8 table_type[0x8];
b4ff3a36 8032 u8 reserved_at_88[0x18];
34a40e68 8033
b4ff3a36 8034 u8 reserved_at_a0[0x8];
34a40e68
MG		 8035 u8 table_id[0x18];
8036
b4ff3a36 8037 u8 reserved_at_c0[0x4];
34a40e68 8038 u8 table_miss_mode[0x4];
b4ff3a36 8039 u8 reserved_at_c8[0x18];
34a40e68 8040
b4ff3a36 8041 u8 reserved_at_e0[0x8];
34a40e68
MG		 8042 u8 table_miss_id[0x18];
8043
84df61eb
AH		 8044 u8 reserved_at_100[0x8];
8045 u8 lag_master_next_table_id[0x18];
8046
8047 u8 reserved_at_120[0x80];
34a40e68
MG		 8048};
8049
4f3961ee
SM		 8050struct mlx5_ifc_ets_tcn_config_reg_bits {
8051 u8 g[0x1];
8052 u8 b[0x1];
8053 u8 r[0x1];
8054 u8 reserved_at_3[0x9];
8055 u8 group[0x4];
8056 u8 reserved_at_10[0x9];
8057 u8 bw_allocation[0x7];
8058
8059 u8 reserved_at_20[0xc];
8060 u8 max_bw_units[0x4];
8061 u8 reserved_at_30[0x8];
8062 u8 max_bw_value[0x8];
8063};
8064
8065struct mlx5_ifc_ets_global_config_reg_bits {
8066 u8 reserved_at_0[0x2];
8067 u8 r[0x1];
8068 u8 reserved_at_3[0x1d];
8069
8070 u8 reserved_at_20[0xc];
8071 u8 max_bw_units[0x4];
8072 u8 reserved_at_30[0x8];
8073 u8 max_bw_value[0x8];
8074};
8075
8076struct mlx5_ifc_qetc_reg_bits {
8077 u8 reserved_at_0[0x8];
8078 u8 port_number[0x8];
8079 u8 reserved_at_10[0x30];
8080
8081 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
8082 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
8083};
8084
8085struct mlx5_ifc_qtct_reg_bits {
8086 u8 reserved_at_0[0x8];
8087 u8 port_number[0x8];
8088 u8 reserved_at_10[0xd];
8089 u8 prio[0x3];
8090
8091 u8 reserved_at_20[0x1d];
8092 u8 tclass[0x3];
8093};
8094
7d5e1423
SM		 8095struct mlx5_ifc_mcia_reg_bits {
8096 u8 l[0x1];
8097 u8 reserved_at_1[0x7];
8098 u8 module[0x8];
8099 u8 reserved_at_10[0x8];
8100 u8 status[0x8];
8101
8102 u8 i2c_device_address[0x8];
8103 u8 page_number[0x8];
8104 u8 device_address[0x10];
8105
8106 u8 reserved_at_40[0x10];
8107 u8 size[0x10];
8108
8109 u8 reserved_at_60[0x20];
8110
8111 u8 dword_0[0x20];
8112 u8 dword_1[0x20];
8113 u8 dword_2[0x20];
8114 u8 dword_3[0x20];
8115 u8 dword_4[0x20];
8116 u8 dword_5[0x20];
8117 u8 dword_6[0x20];
8118 u8 dword_7[0x20];
8119 u8 dword_8[0x20];
8120 u8 dword_9[0x20];
8121 u8 dword_10[0x20];
8122 u8 dword_11[0x20];
8123};
8124
7486216b
SM		 8125struct mlx5_ifc_dcbx_param_bits {
8126 u8 dcbx_cee_cap[0x1];
8127 u8 dcbx_ieee_cap[0x1];
8128 u8 dcbx_standby_cap[0x1];
8129 u8 reserved_at_0[0x5];
8130 u8 port_number[0x8];
8131 u8 reserved_at_10[0xa];
8132 u8 max_application_table_size[6];
8133 u8 reserved_at_20[0x15];
8134 u8 version_oper[0x3];
8135 u8 reserved_at_38[5];
8136 u8 version_admin[0x3];
8137 u8 willing_admin[0x1];
8138 u8 reserved_at_41[0x3];
8139 u8 pfc_cap_oper[0x4];
8140 u8 reserved_at_48[0x4];
8141 u8 pfc_cap_admin[0x4];
8142 u8 reserved_at_50[0x4];
8143 u8 num_of_tc_oper[0x4];
8144 u8 reserved_at_58[0x4];
8145 u8 num_of_tc_admin[0x4];
8146 u8 remote_willing[0x1];
8147 u8 reserved_at_61[3];
8148 u8 remote_pfc_cap[4];
8149 u8 reserved_at_68[0x14];
8150 u8 remote_num_of_tc[0x4];
8151 u8 reserved_at_80[0x18];
8152 u8 error[0x8];
8153 u8 reserved_at_a0[0x160];
8154};
84df61eb
AH		 8155
8156struct mlx5_ifc_lagc_bits {
8157 u8 reserved_at_0[0x1d];
8158 u8 lag_state[0x3];
8159
8160 u8 reserved_at_20[0x14];
8161 u8 tx_remap_affinity_2[0x4];
8162 u8 reserved_at_38[0x4];
8163 u8 tx_remap_affinity_1[0x4];
8164};
8165
8166struct mlx5_ifc_create_lag_out_bits {
8167 u8 status[0x8];
8168 u8 reserved_at_8[0x18];
8169
8170 u8 syndrome[0x20];
8171
8172 u8 reserved_at_40[0x40];
8173};
8174
8175struct mlx5_ifc_create_lag_in_bits {
8176 u8 opcode[0x10];
8177 u8 reserved_at_10[0x10];
8178
8179 u8 reserved_at_20[0x10];
8180 u8 op_mod[0x10];
8181
8182 struct mlx5_ifc_lagc_bits ctx;
8183};
8184
8185struct mlx5_ifc_modify_lag_out_bits {
8186 u8 status[0x8];
8187 u8 reserved_at_8[0x18];
8188
8189 u8 syndrome[0x20];
8190
8191 u8 reserved_at_40[0x40];
8192};
8193
8194struct mlx5_ifc_modify_lag_in_bits {
8195 u8 opcode[0x10];
8196 u8 reserved_at_10[0x10];
8197
8198 u8 reserved_at_20[0x10];
8199 u8 op_mod[0x10];
8200
8201 u8 reserved_at_40[0x20];
8202 u8 field_select[0x20];
8203
8204 struct mlx5_ifc_lagc_bits ctx;
8205};
8206
8207struct mlx5_ifc_query_lag_out_bits {
8208 u8 status[0x8];
8209 u8 reserved_at_8[0x18];
8210
8211 u8 syndrome[0x20];
8212
8213 u8 reserved_at_40[0x40];
8214
8215 struct mlx5_ifc_lagc_bits ctx;
8216};
8217
8218struct mlx5_ifc_query_lag_in_bits {
8219 u8 opcode[0x10];
8220 u8 reserved_at_10[0x10];
8221
8222 u8 reserved_at_20[0x10];
8223 u8 op_mod[0x10];
8224
8225 u8 reserved_at_40[0x40];
8226};
8227
8228struct mlx5_ifc_destroy_lag_out_bits {
8229 u8 status[0x8];
8230 u8 reserved_at_8[0x18];
8231
8232 u8 syndrome[0x20];
8233
8234 u8 reserved_at_40[0x40];
8235};
8236
8237struct mlx5_ifc_destroy_lag_in_bits {
8238 u8 opcode[0x10];
8239 u8 reserved_at_10[0x10];
8240
8241 u8 reserved_at_20[0x10];
8242 u8 op_mod[0x10];
8243
8244 u8 reserved_at_40[0x40];
8245};
8246
8247struct mlx5_ifc_create_vport_lag_out_bits {
8248 u8 status[0x8];
8249 u8 reserved_at_8[0x18];
8250
8251 u8 syndrome[0x20];
8252
8253 u8 reserved_at_40[0x40];
8254};
8255
8256struct mlx5_ifc_create_vport_lag_in_bits {
8257 u8 opcode[0x10];
8258 u8 reserved_at_10[0x10];
8259
8260 u8 reserved_at_20[0x10];
8261 u8 op_mod[0x10];
8262
8263 u8 reserved_at_40[0x40];
8264};
8265
8266struct mlx5_ifc_destroy_vport_lag_out_bits {
8267 u8 status[0x8];
8268 u8 reserved_at_8[0x18];
8269
8270 u8 syndrome[0x20];
8271
8272 u8 reserved_at_40[0x40];
8273};
8274
8275struct mlx5_ifc_destroy_vport_lag_in_bits {
8276 u8 opcode[0x10];
8277 u8 reserved_at_10[0x10];
8278
8279 u8 reserved_at_20[0x10];
8280 u8 op_mod[0x10];
8281
8282 u8 reserved_at_40[0x40];
8283};
8284
d29b796a 8285#endif /* MLX5_IFC_H */
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