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d29b796a | 1 | /* |
e281682b | 2 | * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. |
d29b796a EC |
3 | * |
4 | * This software is available to you under a choice of one of two | |
5 | * licenses. You may choose to be licensed under the terms of the GNU | |
6 | * General Public License (GPL) Version 2, available from the file | |
7 | * COPYING in the main directory of this source tree, or the | |
8 | * OpenIB.org BSD license below: | |
9 | * | |
10 | * Redistribution and use in source and binary forms, with or | |
11 | * without modification, are permitted provided that the following | |
12 | * conditions are met: | |
13 | * | |
14 | * - Redistributions of source code must retain the above | |
15 | * copyright notice, this list of conditions and the following | |
16 | * disclaimer. | |
17 | * | |
18 | * - Redistributions in binary form must reproduce the above | |
19 | * copyright notice, this list of conditions and the following | |
20 | * disclaimer in the documentation and/or other materials | |
21 | * provided with the distribution. | |
22 | * | |
23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF | |
25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS | |
27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN | |
28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN | |
29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
30 | * SOFTWARE. | |
e281682b | 31 | */ |
d29b796a EC |
32 | #ifndef MLX5_IFC_H |
33 | #define MLX5_IFC_H | |
34 | ||
e29341fb IT |
35 | #include "mlx5_ifc_fpga.h" |
36 | ||
e281682b SM |
37 | enum { |
38 | MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0, | |
39 | MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1, | |
40 | MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2, | |
41 | MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3, | |
42 | MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13, | |
43 | MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14, | |
44 | MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c, | |
45 | MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d, | |
46 | MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4, | |
47 | MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5, | |
48 | MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7, | |
49 | MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc, | |
50 | MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10, | |
51 | MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11, | |
52 | MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12, | |
53 | MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8, | |
54 | MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9, | |
55 | MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15, | |
56 | MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19, | |
57 | MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a, | |
58 | MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b, | |
59 | MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f, | |
60 | MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa, | |
e29341fb IT |
61 | MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb, |
62 | MLX5_EVENT_TYPE_CODING_FPGA_ERROR = 0x20, | |
e281682b SM |
63 | }; |
64 | ||
65 | enum { | |
66 | MLX5_MODIFY_TIR_BITMASK_LRO = 0x0, | |
67 | MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1, | |
68 | MLX5_MODIFY_TIR_BITMASK_HASH = 0x2, | |
69 | MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3 | |
70 | }; | |
71 | ||
f91e6d89 EBE |
72 | enum { |
73 | MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0, | |
74 | MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3, | |
75 | }; | |
76 | ||
d29b796a EC |
77 | enum { |
78 | MLX5_CMD_OP_QUERY_HCA_CAP = 0x100, | |
79 | MLX5_CMD_OP_QUERY_ADAPTER = 0x101, | |
80 | MLX5_CMD_OP_INIT_HCA = 0x102, | |
81 | MLX5_CMD_OP_TEARDOWN_HCA = 0x103, | |
82 | MLX5_CMD_OP_ENABLE_HCA = 0x104, | |
83 | MLX5_CMD_OP_DISABLE_HCA = 0x105, | |
84 | MLX5_CMD_OP_QUERY_PAGES = 0x107, | |
85 | MLX5_CMD_OP_MANAGE_PAGES = 0x108, | |
86 | MLX5_CMD_OP_SET_HCA_CAP = 0x109, | |
e281682b SM |
87 | MLX5_CMD_OP_QUERY_ISSI = 0x10a, |
88 | MLX5_CMD_OP_SET_ISSI = 0x10b, | |
0dbc6fe0 | 89 | MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d, |
d29b796a EC |
90 | MLX5_CMD_OP_CREATE_MKEY = 0x200, |
91 | MLX5_CMD_OP_QUERY_MKEY = 0x201, | |
92 | MLX5_CMD_OP_DESTROY_MKEY = 0x202, | |
93 | MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203, | |
94 | MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204, | |
95 | MLX5_CMD_OP_CREATE_EQ = 0x301, | |
96 | MLX5_CMD_OP_DESTROY_EQ = 0x302, | |
97 | MLX5_CMD_OP_QUERY_EQ = 0x303, | |
98 | MLX5_CMD_OP_GEN_EQE = 0x304, | |
99 | MLX5_CMD_OP_CREATE_CQ = 0x400, | |
100 | MLX5_CMD_OP_DESTROY_CQ = 0x401, | |
101 | MLX5_CMD_OP_QUERY_CQ = 0x402, | |
102 | MLX5_CMD_OP_MODIFY_CQ = 0x403, | |
103 | MLX5_CMD_OP_CREATE_QP = 0x500, | |
104 | MLX5_CMD_OP_DESTROY_QP = 0x501, | |
105 | MLX5_CMD_OP_RST2INIT_QP = 0x502, | |
106 | MLX5_CMD_OP_INIT2RTR_QP = 0x503, | |
107 | MLX5_CMD_OP_RTR2RTS_QP = 0x504, | |
108 | MLX5_CMD_OP_RTS2RTS_QP = 0x505, | |
109 | MLX5_CMD_OP_SQERR2RTS_QP = 0x506, | |
110 | MLX5_CMD_OP_2ERR_QP = 0x507, | |
111 | MLX5_CMD_OP_2RST_QP = 0x50a, | |
112 | MLX5_CMD_OP_QUERY_QP = 0x50b, | |
e281682b | 113 | MLX5_CMD_OP_SQD_RTS_QP = 0x50c, |
d29b796a EC |
114 | MLX5_CMD_OP_INIT2INIT_QP = 0x50e, |
115 | MLX5_CMD_OP_CREATE_PSV = 0x600, | |
116 | MLX5_CMD_OP_DESTROY_PSV = 0x601, | |
117 | MLX5_CMD_OP_CREATE_SRQ = 0x700, | |
118 | MLX5_CMD_OP_DESTROY_SRQ = 0x701, | |
119 | MLX5_CMD_OP_QUERY_SRQ = 0x702, | |
120 | MLX5_CMD_OP_ARM_RQ = 0x703, | |
e281682b SM |
121 | MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705, |
122 | MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706, | |
123 | MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707, | |
124 | MLX5_CMD_OP_ARM_XRC_SRQ = 0x708, | |
d29b796a EC |
125 | MLX5_CMD_OP_CREATE_DCT = 0x710, |
126 | MLX5_CMD_OP_DESTROY_DCT = 0x711, | |
127 | MLX5_CMD_OP_DRAIN_DCT = 0x712, | |
128 | MLX5_CMD_OP_QUERY_DCT = 0x713, | |
129 | MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714, | |
7486216b SM |
130 | MLX5_CMD_OP_CREATE_XRQ = 0x717, |
131 | MLX5_CMD_OP_DESTROY_XRQ = 0x718, | |
132 | MLX5_CMD_OP_QUERY_XRQ = 0x719, | |
133 | MLX5_CMD_OP_ARM_XRQ = 0x71a, | |
d29b796a EC |
134 | MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750, |
135 | MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751, | |
136 | MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752, | |
137 | MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753, | |
138 | MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754, | |
139 | MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755, | |
e281682b | 140 | MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760, |
d29b796a | 141 | MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761, |
e281682b SM |
142 | MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762, |
143 | MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763, | |
144 | MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764, | |
145 | MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765, | |
d29b796a EC |
146 | MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770, |
147 | MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771, | |
148 | MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772, | |
149 | MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773, | |
7486216b SM |
150 | MLX5_CMD_OP_SET_RATE_LIMIT = 0x780, |
151 | MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781, | |
813f8540 MHY |
152 | MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782, |
153 | MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783, | |
154 | MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784, | |
155 | MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785, | |
156 | MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786, | |
157 | MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787, | |
d29b796a EC |
158 | MLX5_CMD_OP_ALLOC_PD = 0x800, |
159 | MLX5_CMD_OP_DEALLOC_PD = 0x801, | |
160 | MLX5_CMD_OP_ALLOC_UAR = 0x802, | |
161 | MLX5_CMD_OP_DEALLOC_UAR = 0x803, | |
162 | MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804, | |
163 | MLX5_CMD_OP_ACCESS_REG = 0x805, | |
164 | MLX5_CMD_OP_ATTACH_TO_MCG = 0x806, | |
20bb566b | 165 | MLX5_CMD_OP_DETACH_FROM_MCG = 0x807, |
d29b796a EC |
166 | MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a, |
167 | MLX5_CMD_OP_MAD_IFC = 0x50d, | |
168 | MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b, | |
169 | MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c, | |
170 | MLX5_CMD_OP_NOP = 0x80d, | |
171 | MLX5_CMD_OP_ALLOC_XRCD = 0x80e, | |
172 | MLX5_CMD_OP_DEALLOC_XRCD = 0x80f, | |
e281682b SM |
173 | MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816, |
174 | MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817, | |
175 | MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822, | |
176 | MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823, | |
177 | MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824, | |
178 | MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825, | |
179 | MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826, | |
180 | MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827, | |
181 | MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828, | |
182 | MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829, | |
183 | MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a, | |
184 | MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b, | |
928cfe87 TT |
185 | MLX5_CMD_OP_SET_WOL_ROL = 0x830, |
186 | MLX5_CMD_OP_QUERY_WOL_ROL = 0x831, | |
84df61eb AH |
187 | MLX5_CMD_OP_CREATE_LAG = 0x840, |
188 | MLX5_CMD_OP_MODIFY_LAG = 0x841, | |
189 | MLX5_CMD_OP_QUERY_LAG = 0x842, | |
190 | MLX5_CMD_OP_DESTROY_LAG = 0x843, | |
191 | MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844, | |
192 | MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845, | |
d29b796a EC |
193 | MLX5_CMD_OP_CREATE_TIR = 0x900, |
194 | MLX5_CMD_OP_MODIFY_TIR = 0x901, | |
195 | MLX5_CMD_OP_DESTROY_TIR = 0x902, | |
196 | MLX5_CMD_OP_QUERY_TIR = 0x903, | |
d29b796a EC |
197 | MLX5_CMD_OP_CREATE_SQ = 0x904, |
198 | MLX5_CMD_OP_MODIFY_SQ = 0x905, | |
199 | MLX5_CMD_OP_DESTROY_SQ = 0x906, | |
200 | MLX5_CMD_OP_QUERY_SQ = 0x907, | |
201 | MLX5_CMD_OP_CREATE_RQ = 0x908, | |
202 | MLX5_CMD_OP_MODIFY_RQ = 0x909, | |
203 | MLX5_CMD_OP_DESTROY_RQ = 0x90a, | |
204 | MLX5_CMD_OP_QUERY_RQ = 0x90b, | |
205 | MLX5_CMD_OP_CREATE_RMP = 0x90c, | |
206 | MLX5_CMD_OP_MODIFY_RMP = 0x90d, | |
207 | MLX5_CMD_OP_DESTROY_RMP = 0x90e, | |
208 | MLX5_CMD_OP_QUERY_RMP = 0x90f, | |
e281682b SM |
209 | MLX5_CMD_OP_CREATE_TIS = 0x912, |
210 | MLX5_CMD_OP_MODIFY_TIS = 0x913, | |
211 | MLX5_CMD_OP_DESTROY_TIS = 0x914, | |
212 | MLX5_CMD_OP_QUERY_TIS = 0x915, | |
213 | MLX5_CMD_OP_CREATE_RQT = 0x916, | |
214 | MLX5_CMD_OP_MODIFY_RQT = 0x917, | |
215 | MLX5_CMD_OP_DESTROY_RQT = 0x918, | |
216 | MLX5_CMD_OP_QUERY_RQT = 0x919, | |
2cc43b49 | 217 | MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f, |
e281682b SM |
218 | MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930, |
219 | MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931, | |
220 | MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932, | |
221 | MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933, | |
222 | MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934, | |
223 | MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935, | |
224 | MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936, | |
225 | MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937, | |
34a40e68 | 226 | MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938, |
9dc0b289 AV |
227 | MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939, |
228 | MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a, | |
229 | MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b, | |
86d56a1a | 230 | MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c, |
7adbde20 HHZ |
231 | MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d, |
232 | MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e, | |
2a69cb9f OG |
233 | MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940, |
234 | MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941, | |
86d56a1a | 235 | MLX5_CMD_OP_MAX |
e281682b SM |
236 | }; |
237 | ||
238 | struct mlx5_ifc_flow_table_fields_supported_bits { | |
239 | u8 outer_dmac[0x1]; | |
240 | u8 outer_smac[0x1]; | |
241 | u8 outer_ether_type[0x1]; | |
19cc7524 | 242 | u8 outer_ip_version[0x1]; |
e281682b SM |
243 | u8 outer_first_prio[0x1]; |
244 | u8 outer_first_cfi[0x1]; | |
245 | u8 outer_first_vid[0x1]; | |
a8ade55f | 246 | u8 outer_ipv4_ttl[0x1]; |
e281682b SM |
247 | u8 outer_second_prio[0x1]; |
248 | u8 outer_second_cfi[0x1]; | |
249 | u8 outer_second_vid[0x1]; | |
b4ff3a36 | 250 | u8 reserved_at_b[0x1]; |
e281682b SM |
251 | u8 outer_sip[0x1]; |
252 | u8 outer_dip[0x1]; | |
253 | u8 outer_frag[0x1]; | |
254 | u8 outer_ip_protocol[0x1]; | |
255 | u8 outer_ip_ecn[0x1]; | |
256 | u8 outer_ip_dscp[0x1]; | |
257 | u8 outer_udp_sport[0x1]; | |
258 | u8 outer_udp_dport[0x1]; | |
259 | u8 outer_tcp_sport[0x1]; | |
260 | u8 outer_tcp_dport[0x1]; | |
261 | u8 outer_tcp_flags[0x1]; | |
262 | u8 outer_gre_protocol[0x1]; | |
263 | u8 outer_gre_key[0x1]; | |
264 | u8 outer_vxlan_vni[0x1]; | |
b4ff3a36 | 265 | u8 reserved_at_1a[0x5]; |
e281682b SM |
266 | u8 source_eswitch_port[0x1]; |
267 | ||
268 | u8 inner_dmac[0x1]; | |
269 | u8 inner_smac[0x1]; | |
270 | u8 inner_ether_type[0x1]; | |
19cc7524 | 271 | u8 inner_ip_version[0x1]; |
e281682b SM |
272 | u8 inner_first_prio[0x1]; |
273 | u8 inner_first_cfi[0x1]; | |
274 | u8 inner_first_vid[0x1]; | |
b4ff3a36 | 275 | u8 reserved_at_27[0x1]; |
e281682b SM |
276 | u8 inner_second_prio[0x1]; |
277 | u8 inner_second_cfi[0x1]; | |
278 | u8 inner_second_vid[0x1]; | |
b4ff3a36 | 279 | u8 reserved_at_2b[0x1]; |
e281682b SM |
280 | u8 inner_sip[0x1]; |
281 | u8 inner_dip[0x1]; | |
282 | u8 inner_frag[0x1]; | |
283 | u8 inner_ip_protocol[0x1]; | |
284 | u8 inner_ip_ecn[0x1]; | |
285 | u8 inner_ip_dscp[0x1]; | |
286 | u8 inner_udp_sport[0x1]; | |
287 | u8 inner_udp_dport[0x1]; | |
288 | u8 inner_tcp_sport[0x1]; | |
289 | u8 inner_tcp_dport[0x1]; | |
290 | u8 inner_tcp_flags[0x1]; | |
b4ff3a36 | 291 | u8 reserved_at_37[0x9]; |
e281682b | 292 | |
b4ff3a36 | 293 | u8 reserved_at_40[0x40]; |
e281682b SM |
294 | }; |
295 | ||
296 | struct mlx5_ifc_flow_table_prop_layout_bits { | |
297 | u8 ft_support[0x1]; | |
9dc0b289 AV |
298 | u8 reserved_at_1[0x1]; |
299 | u8 flow_counter[0x1]; | |
26a81453 | 300 | u8 flow_modify_en[0x1]; |
2cc43b49 | 301 | u8 modify_root[0x1]; |
34a40e68 MG |
302 | u8 identified_miss_table_mode[0x1]; |
303 | u8 flow_table_modify[0x1]; | |
7adbde20 HHZ |
304 | u8 encap[0x1]; |
305 | u8 decap[0x1]; | |
306 | u8 reserved_at_9[0x17]; | |
e281682b | 307 | |
b4ff3a36 | 308 | u8 reserved_at_20[0x2]; |
e281682b | 309 | u8 log_max_ft_size[0x6]; |
2a69cb9f OG |
310 | u8 log_max_modify_header_context[0x8]; |
311 | u8 max_modify_header_actions[0x8]; | |
e281682b SM |
312 | u8 max_ft_level[0x8]; |
313 | ||
b4ff3a36 | 314 | u8 reserved_at_40[0x20]; |
e281682b | 315 | |
b4ff3a36 | 316 | u8 reserved_at_60[0x18]; |
e281682b SM |
317 | u8 log_max_ft_num[0x8]; |
318 | ||
b4ff3a36 | 319 | u8 reserved_at_80[0x18]; |
e281682b SM |
320 | u8 log_max_destination[0x8]; |
321 | ||
b4ff3a36 | 322 | u8 reserved_at_a0[0x18]; |
e281682b SM |
323 | u8 log_max_flow[0x8]; |
324 | ||
b4ff3a36 | 325 | u8 reserved_at_c0[0x40]; |
e281682b SM |
326 | |
327 | struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support; | |
328 | ||
329 | struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support; | |
330 | }; | |
331 | ||
332 | struct mlx5_ifc_odp_per_transport_service_cap_bits { | |
333 | u8 send[0x1]; | |
334 | u8 receive[0x1]; | |
335 | u8 write[0x1]; | |
336 | u8 read[0x1]; | |
17d2f88f | 337 | u8 atomic[0x1]; |
e281682b | 338 | u8 srq_receive[0x1]; |
b4ff3a36 | 339 | u8 reserved_at_6[0x1a]; |
e281682b SM |
340 | }; |
341 | ||
b4d1f032 | 342 | struct mlx5_ifc_ipv4_layout_bits { |
b4ff3a36 | 343 | u8 reserved_at_0[0x60]; |
b4d1f032 MG |
344 | |
345 | u8 ipv4[0x20]; | |
346 | }; | |
347 | ||
348 | struct mlx5_ifc_ipv6_layout_bits { | |
349 | u8 ipv6[16][0x8]; | |
350 | }; | |
351 | ||
352 | union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits { | |
353 | struct mlx5_ifc_ipv6_layout_bits ipv6_layout; | |
354 | struct mlx5_ifc_ipv4_layout_bits ipv4_layout; | |
b4ff3a36 | 355 | u8 reserved_at_0[0x80]; |
b4d1f032 MG |
356 | }; |
357 | ||
e281682b SM |
358 | struct mlx5_ifc_fte_match_set_lyr_2_4_bits { |
359 | u8 smac_47_16[0x20]; | |
360 | ||
361 | u8 smac_15_0[0x10]; | |
362 | u8 ethertype[0x10]; | |
363 | ||
364 | u8 dmac_47_16[0x20]; | |
365 | ||
366 | u8 dmac_15_0[0x10]; | |
367 | u8 first_prio[0x3]; | |
368 | u8 first_cfi[0x1]; | |
369 | u8 first_vid[0xc]; | |
370 | ||
371 | u8 ip_protocol[0x8]; | |
372 | u8 ip_dscp[0x6]; | |
373 | u8 ip_ecn[0x2]; | |
10543365 MHY |
374 | u8 cvlan_tag[0x1]; |
375 | u8 svlan_tag[0x1]; | |
e281682b | 376 | u8 frag[0x1]; |
19cc7524 | 377 | u8 ip_version[0x4]; |
e281682b SM |
378 | u8 tcp_flags[0x9]; |
379 | ||
380 | u8 tcp_sport[0x10]; | |
381 | u8 tcp_dport[0x10]; | |
382 | ||
a8ade55f OG |
383 | u8 reserved_at_c0[0x18]; |
384 | u8 ttl_hoplimit[0x8]; | |
e281682b SM |
385 | |
386 | u8 udp_sport[0x10]; | |
387 | u8 udp_dport[0x10]; | |
388 | ||
b4d1f032 | 389 | union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6; |
e281682b | 390 | |
b4d1f032 | 391 | union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6; |
e281682b SM |
392 | }; |
393 | ||
394 | struct mlx5_ifc_fte_match_set_misc_bits { | |
7486216b SM |
395 | u8 reserved_at_0[0x8]; |
396 | u8 source_sqn[0x18]; | |
e281682b | 397 | |
b4ff3a36 | 398 | u8 reserved_at_20[0x10]; |
e281682b SM |
399 | u8 source_port[0x10]; |
400 | ||
401 | u8 outer_second_prio[0x3]; | |
402 | u8 outer_second_cfi[0x1]; | |
403 | u8 outer_second_vid[0xc]; | |
404 | u8 inner_second_prio[0x3]; | |
405 | u8 inner_second_cfi[0x1]; | |
406 | u8 inner_second_vid[0xc]; | |
407 | ||
10543365 MHY |
408 | u8 outer_second_cvlan_tag[0x1]; |
409 | u8 inner_second_cvlan_tag[0x1]; | |
410 | u8 outer_second_svlan_tag[0x1]; | |
411 | u8 inner_second_svlan_tag[0x1]; | |
412 | u8 reserved_at_64[0xc]; | |
e281682b SM |
413 | u8 gre_protocol[0x10]; |
414 | ||
415 | u8 gre_key_h[0x18]; | |
416 | u8 gre_key_l[0x8]; | |
417 | ||
418 | u8 vxlan_vni[0x18]; | |
b4ff3a36 | 419 | u8 reserved_at_b8[0x8]; |
e281682b | 420 | |
b4ff3a36 | 421 | u8 reserved_at_c0[0x20]; |
e281682b | 422 | |
b4ff3a36 | 423 | u8 reserved_at_e0[0xc]; |
e281682b SM |
424 | u8 outer_ipv6_flow_label[0x14]; |
425 | ||
b4ff3a36 | 426 | u8 reserved_at_100[0xc]; |
e281682b SM |
427 | u8 inner_ipv6_flow_label[0x14]; |
428 | ||
b4ff3a36 | 429 | u8 reserved_at_120[0xe0]; |
e281682b SM |
430 | }; |
431 | ||
432 | struct mlx5_ifc_cmd_pas_bits { | |
433 | u8 pa_h[0x20]; | |
434 | ||
435 | u8 pa_l[0x14]; | |
b4ff3a36 | 436 | u8 reserved_at_34[0xc]; |
e281682b SM |
437 | }; |
438 | ||
439 | struct mlx5_ifc_uint64_bits { | |
440 | u8 hi[0x20]; | |
441 | ||
442 | u8 lo[0x20]; | |
443 | }; | |
444 | ||
445 | enum { | |
446 | MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0, | |
447 | MLX5_ADS_STAT_RATE_2_5GBPS = 0x7, | |
448 | MLX5_ADS_STAT_RATE_10GBPS = 0x8, | |
449 | MLX5_ADS_STAT_RATE_30GBPS = 0x9, | |
450 | MLX5_ADS_STAT_RATE_5GBPS = 0xa, | |
451 | MLX5_ADS_STAT_RATE_20GBPS = 0xb, | |
452 | MLX5_ADS_STAT_RATE_40GBPS = 0xc, | |
453 | MLX5_ADS_STAT_RATE_60GBPS = 0xd, | |
454 | MLX5_ADS_STAT_RATE_80GBPS = 0xe, | |
455 | MLX5_ADS_STAT_RATE_120GBPS = 0xf, | |
456 | }; | |
457 | ||
458 | struct mlx5_ifc_ads_bits { | |
459 | u8 fl[0x1]; | |
460 | u8 free_ar[0x1]; | |
b4ff3a36 | 461 | u8 reserved_at_2[0xe]; |
e281682b SM |
462 | u8 pkey_index[0x10]; |
463 | ||
b4ff3a36 | 464 | u8 reserved_at_20[0x8]; |
e281682b SM |
465 | u8 grh[0x1]; |
466 | u8 mlid[0x7]; | |
467 | u8 rlid[0x10]; | |
468 | ||
469 | u8 ack_timeout[0x5]; | |
b4ff3a36 | 470 | u8 reserved_at_45[0x3]; |
e281682b | 471 | u8 src_addr_index[0x8]; |
b4ff3a36 | 472 | u8 reserved_at_50[0x4]; |
e281682b SM |
473 | u8 stat_rate[0x4]; |
474 | u8 hop_limit[0x8]; | |
475 | ||
b4ff3a36 | 476 | u8 reserved_at_60[0x4]; |
e281682b SM |
477 | u8 tclass[0x8]; |
478 | u8 flow_label[0x14]; | |
479 | ||
480 | u8 rgid_rip[16][0x8]; | |
481 | ||
b4ff3a36 | 482 | u8 reserved_at_100[0x4]; |
e281682b SM |
483 | u8 f_dscp[0x1]; |
484 | u8 f_ecn[0x1]; | |
b4ff3a36 | 485 | u8 reserved_at_106[0x1]; |
e281682b SM |
486 | u8 f_eth_prio[0x1]; |
487 | u8 ecn[0x2]; | |
488 | u8 dscp[0x6]; | |
489 | u8 udp_sport[0x10]; | |
490 | ||
491 | u8 dei_cfi[0x1]; | |
492 | u8 eth_prio[0x3]; | |
493 | u8 sl[0x4]; | |
494 | u8 port[0x8]; | |
495 | u8 rmac_47_32[0x10]; | |
496 | ||
497 | u8 rmac_31_0[0x20]; | |
498 | }; | |
499 | ||
500 | struct mlx5_ifc_flow_table_nic_cap_bits { | |
b3638e1a | 501 | u8 nic_rx_multi_path_tirs[0x1]; |
cea824d4 MG |
502 | u8 nic_rx_multi_path_tirs_fts[0x1]; |
503 | u8 allow_sniffer_and_nic_rx_shared_tir[0x1]; | |
504 | u8 reserved_at_3[0x1fd]; | |
e281682b SM |
505 | |
506 | struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive; | |
507 | ||
b4ff3a36 | 508 | u8 reserved_at_400[0x200]; |
e281682b SM |
509 | |
510 | struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer; | |
511 | ||
512 | struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit; | |
513 | ||
b4ff3a36 | 514 | u8 reserved_at_a00[0x200]; |
e281682b SM |
515 | |
516 | struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer; | |
517 | ||
b4ff3a36 | 518 | u8 reserved_at_e00[0x7200]; |
e281682b SM |
519 | }; |
520 | ||
495716b1 | 521 | struct mlx5_ifc_flow_table_eswitch_cap_bits { |
b4ff3a36 | 522 | u8 reserved_at_0[0x200]; |
495716b1 SM |
523 | |
524 | struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb; | |
525 | ||
526 | struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress; | |
527 | ||
528 | struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress; | |
529 | ||
b4ff3a36 | 530 | u8 reserved_at_800[0x7800]; |
495716b1 SM |
531 | }; |
532 | ||
d6666753 SM |
533 | struct mlx5_ifc_e_switch_cap_bits { |
534 | u8 vport_svlan_strip[0x1]; | |
535 | u8 vport_cvlan_strip[0x1]; | |
536 | u8 vport_svlan_insert[0x1]; | |
537 | u8 vport_cvlan_insert_if_not_exist[0x1]; | |
538 | u8 vport_cvlan_insert_overwrite[0x1]; | |
23898c76 NO |
539 | u8 reserved_at_5[0x19]; |
540 | u8 nic_vport_node_guid_modify[0x1]; | |
541 | u8 nic_vport_port_guid_modify[0x1]; | |
d6666753 | 542 | |
7adbde20 HHZ |
543 | u8 vxlan_encap_decap[0x1]; |
544 | u8 nvgre_encap_decap[0x1]; | |
545 | u8 reserved_at_22[0x9]; | |
546 | u8 log_max_encap_headers[0x5]; | |
547 | u8 reserved_2b[0x6]; | |
548 | u8 max_encap_header_size[0xa]; | |
549 | ||
550 | u8 reserved_40[0x7c0]; | |
551 | ||
d6666753 SM |
552 | }; |
553 | ||
7486216b SM |
554 | struct mlx5_ifc_qos_cap_bits { |
555 | u8 packet_pacing[0x1]; | |
813f8540 | 556 | u8 esw_scheduling[0x1]; |
c9497c98 MHY |
557 | u8 esw_bw_share[0x1]; |
558 | u8 esw_rate_limit[0x1]; | |
559 | u8 reserved_at_4[0x1c]; | |
813f8540 MHY |
560 | |
561 | u8 reserved_at_20[0x20]; | |
562 | ||
7486216b | 563 | u8 packet_pacing_max_rate[0x20]; |
813f8540 | 564 | |
7486216b | 565 | u8 packet_pacing_min_rate[0x20]; |
813f8540 MHY |
566 | |
567 | u8 reserved_at_80[0x10]; | |
7486216b | 568 | u8 packet_pacing_rate_table_size[0x10]; |
813f8540 MHY |
569 | |
570 | u8 esw_element_type[0x10]; | |
571 | u8 esw_tsar_type[0x10]; | |
572 | ||
573 | u8 reserved_at_c0[0x10]; | |
574 | u8 max_qos_para_vport[0x10]; | |
575 | ||
576 | u8 max_tsar_bw_share[0x20]; | |
577 | ||
578 | u8 reserved_at_100[0x700]; | |
7486216b SM |
579 | }; |
580 | ||
e281682b SM |
581 | struct mlx5_ifc_per_protocol_networking_offload_caps_bits { |
582 | u8 csum_cap[0x1]; | |
583 | u8 vlan_cap[0x1]; | |
584 | u8 lro_cap[0x1]; | |
585 | u8 lro_psh_flag[0x1]; | |
586 | u8 lro_time_stamp[0x1]; | |
2b31f7ae SM |
587 | u8 reserved_at_5[0x2]; |
588 | u8 wqe_vlan_insert[0x1]; | |
66189961 | 589 | u8 self_lb_en_modifiable[0x1]; |
b4ff3a36 | 590 | u8 reserved_at_9[0x2]; |
e281682b | 591 | u8 max_lso_cap[0x5]; |
c226dc22 | 592 | u8 multi_pkt_send_wqe[0x2]; |
cff92d7c | 593 | u8 wqe_inline_mode[0x2]; |
e281682b | 594 | u8 rss_ind_tbl_cap[0x4]; |
7d5e1423 SM |
595 | u8 reg_umr_sq[0x1]; |
596 | u8 scatter_fcs[0x1]; | |
597 | u8 reserved_at_1a[0x1]; | |
e281682b | 598 | u8 tunnel_lso_const_out_ip_id[0x1]; |
b4ff3a36 | 599 | u8 reserved_at_1c[0x2]; |
e281682b SM |
600 | u8 tunnel_statless_gre[0x1]; |
601 | u8 tunnel_stateless_vxlan[0x1]; | |
602 | ||
b4ff3a36 | 603 | u8 reserved_at_20[0x20]; |
e281682b | 604 | |
b4ff3a36 | 605 | u8 reserved_at_40[0x10]; |
e281682b SM |
606 | u8 lro_min_mss_size[0x10]; |
607 | ||
b4ff3a36 | 608 | u8 reserved_at_60[0x120]; |
e281682b SM |
609 | |
610 | u8 lro_timer_supported_periods[4][0x20]; | |
611 | ||
b4ff3a36 | 612 | u8 reserved_at_200[0x600]; |
e281682b SM |
613 | }; |
614 | ||
615 | struct mlx5_ifc_roce_cap_bits { | |
616 | u8 roce_apm[0x1]; | |
b4ff3a36 | 617 | u8 reserved_at_1[0x1f]; |
e281682b | 618 | |
b4ff3a36 | 619 | u8 reserved_at_20[0x60]; |
e281682b | 620 | |
b4ff3a36 | 621 | u8 reserved_at_80[0xc]; |
e281682b | 622 | u8 l3_type[0x4]; |
b4ff3a36 | 623 | u8 reserved_at_90[0x8]; |
e281682b SM |
624 | u8 roce_version[0x8]; |
625 | ||
b4ff3a36 | 626 | u8 reserved_at_a0[0x10]; |
e281682b SM |
627 | u8 r_roce_dest_udp_port[0x10]; |
628 | ||
629 | u8 r_roce_max_src_udp_port[0x10]; | |
630 | u8 r_roce_min_src_udp_port[0x10]; | |
631 | ||
b4ff3a36 | 632 | u8 reserved_at_e0[0x10]; |
e281682b SM |
633 | u8 roce_address_table_size[0x10]; |
634 | ||
b4ff3a36 | 635 | u8 reserved_at_100[0x700]; |
e281682b SM |
636 | }; |
637 | ||
638 | enum { | |
639 | MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0, | |
640 | MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2, | |
641 | MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4, | |
642 | MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8, | |
643 | MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10, | |
644 | MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20, | |
645 | MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40, | |
646 | MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80, | |
647 | MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100, | |
648 | }; | |
649 | ||
650 | enum { | |
651 | MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1, | |
652 | MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2, | |
653 | MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4, | |
654 | MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8, | |
655 | MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10, | |
656 | MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20, | |
657 | MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40, | |
658 | MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80, | |
659 | MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100, | |
660 | }; | |
661 | ||
662 | struct mlx5_ifc_atomic_caps_bits { | |
b4ff3a36 | 663 | u8 reserved_at_0[0x40]; |
e281682b | 664 | |
bd10838a | 665 | u8 atomic_req_8B_endianness_mode[0x2]; |
b4ff3a36 | 666 | u8 reserved_at_42[0x4]; |
bd10838a | 667 | u8 supported_atomic_req_8B_endianness_mode_1[0x1]; |
e281682b | 668 | |
b4ff3a36 | 669 | u8 reserved_at_47[0x19]; |
e281682b | 670 | |
b4ff3a36 | 671 | u8 reserved_at_60[0x20]; |
e281682b | 672 | |
b4ff3a36 | 673 | u8 reserved_at_80[0x10]; |
f91e6d89 | 674 | u8 atomic_operations[0x10]; |
e281682b | 675 | |
b4ff3a36 | 676 | u8 reserved_at_a0[0x10]; |
f91e6d89 EBE |
677 | u8 atomic_size_qp[0x10]; |
678 | ||
b4ff3a36 | 679 | u8 reserved_at_c0[0x10]; |
e281682b SM |
680 | u8 atomic_size_dc[0x10]; |
681 | ||
b4ff3a36 | 682 | u8 reserved_at_e0[0x720]; |
e281682b SM |
683 | }; |
684 | ||
685 | struct mlx5_ifc_odp_cap_bits { | |
b4ff3a36 | 686 | u8 reserved_at_0[0x40]; |
e281682b SM |
687 | |
688 | u8 sig[0x1]; | |
b4ff3a36 | 689 | u8 reserved_at_41[0x1f]; |
e281682b | 690 | |
b4ff3a36 | 691 | u8 reserved_at_60[0x20]; |
e281682b SM |
692 | |
693 | struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; | |
694 | ||
695 | struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; | |
696 | ||
697 | struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; | |
698 | ||
b4ff3a36 | 699 | u8 reserved_at_e0[0x720]; |
e281682b SM |
700 | }; |
701 | ||
3f0393a5 SG |
702 | struct mlx5_ifc_calc_op { |
703 | u8 reserved_at_0[0x10]; | |
704 | u8 reserved_at_10[0x9]; | |
705 | u8 op_swap_endianness[0x1]; | |
706 | u8 op_min[0x1]; | |
707 | u8 op_xor[0x1]; | |
708 | u8 op_or[0x1]; | |
709 | u8 op_and[0x1]; | |
710 | u8 op_max[0x1]; | |
711 | u8 op_add[0x1]; | |
712 | }; | |
713 | ||
714 | struct mlx5_ifc_vector_calc_cap_bits { | |
715 | u8 calc_matrix[0x1]; | |
716 | u8 reserved_at_1[0x1f]; | |
717 | u8 reserved_at_20[0x8]; | |
718 | u8 max_vec_count[0x8]; | |
719 | u8 reserved_at_30[0xd]; | |
720 | u8 max_chunk_size[0x3]; | |
721 | struct mlx5_ifc_calc_op calc0; | |
722 | struct mlx5_ifc_calc_op calc1; | |
723 | struct mlx5_ifc_calc_op calc2; | |
724 | struct mlx5_ifc_calc_op calc3; | |
725 | ||
726 | u8 reserved_at_e0[0x720]; | |
727 | }; | |
728 | ||
e281682b SM |
729 | enum { |
730 | MLX5_WQ_TYPE_LINKED_LIST = 0x0, | |
731 | MLX5_WQ_TYPE_CYCLIC = 0x1, | |
7d5e1423 | 732 | MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2, |
e281682b SM |
733 | }; |
734 | ||
735 | enum { | |
736 | MLX5_WQ_END_PAD_MODE_NONE = 0x0, | |
737 | MLX5_WQ_END_PAD_MODE_ALIGN = 0x1, | |
738 | }; | |
739 | ||
740 | enum { | |
741 | MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0, | |
742 | MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1, | |
743 | MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2, | |
744 | MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3, | |
745 | MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4, | |
746 | }; | |
747 | ||
748 | enum { | |
749 | MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0, | |
750 | MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1, | |
751 | MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2, | |
752 | MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3, | |
753 | MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4, | |
754 | MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5, | |
755 | }; | |
756 | ||
757 | enum { | |
758 | MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0, | |
759 | MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1, | |
760 | }; | |
761 | ||
762 | enum { | |
763 | MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0, | |
764 | MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1, | |
765 | MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3, | |
766 | }; | |
767 | ||
768 | enum { | |
769 | MLX5_CAP_PORT_TYPE_IB = 0x0, | |
770 | MLX5_CAP_PORT_TYPE_ETH = 0x1, | |
d29b796a EC |
771 | }; |
772 | ||
1410a90a MG |
773 | enum { |
774 | MLX5_CAP_UMR_FENCE_STRONG = 0x0, | |
775 | MLX5_CAP_UMR_FENCE_SMALL = 0x1, | |
776 | MLX5_CAP_UMR_FENCE_NONE = 0x2, | |
777 | }; | |
778 | ||
b775516b | 779 | struct mlx5_ifc_cmd_hca_cap_bits { |
b4ff3a36 | 780 | u8 reserved_at_0[0x80]; |
b775516b EC |
781 | |
782 | u8 log_max_srq_sz[0x8]; | |
783 | u8 log_max_qp_sz[0x8]; | |
b4ff3a36 | 784 | u8 reserved_at_90[0xb]; |
b775516b EC |
785 | u8 log_max_qp[0x5]; |
786 | ||
b4ff3a36 | 787 | u8 reserved_at_a0[0xb]; |
e281682b | 788 | u8 log_max_srq[0x5]; |
b4ff3a36 | 789 | u8 reserved_at_b0[0x10]; |
b775516b | 790 | |
b4ff3a36 | 791 | u8 reserved_at_c0[0x8]; |
b775516b | 792 | u8 log_max_cq_sz[0x8]; |
b4ff3a36 | 793 | u8 reserved_at_d0[0xb]; |
b775516b EC |
794 | u8 log_max_cq[0x5]; |
795 | ||
796 | u8 log_max_eq_sz[0x8]; | |
b4ff3a36 | 797 | u8 reserved_at_e8[0x2]; |
b775516b | 798 | u8 log_max_mkey[0x6]; |
b4ff3a36 | 799 | u8 reserved_at_f0[0xc]; |
b775516b EC |
800 | u8 log_max_eq[0x4]; |
801 | ||
802 | u8 max_indirection[0x8]; | |
bcda1aca | 803 | u8 fixed_buffer_size[0x1]; |
b775516b | 804 | u8 log_max_mrw_sz[0x7]; |
8812c24d MD |
805 | u8 force_teardown[0x1]; |
806 | u8 reserved_at_111[0x1]; | |
b775516b | 807 | u8 log_max_bsf_list_size[0x6]; |
bcda1aca AK |
808 | u8 umr_extended_translation_offset[0x1]; |
809 | u8 null_mkey[0x1]; | |
b775516b EC |
810 | u8 log_max_klm_list_size[0x6]; |
811 | ||
b4ff3a36 | 812 | u8 reserved_at_120[0xa]; |
b775516b | 813 | u8 log_max_ra_req_dc[0x6]; |
b4ff3a36 | 814 | u8 reserved_at_130[0xa]; |
b775516b EC |
815 | u8 log_max_ra_res_dc[0x6]; |
816 | ||
b4ff3a36 | 817 | u8 reserved_at_140[0xa]; |
b775516b | 818 | u8 log_max_ra_req_qp[0x6]; |
b4ff3a36 | 819 | u8 reserved_at_150[0xa]; |
b775516b EC |
820 | u8 log_max_ra_res_qp[0x6]; |
821 | ||
f32f5bd2 | 822 | u8 end_pad[0x1]; |
b775516b EC |
823 | u8 cc_query_allowed[0x1]; |
824 | u8 cc_modify_allowed[0x1]; | |
f32f5bd2 DJ |
825 | u8 start_pad[0x1]; |
826 | u8 cache_line_128byte[0x1]; | |
137ffd15 | 827 | u8 reserved_at_165[0xb]; |
e281682b | 828 | u8 gid_table_size[0x10]; |
b775516b | 829 | |
e281682b SM |
830 | u8 out_of_seq_cnt[0x1]; |
831 | u8 vport_counters[0x1]; | |
7486216b | 832 | u8 retransmission_q_counters[0x1]; |
83b502a1 AV |
833 | u8 reserved_at_183[0x1]; |
834 | u8 modify_rq_counter_set_id[0x1]; | |
835 | u8 reserved_at_185[0x1]; | |
b775516b EC |
836 | u8 max_qp_cnt[0xa]; |
837 | u8 pkey_table_size[0x10]; | |
838 | ||
e281682b SM |
839 | u8 vport_group_manager[0x1]; |
840 | u8 vhca_group_manager[0x1]; | |
841 | u8 ib_virt[0x1]; | |
842 | u8 eth_virt[0x1]; | |
b4ff3a36 | 843 | u8 reserved_at_1a4[0x1]; |
e281682b SM |
844 | u8 ets[0x1]; |
845 | u8 nic_flow_table[0x1]; | |
54f0a411 | 846 | u8 eswitch_flow_table[0x1]; |
e1c9c62b | 847 | u8 early_vf_enable[0x1]; |
cfdcbcea GP |
848 | u8 mcam_reg[0x1]; |
849 | u8 pcam_reg[0x1]; | |
b775516b | 850 | u8 local_ca_ack_delay[0x5]; |
4ce3bf2f | 851 | u8 port_module_event[0x1]; |
7b13558f | 852 | u8 reserved_at_1b1[0x1]; |
7d5e1423 | 853 | u8 ports_check[0x1]; |
7b13558f | 854 | u8 reserved_at_1b3[0x1]; |
7d5e1423 SM |
855 | u8 disable_link_up[0x1]; |
856 | u8 beacon_led[0x1]; | |
e281682b | 857 | u8 port_type[0x2]; |
b775516b EC |
858 | u8 num_ports[0x8]; |
859 | ||
f9a1ef72 EE |
860 | u8 reserved_at_1c0[0x1]; |
861 | u8 pps[0x1]; | |
862 | u8 pps_modify[0x1]; | |
b775516b | 863 | u8 log_max_msg[0x5]; |
e1c9c62b | 864 | u8 reserved_at_1c8[0x4]; |
4f3961ee | 865 | u8 max_tc[0x4]; |
7486216b SM |
866 | u8 reserved_at_1d0[0x1]; |
867 | u8 dcbx[0x1]; | |
e29341fb IT |
868 | u8 reserved_at_1d2[0x3]; |
869 | u8 fpga[0x1]; | |
928cfe87 TT |
870 | u8 rol_s[0x1]; |
871 | u8 rol_g[0x1]; | |
e1c9c62b | 872 | u8 reserved_at_1d8[0x1]; |
928cfe87 TT |
873 | u8 wol_s[0x1]; |
874 | u8 wol_g[0x1]; | |
875 | u8 wol_a[0x1]; | |
876 | u8 wol_b[0x1]; | |
877 | u8 wol_m[0x1]; | |
878 | u8 wol_u[0x1]; | |
879 | u8 wol_p[0x1]; | |
b775516b EC |
880 | |
881 | u8 stat_rate_support[0x10]; | |
e1c9c62b | 882 | u8 reserved_at_1f0[0xc]; |
e281682b | 883 | u8 cqe_version[0x4]; |
b775516b | 884 | |
e281682b | 885 | u8 compact_address_vector[0x1]; |
7d5e1423 | 886 | u8 striding_rq[0x1]; |
500a3d0d ES |
887 | u8 reserved_at_202[0x1]; |
888 | u8 ipoib_enhanced_offloads[0x1]; | |
1015c2e8 | 889 | u8 ipoib_basic_offloads[0x1]; |
1410a90a MG |
890 | u8 reserved_at_205[0x5]; |
891 | u8 umr_fence[0x2]; | |
892 | u8 reserved_at_20c[0x3]; | |
e281682b | 893 | u8 drain_sigerr[0x1]; |
b775516b EC |
894 | u8 cmdif_checksum[0x2]; |
895 | u8 sigerr_cqe[0x1]; | |
e1c9c62b | 896 | u8 reserved_at_213[0x1]; |
b775516b EC |
897 | u8 wq_signature[0x1]; |
898 | u8 sctr_data_cqe[0x1]; | |
e1c9c62b | 899 | u8 reserved_at_216[0x1]; |
b775516b EC |
900 | u8 sho[0x1]; |
901 | u8 tph[0x1]; | |
902 | u8 rf[0x1]; | |
e281682b | 903 | u8 dct[0x1]; |
7486216b | 904 | u8 qos[0x1]; |
e281682b | 905 | u8 eth_net_offloads[0x1]; |
b775516b EC |
906 | u8 roce[0x1]; |
907 | u8 atomic[0x1]; | |
e1c9c62b | 908 | u8 reserved_at_21f[0x1]; |
b775516b EC |
909 | |
910 | u8 cq_oi[0x1]; | |
911 | u8 cq_resize[0x1]; | |
912 | u8 cq_moderation[0x1]; | |
e1c9c62b | 913 | u8 reserved_at_223[0x3]; |
e281682b | 914 | u8 cq_eq_remap[0x1]; |
b775516b EC |
915 | u8 pg[0x1]; |
916 | u8 block_lb_mc[0x1]; | |
e1c9c62b | 917 | u8 reserved_at_229[0x1]; |
e281682b | 918 | u8 scqe_break_moderation[0x1]; |
7d5e1423 | 919 | u8 cq_period_start_from_cqe[0x1]; |
b775516b | 920 | u8 cd[0x1]; |
e1c9c62b | 921 | u8 reserved_at_22d[0x1]; |
b775516b | 922 | u8 apm[0x1]; |
3f0393a5 | 923 | u8 vector_calc[0x1]; |
7d5e1423 | 924 | u8 umr_ptr_rlky[0x1]; |
d2370e0a | 925 | u8 imaicl[0x1]; |
e1c9c62b | 926 | u8 reserved_at_232[0x4]; |
b775516b EC |
927 | u8 qkv[0x1]; |
928 | u8 pkv[0x1]; | |
b11a4f9c HE |
929 | u8 set_deth_sqpn[0x1]; |
930 | u8 reserved_at_239[0x3]; | |
b775516b EC |
931 | u8 xrc[0x1]; |
932 | u8 ud[0x1]; | |
933 | u8 uc[0x1]; | |
934 | u8 rc[0x1]; | |
935 | ||
a6d51b68 EC |
936 | u8 uar_4k[0x1]; |
937 | u8 reserved_at_241[0x9]; | |
b775516b | 938 | u8 uar_sz[0x6]; |
e1c9c62b | 939 | u8 reserved_at_250[0x8]; |
b775516b EC |
940 | u8 log_pg_sz[0x8]; |
941 | ||
942 | u8 bf[0x1]; | |
0dbc6fe0 | 943 | u8 driver_version[0x1]; |
e281682b | 944 | u8 pad_tx_eth_packet[0x1]; |
e1c9c62b | 945 | u8 reserved_at_263[0x8]; |
b775516b | 946 | u8 log_bf_reg_size[0x5]; |
84df61eb AH |
947 | |
948 | u8 reserved_at_270[0xb]; | |
949 | u8 lag_master[0x1]; | |
950 | u8 num_lag_ports[0x4]; | |
b775516b | 951 | |
e1c9c62b | 952 | u8 reserved_at_280[0x10]; |
b775516b EC |
953 | u8 max_wqe_sz_sq[0x10]; |
954 | ||
e1c9c62b | 955 | u8 reserved_at_2a0[0x10]; |
b775516b EC |
956 | u8 max_wqe_sz_rq[0x10]; |
957 | ||
e1c9c62b | 958 | u8 reserved_at_2c0[0x10]; |
b775516b EC |
959 | u8 max_wqe_sz_sq_dc[0x10]; |
960 | ||
e1c9c62b | 961 | u8 reserved_at_2e0[0x7]; |
b775516b EC |
962 | u8 max_qp_mcg[0x19]; |
963 | ||
e1c9c62b | 964 | u8 reserved_at_300[0x18]; |
b775516b EC |
965 | u8 log_max_mcg[0x8]; |
966 | ||
e1c9c62b | 967 | u8 reserved_at_320[0x3]; |
e281682b | 968 | u8 log_max_transport_domain[0x5]; |
e1c9c62b | 969 | u8 reserved_at_328[0x3]; |
b775516b | 970 | u8 log_max_pd[0x5]; |
e1c9c62b | 971 | u8 reserved_at_330[0xb]; |
b775516b EC |
972 | u8 log_max_xrcd[0x5]; |
973 | ||
a351a1b0 AV |
974 | u8 reserved_at_340[0x8]; |
975 | u8 log_max_flow_counter_bulk[0x8]; | |
976 | u8 max_flow_counter[0x10]; | |
977 | ||
b775516b | 978 | |
e1c9c62b | 979 | u8 reserved_at_360[0x3]; |
b775516b | 980 | u8 log_max_rq[0x5]; |
e1c9c62b | 981 | u8 reserved_at_368[0x3]; |
b775516b | 982 | u8 log_max_sq[0x5]; |
e1c9c62b | 983 | u8 reserved_at_370[0x3]; |
b775516b | 984 | u8 log_max_tir[0x5]; |
e1c9c62b | 985 | u8 reserved_at_378[0x3]; |
b775516b EC |
986 | u8 log_max_tis[0x5]; |
987 | ||
e281682b | 988 | u8 basic_cyclic_rcv_wqe[0x1]; |
e1c9c62b | 989 | u8 reserved_at_381[0x2]; |
e281682b | 990 | u8 log_max_rmp[0x5]; |
e1c9c62b | 991 | u8 reserved_at_388[0x3]; |
e281682b | 992 | u8 log_max_rqt[0x5]; |
e1c9c62b | 993 | u8 reserved_at_390[0x3]; |
e281682b | 994 | u8 log_max_rqt_size[0x5]; |
e1c9c62b | 995 | u8 reserved_at_398[0x3]; |
b775516b EC |
996 | u8 log_max_tis_per_sq[0x5]; |
997 | ||
e1c9c62b | 998 | u8 reserved_at_3a0[0x3]; |
e281682b | 999 | u8 log_max_stride_sz_rq[0x5]; |
e1c9c62b | 1000 | u8 reserved_at_3a8[0x3]; |
e281682b | 1001 | u8 log_min_stride_sz_rq[0x5]; |
e1c9c62b | 1002 | u8 reserved_at_3b0[0x3]; |
e281682b | 1003 | u8 log_max_stride_sz_sq[0x5]; |
e1c9c62b | 1004 | u8 reserved_at_3b8[0x3]; |
e281682b SM |
1005 | u8 log_min_stride_sz_sq[0x5]; |
1006 | ||
e1c9c62b | 1007 | u8 reserved_at_3c0[0x1b]; |
e281682b SM |
1008 | u8 log_max_wq_sz[0x5]; |
1009 | ||
54f0a411 | 1010 | u8 nic_vport_change_event[0x1]; |
e1c9c62b | 1011 | u8 reserved_at_3e1[0xa]; |
54f0a411 | 1012 | u8 log_max_vlan_list[0x5]; |
e1c9c62b | 1013 | u8 reserved_at_3f0[0x3]; |
54f0a411 | 1014 | u8 log_max_current_mc_list[0x5]; |
e1c9c62b | 1015 | u8 reserved_at_3f8[0x3]; |
54f0a411 SM |
1016 | u8 log_max_current_uc_list[0x5]; |
1017 | ||
e1c9c62b | 1018 | u8 reserved_at_400[0x80]; |
54f0a411 | 1019 | |
e1c9c62b | 1020 | u8 reserved_at_480[0x3]; |
e281682b | 1021 | u8 log_max_l2_table[0x5]; |
e1c9c62b | 1022 | u8 reserved_at_488[0x8]; |
b775516b EC |
1023 | u8 log_uar_page_sz[0x10]; |
1024 | ||
e1c9c62b | 1025 | u8 reserved_at_4a0[0x20]; |
048ccca8 | 1026 | u8 device_frequency_mhz[0x20]; |
b0844444 | 1027 | u8 device_frequency_khz[0x20]; |
e1c9c62b | 1028 | |
a6d51b68 EC |
1029 | u8 reserved_at_500[0x20]; |
1030 | u8 num_of_uars_per_page[0x20]; | |
1031 | u8 reserved_at_540[0x40]; | |
e1c9c62b TT |
1032 | |
1033 | u8 reserved_at_580[0x3f]; | |
7d5e1423 | 1034 | u8 cqe_compression[0x1]; |
b775516b | 1035 | |
7d5e1423 SM |
1036 | u8 cqe_compression_timeout[0x10]; |
1037 | u8 cqe_compression_max_num[0x10]; | |
b775516b | 1038 | |
7486216b SM |
1039 | u8 reserved_at_5e0[0x10]; |
1040 | u8 tag_matching[0x1]; | |
1041 | u8 rndv_offload_rc[0x1]; | |
1042 | u8 rndv_offload_dc[0x1]; | |
1043 | u8 log_tag_matching_list_sz[0x5]; | |
7b13558f | 1044 | u8 reserved_at_5f8[0x3]; |
7486216b SM |
1045 | u8 log_max_xrq[0x5]; |
1046 | ||
7b13558f | 1047 | u8 reserved_at_600[0x200]; |
b775516b EC |
1048 | }; |
1049 | ||
81848731 SM |
1050 | enum mlx5_flow_destination_type { |
1051 | MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0, | |
1052 | MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1, | |
1053 | MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2, | |
bd5251db AV |
1054 | |
1055 | MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100, | |
e281682b | 1056 | }; |
b775516b | 1057 | |
e281682b SM |
1058 | struct mlx5_ifc_dest_format_struct_bits { |
1059 | u8 destination_type[0x8]; | |
1060 | u8 destination_id[0x18]; | |
b775516b | 1061 | |
b4ff3a36 | 1062 | u8 reserved_at_20[0x20]; |
e281682b SM |
1063 | }; |
1064 | ||
9dc0b289 | 1065 | struct mlx5_ifc_flow_counter_list_bits { |
a351a1b0 AV |
1066 | u8 clear[0x1]; |
1067 | u8 num_of_counters[0xf]; | |
9dc0b289 AV |
1068 | u8 flow_counter_id[0x10]; |
1069 | ||
1070 | u8 reserved_at_20[0x20]; | |
1071 | }; | |
1072 | ||
1073 | union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits { | |
1074 | struct mlx5_ifc_dest_format_struct_bits dest_format_struct; | |
1075 | struct mlx5_ifc_flow_counter_list_bits flow_counter_list; | |
1076 | u8 reserved_at_0[0x40]; | |
1077 | }; | |
1078 | ||
e281682b SM |
1079 | struct mlx5_ifc_fte_match_param_bits { |
1080 | struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers; | |
1081 | ||
1082 | struct mlx5_ifc_fte_match_set_misc_bits misc_parameters; | |
1083 | ||
1084 | struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers; | |
b775516b | 1085 | |
b4ff3a36 | 1086 | u8 reserved_at_600[0xa00]; |
b775516b EC |
1087 | }; |
1088 | ||
e281682b SM |
1089 | enum { |
1090 | MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0, | |
1091 | MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1, | |
1092 | MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2, | |
1093 | MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3, | |
1094 | MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4, | |
1095 | }; | |
b775516b | 1096 | |
e281682b SM |
1097 | struct mlx5_ifc_rx_hash_field_select_bits { |
1098 | u8 l3_prot_type[0x1]; | |
1099 | u8 l4_prot_type[0x1]; | |
1100 | u8 selected_fields[0x1e]; | |
1101 | }; | |
b775516b | 1102 | |
e281682b SM |
1103 | enum { |
1104 | MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0, | |
1105 | MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1, | |
b775516b EC |
1106 | }; |
1107 | ||
e281682b SM |
1108 | enum { |
1109 | MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0, | |
1110 | MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1, | |
1111 | }; | |
1112 | ||
1113 | struct mlx5_ifc_wq_bits { | |
1114 | u8 wq_type[0x4]; | |
1115 | u8 wq_signature[0x1]; | |
1116 | u8 end_padding_mode[0x2]; | |
1117 | u8 cd_slave[0x1]; | |
b4ff3a36 | 1118 | u8 reserved_at_8[0x18]; |
b775516b | 1119 | |
e281682b SM |
1120 | u8 hds_skip_first_sge[0x1]; |
1121 | u8 log2_hds_buf_size[0x3]; | |
b4ff3a36 | 1122 | u8 reserved_at_24[0x7]; |
e281682b SM |
1123 | u8 page_offset[0x5]; |
1124 | u8 lwm[0x10]; | |
b775516b | 1125 | |
b4ff3a36 | 1126 | u8 reserved_at_40[0x8]; |
e281682b SM |
1127 | u8 pd[0x18]; |
1128 | ||
b4ff3a36 | 1129 | u8 reserved_at_60[0x8]; |
e281682b SM |
1130 | u8 uar_page[0x18]; |
1131 | ||
1132 | u8 dbr_addr[0x40]; | |
1133 | ||
1134 | u8 hw_counter[0x20]; | |
1135 | ||
1136 | u8 sw_counter[0x20]; | |
1137 | ||
b4ff3a36 | 1138 | u8 reserved_at_100[0xc]; |
e281682b | 1139 | u8 log_wq_stride[0x4]; |
b4ff3a36 | 1140 | u8 reserved_at_110[0x3]; |
e281682b | 1141 | u8 log_wq_pg_sz[0x5]; |
b4ff3a36 | 1142 | u8 reserved_at_118[0x3]; |
e281682b SM |
1143 | u8 log_wq_sz[0x5]; |
1144 | ||
7d5e1423 SM |
1145 | u8 reserved_at_120[0x15]; |
1146 | u8 log_wqe_num_of_strides[0x3]; | |
1147 | u8 two_byte_shift_en[0x1]; | |
1148 | u8 reserved_at_139[0x4]; | |
1149 | u8 log_wqe_stride_size[0x3]; | |
1150 | ||
1151 | u8 reserved_at_140[0x4c0]; | |
b775516b | 1152 | |
e281682b | 1153 | struct mlx5_ifc_cmd_pas_bits pas[0]; |
b775516b EC |
1154 | }; |
1155 | ||
e281682b | 1156 | struct mlx5_ifc_rq_num_bits { |
b4ff3a36 | 1157 | u8 reserved_at_0[0x8]; |
e281682b SM |
1158 | u8 rq_num[0x18]; |
1159 | }; | |
b775516b | 1160 | |
e281682b | 1161 | struct mlx5_ifc_mac_address_layout_bits { |
b4ff3a36 | 1162 | u8 reserved_at_0[0x10]; |
e281682b | 1163 | u8 mac_addr_47_32[0x10]; |
b775516b | 1164 | |
e281682b SM |
1165 | u8 mac_addr_31_0[0x20]; |
1166 | }; | |
1167 | ||
c0046cf7 | 1168 | struct mlx5_ifc_vlan_layout_bits { |
b4ff3a36 | 1169 | u8 reserved_at_0[0x14]; |
c0046cf7 SM |
1170 | u8 vlan[0x0c]; |
1171 | ||
b4ff3a36 | 1172 | u8 reserved_at_20[0x20]; |
c0046cf7 SM |
1173 | }; |
1174 | ||
e281682b | 1175 | struct mlx5_ifc_cong_control_r_roce_ecn_np_bits { |
b4ff3a36 | 1176 | u8 reserved_at_0[0xa0]; |
e281682b SM |
1177 | |
1178 | u8 min_time_between_cnps[0x20]; | |
1179 | ||
b4ff3a36 | 1180 | u8 reserved_at_c0[0x12]; |
e281682b | 1181 | u8 cnp_dscp[0x6]; |
b4ff3a36 | 1182 | u8 reserved_at_d8[0x5]; |
e281682b SM |
1183 | u8 cnp_802p_prio[0x3]; |
1184 | ||
b4ff3a36 | 1185 | u8 reserved_at_e0[0x720]; |
e281682b SM |
1186 | }; |
1187 | ||
1188 | struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits { | |
b4ff3a36 | 1189 | u8 reserved_at_0[0x60]; |
e281682b | 1190 | |
b4ff3a36 | 1191 | u8 reserved_at_60[0x4]; |
e281682b | 1192 | u8 clamp_tgt_rate[0x1]; |
b4ff3a36 | 1193 | u8 reserved_at_65[0x3]; |
e281682b | 1194 | u8 clamp_tgt_rate_after_time_inc[0x1]; |
b4ff3a36 | 1195 | u8 reserved_at_69[0x17]; |
e281682b | 1196 | |
b4ff3a36 | 1197 | u8 reserved_at_80[0x20]; |
e281682b SM |
1198 | |
1199 | u8 rpg_time_reset[0x20]; | |
1200 | ||
1201 | u8 rpg_byte_reset[0x20]; | |
1202 | ||
1203 | u8 rpg_threshold[0x20]; | |
1204 | ||
1205 | u8 rpg_max_rate[0x20]; | |
1206 | ||
1207 | u8 rpg_ai_rate[0x20]; | |
1208 | ||
1209 | u8 rpg_hai_rate[0x20]; | |
1210 | ||
1211 | u8 rpg_gd[0x20]; | |
1212 | ||
1213 | u8 rpg_min_dec_fac[0x20]; | |
1214 | ||
1215 | u8 rpg_min_rate[0x20]; | |
1216 | ||
b4ff3a36 | 1217 | u8 reserved_at_1c0[0xe0]; |
e281682b SM |
1218 | |
1219 | u8 rate_to_set_on_first_cnp[0x20]; | |
1220 | ||
1221 | u8 dce_tcp_g[0x20]; | |
1222 | ||
1223 | u8 dce_tcp_rtt[0x20]; | |
1224 | ||
1225 | u8 rate_reduce_monitor_period[0x20]; | |
1226 | ||
b4ff3a36 | 1227 | u8 reserved_at_320[0x20]; |
e281682b SM |
1228 | |
1229 | u8 initial_alpha_value[0x20]; | |
1230 | ||
b4ff3a36 | 1231 | u8 reserved_at_360[0x4a0]; |
e281682b SM |
1232 | }; |
1233 | ||
1234 | struct mlx5_ifc_cong_control_802_1qau_rp_bits { | |
b4ff3a36 | 1235 | u8 reserved_at_0[0x80]; |
e281682b SM |
1236 | |
1237 | u8 rppp_max_rps[0x20]; | |
1238 | ||
1239 | u8 rpg_time_reset[0x20]; | |
1240 | ||
1241 | u8 rpg_byte_reset[0x20]; | |
1242 | ||
1243 | u8 rpg_threshold[0x20]; | |
1244 | ||
1245 | u8 rpg_max_rate[0x20]; | |
1246 | ||
1247 | u8 rpg_ai_rate[0x20]; | |
1248 | ||
1249 | u8 rpg_hai_rate[0x20]; | |
1250 | ||
1251 | u8 rpg_gd[0x20]; | |
1252 | ||
1253 | u8 rpg_min_dec_fac[0x20]; | |
1254 | ||
1255 | u8 rpg_min_rate[0x20]; | |
1256 | ||
b4ff3a36 | 1257 | u8 reserved_at_1c0[0x640]; |
e281682b SM |
1258 | }; |
1259 | ||
1260 | enum { | |
1261 | MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1, | |
1262 | MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2, | |
1263 | MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4, | |
1264 | }; | |
1265 | ||
1266 | struct mlx5_ifc_resize_field_select_bits { | |
1267 | u8 resize_field_select[0x20]; | |
1268 | }; | |
1269 | ||
1270 | enum { | |
1271 | MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1, | |
1272 | MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2, | |
1273 | MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4, | |
1274 | MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8, | |
1275 | }; | |
1276 | ||
1277 | struct mlx5_ifc_modify_field_select_bits { | |
1278 | u8 modify_field_select[0x20]; | |
1279 | }; | |
1280 | ||
1281 | struct mlx5_ifc_field_select_r_roce_np_bits { | |
1282 | u8 field_select_r_roce_np[0x20]; | |
1283 | }; | |
1284 | ||
1285 | struct mlx5_ifc_field_select_r_roce_rp_bits { | |
1286 | u8 field_select_r_roce_rp[0x20]; | |
1287 | }; | |
1288 | ||
1289 | enum { | |
1290 | MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4, | |
1291 | MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8, | |
1292 | MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10, | |
1293 | MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20, | |
1294 | MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40, | |
1295 | MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80, | |
1296 | MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100, | |
1297 | MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200, | |
1298 | MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400, | |
1299 | MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800, | |
1300 | }; | |
1301 | ||
1302 | struct mlx5_ifc_field_select_802_1qau_rp_bits { | |
1303 | u8 field_select_8021qaurp[0x20]; | |
1304 | }; | |
1305 | ||
1306 | struct mlx5_ifc_phys_layer_cntrs_bits { | |
1307 | u8 time_since_last_clear_high[0x20]; | |
1308 | ||
1309 | u8 time_since_last_clear_low[0x20]; | |
1310 | ||
1311 | u8 symbol_errors_high[0x20]; | |
1312 | ||
1313 | u8 symbol_errors_low[0x20]; | |
1314 | ||
1315 | u8 sync_headers_errors_high[0x20]; | |
1316 | ||
1317 | u8 sync_headers_errors_low[0x20]; | |
1318 | ||
1319 | u8 edpl_bip_errors_lane0_high[0x20]; | |
1320 | ||
1321 | u8 edpl_bip_errors_lane0_low[0x20]; | |
1322 | ||
1323 | u8 edpl_bip_errors_lane1_high[0x20]; | |
1324 | ||
1325 | u8 edpl_bip_errors_lane1_low[0x20]; | |
1326 | ||
1327 | u8 edpl_bip_errors_lane2_high[0x20]; | |
1328 | ||
1329 | u8 edpl_bip_errors_lane2_low[0x20]; | |
1330 | ||
1331 | u8 edpl_bip_errors_lane3_high[0x20]; | |
1332 | ||
1333 | u8 edpl_bip_errors_lane3_low[0x20]; | |
1334 | ||
1335 | u8 fc_fec_corrected_blocks_lane0_high[0x20]; | |
1336 | ||
1337 | u8 fc_fec_corrected_blocks_lane0_low[0x20]; | |
1338 | ||
1339 | u8 fc_fec_corrected_blocks_lane1_high[0x20]; | |
1340 | ||
1341 | u8 fc_fec_corrected_blocks_lane1_low[0x20]; | |
1342 | ||
1343 | u8 fc_fec_corrected_blocks_lane2_high[0x20]; | |
1344 | ||
1345 | u8 fc_fec_corrected_blocks_lane2_low[0x20]; | |
1346 | ||
1347 | u8 fc_fec_corrected_blocks_lane3_high[0x20]; | |
1348 | ||
1349 | u8 fc_fec_corrected_blocks_lane3_low[0x20]; | |
1350 | ||
1351 | u8 fc_fec_uncorrectable_blocks_lane0_high[0x20]; | |
1352 | ||
1353 | u8 fc_fec_uncorrectable_blocks_lane0_low[0x20]; | |
1354 | ||
1355 | u8 fc_fec_uncorrectable_blocks_lane1_high[0x20]; | |
1356 | ||
1357 | u8 fc_fec_uncorrectable_blocks_lane1_low[0x20]; | |
1358 | ||
1359 | u8 fc_fec_uncorrectable_blocks_lane2_high[0x20]; | |
1360 | ||
1361 | u8 fc_fec_uncorrectable_blocks_lane2_low[0x20]; | |
1362 | ||
1363 | u8 fc_fec_uncorrectable_blocks_lane3_high[0x20]; | |
1364 | ||
1365 | u8 fc_fec_uncorrectable_blocks_lane3_low[0x20]; | |
1366 | ||
1367 | u8 rs_fec_corrected_blocks_high[0x20]; | |
1368 | ||
1369 | u8 rs_fec_corrected_blocks_low[0x20]; | |
1370 | ||
1371 | u8 rs_fec_uncorrectable_blocks_high[0x20]; | |
1372 | ||
1373 | u8 rs_fec_uncorrectable_blocks_low[0x20]; | |
1374 | ||
1375 | u8 rs_fec_no_errors_blocks_high[0x20]; | |
1376 | ||
1377 | u8 rs_fec_no_errors_blocks_low[0x20]; | |
1378 | ||
1379 | u8 rs_fec_single_error_blocks_high[0x20]; | |
1380 | ||
1381 | u8 rs_fec_single_error_blocks_low[0x20]; | |
1382 | ||
1383 | u8 rs_fec_corrected_symbols_total_high[0x20]; | |
1384 | ||
1385 | u8 rs_fec_corrected_symbols_total_low[0x20]; | |
1386 | ||
1387 | u8 rs_fec_corrected_symbols_lane0_high[0x20]; | |
1388 | ||
1389 | u8 rs_fec_corrected_symbols_lane0_low[0x20]; | |
1390 | ||
1391 | u8 rs_fec_corrected_symbols_lane1_high[0x20]; | |
1392 | ||
1393 | u8 rs_fec_corrected_symbols_lane1_low[0x20]; | |
1394 | ||
1395 | u8 rs_fec_corrected_symbols_lane2_high[0x20]; | |
1396 | ||
1397 | u8 rs_fec_corrected_symbols_lane2_low[0x20]; | |
1398 | ||
1399 | u8 rs_fec_corrected_symbols_lane3_high[0x20]; | |
1400 | ||
1401 | u8 rs_fec_corrected_symbols_lane3_low[0x20]; | |
1402 | ||
1403 | u8 link_down_events[0x20]; | |
1404 | ||
1405 | u8 successful_recovery_events[0x20]; | |
1406 | ||
b4ff3a36 | 1407 | u8 reserved_at_640[0x180]; |
e281682b SM |
1408 | }; |
1409 | ||
d8dc0508 GP |
1410 | struct mlx5_ifc_phys_layer_statistical_cntrs_bits { |
1411 | u8 time_since_last_clear_high[0x20]; | |
1412 | ||
1413 | u8 time_since_last_clear_low[0x20]; | |
1414 | ||
1415 | u8 phy_received_bits_high[0x20]; | |
1416 | ||
1417 | u8 phy_received_bits_low[0x20]; | |
1418 | ||
1419 | u8 phy_symbol_errors_high[0x20]; | |
1420 | ||
1421 | u8 phy_symbol_errors_low[0x20]; | |
1422 | ||
1423 | u8 phy_corrected_bits_high[0x20]; | |
1424 | ||
1425 | u8 phy_corrected_bits_low[0x20]; | |
1426 | ||
1427 | u8 phy_corrected_bits_lane0_high[0x20]; | |
1428 | ||
1429 | u8 phy_corrected_bits_lane0_low[0x20]; | |
1430 | ||
1431 | u8 phy_corrected_bits_lane1_high[0x20]; | |
1432 | ||
1433 | u8 phy_corrected_bits_lane1_low[0x20]; | |
1434 | ||
1435 | u8 phy_corrected_bits_lane2_high[0x20]; | |
1436 | ||
1437 | u8 phy_corrected_bits_lane2_low[0x20]; | |
1438 | ||
1439 | u8 phy_corrected_bits_lane3_high[0x20]; | |
1440 | ||
1441 | u8 phy_corrected_bits_lane3_low[0x20]; | |
1442 | ||
1443 | u8 reserved_at_200[0x5c0]; | |
1444 | }; | |
1445 | ||
1c64bf6f MY |
1446 | struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits { |
1447 | u8 symbol_error_counter[0x10]; | |
1448 | ||
1449 | u8 link_error_recovery_counter[0x8]; | |
1450 | ||
1451 | u8 link_downed_counter[0x8]; | |
1452 | ||
1453 | u8 port_rcv_errors[0x10]; | |
1454 | ||
1455 | u8 port_rcv_remote_physical_errors[0x10]; | |
1456 | ||
1457 | u8 port_rcv_switch_relay_errors[0x10]; | |
1458 | ||
1459 | u8 port_xmit_discards[0x10]; | |
1460 | ||
1461 | u8 port_xmit_constraint_errors[0x8]; | |
1462 | ||
1463 | u8 port_rcv_constraint_errors[0x8]; | |
1464 | ||
1465 | u8 reserved_at_70[0x8]; | |
1466 | ||
1467 | u8 link_overrun_errors[0x8]; | |
1468 | ||
1469 | u8 reserved_at_80[0x10]; | |
1470 | ||
1471 | u8 vl_15_dropped[0x10]; | |
1472 | ||
133bea04 TW |
1473 | u8 reserved_at_a0[0x80]; |
1474 | ||
1475 | u8 port_xmit_wait[0x20]; | |
1c64bf6f MY |
1476 | }; |
1477 | ||
e281682b SM |
1478 | struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits { |
1479 | u8 transmit_queue_high[0x20]; | |
1480 | ||
1481 | u8 transmit_queue_low[0x20]; | |
1482 | ||
b4ff3a36 | 1483 | u8 reserved_at_40[0x780]; |
e281682b SM |
1484 | }; |
1485 | ||
1486 | struct mlx5_ifc_eth_per_prio_grp_data_layout_bits { | |
1487 | u8 rx_octets_high[0x20]; | |
1488 | ||
1489 | u8 rx_octets_low[0x20]; | |
1490 | ||
b4ff3a36 | 1491 | u8 reserved_at_40[0xc0]; |
e281682b SM |
1492 | |
1493 | u8 rx_frames_high[0x20]; | |
1494 | ||
1495 | u8 rx_frames_low[0x20]; | |
1496 | ||
1497 | u8 tx_octets_high[0x20]; | |
1498 | ||
1499 | u8 tx_octets_low[0x20]; | |
1500 | ||
b4ff3a36 | 1501 | u8 reserved_at_180[0xc0]; |
e281682b SM |
1502 | |
1503 | u8 tx_frames_high[0x20]; | |
1504 | ||
1505 | u8 tx_frames_low[0x20]; | |
1506 | ||
1507 | u8 rx_pause_high[0x20]; | |
1508 | ||
1509 | u8 rx_pause_low[0x20]; | |
1510 | ||
1511 | u8 rx_pause_duration_high[0x20]; | |
1512 | ||
1513 | u8 rx_pause_duration_low[0x20]; | |
1514 | ||
1515 | u8 tx_pause_high[0x20]; | |
1516 | ||
1517 | u8 tx_pause_low[0x20]; | |
1518 | ||
1519 | u8 tx_pause_duration_high[0x20]; | |
1520 | ||
1521 | u8 tx_pause_duration_low[0x20]; | |
1522 | ||
1523 | u8 rx_pause_transition_high[0x20]; | |
1524 | ||
1525 | u8 rx_pause_transition_low[0x20]; | |
1526 | ||
b4ff3a36 | 1527 | u8 reserved_at_3c0[0x400]; |
e281682b SM |
1528 | }; |
1529 | ||
1530 | struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits { | |
1531 | u8 port_transmit_wait_high[0x20]; | |
1532 | ||
1533 | u8 port_transmit_wait_low[0x20]; | |
1534 | ||
b4ff3a36 | 1535 | u8 reserved_at_40[0x780]; |
e281682b SM |
1536 | }; |
1537 | ||
1538 | struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits { | |
1539 | u8 dot3stats_alignment_errors_high[0x20]; | |
1540 | ||
1541 | u8 dot3stats_alignment_errors_low[0x20]; | |
1542 | ||
1543 | u8 dot3stats_fcs_errors_high[0x20]; | |
1544 | ||
1545 | u8 dot3stats_fcs_errors_low[0x20]; | |
1546 | ||
1547 | u8 dot3stats_single_collision_frames_high[0x20]; | |
1548 | ||
1549 | u8 dot3stats_single_collision_frames_low[0x20]; | |
1550 | ||
1551 | u8 dot3stats_multiple_collision_frames_high[0x20]; | |
1552 | ||
1553 | u8 dot3stats_multiple_collision_frames_low[0x20]; | |
1554 | ||
1555 | u8 dot3stats_sqe_test_errors_high[0x20]; | |
1556 | ||
1557 | u8 dot3stats_sqe_test_errors_low[0x20]; | |
1558 | ||
1559 | u8 dot3stats_deferred_transmissions_high[0x20]; | |
1560 | ||
1561 | u8 dot3stats_deferred_transmissions_low[0x20]; | |
1562 | ||
1563 | u8 dot3stats_late_collisions_high[0x20]; | |
1564 | ||
1565 | u8 dot3stats_late_collisions_low[0x20]; | |
1566 | ||
1567 | u8 dot3stats_excessive_collisions_high[0x20]; | |
1568 | ||
1569 | u8 dot3stats_excessive_collisions_low[0x20]; | |
1570 | ||
1571 | u8 dot3stats_internal_mac_transmit_errors_high[0x20]; | |
1572 | ||
1573 | u8 dot3stats_internal_mac_transmit_errors_low[0x20]; | |
1574 | ||
1575 | u8 dot3stats_carrier_sense_errors_high[0x20]; | |
1576 | ||
1577 | u8 dot3stats_carrier_sense_errors_low[0x20]; | |
1578 | ||
1579 | u8 dot3stats_frame_too_longs_high[0x20]; | |
1580 | ||
1581 | u8 dot3stats_frame_too_longs_low[0x20]; | |
1582 | ||
1583 | u8 dot3stats_internal_mac_receive_errors_high[0x20]; | |
1584 | ||
1585 | u8 dot3stats_internal_mac_receive_errors_low[0x20]; | |
1586 | ||
1587 | u8 dot3stats_symbol_errors_high[0x20]; | |
1588 | ||
1589 | u8 dot3stats_symbol_errors_low[0x20]; | |
1590 | ||
1591 | u8 dot3control_in_unknown_opcodes_high[0x20]; | |
1592 | ||
1593 | u8 dot3control_in_unknown_opcodes_low[0x20]; | |
1594 | ||
1595 | u8 dot3in_pause_frames_high[0x20]; | |
1596 | ||
1597 | u8 dot3in_pause_frames_low[0x20]; | |
1598 | ||
1599 | u8 dot3out_pause_frames_high[0x20]; | |
1600 | ||
1601 | u8 dot3out_pause_frames_low[0x20]; | |
1602 | ||
b4ff3a36 | 1603 | u8 reserved_at_400[0x3c0]; |
e281682b SM |
1604 | }; |
1605 | ||
1606 | struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits { | |
1607 | u8 ether_stats_drop_events_high[0x20]; | |
1608 | ||
1609 | u8 ether_stats_drop_events_low[0x20]; | |
1610 | ||
1611 | u8 ether_stats_octets_high[0x20]; | |
1612 | ||
1613 | u8 ether_stats_octets_low[0x20]; | |
1614 | ||
1615 | u8 ether_stats_pkts_high[0x20]; | |
1616 | ||
1617 | u8 ether_stats_pkts_low[0x20]; | |
1618 | ||
1619 | u8 ether_stats_broadcast_pkts_high[0x20]; | |
1620 | ||
1621 | u8 ether_stats_broadcast_pkts_low[0x20]; | |
1622 | ||
1623 | u8 ether_stats_multicast_pkts_high[0x20]; | |
1624 | ||
1625 | u8 ether_stats_multicast_pkts_low[0x20]; | |
1626 | ||
1627 | u8 ether_stats_crc_align_errors_high[0x20]; | |
1628 | ||
1629 | u8 ether_stats_crc_align_errors_low[0x20]; | |
1630 | ||
1631 | u8 ether_stats_undersize_pkts_high[0x20]; | |
1632 | ||
1633 | u8 ether_stats_undersize_pkts_low[0x20]; | |
1634 | ||
1635 | u8 ether_stats_oversize_pkts_high[0x20]; | |
1636 | ||
1637 | u8 ether_stats_oversize_pkts_low[0x20]; | |
1638 | ||
1639 | u8 ether_stats_fragments_high[0x20]; | |
1640 | ||
1641 | u8 ether_stats_fragments_low[0x20]; | |
1642 | ||
1643 | u8 ether_stats_jabbers_high[0x20]; | |
1644 | ||
1645 | u8 ether_stats_jabbers_low[0x20]; | |
1646 | ||
1647 | u8 ether_stats_collisions_high[0x20]; | |
1648 | ||
1649 | u8 ether_stats_collisions_low[0x20]; | |
1650 | ||
1651 | u8 ether_stats_pkts64octets_high[0x20]; | |
1652 | ||
1653 | u8 ether_stats_pkts64octets_low[0x20]; | |
1654 | ||
1655 | u8 ether_stats_pkts65to127octets_high[0x20]; | |
1656 | ||
1657 | u8 ether_stats_pkts65to127octets_low[0x20]; | |
1658 | ||
1659 | u8 ether_stats_pkts128to255octets_high[0x20]; | |
1660 | ||
1661 | u8 ether_stats_pkts128to255octets_low[0x20]; | |
1662 | ||
1663 | u8 ether_stats_pkts256to511octets_high[0x20]; | |
1664 | ||
1665 | u8 ether_stats_pkts256to511octets_low[0x20]; | |
1666 | ||
1667 | u8 ether_stats_pkts512to1023octets_high[0x20]; | |
1668 | ||
1669 | u8 ether_stats_pkts512to1023octets_low[0x20]; | |
1670 | ||
1671 | u8 ether_stats_pkts1024to1518octets_high[0x20]; | |
1672 | ||
1673 | u8 ether_stats_pkts1024to1518octets_low[0x20]; | |
1674 | ||
1675 | u8 ether_stats_pkts1519to2047octets_high[0x20]; | |
1676 | ||
1677 | u8 ether_stats_pkts1519to2047octets_low[0x20]; | |
1678 | ||
1679 | u8 ether_stats_pkts2048to4095octets_high[0x20]; | |
1680 | ||
1681 | u8 ether_stats_pkts2048to4095octets_low[0x20]; | |
1682 | ||
1683 | u8 ether_stats_pkts4096to8191octets_high[0x20]; | |
1684 | ||
1685 | u8 ether_stats_pkts4096to8191octets_low[0x20]; | |
1686 | ||
1687 | u8 ether_stats_pkts8192to10239octets_high[0x20]; | |
1688 | ||
1689 | u8 ether_stats_pkts8192to10239octets_low[0x20]; | |
1690 | ||
b4ff3a36 | 1691 | u8 reserved_at_540[0x280]; |
e281682b SM |
1692 | }; |
1693 | ||
1694 | struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits { | |
1695 | u8 if_in_octets_high[0x20]; | |
1696 | ||
1697 | u8 if_in_octets_low[0x20]; | |
1698 | ||
1699 | u8 if_in_ucast_pkts_high[0x20]; | |
1700 | ||
1701 | u8 if_in_ucast_pkts_low[0x20]; | |
1702 | ||
1703 | u8 if_in_discards_high[0x20]; | |
1704 | ||
1705 | u8 if_in_discards_low[0x20]; | |
1706 | ||
1707 | u8 if_in_errors_high[0x20]; | |
1708 | ||
1709 | u8 if_in_errors_low[0x20]; | |
1710 | ||
1711 | u8 if_in_unknown_protos_high[0x20]; | |
1712 | ||
1713 | u8 if_in_unknown_protos_low[0x20]; | |
1714 | ||
1715 | u8 if_out_octets_high[0x20]; | |
1716 | ||
1717 | u8 if_out_octets_low[0x20]; | |
1718 | ||
1719 | u8 if_out_ucast_pkts_high[0x20]; | |
1720 | ||
1721 | u8 if_out_ucast_pkts_low[0x20]; | |
1722 | ||
1723 | u8 if_out_discards_high[0x20]; | |
1724 | ||
1725 | u8 if_out_discards_low[0x20]; | |
1726 | ||
1727 | u8 if_out_errors_high[0x20]; | |
1728 | ||
1729 | u8 if_out_errors_low[0x20]; | |
1730 | ||
1731 | u8 if_in_multicast_pkts_high[0x20]; | |
1732 | ||
1733 | u8 if_in_multicast_pkts_low[0x20]; | |
1734 | ||
1735 | u8 if_in_broadcast_pkts_high[0x20]; | |
1736 | ||
1737 | u8 if_in_broadcast_pkts_low[0x20]; | |
1738 | ||
1739 | u8 if_out_multicast_pkts_high[0x20]; | |
1740 | ||
1741 | u8 if_out_multicast_pkts_low[0x20]; | |
1742 | ||
1743 | u8 if_out_broadcast_pkts_high[0x20]; | |
1744 | ||
1745 | u8 if_out_broadcast_pkts_low[0x20]; | |
1746 | ||
b4ff3a36 | 1747 | u8 reserved_at_340[0x480]; |
e281682b SM |
1748 | }; |
1749 | ||
1750 | struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits { | |
1751 | u8 a_frames_transmitted_ok_high[0x20]; | |
1752 | ||
1753 | u8 a_frames_transmitted_ok_low[0x20]; | |
1754 | ||
1755 | u8 a_frames_received_ok_high[0x20]; | |
1756 | ||
1757 | u8 a_frames_received_ok_low[0x20]; | |
1758 | ||
1759 | u8 a_frame_check_sequence_errors_high[0x20]; | |
1760 | ||
1761 | u8 a_frame_check_sequence_errors_low[0x20]; | |
1762 | ||
1763 | u8 a_alignment_errors_high[0x20]; | |
1764 | ||
1765 | u8 a_alignment_errors_low[0x20]; | |
1766 | ||
1767 | u8 a_octets_transmitted_ok_high[0x20]; | |
1768 | ||
1769 | u8 a_octets_transmitted_ok_low[0x20]; | |
1770 | ||
1771 | u8 a_octets_received_ok_high[0x20]; | |
1772 | ||
1773 | u8 a_octets_received_ok_low[0x20]; | |
1774 | ||
1775 | u8 a_multicast_frames_xmitted_ok_high[0x20]; | |
1776 | ||
1777 | u8 a_multicast_frames_xmitted_ok_low[0x20]; | |
1778 | ||
1779 | u8 a_broadcast_frames_xmitted_ok_high[0x20]; | |
1780 | ||
1781 | u8 a_broadcast_frames_xmitted_ok_low[0x20]; | |
1782 | ||
1783 | u8 a_multicast_frames_received_ok_high[0x20]; | |
1784 | ||
1785 | u8 a_multicast_frames_received_ok_low[0x20]; | |
1786 | ||
1787 | u8 a_broadcast_frames_received_ok_high[0x20]; | |
1788 | ||
1789 | u8 a_broadcast_frames_received_ok_low[0x20]; | |
1790 | ||
1791 | u8 a_in_range_length_errors_high[0x20]; | |
1792 | ||
1793 | u8 a_in_range_length_errors_low[0x20]; | |
1794 | ||
1795 | u8 a_out_of_range_length_field_high[0x20]; | |
1796 | ||
1797 | u8 a_out_of_range_length_field_low[0x20]; | |
1798 | ||
1799 | u8 a_frame_too_long_errors_high[0x20]; | |
1800 | ||
1801 | u8 a_frame_too_long_errors_low[0x20]; | |
1802 | ||
1803 | u8 a_symbol_error_during_carrier_high[0x20]; | |
1804 | ||
1805 | u8 a_symbol_error_during_carrier_low[0x20]; | |
1806 | ||
1807 | u8 a_mac_control_frames_transmitted_high[0x20]; | |
1808 | ||
1809 | u8 a_mac_control_frames_transmitted_low[0x20]; | |
1810 | ||
1811 | u8 a_mac_control_frames_received_high[0x20]; | |
1812 | ||
1813 | u8 a_mac_control_frames_received_low[0x20]; | |
1814 | ||
1815 | u8 a_unsupported_opcodes_received_high[0x20]; | |
1816 | ||
1817 | u8 a_unsupported_opcodes_received_low[0x20]; | |
1818 | ||
1819 | u8 a_pause_mac_ctrl_frames_received_high[0x20]; | |
1820 | ||
1821 | u8 a_pause_mac_ctrl_frames_received_low[0x20]; | |
1822 | ||
1823 | u8 a_pause_mac_ctrl_frames_transmitted_high[0x20]; | |
1824 | ||
1825 | u8 a_pause_mac_ctrl_frames_transmitted_low[0x20]; | |
1826 | ||
b4ff3a36 | 1827 | u8 reserved_at_4c0[0x300]; |
e281682b SM |
1828 | }; |
1829 | ||
8ed1a630 GP |
1830 | struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits { |
1831 | u8 life_time_counter_high[0x20]; | |
1832 | ||
1833 | u8 life_time_counter_low[0x20]; | |
1834 | ||
1835 | u8 rx_errors[0x20]; | |
1836 | ||
1837 | u8 tx_errors[0x20]; | |
1838 | ||
1839 | u8 l0_to_recovery_eieos[0x20]; | |
1840 | ||
1841 | u8 l0_to_recovery_ts[0x20]; | |
1842 | ||
1843 | u8 l0_to_recovery_framing[0x20]; | |
1844 | ||
1845 | u8 l0_to_recovery_retrain[0x20]; | |
1846 | ||
1847 | u8 crc_error_dllp[0x20]; | |
1848 | ||
1849 | u8 crc_error_tlp[0x20]; | |
1850 | ||
1851 | u8 reserved_at_140[0x680]; | |
1852 | }; | |
1853 | ||
e281682b SM |
1854 | struct mlx5_ifc_cmd_inter_comp_event_bits { |
1855 | u8 command_completion_vector[0x20]; | |
1856 | ||
b4ff3a36 | 1857 | u8 reserved_at_20[0xc0]; |
e281682b SM |
1858 | }; |
1859 | ||
1860 | struct mlx5_ifc_stall_vl_event_bits { | |
b4ff3a36 | 1861 | u8 reserved_at_0[0x18]; |
e281682b | 1862 | u8 port_num[0x1]; |
b4ff3a36 | 1863 | u8 reserved_at_19[0x3]; |
e281682b SM |
1864 | u8 vl[0x4]; |
1865 | ||
b4ff3a36 | 1866 | u8 reserved_at_20[0xa0]; |
e281682b SM |
1867 | }; |
1868 | ||
1869 | struct mlx5_ifc_db_bf_congestion_event_bits { | |
1870 | u8 event_subtype[0x8]; | |
b4ff3a36 | 1871 | u8 reserved_at_8[0x8]; |
e281682b | 1872 | u8 congestion_level[0x8]; |
b4ff3a36 | 1873 | u8 reserved_at_18[0x8]; |
e281682b | 1874 | |
b4ff3a36 | 1875 | u8 reserved_at_20[0xa0]; |
e281682b SM |
1876 | }; |
1877 | ||
1878 | struct mlx5_ifc_gpio_event_bits { | |
b4ff3a36 | 1879 | u8 reserved_at_0[0x60]; |
e281682b SM |
1880 | |
1881 | u8 gpio_event_hi[0x20]; | |
1882 | ||
1883 | u8 gpio_event_lo[0x20]; | |
1884 | ||
b4ff3a36 | 1885 | u8 reserved_at_a0[0x40]; |
e281682b SM |
1886 | }; |
1887 | ||
1888 | struct mlx5_ifc_port_state_change_event_bits { | |
b4ff3a36 | 1889 | u8 reserved_at_0[0x40]; |
e281682b SM |
1890 | |
1891 | u8 port_num[0x4]; | |
b4ff3a36 | 1892 | u8 reserved_at_44[0x1c]; |
e281682b | 1893 | |
b4ff3a36 | 1894 | u8 reserved_at_60[0x80]; |
e281682b SM |
1895 | }; |
1896 | ||
1897 | struct mlx5_ifc_dropped_packet_logged_bits { | |
b4ff3a36 | 1898 | u8 reserved_at_0[0xe0]; |
e281682b SM |
1899 | }; |
1900 | ||
1901 | enum { | |
1902 | MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1, | |
1903 | MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2, | |
1904 | }; | |
1905 | ||
1906 | struct mlx5_ifc_cq_error_bits { | |
b4ff3a36 | 1907 | u8 reserved_at_0[0x8]; |
e281682b SM |
1908 | u8 cqn[0x18]; |
1909 | ||
b4ff3a36 | 1910 | u8 reserved_at_20[0x20]; |
e281682b | 1911 | |
b4ff3a36 | 1912 | u8 reserved_at_40[0x18]; |
e281682b SM |
1913 | u8 syndrome[0x8]; |
1914 | ||
b4ff3a36 | 1915 | u8 reserved_at_60[0x80]; |
e281682b SM |
1916 | }; |
1917 | ||
1918 | struct mlx5_ifc_rdma_page_fault_event_bits { | |
1919 | u8 bytes_committed[0x20]; | |
1920 | ||
1921 | u8 r_key[0x20]; | |
1922 | ||
b4ff3a36 | 1923 | u8 reserved_at_40[0x10]; |
e281682b SM |
1924 | u8 packet_len[0x10]; |
1925 | ||
1926 | u8 rdma_op_len[0x20]; | |
1927 | ||
1928 | u8 rdma_va[0x40]; | |
1929 | ||
b4ff3a36 | 1930 | u8 reserved_at_c0[0x5]; |
e281682b SM |
1931 | u8 rdma[0x1]; |
1932 | u8 write[0x1]; | |
1933 | u8 requestor[0x1]; | |
1934 | u8 qp_number[0x18]; | |
1935 | }; | |
1936 | ||
1937 | struct mlx5_ifc_wqe_associated_page_fault_event_bits { | |
1938 | u8 bytes_committed[0x20]; | |
1939 | ||
b4ff3a36 | 1940 | u8 reserved_at_20[0x10]; |
e281682b SM |
1941 | u8 wqe_index[0x10]; |
1942 | ||
b4ff3a36 | 1943 | u8 reserved_at_40[0x10]; |
e281682b SM |
1944 | u8 len[0x10]; |
1945 | ||
b4ff3a36 | 1946 | u8 reserved_at_60[0x60]; |
e281682b | 1947 | |
b4ff3a36 | 1948 | u8 reserved_at_c0[0x5]; |
e281682b SM |
1949 | u8 rdma[0x1]; |
1950 | u8 write_read[0x1]; | |
1951 | u8 requestor[0x1]; | |
1952 | u8 qpn[0x18]; | |
1953 | }; | |
1954 | ||
1955 | struct mlx5_ifc_qp_events_bits { | |
b4ff3a36 | 1956 | u8 reserved_at_0[0xa0]; |
e281682b SM |
1957 | |
1958 | u8 type[0x8]; | |
b4ff3a36 | 1959 | u8 reserved_at_a8[0x18]; |
e281682b | 1960 | |
b4ff3a36 | 1961 | u8 reserved_at_c0[0x8]; |
e281682b SM |
1962 | u8 qpn_rqn_sqn[0x18]; |
1963 | }; | |
1964 | ||
1965 | struct mlx5_ifc_dct_events_bits { | |
b4ff3a36 | 1966 | u8 reserved_at_0[0xc0]; |
e281682b | 1967 | |
b4ff3a36 | 1968 | u8 reserved_at_c0[0x8]; |
e281682b SM |
1969 | u8 dct_number[0x18]; |
1970 | }; | |
1971 | ||
1972 | struct mlx5_ifc_comp_event_bits { | |
b4ff3a36 | 1973 | u8 reserved_at_0[0xc0]; |
e281682b | 1974 | |
b4ff3a36 | 1975 | u8 reserved_at_c0[0x8]; |
e281682b SM |
1976 | u8 cq_number[0x18]; |
1977 | }; | |
1978 | ||
1979 | enum { | |
1980 | MLX5_QPC_STATE_RST = 0x0, | |
1981 | MLX5_QPC_STATE_INIT = 0x1, | |
1982 | MLX5_QPC_STATE_RTR = 0x2, | |
1983 | MLX5_QPC_STATE_RTS = 0x3, | |
1984 | MLX5_QPC_STATE_SQER = 0x4, | |
1985 | MLX5_QPC_STATE_ERR = 0x6, | |
1986 | MLX5_QPC_STATE_SQD = 0x7, | |
1987 | MLX5_QPC_STATE_SUSPENDED = 0x9, | |
1988 | }; | |
1989 | ||
1990 | enum { | |
1991 | MLX5_QPC_ST_RC = 0x0, | |
1992 | MLX5_QPC_ST_UC = 0x1, | |
1993 | MLX5_QPC_ST_UD = 0x2, | |
1994 | MLX5_QPC_ST_XRC = 0x3, | |
1995 | MLX5_QPC_ST_DCI = 0x5, | |
1996 | MLX5_QPC_ST_QP0 = 0x7, | |
1997 | MLX5_QPC_ST_QP1 = 0x8, | |
1998 | MLX5_QPC_ST_RAW_DATAGRAM = 0x9, | |
1999 | MLX5_QPC_ST_REG_UMR = 0xc, | |
2000 | }; | |
2001 | ||
2002 | enum { | |
2003 | MLX5_QPC_PM_STATE_ARMED = 0x0, | |
2004 | MLX5_QPC_PM_STATE_REARM = 0x1, | |
2005 | MLX5_QPC_PM_STATE_RESERVED = 0x2, | |
2006 | MLX5_QPC_PM_STATE_MIGRATED = 0x3, | |
2007 | }; | |
2008 | ||
2009 | enum { | |
2010 | MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0, | |
2011 | MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1, | |
2012 | }; | |
2013 | ||
2014 | enum { | |
2015 | MLX5_QPC_MTU_256_BYTES = 0x1, | |
2016 | MLX5_QPC_MTU_512_BYTES = 0x2, | |
2017 | MLX5_QPC_MTU_1K_BYTES = 0x3, | |
2018 | MLX5_QPC_MTU_2K_BYTES = 0x4, | |
2019 | MLX5_QPC_MTU_4K_BYTES = 0x5, | |
2020 | MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7, | |
2021 | }; | |
2022 | ||
2023 | enum { | |
2024 | MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1, | |
2025 | MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2, | |
2026 | MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3, | |
2027 | MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4, | |
2028 | MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5, | |
2029 | MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6, | |
2030 | MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7, | |
2031 | MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8, | |
2032 | }; | |
2033 | ||
2034 | enum { | |
2035 | MLX5_QPC_CS_REQ_DISABLE = 0x0, | |
2036 | MLX5_QPC_CS_REQ_UP_TO_32B = 0x11, | |
2037 | MLX5_QPC_CS_REQ_UP_TO_64B = 0x22, | |
2038 | }; | |
2039 | ||
2040 | enum { | |
2041 | MLX5_QPC_CS_RES_DISABLE = 0x0, | |
2042 | MLX5_QPC_CS_RES_UP_TO_32B = 0x1, | |
2043 | MLX5_QPC_CS_RES_UP_TO_64B = 0x2, | |
2044 | }; | |
2045 | ||
2046 | struct mlx5_ifc_qpc_bits { | |
2047 | u8 state[0x4]; | |
84df61eb | 2048 | u8 lag_tx_port_affinity[0x4]; |
e281682b | 2049 | u8 st[0x8]; |
b4ff3a36 | 2050 | u8 reserved_at_10[0x3]; |
e281682b | 2051 | u8 pm_state[0x2]; |
b4ff3a36 | 2052 | u8 reserved_at_15[0x7]; |
e281682b | 2053 | u8 end_padding_mode[0x2]; |
b4ff3a36 | 2054 | u8 reserved_at_1e[0x2]; |
e281682b SM |
2055 | |
2056 | u8 wq_signature[0x1]; | |
2057 | u8 block_lb_mc[0x1]; | |
2058 | u8 atomic_like_write_en[0x1]; | |
2059 | u8 latency_sensitive[0x1]; | |
b4ff3a36 | 2060 | u8 reserved_at_24[0x1]; |
e281682b | 2061 | u8 drain_sigerr[0x1]; |
b4ff3a36 | 2062 | u8 reserved_at_26[0x2]; |
e281682b SM |
2063 | u8 pd[0x18]; |
2064 | ||
2065 | u8 mtu[0x3]; | |
2066 | u8 log_msg_max[0x5]; | |
b4ff3a36 | 2067 | u8 reserved_at_48[0x1]; |
e281682b SM |
2068 | u8 log_rq_size[0x4]; |
2069 | u8 log_rq_stride[0x3]; | |
2070 | u8 no_sq[0x1]; | |
2071 | u8 log_sq_size[0x4]; | |
b4ff3a36 | 2072 | u8 reserved_at_55[0x6]; |
e281682b | 2073 | u8 rlky[0x1]; |
1015c2e8 | 2074 | u8 ulp_stateless_offload_mode[0x4]; |
e281682b SM |
2075 | |
2076 | u8 counter_set_id[0x8]; | |
2077 | u8 uar_page[0x18]; | |
2078 | ||
b4ff3a36 | 2079 | u8 reserved_at_80[0x8]; |
e281682b SM |
2080 | u8 user_index[0x18]; |
2081 | ||
b4ff3a36 | 2082 | u8 reserved_at_a0[0x3]; |
e281682b SM |
2083 | u8 log_page_size[0x5]; |
2084 | u8 remote_qpn[0x18]; | |
2085 | ||
2086 | struct mlx5_ifc_ads_bits primary_address_path; | |
2087 | ||
2088 | struct mlx5_ifc_ads_bits secondary_address_path; | |
2089 | ||
2090 | u8 log_ack_req_freq[0x4]; | |
b4ff3a36 | 2091 | u8 reserved_at_384[0x4]; |
e281682b | 2092 | u8 log_sra_max[0x3]; |
b4ff3a36 | 2093 | u8 reserved_at_38b[0x2]; |
e281682b SM |
2094 | u8 retry_count[0x3]; |
2095 | u8 rnr_retry[0x3]; | |
b4ff3a36 | 2096 | u8 reserved_at_393[0x1]; |
e281682b SM |
2097 | u8 fre[0x1]; |
2098 | u8 cur_rnr_retry[0x3]; | |
2099 | u8 cur_retry_count[0x3]; | |
b4ff3a36 | 2100 | u8 reserved_at_39b[0x5]; |
e281682b | 2101 | |
b4ff3a36 | 2102 | u8 reserved_at_3a0[0x20]; |
e281682b | 2103 | |
b4ff3a36 | 2104 | u8 reserved_at_3c0[0x8]; |
e281682b SM |
2105 | u8 next_send_psn[0x18]; |
2106 | ||
b4ff3a36 | 2107 | u8 reserved_at_3e0[0x8]; |
e281682b SM |
2108 | u8 cqn_snd[0x18]; |
2109 | ||
09a7d9ec SM |
2110 | u8 reserved_at_400[0x8]; |
2111 | u8 deth_sqpn[0x18]; | |
2112 | ||
2113 | u8 reserved_at_420[0x20]; | |
e281682b | 2114 | |
b4ff3a36 | 2115 | u8 reserved_at_440[0x8]; |
e281682b SM |
2116 | u8 last_acked_psn[0x18]; |
2117 | ||
b4ff3a36 | 2118 | u8 reserved_at_460[0x8]; |
e281682b SM |
2119 | u8 ssn[0x18]; |
2120 | ||
b4ff3a36 | 2121 | u8 reserved_at_480[0x8]; |
e281682b | 2122 | u8 log_rra_max[0x3]; |
b4ff3a36 | 2123 | u8 reserved_at_48b[0x1]; |
e281682b SM |
2124 | u8 atomic_mode[0x4]; |
2125 | u8 rre[0x1]; | |
2126 | u8 rwe[0x1]; | |
2127 | u8 rae[0x1]; | |
b4ff3a36 | 2128 | u8 reserved_at_493[0x1]; |
e281682b | 2129 | u8 page_offset[0x6]; |
b4ff3a36 | 2130 | u8 reserved_at_49a[0x3]; |
e281682b SM |
2131 | u8 cd_slave_receive[0x1]; |
2132 | u8 cd_slave_send[0x1]; | |
2133 | u8 cd_master[0x1]; | |
2134 | ||
b4ff3a36 | 2135 | u8 reserved_at_4a0[0x3]; |
e281682b SM |
2136 | u8 min_rnr_nak[0x5]; |
2137 | u8 next_rcv_psn[0x18]; | |
2138 | ||
b4ff3a36 | 2139 | u8 reserved_at_4c0[0x8]; |
e281682b SM |
2140 | u8 xrcd[0x18]; |
2141 | ||
b4ff3a36 | 2142 | u8 reserved_at_4e0[0x8]; |
e281682b SM |
2143 | u8 cqn_rcv[0x18]; |
2144 | ||
2145 | u8 dbr_addr[0x40]; | |
2146 | ||
2147 | u8 q_key[0x20]; | |
2148 | ||
b4ff3a36 | 2149 | u8 reserved_at_560[0x5]; |
e281682b | 2150 | u8 rq_type[0x3]; |
7486216b | 2151 | u8 srqn_rmpn_xrqn[0x18]; |
e281682b | 2152 | |
b4ff3a36 | 2153 | u8 reserved_at_580[0x8]; |
e281682b SM |
2154 | u8 rmsn[0x18]; |
2155 | ||
2156 | u8 hw_sq_wqebb_counter[0x10]; | |
2157 | u8 sw_sq_wqebb_counter[0x10]; | |
2158 | ||
2159 | u8 hw_rq_counter[0x20]; | |
2160 | ||
2161 | u8 sw_rq_counter[0x20]; | |
2162 | ||
b4ff3a36 | 2163 | u8 reserved_at_600[0x20]; |
e281682b | 2164 | |
b4ff3a36 | 2165 | u8 reserved_at_620[0xf]; |
e281682b SM |
2166 | u8 cgs[0x1]; |
2167 | u8 cs_req[0x8]; | |
2168 | u8 cs_res[0x8]; | |
2169 | ||
2170 | u8 dc_access_key[0x40]; | |
2171 | ||
b4ff3a36 | 2172 | u8 reserved_at_680[0xc0]; |
e281682b SM |
2173 | }; |
2174 | ||
2175 | struct mlx5_ifc_roce_addr_layout_bits { | |
2176 | u8 source_l3_address[16][0x8]; | |
2177 | ||
b4ff3a36 | 2178 | u8 reserved_at_80[0x3]; |
e281682b SM |
2179 | u8 vlan_valid[0x1]; |
2180 | u8 vlan_id[0xc]; | |
2181 | u8 source_mac_47_32[0x10]; | |
2182 | ||
2183 | u8 source_mac_31_0[0x20]; | |
2184 | ||
b4ff3a36 | 2185 | u8 reserved_at_c0[0x14]; |
e281682b SM |
2186 | u8 roce_l3_type[0x4]; |
2187 | u8 roce_version[0x8]; | |
2188 | ||
b4ff3a36 | 2189 | u8 reserved_at_e0[0x20]; |
e281682b SM |
2190 | }; |
2191 | ||
2192 | union mlx5_ifc_hca_cap_union_bits { | |
2193 | struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap; | |
2194 | struct mlx5_ifc_odp_cap_bits odp_cap; | |
2195 | struct mlx5_ifc_atomic_caps_bits atomic_caps; | |
2196 | struct mlx5_ifc_roce_cap_bits roce_cap; | |
2197 | struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps; | |
2198 | struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap; | |
495716b1 | 2199 | struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap; |
d6666753 | 2200 | struct mlx5_ifc_e_switch_cap_bits e_switch_cap; |
3f0393a5 | 2201 | struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap; |
7486216b | 2202 | struct mlx5_ifc_qos_cap_bits qos_cap; |
e29341fb | 2203 | struct mlx5_ifc_fpga_cap_bits fpga_cap; |
b4ff3a36 | 2204 | u8 reserved_at_0[0x8000]; |
e281682b SM |
2205 | }; |
2206 | ||
2207 | enum { | |
2208 | MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1, | |
2209 | MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2, | |
2210 | MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4, | |
9dc0b289 | 2211 | MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8, |
7adbde20 HHZ |
2212 | MLX5_FLOW_CONTEXT_ACTION_ENCAP = 0x10, |
2213 | MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20, | |
2a69cb9f | 2214 | MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40, |
e281682b SM |
2215 | }; |
2216 | ||
2217 | struct mlx5_ifc_flow_context_bits { | |
b4ff3a36 | 2218 | u8 reserved_at_0[0x20]; |
e281682b SM |
2219 | |
2220 | u8 group_id[0x20]; | |
2221 | ||
b4ff3a36 | 2222 | u8 reserved_at_40[0x8]; |
e281682b SM |
2223 | u8 flow_tag[0x18]; |
2224 | ||
b4ff3a36 | 2225 | u8 reserved_at_60[0x10]; |
e281682b SM |
2226 | u8 action[0x10]; |
2227 | ||
b4ff3a36 | 2228 | u8 reserved_at_80[0x8]; |
e281682b SM |
2229 | u8 destination_list_size[0x18]; |
2230 | ||
9dc0b289 AV |
2231 | u8 reserved_at_a0[0x8]; |
2232 | u8 flow_counter_list_size[0x18]; | |
2233 | ||
7adbde20 HHZ |
2234 | u8 encap_id[0x20]; |
2235 | ||
2a69cb9f OG |
2236 | u8 modify_header_id[0x20]; |
2237 | ||
2238 | u8 reserved_at_100[0x100]; | |
e281682b SM |
2239 | |
2240 | struct mlx5_ifc_fte_match_param_bits match_value; | |
2241 | ||
b4ff3a36 | 2242 | u8 reserved_at_1200[0x600]; |
e281682b | 2243 | |
9dc0b289 | 2244 | union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0]; |
e281682b SM |
2245 | }; |
2246 | ||
2247 | enum { | |
2248 | MLX5_XRC_SRQC_STATE_GOOD = 0x0, | |
2249 | MLX5_XRC_SRQC_STATE_ERROR = 0x1, | |
2250 | }; | |
2251 | ||
2252 | struct mlx5_ifc_xrc_srqc_bits { | |
2253 | u8 state[0x4]; | |
2254 | u8 log_xrc_srq_size[0x4]; | |
b4ff3a36 | 2255 | u8 reserved_at_8[0x18]; |
e281682b SM |
2256 | |
2257 | u8 wq_signature[0x1]; | |
2258 | u8 cont_srq[0x1]; | |
b4ff3a36 | 2259 | u8 reserved_at_22[0x1]; |
e281682b SM |
2260 | u8 rlky[0x1]; |
2261 | u8 basic_cyclic_rcv_wqe[0x1]; | |
2262 | u8 log_rq_stride[0x3]; | |
2263 | u8 xrcd[0x18]; | |
2264 | ||
2265 | u8 page_offset[0x6]; | |
b4ff3a36 | 2266 | u8 reserved_at_46[0x2]; |
e281682b SM |
2267 | u8 cqn[0x18]; |
2268 | ||
b4ff3a36 | 2269 | u8 reserved_at_60[0x20]; |
e281682b SM |
2270 | |
2271 | u8 user_index_equal_xrc_srqn[0x1]; | |
b4ff3a36 | 2272 | u8 reserved_at_81[0x1]; |
e281682b SM |
2273 | u8 log_page_size[0x6]; |
2274 | u8 user_index[0x18]; | |
2275 | ||
b4ff3a36 | 2276 | u8 reserved_at_a0[0x20]; |
e281682b | 2277 | |
b4ff3a36 | 2278 | u8 reserved_at_c0[0x8]; |
e281682b SM |
2279 | u8 pd[0x18]; |
2280 | ||
2281 | u8 lwm[0x10]; | |
2282 | u8 wqe_cnt[0x10]; | |
2283 | ||
b4ff3a36 | 2284 | u8 reserved_at_100[0x40]; |
e281682b SM |
2285 | |
2286 | u8 db_record_addr_h[0x20]; | |
2287 | ||
2288 | u8 db_record_addr_l[0x1e]; | |
b4ff3a36 | 2289 | u8 reserved_at_17e[0x2]; |
e281682b | 2290 | |
b4ff3a36 | 2291 | u8 reserved_at_180[0x80]; |
e281682b SM |
2292 | }; |
2293 | ||
2294 | struct mlx5_ifc_traffic_counter_bits { | |
2295 | u8 packets[0x40]; | |
2296 | ||
2297 | u8 octets[0x40]; | |
2298 | }; | |
2299 | ||
2300 | struct mlx5_ifc_tisc_bits { | |
84df61eb AH |
2301 | u8 strict_lag_tx_port_affinity[0x1]; |
2302 | u8 reserved_at_1[0x3]; | |
2303 | u8 lag_tx_port_affinity[0x04]; | |
2304 | ||
2305 | u8 reserved_at_8[0x4]; | |
e281682b | 2306 | u8 prio[0x4]; |
b4ff3a36 | 2307 | u8 reserved_at_10[0x10]; |
e281682b | 2308 | |
b4ff3a36 | 2309 | u8 reserved_at_20[0x100]; |
e281682b | 2310 | |
b4ff3a36 | 2311 | u8 reserved_at_120[0x8]; |
e281682b SM |
2312 | u8 transport_domain[0x18]; |
2313 | ||
500a3d0d ES |
2314 | u8 reserved_at_140[0x8]; |
2315 | u8 underlay_qpn[0x18]; | |
2316 | u8 reserved_at_160[0x3a0]; | |
e281682b SM |
2317 | }; |
2318 | ||
2319 | enum { | |
2320 | MLX5_TIRC_DISP_TYPE_DIRECT = 0x0, | |
2321 | MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1, | |
2322 | }; | |
2323 | ||
2324 | enum { | |
2325 | MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1, | |
2326 | MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2, | |
2327 | }; | |
2328 | ||
2329 | enum { | |
2be6967c SM |
2330 | MLX5_RX_HASH_FN_NONE = 0x0, |
2331 | MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1, | |
2332 | MLX5_RX_HASH_FN_TOEPLITZ = 0x2, | |
e281682b SM |
2333 | }; |
2334 | ||
2335 | enum { | |
2336 | MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1, | |
2337 | MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2, | |
2338 | }; | |
2339 | ||
2340 | struct mlx5_ifc_tirc_bits { | |
b4ff3a36 | 2341 | u8 reserved_at_0[0x20]; |
e281682b SM |
2342 | |
2343 | u8 disp_type[0x4]; | |
b4ff3a36 | 2344 | u8 reserved_at_24[0x1c]; |
e281682b | 2345 | |
b4ff3a36 | 2346 | u8 reserved_at_40[0x40]; |
e281682b | 2347 | |
b4ff3a36 | 2348 | u8 reserved_at_80[0x4]; |
e281682b SM |
2349 | u8 lro_timeout_period_usecs[0x10]; |
2350 | u8 lro_enable_mask[0x4]; | |
2351 | u8 lro_max_ip_payload_size[0x8]; | |
2352 | ||
b4ff3a36 | 2353 | u8 reserved_at_a0[0x40]; |
e281682b | 2354 | |
b4ff3a36 | 2355 | u8 reserved_at_e0[0x8]; |
e281682b SM |
2356 | u8 inline_rqn[0x18]; |
2357 | ||
2358 | u8 rx_hash_symmetric[0x1]; | |
b4ff3a36 | 2359 | u8 reserved_at_101[0x1]; |
e281682b | 2360 | u8 tunneled_offload_en[0x1]; |
b4ff3a36 | 2361 | u8 reserved_at_103[0x5]; |
e281682b SM |
2362 | u8 indirect_table[0x18]; |
2363 | ||
2364 | u8 rx_hash_fn[0x4]; | |
b4ff3a36 | 2365 | u8 reserved_at_124[0x2]; |
e281682b SM |
2366 | u8 self_lb_block[0x2]; |
2367 | u8 transport_domain[0x18]; | |
2368 | ||
2369 | u8 rx_hash_toeplitz_key[10][0x20]; | |
2370 | ||
2371 | struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer; | |
2372 | ||
2373 | struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner; | |
2374 | ||
b4ff3a36 | 2375 | u8 reserved_at_2c0[0x4c0]; |
e281682b SM |
2376 | }; |
2377 | ||
2378 | enum { | |
2379 | MLX5_SRQC_STATE_GOOD = 0x0, | |
2380 | MLX5_SRQC_STATE_ERROR = 0x1, | |
2381 | }; | |
2382 | ||
2383 | struct mlx5_ifc_srqc_bits { | |
2384 | u8 state[0x4]; | |
2385 | u8 log_srq_size[0x4]; | |
b4ff3a36 | 2386 | u8 reserved_at_8[0x18]; |
e281682b SM |
2387 | |
2388 | u8 wq_signature[0x1]; | |
2389 | u8 cont_srq[0x1]; | |
b4ff3a36 | 2390 | u8 reserved_at_22[0x1]; |
e281682b | 2391 | u8 rlky[0x1]; |
b4ff3a36 | 2392 | u8 reserved_at_24[0x1]; |
e281682b SM |
2393 | u8 log_rq_stride[0x3]; |
2394 | u8 xrcd[0x18]; | |
2395 | ||
2396 | u8 page_offset[0x6]; | |
b4ff3a36 | 2397 | u8 reserved_at_46[0x2]; |
e281682b SM |
2398 | u8 cqn[0x18]; |
2399 | ||
b4ff3a36 | 2400 | u8 reserved_at_60[0x20]; |
e281682b | 2401 | |
b4ff3a36 | 2402 | u8 reserved_at_80[0x2]; |
e281682b | 2403 | u8 log_page_size[0x6]; |
b4ff3a36 | 2404 | u8 reserved_at_88[0x18]; |
e281682b | 2405 | |
b4ff3a36 | 2406 | u8 reserved_at_a0[0x20]; |
e281682b | 2407 | |
b4ff3a36 | 2408 | u8 reserved_at_c0[0x8]; |
e281682b SM |
2409 | u8 pd[0x18]; |
2410 | ||
2411 | u8 lwm[0x10]; | |
2412 | u8 wqe_cnt[0x10]; | |
2413 | ||
b4ff3a36 | 2414 | u8 reserved_at_100[0x40]; |
e281682b | 2415 | |
01949d01 | 2416 | u8 dbr_addr[0x40]; |
e281682b | 2417 | |
b4ff3a36 | 2418 | u8 reserved_at_180[0x80]; |
e281682b SM |
2419 | }; |
2420 | ||
2421 | enum { | |
2422 | MLX5_SQC_STATE_RST = 0x0, | |
2423 | MLX5_SQC_STATE_RDY = 0x1, | |
2424 | MLX5_SQC_STATE_ERR = 0x3, | |
2425 | }; | |
2426 | ||
2427 | struct mlx5_ifc_sqc_bits { | |
2428 | u8 rlky[0x1]; | |
2429 | u8 cd_master[0x1]; | |
2430 | u8 fre[0x1]; | |
2431 | u8 flush_in_error_en[0x1]; | |
cff92d7c HHZ |
2432 | u8 reserved_at_4[0x1]; |
2433 | u8 min_wqe_inline_mode[0x3]; | |
e281682b | 2434 | u8 state[0x4]; |
7d5e1423 SM |
2435 | u8 reg_umr[0x1]; |
2436 | u8 reserved_at_d[0x13]; | |
e281682b | 2437 | |
b4ff3a36 | 2438 | u8 reserved_at_20[0x8]; |
e281682b SM |
2439 | u8 user_index[0x18]; |
2440 | ||
b4ff3a36 | 2441 | u8 reserved_at_40[0x8]; |
e281682b SM |
2442 | u8 cqn[0x18]; |
2443 | ||
7486216b | 2444 | u8 reserved_at_60[0x90]; |
e281682b | 2445 | |
7486216b | 2446 | u8 packet_pacing_rate_limit_index[0x10]; |
e281682b | 2447 | u8 tis_lst_sz[0x10]; |
b4ff3a36 | 2448 | u8 reserved_at_110[0x10]; |
e281682b | 2449 | |
b4ff3a36 | 2450 | u8 reserved_at_120[0x40]; |
e281682b | 2451 | |
b4ff3a36 | 2452 | u8 reserved_at_160[0x8]; |
e281682b SM |
2453 | u8 tis_num_0[0x18]; |
2454 | ||
2455 | struct mlx5_ifc_wq_bits wq; | |
2456 | }; | |
2457 | ||
813f8540 MHY |
2458 | enum { |
2459 | SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0, | |
2460 | SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1, | |
2461 | SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2, | |
2462 | SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3, | |
2463 | }; | |
2464 | ||
2465 | struct mlx5_ifc_scheduling_context_bits { | |
2466 | u8 element_type[0x8]; | |
2467 | u8 reserved_at_8[0x18]; | |
2468 | ||
2469 | u8 element_attributes[0x20]; | |
2470 | ||
2471 | u8 parent_element_id[0x20]; | |
2472 | ||
2473 | u8 reserved_at_60[0x40]; | |
2474 | ||
2475 | u8 bw_share[0x20]; | |
2476 | ||
2477 | u8 max_average_bw[0x20]; | |
2478 | ||
2479 | u8 reserved_at_e0[0x120]; | |
2480 | }; | |
2481 | ||
e281682b | 2482 | struct mlx5_ifc_rqtc_bits { |
b4ff3a36 | 2483 | u8 reserved_at_0[0xa0]; |
e281682b | 2484 | |
b4ff3a36 | 2485 | u8 reserved_at_a0[0x10]; |
e281682b SM |
2486 | u8 rqt_max_size[0x10]; |
2487 | ||
b4ff3a36 | 2488 | u8 reserved_at_c0[0x10]; |
e281682b SM |
2489 | u8 rqt_actual_size[0x10]; |
2490 | ||
b4ff3a36 | 2491 | u8 reserved_at_e0[0x6a0]; |
e281682b SM |
2492 | |
2493 | struct mlx5_ifc_rq_num_bits rq_num[0]; | |
2494 | }; | |
2495 | ||
2496 | enum { | |
2497 | MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0, | |
2498 | MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1, | |
2499 | }; | |
2500 | ||
2501 | enum { | |
2502 | MLX5_RQC_STATE_RST = 0x0, | |
2503 | MLX5_RQC_STATE_RDY = 0x1, | |
2504 | MLX5_RQC_STATE_ERR = 0x3, | |
2505 | }; | |
2506 | ||
2507 | struct mlx5_ifc_rqc_bits { | |
2508 | u8 rlky[0x1]; | |
7d5e1423 SM |
2509 | u8 reserved_at_1[0x1]; |
2510 | u8 scatter_fcs[0x1]; | |
e281682b SM |
2511 | u8 vsd[0x1]; |
2512 | u8 mem_rq_type[0x4]; | |
2513 | u8 state[0x4]; | |
b4ff3a36 | 2514 | u8 reserved_at_c[0x1]; |
e281682b | 2515 | u8 flush_in_error_en[0x1]; |
b4ff3a36 | 2516 | u8 reserved_at_e[0x12]; |
e281682b | 2517 | |
b4ff3a36 | 2518 | u8 reserved_at_20[0x8]; |
e281682b SM |
2519 | u8 user_index[0x18]; |
2520 | ||
b4ff3a36 | 2521 | u8 reserved_at_40[0x8]; |
e281682b SM |
2522 | u8 cqn[0x18]; |
2523 | ||
2524 | u8 counter_set_id[0x8]; | |
b4ff3a36 | 2525 | u8 reserved_at_68[0x18]; |
e281682b | 2526 | |
b4ff3a36 | 2527 | u8 reserved_at_80[0x8]; |
e281682b SM |
2528 | u8 rmpn[0x18]; |
2529 | ||
b4ff3a36 | 2530 | u8 reserved_at_a0[0xe0]; |
e281682b SM |
2531 | |
2532 | struct mlx5_ifc_wq_bits wq; | |
2533 | }; | |
2534 | ||
2535 | enum { | |
2536 | MLX5_RMPC_STATE_RDY = 0x1, | |
2537 | MLX5_RMPC_STATE_ERR = 0x3, | |
2538 | }; | |
2539 | ||
2540 | struct mlx5_ifc_rmpc_bits { | |
b4ff3a36 | 2541 | u8 reserved_at_0[0x8]; |
e281682b | 2542 | u8 state[0x4]; |
b4ff3a36 | 2543 | u8 reserved_at_c[0x14]; |
e281682b SM |
2544 | |
2545 | u8 basic_cyclic_rcv_wqe[0x1]; | |
b4ff3a36 | 2546 | u8 reserved_at_21[0x1f]; |
e281682b | 2547 | |
b4ff3a36 | 2548 | u8 reserved_at_40[0x140]; |
e281682b SM |
2549 | |
2550 | struct mlx5_ifc_wq_bits wq; | |
2551 | }; | |
2552 | ||
e281682b | 2553 | struct mlx5_ifc_nic_vport_context_bits { |
cff92d7c HHZ |
2554 | u8 reserved_at_0[0x5]; |
2555 | u8 min_wqe_inline_mode[0x3]; | |
2556 | u8 reserved_at_8[0x17]; | |
e281682b SM |
2557 | u8 roce_en[0x1]; |
2558 | ||
d82b7318 | 2559 | u8 arm_change_event[0x1]; |
b4ff3a36 | 2560 | u8 reserved_at_21[0x1a]; |
d82b7318 SM |
2561 | u8 event_on_mtu[0x1]; |
2562 | u8 event_on_promisc_change[0x1]; | |
2563 | u8 event_on_vlan_change[0x1]; | |
2564 | u8 event_on_mc_address_change[0x1]; | |
2565 | u8 event_on_uc_address_change[0x1]; | |
e281682b | 2566 | |
b4ff3a36 | 2567 | u8 reserved_at_40[0xf0]; |
d82b7318 SM |
2568 | |
2569 | u8 mtu[0x10]; | |
2570 | ||
9efa7525 AS |
2571 | u8 system_image_guid[0x40]; |
2572 | u8 port_guid[0x40]; | |
2573 | u8 node_guid[0x40]; | |
2574 | ||
b4ff3a36 | 2575 | u8 reserved_at_200[0x140]; |
9efa7525 | 2576 | u8 qkey_violation_counter[0x10]; |
b4ff3a36 | 2577 | u8 reserved_at_350[0x430]; |
d82b7318 SM |
2578 | |
2579 | u8 promisc_uc[0x1]; | |
2580 | u8 promisc_mc[0x1]; | |
2581 | u8 promisc_all[0x1]; | |
b4ff3a36 | 2582 | u8 reserved_at_783[0x2]; |
e281682b | 2583 | u8 allowed_list_type[0x3]; |
b4ff3a36 | 2584 | u8 reserved_at_788[0xc]; |
e281682b SM |
2585 | u8 allowed_list_size[0xc]; |
2586 | ||
2587 | struct mlx5_ifc_mac_address_layout_bits permanent_address; | |
2588 | ||
b4ff3a36 | 2589 | u8 reserved_at_7e0[0x20]; |
e281682b SM |
2590 | |
2591 | u8 current_uc_mac_address[0][0x40]; | |
2592 | }; | |
2593 | ||
2594 | enum { | |
2595 | MLX5_MKC_ACCESS_MODE_PA = 0x0, | |
2596 | MLX5_MKC_ACCESS_MODE_MTT = 0x1, | |
2597 | MLX5_MKC_ACCESS_MODE_KLMS = 0x2, | |
bcda1aca | 2598 | MLX5_MKC_ACCESS_MODE_KSM = 0x3, |
e281682b SM |
2599 | }; |
2600 | ||
2601 | struct mlx5_ifc_mkc_bits { | |
b4ff3a36 | 2602 | u8 reserved_at_0[0x1]; |
e281682b | 2603 | u8 free[0x1]; |
b4ff3a36 | 2604 | u8 reserved_at_2[0xd]; |
e281682b SM |
2605 | u8 small_fence_on_rdma_read_response[0x1]; |
2606 | u8 umr_en[0x1]; | |
2607 | u8 a[0x1]; | |
2608 | u8 rw[0x1]; | |
2609 | u8 rr[0x1]; | |
2610 | u8 lw[0x1]; | |
2611 | u8 lr[0x1]; | |
2612 | u8 access_mode[0x2]; | |
b4ff3a36 | 2613 | u8 reserved_at_18[0x8]; |
e281682b SM |
2614 | |
2615 | u8 qpn[0x18]; | |
2616 | u8 mkey_7_0[0x8]; | |
2617 | ||
b4ff3a36 | 2618 | u8 reserved_at_40[0x20]; |
e281682b SM |
2619 | |
2620 | u8 length64[0x1]; | |
2621 | u8 bsf_en[0x1]; | |
2622 | u8 sync_umr[0x1]; | |
b4ff3a36 | 2623 | u8 reserved_at_63[0x2]; |
e281682b | 2624 | u8 expected_sigerr_count[0x1]; |
b4ff3a36 | 2625 | u8 reserved_at_66[0x1]; |
e281682b SM |
2626 | u8 en_rinval[0x1]; |
2627 | u8 pd[0x18]; | |
2628 | ||
2629 | u8 start_addr[0x40]; | |
2630 | ||
2631 | u8 len[0x40]; | |
2632 | ||
2633 | u8 bsf_octword_size[0x20]; | |
2634 | ||
b4ff3a36 | 2635 | u8 reserved_at_120[0x80]; |
e281682b SM |
2636 | |
2637 | u8 translations_octword_size[0x20]; | |
2638 | ||
b4ff3a36 | 2639 | u8 reserved_at_1c0[0x1b]; |
e281682b SM |
2640 | u8 log_page_size[0x5]; |
2641 | ||
b4ff3a36 | 2642 | u8 reserved_at_1e0[0x20]; |
e281682b SM |
2643 | }; |
2644 | ||
2645 | struct mlx5_ifc_pkey_bits { | |
b4ff3a36 | 2646 | u8 reserved_at_0[0x10]; |
e281682b SM |
2647 | u8 pkey[0x10]; |
2648 | }; | |
2649 | ||
2650 | struct mlx5_ifc_array128_auto_bits { | |
2651 | u8 array128_auto[16][0x8]; | |
2652 | }; | |
2653 | ||
2654 | struct mlx5_ifc_hca_vport_context_bits { | |
2655 | u8 field_select[0x20]; | |
2656 | ||
b4ff3a36 | 2657 | u8 reserved_at_20[0xe0]; |
e281682b SM |
2658 | |
2659 | u8 sm_virt_aware[0x1]; | |
2660 | u8 has_smi[0x1]; | |
2661 | u8 has_raw[0x1]; | |
2662 | u8 grh_required[0x1]; | |
b4ff3a36 | 2663 | u8 reserved_at_104[0xc]; |
707c4602 MD |
2664 | u8 port_physical_state[0x4]; |
2665 | u8 vport_state_policy[0x4]; | |
2666 | u8 port_state[0x4]; | |
e281682b SM |
2667 | u8 vport_state[0x4]; |
2668 | ||
b4ff3a36 | 2669 | u8 reserved_at_120[0x20]; |
707c4602 MD |
2670 | |
2671 | u8 system_image_guid[0x40]; | |
e281682b SM |
2672 | |
2673 | u8 port_guid[0x40]; | |
2674 | ||
2675 | u8 node_guid[0x40]; | |
2676 | ||
2677 | u8 cap_mask1[0x20]; | |
2678 | ||
2679 | u8 cap_mask1_field_select[0x20]; | |
2680 | ||
2681 | u8 cap_mask2[0x20]; | |
2682 | ||
2683 | u8 cap_mask2_field_select[0x20]; | |
2684 | ||
b4ff3a36 | 2685 | u8 reserved_at_280[0x80]; |
e281682b SM |
2686 | |
2687 | u8 lid[0x10]; | |
b4ff3a36 | 2688 | u8 reserved_at_310[0x4]; |
e281682b SM |
2689 | u8 init_type_reply[0x4]; |
2690 | u8 lmc[0x3]; | |
2691 | u8 subnet_timeout[0x5]; | |
2692 | ||
2693 | u8 sm_lid[0x10]; | |
2694 | u8 sm_sl[0x4]; | |
b4ff3a36 | 2695 | u8 reserved_at_334[0xc]; |
e281682b SM |
2696 | |
2697 | u8 qkey_violation_counter[0x10]; | |
2698 | u8 pkey_violation_counter[0x10]; | |
2699 | ||
b4ff3a36 | 2700 | u8 reserved_at_360[0xca0]; |
e281682b SM |
2701 | }; |
2702 | ||
d6666753 | 2703 | struct mlx5_ifc_esw_vport_context_bits { |
b4ff3a36 | 2704 | u8 reserved_at_0[0x3]; |
d6666753 SM |
2705 | u8 vport_svlan_strip[0x1]; |
2706 | u8 vport_cvlan_strip[0x1]; | |
2707 | u8 vport_svlan_insert[0x1]; | |
2708 | u8 vport_cvlan_insert[0x2]; | |
b4ff3a36 | 2709 | u8 reserved_at_8[0x18]; |
d6666753 | 2710 | |
b4ff3a36 | 2711 | u8 reserved_at_20[0x20]; |
d6666753 SM |
2712 | |
2713 | u8 svlan_cfi[0x1]; | |
2714 | u8 svlan_pcp[0x3]; | |
2715 | u8 svlan_id[0xc]; | |
2716 | u8 cvlan_cfi[0x1]; | |
2717 | u8 cvlan_pcp[0x3]; | |
2718 | u8 cvlan_id[0xc]; | |
2719 | ||
b4ff3a36 | 2720 | u8 reserved_at_60[0x7a0]; |
d6666753 SM |
2721 | }; |
2722 | ||
e281682b SM |
2723 | enum { |
2724 | MLX5_EQC_STATUS_OK = 0x0, | |
2725 | MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa, | |
2726 | }; | |
2727 | ||
2728 | enum { | |
2729 | MLX5_EQC_ST_ARMED = 0x9, | |
2730 | MLX5_EQC_ST_FIRED = 0xa, | |
2731 | }; | |
2732 | ||
2733 | struct mlx5_ifc_eqc_bits { | |
2734 | u8 status[0x4]; | |
b4ff3a36 | 2735 | u8 reserved_at_4[0x9]; |
e281682b SM |
2736 | u8 ec[0x1]; |
2737 | u8 oi[0x1]; | |
b4ff3a36 | 2738 | u8 reserved_at_f[0x5]; |
e281682b | 2739 | u8 st[0x4]; |
b4ff3a36 | 2740 | u8 reserved_at_18[0x8]; |
e281682b | 2741 | |
b4ff3a36 | 2742 | u8 reserved_at_20[0x20]; |
e281682b | 2743 | |
b4ff3a36 | 2744 | u8 reserved_at_40[0x14]; |
e281682b | 2745 | u8 page_offset[0x6]; |
b4ff3a36 | 2746 | u8 reserved_at_5a[0x6]; |
e281682b | 2747 | |
b4ff3a36 | 2748 | u8 reserved_at_60[0x3]; |
e281682b SM |
2749 | u8 log_eq_size[0x5]; |
2750 | u8 uar_page[0x18]; | |
2751 | ||
b4ff3a36 | 2752 | u8 reserved_at_80[0x20]; |
e281682b | 2753 | |
b4ff3a36 | 2754 | u8 reserved_at_a0[0x18]; |
e281682b SM |
2755 | u8 intr[0x8]; |
2756 | ||
b4ff3a36 | 2757 | u8 reserved_at_c0[0x3]; |
e281682b | 2758 | u8 log_page_size[0x5]; |
b4ff3a36 | 2759 | u8 reserved_at_c8[0x18]; |
e281682b | 2760 | |
b4ff3a36 | 2761 | u8 reserved_at_e0[0x60]; |
e281682b | 2762 | |
b4ff3a36 | 2763 | u8 reserved_at_140[0x8]; |
e281682b SM |
2764 | u8 consumer_counter[0x18]; |
2765 | ||
b4ff3a36 | 2766 | u8 reserved_at_160[0x8]; |
e281682b SM |
2767 | u8 producer_counter[0x18]; |
2768 | ||
b4ff3a36 | 2769 | u8 reserved_at_180[0x80]; |
e281682b SM |
2770 | }; |
2771 | ||
2772 | enum { | |
2773 | MLX5_DCTC_STATE_ACTIVE = 0x0, | |
2774 | MLX5_DCTC_STATE_DRAINING = 0x1, | |
2775 | MLX5_DCTC_STATE_DRAINED = 0x2, | |
2776 | }; | |
2777 | ||
2778 | enum { | |
2779 | MLX5_DCTC_CS_RES_DISABLE = 0x0, | |
2780 | MLX5_DCTC_CS_RES_NA = 0x1, | |
2781 | MLX5_DCTC_CS_RES_UP_TO_64B = 0x2, | |
2782 | }; | |
2783 | ||
2784 | enum { | |
2785 | MLX5_DCTC_MTU_256_BYTES = 0x1, | |
2786 | MLX5_DCTC_MTU_512_BYTES = 0x2, | |
2787 | MLX5_DCTC_MTU_1K_BYTES = 0x3, | |
2788 | MLX5_DCTC_MTU_2K_BYTES = 0x4, | |
2789 | MLX5_DCTC_MTU_4K_BYTES = 0x5, | |
2790 | }; | |
2791 | ||
2792 | struct mlx5_ifc_dctc_bits { | |
b4ff3a36 | 2793 | u8 reserved_at_0[0x4]; |
e281682b | 2794 | u8 state[0x4]; |
b4ff3a36 | 2795 | u8 reserved_at_8[0x18]; |
e281682b | 2796 | |
b4ff3a36 | 2797 | u8 reserved_at_20[0x8]; |
e281682b SM |
2798 | u8 user_index[0x18]; |
2799 | ||
b4ff3a36 | 2800 | u8 reserved_at_40[0x8]; |
e281682b SM |
2801 | u8 cqn[0x18]; |
2802 | ||
2803 | u8 counter_set_id[0x8]; | |
2804 | u8 atomic_mode[0x4]; | |
2805 | u8 rre[0x1]; | |
2806 | u8 rwe[0x1]; | |
2807 | u8 rae[0x1]; | |
2808 | u8 atomic_like_write_en[0x1]; | |
2809 | u8 latency_sensitive[0x1]; | |
2810 | u8 rlky[0x1]; | |
2811 | u8 free_ar[0x1]; | |
b4ff3a36 | 2812 | u8 reserved_at_73[0xd]; |
e281682b | 2813 | |
b4ff3a36 | 2814 | u8 reserved_at_80[0x8]; |
e281682b | 2815 | u8 cs_res[0x8]; |
b4ff3a36 | 2816 | u8 reserved_at_90[0x3]; |
e281682b | 2817 | u8 min_rnr_nak[0x5]; |
b4ff3a36 | 2818 | u8 reserved_at_98[0x8]; |
e281682b | 2819 | |
b4ff3a36 | 2820 | u8 reserved_at_a0[0x8]; |
7486216b | 2821 | u8 srqn_xrqn[0x18]; |
e281682b | 2822 | |
b4ff3a36 | 2823 | u8 reserved_at_c0[0x8]; |
e281682b SM |
2824 | u8 pd[0x18]; |
2825 | ||
2826 | u8 tclass[0x8]; | |
b4ff3a36 | 2827 | u8 reserved_at_e8[0x4]; |
e281682b SM |
2828 | u8 flow_label[0x14]; |
2829 | ||
2830 | u8 dc_access_key[0x40]; | |
2831 | ||
b4ff3a36 | 2832 | u8 reserved_at_140[0x5]; |
e281682b SM |
2833 | u8 mtu[0x3]; |
2834 | u8 port[0x8]; | |
2835 | u8 pkey_index[0x10]; | |
2836 | ||
b4ff3a36 | 2837 | u8 reserved_at_160[0x8]; |
e281682b | 2838 | u8 my_addr_index[0x8]; |
b4ff3a36 | 2839 | u8 reserved_at_170[0x8]; |
e281682b SM |
2840 | u8 hop_limit[0x8]; |
2841 | ||
2842 | u8 dc_access_key_violation_count[0x20]; | |
2843 | ||
b4ff3a36 | 2844 | u8 reserved_at_1a0[0x14]; |
e281682b SM |
2845 | u8 dei_cfi[0x1]; |
2846 | u8 eth_prio[0x3]; | |
2847 | u8 ecn[0x2]; | |
2848 | u8 dscp[0x6]; | |
2849 | ||
b4ff3a36 | 2850 | u8 reserved_at_1c0[0x40]; |
e281682b SM |
2851 | }; |
2852 | ||
2853 | enum { | |
2854 | MLX5_CQC_STATUS_OK = 0x0, | |
2855 | MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9, | |
2856 | MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa, | |
2857 | }; | |
2858 | ||
2859 | enum { | |
2860 | MLX5_CQC_CQE_SZ_64_BYTES = 0x0, | |
2861 | MLX5_CQC_CQE_SZ_128_BYTES = 0x1, | |
2862 | }; | |
2863 | ||
2864 | enum { | |
2865 | MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6, | |
2866 | MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9, | |
2867 | MLX5_CQC_ST_FIRED = 0xa, | |
2868 | }; | |
2869 | ||
7d5e1423 SM |
2870 | enum { |
2871 | MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0, | |
2872 | MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1, | |
7486216b | 2873 | MLX5_CQ_PERIOD_NUM_MODES |
7d5e1423 SM |
2874 | }; |
2875 | ||
e281682b SM |
2876 | struct mlx5_ifc_cqc_bits { |
2877 | u8 status[0x4]; | |
b4ff3a36 | 2878 | u8 reserved_at_4[0x4]; |
e281682b SM |
2879 | u8 cqe_sz[0x3]; |
2880 | u8 cc[0x1]; | |
b4ff3a36 | 2881 | u8 reserved_at_c[0x1]; |
e281682b SM |
2882 | u8 scqe_break_moderation_en[0x1]; |
2883 | u8 oi[0x1]; | |
7d5e1423 SM |
2884 | u8 cq_period_mode[0x2]; |
2885 | u8 cqe_comp_en[0x1]; | |
e281682b SM |
2886 | u8 mini_cqe_res_format[0x2]; |
2887 | u8 st[0x4]; | |
b4ff3a36 | 2888 | u8 reserved_at_18[0x8]; |
e281682b | 2889 | |
b4ff3a36 | 2890 | u8 reserved_at_20[0x20]; |
e281682b | 2891 | |
b4ff3a36 | 2892 | u8 reserved_at_40[0x14]; |
e281682b | 2893 | u8 page_offset[0x6]; |
b4ff3a36 | 2894 | u8 reserved_at_5a[0x6]; |
e281682b | 2895 | |
b4ff3a36 | 2896 | u8 reserved_at_60[0x3]; |
e281682b SM |
2897 | u8 log_cq_size[0x5]; |
2898 | u8 uar_page[0x18]; | |
2899 | ||
b4ff3a36 | 2900 | u8 reserved_at_80[0x4]; |
e281682b SM |
2901 | u8 cq_period[0xc]; |
2902 | u8 cq_max_count[0x10]; | |
2903 | ||
b4ff3a36 | 2904 | u8 reserved_at_a0[0x18]; |
e281682b SM |
2905 | u8 c_eqn[0x8]; |
2906 | ||
b4ff3a36 | 2907 | u8 reserved_at_c0[0x3]; |
e281682b | 2908 | u8 log_page_size[0x5]; |
b4ff3a36 | 2909 | u8 reserved_at_c8[0x18]; |
e281682b | 2910 | |
b4ff3a36 | 2911 | u8 reserved_at_e0[0x20]; |
e281682b | 2912 | |
b4ff3a36 | 2913 | u8 reserved_at_100[0x8]; |
e281682b SM |
2914 | u8 last_notified_index[0x18]; |
2915 | ||
b4ff3a36 | 2916 | u8 reserved_at_120[0x8]; |
e281682b SM |
2917 | u8 last_solicit_index[0x18]; |
2918 | ||
b4ff3a36 | 2919 | u8 reserved_at_140[0x8]; |
e281682b SM |
2920 | u8 consumer_counter[0x18]; |
2921 | ||
b4ff3a36 | 2922 | u8 reserved_at_160[0x8]; |
e281682b SM |
2923 | u8 producer_counter[0x18]; |
2924 | ||
b4ff3a36 | 2925 | u8 reserved_at_180[0x40]; |
e281682b SM |
2926 | |
2927 | u8 dbr_addr[0x40]; | |
2928 | }; | |
2929 | ||
2930 | union mlx5_ifc_cong_control_roce_ecn_auto_bits { | |
2931 | struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp; | |
2932 | struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp; | |
2933 | struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np; | |
b4ff3a36 | 2934 | u8 reserved_at_0[0x800]; |
e281682b SM |
2935 | }; |
2936 | ||
2937 | struct mlx5_ifc_query_adapter_param_block_bits { | |
b4ff3a36 | 2938 | u8 reserved_at_0[0xc0]; |
e281682b | 2939 | |
b4ff3a36 | 2940 | u8 reserved_at_c0[0x8]; |
211e6c80 MD |
2941 | u8 ieee_vendor_id[0x18]; |
2942 | ||
b4ff3a36 | 2943 | u8 reserved_at_e0[0x10]; |
e281682b SM |
2944 | u8 vsd_vendor_id[0x10]; |
2945 | ||
2946 | u8 vsd[208][0x8]; | |
2947 | ||
2948 | u8 vsd_contd_psid[16][0x8]; | |
2949 | }; | |
2950 | ||
7486216b SM |
2951 | enum { |
2952 | MLX5_XRQC_STATE_GOOD = 0x0, | |
2953 | MLX5_XRQC_STATE_ERROR = 0x1, | |
2954 | }; | |
2955 | ||
2956 | enum { | |
2957 | MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0, | |
2958 | MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1, | |
2959 | }; | |
2960 | ||
2961 | enum { | |
2962 | MLX5_XRQC_OFFLOAD_RNDV = 0x1, | |
2963 | }; | |
2964 | ||
2965 | struct mlx5_ifc_tag_matching_topology_context_bits { | |
2966 | u8 log_matching_list_sz[0x4]; | |
2967 | u8 reserved_at_4[0xc]; | |
2968 | u8 append_next_index[0x10]; | |
2969 | ||
2970 | u8 sw_phase_cnt[0x10]; | |
2971 | u8 hw_phase_cnt[0x10]; | |
2972 | ||
2973 | u8 reserved_at_40[0x40]; | |
2974 | }; | |
2975 | ||
2976 | struct mlx5_ifc_xrqc_bits { | |
2977 | u8 state[0x4]; | |
2978 | u8 rlkey[0x1]; | |
2979 | u8 reserved_at_5[0xf]; | |
2980 | u8 topology[0x4]; | |
2981 | u8 reserved_at_18[0x4]; | |
2982 | u8 offload[0x4]; | |
2983 | ||
2984 | u8 reserved_at_20[0x8]; | |
2985 | u8 user_index[0x18]; | |
2986 | ||
2987 | u8 reserved_at_40[0x8]; | |
2988 | u8 cqn[0x18]; | |
2989 | ||
2990 | u8 reserved_at_60[0xa0]; | |
2991 | ||
2992 | struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context; | |
2993 | ||
5579e151 | 2994 | u8 reserved_at_180[0x880]; |
7486216b SM |
2995 | |
2996 | struct mlx5_ifc_wq_bits wq; | |
2997 | }; | |
2998 | ||
e281682b SM |
2999 | union mlx5_ifc_modify_field_select_resize_field_select_auto_bits { |
3000 | struct mlx5_ifc_modify_field_select_bits modify_field_select; | |
3001 | struct mlx5_ifc_resize_field_select_bits resize_field_select; | |
b4ff3a36 | 3002 | u8 reserved_at_0[0x20]; |
e281682b SM |
3003 | }; |
3004 | ||
3005 | union mlx5_ifc_field_select_802_1_r_roce_auto_bits { | |
3006 | struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp; | |
3007 | struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp; | |
3008 | struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np; | |
b4ff3a36 | 3009 | u8 reserved_at_0[0x20]; |
e281682b SM |
3010 | }; |
3011 | ||
3012 | union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits { | |
3013 | struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; | |
3014 | struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; | |
3015 | struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; | |
3016 | struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; | |
3017 | struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; | |
3018 | struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; | |
3019 | struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout; | |
1c64bf6f | 3020 | struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; |
e281682b | 3021 | struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; |
d8dc0508 | 3022 | struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs; |
b4ff3a36 | 3023 | u8 reserved_at_0[0x7c0]; |
e281682b SM |
3024 | }; |
3025 | ||
8ed1a630 GP |
3026 | union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits { |
3027 | struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout; | |
3028 | u8 reserved_at_0[0x7c0]; | |
3029 | }; | |
3030 | ||
e281682b SM |
3031 | union mlx5_ifc_event_auto_bits { |
3032 | struct mlx5_ifc_comp_event_bits comp_event; | |
3033 | struct mlx5_ifc_dct_events_bits dct_events; | |
3034 | struct mlx5_ifc_qp_events_bits qp_events; | |
3035 | struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event; | |
3036 | struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event; | |
3037 | struct mlx5_ifc_cq_error_bits cq_error; | |
3038 | struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged; | |
3039 | struct mlx5_ifc_port_state_change_event_bits port_state_change_event; | |
3040 | struct mlx5_ifc_gpio_event_bits gpio_event; | |
3041 | struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event; | |
3042 | struct mlx5_ifc_stall_vl_event_bits stall_vl_event; | |
3043 | struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event; | |
b4ff3a36 | 3044 | u8 reserved_at_0[0xe0]; |
e281682b SM |
3045 | }; |
3046 | ||
3047 | struct mlx5_ifc_health_buffer_bits { | |
b4ff3a36 | 3048 | u8 reserved_at_0[0x100]; |
e281682b SM |
3049 | |
3050 | u8 assert_existptr[0x20]; | |
3051 | ||
3052 | u8 assert_callra[0x20]; | |
3053 | ||
b4ff3a36 | 3054 | u8 reserved_at_140[0x40]; |
e281682b SM |
3055 | |
3056 | u8 fw_version[0x20]; | |
3057 | ||
3058 | u8 hw_id[0x20]; | |
3059 | ||
b4ff3a36 | 3060 | u8 reserved_at_1c0[0x20]; |
e281682b SM |
3061 | |
3062 | u8 irisc_index[0x8]; | |
3063 | u8 synd[0x8]; | |
3064 | u8 ext_synd[0x10]; | |
3065 | }; | |
3066 | ||
3067 | struct mlx5_ifc_register_loopback_control_bits { | |
3068 | u8 no_lb[0x1]; | |
b4ff3a36 | 3069 | u8 reserved_at_1[0x7]; |
e281682b | 3070 | u8 port[0x8]; |
b4ff3a36 | 3071 | u8 reserved_at_10[0x10]; |
e281682b | 3072 | |
b4ff3a36 | 3073 | u8 reserved_at_20[0x60]; |
e281682b SM |
3074 | }; |
3075 | ||
813f8540 MHY |
3076 | struct mlx5_ifc_vport_tc_element_bits { |
3077 | u8 traffic_class[0x4]; | |
3078 | u8 reserved_at_4[0xc]; | |
3079 | u8 vport_number[0x10]; | |
3080 | }; | |
3081 | ||
3082 | struct mlx5_ifc_vport_element_bits { | |
3083 | u8 reserved_at_0[0x10]; | |
3084 | u8 vport_number[0x10]; | |
3085 | }; | |
3086 | ||
3087 | enum { | |
3088 | TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0, | |
3089 | TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1, | |
3090 | TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2, | |
3091 | }; | |
3092 | ||
3093 | struct mlx5_ifc_tsar_element_bits { | |
3094 | u8 reserved_at_0[0x8]; | |
3095 | u8 tsar_type[0x8]; | |
3096 | u8 reserved_at_10[0x10]; | |
3097 | }; | |
3098 | ||
8812c24d MD |
3099 | enum { |
3100 | MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_SUCCESS = 0x0, | |
3101 | MLX5_TEARDOWN_HCA_OUT_FORCE_STATE_FAIL = 0x1, | |
3102 | }; | |
3103 | ||
e281682b SM |
3104 | struct mlx5_ifc_teardown_hca_out_bits { |
3105 | u8 status[0x8]; | |
b4ff3a36 | 3106 | u8 reserved_at_8[0x18]; |
e281682b SM |
3107 | |
3108 | u8 syndrome[0x20]; | |
3109 | ||
8812c24d MD |
3110 | u8 reserved_at_40[0x3f]; |
3111 | ||
3112 | u8 force_state[0x1]; | |
e281682b SM |
3113 | }; |
3114 | ||
3115 | enum { | |
3116 | MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0, | |
8812c24d | 3117 | MLX5_TEARDOWN_HCA_IN_PROFILE_FORCE_CLOSE = 0x1, |
e281682b SM |
3118 | }; |
3119 | ||
3120 | struct mlx5_ifc_teardown_hca_in_bits { | |
3121 | u8 opcode[0x10]; | |
b4ff3a36 | 3122 | u8 reserved_at_10[0x10]; |
e281682b | 3123 | |
b4ff3a36 | 3124 | u8 reserved_at_20[0x10]; |
e281682b SM |
3125 | u8 op_mod[0x10]; |
3126 | ||
b4ff3a36 | 3127 | u8 reserved_at_40[0x10]; |
e281682b SM |
3128 | u8 profile[0x10]; |
3129 | ||
b4ff3a36 | 3130 | u8 reserved_at_60[0x20]; |
e281682b SM |
3131 | }; |
3132 | ||
3133 | struct mlx5_ifc_sqerr2rts_qp_out_bits { | |
3134 | u8 status[0x8]; | |
b4ff3a36 | 3135 | u8 reserved_at_8[0x18]; |
e281682b SM |
3136 | |
3137 | u8 syndrome[0x20]; | |
3138 | ||
b4ff3a36 | 3139 | u8 reserved_at_40[0x40]; |
e281682b SM |
3140 | }; |
3141 | ||
3142 | struct mlx5_ifc_sqerr2rts_qp_in_bits { | |
3143 | u8 opcode[0x10]; | |
b4ff3a36 | 3144 | u8 reserved_at_10[0x10]; |
e281682b | 3145 | |
b4ff3a36 | 3146 | u8 reserved_at_20[0x10]; |
e281682b SM |
3147 | u8 op_mod[0x10]; |
3148 | ||
b4ff3a36 | 3149 | u8 reserved_at_40[0x8]; |
e281682b SM |
3150 | u8 qpn[0x18]; |
3151 | ||
b4ff3a36 | 3152 | u8 reserved_at_60[0x20]; |
e281682b SM |
3153 | |
3154 | u8 opt_param_mask[0x20]; | |
3155 | ||
b4ff3a36 | 3156 | u8 reserved_at_a0[0x20]; |
e281682b SM |
3157 | |
3158 | struct mlx5_ifc_qpc_bits qpc; | |
3159 | ||
b4ff3a36 | 3160 | u8 reserved_at_800[0x80]; |
e281682b SM |
3161 | }; |
3162 | ||
3163 | struct mlx5_ifc_sqd2rts_qp_out_bits { | |
3164 | u8 status[0x8]; | |
b4ff3a36 | 3165 | u8 reserved_at_8[0x18]; |
e281682b SM |
3166 | |
3167 | u8 syndrome[0x20]; | |
3168 | ||
b4ff3a36 | 3169 | u8 reserved_at_40[0x40]; |
e281682b SM |
3170 | }; |
3171 | ||
3172 | struct mlx5_ifc_sqd2rts_qp_in_bits { | |
3173 | u8 opcode[0x10]; | |
b4ff3a36 | 3174 | u8 reserved_at_10[0x10]; |
e281682b | 3175 | |
b4ff3a36 | 3176 | u8 reserved_at_20[0x10]; |
e281682b SM |
3177 | u8 op_mod[0x10]; |
3178 | ||
b4ff3a36 | 3179 | u8 reserved_at_40[0x8]; |
e281682b SM |
3180 | u8 qpn[0x18]; |
3181 | ||
b4ff3a36 | 3182 | u8 reserved_at_60[0x20]; |
e281682b SM |
3183 | |
3184 | u8 opt_param_mask[0x20]; | |
3185 | ||
b4ff3a36 | 3186 | u8 reserved_at_a0[0x20]; |
e281682b SM |
3187 | |
3188 | struct mlx5_ifc_qpc_bits qpc; | |
3189 | ||
b4ff3a36 | 3190 | u8 reserved_at_800[0x80]; |
e281682b SM |
3191 | }; |
3192 | ||
3193 | struct mlx5_ifc_set_roce_address_out_bits { | |
3194 | u8 status[0x8]; | |
b4ff3a36 | 3195 | u8 reserved_at_8[0x18]; |
e281682b SM |
3196 | |
3197 | u8 syndrome[0x20]; | |
3198 | ||
b4ff3a36 | 3199 | u8 reserved_at_40[0x40]; |
e281682b SM |
3200 | }; |
3201 | ||
3202 | struct mlx5_ifc_set_roce_address_in_bits { | |
3203 | u8 opcode[0x10]; | |
b4ff3a36 | 3204 | u8 reserved_at_10[0x10]; |
e281682b | 3205 | |
b4ff3a36 | 3206 | u8 reserved_at_20[0x10]; |
e281682b SM |
3207 | u8 op_mod[0x10]; |
3208 | ||
3209 | u8 roce_address_index[0x10]; | |
b4ff3a36 | 3210 | u8 reserved_at_50[0x10]; |
e281682b | 3211 | |
b4ff3a36 | 3212 | u8 reserved_at_60[0x20]; |
e281682b SM |
3213 | |
3214 | struct mlx5_ifc_roce_addr_layout_bits roce_address; | |
3215 | }; | |
3216 | ||
3217 | struct mlx5_ifc_set_mad_demux_out_bits { | |
3218 | u8 status[0x8]; | |
b4ff3a36 | 3219 | u8 reserved_at_8[0x18]; |
e281682b SM |
3220 | |
3221 | u8 syndrome[0x20]; | |
3222 | ||
b4ff3a36 | 3223 | u8 reserved_at_40[0x40]; |
e281682b SM |
3224 | }; |
3225 | ||
3226 | enum { | |
3227 | MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0, | |
3228 | MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2, | |
3229 | }; | |
3230 | ||
3231 | struct mlx5_ifc_set_mad_demux_in_bits { | |
3232 | u8 opcode[0x10]; | |
b4ff3a36 | 3233 | u8 reserved_at_10[0x10]; |
e281682b | 3234 | |
b4ff3a36 | 3235 | u8 reserved_at_20[0x10]; |
e281682b SM |
3236 | u8 op_mod[0x10]; |
3237 | ||
b4ff3a36 | 3238 | u8 reserved_at_40[0x20]; |
e281682b | 3239 | |
b4ff3a36 | 3240 | u8 reserved_at_60[0x6]; |
e281682b | 3241 | u8 demux_mode[0x2]; |
b4ff3a36 | 3242 | u8 reserved_at_68[0x18]; |
e281682b SM |
3243 | }; |
3244 | ||
3245 | struct mlx5_ifc_set_l2_table_entry_out_bits { | |
3246 | u8 status[0x8]; | |
b4ff3a36 | 3247 | u8 reserved_at_8[0x18]; |
e281682b SM |
3248 | |
3249 | u8 syndrome[0x20]; | |
3250 | ||
b4ff3a36 | 3251 | u8 reserved_at_40[0x40]; |
e281682b SM |
3252 | }; |
3253 | ||
3254 | struct mlx5_ifc_set_l2_table_entry_in_bits { | |
3255 | u8 opcode[0x10]; | |
b4ff3a36 | 3256 | u8 reserved_at_10[0x10]; |
e281682b | 3257 | |
b4ff3a36 | 3258 | u8 reserved_at_20[0x10]; |
e281682b SM |
3259 | u8 op_mod[0x10]; |
3260 | ||
b4ff3a36 | 3261 | u8 reserved_at_40[0x60]; |
e281682b | 3262 | |
b4ff3a36 | 3263 | u8 reserved_at_a0[0x8]; |
e281682b SM |
3264 | u8 table_index[0x18]; |
3265 | ||
b4ff3a36 | 3266 | u8 reserved_at_c0[0x20]; |
e281682b | 3267 | |
b4ff3a36 | 3268 | u8 reserved_at_e0[0x13]; |
e281682b SM |
3269 | u8 vlan_valid[0x1]; |
3270 | u8 vlan[0xc]; | |
3271 | ||
3272 | struct mlx5_ifc_mac_address_layout_bits mac_address; | |
3273 | ||
b4ff3a36 | 3274 | u8 reserved_at_140[0xc0]; |
e281682b SM |
3275 | }; |
3276 | ||
3277 | struct mlx5_ifc_set_issi_out_bits { | |
3278 | u8 status[0x8]; | |
b4ff3a36 | 3279 | u8 reserved_at_8[0x18]; |
e281682b SM |
3280 | |
3281 | u8 syndrome[0x20]; | |
3282 | ||
b4ff3a36 | 3283 | u8 reserved_at_40[0x40]; |
e281682b SM |
3284 | }; |
3285 | ||
3286 | struct mlx5_ifc_set_issi_in_bits { | |
3287 | u8 opcode[0x10]; | |
b4ff3a36 | 3288 | u8 reserved_at_10[0x10]; |
e281682b | 3289 | |
b4ff3a36 | 3290 | u8 reserved_at_20[0x10]; |
e281682b SM |
3291 | u8 op_mod[0x10]; |
3292 | ||
b4ff3a36 | 3293 | u8 reserved_at_40[0x10]; |
e281682b SM |
3294 | u8 current_issi[0x10]; |
3295 | ||
b4ff3a36 | 3296 | u8 reserved_at_60[0x20]; |
e281682b SM |
3297 | }; |
3298 | ||
3299 | struct mlx5_ifc_set_hca_cap_out_bits { | |
3300 | u8 status[0x8]; | |
b4ff3a36 | 3301 | u8 reserved_at_8[0x18]; |
e281682b SM |
3302 | |
3303 | u8 syndrome[0x20]; | |
3304 | ||
b4ff3a36 | 3305 | u8 reserved_at_40[0x40]; |
e281682b SM |
3306 | }; |
3307 | ||
3308 | struct mlx5_ifc_set_hca_cap_in_bits { | |
3309 | u8 opcode[0x10]; | |
b4ff3a36 | 3310 | u8 reserved_at_10[0x10]; |
e281682b | 3311 | |
b4ff3a36 | 3312 | u8 reserved_at_20[0x10]; |
e281682b SM |
3313 | u8 op_mod[0x10]; |
3314 | ||
b4ff3a36 | 3315 | u8 reserved_at_40[0x40]; |
e281682b SM |
3316 | |
3317 | union mlx5_ifc_hca_cap_union_bits capability; | |
3318 | }; | |
3319 | ||
26a81453 MG |
3320 | enum { |
3321 | MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0, | |
3322 | MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1, | |
3323 | MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2, | |
3324 | MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3 | |
3325 | }; | |
3326 | ||
e281682b SM |
3327 | struct mlx5_ifc_set_fte_out_bits { |
3328 | u8 status[0x8]; | |
b4ff3a36 | 3329 | u8 reserved_at_8[0x18]; |
e281682b SM |
3330 | |
3331 | u8 syndrome[0x20]; | |
3332 | ||
b4ff3a36 | 3333 | u8 reserved_at_40[0x40]; |
e281682b SM |
3334 | }; |
3335 | ||
3336 | struct mlx5_ifc_set_fte_in_bits { | |
3337 | u8 opcode[0x10]; | |
b4ff3a36 | 3338 | u8 reserved_at_10[0x10]; |
e281682b | 3339 | |
b4ff3a36 | 3340 | u8 reserved_at_20[0x10]; |
e281682b SM |
3341 | u8 op_mod[0x10]; |
3342 | ||
7d5e1423 SM |
3343 | u8 other_vport[0x1]; |
3344 | u8 reserved_at_41[0xf]; | |
3345 | u8 vport_number[0x10]; | |
3346 | ||
3347 | u8 reserved_at_60[0x20]; | |
e281682b SM |
3348 | |
3349 | u8 table_type[0x8]; | |
b4ff3a36 | 3350 | u8 reserved_at_88[0x18]; |
e281682b | 3351 | |
b4ff3a36 | 3352 | u8 reserved_at_a0[0x8]; |
e281682b SM |
3353 | u8 table_id[0x18]; |
3354 | ||
b4ff3a36 | 3355 | u8 reserved_at_c0[0x18]; |
26a81453 MG |
3356 | u8 modify_enable_mask[0x8]; |
3357 | ||
b4ff3a36 | 3358 | u8 reserved_at_e0[0x20]; |
e281682b SM |
3359 | |
3360 | u8 flow_index[0x20]; | |
3361 | ||
b4ff3a36 | 3362 | u8 reserved_at_120[0xe0]; |
e281682b SM |
3363 | |
3364 | struct mlx5_ifc_flow_context_bits flow_context; | |
3365 | }; | |
3366 | ||
3367 | struct mlx5_ifc_rts2rts_qp_out_bits { | |
3368 | u8 status[0x8]; | |
b4ff3a36 | 3369 | u8 reserved_at_8[0x18]; |
e281682b SM |
3370 | |
3371 | u8 syndrome[0x20]; | |
3372 | ||
b4ff3a36 | 3373 | u8 reserved_at_40[0x40]; |
e281682b SM |
3374 | }; |
3375 | ||
3376 | struct mlx5_ifc_rts2rts_qp_in_bits { | |
3377 | u8 opcode[0x10]; | |
b4ff3a36 | 3378 | u8 reserved_at_10[0x10]; |
e281682b | 3379 | |
b4ff3a36 | 3380 | u8 reserved_at_20[0x10]; |
e281682b SM |
3381 | u8 op_mod[0x10]; |
3382 | ||
b4ff3a36 | 3383 | u8 reserved_at_40[0x8]; |
e281682b SM |
3384 | u8 qpn[0x18]; |
3385 | ||
b4ff3a36 | 3386 | u8 reserved_at_60[0x20]; |
e281682b SM |
3387 | |
3388 | u8 opt_param_mask[0x20]; | |
3389 | ||
b4ff3a36 | 3390 | u8 reserved_at_a0[0x20]; |
e281682b SM |
3391 | |
3392 | struct mlx5_ifc_qpc_bits qpc; | |
3393 | ||
b4ff3a36 | 3394 | u8 reserved_at_800[0x80]; |
e281682b SM |
3395 | }; |
3396 | ||
3397 | struct mlx5_ifc_rtr2rts_qp_out_bits { | |
3398 | u8 status[0x8]; | |
b4ff3a36 | 3399 | u8 reserved_at_8[0x18]; |
e281682b SM |
3400 | |
3401 | u8 syndrome[0x20]; | |
3402 | ||
b4ff3a36 | 3403 | u8 reserved_at_40[0x40]; |
e281682b SM |
3404 | }; |
3405 | ||
3406 | struct mlx5_ifc_rtr2rts_qp_in_bits { | |
3407 | u8 opcode[0x10]; | |
b4ff3a36 | 3408 | u8 reserved_at_10[0x10]; |
e281682b | 3409 | |
b4ff3a36 | 3410 | u8 reserved_at_20[0x10]; |
e281682b SM |
3411 | u8 op_mod[0x10]; |
3412 | ||
b4ff3a36 | 3413 | u8 reserved_at_40[0x8]; |
e281682b SM |
3414 | u8 qpn[0x18]; |
3415 | ||
b4ff3a36 | 3416 | u8 reserved_at_60[0x20]; |
e281682b SM |
3417 | |
3418 | u8 opt_param_mask[0x20]; | |
3419 | ||
b4ff3a36 | 3420 | u8 reserved_at_a0[0x20]; |
e281682b SM |
3421 | |
3422 | struct mlx5_ifc_qpc_bits qpc; | |
3423 | ||
b4ff3a36 | 3424 | u8 reserved_at_800[0x80]; |
e281682b SM |
3425 | }; |
3426 | ||
3427 | struct mlx5_ifc_rst2init_qp_out_bits { | |
3428 | u8 status[0x8]; | |
b4ff3a36 | 3429 | u8 reserved_at_8[0x18]; |
e281682b SM |
3430 | |
3431 | u8 syndrome[0x20]; | |
3432 | ||
b4ff3a36 | 3433 | u8 reserved_at_40[0x40]; |
e281682b SM |
3434 | }; |
3435 | ||
3436 | struct mlx5_ifc_rst2init_qp_in_bits { | |
3437 | u8 opcode[0x10]; | |
b4ff3a36 | 3438 | u8 reserved_at_10[0x10]; |
e281682b | 3439 | |
b4ff3a36 | 3440 | u8 reserved_at_20[0x10]; |
e281682b SM |
3441 | u8 op_mod[0x10]; |
3442 | ||
b4ff3a36 | 3443 | u8 reserved_at_40[0x8]; |
e281682b SM |
3444 | u8 qpn[0x18]; |
3445 | ||
b4ff3a36 | 3446 | u8 reserved_at_60[0x20]; |
e281682b SM |
3447 | |
3448 | u8 opt_param_mask[0x20]; | |
3449 | ||
b4ff3a36 | 3450 | u8 reserved_at_a0[0x20]; |
e281682b SM |
3451 | |
3452 | struct mlx5_ifc_qpc_bits qpc; | |
3453 | ||
b4ff3a36 | 3454 | u8 reserved_at_800[0x80]; |
e281682b SM |
3455 | }; |
3456 | ||
7486216b SM |
3457 | struct mlx5_ifc_query_xrq_out_bits { |
3458 | u8 status[0x8]; | |
3459 | u8 reserved_at_8[0x18]; | |
3460 | ||
3461 | u8 syndrome[0x20]; | |
3462 | ||
3463 | u8 reserved_at_40[0x40]; | |
3464 | ||
3465 | struct mlx5_ifc_xrqc_bits xrq_context; | |
3466 | }; | |
3467 | ||
3468 | struct mlx5_ifc_query_xrq_in_bits { | |
3469 | u8 opcode[0x10]; | |
3470 | u8 reserved_at_10[0x10]; | |
3471 | ||
3472 | u8 reserved_at_20[0x10]; | |
3473 | u8 op_mod[0x10]; | |
3474 | ||
3475 | u8 reserved_at_40[0x8]; | |
3476 | u8 xrqn[0x18]; | |
3477 | ||
3478 | u8 reserved_at_60[0x20]; | |
3479 | }; | |
3480 | ||
e281682b SM |
3481 | struct mlx5_ifc_query_xrc_srq_out_bits { |
3482 | u8 status[0x8]; | |
b4ff3a36 | 3483 | u8 reserved_at_8[0x18]; |
e281682b SM |
3484 | |
3485 | u8 syndrome[0x20]; | |
3486 | ||
b4ff3a36 | 3487 | u8 reserved_at_40[0x40]; |
e281682b SM |
3488 | |
3489 | struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; | |
3490 | ||
b4ff3a36 | 3491 | u8 reserved_at_280[0x600]; |
e281682b SM |
3492 | |
3493 | u8 pas[0][0x40]; | |
3494 | }; | |
3495 | ||
3496 | struct mlx5_ifc_query_xrc_srq_in_bits { | |
3497 | u8 opcode[0x10]; | |
b4ff3a36 | 3498 | u8 reserved_at_10[0x10]; |
e281682b | 3499 | |
b4ff3a36 | 3500 | u8 reserved_at_20[0x10]; |
e281682b SM |
3501 | u8 op_mod[0x10]; |
3502 | ||
b4ff3a36 | 3503 | u8 reserved_at_40[0x8]; |
e281682b SM |
3504 | u8 xrc_srqn[0x18]; |
3505 | ||
b4ff3a36 | 3506 | u8 reserved_at_60[0x20]; |
e281682b SM |
3507 | }; |
3508 | ||
3509 | enum { | |
3510 | MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0, | |
3511 | MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1, | |
3512 | }; | |
3513 | ||
3514 | struct mlx5_ifc_query_vport_state_out_bits { | |
3515 | u8 status[0x8]; | |
b4ff3a36 | 3516 | u8 reserved_at_8[0x18]; |
e281682b SM |
3517 | |
3518 | u8 syndrome[0x20]; | |
3519 | ||
b4ff3a36 | 3520 | u8 reserved_at_40[0x20]; |
e281682b | 3521 | |
b4ff3a36 | 3522 | u8 reserved_at_60[0x18]; |
e281682b SM |
3523 | u8 admin_state[0x4]; |
3524 | u8 state[0x4]; | |
3525 | }; | |
3526 | ||
3527 | enum { | |
3528 | MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0, | |
e7546514 | 3529 | MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1, |
e281682b SM |
3530 | }; |
3531 | ||
3532 | struct mlx5_ifc_query_vport_state_in_bits { | |
3533 | u8 opcode[0x10]; | |
b4ff3a36 | 3534 | u8 reserved_at_10[0x10]; |
e281682b | 3535 | |
b4ff3a36 | 3536 | u8 reserved_at_20[0x10]; |
e281682b SM |
3537 | u8 op_mod[0x10]; |
3538 | ||
3539 | u8 other_vport[0x1]; | |
b4ff3a36 | 3540 | u8 reserved_at_41[0xf]; |
e281682b SM |
3541 | u8 vport_number[0x10]; |
3542 | ||
b4ff3a36 | 3543 | u8 reserved_at_60[0x20]; |
e281682b SM |
3544 | }; |
3545 | ||
3546 | struct mlx5_ifc_query_vport_counter_out_bits { | |
3547 | u8 status[0x8]; | |
b4ff3a36 | 3548 | u8 reserved_at_8[0x18]; |
e281682b SM |
3549 | |
3550 | u8 syndrome[0x20]; | |
3551 | ||
b4ff3a36 | 3552 | u8 reserved_at_40[0x40]; |
e281682b SM |
3553 | |
3554 | struct mlx5_ifc_traffic_counter_bits received_errors; | |
3555 | ||
3556 | struct mlx5_ifc_traffic_counter_bits transmit_errors; | |
3557 | ||
3558 | struct mlx5_ifc_traffic_counter_bits received_ib_unicast; | |
3559 | ||
3560 | struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast; | |
3561 | ||
3562 | struct mlx5_ifc_traffic_counter_bits received_ib_multicast; | |
3563 | ||
3564 | struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast; | |
3565 | ||
3566 | struct mlx5_ifc_traffic_counter_bits received_eth_broadcast; | |
3567 | ||
3568 | struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast; | |
3569 | ||
3570 | struct mlx5_ifc_traffic_counter_bits received_eth_unicast; | |
3571 | ||
3572 | struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast; | |
3573 | ||
3574 | struct mlx5_ifc_traffic_counter_bits received_eth_multicast; | |
3575 | ||
3576 | struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast; | |
3577 | ||
b4ff3a36 | 3578 | u8 reserved_at_680[0xa00]; |
e281682b SM |
3579 | }; |
3580 | ||
3581 | enum { | |
3582 | MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0, | |
3583 | }; | |
3584 | ||
3585 | struct mlx5_ifc_query_vport_counter_in_bits { | |
3586 | u8 opcode[0x10]; | |
b4ff3a36 | 3587 | u8 reserved_at_10[0x10]; |
e281682b | 3588 | |
b4ff3a36 | 3589 | u8 reserved_at_20[0x10]; |
e281682b SM |
3590 | u8 op_mod[0x10]; |
3591 | ||
3592 | u8 other_vport[0x1]; | |
b54ba277 MY |
3593 | u8 reserved_at_41[0xb]; |
3594 | u8 port_num[0x4]; | |
e281682b SM |
3595 | u8 vport_number[0x10]; |
3596 | ||
b4ff3a36 | 3597 | u8 reserved_at_60[0x60]; |
e281682b SM |
3598 | |
3599 | u8 clear[0x1]; | |
b4ff3a36 | 3600 | u8 reserved_at_c1[0x1f]; |
e281682b | 3601 | |
b4ff3a36 | 3602 | u8 reserved_at_e0[0x20]; |
e281682b SM |
3603 | }; |
3604 | ||
3605 | struct mlx5_ifc_query_tis_out_bits { | |
3606 | u8 status[0x8]; | |
b4ff3a36 | 3607 | u8 reserved_at_8[0x18]; |
e281682b SM |
3608 | |
3609 | u8 syndrome[0x20]; | |
3610 | ||
b4ff3a36 | 3611 | u8 reserved_at_40[0x40]; |
e281682b SM |
3612 | |
3613 | struct mlx5_ifc_tisc_bits tis_context; | |
3614 | }; | |
3615 | ||
3616 | struct mlx5_ifc_query_tis_in_bits { | |
3617 | u8 opcode[0x10]; | |
b4ff3a36 | 3618 | u8 reserved_at_10[0x10]; |
e281682b | 3619 | |
b4ff3a36 | 3620 | u8 reserved_at_20[0x10]; |
e281682b SM |
3621 | u8 op_mod[0x10]; |
3622 | ||
b4ff3a36 | 3623 | u8 reserved_at_40[0x8]; |
e281682b SM |
3624 | u8 tisn[0x18]; |
3625 | ||
b4ff3a36 | 3626 | u8 reserved_at_60[0x20]; |
e281682b SM |
3627 | }; |
3628 | ||
3629 | struct mlx5_ifc_query_tir_out_bits { | |
3630 | u8 status[0x8]; | |
b4ff3a36 | 3631 | u8 reserved_at_8[0x18]; |
e281682b SM |
3632 | |
3633 | u8 syndrome[0x20]; | |
3634 | ||
b4ff3a36 | 3635 | u8 reserved_at_40[0xc0]; |
e281682b SM |
3636 | |
3637 | struct mlx5_ifc_tirc_bits tir_context; | |
3638 | }; | |
3639 | ||
3640 | struct mlx5_ifc_query_tir_in_bits { | |
3641 | u8 opcode[0x10]; | |
b4ff3a36 | 3642 | u8 reserved_at_10[0x10]; |
e281682b | 3643 | |
b4ff3a36 | 3644 | u8 reserved_at_20[0x10]; |
e281682b SM |
3645 | u8 op_mod[0x10]; |
3646 | ||
b4ff3a36 | 3647 | u8 reserved_at_40[0x8]; |
e281682b SM |
3648 | u8 tirn[0x18]; |
3649 | ||
b4ff3a36 | 3650 | u8 reserved_at_60[0x20]; |
e281682b SM |
3651 | }; |
3652 | ||
3653 | struct mlx5_ifc_query_srq_out_bits { | |
3654 | u8 status[0x8]; | |
b4ff3a36 | 3655 | u8 reserved_at_8[0x18]; |
e281682b SM |
3656 | |
3657 | u8 syndrome[0x20]; | |
3658 | ||
b4ff3a36 | 3659 | u8 reserved_at_40[0x40]; |
e281682b SM |
3660 | |
3661 | struct mlx5_ifc_srqc_bits srq_context_entry; | |
3662 | ||
b4ff3a36 | 3663 | u8 reserved_at_280[0x600]; |
e281682b SM |
3664 | |
3665 | u8 pas[0][0x40]; | |
3666 | }; | |
3667 | ||
3668 | struct mlx5_ifc_query_srq_in_bits { | |
3669 | u8 opcode[0x10]; | |
b4ff3a36 | 3670 | u8 reserved_at_10[0x10]; |
e281682b | 3671 | |
b4ff3a36 | 3672 | u8 reserved_at_20[0x10]; |
e281682b SM |
3673 | u8 op_mod[0x10]; |
3674 | ||
b4ff3a36 | 3675 | u8 reserved_at_40[0x8]; |
e281682b SM |
3676 | u8 srqn[0x18]; |
3677 | ||
b4ff3a36 | 3678 | u8 reserved_at_60[0x20]; |
e281682b SM |
3679 | }; |
3680 | ||
3681 | struct mlx5_ifc_query_sq_out_bits { | |
3682 | u8 status[0x8]; | |
b4ff3a36 | 3683 | u8 reserved_at_8[0x18]; |
e281682b SM |
3684 | |
3685 | u8 syndrome[0x20]; | |
3686 | ||
b4ff3a36 | 3687 | u8 reserved_at_40[0xc0]; |
e281682b SM |
3688 | |
3689 | struct mlx5_ifc_sqc_bits sq_context; | |
3690 | }; | |
3691 | ||
3692 | struct mlx5_ifc_query_sq_in_bits { | |
3693 | u8 opcode[0x10]; | |
b4ff3a36 | 3694 | u8 reserved_at_10[0x10]; |
e281682b | 3695 | |
b4ff3a36 | 3696 | u8 reserved_at_20[0x10]; |
e281682b SM |
3697 | u8 op_mod[0x10]; |
3698 | ||
b4ff3a36 | 3699 | u8 reserved_at_40[0x8]; |
e281682b SM |
3700 | u8 sqn[0x18]; |
3701 | ||
b4ff3a36 | 3702 | u8 reserved_at_60[0x20]; |
e281682b SM |
3703 | }; |
3704 | ||
3705 | struct mlx5_ifc_query_special_contexts_out_bits { | |
3706 | u8 status[0x8]; | |
b4ff3a36 | 3707 | u8 reserved_at_8[0x18]; |
e281682b SM |
3708 | |
3709 | u8 syndrome[0x20]; | |
3710 | ||
ec22eb53 | 3711 | u8 dump_fill_mkey[0x20]; |
e281682b SM |
3712 | |
3713 | u8 resd_lkey[0x20]; | |
bcda1aca AK |
3714 | |
3715 | u8 null_mkey[0x20]; | |
3716 | ||
3717 | u8 reserved_at_a0[0x60]; | |
e281682b SM |
3718 | }; |
3719 | ||
3720 | struct mlx5_ifc_query_special_contexts_in_bits { | |
3721 | u8 opcode[0x10]; | |
b4ff3a36 | 3722 | u8 reserved_at_10[0x10]; |
e281682b | 3723 | |
b4ff3a36 | 3724 | u8 reserved_at_20[0x10]; |
e281682b SM |
3725 | u8 op_mod[0x10]; |
3726 | ||
b4ff3a36 | 3727 | u8 reserved_at_40[0x40]; |
e281682b SM |
3728 | }; |
3729 | ||
813f8540 MHY |
3730 | struct mlx5_ifc_query_scheduling_element_out_bits { |
3731 | u8 opcode[0x10]; | |
3732 | u8 reserved_at_10[0x10]; | |
3733 | ||
3734 | u8 reserved_at_20[0x10]; | |
3735 | u8 op_mod[0x10]; | |
3736 | ||
3737 | u8 reserved_at_40[0xc0]; | |
3738 | ||
3739 | struct mlx5_ifc_scheduling_context_bits scheduling_context; | |
3740 | ||
3741 | u8 reserved_at_300[0x100]; | |
3742 | }; | |
3743 | ||
3744 | enum { | |
3745 | SCHEDULING_HIERARCHY_E_SWITCH = 0x2, | |
3746 | }; | |
3747 | ||
3748 | struct mlx5_ifc_query_scheduling_element_in_bits { | |
3749 | u8 opcode[0x10]; | |
3750 | u8 reserved_at_10[0x10]; | |
3751 | ||
3752 | u8 reserved_at_20[0x10]; | |
3753 | u8 op_mod[0x10]; | |
3754 | ||
3755 | u8 scheduling_hierarchy[0x8]; | |
3756 | u8 reserved_at_48[0x18]; | |
3757 | ||
3758 | u8 scheduling_element_id[0x20]; | |
3759 | ||
3760 | u8 reserved_at_80[0x180]; | |
3761 | }; | |
3762 | ||
e281682b SM |
3763 | struct mlx5_ifc_query_rqt_out_bits { |
3764 | u8 status[0x8]; | |
b4ff3a36 | 3765 | u8 reserved_at_8[0x18]; |
e281682b SM |
3766 | |
3767 | u8 syndrome[0x20]; | |
3768 | ||
b4ff3a36 | 3769 | u8 reserved_at_40[0xc0]; |
e281682b SM |
3770 | |
3771 | struct mlx5_ifc_rqtc_bits rqt_context; | |
3772 | }; | |
3773 | ||
3774 | struct mlx5_ifc_query_rqt_in_bits { | |
3775 | u8 opcode[0x10]; | |
b4ff3a36 | 3776 | u8 reserved_at_10[0x10]; |
e281682b | 3777 | |
b4ff3a36 | 3778 | u8 reserved_at_20[0x10]; |
e281682b SM |
3779 | u8 op_mod[0x10]; |
3780 | ||
b4ff3a36 | 3781 | u8 reserved_at_40[0x8]; |
e281682b SM |
3782 | u8 rqtn[0x18]; |
3783 | ||
b4ff3a36 | 3784 | u8 reserved_at_60[0x20]; |
e281682b SM |
3785 | }; |
3786 | ||
3787 | struct mlx5_ifc_query_rq_out_bits { | |
3788 | u8 status[0x8]; | |
b4ff3a36 | 3789 | u8 reserved_at_8[0x18]; |
e281682b SM |
3790 | |
3791 | u8 syndrome[0x20]; | |
3792 | ||
b4ff3a36 | 3793 | u8 reserved_at_40[0xc0]; |
e281682b SM |
3794 | |
3795 | struct mlx5_ifc_rqc_bits rq_context; | |
3796 | }; | |
3797 | ||
3798 | struct mlx5_ifc_query_rq_in_bits { | |
3799 | u8 opcode[0x10]; | |
b4ff3a36 | 3800 | u8 reserved_at_10[0x10]; |
e281682b | 3801 | |
b4ff3a36 | 3802 | u8 reserved_at_20[0x10]; |
e281682b SM |
3803 | u8 op_mod[0x10]; |
3804 | ||
b4ff3a36 | 3805 | u8 reserved_at_40[0x8]; |
e281682b SM |
3806 | u8 rqn[0x18]; |
3807 | ||
b4ff3a36 | 3808 | u8 reserved_at_60[0x20]; |
e281682b SM |
3809 | }; |
3810 | ||
3811 | struct mlx5_ifc_query_roce_address_out_bits { | |
3812 | u8 status[0x8]; | |
b4ff3a36 | 3813 | u8 reserved_at_8[0x18]; |
e281682b SM |
3814 | |
3815 | u8 syndrome[0x20]; | |
3816 | ||
b4ff3a36 | 3817 | u8 reserved_at_40[0x40]; |
e281682b SM |
3818 | |
3819 | struct mlx5_ifc_roce_addr_layout_bits roce_address; | |
3820 | }; | |
3821 | ||
3822 | struct mlx5_ifc_query_roce_address_in_bits { | |
3823 | u8 opcode[0x10]; | |
b4ff3a36 | 3824 | u8 reserved_at_10[0x10]; |
e281682b | 3825 | |
b4ff3a36 | 3826 | u8 reserved_at_20[0x10]; |
e281682b SM |
3827 | u8 op_mod[0x10]; |
3828 | ||
3829 | u8 roce_address_index[0x10]; | |
b4ff3a36 | 3830 | u8 reserved_at_50[0x10]; |
e281682b | 3831 | |
b4ff3a36 | 3832 | u8 reserved_at_60[0x20]; |
e281682b SM |
3833 | }; |
3834 | ||
3835 | struct mlx5_ifc_query_rmp_out_bits { | |
3836 | u8 status[0x8]; | |
b4ff3a36 | 3837 | u8 reserved_at_8[0x18]; |
e281682b SM |
3838 | |
3839 | u8 syndrome[0x20]; | |
3840 | ||
b4ff3a36 | 3841 | u8 reserved_at_40[0xc0]; |
e281682b SM |
3842 | |
3843 | struct mlx5_ifc_rmpc_bits rmp_context; | |
3844 | }; | |
3845 | ||
3846 | struct mlx5_ifc_query_rmp_in_bits { | |
3847 | u8 opcode[0x10]; | |
b4ff3a36 | 3848 | u8 reserved_at_10[0x10]; |
e281682b | 3849 | |
b4ff3a36 | 3850 | u8 reserved_at_20[0x10]; |
e281682b SM |
3851 | u8 op_mod[0x10]; |
3852 | ||
b4ff3a36 | 3853 | u8 reserved_at_40[0x8]; |
e281682b SM |
3854 | u8 rmpn[0x18]; |
3855 | ||
b4ff3a36 | 3856 | u8 reserved_at_60[0x20]; |
e281682b SM |
3857 | }; |
3858 | ||
3859 | struct mlx5_ifc_query_qp_out_bits { | |
3860 | u8 status[0x8]; | |
b4ff3a36 | 3861 | u8 reserved_at_8[0x18]; |
e281682b SM |
3862 | |
3863 | u8 syndrome[0x20]; | |
3864 | ||
b4ff3a36 | 3865 | u8 reserved_at_40[0x40]; |
e281682b SM |
3866 | |
3867 | u8 opt_param_mask[0x20]; | |
3868 | ||
b4ff3a36 | 3869 | u8 reserved_at_a0[0x20]; |
e281682b SM |
3870 | |
3871 | struct mlx5_ifc_qpc_bits qpc; | |
3872 | ||
b4ff3a36 | 3873 | u8 reserved_at_800[0x80]; |
e281682b SM |
3874 | |
3875 | u8 pas[0][0x40]; | |
3876 | }; | |
3877 | ||
3878 | struct mlx5_ifc_query_qp_in_bits { | |
3879 | u8 opcode[0x10]; | |
b4ff3a36 | 3880 | u8 reserved_at_10[0x10]; |
e281682b | 3881 | |
b4ff3a36 | 3882 | u8 reserved_at_20[0x10]; |
e281682b SM |
3883 | u8 op_mod[0x10]; |
3884 | ||
b4ff3a36 | 3885 | u8 reserved_at_40[0x8]; |
e281682b SM |
3886 | u8 qpn[0x18]; |
3887 | ||
b4ff3a36 | 3888 | u8 reserved_at_60[0x20]; |
e281682b SM |
3889 | }; |
3890 | ||
3891 | struct mlx5_ifc_query_q_counter_out_bits { | |
3892 | u8 status[0x8]; | |
b4ff3a36 | 3893 | u8 reserved_at_8[0x18]; |
e281682b SM |
3894 | |
3895 | u8 syndrome[0x20]; | |
3896 | ||
b4ff3a36 | 3897 | u8 reserved_at_40[0x40]; |
e281682b SM |
3898 | |
3899 | u8 rx_write_requests[0x20]; | |
3900 | ||
b4ff3a36 | 3901 | u8 reserved_at_a0[0x20]; |
e281682b SM |
3902 | |
3903 | u8 rx_read_requests[0x20]; | |
3904 | ||
b4ff3a36 | 3905 | u8 reserved_at_e0[0x20]; |
e281682b SM |
3906 | |
3907 | u8 rx_atomic_requests[0x20]; | |
3908 | ||
b4ff3a36 | 3909 | u8 reserved_at_120[0x20]; |
e281682b SM |
3910 | |
3911 | u8 rx_dct_connect[0x20]; | |
3912 | ||
b4ff3a36 | 3913 | u8 reserved_at_160[0x20]; |
e281682b SM |
3914 | |
3915 | u8 out_of_buffer[0x20]; | |
3916 | ||
b4ff3a36 | 3917 | u8 reserved_at_1a0[0x20]; |
e281682b SM |
3918 | |
3919 | u8 out_of_sequence[0x20]; | |
3920 | ||
7486216b SM |
3921 | u8 reserved_at_1e0[0x20]; |
3922 | ||
3923 | u8 duplicate_request[0x20]; | |
3924 | ||
3925 | u8 reserved_at_220[0x20]; | |
3926 | ||
3927 | u8 rnr_nak_retry_err[0x20]; | |
3928 | ||
3929 | u8 reserved_at_260[0x20]; | |
3930 | ||
3931 | u8 packet_seq_err[0x20]; | |
3932 | ||
3933 | u8 reserved_at_2a0[0x20]; | |
3934 | ||
3935 | u8 implied_nak_seq_err[0x20]; | |
3936 | ||
3937 | u8 reserved_at_2e0[0x20]; | |
3938 | ||
3939 | u8 local_ack_timeout_err[0x20]; | |
3940 | ||
3941 | u8 reserved_at_320[0x4e0]; | |
e281682b SM |
3942 | }; |
3943 | ||
3944 | struct mlx5_ifc_query_q_counter_in_bits { | |
3945 | u8 opcode[0x10]; | |
b4ff3a36 | 3946 | u8 reserved_at_10[0x10]; |
e281682b | 3947 | |
b4ff3a36 | 3948 | u8 reserved_at_20[0x10]; |
e281682b SM |
3949 | u8 op_mod[0x10]; |
3950 | ||
b4ff3a36 | 3951 | u8 reserved_at_40[0x80]; |
e281682b SM |
3952 | |
3953 | u8 clear[0x1]; | |
b4ff3a36 | 3954 | u8 reserved_at_c1[0x1f]; |
e281682b | 3955 | |
b4ff3a36 | 3956 | u8 reserved_at_e0[0x18]; |
e281682b SM |
3957 | u8 counter_set_id[0x8]; |
3958 | }; | |
3959 | ||
3960 | struct mlx5_ifc_query_pages_out_bits { | |
3961 | u8 status[0x8]; | |
b4ff3a36 | 3962 | u8 reserved_at_8[0x18]; |
e281682b SM |
3963 | |
3964 | u8 syndrome[0x20]; | |
3965 | ||
b4ff3a36 | 3966 | u8 reserved_at_40[0x10]; |
e281682b SM |
3967 | u8 function_id[0x10]; |
3968 | ||
3969 | u8 num_pages[0x20]; | |
3970 | }; | |
3971 | ||
3972 | enum { | |
3973 | MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1, | |
3974 | MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2, | |
3975 | MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3, | |
3976 | }; | |
3977 | ||
3978 | struct mlx5_ifc_query_pages_in_bits { | |
3979 | u8 opcode[0x10]; | |
b4ff3a36 | 3980 | u8 reserved_at_10[0x10]; |
e281682b | 3981 | |
b4ff3a36 | 3982 | u8 reserved_at_20[0x10]; |
e281682b SM |
3983 | u8 op_mod[0x10]; |
3984 | ||
b4ff3a36 | 3985 | u8 reserved_at_40[0x10]; |
e281682b SM |
3986 | u8 function_id[0x10]; |
3987 | ||
b4ff3a36 | 3988 | u8 reserved_at_60[0x20]; |
e281682b SM |
3989 | }; |
3990 | ||
3991 | struct mlx5_ifc_query_nic_vport_context_out_bits { | |
3992 | u8 status[0x8]; | |
b4ff3a36 | 3993 | u8 reserved_at_8[0x18]; |
e281682b SM |
3994 | |
3995 | u8 syndrome[0x20]; | |
3996 | ||
b4ff3a36 | 3997 | u8 reserved_at_40[0x40]; |
e281682b SM |
3998 | |
3999 | struct mlx5_ifc_nic_vport_context_bits nic_vport_context; | |
4000 | }; | |
4001 | ||
4002 | struct mlx5_ifc_query_nic_vport_context_in_bits { | |
4003 | u8 opcode[0x10]; | |
b4ff3a36 | 4004 | u8 reserved_at_10[0x10]; |
e281682b | 4005 | |
b4ff3a36 | 4006 | u8 reserved_at_20[0x10]; |
e281682b SM |
4007 | u8 op_mod[0x10]; |
4008 | ||
4009 | u8 other_vport[0x1]; | |
b4ff3a36 | 4010 | u8 reserved_at_41[0xf]; |
e281682b SM |
4011 | u8 vport_number[0x10]; |
4012 | ||
b4ff3a36 | 4013 | u8 reserved_at_60[0x5]; |
e281682b | 4014 | u8 allowed_list_type[0x3]; |
b4ff3a36 | 4015 | u8 reserved_at_68[0x18]; |
e281682b SM |
4016 | }; |
4017 | ||
4018 | struct mlx5_ifc_query_mkey_out_bits { | |
4019 | u8 status[0x8]; | |
b4ff3a36 | 4020 | u8 reserved_at_8[0x18]; |
e281682b SM |
4021 | |
4022 | u8 syndrome[0x20]; | |
4023 | ||
b4ff3a36 | 4024 | u8 reserved_at_40[0x40]; |
e281682b SM |
4025 | |
4026 | struct mlx5_ifc_mkc_bits memory_key_mkey_entry; | |
4027 | ||
b4ff3a36 | 4028 | u8 reserved_at_280[0x600]; |
e281682b SM |
4029 | |
4030 | u8 bsf0_klm0_pas_mtt0_1[16][0x8]; | |
4031 | ||
4032 | u8 bsf1_klm1_pas_mtt2_3[16][0x8]; | |
4033 | }; | |
4034 | ||
4035 | struct mlx5_ifc_query_mkey_in_bits { | |
4036 | u8 opcode[0x10]; | |
b4ff3a36 | 4037 | u8 reserved_at_10[0x10]; |
e281682b | 4038 | |
b4ff3a36 | 4039 | u8 reserved_at_20[0x10]; |
e281682b SM |
4040 | u8 op_mod[0x10]; |
4041 | ||
b4ff3a36 | 4042 | u8 reserved_at_40[0x8]; |
e281682b SM |
4043 | u8 mkey_index[0x18]; |
4044 | ||
4045 | u8 pg_access[0x1]; | |
b4ff3a36 | 4046 | u8 reserved_at_61[0x1f]; |
e281682b SM |
4047 | }; |
4048 | ||
4049 | struct mlx5_ifc_query_mad_demux_out_bits { | |
4050 | u8 status[0x8]; | |
b4ff3a36 | 4051 | u8 reserved_at_8[0x18]; |
e281682b SM |
4052 | |
4053 | u8 syndrome[0x20]; | |
4054 | ||
b4ff3a36 | 4055 | u8 reserved_at_40[0x40]; |
e281682b SM |
4056 | |
4057 | u8 mad_dumux_parameters_block[0x20]; | |
4058 | }; | |
4059 | ||
4060 | struct mlx5_ifc_query_mad_demux_in_bits { | |
4061 | u8 opcode[0x10]; | |
b4ff3a36 | 4062 | u8 reserved_at_10[0x10]; |
e281682b | 4063 | |
b4ff3a36 | 4064 | u8 reserved_at_20[0x10]; |
e281682b SM |
4065 | u8 op_mod[0x10]; |
4066 | ||
b4ff3a36 | 4067 | u8 reserved_at_40[0x40]; |
e281682b SM |
4068 | }; |
4069 | ||
4070 | struct mlx5_ifc_query_l2_table_entry_out_bits { | |
4071 | u8 status[0x8]; | |
b4ff3a36 | 4072 | u8 reserved_at_8[0x18]; |
e281682b SM |
4073 | |
4074 | u8 syndrome[0x20]; | |
4075 | ||
b4ff3a36 | 4076 | u8 reserved_at_40[0xa0]; |
e281682b | 4077 | |
b4ff3a36 | 4078 | u8 reserved_at_e0[0x13]; |
e281682b SM |
4079 | u8 vlan_valid[0x1]; |
4080 | u8 vlan[0xc]; | |
4081 | ||
4082 | struct mlx5_ifc_mac_address_layout_bits mac_address; | |
4083 | ||
b4ff3a36 | 4084 | u8 reserved_at_140[0xc0]; |
e281682b SM |
4085 | }; |
4086 | ||
4087 | struct mlx5_ifc_query_l2_table_entry_in_bits { | |
4088 | u8 opcode[0x10]; | |
b4ff3a36 | 4089 | u8 reserved_at_10[0x10]; |
e281682b | 4090 | |
b4ff3a36 | 4091 | u8 reserved_at_20[0x10]; |
e281682b SM |
4092 | u8 op_mod[0x10]; |
4093 | ||
b4ff3a36 | 4094 | u8 reserved_at_40[0x60]; |
e281682b | 4095 | |
b4ff3a36 | 4096 | u8 reserved_at_a0[0x8]; |
e281682b SM |
4097 | u8 table_index[0x18]; |
4098 | ||
b4ff3a36 | 4099 | u8 reserved_at_c0[0x140]; |
e281682b SM |
4100 | }; |
4101 | ||
4102 | struct mlx5_ifc_query_issi_out_bits { | |
4103 | u8 status[0x8]; | |
b4ff3a36 | 4104 | u8 reserved_at_8[0x18]; |
e281682b SM |
4105 | |
4106 | u8 syndrome[0x20]; | |
4107 | ||
b4ff3a36 | 4108 | u8 reserved_at_40[0x10]; |
e281682b SM |
4109 | u8 current_issi[0x10]; |
4110 | ||
b4ff3a36 | 4111 | u8 reserved_at_60[0xa0]; |
e281682b | 4112 | |
b4ff3a36 | 4113 | u8 reserved_at_100[76][0x8]; |
e281682b SM |
4114 | u8 supported_issi_dw0[0x20]; |
4115 | }; | |
4116 | ||
4117 | struct mlx5_ifc_query_issi_in_bits { | |
4118 | u8 opcode[0x10]; | |
b4ff3a36 | 4119 | u8 reserved_at_10[0x10]; |
e281682b | 4120 | |
b4ff3a36 | 4121 | u8 reserved_at_20[0x10]; |
e281682b SM |
4122 | u8 op_mod[0x10]; |
4123 | ||
b4ff3a36 | 4124 | u8 reserved_at_40[0x40]; |
e281682b SM |
4125 | }; |
4126 | ||
0dbc6fe0 SM |
4127 | struct mlx5_ifc_set_driver_version_out_bits { |
4128 | u8 status[0x8]; | |
4129 | u8 reserved_0[0x18]; | |
4130 | ||
4131 | u8 syndrome[0x20]; | |
4132 | u8 reserved_1[0x40]; | |
4133 | }; | |
4134 | ||
4135 | struct mlx5_ifc_set_driver_version_in_bits { | |
4136 | u8 opcode[0x10]; | |
4137 | u8 reserved_0[0x10]; | |
4138 | ||
4139 | u8 reserved_1[0x10]; | |
4140 | u8 op_mod[0x10]; | |
4141 | ||
4142 | u8 reserved_2[0x40]; | |
4143 | u8 driver_version[64][0x8]; | |
4144 | }; | |
4145 | ||
e281682b SM |
4146 | struct mlx5_ifc_query_hca_vport_pkey_out_bits { |
4147 | u8 status[0x8]; | |
b4ff3a36 | 4148 | u8 reserved_at_8[0x18]; |
e281682b SM |
4149 | |
4150 | u8 syndrome[0x20]; | |
4151 | ||
b4ff3a36 | 4152 | u8 reserved_at_40[0x40]; |
e281682b SM |
4153 | |
4154 | struct mlx5_ifc_pkey_bits pkey[0]; | |
4155 | }; | |
4156 | ||
4157 | struct mlx5_ifc_query_hca_vport_pkey_in_bits { | |
4158 | u8 opcode[0x10]; | |
b4ff3a36 | 4159 | u8 reserved_at_10[0x10]; |
e281682b | 4160 | |
b4ff3a36 | 4161 | u8 reserved_at_20[0x10]; |
e281682b SM |
4162 | u8 op_mod[0x10]; |
4163 | ||
4164 | u8 other_vport[0x1]; | |
b4ff3a36 | 4165 | u8 reserved_at_41[0xb]; |
707c4602 | 4166 | u8 port_num[0x4]; |
e281682b SM |
4167 | u8 vport_number[0x10]; |
4168 | ||
b4ff3a36 | 4169 | u8 reserved_at_60[0x10]; |
e281682b SM |
4170 | u8 pkey_index[0x10]; |
4171 | }; | |
4172 | ||
eff901d3 EC |
4173 | enum { |
4174 | MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0, | |
4175 | MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1, | |
4176 | MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2, | |
4177 | }; | |
4178 | ||
e281682b SM |
4179 | struct mlx5_ifc_query_hca_vport_gid_out_bits { |
4180 | u8 status[0x8]; | |
b4ff3a36 | 4181 | u8 reserved_at_8[0x18]; |
e281682b SM |
4182 | |
4183 | u8 syndrome[0x20]; | |
4184 | ||
b4ff3a36 | 4185 | u8 reserved_at_40[0x20]; |
e281682b SM |
4186 | |
4187 | u8 gids_num[0x10]; | |
b4ff3a36 | 4188 | u8 reserved_at_70[0x10]; |
e281682b SM |
4189 | |
4190 | struct mlx5_ifc_array128_auto_bits gid[0]; | |
4191 | }; | |
4192 | ||
4193 | struct mlx5_ifc_query_hca_vport_gid_in_bits { | |
4194 | u8 opcode[0x10]; | |
b4ff3a36 | 4195 | u8 reserved_at_10[0x10]; |
e281682b | 4196 | |
b4ff3a36 | 4197 | u8 reserved_at_20[0x10]; |
e281682b SM |
4198 | u8 op_mod[0x10]; |
4199 | ||
4200 | u8 other_vport[0x1]; | |
b4ff3a36 | 4201 | u8 reserved_at_41[0xb]; |
707c4602 | 4202 | u8 port_num[0x4]; |
e281682b SM |
4203 | u8 vport_number[0x10]; |
4204 | ||
b4ff3a36 | 4205 | u8 reserved_at_60[0x10]; |
e281682b SM |
4206 | u8 gid_index[0x10]; |
4207 | }; | |
4208 | ||
4209 | struct mlx5_ifc_query_hca_vport_context_out_bits { | |
4210 | u8 status[0x8]; | |
b4ff3a36 | 4211 | u8 reserved_at_8[0x18]; |
e281682b SM |
4212 | |
4213 | u8 syndrome[0x20]; | |
4214 | ||
b4ff3a36 | 4215 | u8 reserved_at_40[0x40]; |
e281682b SM |
4216 | |
4217 | struct mlx5_ifc_hca_vport_context_bits hca_vport_context; | |
4218 | }; | |
4219 | ||
4220 | struct mlx5_ifc_query_hca_vport_context_in_bits { | |
4221 | u8 opcode[0x10]; | |
b4ff3a36 | 4222 | u8 reserved_at_10[0x10]; |
e281682b | 4223 | |
b4ff3a36 | 4224 | u8 reserved_at_20[0x10]; |
e281682b SM |
4225 | u8 op_mod[0x10]; |
4226 | ||
4227 | u8 other_vport[0x1]; | |
b4ff3a36 | 4228 | u8 reserved_at_41[0xb]; |
707c4602 | 4229 | u8 port_num[0x4]; |
e281682b SM |
4230 | u8 vport_number[0x10]; |
4231 | ||
b4ff3a36 | 4232 | u8 reserved_at_60[0x20]; |
e281682b SM |
4233 | }; |
4234 | ||
4235 | struct mlx5_ifc_query_hca_cap_out_bits { | |
4236 | u8 status[0x8]; | |
b4ff3a36 | 4237 | u8 reserved_at_8[0x18]; |
e281682b SM |
4238 | |
4239 | u8 syndrome[0x20]; | |
4240 | ||
b4ff3a36 | 4241 | u8 reserved_at_40[0x40]; |
e281682b SM |
4242 | |
4243 | union mlx5_ifc_hca_cap_union_bits capability; | |
4244 | }; | |
4245 | ||
4246 | struct mlx5_ifc_query_hca_cap_in_bits { | |
4247 | u8 opcode[0x10]; | |
b4ff3a36 | 4248 | u8 reserved_at_10[0x10]; |
e281682b | 4249 | |
b4ff3a36 | 4250 | u8 reserved_at_20[0x10]; |
e281682b SM |
4251 | u8 op_mod[0x10]; |
4252 | ||
b4ff3a36 | 4253 | u8 reserved_at_40[0x40]; |
e281682b SM |
4254 | }; |
4255 | ||
4256 | struct mlx5_ifc_query_flow_table_out_bits { | |
4257 | u8 status[0x8]; | |
b4ff3a36 | 4258 | u8 reserved_at_8[0x18]; |
e281682b SM |
4259 | |
4260 | u8 syndrome[0x20]; | |
4261 | ||
b4ff3a36 | 4262 | u8 reserved_at_40[0x80]; |
e281682b | 4263 | |
b4ff3a36 | 4264 | u8 reserved_at_c0[0x8]; |
e281682b | 4265 | u8 level[0x8]; |
b4ff3a36 | 4266 | u8 reserved_at_d0[0x8]; |
e281682b SM |
4267 | u8 log_size[0x8]; |
4268 | ||
b4ff3a36 | 4269 | u8 reserved_at_e0[0x120]; |
e281682b SM |
4270 | }; |
4271 | ||
4272 | struct mlx5_ifc_query_flow_table_in_bits { | |
4273 | u8 opcode[0x10]; | |
b4ff3a36 | 4274 | u8 reserved_at_10[0x10]; |
e281682b | 4275 | |
b4ff3a36 | 4276 | u8 reserved_at_20[0x10]; |
e281682b SM |
4277 | u8 op_mod[0x10]; |
4278 | ||
b4ff3a36 | 4279 | u8 reserved_at_40[0x40]; |
e281682b SM |
4280 | |
4281 | u8 table_type[0x8]; | |
b4ff3a36 | 4282 | u8 reserved_at_88[0x18]; |
e281682b | 4283 | |
b4ff3a36 | 4284 | u8 reserved_at_a0[0x8]; |
e281682b SM |
4285 | u8 table_id[0x18]; |
4286 | ||
b4ff3a36 | 4287 | u8 reserved_at_c0[0x140]; |
e281682b SM |
4288 | }; |
4289 | ||
4290 | struct mlx5_ifc_query_fte_out_bits { | |
4291 | u8 status[0x8]; | |
b4ff3a36 | 4292 | u8 reserved_at_8[0x18]; |
e281682b SM |
4293 | |
4294 | u8 syndrome[0x20]; | |
4295 | ||
b4ff3a36 | 4296 | u8 reserved_at_40[0x1c0]; |
e281682b SM |
4297 | |
4298 | struct mlx5_ifc_flow_context_bits flow_context; | |
4299 | }; | |
4300 | ||
4301 | struct mlx5_ifc_query_fte_in_bits { | |
4302 | u8 opcode[0x10]; | |
b4ff3a36 | 4303 | u8 reserved_at_10[0x10]; |
e281682b | 4304 | |
b4ff3a36 | 4305 | u8 reserved_at_20[0x10]; |
e281682b SM |
4306 | u8 op_mod[0x10]; |
4307 | ||
b4ff3a36 | 4308 | u8 reserved_at_40[0x40]; |
e281682b SM |
4309 | |
4310 | u8 table_type[0x8]; | |
b4ff3a36 | 4311 | u8 reserved_at_88[0x18]; |
e281682b | 4312 | |
b4ff3a36 | 4313 | u8 reserved_at_a0[0x8]; |
e281682b SM |
4314 | u8 table_id[0x18]; |
4315 | ||
b4ff3a36 | 4316 | u8 reserved_at_c0[0x40]; |
e281682b SM |
4317 | |
4318 | u8 flow_index[0x20]; | |
4319 | ||
b4ff3a36 | 4320 | u8 reserved_at_120[0xe0]; |
e281682b SM |
4321 | }; |
4322 | ||
4323 | enum { | |
4324 | MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, | |
4325 | MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, | |
4326 | MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, | |
4327 | }; | |
4328 | ||
4329 | struct mlx5_ifc_query_flow_group_out_bits { | |
4330 | u8 status[0x8]; | |
b4ff3a36 | 4331 | u8 reserved_at_8[0x18]; |
e281682b SM |
4332 | |
4333 | u8 syndrome[0x20]; | |
4334 | ||
b4ff3a36 | 4335 | u8 reserved_at_40[0xa0]; |
e281682b SM |
4336 | |
4337 | u8 start_flow_index[0x20]; | |
4338 | ||
b4ff3a36 | 4339 | u8 reserved_at_100[0x20]; |
e281682b SM |
4340 | |
4341 | u8 end_flow_index[0x20]; | |
4342 | ||
b4ff3a36 | 4343 | u8 reserved_at_140[0xa0]; |
e281682b | 4344 | |
b4ff3a36 | 4345 | u8 reserved_at_1e0[0x18]; |
e281682b SM |
4346 | u8 match_criteria_enable[0x8]; |
4347 | ||
4348 | struct mlx5_ifc_fte_match_param_bits match_criteria; | |
4349 | ||
b4ff3a36 | 4350 | u8 reserved_at_1200[0xe00]; |
e281682b SM |
4351 | }; |
4352 | ||
4353 | struct mlx5_ifc_query_flow_group_in_bits { | |
4354 | u8 opcode[0x10]; | |
b4ff3a36 | 4355 | u8 reserved_at_10[0x10]; |
e281682b | 4356 | |
b4ff3a36 | 4357 | u8 reserved_at_20[0x10]; |
e281682b SM |
4358 | u8 op_mod[0x10]; |
4359 | ||
b4ff3a36 | 4360 | u8 reserved_at_40[0x40]; |
e281682b SM |
4361 | |
4362 | u8 table_type[0x8]; | |
b4ff3a36 | 4363 | u8 reserved_at_88[0x18]; |
e281682b | 4364 | |
b4ff3a36 | 4365 | u8 reserved_at_a0[0x8]; |
e281682b SM |
4366 | u8 table_id[0x18]; |
4367 | ||
4368 | u8 group_id[0x20]; | |
4369 | ||
b4ff3a36 | 4370 | u8 reserved_at_e0[0x120]; |
e281682b SM |
4371 | }; |
4372 | ||
9dc0b289 AV |
4373 | struct mlx5_ifc_query_flow_counter_out_bits { |
4374 | u8 status[0x8]; | |
4375 | u8 reserved_at_8[0x18]; | |
4376 | ||
4377 | u8 syndrome[0x20]; | |
4378 | ||
4379 | u8 reserved_at_40[0x40]; | |
4380 | ||
4381 | struct mlx5_ifc_traffic_counter_bits flow_statistics[0]; | |
4382 | }; | |
4383 | ||
4384 | struct mlx5_ifc_query_flow_counter_in_bits { | |
4385 | u8 opcode[0x10]; | |
4386 | u8 reserved_at_10[0x10]; | |
4387 | ||
4388 | u8 reserved_at_20[0x10]; | |
4389 | u8 op_mod[0x10]; | |
4390 | ||
4391 | u8 reserved_at_40[0x80]; | |
4392 | ||
4393 | u8 clear[0x1]; | |
4394 | u8 reserved_at_c1[0xf]; | |
4395 | u8 num_of_counters[0x10]; | |
4396 | ||
4397 | u8 reserved_at_e0[0x10]; | |
4398 | u8 flow_counter_id[0x10]; | |
4399 | }; | |
4400 | ||
d6666753 SM |
4401 | struct mlx5_ifc_query_esw_vport_context_out_bits { |
4402 | u8 status[0x8]; | |
b4ff3a36 | 4403 | u8 reserved_at_8[0x18]; |
d6666753 SM |
4404 | |
4405 | u8 syndrome[0x20]; | |
4406 | ||
b4ff3a36 | 4407 | u8 reserved_at_40[0x40]; |
d6666753 SM |
4408 | |
4409 | struct mlx5_ifc_esw_vport_context_bits esw_vport_context; | |
4410 | }; | |
4411 | ||
4412 | struct mlx5_ifc_query_esw_vport_context_in_bits { | |
4413 | u8 opcode[0x10]; | |
b4ff3a36 | 4414 | u8 reserved_at_10[0x10]; |
d6666753 | 4415 | |
b4ff3a36 | 4416 | u8 reserved_at_20[0x10]; |
d6666753 SM |
4417 | u8 op_mod[0x10]; |
4418 | ||
4419 | u8 other_vport[0x1]; | |
b4ff3a36 | 4420 | u8 reserved_at_41[0xf]; |
d6666753 SM |
4421 | u8 vport_number[0x10]; |
4422 | ||
b4ff3a36 | 4423 | u8 reserved_at_60[0x20]; |
d6666753 SM |
4424 | }; |
4425 | ||
4426 | struct mlx5_ifc_modify_esw_vport_context_out_bits { | |
4427 | u8 status[0x8]; | |
b4ff3a36 | 4428 | u8 reserved_at_8[0x18]; |
d6666753 SM |
4429 | |
4430 | u8 syndrome[0x20]; | |
4431 | ||
b4ff3a36 | 4432 | u8 reserved_at_40[0x40]; |
d6666753 SM |
4433 | }; |
4434 | ||
4435 | struct mlx5_ifc_esw_vport_context_fields_select_bits { | |
b4ff3a36 | 4436 | u8 reserved_at_0[0x1c]; |
d6666753 SM |
4437 | u8 vport_cvlan_insert[0x1]; |
4438 | u8 vport_svlan_insert[0x1]; | |
4439 | u8 vport_cvlan_strip[0x1]; | |
4440 | u8 vport_svlan_strip[0x1]; | |
4441 | }; | |
4442 | ||
4443 | struct mlx5_ifc_modify_esw_vport_context_in_bits { | |
4444 | u8 opcode[0x10]; | |
b4ff3a36 | 4445 | u8 reserved_at_10[0x10]; |
d6666753 | 4446 | |
b4ff3a36 | 4447 | u8 reserved_at_20[0x10]; |
d6666753 SM |
4448 | u8 op_mod[0x10]; |
4449 | ||
4450 | u8 other_vport[0x1]; | |
b4ff3a36 | 4451 | u8 reserved_at_41[0xf]; |
d6666753 SM |
4452 | u8 vport_number[0x10]; |
4453 | ||
4454 | struct mlx5_ifc_esw_vport_context_fields_select_bits field_select; | |
4455 | ||
4456 | struct mlx5_ifc_esw_vport_context_bits esw_vport_context; | |
4457 | }; | |
4458 | ||
e281682b SM |
4459 | struct mlx5_ifc_query_eq_out_bits { |
4460 | u8 status[0x8]; | |
b4ff3a36 | 4461 | u8 reserved_at_8[0x18]; |
e281682b SM |
4462 | |
4463 | u8 syndrome[0x20]; | |
4464 | ||
b4ff3a36 | 4465 | u8 reserved_at_40[0x40]; |
e281682b SM |
4466 | |
4467 | struct mlx5_ifc_eqc_bits eq_context_entry; | |
4468 | ||
b4ff3a36 | 4469 | u8 reserved_at_280[0x40]; |
e281682b SM |
4470 | |
4471 | u8 event_bitmask[0x40]; | |
4472 | ||
b4ff3a36 | 4473 | u8 reserved_at_300[0x580]; |
e281682b SM |
4474 | |
4475 | u8 pas[0][0x40]; | |
4476 | }; | |
4477 | ||
4478 | struct mlx5_ifc_query_eq_in_bits { | |
4479 | u8 opcode[0x10]; | |
b4ff3a36 | 4480 | u8 reserved_at_10[0x10]; |
e281682b | 4481 | |
b4ff3a36 | 4482 | u8 reserved_at_20[0x10]; |
e281682b SM |
4483 | u8 op_mod[0x10]; |
4484 | ||
b4ff3a36 | 4485 | u8 reserved_at_40[0x18]; |
e281682b SM |
4486 | u8 eq_number[0x8]; |
4487 | ||
b4ff3a36 | 4488 | u8 reserved_at_60[0x20]; |
e281682b SM |
4489 | }; |
4490 | ||
7adbde20 HHZ |
4491 | struct mlx5_ifc_encap_header_in_bits { |
4492 | u8 reserved_at_0[0x5]; | |
4493 | u8 header_type[0x3]; | |
4494 | u8 reserved_at_8[0xe]; | |
4495 | u8 encap_header_size[0xa]; | |
4496 | ||
4497 | u8 reserved_at_20[0x10]; | |
4498 | u8 encap_header[2][0x8]; | |
4499 | ||
4500 | u8 more_encap_header[0][0x8]; | |
4501 | }; | |
4502 | ||
4503 | struct mlx5_ifc_query_encap_header_out_bits { | |
4504 | u8 status[0x8]; | |
4505 | u8 reserved_at_8[0x18]; | |
4506 | ||
4507 | u8 syndrome[0x20]; | |
4508 | ||
4509 | u8 reserved_at_40[0xa0]; | |
4510 | ||
4511 | struct mlx5_ifc_encap_header_in_bits encap_header[0]; | |
4512 | }; | |
4513 | ||
4514 | struct mlx5_ifc_query_encap_header_in_bits { | |
4515 | u8 opcode[0x10]; | |
4516 | u8 reserved_at_10[0x10]; | |
4517 | ||
4518 | u8 reserved_at_20[0x10]; | |
4519 | u8 op_mod[0x10]; | |
4520 | ||
4521 | u8 encap_id[0x20]; | |
4522 | ||
4523 | u8 reserved_at_60[0xa0]; | |
4524 | }; | |
4525 | ||
4526 | struct mlx5_ifc_alloc_encap_header_out_bits { | |
4527 | u8 status[0x8]; | |
4528 | u8 reserved_at_8[0x18]; | |
4529 | ||
4530 | u8 syndrome[0x20]; | |
4531 | ||
4532 | u8 encap_id[0x20]; | |
4533 | ||
4534 | u8 reserved_at_60[0x20]; | |
4535 | }; | |
4536 | ||
4537 | struct mlx5_ifc_alloc_encap_header_in_bits { | |
4538 | u8 opcode[0x10]; | |
4539 | u8 reserved_at_10[0x10]; | |
4540 | ||
4541 | u8 reserved_at_20[0x10]; | |
4542 | u8 op_mod[0x10]; | |
4543 | ||
4544 | u8 reserved_at_40[0xa0]; | |
4545 | ||
4546 | struct mlx5_ifc_encap_header_in_bits encap_header; | |
4547 | }; | |
4548 | ||
4549 | struct mlx5_ifc_dealloc_encap_header_out_bits { | |
4550 | u8 status[0x8]; | |
4551 | u8 reserved_at_8[0x18]; | |
4552 | ||
4553 | u8 syndrome[0x20]; | |
4554 | ||
4555 | u8 reserved_at_40[0x40]; | |
4556 | }; | |
4557 | ||
4558 | struct mlx5_ifc_dealloc_encap_header_in_bits { | |
4559 | u8 opcode[0x10]; | |
4560 | u8 reserved_at_10[0x10]; | |
4561 | ||
4562 | u8 reserved_20[0x10]; | |
4563 | u8 op_mod[0x10]; | |
4564 | ||
4565 | u8 encap_id[0x20]; | |
4566 | ||
4567 | u8 reserved_60[0x20]; | |
4568 | }; | |
4569 | ||
2a69cb9f OG |
4570 | struct mlx5_ifc_set_action_in_bits { |
4571 | u8 action_type[0x4]; | |
4572 | u8 field[0xc]; | |
4573 | u8 reserved_at_10[0x3]; | |
4574 | u8 offset[0x5]; | |
4575 | u8 reserved_at_18[0x3]; | |
4576 | u8 length[0x5]; | |
4577 | ||
4578 | u8 data[0x20]; | |
4579 | }; | |
4580 | ||
4581 | struct mlx5_ifc_add_action_in_bits { | |
4582 | u8 action_type[0x4]; | |
4583 | u8 field[0xc]; | |
4584 | u8 reserved_at_10[0x10]; | |
4585 | ||
4586 | u8 data[0x20]; | |
4587 | }; | |
4588 | ||
4589 | union mlx5_ifc_set_action_in_add_action_in_auto_bits { | |
4590 | struct mlx5_ifc_set_action_in_bits set_action_in; | |
4591 | struct mlx5_ifc_add_action_in_bits add_action_in; | |
4592 | u8 reserved_at_0[0x40]; | |
4593 | }; | |
4594 | ||
4595 | enum { | |
4596 | MLX5_ACTION_TYPE_SET = 0x1, | |
4597 | MLX5_ACTION_TYPE_ADD = 0x2, | |
4598 | }; | |
4599 | ||
4600 | enum { | |
4601 | MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1, | |
4602 | MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2, | |
4603 | MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3, | |
4604 | MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4, | |
4605 | MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5, | |
4606 | MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6, | |
4607 | MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7, | |
4608 | MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8, | |
4609 | MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9, | |
4610 | MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa, | |
4611 | MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb, | |
4612 | MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc, | |
4613 | MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd, | |
4614 | MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe, | |
4615 | MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf, | |
4616 | MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10, | |
4617 | MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11, | |
4618 | MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12, | |
4619 | MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13, | |
4620 | MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14, | |
4621 | MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15, | |
4622 | MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16, | |
0c0316f5 | 4623 | MLX5_ACTION_IN_FIELD_OUT_IPV6_HOPLIMIT = 0x47, |
2a69cb9f OG |
4624 | }; |
4625 | ||
4626 | struct mlx5_ifc_alloc_modify_header_context_out_bits { | |
4627 | u8 status[0x8]; | |
4628 | u8 reserved_at_8[0x18]; | |
4629 | ||
4630 | u8 syndrome[0x20]; | |
4631 | ||
4632 | u8 modify_header_id[0x20]; | |
4633 | ||
4634 | u8 reserved_at_60[0x20]; | |
4635 | }; | |
4636 | ||
4637 | struct mlx5_ifc_alloc_modify_header_context_in_bits { | |
4638 | u8 opcode[0x10]; | |
4639 | u8 reserved_at_10[0x10]; | |
4640 | ||
4641 | u8 reserved_at_20[0x10]; | |
4642 | u8 op_mod[0x10]; | |
4643 | ||
4644 | u8 reserved_at_40[0x20]; | |
4645 | ||
4646 | u8 table_type[0x8]; | |
4647 | u8 reserved_at_68[0x10]; | |
4648 | u8 num_of_actions[0x8]; | |
4649 | ||
4650 | union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0]; | |
4651 | }; | |
4652 | ||
4653 | struct mlx5_ifc_dealloc_modify_header_context_out_bits { | |
4654 | u8 status[0x8]; | |
4655 | u8 reserved_at_8[0x18]; | |
4656 | ||
4657 | u8 syndrome[0x20]; | |
4658 | ||
4659 | u8 reserved_at_40[0x40]; | |
4660 | }; | |
4661 | ||
4662 | struct mlx5_ifc_dealloc_modify_header_context_in_bits { | |
4663 | u8 opcode[0x10]; | |
4664 | u8 reserved_at_10[0x10]; | |
4665 | ||
4666 | u8 reserved_at_20[0x10]; | |
4667 | u8 op_mod[0x10]; | |
4668 | ||
4669 | u8 modify_header_id[0x20]; | |
4670 | ||
4671 | u8 reserved_at_60[0x20]; | |
4672 | }; | |
4673 | ||
e281682b SM |
4674 | struct mlx5_ifc_query_dct_out_bits { |
4675 | u8 status[0x8]; | |
b4ff3a36 | 4676 | u8 reserved_at_8[0x18]; |
e281682b SM |
4677 | |
4678 | u8 syndrome[0x20]; | |
4679 | ||
b4ff3a36 | 4680 | u8 reserved_at_40[0x40]; |
e281682b SM |
4681 | |
4682 | struct mlx5_ifc_dctc_bits dct_context_entry; | |
4683 | ||
b4ff3a36 | 4684 | u8 reserved_at_280[0x180]; |
e281682b SM |
4685 | }; |
4686 | ||
4687 | struct mlx5_ifc_query_dct_in_bits { | |
4688 | u8 opcode[0x10]; | |
b4ff3a36 | 4689 | u8 reserved_at_10[0x10]; |
e281682b | 4690 | |
b4ff3a36 | 4691 | u8 reserved_at_20[0x10]; |
e281682b SM |
4692 | u8 op_mod[0x10]; |
4693 | ||
b4ff3a36 | 4694 | u8 reserved_at_40[0x8]; |
e281682b SM |
4695 | u8 dctn[0x18]; |
4696 | ||
b4ff3a36 | 4697 | u8 reserved_at_60[0x20]; |
e281682b SM |
4698 | }; |
4699 | ||
4700 | struct mlx5_ifc_query_cq_out_bits { | |
4701 | u8 status[0x8]; | |
b4ff3a36 | 4702 | u8 reserved_at_8[0x18]; |
e281682b SM |
4703 | |
4704 | u8 syndrome[0x20]; | |
4705 | ||
b4ff3a36 | 4706 | u8 reserved_at_40[0x40]; |
e281682b SM |
4707 | |
4708 | struct mlx5_ifc_cqc_bits cq_context; | |
4709 | ||
b4ff3a36 | 4710 | u8 reserved_at_280[0x600]; |
e281682b SM |
4711 | |
4712 | u8 pas[0][0x40]; | |
4713 | }; | |
4714 | ||
4715 | struct mlx5_ifc_query_cq_in_bits { | |
4716 | u8 opcode[0x10]; | |
b4ff3a36 | 4717 | u8 reserved_at_10[0x10]; |
e281682b | 4718 | |
b4ff3a36 | 4719 | u8 reserved_at_20[0x10]; |
e281682b SM |
4720 | u8 op_mod[0x10]; |
4721 | ||
b4ff3a36 | 4722 | u8 reserved_at_40[0x8]; |
e281682b SM |
4723 | u8 cqn[0x18]; |
4724 | ||
b4ff3a36 | 4725 | u8 reserved_at_60[0x20]; |
e281682b SM |
4726 | }; |
4727 | ||
4728 | struct mlx5_ifc_query_cong_status_out_bits { | |
4729 | u8 status[0x8]; | |
b4ff3a36 | 4730 | u8 reserved_at_8[0x18]; |
e281682b SM |
4731 | |
4732 | u8 syndrome[0x20]; | |
4733 | ||
b4ff3a36 | 4734 | u8 reserved_at_40[0x20]; |
e281682b SM |
4735 | |
4736 | u8 enable[0x1]; | |
4737 | u8 tag_enable[0x1]; | |
b4ff3a36 | 4738 | u8 reserved_at_62[0x1e]; |
e281682b SM |
4739 | }; |
4740 | ||
4741 | struct mlx5_ifc_query_cong_status_in_bits { | |
4742 | u8 opcode[0x10]; | |
b4ff3a36 | 4743 | u8 reserved_at_10[0x10]; |
e281682b | 4744 | |
b4ff3a36 | 4745 | u8 reserved_at_20[0x10]; |
e281682b SM |
4746 | u8 op_mod[0x10]; |
4747 | ||
b4ff3a36 | 4748 | u8 reserved_at_40[0x18]; |
e281682b SM |
4749 | u8 priority[0x4]; |
4750 | u8 cong_protocol[0x4]; | |
4751 | ||
b4ff3a36 | 4752 | u8 reserved_at_60[0x20]; |
e281682b SM |
4753 | }; |
4754 | ||
4755 | struct mlx5_ifc_query_cong_statistics_out_bits { | |
4756 | u8 status[0x8]; | |
b4ff3a36 | 4757 | u8 reserved_at_8[0x18]; |
e281682b SM |
4758 | |
4759 | u8 syndrome[0x20]; | |
4760 | ||
b4ff3a36 | 4761 | u8 reserved_at_40[0x40]; |
e281682b | 4762 | |
e1f24a79 | 4763 | u8 rp_cur_flows[0x20]; |
e281682b SM |
4764 | |
4765 | u8 sum_flows[0x20]; | |
4766 | ||
e1f24a79 | 4767 | u8 rp_cnp_ignored_high[0x20]; |
e281682b | 4768 | |
e1f24a79 | 4769 | u8 rp_cnp_ignored_low[0x20]; |
e281682b | 4770 | |
e1f24a79 | 4771 | u8 rp_cnp_handled_high[0x20]; |
e281682b | 4772 | |
e1f24a79 | 4773 | u8 rp_cnp_handled_low[0x20]; |
e281682b | 4774 | |
b4ff3a36 | 4775 | u8 reserved_at_140[0x100]; |
e281682b SM |
4776 | |
4777 | u8 time_stamp_high[0x20]; | |
4778 | ||
4779 | u8 time_stamp_low[0x20]; | |
4780 | ||
4781 | u8 accumulators_period[0x20]; | |
4782 | ||
e1f24a79 | 4783 | u8 np_ecn_marked_roce_packets_high[0x20]; |
e281682b | 4784 | |
e1f24a79 | 4785 | u8 np_ecn_marked_roce_packets_low[0x20]; |
e281682b | 4786 | |
e1f24a79 | 4787 | u8 np_cnp_sent_high[0x20]; |
e281682b | 4788 | |
e1f24a79 | 4789 | u8 np_cnp_sent_low[0x20]; |
e281682b | 4790 | |
b4ff3a36 | 4791 | u8 reserved_at_320[0x560]; |
e281682b SM |
4792 | }; |
4793 | ||
4794 | struct mlx5_ifc_query_cong_statistics_in_bits { | |
4795 | u8 opcode[0x10]; | |
b4ff3a36 | 4796 | u8 reserved_at_10[0x10]; |
e281682b | 4797 | |
b4ff3a36 | 4798 | u8 reserved_at_20[0x10]; |
e281682b SM |
4799 | u8 op_mod[0x10]; |
4800 | ||
4801 | u8 clear[0x1]; | |
b4ff3a36 | 4802 | u8 reserved_at_41[0x1f]; |
e281682b | 4803 | |
b4ff3a36 | 4804 | u8 reserved_at_60[0x20]; |
e281682b SM |
4805 | }; |
4806 | ||
4807 | struct mlx5_ifc_query_cong_params_out_bits { | |
4808 | u8 status[0x8]; | |
b4ff3a36 | 4809 | u8 reserved_at_8[0x18]; |
e281682b SM |
4810 | |
4811 | u8 syndrome[0x20]; | |
4812 | ||
b4ff3a36 | 4813 | u8 reserved_at_40[0x40]; |
e281682b SM |
4814 | |
4815 | union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; | |
4816 | }; | |
4817 | ||
4818 | struct mlx5_ifc_query_cong_params_in_bits { | |
4819 | u8 opcode[0x10]; | |
b4ff3a36 | 4820 | u8 reserved_at_10[0x10]; |
e281682b | 4821 | |
b4ff3a36 | 4822 | u8 reserved_at_20[0x10]; |
e281682b SM |
4823 | u8 op_mod[0x10]; |
4824 | ||
b4ff3a36 | 4825 | u8 reserved_at_40[0x1c]; |
e281682b SM |
4826 | u8 cong_protocol[0x4]; |
4827 | ||
b4ff3a36 | 4828 | u8 reserved_at_60[0x20]; |
e281682b SM |
4829 | }; |
4830 | ||
4831 | struct mlx5_ifc_query_adapter_out_bits { | |
4832 | u8 status[0x8]; | |
b4ff3a36 | 4833 | u8 reserved_at_8[0x18]; |
e281682b SM |
4834 | |
4835 | u8 syndrome[0x20]; | |
4836 | ||
b4ff3a36 | 4837 | u8 reserved_at_40[0x40]; |
e281682b SM |
4838 | |
4839 | struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct; | |
4840 | }; | |
4841 | ||
4842 | struct mlx5_ifc_query_adapter_in_bits { | |
4843 | u8 opcode[0x10]; | |
b4ff3a36 | 4844 | u8 reserved_at_10[0x10]; |
e281682b | 4845 | |
b4ff3a36 | 4846 | u8 reserved_at_20[0x10]; |
e281682b SM |
4847 | u8 op_mod[0x10]; |
4848 | ||
b4ff3a36 | 4849 | u8 reserved_at_40[0x40]; |
e281682b SM |
4850 | }; |
4851 | ||
4852 | struct mlx5_ifc_qp_2rst_out_bits { | |
4853 | u8 status[0x8]; | |
b4ff3a36 | 4854 | u8 reserved_at_8[0x18]; |
e281682b SM |
4855 | |
4856 | u8 syndrome[0x20]; | |
4857 | ||
b4ff3a36 | 4858 | u8 reserved_at_40[0x40]; |
e281682b SM |
4859 | }; |
4860 | ||
4861 | struct mlx5_ifc_qp_2rst_in_bits { | |
4862 | u8 opcode[0x10]; | |
b4ff3a36 | 4863 | u8 reserved_at_10[0x10]; |
e281682b | 4864 | |
b4ff3a36 | 4865 | u8 reserved_at_20[0x10]; |
e281682b SM |
4866 | u8 op_mod[0x10]; |
4867 | ||
b4ff3a36 | 4868 | u8 reserved_at_40[0x8]; |
e281682b SM |
4869 | u8 qpn[0x18]; |
4870 | ||
b4ff3a36 | 4871 | u8 reserved_at_60[0x20]; |
e281682b SM |
4872 | }; |
4873 | ||
4874 | struct mlx5_ifc_qp_2err_out_bits { | |
4875 | u8 status[0x8]; | |
b4ff3a36 | 4876 | u8 reserved_at_8[0x18]; |
e281682b SM |
4877 | |
4878 | u8 syndrome[0x20]; | |
4879 | ||
b4ff3a36 | 4880 | u8 reserved_at_40[0x40]; |
e281682b SM |
4881 | }; |
4882 | ||
4883 | struct mlx5_ifc_qp_2err_in_bits { | |
4884 | u8 opcode[0x10]; | |
b4ff3a36 | 4885 | u8 reserved_at_10[0x10]; |
e281682b | 4886 | |
b4ff3a36 | 4887 | u8 reserved_at_20[0x10]; |
e281682b SM |
4888 | u8 op_mod[0x10]; |
4889 | ||
b4ff3a36 | 4890 | u8 reserved_at_40[0x8]; |
e281682b SM |
4891 | u8 qpn[0x18]; |
4892 | ||
b4ff3a36 | 4893 | u8 reserved_at_60[0x20]; |
e281682b SM |
4894 | }; |
4895 | ||
4896 | struct mlx5_ifc_page_fault_resume_out_bits { | |
4897 | u8 status[0x8]; | |
b4ff3a36 | 4898 | u8 reserved_at_8[0x18]; |
e281682b SM |
4899 | |
4900 | u8 syndrome[0x20]; | |
4901 | ||
b4ff3a36 | 4902 | u8 reserved_at_40[0x40]; |
e281682b SM |
4903 | }; |
4904 | ||
4905 | struct mlx5_ifc_page_fault_resume_in_bits { | |
4906 | u8 opcode[0x10]; | |
b4ff3a36 | 4907 | u8 reserved_at_10[0x10]; |
e281682b | 4908 | |
b4ff3a36 | 4909 | u8 reserved_at_20[0x10]; |
e281682b SM |
4910 | u8 op_mod[0x10]; |
4911 | ||
4912 | u8 error[0x1]; | |
b4ff3a36 | 4913 | u8 reserved_at_41[0x4]; |
223cdc72 AK |
4914 | u8 page_fault_type[0x3]; |
4915 | u8 wq_number[0x18]; | |
e281682b | 4916 | |
223cdc72 AK |
4917 | u8 reserved_at_60[0x8]; |
4918 | u8 token[0x18]; | |
e281682b SM |
4919 | }; |
4920 | ||
4921 | struct mlx5_ifc_nop_out_bits { | |
4922 | u8 status[0x8]; | |
b4ff3a36 | 4923 | u8 reserved_at_8[0x18]; |
e281682b SM |
4924 | |
4925 | u8 syndrome[0x20]; | |
4926 | ||
b4ff3a36 | 4927 | u8 reserved_at_40[0x40]; |
e281682b SM |
4928 | }; |
4929 | ||
4930 | struct mlx5_ifc_nop_in_bits { | |
4931 | u8 opcode[0x10]; | |
b4ff3a36 | 4932 | u8 reserved_at_10[0x10]; |
e281682b | 4933 | |
b4ff3a36 | 4934 | u8 reserved_at_20[0x10]; |
e281682b SM |
4935 | u8 op_mod[0x10]; |
4936 | ||
b4ff3a36 | 4937 | u8 reserved_at_40[0x40]; |
e281682b SM |
4938 | }; |
4939 | ||
4940 | struct mlx5_ifc_modify_vport_state_out_bits { | |
4941 | u8 status[0x8]; | |
b4ff3a36 | 4942 | u8 reserved_at_8[0x18]; |
e281682b SM |
4943 | |
4944 | u8 syndrome[0x20]; | |
4945 | ||
b4ff3a36 | 4946 | u8 reserved_at_40[0x40]; |
e281682b SM |
4947 | }; |
4948 | ||
4949 | struct mlx5_ifc_modify_vport_state_in_bits { | |
4950 | u8 opcode[0x10]; | |
b4ff3a36 | 4951 | u8 reserved_at_10[0x10]; |
e281682b | 4952 | |
b4ff3a36 | 4953 | u8 reserved_at_20[0x10]; |
e281682b SM |
4954 | u8 op_mod[0x10]; |
4955 | ||
4956 | u8 other_vport[0x1]; | |
b4ff3a36 | 4957 | u8 reserved_at_41[0xf]; |
e281682b SM |
4958 | u8 vport_number[0x10]; |
4959 | ||
b4ff3a36 | 4960 | u8 reserved_at_60[0x18]; |
e281682b | 4961 | u8 admin_state[0x4]; |
b4ff3a36 | 4962 | u8 reserved_at_7c[0x4]; |
e281682b SM |
4963 | }; |
4964 | ||
4965 | struct mlx5_ifc_modify_tis_out_bits { | |
4966 | u8 status[0x8]; | |
b4ff3a36 | 4967 | u8 reserved_at_8[0x18]; |
e281682b SM |
4968 | |
4969 | u8 syndrome[0x20]; | |
4970 | ||
b4ff3a36 | 4971 | u8 reserved_at_40[0x40]; |
e281682b SM |
4972 | }; |
4973 | ||
75850d0b | 4974 | struct mlx5_ifc_modify_tis_bitmask_bits { |
b4ff3a36 | 4975 | u8 reserved_at_0[0x20]; |
75850d0b | 4976 | |
84df61eb AH |
4977 | u8 reserved_at_20[0x1d]; |
4978 | u8 lag_tx_port_affinity[0x1]; | |
4979 | u8 strict_lag_tx_port_affinity[0x1]; | |
75850d0b | 4980 | u8 prio[0x1]; |
4981 | }; | |
4982 | ||
e281682b SM |
4983 | struct mlx5_ifc_modify_tis_in_bits { |
4984 | u8 opcode[0x10]; | |
b4ff3a36 | 4985 | u8 reserved_at_10[0x10]; |
e281682b | 4986 | |
b4ff3a36 | 4987 | u8 reserved_at_20[0x10]; |
e281682b SM |
4988 | u8 op_mod[0x10]; |
4989 | ||
b4ff3a36 | 4990 | u8 reserved_at_40[0x8]; |
e281682b SM |
4991 | u8 tisn[0x18]; |
4992 | ||
b4ff3a36 | 4993 | u8 reserved_at_60[0x20]; |
e281682b | 4994 | |
75850d0b | 4995 | struct mlx5_ifc_modify_tis_bitmask_bits bitmask; |
e281682b | 4996 | |
b4ff3a36 | 4997 | u8 reserved_at_c0[0x40]; |
e281682b SM |
4998 | |
4999 | struct mlx5_ifc_tisc_bits ctx; | |
5000 | }; | |
5001 | ||
d9eea403 | 5002 | struct mlx5_ifc_modify_tir_bitmask_bits { |
b4ff3a36 | 5003 | u8 reserved_at_0[0x20]; |
d9eea403 | 5004 | |
b4ff3a36 | 5005 | u8 reserved_at_20[0x1b]; |
66189961 | 5006 | u8 self_lb_en[0x1]; |
bdfc028d TT |
5007 | u8 reserved_at_3c[0x1]; |
5008 | u8 hash[0x1]; | |
5009 | u8 reserved_at_3e[0x1]; | |
d9eea403 AS |
5010 | u8 lro[0x1]; |
5011 | }; | |
5012 | ||
e281682b SM |
5013 | struct mlx5_ifc_modify_tir_out_bits { |
5014 | u8 status[0x8]; | |
b4ff3a36 | 5015 | u8 reserved_at_8[0x18]; |
e281682b SM |
5016 | |
5017 | u8 syndrome[0x20]; | |
5018 | ||
b4ff3a36 | 5019 | u8 reserved_at_40[0x40]; |
e281682b SM |
5020 | }; |
5021 | ||
5022 | struct mlx5_ifc_modify_tir_in_bits { | |
5023 | u8 opcode[0x10]; | |
b4ff3a36 | 5024 | u8 reserved_at_10[0x10]; |
e281682b | 5025 | |
b4ff3a36 | 5026 | u8 reserved_at_20[0x10]; |
e281682b SM |
5027 | u8 op_mod[0x10]; |
5028 | ||
b4ff3a36 | 5029 | u8 reserved_at_40[0x8]; |
e281682b SM |
5030 | u8 tirn[0x18]; |
5031 | ||
b4ff3a36 | 5032 | u8 reserved_at_60[0x20]; |
e281682b | 5033 | |
d9eea403 | 5034 | struct mlx5_ifc_modify_tir_bitmask_bits bitmask; |
e281682b | 5035 | |
b4ff3a36 | 5036 | u8 reserved_at_c0[0x40]; |
e281682b SM |
5037 | |
5038 | struct mlx5_ifc_tirc_bits ctx; | |
5039 | }; | |
5040 | ||
5041 | struct mlx5_ifc_modify_sq_out_bits { | |
5042 | u8 status[0x8]; | |
b4ff3a36 | 5043 | u8 reserved_at_8[0x18]; |
e281682b SM |
5044 | |
5045 | u8 syndrome[0x20]; | |
5046 | ||
b4ff3a36 | 5047 | u8 reserved_at_40[0x40]; |
e281682b SM |
5048 | }; |
5049 | ||
5050 | struct mlx5_ifc_modify_sq_in_bits { | |
5051 | u8 opcode[0x10]; | |
b4ff3a36 | 5052 | u8 reserved_at_10[0x10]; |
e281682b | 5053 | |
b4ff3a36 | 5054 | u8 reserved_at_20[0x10]; |
e281682b SM |
5055 | u8 op_mod[0x10]; |
5056 | ||
5057 | u8 sq_state[0x4]; | |
b4ff3a36 | 5058 | u8 reserved_at_44[0x4]; |
e281682b SM |
5059 | u8 sqn[0x18]; |
5060 | ||
b4ff3a36 | 5061 | u8 reserved_at_60[0x20]; |
e281682b SM |
5062 | |
5063 | u8 modify_bitmask[0x40]; | |
5064 | ||
b4ff3a36 | 5065 | u8 reserved_at_c0[0x40]; |
e281682b SM |
5066 | |
5067 | struct mlx5_ifc_sqc_bits ctx; | |
5068 | }; | |
5069 | ||
813f8540 MHY |
5070 | struct mlx5_ifc_modify_scheduling_element_out_bits { |
5071 | u8 status[0x8]; | |
5072 | u8 reserved_at_8[0x18]; | |
5073 | ||
5074 | u8 syndrome[0x20]; | |
5075 | ||
5076 | u8 reserved_at_40[0x1c0]; | |
5077 | }; | |
5078 | ||
5079 | enum { | |
5080 | MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1, | |
5081 | MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2, | |
5082 | }; | |
5083 | ||
5084 | struct mlx5_ifc_modify_scheduling_element_in_bits { | |
5085 | u8 opcode[0x10]; | |
5086 | u8 reserved_at_10[0x10]; | |
5087 | ||
5088 | u8 reserved_at_20[0x10]; | |
5089 | u8 op_mod[0x10]; | |
5090 | ||
5091 | u8 scheduling_hierarchy[0x8]; | |
5092 | u8 reserved_at_48[0x18]; | |
5093 | ||
5094 | u8 scheduling_element_id[0x20]; | |
5095 | ||
5096 | u8 reserved_at_80[0x20]; | |
5097 | ||
5098 | u8 modify_bitmask[0x20]; | |
5099 | ||
5100 | u8 reserved_at_c0[0x40]; | |
5101 | ||
5102 | struct mlx5_ifc_scheduling_context_bits scheduling_context; | |
5103 | ||
5104 | u8 reserved_at_300[0x100]; | |
5105 | }; | |
5106 | ||
e281682b SM |
5107 | struct mlx5_ifc_modify_rqt_out_bits { |
5108 | u8 status[0x8]; | |
b4ff3a36 | 5109 | u8 reserved_at_8[0x18]; |
e281682b SM |
5110 | |
5111 | u8 syndrome[0x20]; | |
5112 | ||
b4ff3a36 | 5113 | u8 reserved_at_40[0x40]; |
e281682b SM |
5114 | }; |
5115 | ||
5c50368f | 5116 | struct mlx5_ifc_rqt_bitmask_bits { |
b4ff3a36 | 5117 | u8 reserved_at_0[0x20]; |
5c50368f | 5118 | |
b4ff3a36 | 5119 | u8 reserved_at_20[0x1f]; |
5c50368f AS |
5120 | u8 rqn_list[0x1]; |
5121 | }; | |
5122 | ||
e281682b SM |
5123 | struct mlx5_ifc_modify_rqt_in_bits { |
5124 | u8 opcode[0x10]; | |
b4ff3a36 | 5125 | u8 reserved_at_10[0x10]; |
e281682b | 5126 | |
b4ff3a36 | 5127 | u8 reserved_at_20[0x10]; |
e281682b SM |
5128 | u8 op_mod[0x10]; |
5129 | ||
b4ff3a36 | 5130 | u8 reserved_at_40[0x8]; |
e281682b SM |
5131 | u8 rqtn[0x18]; |
5132 | ||
b4ff3a36 | 5133 | u8 reserved_at_60[0x20]; |
e281682b | 5134 | |
5c50368f | 5135 | struct mlx5_ifc_rqt_bitmask_bits bitmask; |
e281682b | 5136 | |
b4ff3a36 | 5137 | u8 reserved_at_c0[0x40]; |
e281682b SM |
5138 | |
5139 | struct mlx5_ifc_rqtc_bits ctx; | |
5140 | }; | |
5141 | ||
5142 | struct mlx5_ifc_modify_rq_out_bits { | |
5143 | u8 status[0x8]; | |
b4ff3a36 | 5144 | u8 reserved_at_8[0x18]; |
e281682b SM |
5145 | |
5146 | u8 syndrome[0x20]; | |
5147 | ||
b4ff3a36 | 5148 | u8 reserved_at_40[0x40]; |
e281682b SM |
5149 | }; |
5150 | ||
83b502a1 AV |
5151 | enum { |
5152 | MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1, | |
102722fc | 5153 | MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2, |
23a6964e | 5154 | MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3, |
83b502a1 AV |
5155 | }; |
5156 | ||
e281682b SM |
5157 | struct mlx5_ifc_modify_rq_in_bits { |
5158 | u8 opcode[0x10]; | |
b4ff3a36 | 5159 | u8 reserved_at_10[0x10]; |
e281682b | 5160 | |
b4ff3a36 | 5161 | u8 reserved_at_20[0x10]; |
e281682b SM |
5162 | u8 op_mod[0x10]; |
5163 | ||
5164 | u8 rq_state[0x4]; | |
b4ff3a36 | 5165 | u8 reserved_at_44[0x4]; |
e281682b SM |
5166 | u8 rqn[0x18]; |
5167 | ||
b4ff3a36 | 5168 | u8 reserved_at_60[0x20]; |
e281682b SM |
5169 | |
5170 | u8 modify_bitmask[0x40]; | |
5171 | ||
b4ff3a36 | 5172 | u8 reserved_at_c0[0x40]; |
e281682b SM |
5173 | |
5174 | struct mlx5_ifc_rqc_bits ctx; | |
5175 | }; | |
5176 | ||
5177 | struct mlx5_ifc_modify_rmp_out_bits { | |
5178 | u8 status[0x8]; | |
b4ff3a36 | 5179 | u8 reserved_at_8[0x18]; |
e281682b SM |
5180 | |
5181 | u8 syndrome[0x20]; | |
5182 | ||
b4ff3a36 | 5183 | u8 reserved_at_40[0x40]; |
e281682b SM |
5184 | }; |
5185 | ||
01949d01 | 5186 | struct mlx5_ifc_rmp_bitmask_bits { |
b4ff3a36 | 5187 | u8 reserved_at_0[0x20]; |
01949d01 | 5188 | |
b4ff3a36 | 5189 | u8 reserved_at_20[0x1f]; |
01949d01 HA |
5190 | u8 lwm[0x1]; |
5191 | }; | |
5192 | ||
e281682b SM |
5193 | struct mlx5_ifc_modify_rmp_in_bits { |
5194 | u8 opcode[0x10]; | |
b4ff3a36 | 5195 | u8 reserved_at_10[0x10]; |
e281682b | 5196 | |
b4ff3a36 | 5197 | u8 reserved_at_20[0x10]; |
e281682b SM |
5198 | u8 op_mod[0x10]; |
5199 | ||
5200 | u8 rmp_state[0x4]; | |
b4ff3a36 | 5201 | u8 reserved_at_44[0x4]; |
e281682b SM |
5202 | u8 rmpn[0x18]; |
5203 | ||
b4ff3a36 | 5204 | u8 reserved_at_60[0x20]; |
e281682b | 5205 | |
01949d01 | 5206 | struct mlx5_ifc_rmp_bitmask_bits bitmask; |
e281682b | 5207 | |
b4ff3a36 | 5208 | u8 reserved_at_c0[0x40]; |
e281682b SM |
5209 | |
5210 | struct mlx5_ifc_rmpc_bits ctx; | |
5211 | }; | |
5212 | ||
5213 | struct mlx5_ifc_modify_nic_vport_context_out_bits { | |
5214 | u8 status[0x8]; | |
b4ff3a36 | 5215 | u8 reserved_at_8[0x18]; |
e281682b SM |
5216 | |
5217 | u8 syndrome[0x20]; | |
5218 | ||
b4ff3a36 | 5219 | u8 reserved_at_40[0x40]; |
e281682b SM |
5220 | }; |
5221 | ||
5222 | struct mlx5_ifc_modify_nic_vport_field_select_bits { | |
23898c76 NO |
5223 | u8 reserved_at_0[0x16]; |
5224 | u8 node_guid[0x1]; | |
5225 | u8 port_guid[0x1]; | |
9def7121 | 5226 | u8 min_inline[0x1]; |
d82b7318 SM |
5227 | u8 mtu[0x1]; |
5228 | u8 change_event[0x1]; | |
5229 | u8 promisc[0x1]; | |
e281682b SM |
5230 | u8 permanent_address[0x1]; |
5231 | u8 addresses_list[0x1]; | |
5232 | u8 roce_en[0x1]; | |
b4ff3a36 | 5233 | u8 reserved_at_1f[0x1]; |
e281682b SM |
5234 | }; |
5235 | ||
5236 | struct mlx5_ifc_modify_nic_vport_context_in_bits { | |
5237 | u8 opcode[0x10]; | |
b4ff3a36 | 5238 | u8 reserved_at_10[0x10]; |
e281682b | 5239 | |
b4ff3a36 | 5240 | u8 reserved_at_20[0x10]; |
e281682b SM |
5241 | u8 op_mod[0x10]; |
5242 | ||
5243 | u8 other_vport[0x1]; | |
b4ff3a36 | 5244 | u8 reserved_at_41[0xf]; |
e281682b SM |
5245 | u8 vport_number[0x10]; |
5246 | ||
5247 | struct mlx5_ifc_modify_nic_vport_field_select_bits field_select; | |
5248 | ||
b4ff3a36 | 5249 | u8 reserved_at_80[0x780]; |
e281682b SM |
5250 | |
5251 | struct mlx5_ifc_nic_vport_context_bits nic_vport_context; | |
5252 | }; | |
5253 | ||
5254 | struct mlx5_ifc_modify_hca_vport_context_out_bits { | |
5255 | u8 status[0x8]; | |
b4ff3a36 | 5256 | u8 reserved_at_8[0x18]; |
e281682b SM |
5257 | |
5258 | u8 syndrome[0x20]; | |
5259 | ||
b4ff3a36 | 5260 | u8 reserved_at_40[0x40]; |
e281682b SM |
5261 | }; |
5262 | ||
5263 | struct mlx5_ifc_modify_hca_vport_context_in_bits { | |
5264 | u8 opcode[0x10]; | |
b4ff3a36 | 5265 | u8 reserved_at_10[0x10]; |
e281682b | 5266 | |
b4ff3a36 | 5267 | u8 reserved_at_20[0x10]; |
e281682b SM |
5268 | u8 op_mod[0x10]; |
5269 | ||
5270 | u8 other_vport[0x1]; | |
b4ff3a36 | 5271 | u8 reserved_at_41[0xb]; |
707c4602 | 5272 | u8 port_num[0x4]; |
e281682b SM |
5273 | u8 vport_number[0x10]; |
5274 | ||
b4ff3a36 | 5275 | u8 reserved_at_60[0x20]; |
e281682b SM |
5276 | |
5277 | struct mlx5_ifc_hca_vport_context_bits hca_vport_context; | |
5278 | }; | |
5279 | ||
5280 | struct mlx5_ifc_modify_cq_out_bits { | |
5281 | u8 status[0x8]; | |
b4ff3a36 | 5282 | u8 reserved_at_8[0x18]; |
e281682b SM |
5283 | |
5284 | u8 syndrome[0x20]; | |
5285 | ||
b4ff3a36 | 5286 | u8 reserved_at_40[0x40]; |
e281682b SM |
5287 | }; |
5288 | ||
5289 | enum { | |
5290 | MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0, | |
5291 | MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1, | |
5292 | }; | |
5293 | ||
5294 | struct mlx5_ifc_modify_cq_in_bits { | |
5295 | u8 opcode[0x10]; | |
b4ff3a36 | 5296 | u8 reserved_at_10[0x10]; |
e281682b | 5297 | |
b4ff3a36 | 5298 | u8 reserved_at_20[0x10]; |
e281682b SM |
5299 | u8 op_mod[0x10]; |
5300 | ||
b4ff3a36 | 5301 | u8 reserved_at_40[0x8]; |
e281682b SM |
5302 | u8 cqn[0x18]; |
5303 | ||
5304 | union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select; | |
5305 | ||
5306 | struct mlx5_ifc_cqc_bits cq_context; | |
5307 | ||
b4ff3a36 | 5308 | u8 reserved_at_280[0x600]; |
e281682b SM |
5309 | |
5310 | u8 pas[0][0x40]; | |
5311 | }; | |
5312 | ||
5313 | struct mlx5_ifc_modify_cong_status_out_bits { | |
5314 | u8 status[0x8]; | |
b4ff3a36 | 5315 | u8 reserved_at_8[0x18]; |
e281682b SM |
5316 | |
5317 | u8 syndrome[0x20]; | |
5318 | ||
b4ff3a36 | 5319 | u8 reserved_at_40[0x40]; |
e281682b SM |
5320 | }; |
5321 | ||
5322 | struct mlx5_ifc_modify_cong_status_in_bits { | |
5323 | u8 opcode[0x10]; | |
b4ff3a36 | 5324 | u8 reserved_at_10[0x10]; |
e281682b | 5325 | |
b4ff3a36 | 5326 | u8 reserved_at_20[0x10]; |
e281682b SM |
5327 | u8 op_mod[0x10]; |
5328 | ||
b4ff3a36 | 5329 | u8 reserved_at_40[0x18]; |
e281682b SM |
5330 | u8 priority[0x4]; |
5331 | u8 cong_protocol[0x4]; | |
5332 | ||
5333 | u8 enable[0x1]; | |
5334 | u8 tag_enable[0x1]; | |
b4ff3a36 | 5335 | u8 reserved_at_62[0x1e]; |
e281682b SM |
5336 | }; |
5337 | ||
5338 | struct mlx5_ifc_modify_cong_params_out_bits { | |
5339 | u8 status[0x8]; | |
b4ff3a36 | 5340 | u8 reserved_at_8[0x18]; |
e281682b SM |
5341 | |
5342 | u8 syndrome[0x20]; | |
5343 | ||
b4ff3a36 | 5344 | u8 reserved_at_40[0x40]; |
e281682b SM |
5345 | }; |
5346 | ||
5347 | struct mlx5_ifc_modify_cong_params_in_bits { | |
5348 | u8 opcode[0x10]; | |
b4ff3a36 | 5349 | u8 reserved_at_10[0x10]; |
e281682b | 5350 | |
b4ff3a36 | 5351 | u8 reserved_at_20[0x10]; |
e281682b SM |
5352 | u8 op_mod[0x10]; |
5353 | ||
b4ff3a36 | 5354 | u8 reserved_at_40[0x1c]; |
e281682b SM |
5355 | u8 cong_protocol[0x4]; |
5356 | ||
5357 | union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select; | |
5358 | ||
b4ff3a36 | 5359 | u8 reserved_at_80[0x80]; |
e281682b SM |
5360 | |
5361 | union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters; | |
5362 | }; | |
5363 | ||
5364 | struct mlx5_ifc_manage_pages_out_bits { | |
5365 | u8 status[0x8]; | |
b4ff3a36 | 5366 | u8 reserved_at_8[0x18]; |
e281682b SM |
5367 | |
5368 | u8 syndrome[0x20]; | |
5369 | ||
5370 | u8 output_num_entries[0x20]; | |
5371 | ||
b4ff3a36 | 5372 | u8 reserved_at_60[0x20]; |
e281682b SM |
5373 | |
5374 | u8 pas[0][0x40]; | |
5375 | }; | |
5376 | ||
5377 | enum { | |
5378 | MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0, | |
5379 | MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1, | |
5380 | MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2, | |
5381 | }; | |
5382 | ||
5383 | struct mlx5_ifc_manage_pages_in_bits { | |
5384 | u8 opcode[0x10]; | |
b4ff3a36 | 5385 | u8 reserved_at_10[0x10]; |
e281682b | 5386 | |
b4ff3a36 | 5387 | u8 reserved_at_20[0x10]; |
e281682b SM |
5388 | u8 op_mod[0x10]; |
5389 | ||
b4ff3a36 | 5390 | u8 reserved_at_40[0x10]; |
e281682b SM |
5391 | u8 function_id[0x10]; |
5392 | ||
5393 | u8 input_num_entries[0x20]; | |
5394 | ||
5395 | u8 pas[0][0x40]; | |
5396 | }; | |
5397 | ||
5398 | struct mlx5_ifc_mad_ifc_out_bits { | |
5399 | u8 status[0x8]; | |
b4ff3a36 | 5400 | u8 reserved_at_8[0x18]; |
e281682b SM |
5401 | |
5402 | u8 syndrome[0x20]; | |
5403 | ||
b4ff3a36 | 5404 | u8 reserved_at_40[0x40]; |
e281682b SM |
5405 | |
5406 | u8 response_mad_packet[256][0x8]; | |
5407 | }; | |
5408 | ||
5409 | struct mlx5_ifc_mad_ifc_in_bits { | |
5410 | u8 opcode[0x10]; | |
b4ff3a36 | 5411 | u8 reserved_at_10[0x10]; |
e281682b | 5412 | |
b4ff3a36 | 5413 | u8 reserved_at_20[0x10]; |
e281682b SM |
5414 | u8 op_mod[0x10]; |
5415 | ||
5416 | u8 remote_lid[0x10]; | |
b4ff3a36 | 5417 | u8 reserved_at_50[0x8]; |
e281682b SM |
5418 | u8 port[0x8]; |
5419 | ||
b4ff3a36 | 5420 | u8 reserved_at_60[0x20]; |
e281682b SM |
5421 | |
5422 | u8 mad[256][0x8]; | |
5423 | }; | |
5424 | ||
5425 | struct mlx5_ifc_init_hca_out_bits { | |
5426 | u8 status[0x8]; | |
b4ff3a36 | 5427 | u8 reserved_at_8[0x18]; |
e281682b SM |
5428 | |
5429 | u8 syndrome[0x20]; | |
5430 | ||
b4ff3a36 | 5431 | u8 reserved_at_40[0x40]; |
e281682b SM |
5432 | }; |
5433 | ||
5434 | struct mlx5_ifc_init_hca_in_bits { | |
5435 | u8 opcode[0x10]; | |
b4ff3a36 | 5436 | u8 reserved_at_10[0x10]; |
e281682b | 5437 | |
b4ff3a36 | 5438 | u8 reserved_at_20[0x10]; |
e281682b SM |
5439 | u8 op_mod[0x10]; |
5440 | ||
b4ff3a36 | 5441 | u8 reserved_at_40[0x40]; |
e281682b SM |
5442 | }; |
5443 | ||
5444 | struct mlx5_ifc_init2rtr_qp_out_bits { | |
5445 | u8 status[0x8]; | |
b4ff3a36 | 5446 | u8 reserved_at_8[0x18]; |
e281682b SM |
5447 | |
5448 | u8 syndrome[0x20]; | |
5449 | ||
b4ff3a36 | 5450 | u8 reserved_at_40[0x40]; |
e281682b SM |
5451 | }; |
5452 | ||
5453 | struct mlx5_ifc_init2rtr_qp_in_bits { | |
5454 | u8 opcode[0x10]; | |
b4ff3a36 | 5455 | u8 reserved_at_10[0x10]; |
e281682b | 5456 | |
b4ff3a36 | 5457 | u8 reserved_at_20[0x10]; |
e281682b SM |
5458 | u8 op_mod[0x10]; |
5459 | ||
b4ff3a36 | 5460 | u8 reserved_at_40[0x8]; |
e281682b SM |
5461 | u8 qpn[0x18]; |
5462 | ||
b4ff3a36 | 5463 | u8 reserved_at_60[0x20]; |
e281682b SM |
5464 | |
5465 | u8 opt_param_mask[0x20]; | |
5466 | ||
b4ff3a36 | 5467 | u8 reserved_at_a0[0x20]; |
e281682b SM |
5468 | |
5469 | struct mlx5_ifc_qpc_bits qpc; | |
5470 | ||
b4ff3a36 | 5471 | u8 reserved_at_800[0x80]; |
e281682b SM |
5472 | }; |
5473 | ||
5474 | struct mlx5_ifc_init2init_qp_out_bits { | |
5475 | u8 status[0x8]; | |
b4ff3a36 | 5476 | u8 reserved_at_8[0x18]; |
e281682b SM |
5477 | |
5478 | u8 syndrome[0x20]; | |
5479 | ||
b4ff3a36 | 5480 | u8 reserved_at_40[0x40]; |
e281682b SM |
5481 | }; |
5482 | ||
5483 | struct mlx5_ifc_init2init_qp_in_bits { | |
5484 | u8 opcode[0x10]; | |
b4ff3a36 | 5485 | u8 reserved_at_10[0x10]; |
e281682b | 5486 | |
b4ff3a36 | 5487 | u8 reserved_at_20[0x10]; |
e281682b SM |
5488 | u8 op_mod[0x10]; |
5489 | ||
b4ff3a36 | 5490 | u8 reserved_at_40[0x8]; |
e281682b SM |
5491 | u8 qpn[0x18]; |
5492 | ||
b4ff3a36 | 5493 | u8 reserved_at_60[0x20]; |
e281682b SM |
5494 | |
5495 | u8 opt_param_mask[0x20]; | |
5496 | ||
b4ff3a36 | 5497 | u8 reserved_at_a0[0x20]; |
e281682b SM |
5498 | |
5499 | struct mlx5_ifc_qpc_bits qpc; | |
5500 | ||
b4ff3a36 | 5501 | u8 reserved_at_800[0x80]; |
e281682b SM |
5502 | }; |
5503 | ||
5504 | struct mlx5_ifc_get_dropped_packet_log_out_bits { | |
5505 | u8 status[0x8]; | |
b4ff3a36 | 5506 | u8 reserved_at_8[0x18]; |
e281682b SM |
5507 | |
5508 | u8 syndrome[0x20]; | |
5509 | ||
b4ff3a36 | 5510 | u8 reserved_at_40[0x40]; |
e281682b SM |
5511 | |
5512 | u8 packet_headers_log[128][0x8]; | |
5513 | ||
5514 | u8 packet_syndrome[64][0x8]; | |
5515 | }; | |
5516 | ||
5517 | struct mlx5_ifc_get_dropped_packet_log_in_bits { | |
5518 | u8 opcode[0x10]; | |
b4ff3a36 | 5519 | u8 reserved_at_10[0x10]; |
e281682b | 5520 | |
b4ff3a36 | 5521 | u8 reserved_at_20[0x10]; |
e281682b SM |
5522 | u8 op_mod[0x10]; |
5523 | ||
b4ff3a36 | 5524 | u8 reserved_at_40[0x40]; |
e281682b SM |
5525 | }; |
5526 | ||
5527 | struct mlx5_ifc_gen_eqe_in_bits { | |
5528 | u8 opcode[0x10]; | |
b4ff3a36 | 5529 | u8 reserved_at_10[0x10]; |
e281682b | 5530 | |
b4ff3a36 | 5531 | u8 reserved_at_20[0x10]; |
e281682b SM |
5532 | u8 op_mod[0x10]; |
5533 | ||
b4ff3a36 | 5534 | u8 reserved_at_40[0x18]; |
e281682b SM |
5535 | u8 eq_number[0x8]; |
5536 | ||
b4ff3a36 | 5537 | u8 reserved_at_60[0x20]; |
e281682b SM |
5538 | |
5539 | u8 eqe[64][0x8]; | |
5540 | }; | |
5541 | ||
5542 | struct mlx5_ifc_gen_eq_out_bits { | |
5543 | u8 status[0x8]; | |
b4ff3a36 | 5544 | u8 reserved_at_8[0x18]; |
e281682b SM |
5545 | |
5546 | u8 syndrome[0x20]; | |
5547 | ||
b4ff3a36 | 5548 | u8 reserved_at_40[0x40]; |
e281682b SM |
5549 | }; |
5550 | ||
5551 | struct mlx5_ifc_enable_hca_out_bits { | |
5552 | u8 status[0x8]; | |
b4ff3a36 | 5553 | u8 reserved_at_8[0x18]; |
e281682b SM |
5554 | |
5555 | u8 syndrome[0x20]; | |
5556 | ||
b4ff3a36 | 5557 | u8 reserved_at_40[0x20]; |
e281682b SM |
5558 | }; |
5559 | ||
5560 | struct mlx5_ifc_enable_hca_in_bits { | |
5561 | u8 opcode[0x10]; | |
b4ff3a36 | 5562 | u8 reserved_at_10[0x10]; |
e281682b | 5563 | |
b4ff3a36 | 5564 | u8 reserved_at_20[0x10]; |
e281682b SM |
5565 | u8 op_mod[0x10]; |
5566 | ||
b4ff3a36 | 5567 | u8 reserved_at_40[0x10]; |
e281682b SM |
5568 | u8 function_id[0x10]; |
5569 | ||
b4ff3a36 | 5570 | u8 reserved_at_60[0x20]; |
e281682b SM |
5571 | }; |
5572 | ||
5573 | struct mlx5_ifc_drain_dct_out_bits { | |
5574 | u8 status[0x8]; | |
b4ff3a36 | 5575 | u8 reserved_at_8[0x18]; |
e281682b SM |
5576 | |
5577 | u8 syndrome[0x20]; | |
5578 | ||
b4ff3a36 | 5579 | u8 reserved_at_40[0x40]; |
e281682b SM |
5580 | }; |
5581 | ||
5582 | struct mlx5_ifc_drain_dct_in_bits { | |
5583 | u8 opcode[0x10]; | |
b4ff3a36 | 5584 | u8 reserved_at_10[0x10]; |
e281682b | 5585 | |
b4ff3a36 | 5586 | u8 reserved_at_20[0x10]; |
e281682b SM |
5587 | u8 op_mod[0x10]; |
5588 | ||
b4ff3a36 | 5589 | u8 reserved_at_40[0x8]; |
e281682b SM |
5590 | u8 dctn[0x18]; |
5591 | ||
b4ff3a36 | 5592 | u8 reserved_at_60[0x20]; |
e281682b SM |
5593 | }; |
5594 | ||
5595 | struct mlx5_ifc_disable_hca_out_bits { | |
5596 | u8 status[0x8]; | |
b4ff3a36 | 5597 | u8 reserved_at_8[0x18]; |
e281682b SM |
5598 | |
5599 | u8 syndrome[0x20]; | |
5600 | ||
b4ff3a36 | 5601 | u8 reserved_at_40[0x20]; |
e281682b SM |
5602 | }; |
5603 | ||
5604 | struct mlx5_ifc_disable_hca_in_bits { | |
5605 | u8 opcode[0x10]; | |
b4ff3a36 | 5606 | u8 reserved_at_10[0x10]; |
e281682b | 5607 | |
b4ff3a36 | 5608 | u8 reserved_at_20[0x10]; |
e281682b SM |
5609 | u8 op_mod[0x10]; |
5610 | ||
b4ff3a36 | 5611 | u8 reserved_at_40[0x10]; |
e281682b SM |
5612 | u8 function_id[0x10]; |
5613 | ||
b4ff3a36 | 5614 | u8 reserved_at_60[0x20]; |
e281682b SM |
5615 | }; |
5616 | ||
5617 | struct mlx5_ifc_detach_from_mcg_out_bits { | |
5618 | u8 status[0x8]; | |
b4ff3a36 | 5619 | u8 reserved_at_8[0x18]; |
e281682b SM |
5620 | |
5621 | u8 syndrome[0x20]; | |
5622 | ||
b4ff3a36 | 5623 | u8 reserved_at_40[0x40]; |
e281682b SM |
5624 | }; |
5625 | ||
5626 | struct mlx5_ifc_detach_from_mcg_in_bits { | |
5627 | u8 opcode[0x10]; | |
b4ff3a36 | 5628 | u8 reserved_at_10[0x10]; |
e281682b | 5629 | |
b4ff3a36 | 5630 | u8 reserved_at_20[0x10]; |
e281682b SM |
5631 | u8 op_mod[0x10]; |
5632 | ||
b4ff3a36 | 5633 | u8 reserved_at_40[0x8]; |
e281682b SM |
5634 | u8 qpn[0x18]; |
5635 | ||
b4ff3a36 | 5636 | u8 reserved_at_60[0x20]; |
e281682b SM |
5637 | |
5638 | u8 multicast_gid[16][0x8]; | |
5639 | }; | |
5640 | ||
7486216b SM |
5641 | struct mlx5_ifc_destroy_xrq_out_bits { |
5642 | u8 status[0x8]; | |
5643 | u8 reserved_at_8[0x18]; | |
5644 | ||
5645 | u8 syndrome[0x20]; | |
5646 | ||
5647 | u8 reserved_at_40[0x40]; | |
5648 | }; | |
5649 | ||
5650 | struct mlx5_ifc_destroy_xrq_in_bits { | |
5651 | u8 opcode[0x10]; | |
5652 | u8 reserved_at_10[0x10]; | |
5653 | ||
5654 | u8 reserved_at_20[0x10]; | |
5655 | u8 op_mod[0x10]; | |
5656 | ||
5657 | u8 reserved_at_40[0x8]; | |
5658 | u8 xrqn[0x18]; | |
5659 | ||
5660 | u8 reserved_at_60[0x20]; | |
5661 | }; | |
5662 | ||
e281682b SM |
5663 | struct mlx5_ifc_destroy_xrc_srq_out_bits { |
5664 | u8 status[0x8]; | |
b4ff3a36 | 5665 | u8 reserved_at_8[0x18]; |
e281682b SM |
5666 | |
5667 | u8 syndrome[0x20]; | |
5668 | ||
b4ff3a36 | 5669 | u8 reserved_at_40[0x40]; |
e281682b SM |
5670 | }; |
5671 | ||
5672 | struct mlx5_ifc_destroy_xrc_srq_in_bits { | |
5673 | u8 opcode[0x10]; | |
b4ff3a36 | 5674 | u8 reserved_at_10[0x10]; |
e281682b | 5675 | |
b4ff3a36 | 5676 | u8 reserved_at_20[0x10]; |
e281682b SM |
5677 | u8 op_mod[0x10]; |
5678 | ||
b4ff3a36 | 5679 | u8 reserved_at_40[0x8]; |
e281682b SM |
5680 | u8 xrc_srqn[0x18]; |
5681 | ||
b4ff3a36 | 5682 | u8 reserved_at_60[0x20]; |
e281682b SM |
5683 | }; |
5684 | ||
5685 | struct mlx5_ifc_destroy_tis_out_bits { | |
5686 | u8 status[0x8]; | |
b4ff3a36 | 5687 | u8 reserved_at_8[0x18]; |
e281682b SM |
5688 | |
5689 | u8 syndrome[0x20]; | |
5690 | ||
b4ff3a36 | 5691 | u8 reserved_at_40[0x40]; |
e281682b SM |
5692 | }; |
5693 | ||
5694 | struct mlx5_ifc_destroy_tis_in_bits { | |
5695 | u8 opcode[0x10]; | |
b4ff3a36 | 5696 | u8 reserved_at_10[0x10]; |
e281682b | 5697 | |
b4ff3a36 | 5698 | u8 reserved_at_20[0x10]; |
e281682b SM |
5699 | u8 op_mod[0x10]; |
5700 | ||
b4ff3a36 | 5701 | u8 reserved_at_40[0x8]; |
e281682b SM |
5702 | u8 tisn[0x18]; |
5703 | ||
b4ff3a36 | 5704 | u8 reserved_at_60[0x20]; |
e281682b SM |
5705 | }; |
5706 | ||
5707 | struct mlx5_ifc_destroy_tir_out_bits { | |
5708 | u8 status[0x8]; | |
b4ff3a36 | 5709 | u8 reserved_at_8[0x18]; |
e281682b SM |
5710 | |
5711 | u8 syndrome[0x20]; | |
5712 | ||
b4ff3a36 | 5713 | u8 reserved_at_40[0x40]; |
e281682b SM |
5714 | }; |
5715 | ||
5716 | struct mlx5_ifc_destroy_tir_in_bits { | |
5717 | u8 opcode[0x10]; | |
b4ff3a36 | 5718 | u8 reserved_at_10[0x10]; |
e281682b | 5719 | |
b4ff3a36 | 5720 | u8 reserved_at_20[0x10]; |
e281682b SM |
5721 | u8 op_mod[0x10]; |
5722 | ||
b4ff3a36 | 5723 | u8 reserved_at_40[0x8]; |
e281682b SM |
5724 | u8 tirn[0x18]; |
5725 | ||
b4ff3a36 | 5726 | u8 reserved_at_60[0x20]; |
e281682b SM |
5727 | }; |
5728 | ||
5729 | struct mlx5_ifc_destroy_srq_out_bits { | |
5730 | u8 status[0x8]; | |
b4ff3a36 | 5731 | u8 reserved_at_8[0x18]; |
e281682b SM |
5732 | |
5733 | u8 syndrome[0x20]; | |
5734 | ||
b4ff3a36 | 5735 | u8 reserved_at_40[0x40]; |
e281682b SM |
5736 | }; |
5737 | ||
5738 | struct mlx5_ifc_destroy_srq_in_bits { | |
5739 | u8 opcode[0x10]; | |
b4ff3a36 | 5740 | u8 reserved_at_10[0x10]; |
e281682b | 5741 | |
b4ff3a36 | 5742 | u8 reserved_at_20[0x10]; |
e281682b SM |
5743 | u8 op_mod[0x10]; |
5744 | ||
b4ff3a36 | 5745 | u8 reserved_at_40[0x8]; |
e281682b SM |
5746 | u8 srqn[0x18]; |
5747 | ||
b4ff3a36 | 5748 | u8 reserved_at_60[0x20]; |
e281682b SM |
5749 | }; |
5750 | ||
5751 | struct mlx5_ifc_destroy_sq_out_bits { | |
5752 | u8 status[0x8]; | |
b4ff3a36 | 5753 | u8 reserved_at_8[0x18]; |
e281682b SM |
5754 | |
5755 | u8 syndrome[0x20]; | |
5756 | ||
b4ff3a36 | 5757 | u8 reserved_at_40[0x40]; |
e281682b SM |
5758 | }; |
5759 | ||
5760 | struct mlx5_ifc_destroy_sq_in_bits { | |
5761 | u8 opcode[0x10]; | |
b4ff3a36 | 5762 | u8 reserved_at_10[0x10]; |
e281682b | 5763 | |
b4ff3a36 | 5764 | u8 reserved_at_20[0x10]; |
e281682b SM |
5765 | u8 op_mod[0x10]; |
5766 | ||
b4ff3a36 | 5767 | u8 reserved_at_40[0x8]; |
e281682b SM |
5768 | u8 sqn[0x18]; |
5769 | ||
b4ff3a36 | 5770 | u8 reserved_at_60[0x20]; |
e281682b SM |
5771 | }; |
5772 | ||
813f8540 MHY |
5773 | struct mlx5_ifc_destroy_scheduling_element_out_bits { |
5774 | u8 status[0x8]; | |
5775 | u8 reserved_at_8[0x18]; | |
5776 | ||
5777 | u8 syndrome[0x20]; | |
5778 | ||
5779 | u8 reserved_at_40[0x1c0]; | |
5780 | }; | |
5781 | ||
5782 | struct mlx5_ifc_destroy_scheduling_element_in_bits { | |
5783 | u8 opcode[0x10]; | |
5784 | u8 reserved_at_10[0x10]; | |
5785 | ||
5786 | u8 reserved_at_20[0x10]; | |
5787 | u8 op_mod[0x10]; | |
5788 | ||
5789 | u8 scheduling_hierarchy[0x8]; | |
5790 | u8 reserved_at_48[0x18]; | |
5791 | ||
5792 | u8 scheduling_element_id[0x20]; | |
5793 | ||
5794 | u8 reserved_at_80[0x180]; | |
5795 | }; | |
5796 | ||
e281682b SM |
5797 | struct mlx5_ifc_destroy_rqt_out_bits { |
5798 | u8 status[0x8]; | |
b4ff3a36 | 5799 | u8 reserved_at_8[0x18]; |
e281682b SM |
5800 | |
5801 | u8 syndrome[0x20]; | |
5802 | ||
b4ff3a36 | 5803 | u8 reserved_at_40[0x40]; |
e281682b SM |
5804 | }; |
5805 | ||
5806 | struct mlx5_ifc_destroy_rqt_in_bits { | |
5807 | u8 opcode[0x10]; | |
b4ff3a36 | 5808 | u8 reserved_at_10[0x10]; |
e281682b | 5809 | |
b4ff3a36 | 5810 | u8 reserved_at_20[0x10]; |
e281682b SM |
5811 | u8 op_mod[0x10]; |
5812 | ||
b4ff3a36 | 5813 | u8 reserved_at_40[0x8]; |
e281682b SM |
5814 | u8 rqtn[0x18]; |
5815 | ||
b4ff3a36 | 5816 | u8 reserved_at_60[0x20]; |
e281682b SM |
5817 | }; |
5818 | ||
5819 | struct mlx5_ifc_destroy_rq_out_bits { | |
5820 | u8 status[0x8]; | |
b4ff3a36 | 5821 | u8 reserved_at_8[0x18]; |
e281682b SM |
5822 | |
5823 | u8 syndrome[0x20]; | |
5824 | ||
b4ff3a36 | 5825 | u8 reserved_at_40[0x40]; |
e281682b SM |
5826 | }; |
5827 | ||
5828 | struct mlx5_ifc_destroy_rq_in_bits { | |
5829 | u8 opcode[0x10]; | |
b4ff3a36 | 5830 | u8 reserved_at_10[0x10]; |
e281682b | 5831 | |
b4ff3a36 | 5832 | u8 reserved_at_20[0x10]; |
e281682b SM |
5833 | u8 op_mod[0x10]; |
5834 | ||
b4ff3a36 | 5835 | u8 reserved_at_40[0x8]; |
e281682b SM |
5836 | u8 rqn[0x18]; |
5837 | ||
b4ff3a36 | 5838 | u8 reserved_at_60[0x20]; |
e281682b SM |
5839 | }; |
5840 | ||
5841 | struct mlx5_ifc_destroy_rmp_out_bits { | |
5842 | u8 status[0x8]; | |
b4ff3a36 | 5843 | u8 reserved_at_8[0x18]; |
e281682b SM |
5844 | |
5845 | u8 syndrome[0x20]; | |
5846 | ||
b4ff3a36 | 5847 | u8 reserved_at_40[0x40]; |
e281682b SM |
5848 | }; |
5849 | ||
5850 | struct mlx5_ifc_destroy_rmp_in_bits { | |
5851 | u8 opcode[0x10]; | |
b4ff3a36 | 5852 | u8 reserved_at_10[0x10]; |
e281682b | 5853 | |
b4ff3a36 | 5854 | u8 reserved_at_20[0x10]; |
e281682b SM |
5855 | u8 op_mod[0x10]; |
5856 | ||
b4ff3a36 | 5857 | u8 reserved_at_40[0x8]; |
e281682b SM |
5858 | u8 rmpn[0x18]; |
5859 | ||
b4ff3a36 | 5860 | u8 reserved_at_60[0x20]; |
e281682b SM |
5861 | }; |
5862 | ||
5863 | struct mlx5_ifc_destroy_qp_out_bits { | |
5864 | u8 status[0x8]; | |
b4ff3a36 | 5865 | u8 reserved_at_8[0x18]; |
e281682b SM |
5866 | |
5867 | u8 syndrome[0x20]; | |
5868 | ||
b4ff3a36 | 5869 | u8 reserved_at_40[0x40]; |
e281682b SM |
5870 | }; |
5871 | ||
5872 | struct mlx5_ifc_destroy_qp_in_bits { | |
5873 | u8 opcode[0x10]; | |
b4ff3a36 | 5874 | u8 reserved_at_10[0x10]; |
e281682b | 5875 | |
b4ff3a36 | 5876 | u8 reserved_at_20[0x10]; |
e281682b SM |
5877 | u8 op_mod[0x10]; |
5878 | ||
b4ff3a36 | 5879 | u8 reserved_at_40[0x8]; |
e281682b SM |
5880 | u8 qpn[0x18]; |
5881 | ||
b4ff3a36 | 5882 | u8 reserved_at_60[0x20]; |
e281682b SM |
5883 | }; |
5884 | ||
5885 | struct mlx5_ifc_destroy_psv_out_bits { | |
5886 | u8 status[0x8]; | |
b4ff3a36 | 5887 | u8 reserved_at_8[0x18]; |
e281682b SM |
5888 | |
5889 | u8 syndrome[0x20]; | |
5890 | ||
b4ff3a36 | 5891 | u8 reserved_at_40[0x40]; |
e281682b SM |
5892 | }; |
5893 | ||
5894 | struct mlx5_ifc_destroy_psv_in_bits { | |
5895 | u8 opcode[0x10]; | |
b4ff3a36 | 5896 | u8 reserved_at_10[0x10]; |
e281682b | 5897 | |
b4ff3a36 | 5898 | u8 reserved_at_20[0x10]; |
e281682b SM |
5899 | u8 op_mod[0x10]; |
5900 | ||
b4ff3a36 | 5901 | u8 reserved_at_40[0x8]; |
e281682b SM |
5902 | u8 psvn[0x18]; |
5903 | ||
b4ff3a36 | 5904 | u8 reserved_at_60[0x20]; |
e281682b SM |
5905 | }; |
5906 | ||
5907 | struct mlx5_ifc_destroy_mkey_out_bits { | |
5908 | u8 status[0x8]; | |
b4ff3a36 | 5909 | u8 reserved_at_8[0x18]; |
e281682b SM |
5910 | |
5911 | u8 syndrome[0x20]; | |
5912 | ||
b4ff3a36 | 5913 | u8 reserved_at_40[0x40]; |
e281682b SM |
5914 | }; |
5915 | ||
5916 | struct mlx5_ifc_destroy_mkey_in_bits { | |
5917 | u8 opcode[0x10]; | |
b4ff3a36 | 5918 | u8 reserved_at_10[0x10]; |
e281682b | 5919 | |
b4ff3a36 | 5920 | u8 reserved_at_20[0x10]; |
e281682b SM |
5921 | u8 op_mod[0x10]; |
5922 | ||
b4ff3a36 | 5923 | u8 reserved_at_40[0x8]; |
e281682b SM |
5924 | u8 mkey_index[0x18]; |
5925 | ||
b4ff3a36 | 5926 | u8 reserved_at_60[0x20]; |
e281682b SM |
5927 | }; |
5928 | ||
5929 | struct mlx5_ifc_destroy_flow_table_out_bits { | |
5930 | u8 status[0x8]; | |
b4ff3a36 | 5931 | u8 reserved_at_8[0x18]; |
e281682b SM |
5932 | |
5933 | u8 syndrome[0x20]; | |
5934 | ||
b4ff3a36 | 5935 | u8 reserved_at_40[0x40]; |
e281682b SM |
5936 | }; |
5937 | ||
5938 | struct mlx5_ifc_destroy_flow_table_in_bits { | |
5939 | u8 opcode[0x10]; | |
b4ff3a36 | 5940 | u8 reserved_at_10[0x10]; |
e281682b | 5941 | |
b4ff3a36 | 5942 | u8 reserved_at_20[0x10]; |
e281682b SM |
5943 | u8 op_mod[0x10]; |
5944 | ||
7d5e1423 SM |
5945 | u8 other_vport[0x1]; |
5946 | u8 reserved_at_41[0xf]; | |
5947 | u8 vport_number[0x10]; | |
5948 | ||
5949 | u8 reserved_at_60[0x20]; | |
e281682b SM |
5950 | |
5951 | u8 table_type[0x8]; | |
b4ff3a36 | 5952 | u8 reserved_at_88[0x18]; |
e281682b | 5953 | |
b4ff3a36 | 5954 | u8 reserved_at_a0[0x8]; |
e281682b SM |
5955 | u8 table_id[0x18]; |
5956 | ||
b4ff3a36 | 5957 | u8 reserved_at_c0[0x140]; |
e281682b SM |
5958 | }; |
5959 | ||
5960 | struct mlx5_ifc_destroy_flow_group_out_bits { | |
5961 | u8 status[0x8]; | |
b4ff3a36 | 5962 | u8 reserved_at_8[0x18]; |
e281682b SM |
5963 | |
5964 | u8 syndrome[0x20]; | |
5965 | ||
b4ff3a36 | 5966 | u8 reserved_at_40[0x40]; |
e281682b SM |
5967 | }; |
5968 | ||
5969 | struct mlx5_ifc_destroy_flow_group_in_bits { | |
5970 | u8 opcode[0x10]; | |
b4ff3a36 | 5971 | u8 reserved_at_10[0x10]; |
e281682b | 5972 | |
b4ff3a36 | 5973 | u8 reserved_at_20[0x10]; |
e281682b SM |
5974 | u8 op_mod[0x10]; |
5975 | ||
7d5e1423 SM |
5976 | u8 other_vport[0x1]; |
5977 | u8 reserved_at_41[0xf]; | |
5978 | u8 vport_number[0x10]; | |
5979 | ||
5980 | u8 reserved_at_60[0x20]; | |
e281682b SM |
5981 | |
5982 | u8 table_type[0x8]; | |
b4ff3a36 | 5983 | u8 reserved_at_88[0x18]; |
e281682b | 5984 | |
b4ff3a36 | 5985 | u8 reserved_at_a0[0x8]; |
e281682b SM |
5986 | u8 table_id[0x18]; |
5987 | ||
5988 | u8 group_id[0x20]; | |
5989 | ||
b4ff3a36 | 5990 | u8 reserved_at_e0[0x120]; |
e281682b SM |
5991 | }; |
5992 | ||
5993 | struct mlx5_ifc_destroy_eq_out_bits { | |
5994 | u8 status[0x8]; | |
b4ff3a36 | 5995 | u8 reserved_at_8[0x18]; |
e281682b SM |
5996 | |
5997 | u8 syndrome[0x20]; | |
5998 | ||
b4ff3a36 | 5999 | u8 reserved_at_40[0x40]; |
e281682b SM |
6000 | }; |
6001 | ||
6002 | struct mlx5_ifc_destroy_eq_in_bits { | |
6003 | u8 opcode[0x10]; | |
b4ff3a36 | 6004 | u8 reserved_at_10[0x10]; |
e281682b | 6005 | |
b4ff3a36 | 6006 | u8 reserved_at_20[0x10]; |
e281682b SM |
6007 | u8 op_mod[0x10]; |
6008 | ||
b4ff3a36 | 6009 | u8 reserved_at_40[0x18]; |
e281682b SM |
6010 | u8 eq_number[0x8]; |
6011 | ||
b4ff3a36 | 6012 | u8 reserved_at_60[0x20]; |
e281682b SM |
6013 | }; |
6014 | ||
6015 | struct mlx5_ifc_destroy_dct_out_bits { | |
6016 | u8 status[0x8]; | |
b4ff3a36 | 6017 | u8 reserved_at_8[0x18]; |
e281682b SM |
6018 | |
6019 | u8 syndrome[0x20]; | |
6020 | ||
b4ff3a36 | 6021 | u8 reserved_at_40[0x40]; |
e281682b SM |
6022 | }; |
6023 | ||
6024 | struct mlx5_ifc_destroy_dct_in_bits { | |
6025 | u8 opcode[0x10]; | |
b4ff3a36 | 6026 | u8 reserved_at_10[0x10]; |
e281682b | 6027 | |
b4ff3a36 | 6028 | u8 reserved_at_20[0x10]; |
e281682b SM |
6029 | u8 op_mod[0x10]; |
6030 | ||
b4ff3a36 | 6031 | u8 reserved_at_40[0x8]; |
e281682b SM |
6032 | u8 dctn[0x18]; |
6033 | ||
b4ff3a36 | 6034 | u8 reserved_at_60[0x20]; |
e281682b SM |
6035 | }; |
6036 | ||
6037 | struct mlx5_ifc_destroy_cq_out_bits { | |
6038 | u8 status[0x8]; | |
b4ff3a36 | 6039 | u8 reserved_at_8[0x18]; |
e281682b SM |
6040 | |
6041 | u8 syndrome[0x20]; | |
6042 | ||
b4ff3a36 | 6043 | u8 reserved_at_40[0x40]; |
e281682b SM |
6044 | }; |
6045 | ||
6046 | struct mlx5_ifc_destroy_cq_in_bits { | |
6047 | u8 opcode[0x10]; | |
b4ff3a36 | 6048 | u8 reserved_at_10[0x10]; |
e281682b | 6049 | |
b4ff3a36 | 6050 | u8 reserved_at_20[0x10]; |
e281682b SM |
6051 | u8 op_mod[0x10]; |
6052 | ||
b4ff3a36 | 6053 | u8 reserved_at_40[0x8]; |
e281682b SM |
6054 | u8 cqn[0x18]; |
6055 | ||
b4ff3a36 | 6056 | u8 reserved_at_60[0x20]; |
e281682b SM |
6057 | }; |
6058 | ||
6059 | struct mlx5_ifc_delete_vxlan_udp_dport_out_bits { | |
6060 | u8 status[0x8]; | |
b4ff3a36 | 6061 | u8 reserved_at_8[0x18]; |
e281682b SM |
6062 | |
6063 | u8 syndrome[0x20]; | |
6064 | ||
b4ff3a36 | 6065 | u8 reserved_at_40[0x40]; |
e281682b SM |
6066 | }; |
6067 | ||
6068 | struct mlx5_ifc_delete_vxlan_udp_dport_in_bits { | |
6069 | u8 opcode[0x10]; | |
b4ff3a36 | 6070 | u8 reserved_at_10[0x10]; |
e281682b | 6071 | |
b4ff3a36 | 6072 | u8 reserved_at_20[0x10]; |
e281682b SM |
6073 | u8 op_mod[0x10]; |
6074 | ||
b4ff3a36 | 6075 | u8 reserved_at_40[0x20]; |
e281682b | 6076 | |
b4ff3a36 | 6077 | u8 reserved_at_60[0x10]; |
e281682b SM |
6078 | u8 vxlan_udp_port[0x10]; |
6079 | }; | |
6080 | ||
6081 | struct mlx5_ifc_delete_l2_table_entry_out_bits { | |
6082 | u8 status[0x8]; | |
b4ff3a36 | 6083 | u8 reserved_at_8[0x18]; |
e281682b SM |
6084 | |
6085 | u8 syndrome[0x20]; | |
6086 | ||
b4ff3a36 | 6087 | u8 reserved_at_40[0x40]; |
e281682b SM |
6088 | }; |
6089 | ||
6090 | struct mlx5_ifc_delete_l2_table_entry_in_bits { | |
6091 | u8 opcode[0x10]; | |
b4ff3a36 | 6092 | u8 reserved_at_10[0x10]; |
e281682b | 6093 | |
b4ff3a36 | 6094 | u8 reserved_at_20[0x10]; |
e281682b SM |
6095 | u8 op_mod[0x10]; |
6096 | ||
b4ff3a36 | 6097 | u8 reserved_at_40[0x60]; |
e281682b | 6098 | |
b4ff3a36 | 6099 | u8 reserved_at_a0[0x8]; |
e281682b SM |
6100 | u8 table_index[0x18]; |
6101 | ||
b4ff3a36 | 6102 | u8 reserved_at_c0[0x140]; |
e281682b SM |
6103 | }; |
6104 | ||
6105 | struct mlx5_ifc_delete_fte_out_bits { | |
6106 | u8 status[0x8]; | |
b4ff3a36 | 6107 | u8 reserved_at_8[0x18]; |
e281682b SM |
6108 | |
6109 | u8 syndrome[0x20]; | |
6110 | ||
b4ff3a36 | 6111 | u8 reserved_at_40[0x40]; |
e281682b SM |
6112 | }; |
6113 | ||
6114 | struct mlx5_ifc_delete_fte_in_bits { | |
6115 | u8 opcode[0x10]; | |
b4ff3a36 | 6116 | u8 reserved_at_10[0x10]; |
e281682b | 6117 | |
b4ff3a36 | 6118 | u8 reserved_at_20[0x10]; |
e281682b SM |
6119 | u8 op_mod[0x10]; |
6120 | ||
7d5e1423 SM |
6121 | u8 other_vport[0x1]; |
6122 | u8 reserved_at_41[0xf]; | |
6123 | u8 vport_number[0x10]; | |
6124 | ||
6125 | u8 reserved_at_60[0x20]; | |
e281682b SM |
6126 | |
6127 | u8 table_type[0x8]; | |
b4ff3a36 | 6128 | u8 reserved_at_88[0x18]; |
e281682b | 6129 | |
b4ff3a36 | 6130 | u8 reserved_at_a0[0x8]; |
e281682b SM |
6131 | u8 table_id[0x18]; |
6132 | ||
b4ff3a36 | 6133 | u8 reserved_at_c0[0x40]; |
e281682b SM |
6134 | |
6135 | u8 flow_index[0x20]; | |
6136 | ||
b4ff3a36 | 6137 | u8 reserved_at_120[0xe0]; |
e281682b SM |
6138 | }; |
6139 | ||
6140 | struct mlx5_ifc_dealloc_xrcd_out_bits { | |
6141 | u8 status[0x8]; | |
b4ff3a36 | 6142 | u8 reserved_at_8[0x18]; |
e281682b SM |
6143 | |
6144 | u8 syndrome[0x20]; | |
6145 | ||
b4ff3a36 | 6146 | u8 reserved_at_40[0x40]; |
e281682b SM |
6147 | }; |
6148 | ||
6149 | struct mlx5_ifc_dealloc_xrcd_in_bits { | |
6150 | u8 opcode[0x10]; | |
b4ff3a36 | 6151 | u8 reserved_at_10[0x10]; |
e281682b | 6152 | |
b4ff3a36 | 6153 | u8 reserved_at_20[0x10]; |
e281682b SM |
6154 | u8 op_mod[0x10]; |
6155 | ||
b4ff3a36 | 6156 | u8 reserved_at_40[0x8]; |
e281682b SM |
6157 | u8 xrcd[0x18]; |
6158 | ||
b4ff3a36 | 6159 | u8 reserved_at_60[0x20]; |
e281682b SM |
6160 | }; |
6161 | ||
6162 | struct mlx5_ifc_dealloc_uar_out_bits { | |
6163 | u8 status[0x8]; | |
b4ff3a36 | 6164 | u8 reserved_at_8[0x18]; |
e281682b SM |
6165 | |
6166 | u8 syndrome[0x20]; | |
6167 | ||
b4ff3a36 | 6168 | u8 reserved_at_40[0x40]; |
e281682b SM |
6169 | }; |
6170 | ||
6171 | struct mlx5_ifc_dealloc_uar_in_bits { | |
6172 | u8 opcode[0x10]; | |
b4ff3a36 | 6173 | u8 reserved_at_10[0x10]; |
e281682b | 6174 | |
b4ff3a36 | 6175 | u8 reserved_at_20[0x10]; |
e281682b SM |
6176 | u8 op_mod[0x10]; |
6177 | ||
b4ff3a36 | 6178 | u8 reserved_at_40[0x8]; |
e281682b SM |
6179 | u8 uar[0x18]; |
6180 | ||
b4ff3a36 | 6181 | u8 reserved_at_60[0x20]; |
e281682b SM |
6182 | }; |
6183 | ||
6184 | struct mlx5_ifc_dealloc_transport_domain_out_bits { | |
6185 | u8 status[0x8]; | |
b4ff3a36 | 6186 | u8 reserved_at_8[0x18]; |
e281682b SM |
6187 | |
6188 | u8 syndrome[0x20]; | |
6189 | ||
b4ff3a36 | 6190 | u8 reserved_at_40[0x40]; |
e281682b SM |
6191 | }; |
6192 | ||
6193 | struct mlx5_ifc_dealloc_transport_domain_in_bits { | |
6194 | u8 opcode[0x10]; | |
b4ff3a36 | 6195 | u8 reserved_at_10[0x10]; |
e281682b | 6196 | |
b4ff3a36 | 6197 | u8 reserved_at_20[0x10]; |
e281682b SM |
6198 | u8 op_mod[0x10]; |
6199 | ||
b4ff3a36 | 6200 | u8 reserved_at_40[0x8]; |
e281682b SM |
6201 | u8 transport_domain[0x18]; |
6202 | ||
b4ff3a36 | 6203 | u8 reserved_at_60[0x20]; |
e281682b SM |
6204 | }; |
6205 | ||
6206 | struct mlx5_ifc_dealloc_q_counter_out_bits { | |
6207 | u8 status[0x8]; | |
b4ff3a36 | 6208 | u8 reserved_at_8[0x18]; |
e281682b SM |
6209 | |
6210 | u8 syndrome[0x20]; | |
6211 | ||
b4ff3a36 | 6212 | u8 reserved_at_40[0x40]; |
e281682b SM |
6213 | }; |
6214 | ||
6215 | struct mlx5_ifc_dealloc_q_counter_in_bits { | |
6216 | u8 opcode[0x10]; | |
b4ff3a36 | 6217 | u8 reserved_at_10[0x10]; |
e281682b | 6218 | |
b4ff3a36 | 6219 | u8 reserved_at_20[0x10]; |
e281682b SM |
6220 | u8 op_mod[0x10]; |
6221 | ||
b4ff3a36 | 6222 | u8 reserved_at_40[0x18]; |
e281682b SM |
6223 | u8 counter_set_id[0x8]; |
6224 | ||
b4ff3a36 | 6225 | u8 reserved_at_60[0x20]; |
e281682b SM |
6226 | }; |
6227 | ||
6228 | struct mlx5_ifc_dealloc_pd_out_bits { | |
6229 | u8 status[0x8]; | |
b4ff3a36 | 6230 | u8 reserved_at_8[0x18]; |
e281682b SM |
6231 | |
6232 | u8 syndrome[0x20]; | |
6233 | ||
b4ff3a36 | 6234 | u8 reserved_at_40[0x40]; |
e281682b SM |
6235 | }; |
6236 | ||
6237 | struct mlx5_ifc_dealloc_pd_in_bits { | |
6238 | u8 opcode[0x10]; | |
b4ff3a36 | 6239 | u8 reserved_at_10[0x10]; |
e281682b | 6240 | |
b4ff3a36 | 6241 | u8 reserved_at_20[0x10]; |
e281682b SM |
6242 | u8 op_mod[0x10]; |
6243 | ||
b4ff3a36 | 6244 | u8 reserved_at_40[0x8]; |
e281682b SM |
6245 | u8 pd[0x18]; |
6246 | ||
b4ff3a36 | 6247 | u8 reserved_at_60[0x20]; |
e281682b SM |
6248 | }; |
6249 | ||
9dc0b289 AV |
6250 | struct mlx5_ifc_dealloc_flow_counter_out_bits { |
6251 | u8 status[0x8]; | |
6252 | u8 reserved_at_8[0x18]; | |
6253 | ||
6254 | u8 syndrome[0x20]; | |
6255 | ||
6256 | u8 reserved_at_40[0x40]; | |
6257 | }; | |
6258 | ||
6259 | struct mlx5_ifc_dealloc_flow_counter_in_bits { | |
6260 | u8 opcode[0x10]; | |
6261 | u8 reserved_at_10[0x10]; | |
6262 | ||
6263 | u8 reserved_at_20[0x10]; | |
6264 | u8 op_mod[0x10]; | |
6265 | ||
6266 | u8 reserved_at_40[0x10]; | |
6267 | u8 flow_counter_id[0x10]; | |
6268 | ||
6269 | u8 reserved_at_60[0x20]; | |
6270 | }; | |
6271 | ||
7486216b SM |
6272 | struct mlx5_ifc_create_xrq_out_bits { |
6273 | u8 status[0x8]; | |
6274 | u8 reserved_at_8[0x18]; | |
6275 | ||
6276 | u8 syndrome[0x20]; | |
6277 | ||
6278 | u8 reserved_at_40[0x8]; | |
6279 | u8 xrqn[0x18]; | |
6280 | ||
6281 | u8 reserved_at_60[0x20]; | |
6282 | }; | |
6283 | ||
6284 | struct mlx5_ifc_create_xrq_in_bits { | |
6285 | u8 opcode[0x10]; | |
6286 | u8 reserved_at_10[0x10]; | |
6287 | ||
6288 | u8 reserved_at_20[0x10]; | |
6289 | u8 op_mod[0x10]; | |
6290 | ||
6291 | u8 reserved_at_40[0x40]; | |
6292 | ||
6293 | struct mlx5_ifc_xrqc_bits xrq_context; | |
6294 | }; | |
6295 | ||
e281682b SM |
6296 | struct mlx5_ifc_create_xrc_srq_out_bits { |
6297 | u8 status[0x8]; | |
b4ff3a36 | 6298 | u8 reserved_at_8[0x18]; |
e281682b SM |
6299 | |
6300 | u8 syndrome[0x20]; | |
6301 | ||
b4ff3a36 | 6302 | u8 reserved_at_40[0x8]; |
e281682b SM |
6303 | u8 xrc_srqn[0x18]; |
6304 | ||
b4ff3a36 | 6305 | u8 reserved_at_60[0x20]; |
e281682b SM |
6306 | }; |
6307 | ||
6308 | struct mlx5_ifc_create_xrc_srq_in_bits { | |
6309 | u8 opcode[0x10]; | |
b4ff3a36 | 6310 | u8 reserved_at_10[0x10]; |
e281682b | 6311 | |
b4ff3a36 | 6312 | u8 reserved_at_20[0x10]; |
e281682b SM |
6313 | u8 op_mod[0x10]; |
6314 | ||
b4ff3a36 | 6315 | u8 reserved_at_40[0x40]; |
e281682b SM |
6316 | |
6317 | struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry; | |
6318 | ||
b4ff3a36 | 6319 | u8 reserved_at_280[0x600]; |
e281682b SM |
6320 | |
6321 | u8 pas[0][0x40]; | |
6322 | }; | |
6323 | ||
6324 | struct mlx5_ifc_create_tis_out_bits { | |
6325 | u8 status[0x8]; | |
b4ff3a36 | 6326 | u8 reserved_at_8[0x18]; |
e281682b SM |
6327 | |
6328 | u8 syndrome[0x20]; | |
6329 | ||
b4ff3a36 | 6330 | u8 reserved_at_40[0x8]; |
e281682b SM |
6331 | u8 tisn[0x18]; |
6332 | ||
b4ff3a36 | 6333 | u8 reserved_at_60[0x20]; |
e281682b SM |
6334 | }; |
6335 | ||
6336 | struct mlx5_ifc_create_tis_in_bits { | |
6337 | u8 opcode[0x10]; | |
b4ff3a36 | 6338 | u8 reserved_at_10[0x10]; |
e281682b | 6339 | |
b4ff3a36 | 6340 | u8 reserved_at_20[0x10]; |
e281682b SM |
6341 | u8 op_mod[0x10]; |
6342 | ||
b4ff3a36 | 6343 | u8 reserved_at_40[0xc0]; |
e281682b SM |
6344 | |
6345 | struct mlx5_ifc_tisc_bits ctx; | |
6346 | }; | |
6347 | ||
6348 | struct mlx5_ifc_create_tir_out_bits { | |
6349 | u8 status[0x8]; | |
b4ff3a36 | 6350 | u8 reserved_at_8[0x18]; |
e281682b SM |
6351 | |
6352 | u8 syndrome[0x20]; | |
6353 | ||
b4ff3a36 | 6354 | u8 reserved_at_40[0x8]; |
e281682b SM |
6355 | u8 tirn[0x18]; |
6356 | ||
b4ff3a36 | 6357 | u8 reserved_at_60[0x20]; |
e281682b SM |
6358 | }; |
6359 | ||
6360 | struct mlx5_ifc_create_tir_in_bits { | |
6361 | u8 opcode[0x10]; | |
b4ff3a36 | 6362 | u8 reserved_at_10[0x10]; |
e281682b | 6363 | |
b4ff3a36 | 6364 | u8 reserved_at_20[0x10]; |
e281682b SM |
6365 | u8 op_mod[0x10]; |
6366 | ||
b4ff3a36 | 6367 | u8 reserved_at_40[0xc0]; |
e281682b SM |
6368 | |
6369 | struct mlx5_ifc_tirc_bits ctx; | |
6370 | }; | |
6371 | ||
6372 | struct mlx5_ifc_create_srq_out_bits { | |
6373 | u8 status[0x8]; | |
b4ff3a36 | 6374 | u8 reserved_at_8[0x18]; |
e281682b SM |
6375 | |
6376 | u8 syndrome[0x20]; | |
6377 | ||
b4ff3a36 | 6378 | u8 reserved_at_40[0x8]; |
e281682b SM |
6379 | u8 srqn[0x18]; |
6380 | ||
b4ff3a36 | 6381 | u8 reserved_at_60[0x20]; |
e281682b SM |
6382 | }; |
6383 | ||
6384 | struct mlx5_ifc_create_srq_in_bits { | |
6385 | u8 opcode[0x10]; | |
b4ff3a36 | 6386 | u8 reserved_at_10[0x10]; |
e281682b | 6387 | |
b4ff3a36 | 6388 | u8 reserved_at_20[0x10]; |
e281682b SM |
6389 | u8 op_mod[0x10]; |
6390 | ||
b4ff3a36 | 6391 | u8 reserved_at_40[0x40]; |
e281682b SM |
6392 | |
6393 | struct mlx5_ifc_srqc_bits srq_context_entry; | |
6394 | ||
b4ff3a36 | 6395 | u8 reserved_at_280[0x600]; |
e281682b SM |
6396 | |
6397 | u8 pas[0][0x40]; | |
6398 | }; | |
6399 | ||
6400 | struct mlx5_ifc_create_sq_out_bits { | |
6401 | u8 status[0x8]; | |
b4ff3a36 | 6402 | u8 reserved_at_8[0x18]; |
e281682b SM |
6403 | |
6404 | u8 syndrome[0x20]; | |
6405 | ||
b4ff3a36 | 6406 | u8 reserved_at_40[0x8]; |
e281682b SM |
6407 | u8 sqn[0x18]; |
6408 | ||
b4ff3a36 | 6409 | u8 reserved_at_60[0x20]; |
e281682b SM |
6410 | }; |
6411 | ||
6412 | struct mlx5_ifc_create_sq_in_bits { | |
6413 | u8 opcode[0x10]; | |
b4ff3a36 | 6414 | u8 reserved_at_10[0x10]; |
e281682b | 6415 | |
b4ff3a36 | 6416 | u8 reserved_at_20[0x10]; |
e281682b SM |
6417 | u8 op_mod[0x10]; |
6418 | ||
b4ff3a36 | 6419 | u8 reserved_at_40[0xc0]; |
e281682b SM |
6420 | |
6421 | struct mlx5_ifc_sqc_bits ctx; | |
6422 | }; | |
6423 | ||
813f8540 MHY |
6424 | struct mlx5_ifc_create_scheduling_element_out_bits { |
6425 | u8 status[0x8]; | |
6426 | u8 reserved_at_8[0x18]; | |
6427 | ||
6428 | u8 syndrome[0x20]; | |
6429 | ||
6430 | u8 reserved_at_40[0x40]; | |
6431 | ||
6432 | u8 scheduling_element_id[0x20]; | |
6433 | ||
6434 | u8 reserved_at_a0[0x160]; | |
6435 | }; | |
6436 | ||
6437 | struct mlx5_ifc_create_scheduling_element_in_bits { | |
6438 | u8 opcode[0x10]; | |
6439 | u8 reserved_at_10[0x10]; | |
6440 | ||
6441 | u8 reserved_at_20[0x10]; | |
6442 | u8 op_mod[0x10]; | |
6443 | ||
6444 | u8 scheduling_hierarchy[0x8]; | |
6445 | u8 reserved_at_48[0x18]; | |
6446 | ||
6447 | u8 reserved_at_60[0xa0]; | |
6448 | ||
6449 | struct mlx5_ifc_scheduling_context_bits scheduling_context; | |
6450 | ||
6451 | u8 reserved_at_300[0x100]; | |
6452 | }; | |
6453 | ||
e281682b SM |
6454 | struct mlx5_ifc_create_rqt_out_bits { |
6455 | u8 status[0x8]; | |
b4ff3a36 | 6456 | u8 reserved_at_8[0x18]; |
e281682b SM |
6457 | |
6458 | u8 syndrome[0x20]; | |
6459 | ||
b4ff3a36 | 6460 | u8 reserved_at_40[0x8]; |
e281682b SM |
6461 | u8 rqtn[0x18]; |
6462 | ||
b4ff3a36 | 6463 | u8 reserved_at_60[0x20]; |
e281682b SM |
6464 | }; |
6465 | ||
6466 | struct mlx5_ifc_create_rqt_in_bits { | |
6467 | u8 opcode[0x10]; | |
b4ff3a36 | 6468 | u8 reserved_at_10[0x10]; |
e281682b | 6469 | |
b4ff3a36 | 6470 | u8 reserved_at_20[0x10]; |
e281682b SM |
6471 | u8 op_mod[0x10]; |
6472 | ||
b4ff3a36 | 6473 | u8 reserved_at_40[0xc0]; |
e281682b SM |
6474 | |
6475 | struct mlx5_ifc_rqtc_bits rqt_context; | |
6476 | }; | |
6477 | ||
6478 | struct mlx5_ifc_create_rq_out_bits { | |
6479 | u8 status[0x8]; | |
b4ff3a36 | 6480 | u8 reserved_at_8[0x18]; |
e281682b SM |
6481 | |
6482 | u8 syndrome[0x20]; | |
6483 | ||
b4ff3a36 | 6484 | u8 reserved_at_40[0x8]; |
e281682b SM |
6485 | u8 rqn[0x18]; |
6486 | ||
b4ff3a36 | 6487 | u8 reserved_at_60[0x20]; |
e281682b SM |
6488 | }; |
6489 | ||
6490 | struct mlx5_ifc_create_rq_in_bits { | |
6491 | u8 opcode[0x10]; | |
b4ff3a36 | 6492 | u8 reserved_at_10[0x10]; |
e281682b | 6493 | |
b4ff3a36 | 6494 | u8 reserved_at_20[0x10]; |
e281682b SM |
6495 | u8 op_mod[0x10]; |
6496 | ||
b4ff3a36 | 6497 | u8 reserved_at_40[0xc0]; |
e281682b SM |
6498 | |
6499 | struct mlx5_ifc_rqc_bits ctx; | |
6500 | }; | |
6501 | ||
6502 | struct mlx5_ifc_create_rmp_out_bits { | |
6503 | u8 status[0x8]; | |
b4ff3a36 | 6504 | u8 reserved_at_8[0x18]; |
e281682b SM |
6505 | |
6506 | u8 syndrome[0x20]; | |
6507 | ||
b4ff3a36 | 6508 | u8 reserved_at_40[0x8]; |
e281682b SM |
6509 | u8 rmpn[0x18]; |
6510 | ||
b4ff3a36 | 6511 | u8 reserved_at_60[0x20]; |
e281682b SM |
6512 | }; |
6513 | ||
6514 | struct mlx5_ifc_create_rmp_in_bits { | |
6515 | u8 opcode[0x10]; | |
b4ff3a36 | 6516 | u8 reserved_at_10[0x10]; |
e281682b | 6517 | |
b4ff3a36 | 6518 | u8 reserved_at_20[0x10]; |
e281682b SM |
6519 | u8 op_mod[0x10]; |
6520 | ||
b4ff3a36 | 6521 | u8 reserved_at_40[0xc0]; |
e281682b SM |
6522 | |
6523 | struct mlx5_ifc_rmpc_bits ctx; | |
6524 | }; | |
6525 | ||
6526 | struct mlx5_ifc_create_qp_out_bits { | |
6527 | u8 status[0x8]; | |
b4ff3a36 | 6528 | u8 reserved_at_8[0x18]; |
e281682b SM |
6529 | |
6530 | u8 syndrome[0x20]; | |
6531 | ||
b4ff3a36 | 6532 | u8 reserved_at_40[0x8]; |
e281682b SM |
6533 | u8 qpn[0x18]; |
6534 | ||
b4ff3a36 | 6535 | u8 reserved_at_60[0x20]; |
e281682b SM |
6536 | }; |
6537 | ||
6538 | struct mlx5_ifc_create_qp_in_bits { | |
6539 | u8 opcode[0x10]; | |
b4ff3a36 | 6540 | u8 reserved_at_10[0x10]; |
e281682b | 6541 | |
b4ff3a36 | 6542 | u8 reserved_at_20[0x10]; |
e281682b SM |
6543 | u8 op_mod[0x10]; |
6544 | ||
b4ff3a36 | 6545 | u8 reserved_at_40[0x40]; |
e281682b SM |
6546 | |
6547 | u8 opt_param_mask[0x20]; | |
6548 | ||
b4ff3a36 | 6549 | u8 reserved_at_a0[0x20]; |
e281682b SM |
6550 | |
6551 | struct mlx5_ifc_qpc_bits qpc; | |
6552 | ||
b4ff3a36 | 6553 | u8 reserved_at_800[0x80]; |
e281682b SM |
6554 | |
6555 | u8 pas[0][0x40]; | |
6556 | }; | |
6557 | ||
6558 | struct mlx5_ifc_create_psv_out_bits { | |
6559 | u8 status[0x8]; | |
b4ff3a36 | 6560 | u8 reserved_at_8[0x18]; |
e281682b SM |
6561 | |
6562 | u8 syndrome[0x20]; | |
6563 | ||
b4ff3a36 | 6564 | u8 reserved_at_40[0x40]; |
e281682b | 6565 | |
b4ff3a36 | 6566 | u8 reserved_at_80[0x8]; |
e281682b SM |
6567 | u8 psv0_index[0x18]; |
6568 | ||
b4ff3a36 | 6569 | u8 reserved_at_a0[0x8]; |
e281682b SM |
6570 | u8 psv1_index[0x18]; |
6571 | ||
b4ff3a36 | 6572 | u8 reserved_at_c0[0x8]; |
e281682b SM |
6573 | u8 psv2_index[0x18]; |
6574 | ||
b4ff3a36 | 6575 | u8 reserved_at_e0[0x8]; |
e281682b SM |
6576 | u8 psv3_index[0x18]; |
6577 | }; | |
6578 | ||
6579 | struct mlx5_ifc_create_psv_in_bits { | |
6580 | u8 opcode[0x10]; | |
b4ff3a36 | 6581 | u8 reserved_at_10[0x10]; |
e281682b | 6582 | |
b4ff3a36 | 6583 | u8 reserved_at_20[0x10]; |
e281682b SM |
6584 | u8 op_mod[0x10]; |
6585 | ||
6586 | u8 num_psv[0x4]; | |
b4ff3a36 | 6587 | u8 reserved_at_44[0x4]; |
e281682b SM |
6588 | u8 pd[0x18]; |
6589 | ||
b4ff3a36 | 6590 | u8 reserved_at_60[0x20]; |
e281682b SM |
6591 | }; |
6592 | ||
6593 | struct mlx5_ifc_create_mkey_out_bits { | |
6594 | u8 status[0x8]; | |
b4ff3a36 | 6595 | u8 reserved_at_8[0x18]; |
e281682b SM |
6596 | |
6597 | u8 syndrome[0x20]; | |
6598 | ||
b4ff3a36 | 6599 | u8 reserved_at_40[0x8]; |
e281682b SM |
6600 | u8 mkey_index[0x18]; |
6601 | ||
b4ff3a36 | 6602 | u8 reserved_at_60[0x20]; |
e281682b SM |
6603 | }; |
6604 | ||
6605 | struct mlx5_ifc_create_mkey_in_bits { | |
6606 | u8 opcode[0x10]; | |
b4ff3a36 | 6607 | u8 reserved_at_10[0x10]; |
e281682b | 6608 | |
b4ff3a36 | 6609 | u8 reserved_at_20[0x10]; |
e281682b SM |
6610 | u8 op_mod[0x10]; |
6611 | ||
b4ff3a36 | 6612 | u8 reserved_at_40[0x20]; |
e281682b SM |
6613 | |
6614 | u8 pg_access[0x1]; | |
b4ff3a36 | 6615 | u8 reserved_at_61[0x1f]; |
e281682b SM |
6616 | |
6617 | struct mlx5_ifc_mkc_bits memory_key_mkey_entry; | |
6618 | ||
b4ff3a36 | 6619 | u8 reserved_at_280[0x80]; |
e281682b SM |
6620 | |
6621 | u8 translations_octword_actual_size[0x20]; | |
6622 | ||
b4ff3a36 | 6623 | u8 reserved_at_320[0x560]; |
e281682b SM |
6624 | |
6625 | u8 klm_pas_mtt[0][0x20]; | |
6626 | }; | |
6627 | ||
6628 | struct mlx5_ifc_create_flow_table_out_bits { | |
6629 | u8 status[0x8]; | |
b4ff3a36 | 6630 | u8 reserved_at_8[0x18]; |
e281682b SM |
6631 | |
6632 | u8 syndrome[0x20]; | |
6633 | ||
b4ff3a36 | 6634 | u8 reserved_at_40[0x8]; |
e281682b SM |
6635 | u8 table_id[0x18]; |
6636 | ||
b4ff3a36 | 6637 | u8 reserved_at_60[0x20]; |
e281682b SM |
6638 | }; |
6639 | ||
0c90e9c6 MG |
6640 | struct mlx5_ifc_flow_table_context_bits { |
6641 | u8 encap_en[0x1]; | |
6642 | u8 decap_en[0x1]; | |
6643 | u8 reserved_at_2[0x2]; | |
6644 | u8 table_miss_action[0x4]; | |
6645 | u8 level[0x8]; | |
6646 | u8 reserved_at_10[0x8]; | |
6647 | u8 log_size[0x8]; | |
6648 | ||
6649 | u8 reserved_at_20[0x8]; | |
6650 | u8 table_miss_id[0x18]; | |
6651 | ||
6652 | u8 reserved_at_40[0x8]; | |
6653 | u8 lag_master_next_table_id[0x18]; | |
6654 | ||
6655 | u8 reserved_at_60[0xe0]; | |
6656 | }; | |
6657 | ||
e281682b SM |
6658 | struct mlx5_ifc_create_flow_table_in_bits { |
6659 | u8 opcode[0x10]; | |
b4ff3a36 | 6660 | u8 reserved_at_10[0x10]; |
e281682b | 6661 | |
b4ff3a36 | 6662 | u8 reserved_at_20[0x10]; |
e281682b SM |
6663 | u8 op_mod[0x10]; |
6664 | ||
7d5e1423 SM |
6665 | u8 other_vport[0x1]; |
6666 | u8 reserved_at_41[0xf]; | |
6667 | u8 vport_number[0x10]; | |
6668 | ||
6669 | u8 reserved_at_60[0x20]; | |
e281682b SM |
6670 | |
6671 | u8 table_type[0x8]; | |
b4ff3a36 | 6672 | u8 reserved_at_88[0x18]; |
e281682b | 6673 | |
b4ff3a36 | 6674 | u8 reserved_at_a0[0x20]; |
e281682b | 6675 | |
0c90e9c6 | 6676 | struct mlx5_ifc_flow_table_context_bits flow_table_context; |
e281682b SM |
6677 | }; |
6678 | ||
6679 | struct mlx5_ifc_create_flow_group_out_bits { | |
6680 | u8 status[0x8]; | |
b4ff3a36 | 6681 | u8 reserved_at_8[0x18]; |
e281682b SM |
6682 | |
6683 | u8 syndrome[0x20]; | |
6684 | ||
b4ff3a36 | 6685 | u8 reserved_at_40[0x8]; |
e281682b SM |
6686 | u8 group_id[0x18]; |
6687 | ||
b4ff3a36 | 6688 | u8 reserved_at_60[0x20]; |
e281682b SM |
6689 | }; |
6690 | ||
6691 | enum { | |
6692 | MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0, | |
6693 | MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1, | |
6694 | MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2, | |
6695 | }; | |
6696 | ||
6697 | struct mlx5_ifc_create_flow_group_in_bits { | |
6698 | u8 opcode[0x10]; | |
b4ff3a36 | 6699 | u8 reserved_at_10[0x10]; |
e281682b | 6700 | |
b4ff3a36 | 6701 | u8 reserved_at_20[0x10]; |
e281682b SM |
6702 | u8 op_mod[0x10]; |
6703 | ||
7d5e1423 SM |
6704 | u8 other_vport[0x1]; |
6705 | u8 reserved_at_41[0xf]; | |
6706 | u8 vport_number[0x10]; | |
6707 | ||
6708 | u8 reserved_at_60[0x20]; | |
e281682b SM |
6709 | |
6710 | u8 table_type[0x8]; | |
b4ff3a36 | 6711 | u8 reserved_at_88[0x18]; |
e281682b | 6712 | |
b4ff3a36 | 6713 | u8 reserved_at_a0[0x8]; |
e281682b SM |
6714 | u8 table_id[0x18]; |
6715 | ||
b4ff3a36 | 6716 | u8 reserved_at_c0[0x20]; |
e281682b SM |
6717 | |
6718 | u8 start_flow_index[0x20]; | |
6719 | ||
b4ff3a36 | 6720 | u8 reserved_at_100[0x20]; |
e281682b SM |
6721 | |
6722 | u8 end_flow_index[0x20]; | |
6723 | ||
b4ff3a36 | 6724 | u8 reserved_at_140[0xa0]; |
e281682b | 6725 | |
b4ff3a36 | 6726 | u8 reserved_at_1e0[0x18]; |
e281682b SM |
6727 | u8 match_criteria_enable[0x8]; |
6728 | ||
6729 | struct mlx5_ifc_fte_match_param_bits match_criteria; | |
6730 | ||
b4ff3a36 | 6731 | u8 reserved_at_1200[0xe00]; |
e281682b SM |
6732 | }; |
6733 | ||
6734 | struct mlx5_ifc_create_eq_out_bits { | |
6735 | u8 status[0x8]; | |
b4ff3a36 | 6736 | u8 reserved_at_8[0x18]; |
e281682b SM |
6737 | |
6738 | u8 syndrome[0x20]; | |
6739 | ||
b4ff3a36 | 6740 | u8 reserved_at_40[0x18]; |
e281682b SM |
6741 | u8 eq_number[0x8]; |
6742 | ||
b4ff3a36 | 6743 | u8 reserved_at_60[0x20]; |
e281682b SM |
6744 | }; |
6745 | ||
6746 | struct mlx5_ifc_create_eq_in_bits { | |
6747 | u8 opcode[0x10]; | |
b4ff3a36 | 6748 | u8 reserved_at_10[0x10]; |
e281682b | 6749 | |
b4ff3a36 | 6750 | u8 reserved_at_20[0x10]; |
e281682b SM |
6751 | u8 op_mod[0x10]; |
6752 | ||
b4ff3a36 | 6753 | u8 reserved_at_40[0x40]; |
e281682b SM |
6754 | |
6755 | struct mlx5_ifc_eqc_bits eq_context_entry; | |
6756 | ||
b4ff3a36 | 6757 | u8 reserved_at_280[0x40]; |
e281682b SM |
6758 | |
6759 | u8 event_bitmask[0x40]; | |
6760 | ||
b4ff3a36 | 6761 | u8 reserved_at_300[0x580]; |
e281682b SM |
6762 | |
6763 | u8 pas[0][0x40]; | |
6764 | }; | |
6765 | ||
6766 | struct mlx5_ifc_create_dct_out_bits { | |
6767 | u8 status[0x8]; | |
b4ff3a36 | 6768 | u8 reserved_at_8[0x18]; |
e281682b SM |
6769 | |
6770 | u8 syndrome[0x20]; | |
6771 | ||
b4ff3a36 | 6772 | u8 reserved_at_40[0x8]; |
e281682b SM |
6773 | u8 dctn[0x18]; |
6774 | ||
b4ff3a36 | 6775 | u8 reserved_at_60[0x20]; |
e281682b SM |
6776 | }; |
6777 | ||
6778 | struct mlx5_ifc_create_dct_in_bits { | |
6779 | u8 opcode[0x10]; | |
b4ff3a36 | 6780 | u8 reserved_at_10[0x10]; |
e281682b | 6781 | |
b4ff3a36 | 6782 | u8 reserved_at_20[0x10]; |
e281682b SM |
6783 | u8 op_mod[0x10]; |
6784 | ||
b4ff3a36 | 6785 | u8 reserved_at_40[0x40]; |
e281682b SM |
6786 | |
6787 | struct mlx5_ifc_dctc_bits dct_context_entry; | |
6788 | ||
b4ff3a36 | 6789 | u8 reserved_at_280[0x180]; |
e281682b SM |
6790 | }; |
6791 | ||
6792 | struct mlx5_ifc_create_cq_out_bits { | |
6793 | u8 status[0x8]; | |
b4ff3a36 | 6794 | u8 reserved_at_8[0x18]; |
e281682b SM |
6795 | |
6796 | u8 syndrome[0x20]; | |
6797 | ||
b4ff3a36 | 6798 | u8 reserved_at_40[0x8]; |
e281682b SM |
6799 | u8 cqn[0x18]; |
6800 | ||
b4ff3a36 | 6801 | u8 reserved_at_60[0x20]; |
e281682b SM |
6802 | }; |
6803 | ||
6804 | struct mlx5_ifc_create_cq_in_bits { | |
6805 | u8 opcode[0x10]; | |
b4ff3a36 | 6806 | u8 reserved_at_10[0x10]; |
e281682b | 6807 | |
b4ff3a36 | 6808 | u8 reserved_at_20[0x10]; |
e281682b SM |
6809 | u8 op_mod[0x10]; |
6810 | ||
b4ff3a36 | 6811 | u8 reserved_at_40[0x40]; |
e281682b SM |
6812 | |
6813 | struct mlx5_ifc_cqc_bits cq_context; | |
6814 | ||
b4ff3a36 | 6815 | u8 reserved_at_280[0x600]; |
e281682b SM |
6816 | |
6817 | u8 pas[0][0x40]; | |
6818 | }; | |
6819 | ||
6820 | struct mlx5_ifc_config_int_moderation_out_bits { | |
6821 | u8 status[0x8]; | |
b4ff3a36 | 6822 | u8 reserved_at_8[0x18]; |
e281682b SM |
6823 | |
6824 | u8 syndrome[0x20]; | |
6825 | ||
b4ff3a36 | 6826 | u8 reserved_at_40[0x4]; |
e281682b SM |
6827 | u8 min_delay[0xc]; |
6828 | u8 int_vector[0x10]; | |
6829 | ||
b4ff3a36 | 6830 | u8 reserved_at_60[0x20]; |
e281682b SM |
6831 | }; |
6832 | ||
6833 | enum { | |
6834 | MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0, | |
6835 | MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1, | |
6836 | }; | |
6837 | ||
6838 | struct mlx5_ifc_config_int_moderation_in_bits { | |
6839 | u8 opcode[0x10]; | |
b4ff3a36 | 6840 | u8 reserved_at_10[0x10]; |
e281682b | 6841 | |
b4ff3a36 | 6842 | u8 reserved_at_20[0x10]; |
e281682b SM |
6843 | u8 op_mod[0x10]; |
6844 | ||
b4ff3a36 | 6845 | u8 reserved_at_40[0x4]; |
e281682b SM |
6846 | u8 min_delay[0xc]; |
6847 | u8 int_vector[0x10]; | |
6848 | ||
b4ff3a36 | 6849 | u8 reserved_at_60[0x20]; |
e281682b SM |
6850 | }; |
6851 | ||
6852 | struct mlx5_ifc_attach_to_mcg_out_bits { | |
6853 | u8 status[0x8]; | |
b4ff3a36 | 6854 | u8 reserved_at_8[0x18]; |
e281682b SM |
6855 | |
6856 | u8 syndrome[0x20]; | |
6857 | ||
b4ff3a36 | 6858 | u8 reserved_at_40[0x40]; |
e281682b SM |
6859 | }; |
6860 | ||
6861 | struct mlx5_ifc_attach_to_mcg_in_bits { | |
6862 | u8 opcode[0x10]; | |
b4ff3a36 | 6863 | u8 reserved_at_10[0x10]; |
e281682b | 6864 | |
b4ff3a36 | 6865 | u8 reserved_at_20[0x10]; |
e281682b SM |
6866 | u8 op_mod[0x10]; |
6867 | ||
b4ff3a36 | 6868 | u8 reserved_at_40[0x8]; |
e281682b SM |
6869 | u8 qpn[0x18]; |
6870 | ||
b4ff3a36 | 6871 | u8 reserved_at_60[0x20]; |
e281682b SM |
6872 | |
6873 | u8 multicast_gid[16][0x8]; | |
6874 | }; | |
6875 | ||
7486216b SM |
6876 | struct mlx5_ifc_arm_xrq_out_bits { |
6877 | u8 status[0x8]; | |
6878 | u8 reserved_at_8[0x18]; | |
6879 | ||
6880 | u8 syndrome[0x20]; | |
6881 | ||
6882 | u8 reserved_at_40[0x40]; | |
6883 | }; | |
6884 | ||
6885 | struct mlx5_ifc_arm_xrq_in_bits { | |
6886 | u8 opcode[0x10]; | |
6887 | u8 reserved_at_10[0x10]; | |
6888 | ||
6889 | u8 reserved_at_20[0x10]; | |
6890 | u8 op_mod[0x10]; | |
6891 | ||
6892 | u8 reserved_at_40[0x8]; | |
6893 | u8 xrqn[0x18]; | |
6894 | ||
6895 | u8 reserved_at_60[0x10]; | |
6896 | u8 lwm[0x10]; | |
6897 | }; | |
6898 | ||
e281682b SM |
6899 | struct mlx5_ifc_arm_xrc_srq_out_bits { |
6900 | u8 status[0x8]; | |
b4ff3a36 | 6901 | u8 reserved_at_8[0x18]; |
e281682b SM |
6902 | |
6903 | u8 syndrome[0x20]; | |
6904 | ||
b4ff3a36 | 6905 | u8 reserved_at_40[0x40]; |
e281682b SM |
6906 | }; |
6907 | ||
6908 | enum { | |
6909 | MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1, | |
6910 | }; | |
6911 | ||
6912 | struct mlx5_ifc_arm_xrc_srq_in_bits { | |
6913 | u8 opcode[0x10]; | |
b4ff3a36 | 6914 | u8 reserved_at_10[0x10]; |
e281682b | 6915 | |
b4ff3a36 | 6916 | u8 reserved_at_20[0x10]; |
e281682b SM |
6917 | u8 op_mod[0x10]; |
6918 | ||
b4ff3a36 | 6919 | u8 reserved_at_40[0x8]; |
e281682b SM |
6920 | u8 xrc_srqn[0x18]; |
6921 | ||
b4ff3a36 | 6922 | u8 reserved_at_60[0x10]; |
e281682b SM |
6923 | u8 lwm[0x10]; |
6924 | }; | |
6925 | ||
6926 | struct mlx5_ifc_arm_rq_out_bits { | |
6927 | u8 status[0x8]; | |
b4ff3a36 | 6928 | u8 reserved_at_8[0x18]; |
e281682b SM |
6929 | |
6930 | u8 syndrome[0x20]; | |
6931 | ||
b4ff3a36 | 6932 | u8 reserved_at_40[0x40]; |
e281682b SM |
6933 | }; |
6934 | ||
6935 | enum { | |
7486216b SM |
6936 | MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1, |
6937 | MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2, | |
e281682b SM |
6938 | }; |
6939 | ||
6940 | struct mlx5_ifc_arm_rq_in_bits { | |
6941 | u8 opcode[0x10]; | |
b4ff3a36 | 6942 | u8 reserved_at_10[0x10]; |
e281682b | 6943 | |
b4ff3a36 | 6944 | u8 reserved_at_20[0x10]; |
e281682b SM |
6945 | u8 op_mod[0x10]; |
6946 | ||
b4ff3a36 | 6947 | u8 reserved_at_40[0x8]; |
e281682b SM |
6948 | u8 srq_number[0x18]; |
6949 | ||
b4ff3a36 | 6950 | u8 reserved_at_60[0x10]; |
e281682b SM |
6951 | u8 lwm[0x10]; |
6952 | }; | |
6953 | ||
6954 | struct mlx5_ifc_arm_dct_out_bits { | |
6955 | u8 status[0x8]; | |
b4ff3a36 | 6956 | u8 reserved_at_8[0x18]; |
e281682b SM |
6957 | |
6958 | u8 syndrome[0x20]; | |
6959 | ||
b4ff3a36 | 6960 | u8 reserved_at_40[0x40]; |
e281682b SM |
6961 | }; |
6962 | ||
6963 | struct mlx5_ifc_arm_dct_in_bits { | |
6964 | u8 opcode[0x10]; | |
b4ff3a36 | 6965 | u8 reserved_at_10[0x10]; |
e281682b | 6966 | |
b4ff3a36 | 6967 | u8 reserved_at_20[0x10]; |
e281682b SM |
6968 | u8 op_mod[0x10]; |
6969 | ||
b4ff3a36 | 6970 | u8 reserved_at_40[0x8]; |
e281682b SM |
6971 | u8 dct_number[0x18]; |
6972 | ||
b4ff3a36 | 6973 | u8 reserved_at_60[0x20]; |
e281682b SM |
6974 | }; |
6975 | ||
6976 | struct mlx5_ifc_alloc_xrcd_out_bits { | |
6977 | u8 status[0x8]; | |
b4ff3a36 | 6978 | u8 reserved_at_8[0x18]; |
e281682b SM |
6979 | |
6980 | u8 syndrome[0x20]; | |
6981 | ||
b4ff3a36 | 6982 | u8 reserved_at_40[0x8]; |
e281682b SM |
6983 | u8 xrcd[0x18]; |
6984 | ||
b4ff3a36 | 6985 | u8 reserved_at_60[0x20]; |
e281682b SM |
6986 | }; |
6987 | ||
6988 | struct mlx5_ifc_alloc_xrcd_in_bits { | |
6989 | u8 opcode[0x10]; | |
b4ff3a36 | 6990 | u8 reserved_at_10[0x10]; |
e281682b | 6991 | |
b4ff3a36 | 6992 | u8 reserved_at_20[0x10]; |
e281682b SM |
6993 | u8 op_mod[0x10]; |
6994 | ||
b4ff3a36 | 6995 | u8 reserved_at_40[0x40]; |
e281682b SM |
6996 | }; |
6997 | ||
6998 | struct mlx5_ifc_alloc_uar_out_bits { | |
6999 | u8 status[0x8]; | |
b4ff3a36 | 7000 | u8 reserved_at_8[0x18]; |
e281682b SM |
7001 | |
7002 | u8 syndrome[0x20]; | |
7003 | ||
b4ff3a36 | 7004 | u8 reserved_at_40[0x8]; |
e281682b SM |
7005 | u8 uar[0x18]; |
7006 | ||
b4ff3a36 | 7007 | u8 reserved_at_60[0x20]; |
e281682b SM |
7008 | }; |
7009 | ||
7010 | struct mlx5_ifc_alloc_uar_in_bits { | |
7011 | u8 opcode[0x10]; | |
b4ff3a36 | 7012 | u8 reserved_at_10[0x10]; |
e281682b | 7013 | |
b4ff3a36 | 7014 | u8 reserved_at_20[0x10]; |
e281682b SM |
7015 | u8 op_mod[0x10]; |
7016 | ||
b4ff3a36 | 7017 | u8 reserved_at_40[0x40]; |
e281682b SM |
7018 | }; |
7019 | ||
7020 | struct mlx5_ifc_alloc_transport_domain_out_bits { | |
7021 | u8 status[0x8]; | |
b4ff3a36 | 7022 | u8 reserved_at_8[0x18]; |
e281682b SM |
7023 | |
7024 | u8 syndrome[0x20]; | |
7025 | ||
b4ff3a36 | 7026 | u8 reserved_at_40[0x8]; |
e281682b SM |
7027 | u8 transport_domain[0x18]; |
7028 | ||
b4ff3a36 | 7029 | u8 reserved_at_60[0x20]; |
e281682b SM |
7030 | }; |
7031 | ||
7032 | struct mlx5_ifc_alloc_transport_domain_in_bits { | |
7033 | u8 opcode[0x10]; | |
b4ff3a36 | 7034 | u8 reserved_at_10[0x10]; |
e281682b | 7035 | |
b4ff3a36 | 7036 | u8 reserved_at_20[0x10]; |
e281682b SM |
7037 | u8 op_mod[0x10]; |
7038 | ||
b4ff3a36 | 7039 | u8 reserved_at_40[0x40]; |
e281682b SM |
7040 | }; |
7041 | ||
7042 | struct mlx5_ifc_alloc_q_counter_out_bits { | |
7043 | u8 status[0x8]; | |
b4ff3a36 | 7044 | u8 reserved_at_8[0x18]; |
e281682b SM |
7045 | |
7046 | u8 syndrome[0x20]; | |
7047 | ||
b4ff3a36 | 7048 | u8 reserved_at_40[0x18]; |
e281682b SM |
7049 | u8 counter_set_id[0x8]; |
7050 | ||
b4ff3a36 | 7051 | u8 reserved_at_60[0x20]; |
e281682b SM |
7052 | }; |
7053 | ||
7054 | struct mlx5_ifc_alloc_q_counter_in_bits { | |
7055 | u8 opcode[0x10]; | |
b4ff3a36 | 7056 | u8 reserved_at_10[0x10]; |
e281682b | 7057 | |
b4ff3a36 | 7058 | u8 reserved_at_20[0x10]; |
e281682b SM |
7059 | u8 op_mod[0x10]; |
7060 | ||
b4ff3a36 | 7061 | u8 reserved_at_40[0x40]; |
e281682b SM |
7062 | }; |
7063 | ||
7064 | struct mlx5_ifc_alloc_pd_out_bits { | |
7065 | u8 status[0x8]; | |
b4ff3a36 | 7066 | u8 reserved_at_8[0x18]; |
e281682b SM |
7067 | |
7068 | u8 syndrome[0x20]; | |
7069 | ||
b4ff3a36 | 7070 | u8 reserved_at_40[0x8]; |
e281682b SM |
7071 | u8 pd[0x18]; |
7072 | ||
b4ff3a36 | 7073 | u8 reserved_at_60[0x20]; |
e281682b SM |
7074 | }; |
7075 | ||
7076 | struct mlx5_ifc_alloc_pd_in_bits { | |
9dc0b289 AV |
7077 | u8 opcode[0x10]; |
7078 | u8 reserved_at_10[0x10]; | |
7079 | ||
7080 | u8 reserved_at_20[0x10]; | |
7081 | u8 op_mod[0x10]; | |
7082 | ||
7083 | u8 reserved_at_40[0x40]; | |
7084 | }; | |
7085 | ||
7086 | struct mlx5_ifc_alloc_flow_counter_out_bits { | |
7087 | u8 status[0x8]; | |
7088 | u8 reserved_at_8[0x18]; | |
7089 | ||
7090 | u8 syndrome[0x20]; | |
7091 | ||
7092 | u8 reserved_at_40[0x10]; | |
7093 | u8 flow_counter_id[0x10]; | |
7094 | ||
7095 | u8 reserved_at_60[0x20]; | |
7096 | }; | |
7097 | ||
7098 | struct mlx5_ifc_alloc_flow_counter_in_bits { | |
e281682b | 7099 | u8 opcode[0x10]; |
b4ff3a36 | 7100 | u8 reserved_at_10[0x10]; |
e281682b | 7101 | |
b4ff3a36 | 7102 | u8 reserved_at_20[0x10]; |
e281682b SM |
7103 | u8 op_mod[0x10]; |
7104 | ||
b4ff3a36 | 7105 | u8 reserved_at_40[0x40]; |
e281682b SM |
7106 | }; |
7107 | ||
7108 | struct mlx5_ifc_add_vxlan_udp_dport_out_bits { | |
7109 | u8 status[0x8]; | |
b4ff3a36 | 7110 | u8 reserved_at_8[0x18]; |
e281682b SM |
7111 | |
7112 | u8 syndrome[0x20]; | |
7113 | ||
b4ff3a36 | 7114 | u8 reserved_at_40[0x40]; |
e281682b SM |
7115 | }; |
7116 | ||
7117 | struct mlx5_ifc_add_vxlan_udp_dport_in_bits { | |
7118 | u8 opcode[0x10]; | |
b4ff3a36 | 7119 | u8 reserved_at_10[0x10]; |
e281682b | 7120 | |
b4ff3a36 | 7121 | u8 reserved_at_20[0x10]; |
e281682b SM |
7122 | u8 op_mod[0x10]; |
7123 | ||
b4ff3a36 | 7124 | u8 reserved_at_40[0x20]; |
e281682b | 7125 | |
b4ff3a36 | 7126 | u8 reserved_at_60[0x10]; |
e281682b SM |
7127 | u8 vxlan_udp_port[0x10]; |
7128 | }; | |
7129 | ||
7486216b SM |
7130 | struct mlx5_ifc_set_rate_limit_out_bits { |
7131 | u8 status[0x8]; | |
7132 | u8 reserved_at_8[0x18]; | |
7133 | ||
7134 | u8 syndrome[0x20]; | |
7135 | ||
7136 | u8 reserved_at_40[0x40]; | |
7137 | }; | |
7138 | ||
7139 | struct mlx5_ifc_set_rate_limit_in_bits { | |
7140 | u8 opcode[0x10]; | |
7141 | u8 reserved_at_10[0x10]; | |
7142 | ||
7143 | u8 reserved_at_20[0x10]; | |
7144 | u8 op_mod[0x10]; | |
7145 | ||
7146 | u8 reserved_at_40[0x10]; | |
7147 | u8 rate_limit_index[0x10]; | |
7148 | ||
7149 | u8 reserved_at_60[0x20]; | |
7150 | ||
7151 | u8 rate_limit[0x20]; | |
7152 | }; | |
7153 | ||
e281682b SM |
7154 | struct mlx5_ifc_access_register_out_bits { |
7155 | u8 status[0x8]; | |
b4ff3a36 | 7156 | u8 reserved_at_8[0x18]; |
e281682b SM |
7157 | |
7158 | u8 syndrome[0x20]; | |
7159 | ||
b4ff3a36 | 7160 | u8 reserved_at_40[0x40]; |
e281682b SM |
7161 | |
7162 | u8 register_data[0][0x20]; | |
7163 | }; | |
7164 | ||
7165 | enum { | |
7166 | MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0, | |
7167 | MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1, | |
7168 | }; | |
7169 | ||
7170 | struct mlx5_ifc_access_register_in_bits { | |
7171 | u8 opcode[0x10]; | |
b4ff3a36 | 7172 | u8 reserved_at_10[0x10]; |
e281682b | 7173 | |
b4ff3a36 | 7174 | u8 reserved_at_20[0x10]; |
e281682b SM |
7175 | u8 op_mod[0x10]; |
7176 | ||
b4ff3a36 | 7177 | u8 reserved_at_40[0x10]; |
e281682b SM |
7178 | u8 register_id[0x10]; |
7179 | ||
7180 | u8 argument[0x20]; | |
7181 | ||
7182 | u8 register_data[0][0x20]; | |
7183 | }; | |
7184 | ||
7185 | struct mlx5_ifc_sltp_reg_bits { | |
7186 | u8 status[0x4]; | |
7187 | u8 version[0x4]; | |
7188 | u8 local_port[0x8]; | |
7189 | u8 pnat[0x2]; | |
b4ff3a36 | 7190 | u8 reserved_at_12[0x2]; |
e281682b | 7191 | u8 lane[0x4]; |
b4ff3a36 | 7192 | u8 reserved_at_18[0x8]; |
e281682b | 7193 | |
b4ff3a36 | 7194 | u8 reserved_at_20[0x20]; |
e281682b | 7195 | |
b4ff3a36 | 7196 | u8 reserved_at_40[0x7]; |
e281682b SM |
7197 | u8 polarity[0x1]; |
7198 | u8 ob_tap0[0x8]; | |
7199 | u8 ob_tap1[0x8]; | |
7200 | u8 ob_tap2[0x8]; | |
7201 | ||
b4ff3a36 | 7202 | u8 reserved_at_60[0xc]; |
e281682b SM |
7203 | u8 ob_preemp_mode[0x4]; |
7204 | u8 ob_reg[0x8]; | |
7205 | u8 ob_bias[0x8]; | |
7206 | ||
b4ff3a36 | 7207 | u8 reserved_at_80[0x20]; |
e281682b SM |
7208 | }; |
7209 | ||
7210 | struct mlx5_ifc_slrg_reg_bits { | |
7211 | u8 status[0x4]; | |
7212 | u8 version[0x4]; | |
7213 | u8 local_port[0x8]; | |
7214 | u8 pnat[0x2]; | |
b4ff3a36 | 7215 | u8 reserved_at_12[0x2]; |
e281682b | 7216 | u8 lane[0x4]; |
b4ff3a36 | 7217 | u8 reserved_at_18[0x8]; |
e281682b SM |
7218 | |
7219 | u8 time_to_link_up[0x10]; | |
b4ff3a36 | 7220 | u8 reserved_at_30[0xc]; |
e281682b SM |
7221 | u8 grade_lane_speed[0x4]; |
7222 | ||
7223 | u8 grade_version[0x8]; | |
7224 | u8 grade[0x18]; | |
7225 | ||
b4ff3a36 | 7226 | u8 reserved_at_60[0x4]; |
e281682b SM |
7227 | u8 height_grade_type[0x4]; |
7228 | u8 height_grade[0x18]; | |
7229 | ||
7230 | u8 height_dz[0x10]; | |
7231 | u8 height_dv[0x10]; | |
7232 | ||
b4ff3a36 | 7233 | u8 reserved_at_a0[0x10]; |
e281682b SM |
7234 | u8 height_sigma[0x10]; |
7235 | ||
b4ff3a36 | 7236 | u8 reserved_at_c0[0x20]; |
e281682b | 7237 | |
b4ff3a36 | 7238 | u8 reserved_at_e0[0x4]; |
e281682b SM |
7239 | u8 phase_grade_type[0x4]; |
7240 | u8 phase_grade[0x18]; | |
7241 | ||
b4ff3a36 | 7242 | u8 reserved_at_100[0x8]; |
e281682b | 7243 | u8 phase_eo_pos[0x8]; |
b4ff3a36 | 7244 | u8 reserved_at_110[0x8]; |
e281682b SM |
7245 | u8 phase_eo_neg[0x8]; |
7246 | ||
7247 | u8 ffe_set_tested[0x10]; | |
7248 | u8 test_errors_per_lane[0x10]; | |
7249 | }; | |
7250 | ||
7251 | struct mlx5_ifc_pvlc_reg_bits { | |
b4ff3a36 | 7252 | u8 reserved_at_0[0x8]; |
e281682b | 7253 | u8 local_port[0x8]; |
b4ff3a36 | 7254 | u8 reserved_at_10[0x10]; |
e281682b | 7255 | |
b4ff3a36 | 7256 | u8 reserved_at_20[0x1c]; |
e281682b SM |
7257 | u8 vl_hw_cap[0x4]; |
7258 | ||
b4ff3a36 | 7259 | u8 reserved_at_40[0x1c]; |
e281682b SM |
7260 | u8 vl_admin[0x4]; |
7261 | ||
b4ff3a36 | 7262 | u8 reserved_at_60[0x1c]; |
e281682b SM |
7263 | u8 vl_operational[0x4]; |
7264 | }; | |
7265 | ||
7266 | struct mlx5_ifc_pude_reg_bits { | |
7267 | u8 swid[0x8]; | |
7268 | u8 local_port[0x8]; | |
b4ff3a36 | 7269 | u8 reserved_at_10[0x4]; |
e281682b | 7270 | u8 admin_status[0x4]; |
b4ff3a36 | 7271 | u8 reserved_at_18[0x4]; |
e281682b SM |
7272 | u8 oper_status[0x4]; |
7273 | ||
b4ff3a36 | 7274 | u8 reserved_at_20[0x60]; |
e281682b SM |
7275 | }; |
7276 | ||
7277 | struct mlx5_ifc_ptys_reg_bits { | |
e7e31ca4 | 7278 | u8 reserved_at_0[0x1]; |
7486216b | 7279 | u8 an_disable_admin[0x1]; |
e7e31ca4 BW |
7280 | u8 an_disable_cap[0x1]; |
7281 | u8 reserved_at_3[0x5]; | |
e281682b | 7282 | u8 local_port[0x8]; |
b4ff3a36 | 7283 | u8 reserved_at_10[0xd]; |
e281682b SM |
7284 | u8 proto_mask[0x3]; |
7285 | ||
7486216b SM |
7286 | u8 an_status[0x4]; |
7287 | u8 reserved_at_24[0x3c]; | |
e281682b SM |
7288 | |
7289 | u8 eth_proto_capability[0x20]; | |
7290 | ||
7291 | u8 ib_link_width_capability[0x10]; | |
7292 | u8 ib_proto_capability[0x10]; | |
7293 | ||
b4ff3a36 | 7294 | u8 reserved_at_a0[0x20]; |
e281682b SM |
7295 | |
7296 | u8 eth_proto_admin[0x20]; | |
7297 | ||
7298 | u8 ib_link_width_admin[0x10]; | |
7299 | u8 ib_proto_admin[0x10]; | |
7300 | ||
b4ff3a36 | 7301 | u8 reserved_at_100[0x20]; |
e281682b SM |
7302 | |
7303 | u8 eth_proto_oper[0x20]; | |
7304 | ||
7305 | u8 ib_link_width_oper[0x10]; | |
7306 | u8 ib_proto_oper[0x10]; | |
7307 | ||
5b4793f8 EBE |
7308 | u8 reserved_at_160[0x1c]; |
7309 | u8 connector_type[0x4]; | |
e281682b SM |
7310 | |
7311 | u8 eth_proto_lp_advertise[0x20]; | |
7312 | ||
b4ff3a36 | 7313 | u8 reserved_at_1a0[0x60]; |
e281682b SM |
7314 | }; |
7315 | ||
7d5e1423 SM |
7316 | struct mlx5_ifc_mlcr_reg_bits { |
7317 | u8 reserved_at_0[0x8]; | |
7318 | u8 local_port[0x8]; | |
7319 | u8 reserved_at_10[0x20]; | |
7320 | ||
7321 | u8 beacon_duration[0x10]; | |
7322 | u8 reserved_at_40[0x10]; | |
7323 | ||
7324 | u8 beacon_remain[0x10]; | |
7325 | }; | |
7326 | ||
e281682b | 7327 | struct mlx5_ifc_ptas_reg_bits { |
b4ff3a36 | 7328 | u8 reserved_at_0[0x20]; |
e281682b SM |
7329 | |
7330 | u8 algorithm_options[0x10]; | |
b4ff3a36 | 7331 | u8 reserved_at_30[0x4]; |
e281682b SM |
7332 | u8 repetitions_mode[0x4]; |
7333 | u8 num_of_repetitions[0x8]; | |
7334 | ||
7335 | u8 grade_version[0x8]; | |
7336 | u8 height_grade_type[0x4]; | |
7337 | u8 phase_grade_type[0x4]; | |
7338 | u8 height_grade_weight[0x8]; | |
7339 | u8 phase_grade_weight[0x8]; | |
7340 | ||
7341 | u8 gisim_measure_bits[0x10]; | |
7342 | u8 adaptive_tap_measure_bits[0x10]; | |
7343 | ||
7344 | u8 ber_bath_high_error_threshold[0x10]; | |
7345 | u8 ber_bath_mid_error_threshold[0x10]; | |
7346 | ||
7347 | u8 ber_bath_low_error_threshold[0x10]; | |
7348 | u8 one_ratio_high_threshold[0x10]; | |
7349 | ||
7350 | u8 one_ratio_high_mid_threshold[0x10]; | |
7351 | u8 one_ratio_low_mid_threshold[0x10]; | |
7352 | ||
7353 | u8 one_ratio_low_threshold[0x10]; | |
7354 | u8 ndeo_error_threshold[0x10]; | |
7355 | ||
7356 | u8 mixer_offset_step_size[0x10]; | |
b4ff3a36 | 7357 | u8 reserved_at_110[0x8]; |
e281682b SM |
7358 | u8 mix90_phase_for_voltage_bath[0x8]; |
7359 | ||
7360 | u8 mixer_offset_start[0x10]; | |
7361 | u8 mixer_offset_end[0x10]; | |
7362 | ||
b4ff3a36 | 7363 | u8 reserved_at_140[0x15]; |
e281682b SM |
7364 | u8 ber_test_time[0xb]; |
7365 | }; | |
7366 | ||
7367 | struct mlx5_ifc_pspa_reg_bits { | |
7368 | u8 swid[0x8]; | |
7369 | u8 local_port[0x8]; | |
7370 | u8 sub_port[0x8]; | |
b4ff3a36 | 7371 | u8 reserved_at_18[0x8]; |
e281682b | 7372 | |
b4ff3a36 | 7373 | u8 reserved_at_20[0x20]; |
e281682b SM |
7374 | }; |
7375 | ||
7376 | struct mlx5_ifc_pqdr_reg_bits { | |
b4ff3a36 | 7377 | u8 reserved_at_0[0x8]; |
e281682b | 7378 | u8 local_port[0x8]; |
b4ff3a36 | 7379 | u8 reserved_at_10[0x5]; |
e281682b | 7380 | u8 prio[0x3]; |
b4ff3a36 | 7381 | u8 reserved_at_18[0x6]; |
e281682b SM |
7382 | u8 mode[0x2]; |
7383 | ||
b4ff3a36 | 7384 | u8 reserved_at_20[0x20]; |
e281682b | 7385 | |
b4ff3a36 | 7386 | u8 reserved_at_40[0x10]; |
e281682b SM |
7387 | u8 min_threshold[0x10]; |
7388 | ||
b4ff3a36 | 7389 | u8 reserved_at_60[0x10]; |
e281682b SM |
7390 | u8 max_threshold[0x10]; |
7391 | ||
b4ff3a36 | 7392 | u8 reserved_at_80[0x10]; |
e281682b SM |
7393 | u8 mark_probability_denominator[0x10]; |
7394 | ||
b4ff3a36 | 7395 | u8 reserved_at_a0[0x60]; |
e281682b SM |
7396 | }; |
7397 | ||
7398 | struct mlx5_ifc_ppsc_reg_bits { | |
b4ff3a36 | 7399 | u8 reserved_at_0[0x8]; |
e281682b | 7400 | u8 local_port[0x8]; |
b4ff3a36 | 7401 | u8 reserved_at_10[0x10]; |
e281682b | 7402 | |
b4ff3a36 | 7403 | u8 reserved_at_20[0x60]; |
e281682b | 7404 | |
b4ff3a36 | 7405 | u8 reserved_at_80[0x1c]; |
e281682b SM |
7406 | u8 wrps_admin[0x4]; |
7407 | ||
b4ff3a36 | 7408 | u8 reserved_at_a0[0x1c]; |
e281682b SM |
7409 | u8 wrps_status[0x4]; |
7410 | ||
b4ff3a36 | 7411 | u8 reserved_at_c0[0x8]; |
e281682b | 7412 | u8 up_threshold[0x8]; |
b4ff3a36 | 7413 | u8 reserved_at_d0[0x8]; |
e281682b SM |
7414 | u8 down_threshold[0x8]; |
7415 | ||
b4ff3a36 | 7416 | u8 reserved_at_e0[0x20]; |
e281682b | 7417 | |
b4ff3a36 | 7418 | u8 reserved_at_100[0x1c]; |
e281682b SM |
7419 | u8 srps_admin[0x4]; |
7420 | ||
b4ff3a36 | 7421 | u8 reserved_at_120[0x1c]; |
e281682b SM |
7422 | u8 srps_status[0x4]; |
7423 | ||
b4ff3a36 | 7424 | u8 reserved_at_140[0x40]; |
e281682b SM |
7425 | }; |
7426 | ||
7427 | struct mlx5_ifc_pplr_reg_bits { | |
b4ff3a36 | 7428 | u8 reserved_at_0[0x8]; |
e281682b | 7429 | u8 local_port[0x8]; |
b4ff3a36 | 7430 | u8 reserved_at_10[0x10]; |
e281682b | 7431 | |
b4ff3a36 | 7432 | u8 reserved_at_20[0x8]; |
e281682b | 7433 | u8 lb_cap[0x8]; |
b4ff3a36 | 7434 | u8 reserved_at_30[0x8]; |
e281682b SM |
7435 | u8 lb_en[0x8]; |
7436 | }; | |
7437 | ||
7438 | struct mlx5_ifc_pplm_reg_bits { | |
b4ff3a36 | 7439 | u8 reserved_at_0[0x8]; |
e281682b | 7440 | u8 local_port[0x8]; |
b4ff3a36 | 7441 | u8 reserved_at_10[0x10]; |
e281682b | 7442 | |
b4ff3a36 | 7443 | u8 reserved_at_20[0x20]; |
e281682b SM |
7444 | |
7445 | u8 port_profile_mode[0x8]; | |
7446 | u8 static_port_profile[0x8]; | |
7447 | u8 active_port_profile[0x8]; | |
b4ff3a36 | 7448 | u8 reserved_at_58[0x8]; |
e281682b SM |
7449 | |
7450 | u8 retransmission_active[0x8]; | |
7451 | u8 fec_mode_active[0x18]; | |
7452 | ||
b4ff3a36 | 7453 | u8 reserved_at_80[0x20]; |
e281682b SM |
7454 | }; |
7455 | ||
7456 | struct mlx5_ifc_ppcnt_reg_bits { | |
7457 | u8 swid[0x8]; | |
7458 | u8 local_port[0x8]; | |
7459 | u8 pnat[0x2]; | |
b4ff3a36 | 7460 | u8 reserved_at_12[0x8]; |
e281682b SM |
7461 | u8 grp[0x6]; |
7462 | ||
7463 | u8 clr[0x1]; | |
b4ff3a36 | 7464 | u8 reserved_at_21[0x1c]; |
e281682b SM |
7465 | u8 prio_tc[0x3]; |
7466 | ||
7467 | union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set; | |
7468 | }; | |
7469 | ||
8ed1a630 GP |
7470 | struct mlx5_ifc_mpcnt_reg_bits { |
7471 | u8 reserved_at_0[0x8]; | |
7472 | u8 pcie_index[0x8]; | |
7473 | u8 reserved_at_10[0xa]; | |
7474 | u8 grp[0x6]; | |
7475 | ||
7476 | u8 clr[0x1]; | |
7477 | u8 reserved_at_21[0x1f]; | |
7478 | ||
7479 | union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set; | |
7480 | }; | |
7481 | ||
e281682b | 7482 | struct mlx5_ifc_ppad_reg_bits { |
b4ff3a36 | 7483 | u8 reserved_at_0[0x3]; |
e281682b | 7484 | u8 single_mac[0x1]; |
b4ff3a36 | 7485 | u8 reserved_at_4[0x4]; |
e281682b SM |
7486 | u8 local_port[0x8]; |
7487 | u8 mac_47_32[0x10]; | |
7488 | ||
7489 | u8 mac_31_0[0x20]; | |
7490 | ||
b4ff3a36 | 7491 | u8 reserved_at_40[0x40]; |
e281682b SM |
7492 | }; |
7493 | ||
7494 | struct mlx5_ifc_pmtu_reg_bits { | |
b4ff3a36 | 7495 | u8 reserved_at_0[0x8]; |
e281682b | 7496 | u8 local_port[0x8]; |
b4ff3a36 | 7497 | u8 reserved_at_10[0x10]; |
e281682b SM |
7498 | |
7499 | u8 max_mtu[0x10]; | |
b4ff3a36 | 7500 | u8 reserved_at_30[0x10]; |
e281682b SM |
7501 | |
7502 | u8 admin_mtu[0x10]; | |
b4ff3a36 | 7503 | u8 reserved_at_50[0x10]; |
e281682b SM |
7504 | |
7505 | u8 oper_mtu[0x10]; | |
b4ff3a36 | 7506 | u8 reserved_at_70[0x10]; |
e281682b SM |
7507 | }; |
7508 | ||
7509 | struct mlx5_ifc_pmpr_reg_bits { | |
b4ff3a36 | 7510 | u8 reserved_at_0[0x8]; |
e281682b | 7511 | u8 module[0x8]; |
b4ff3a36 | 7512 | u8 reserved_at_10[0x10]; |
e281682b | 7513 | |
b4ff3a36 | 7514 | u8 reserved_at_20[0x18]; |
e281682b SM |
7515 | u8 attenuation_5g[0x8]; |
7516 | ||
b4ff3a36 | 7517 | u8 reserved_at_40[0x18]; |
e281682b SM |
7518 | u8 attenuation_7g[0x8]; |
7519 | ||
b4ff3a36 | 7520 | u8 reserved_at_60[0x18]; |
e281682b SM |
7521 | u8 attenuation_12g[0x8]; |
7522 | }; | |
7523 | ||
7524 | struct mlx5_ifc_pmpe_reg_bits { | |
b4ff3a36 | 7525 | u8 reserved_at_0[0x8]; |
e281682b | 7526 | u8 module[0x8]; |
b4ff3a36 | 7527 | u8 reserved_at_10[0xc]; |
e281682b SM |
7528 | u8 module_status[0x4]; |
7529 | ||
b4ff3a36 | 7530 | u8 reserved_at_20[0x60]; |
e281682b SM |
7531 | }; |
7532 | ||
7533 | struct mlx5_ifc_pmpc_reg_bits { | |
7534 | u8 module_state_updated[32][0x8]; | |
7535 | }; | |
7536 | ||
7537 | struct mlx5_ifc_pmlpn_reg_bits { | |
b4ff3a36 | 7538 | u8 reserved_at_0[0x4]; |
e281682b SM |
7539 | u8 mlpn_status[0x4]; |
7540 | u8 local_port[0x8]; | |
b4ff3a36 | 7541 | u8 reserved_at_10[0x10]; |
e281682b SM |
7542 | |
7543 | u8 e[0x1]; | |
b4ff3a36 | 7544 | u8 reserved_at_21[0x1f]; |
e281682b SM |
7545 | }; |
7546 | ||
7547 | struct mlx5_ifc_pmlp_reg_bits { | |
7548 | u8 rxtx[0x1]; | |
b4ff3a36 | 7549 | u8 reserved_at_1[0x7]; |
e281682b | 7550 | u8 local_port[0x8]; |
b4ff3a36 | 7551 | u8 reserved_at_10[0x8]; |
e281682b SM |
7552 | u8 width[0x8]; |
7553 | ||
7554 | u8 lane0_module_mapping[0x20]; | |
7555 | ||
7556 | u8 lane1_module_mapping[0x20]; | |
7557 | ||
7558 | u8 lane2_module_mapping[0x20]; | |
7559 | ||
7560 | u8 lane3_module_mapping[0x20]; | |
7561 | ||
b4ff3a36 | 7562 | u8 reserved_at_a0[0x160]; |
e281682b SM |
7563 | }; |
7564 | ||
7565 | struct mlx5_ifc_pmaos_reg_bits { | |
b4ff3a36 | 7566 | u8 reserved_at_0[0x8]; |
e281682b | 7567 | u8 module[0x8]; |
b4ff3a36 | 7568 | u8 reserved_at_10[0x4]; |
e281682b | 7569 | u8 admin_status[0x4]; |
b4ff3a36 | 7570 | u8 reserved_at_18[0x4]; |
e281682b SM |
7571 | u8 oper_status[0x4]; |
7572 | ||
7573 | u8 ase[0x1]; | |
7574 | u8 ee[0x1]; | |
b4ff3a36 | 7575 | u8 reserved_at_22[0x1c]; |
e281682b SM |
7576 | u8 e[0x2]; |
7577 | ||
b4ff3a36 | 7578 | u8 reserved_at_40[0x40]; |
e281682b SM |
7579 | }; |
7580 | ||
7581 | struct mlx5_ifc_plpc_reg_bits { | |
b4ff3a36 | 7582 | u8 reserved_at_0[0x4]; |
e281682b | 7583 | u8 profile_id[0xc]; |
b4ff3a36 | 7584 | u8 reserved_at_10[0x4]; |
e281682b | 7585 | u8 proto_mask[0x4]; |
b4ff3a36 | 7586 | u8 reserved_at_18[0x8]; |
e281682b | 7587 | |
b4ff3a36 | 7588 | u8 reserved_at_20[0x10]; |
e281682b SM |
7589 | u8 lane_speed[0x10]; |
7590 | ||
b4ff3a36 | 7591 | u8 reserved_at_40[0x17]; |
e281682b SM |
7592 | u8 lpbf[0x1]; |
7593 | u8 fec_mode_policy[0x8]; | |
7594 | ||
7595 | u8 retransmission_capability[0x8]; | |
7596 | u8 fec_mode_capability[0x18]; | |
7597 | ||
7598 | u8 retransmission_support_admin[0x8]; | |
7599 | u8 fec_mode_support_admin[0x18]; | |
7600 | ||
7601 | u8 retransmission_request_admin[0x8]; | |
7602 | u8 fec_mode_request_admin[0x18]; | |
7603 | ||
b4ff3a36 | 7604 | u8 reserved_at_c0[0x80]; |
e281682b SM |
7605 | }; |
7606 | ||
7607 | struct mlx5_ifc_plib_reg_bits { | |
b4ff3a36 | 7608 | u8 reserved_at_0[0x8]; |
e281682b | 7609 | u8 local_port[0x8]; |
b4ff3a36 | 7610 | u8 reserved_at_10[0x8]; |
e281682b SM |
7611 | u8 ib_port[0x8]; |
7612 | ||
b4ff3a36 | 7613 | u8 reserved_at_20[0x60]; |
e281682b SM |
7614 | }; |
7615 | ||
7616 | struct mlx5_ifc_plbf_reg_bits { | |
b4ff3a36 | 7617 | u8 reserved_at_0[0x8]; |
e281682b | 7618 | u8 local_port[0x8]; |
b4ff3a36 | 7619 | u8 reserved_at_10[0xd]; |
e281682b SM |
7620 | u8 lbf_mode[0x3]; |
7621 | ||
b4ff3a36 | 7622 | u8 reserved_at_20[0x20]; |
e281682b SM |
7623 | }; |
7624 | ||
7625 | struct mlx5_ifc_pipg_reg_bits { | |
b4ff3a36 | 7626 | u8 reserved_at_0[0x8]; |
e281682b | 7627 | u8 local_port[0x8]; |
b4ff3a36 | 7628 | u8 reserved_at_10[0x10]; |
e281682b SM |
7629 | |
7630 | u8 dic[0x1]; | |
b4ff3a36 | 7631 | u8 reserved_at_21[0x19]; |
e281682b | 7632 | u8 ipg[0x4]; |
b4ff3a36 | 7633 | u8 reserved_at_3e[0x2]; |
e281682b SM |
7634 | }; |
7635 | ||
7636 | struct mlx5_ifc_pifr_reg_bits { | |
b4ff3a36 | 7637 | u8 reserved_at_0[0x8]; |
e281682b | 7638 | u8 local_port[0x8]; |
b4ff3a36 | 7639 | u8 reserved_at_10[0x10]; |
e281682b | 7640 | |
b4ff3a36 | 7641 | u8 reserved_at_20[0xe0]; |
e281682b SM |
7642 | |
7643 | u8 port_filter[8][0x20]; | |
7644 | ||
7645 | u8 port_filter_update_en[8][0x20]; | |
7646 | }; | |
7647 | ||
7648 | struct mlx5_ifc_pfcc_reg_bits { | |
b4ff3a36 | 7649 | u8 reserved_at_0[0x8]; |
e281682b | 7650 | u8 local_port[0x8]; |
b4ff3a36 | 7651 | u8 reserved_at_10[0x10]; |
e281682b SM |
7652 | |
7653 | u8 ppan[0x4]; | |
b4ff3a36 | 7654 | u8 reserved_at_24[0x4]; |
e281682b | 7655 | u8 prio_mask_tx[0x8]; |
b4ff3a36 | 7656 | u8 reserved_at_30[0x8]; |
e281682b SM |
7657 | u8 prio_mask_rx[0x8]; |
7658 | ||
7659 | u8 pptx[0x1]; | |
7660 | u8 aptx[0x1]; | |
b4ff3a36 | 7661 | u8 reserved_at_42[0x6]; |
e281682b | 7662 | u8 pfctx[0x8]; |
b4ff3a36 | 7663 | u8 reserved_at_50[0x10]; |
e281682b SM |
7664 | |
7665 | u8 pprx[0x1]; | |
7666 | u8 aprx[0x1]; | |
b4ff3a36 | 7667 | u8 reserved_at_62[0x6]; |
e281682b | 7668 | u8 pfcrx[0x8]; |
b4ff3a36 | 7669 | u8 reserved_at_70[0x10]; |
e281682b | 7670 | |
b4ff3a36 | 7671 | u8 reserved_at_80[0x80]; |
e281682b SM |
7672 | }; |
7673 | ||
7674 | struct mlx5_ifc_pelc_reg_bits { | |
7675 | u8 op[0x4]; | |
b4ff3a36 | 7676 | u8 reserved_at_4[0x4]; |
e281682b | 7677 | u8 local_port[0x8]; |
b4ff3a36 | 7678 | u8 reserved_at_10[0x10]; |
e281682b SM |
7679 | |
7680 | u8 op_admin[0x8]; | |
7681 | u8 op_capability[0x8]; | |
7682 | u8 op_request[0x8]; | |
7683 | u8 op_active[0x8]; | |
7684 | ||
7685 | u8 admin[0x40]; | |
7686 | ||
7687 | u8 capability[0x40]; | |
7688 | ||
7689 | u8 request[0x40]; | |
7690 | ||
7691 | u8 active[0x40]; | |
7692 | ||
b4ff3a36 | 7693 | u8 reserved_at_140[0x80]; |
e281682b SM |
7694 | }; |
7695 | ||
7696 | struct mlx5_ifc_peir_reg_bits { | |
b4ff3a36 | 7697 | u8 reserved_at_0[0x8]; |
e281682b | 7698 | u8 local_port[0x8]; |
b4ff3a36 | 7699 | u8 reserved_at_10[0x10]; |
e281682b | 7700 | |
b4ff3a36 | 7701 | u8 reserved_at_20[0xc]; |
e281682b | 7702 | u8 error_count[0x4]; |
b4ff3a36 | 7703 | u8 reserved_at_30[0x10]; |
e281682b | 7704 | |
b4ff3a36 | 7705 | u8 reserved_at_40[0xc]; |
e281682b | 7706 | u8 lane[0x4]; |
b4ff3a36 | 7707 | u8 reserved_at_50[0x8]; |
e281682b SM |
7708 | u8 error_type[0x8]; |
7709 | }; | |
7710 | ||
cfdcbcea | 7711 | struct mlx5_ifc_pcam_enhanced_features_bits { |
5b4793f8 | 7712 | u8 reserved_at_0[0x7c]; |
cfdcbcea | 7713 | |
5b4793f8 EBE |
7714 | u8 ptys_connector_type[0x1]; |
7715 | u8 reserved_at_7d[0x1]; | |
cfdcbcea GP |
7716 | u8 ppcnt_discard_group[0x1]; |
7717 | u8 ppcnt_statistical_group[0x1]; | |
7718 | }; | |
7719 | ||
7720 | struct mlx5_ifc_pcam_reg_bits { | |
7721 | u8 reserved_at_0[0x8]; | |
7722 | u8 feature_group[0x8]; | |
7723 | u8 reserved_at_10[0x8]; | |
7724 | u8 access_reg_group[0x8]; | |
7725 | ||
7726 | u8 reserved_at_20[0x20]; | |
7727 | ||
7728 | union { | |
7729 | u8 reserved_at_0[0x80]; | |
7730 | } port_access_reg_cap_mask; | |
7731 | ||
7732 | u8 reserved_at_c0[0x80]; | |
7733 | ||
7734 | union { | |
7735 | struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features; | |
7736 | u8 reserved_at_0[0x80]; | |
7737 | } feature_cap_mask; | |
7738 | ||
7739 | u8 reserved_at_1c0[0xc0]; | |
7740 | }; | |
7741 | ||
7742 | struct mlx5_ifc_mcam_enhanced_features_bits { | |
7743 | u8 reserved_at_0[0x7f]; | |
7744 | ||
7745 | u8 pcie_performance_group[0x1]; | |
7746 | }; | |
7747 | ||
0ab87743 OG |
7748 | struct mlx5_ifc_mcam_access_reg_bits { |
7749 | u8 reserved_at_0[0x1c]; | |
7750 | u8 mcda[0x1]; | |
7751 | u8 mcc[0x1]; | |
7752 | u8 mcqi[0x1]; | |
7753 | u8 reserved_at_1f[0x1]; | |
7754 | ||
7755 | u8 regs_95_to_64[0x20]; | |
7756 | u8 regs_63_to_32[0x20]; | |
7757 | u8 regs_31_to_0[0x20]; | |
7758 | }; | |
7759 | ||
cfdcbcea GP |
7760 | struct mlx5_ifc_mcam_reg_bits { |
7761 | u8 reserved_at_0[0x8]; | |
7762 | u8 feature_group[0x8]; | |
7763 | u8 reserved_at_10[0x8]; | |
7764 | u8 access_reg_group[0x8]; | |
7765 | ||
7766 | u8 reserved_at_20[0x20]; | |
7767 | ||
7768 | union { | |
0ab87743 | 7769 | struct mlx5_ifc_mcam_access_reg_bits access_regs; |
cfdcbcea GP |
7770 | u8 reserved_at_0[0x80]; |
7771 | } mng_access_reg_cap_mask; | |
7772 | ||
7773 | u8 reserved_at_c0[0x80]; | |
7774 | ||
7775 | union { | |
7776 | struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features; | |
7777 | u8 reserved_at_0[0x80]; | |
7778 | } mng_feature_cap_mask; | |
7779 | ||
7780 | u8 reserved_at_1c0[0x80]; | |
7781 | }; | |
7782 | ||
e281682b | 7783 | struct mlx5_ifc_pcap_reg_bits { |
b4ff3a36 | 7784 | u8 reserved_at_0[0x8]; |
e281682b | 7785 | u8 local_port[0x8]; |
b4ff3a36 | 7786 | u8 reserved_at_10[0x10]; |
e281682b SM |
7787 | |
7788 | u8 port_capability_mask[4][0x20]; | |
7789 | }; | |
7790 | ||
7791 | struct mlx5_ifc_paos_reg_bits { | |
7792 | u8 swid[0x8]; | |
7793 | u8 local_port[0x8]; | |
b4ff3a36 | 7794 | u8 reserved_at_10[0x4]; |
e281682b | 7795 | u8 admin_status[0x4]; |
b4ff3a36 | 7796 | u8 reserved_at_18[0x4]; |
e281682b SM |
7797 | u8 oper_status[0x4]; |
7798 | ||
7799 | u8 ase[0x1]; | |
7800 | u8 ee[0x1]; | |
b4ff3a36 | 7801 | u8 reserved_at_22[0x1c]; |
e281682b SM |
7802 | u8 e[0x2]; |
7803 | ||
b4ff3a36 | 7804 | u8 reserved_at_40[0x40]; |
e281682b SM |
7805 | }; |
7806 | ||
7807 | struct mlx5_ifc_pamp_reg_bits { | |
b4ff3a36 | 7808 | u8 reserved_at_0[0x8]; |
e281682b | 7809 | u8 opamp_group[0x8]; |
b4ff3a36 | 7810 | u8 reserved_at_10[0xc]; |
e281682b SM |
7811 | u8 opamp_group_type[0x4]; |
7812 | ||
7813 | u8 start_index[0x10]; | |
b4ff3a36 | 7814 | u8 reserved_at_30[0x4]; |
e281682b SM |
7815 | u8 num_of_indices[0xc]; |
7816 | ||
7817 | u8 index_data[18][0x10]; | |
7818 | }; | |
7819 | ||
7d5e1423 SM |
7820 | struct mlx5_ifc_pcmr_reg_bits { |
7821 | u8 reserved_at_0[0x8]; | |
7822 | u8 local_port[0x8]; | |
7823 | u8 reserved_at_10[0x2e]; | |
7824 | u8 fcs_cap[0x1]; | |
7825 | u8 reserved_at_3f[0x1f]; | |
7826 | u8 fcs_chk[0x1]; | |
7827 | u8 reserved_at_5f[0x1]; | |
7828 | }; | |
7829 | ||
e281682b | 7830 | struct mlx5_ifc_lane_2_module_mapping_bits { |
b4ff3a36 | 7831 | u8 reserved_at_0[0x6]; |
e281682b | 7832 | u8 rx_lane[0x2]; |
b4ff3a36 | 7833 | u8 reserved_at_8[0x6]; |
e281682b | 7834 | u8 tx_lane[0x2]; |
b4ff3a36 | 7835 | u8 reserved_at_10[0x8]; |
e281682b SM |
7836 | u8 module[0x8]; |
7837 | }; | |
7838 | ||
7839 | struct mlx5_ifc_bufferx_reg_bits { | |
b4ff3a36 | 7840 | u8 reserved_at_0[0x6]; |
e281682b SM |
7841 | u8 lossy[0x1]; |
7842 | u8 epsb[0x1]; | |
b4ff3a36 | 7843 | u8 reserved_at_8[0xc]; |
e281682b SM |
7844 | u8 size[0xc]; |
7845 | ||
7846 | u8 xoff_threshold[0x10]; | |
7847 | u8 xon_threshold[0x10]; | |
7848 | }; | |
7849 | ||
7850 | struct mlx5_ifc_set_node_in_bits { | |
7851 | u8 node_description[64][0x8]; | |
7852 | }; | |
7853 | ||
7854 | struct mlx5_ifc_register_power_settings_bits { | |
b4ff3a36 | 7855 | u8 reserved_at_0[0x18]; |
e281682b SM |
7856 | u8 power_settings_level[0x8]; |
7857 | ||
b4ff3a36 | 7858 | u8 reserved_at_20[0x60]; |
e281682b SM |
7859 | }; |
7860 | ||
7861 | struct mlx5_ifc_register_host_endianness_bits { | |
7862 | u8 he[0x1]; | |
b4ff3a36 | 7863 | u8 reserved_at_1[0x1f]; |
e281682b | 7864 | |
b4ff3a36 | 7865 | u8 reserved_at_20[0x60]; |
e281682b SM |
7866 | }; |
7867 | ||
7868 | struct mlx5_ifc_umr_pointer_desc_argument_bits { | |
b4ff3a36 | 7869 | u8 reserved_at_0[0x20]; |
e281682b SM |
7870 | |
7871 | u8 mkey[0x20]; | |
7872 | ||
7873 | u8 addressh_63_32[0x20]; | |
7874 | ||
7875 | u8 addressl_31_0[0x20]; | |
7876 | }; | |
7877 | ||
7878 | struct mlx5_ifc_ud_adrs_vector_bits { | |
7879 | u8 dc_key[0x40]; | |
7880 | ||
7881 | u8 ext[0x1]; | |
b4ff3a36 | 7882 | u8 reserved_at_41[0x7]; |
e281682b SM |
7883 | u8 destination_qp_dct[0x18]; |
7884 | ||
7885 | u8 static_rate[0x4]; | |
7886 | u8 sl_eth_prio[0x4]; | |
7887 | u8 fl[0x1]; | |
7888 | u8 mlid[0x7]; | |
7889 | u8 rlid_udp_sport[0x10]; | |
7890 | ||
b4ff3a36 | 7891 | u8 reserved_at_80[0x20]; |
e281682b SM |
7892 | |
7893 | u8 rmac_47_16[0x20]; | |
7894 | ||
7895 | u8 rmac_15_0[0x10]; | |
7896 | u8 tclass[0x8]; | |
7897 | u8 hop_limit[0x8]; | |
7898 | ||
b4ff3a36 | 7899 | u8 reserved_at_e0[0x1]; |
e281682b | 7900 | u8 grh[0x1]; |
b4ff3a36 | 7901 | u8 reserved_at_e2[0x2]; |
e281682b SM |
7902 | u8 src_addr_index[0x8]; |
7903 | u8 flow_label[0x14]; | |
7904 | ||
7905 | u8 rgid_rip[16][0x8]; | |
7906 | }; | |
7907 | ||
7908 | struct mlx5_ifc_pages_req_event_bits { | |
b4ff3a36 | 7909 | u8 reserved_at_0[0x10]; |
e281682b SM |
7910 | u8 function_id[0x10]; |
7911 | ||
7912 | u8 num_pages[0x20]; | |
7913 | ||
b4ff3a36 | 7914 | u8 reserved_at_40[0xa0]; |
e281682b SM |
7915 | }; |
7916 | ||
7917 | struct mlx5_ifc_eqe_bits { | |
b4ff3a36 | 7918 | u8 reserved_at_0[0x8]; |
e281682b | 7919 | u8 event_type[0x8]; |
b4ff3a36 | 7920 | u8 reserved_at_10[0x8]; |
e281682b SM |
7921 | u8 event_sub_type[0x8]; |
7922 | ||
b4ff3a36 | 7923 | u8 reserved_at_20[0xe0]; |
e281682b SM |
7924 | |
7925 | union mlx5_ifc_event_auto_bits event_data; | |
7926 | ||
b4ff3a36 | 7927 | u8 reserved_at_1e0[0x10]; |
e281682b | 7928 | u8 signature[0x8]; |
b4ff3a36 | 7929 | u8 reserved_at_1f8[0x7]; |
e281682b SM |
7930 | u8 owner[0x1]; |
7931 | }; | |
7932 | ||
7933 | enum { | |
7934 | MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7, | |
7935 | }; | |
7936 | ||
7937 | struct mlx5_ifc_cmd_queue_entry_bits { | |
7938 | u8 type[0x8]; | |
b4ff3a36 | 7939 | u8 reserved_at_8[0x18]; |
e281682b SM |
7940 | |
7941 | u8 input_length[0x20]; | |
7942 | ||
7943 | u8 input_mailbox_pointer_63_32[0x20]; | |
7944 | ||
7945 | u8 input_mailbox_pointer_31_9[0x17]; | |
b4ff3a36 | 7946 | u8 reserved_at_77[0x9]; |
e281682b SM |
7947 | |
7948 | u8 command_input_inline_data[16][0x8]; | |
7949 | ||
7950 | u8 command_output_inline_data[16][0x8]; | |
7951 | ||
7952 | u8 output_mailbox_pointer_63_32[0x20]; | |
7953 | ||
7954 | u8 output_mailbox_pointer_31_9[0x17]; | |
b4ff3a36 | 7955 | u8 reserved_at_1b7[0x9]; |
e281682b SM |
7956 | |
7957 | u8 output_length[0x20]; | |
7958 | ||
7959 | u8 token[0x8]; | |
7960 | u8 signature[0x8]; | |
b4ff3a36 | 7961 | u8 reserved_at_1f0[0x8]; |
e281682b SM |
7962 | u8 status[0x7]; |
7963 | u8 ownership[0x1]; | |
7964 | }; | |
7965 | ||
7966 | struct mlx5_ifc_cmd_out_bits { | |
7967 | u8 status[0x8]; | |
b4ff3a36 | 7968 | u8 reserved_at_8[0x18]; |
e281682b SM |
7969 | |
7970 | u8 syndrome[0x20]; | |
7971 | ||
7972 | u8 command_output[0x20]; | |
7973 | }; | |
7974 | ||
7975 | struct mlx5_ifc_cmd_in_bits { | |
7976 | u8 opcode[0x10]; | |
b4ff3a36 | 7977 | u8 reserved_at_10[0x10]; |
e281682b | 7978 | |
b4ff3a36 | 7979 | u8 reserved_at_20[0x10]; |
e281682b SM |
7980 | u8 op_mod[0x10]; |
7981 | ||
7982 | u8 command[0][0x20]; | |
7983 | }; | |
7984 | ||
7985 | struct mlx5_ifc_cmd_if_box_bits { | |
7986 | u8 mailbox_data[512][0x8]; | |
7987 | ||
b4ff3a36 | 7988 | u8 reserved_at_1000[0x180]; |
e281682b SM |
7989 | |
7990 | u8 next_pointer_63_32[0x20]; | |
7991 | ||
7992 | u8 next_pointer_31_10[0x16]; | |
b4ff3a36 | 7993 | u8 reserved_at_11b6[0xa]; |
e281682b SM |
7994 | |
7995 | u8 block_number[0x20]; | |
7996 | ||
b4ff3a36 | 7997 | u8 reserved_at_11e0[0x8]; |
e281682b SM |
7998 | u8 token[0x8]; |
7999 | u8 ctrl_signature[0x8]; | |
8000 | u8 signature[0x8]; | |
8001 | }; | |
8002 | ||
8003 | struct mlx5_ifc_mtt_bits { | |
8004 | u8 ptag_63_32[0x20]; | |
8005 | ||
8006 | u8 ptag_31_8[0x18]; | |
b4ff3a36 | 8007 | u8 reserved_at_38[0x6]; |
e281682b SM |
8008 | u8 wr_en[0x1]; |
8009 | u8 rd_en[0x1]; | |
8010 | }; | |
8011 | ||
928cfe87 TT |
8012 | struct mlx5_ifc_query_wol_rol_out_bits { |
8013 | u8 status[0x8]; | |
8014 | u8 reserved_at_8[0x18]; | |
8015 | ||
8016 | u8 syndrome[0x20]; | |
8017 | ||
8018 | u8 reserved_at_40[0x10]; | |
8019 | u8 rol_mode[0x8]; | |
8020 | u8 wol_mode[0x8]; | |
8021 | ||
8022 | u8 reserved_at_60[0x20]; | |
8023 | }; | |
8024 | ||
8025 | struct mlx5_ifc_query_wol_rol_in_bits { | |
8026 | u8 opcode[0x10]; | |
8027 | u8 reserved_at_10[0x10]; | |
8028 | ||
8029 | u8 reserved_at_20[0x10]; | |
8030 | u8 op_mod[0x10]; | |
8031 | ||
8032 | u8 reserved_at_40[0x40]; | |
8033 | }; | |
8034 | ||
8035 | struct mlx5_ifc_set_wol_rol_out_bits { | |
8036 | u8 status[0x8]; | |
8037 | u8 reserved_at_8[0x18]; | |
8038 | ||
8039 | u8 syndrome[0x20]; | |
8040 | ||
8041 | u8 reserved_at_40[0x40]; | |
8042 | }; | |
8043 | ||
8044 | struct mlx5_ifc_set_wol_rol_in_bits { | |
8045 | u8 opcode[0x10]; | |
8046 | u8 reserved_at_10[0x10]; | |
8047 | ||
8048 | u8 reserved_at_20[0x10]; | |
8049 | u8 op_mod[0x10]; | |
8050 | ||
8051 | u8 rol_mode_valid[0x1]; | |
8052 | u8 wol_mode_valid[0x1]; | |
8053 | u8 reserved_at_42[0xe]; | |
8054 | u8 rol_mode[0x8]; | |
8055 | u8 wol_mode[0x8]; | |
8056 | ||
8057 | u8 reserved_at_60[0x20]; | |
8058 | }; | |
8059 | ||
e281682b SM |
8060 | enum { |
8061 | MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0, | |
8062 | MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1, | |
8063 | MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2, | |
8064 | }; | |
8065 | ||
8066 | enum { | |
8067 | MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0, | |
8068 | MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1, | |
8069 | MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2, | |
8070 | }; | |
8071 | ||
8072 | enum { | |
8073 | MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1, | |
8074 | MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7, | |
8075 | MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8, | |
8076 | MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9, | |
8077 | MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa, | |
8078 | MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb, | |
8079 | MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc, | |
8080 | MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd, | |
8081 | MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe, | |
8082 | MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf, | |
8083 | MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10, | |
8084 | }; | |
8085 | ||
8086 | struct mlx5_ifc_initial_seg_bits { | |
8087 | u8 fw_rev_minor[0x10]; | |
8088 | u8 fw_rev_major[0x10]; | |
8089 | ||
8090 | u8 cmd_interface_rev[0x10]; | |
8091 | u8 fw_rev_subminor[0x10]; | |
8092 | ||
b4ff3a36 | 8093 | u8 reserved_at_40[0x40]; |
e281682b SM |
8094 | |
8095 | u8 cmdq_phy_addr_63_32[0x20]; | |
8096 | ||
8097 | u8 cmdq_phy_addr_31_12[0x14]; | |
b4ff3a36 | 8098 | u8 reserved_at_b4[0x2]; |
e281682b SM |
8099 | u8 nic_interface[0x2]; |
8100 | u8 log_cmdq_size[0x4]; | |
8101 | u8 log_cmdq_stride[0x4]; | |
8102 | ||
8103 | u8 command_doorbell_vector[0x20]; | |
8104 | ||
b4ff3a36 | 8105 | u8 reserved_at_e0[0xf00]; |
e281682b SM |
8106 | |
8107 | u8 initializing[0x1]; | |
b4ff3a36 | 8108 | u8 reserved_at_fe1[0x4]; |
e281682b | 8109 | u8 nic_interface_supported[0x3]; |
b4ff3a36 | 8110 | u8 reserved_at_fe8[0x18]; |
e281682b SM |
8111 | |
8112 | struct mlx5_ifc_health_buffer_bits health_buffer; | |
8113 | ||
8114 | u8 no_dram_nic_offset[0x20]; | |
8115 | ||
b4ff3a36 | 8116 | u8 reserved_at_1220[0x6e40]; |
e281682b | 8117 | |
b4ff3a36 | 8118 | u8 reserved_at_8060[0x1f]; |
e281682b SM |
8119 | u8 clear_int[0x1]; |
8120 | ||
8121 | u8 health_syndrome[0x8]; | |
8122 | u8 health_counter[0x18]; | |
8123 | ||
b4ff3a36 | 8124 | u8 reserved_at_80a0[0x17fc0]; |
e281682b SM |
8125 | }; |
8126 | ||
f9a1ef72 EE |
8127 | struct mlx5_ifc_mtpps_reg_bits { |
8128 | u8 reserved_at_0[0xc]; | |
8129 | u8 cap_number_of_pps_pins[0x4]; | |
8130 | u8 reserved_at_10[0x4]; | |
8131 | u8 cap_max_num_of_pps_in_pins[0x4]; | |
8132 | u8 reserved_at_18[0x4]; | |
8133 | u8 cap_max_num_of_pps_out_pins[0x4]; | |
8134 | ||
8135 | u8 reserved_at_20[0x24]; | |
8136 | u8 cap_pin_3_mode[0x4]; | |
8137 | u8 reserved_at_48[0x4]; | |
8138 | u8 cap_pin_2_mode[0x4]; | |
8139 | u8 reserved_at_50[0x4]; | |
8140 | u8 cap_pin_1_mode[0x4]; | |
8141 | u8 reserved_at_58[0x4]; | |
8142 | u8 cap_pin_0_mode[0x4]; | |
8143 | ||
8144 | u8 reserved_at_60[0x4]; | |
8145 | u8 cap_pin_7_mode[0x4]; | |
8146 | u8 reserved_at_68[0x4]; | |
8147 | u8 cap_pin_6_mode[0x4]; | |
8148 | u8 reserved_at_70[0x4]; | |
8149 | u8 cap_pin_5_mode[0x4]; | |
8150 | u8 reserved_at_78[0x4]; | |
8151 | u8 cap_pin_4_mode[0x4]; | |
8152 | ||
8153 | u8 reserved_at_80[0x80]; | |
8154 | ||
8155 | u8 enable[0x1]; | |
8156 | u8 reserved_at_101[0xb]; | |
8157 | u8 pattern[0x4]; | |
8158 | u8 reserved_at_110[0x4]; | |
8159 | u8 pin_mode[0x4]; | |
8160 | u8 pin[0x8]; | |
8161 | ||
8162 | u8 reserved_at_120[0x20]; | |
8163 | ||
8164 | u8 time_stamp[0x40]; | |
8165 | ||
8166 | u8 out_pulse_duration[0x10]; | |
8167 | u8 out_periodic_adjustment[0x10]; | |
8168 | ||
8169 | u8 reserved_at_1a0[0x60]; | |
8170 | }; | |
8171 | ||
8172 | struct mlx5_ifc_mtppse_reg_bits { | |
8173 | u8 reserved_at_0[0x18]; | |
8174 | u8 pin[0x8]; | |
8175 | u8 event_arm[0x1]; | |
8176 | u8 reserved_at_21[0x1b]; | |
8177 | u8 event_generation_mode[0x4]; | |
8178 | u8 reserved_at_40[0x40]; | |
8179 | }; | |
8180 | ||
47176289 OG |
8181 | struct mlx5_ifc_mcqi_cap_bits { |
8182 | u8 supported_info_bitmask[0x20]; | |
8183 | ||
8184 | u8 component_size[0x20]; | |
8185 | ||
8186 | u8 max_component_size[0x20]; | |
8187 | ||
8188 | u8 log_mcda_word_size[0x4]; | |
8189 | u8 reserved_at_64[0xc]; | |
8190 | u8 mcda_max_write_size[0x10]; | |
8191 | ||
8192 | u8 rd_en[0x1]; | |
8193 | u8 reserved_at_81[0x1]; | |
8194 | u8 match_chip_id[0x1]; | |
8195 | u8 match_psid[0x1]; | |
8196 | u8 check_user_timestamp[0x1]; | |
8197 | u8 match_base_guid_mac[0x1]; | |
8198 | u8 reserved_at_86[0x1a]; | |
8199 | }; | |
8200 | ||
8201 | struct mlx5_ifc_mcqi_reg_bits { | |
8202 | u8 read_pending_component[0x1]; | |
8203 | u8 reserved_at_1[0xf]; | |
8204 | u8 component_index[0x10]; | |
8205 | ||
8206 | u8 reserved_at_20[0x20]; | |
8207 | ||
8208 | u8 reserved_at_40[0x1b]; | |
8209 | u8 info_type[0x5]; | |
8210 | ||
8211 | u8 info_size[0x20]; | |
8212 | ||
8213 | u8 offset[0x20]; | |
8214 | ||
8215 | u8 reserved_at_a0[0x10]; | |
8216 | u8 data_size[0x10]; | |
8217 | ||
8218 | u8 data[0][0x20]; | |
8219 | }; | |
8220 | ||
8221 | struct mlx5_ifc_mcc_reg_bits { | |
8222 | u8 reserved_at_0[0x4]; | |
8223 | u8 time_elapsed_since_last_cmd[0xc]; | |
8224 | u8 reserved_at_10[0x8]; | |
8225 | u8 instruction[0x8]; | |
8226 | ||
8227 | u8 reserved_at_20[0x10]; | |
8228 | u8 component_index[0x10]; | |
8229 | ||
8230 | u8 reserved_at_40[0x8]; | |
8231 | u8 update_handle[0x18]; | |
8232 | ||
8233 | u8 handle_owner_type[0x4]; | |
8234 | u8 handle_owner_host_id[0x4]; | |
8235 | u8 reserved_at_68[0x1]; | |
8236 | u8 control_progress[0x7]; | |
8237 | u8 error_code[0x8]; | |
8238 | u8 reserved_at_78[0x4]; | |
8239 | u8 control_state[0x4]; | |
8240 | ||
8241 | u8 component_size[0x20]; | |
8242 | ||
8243 | u8 reserved_at_a0[0x60]; | |
8244 | }; | |
8245 | ||
8246 | struct mlx5_ifc_mcda_reg_bits { | |
8247 | u8 reserved_at_0[0x8]; | |
8248 | u8 update_handle[0x18]; | |
8249 | ||
8250 | u8 offset[0x20]; | |
8251 | ||
8252 | u8 reserved_at_40[0x10]; | |
8253 | u8 size[0x10]; | |
8254 | ||
8255 | u8 reserved_at_60[0x20]; | |
8256 | ||
8257 | u8 data[0][0x20]; | |
8258 | }; | |
8259 | ||
e281682b SM |
8260 | union mlx5_ifc_ports_control_registers_document_bits { |
8261 | struct mlx5_ifc_bufferx_reg_bits bufferx_reg; | |
8262 | struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout; | |
8263 | struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout; | |
8264 | struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout; | |
8265 | struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout; | |
8266 | struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout; | |
8267 | struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout; | |
8268 | struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout; | |
8269 | struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping; | |
8270 | struct mlx5_ifc_pamp_reg_bits pamp_reg; | |
8271 | struct mlx5_ifc_paos_reg_bits paos_reg; | |
8272 | struct mlx5_ifc_pcap_reg_bits pcap_reg; | |
8273 | struct mlx5_ifc_peir_reg_bits peir_reg; | |
8274 | struct mlx5_ifc_pelc_reg_bits pelc_reg; | |
8275 | struct mlx5_ifc_pfcc_reg_bits pfcc_reg; | |
1c64bf6f | 8276 | struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout; |
e281682b SM |
8277 | struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs; |
8278 | struct mlx5_ifc_pifr_reg_bits pifr_reg; | |
8279 | struct mlx5_ifc_pipg_reg_bits pipg_reg; | |
8280 | struct mlx5_ifc_plbf_reg_bits plbf_reg; | |
8281 | struct mlx5_ifc_plib_reg_bits plib_reg; | |
8282 | struct mlx5_ifc_plpc_reg_bits plpc_reg; | |
8283 | struct mlx5_ifc_pmaos_reg_bits pmaos_reg; | |
8284 | struct mlx5_ifc_pmlp_reg_bits pmlp_reg; | |
8285 | struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg; | |
8286 | struct mlx5_ifc_pmpc_reg_bits pmpc_reg; | |
8287 | struct mlx5_ifc_pmpe_reg_bits pmpe_reg; | |
8288 | struct mlx5_ifc_pmpr_reg_bits pmpr_reg; | |
8289 | struct mlx5_ifc_pmtu_reg_bits pmtu_reg; | |
8290 | struct mlx5_ifc_ppad_reg_bits ppad_reg; | |
8291 | struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg; | |
8ed1a630 | 8292 | struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg; |
e281682b SM |
8293 | struct mlx5_ifc_pplm_reg_bits pplm_reg; |
8294 | struct mlx5_ifc_pplr_reg_bits pplr_reg; | |
8295 | struct mlx5_ifc_ppsc_reg_bits ppsc_reg; | |
8296 | struct mlx5_ifc_pqdr_reg_bits pqdr_reg; | |
8297 | struct mlx5_ifc_pspa_reg_bits pspa_reg; | |
8298 | struct mlx5_ifc_ptas_reg_bits ptas_reg; | |
8299 | struct mlx5_ifc_ptys_reg_bits ptys_reg; | |
7d5e1423 | 8300 | struct mlx5_ifc_mlcr_reg_bits mlcr_reg; |
e281682b SM |
8301 | struct mlx5_ifc_pude_reg_bits pude_reg; |
8302 | struct mlx5_ifc_pvlc_reg_bits pvlc_reg; | |
8303 | struct mlx5_ifc_slrg_reg_bits slrg_reg; | |
8304 | struct mlx5_ifc_sltp_reg_bits sltp_reg; | |
f9a1ef72 EE |
8305 | struct mlx5_ifc_mtpps_reg_bits mtpps_reg; |
8306 | struct mlx5_ifc_mtppse_reg_bits mtppse_reg; | |
e29341fb IT |
8307 | struct mlx5_ifc_fpga_ctrl_bits fpga_ctrl_bits; |
8308 | struct mlx5_ifc_fpga_cap_bits fpga_cap_bits; | |
47176289 OG |
8309 | struct mlx5_ifc_mcqi_reg_bits mcqi_reg; |
8310 | struct mlx5_ifc_mcc_reg_bits mcc_reg; | |
8311 | struct mlx5_ifc_mcda_reg_bits mcda_reg; | |
b4ff3a36 | 8312 | u8 reserved_at_0[0x60e0]; |
e281682b SM |
8313 | }; |
8314 | ||
8315 | union mlx5_ifc_debug_enhancements_document_bits { | |
8316 | struct mlx5_ifc_health_buffer_bits health_buffer; | |
b4ff3a36 | 8317 | u8 reserved_at_0[0x200]; |
e281682b SM |
8318 | }; |
8319 | ||
8320 | union mlx5_ifc_uplink_pci_interface_document_bits { | |
8321 | struct mlx5_ifc_initial_seg_bits initial_seg; | |
b4ff3a36 | 8322 | u8 reserved_at_0[0x20060]; |
b775516b EC |
8323 | }; |
8324 | ||
2cc43b49 MG |
8325 | struct mlx5_ifc_set_flow_table_root_out_bits { |
8326 | u8 status[0x8]; | |
b4ff3a36 | 8327 | u8 reserved_at_8[0x18]; |
2cc43b49 MG |
8328 | |
8329 | u8 syndrome[0x20]; | |
8330 | ||
b4ff3a36 | 8331 | u8 reserved_at_40[0x40]; |
2cc43b49 MG |
8332 | }; |
8333 | ||
8334 | struct mlx5_ifc_set_flow_table_root_in_bits { | |
8335 | u8 opcode[0x10]; | |
b4ff3a36 | 8336 | u8 reserved_at_10[0x10]; |
2cc43b49 | 8337 | |
b4ff3a36 | 8338 | u8 reserved_at_20[0x10]; |
2cc43b49 MG |
8339 | u8 op_mod[0x10]; |
8340 | ||
7d5e1423 SM |
8341 | u8 other_vport[0x1]; |
8342 | u8 reserved_at_41[0xf]; | |
8343 | u8 vport_number[0x10]; | |
8344 | ||
8345 | u8 reserved_at_60[0x20]; | |
2cc43b49 MG |
8346 | |
8347 | u8 table_type[0x8]; | |
b4ff3a36 | 8348 | u8 reserved_at_88[0x18]; |
2cc43b49 | 8349 | |
b4ff3a36 | 8350 | u8 reserved_at_a0[0x8]; |
2cc43b49 MG |
8351 | u8 table_id[0x18]; |
8352 | ||
500a3d0d ES |
8353 | u8 reserved_at_c0[0x8]; |
8354 | u8 underlay_qpn[0x18]; | |
8355 | u8 reserved_at_e0[0x120]; | |
2cc43b49 MG |
8356 | }; |
8357 | ||
34a40e68 | 8358 | enum { |
84df61eb AH |
8359 | MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0), |
8360 | MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15), | |
34a40e68 MG |
8361 | }; |
8362 | ||
8363 | struct mlx5_ifc_modify_flow_table_out_bits { | |
8364 | u8 status[0x8]; | |
b4ff3a36 | 8365 | u8 reserved_at_8[0x18]; |
34a40e68 MG |
8366 | |
8367 | u8 syndrome[0x20]; | |
8368 | ||
b4ff3a36 | 8369 | u8 reserved_at_40[0x40]; |
34a40e68 MG |
8370 | }; |
8371 | ||
8372 | struct mlx5_ifc_modify_flow_table_in_bits { | |
8373 | u8 opcode[0x10]; | |
b4ff3a36 | 8374 | u8 reserved_at_10[0x10]; |
34a40e68 | 8375 | |
b4ff3a36 | 8376 | u8 reserved_at_20[0x10]; |
34a40e68 MG |
8377 | u8 op_mod[0x10]; |
8378 | ||
7d5e1423 SM |
8379 | u8 other_vport[0x1]; |
8380 | u8 reserved_at_41[0xf]; | |
8381 | u8 vport_number[0x10]; | |
34a40e68 | 8382 | |
b4ff3a36 | 8383 | u8 reserved_at_60[0x10]; |
34a40e68 MG |
8384 | u8 modify_field_select[0x10]; |
8385 | ||
8386 | u8 table_type[0x8]; | |
b4ff3a36 | 8387 | u8 reserved_at_88[0x18]; |
34a40e68 | 8388 | |
b4ff3a36 | 8389 | u8 reserved_at_a0[0x8]; |
34a40e68 MG |
8390 | u8 table_id[0x18]; |
8391 | ||
0c90e9c6 | 8392 | struct mlx5_ifc_flow_table_context_bits flow_table_context; |
34a40e68 MG |
8393 | }; |
8394 | ||
4f3961ee SM |
8395 | struct mlx5_ifc_ets_tcn_config_reg_bits { |
8396 | u8 g[0x1]; | |
8397 | u8 b[0x1]; | |
8398 | u8 r[0x1]; | |
8399 | u8 reserved_at_3[0x9]; | |
8400 | u8 group[0x4]; | |
8401 | u8 reserved_at_10[0x9]; | |
8402 | u8 bw_allocation[0x7]; | |
8403 | ||
8404 | u8 reserved_at_20[0xc]; | |
8405 | u8 max_bw_units[0x4]; | |
8406 | u8 reserved_at_30[0x8]; | |
8407 | u8 max_bw_value[0x8]; | |
8408 | }; | |
8409 | ||
8410 | struct mlx5_ifc_ets_global_config_reg_bits { | |
8411 | u8 reserved_at_0[0x2]; | |
8412 | u8 r[0x1]; | |
8413 | u8 reserved_at_3[0x1d]; | |
8414 | ||
8415 | u8 reserved_at_20[0xc]; | |
8416 | u8 max_bw_units[0x4]; | |
8417 | u8 reserved_at_30[0x8]; | |
8418 | u8 max_bw_value[0x8]; | |
8419 | }; | |
8420 | ||
8421 | struct mlx5_ifc_qetc_reg_bits { | |
8422 | u8 reserved_at_0[0x8]; | |
8423 | u8 port_number[0x8]; | |
8424 | u8 reserved_at_10[0x30]; | |
8425 | ||
8426 | struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8]; | |
8427 | struct mlx5_ifc_ets_global_config_reg_bits global_configuration; | |
8428 | }; | |
8429 | ||
8430 | struct mlx5_ifc_qtct_reg_bits { | |
8431 | u8 reserved_at_0[0x8]; | |
8432 | u8 port_number[0x8]; | |
8433 | u8 reserved_at_10[0xd]; | |
8434 | u8 prio[0x3]; | |
8435 | ||
8436 | u8 reserved_at_20[0x1d]; | |
8437 | u8 tclass[0x3]; | |
8438 | }; | |
8439 | ||
7d5e1423 SM |
8440 | struct mlx5_ifc_mcia_reg_bits { |
8441 | u8 l[0x1]; | |
8442 | u8 reserved_at_1[0x7]; | |
8443 | u8 module[0x8]; | |
8444 | u8 reserved_at_10[0x8]; | |
8445 | u8 status[0x8]; | |
8446 | ||
8447 | u8 i2c_device_address[0x8]; | |
8448 | u8 page_number[0x8]; | |
8449 | u8 device_address[0x10]; | |
8450 | ||
8451 | u8 reserved_at_40[0x10]; | |
8452 | u8 size[0x10]; | |
8453 | ||
8454 | u8 reserved_at_60[0x20]; | |
8455 | ||
8456 | u8 dword_0[0x20]; | |
8457 | u8 dword_1[0x20]; | |
8458 | u8 dword_2[0x20]; | |
8459 | u8 dword_3[0x20]; | |
8460 | u8 dword_4[0x20]; | |
8461 | u8 dword_5[0x20]; | |
8462 | u8 dword_6[0x20]; | |
8463 | u8 dword_7[0x20]; | |
8464 | u8 dword_8[0x20]; | |
8465 | u8 dword_9[0x20]; | |
8466 | u8 dword_10[0x20]; | |
8467 | u8 dword_11[0x20]; | |
8468 | }; | |
8469 | ||
7486216b SM |
8470 | struct mlx5_ifc_dcbx_param_bits { |
8471 | u8 dcbx_cee_cap[0x1]; | |
8472 | u8 dcbx_ieee_cap[0x1]; | |
8473 | u8 dcbx_standby_cap[0x1]; | |
8474 | u8 reserved_at_0[0x5]; | |
8475 | u8 port_number[0x8]; | |
8476 | u8 reserved_at_10[0xa]; | |
8477 | u8 max_application_table_size[6]; | |
8478 | u8 reserved_at_20[0x15]; | |
8479 | u8 version_oper[0x3]; | |
8480 | u8 reserved_at_38[5]; | |
8481 | u8 version_admin[0x3]; | |
8482 | u8 willing_admin[0x1]; | |
8483 | u8 reserved_at_41[0x3]; | |
8484 | u8 pfc_cap_oper[0x4]; | |
8485 | u8 reserved_at_48[0x4]; | |
8486 | u8 pfc_cap_admin[0x4]; | |
8487 | u8 reserved_at_50[0x4]; | |
8488 | u8 num_of_tc_oper[0x4]; | |
8489 | u8 reserved_at_58[0x4]; | |
8490 | u8 num_of_tc_admin[0x4]; | |
8491 | u8 remote_willing[0x1]; | |
8492 | u8 reserved_at_61[3]; | |
8493 | u8 remote_pfc_cap[4]; | |
8494 | u8 reserved_at_68[0x14]; | |
8495 | u8 remote_num_of_tc[0x4]; | |
8496 | u8 reserved_at_80[0x18]; | |
8497 | u8 error[0x8]; | |
8498 | u8 reserved_at_a0[0x160]; | |
8499 | }; | |
84df61eb AH |
8500 | |
8501 | struct mlx5_ifc_lagc_bits { | |
8502 | u8 reserved_at_0[0x1d]; | |
8503 | u8 lag_state[0x3]; | |
8504 | ||
8505 | u8 reserved_at_20[0x14]; | |
8506 | u8 tx_remap_affinity_2[0x4]; | |
8507 | u8 reserved_at_38[0x4]; | |
8508 | u8 tx_remap_affinity_1[0x4]; | |
8509 | }; | |
8510 | ||
8511 | struct mlx5_ifc_create_lag_out_bits { | |
8512 | u8 status[0x8]; | |
8513 | u8 reserved_at_8[0x18]; | |
8514 | ||
8515 | u8 syndrome[0x20]; | |
8516 | ||
8517 | u8 reserved_at_40[0x40]; | |
8518 | }; | |
8519 | ||
8520 | struct mlx5_ifc_create_lag_in_bits { | |
8521 | u8 opcode[0x10]; | |
8522 | u8 reserved_at_10[0x10]; | |
8523 | ||
8524 | u8 reserved_at_20[0x10]; | |
8525 | u8 op_mod[0x10]; | |
8526 | ||
8527 | struct mlx5_ifc_lagc_bits ctx; | |
8528 | }; | |
8529 | ||
8530 | struct mlx5_ifc_modify_lag_out_bits { | |
8531 | u8 status[0x8]; | |
8532 | u8 reserved_at_8[0x18]; | |
8533 | ||
8534 | u8 syndrome[0x20]; | |
8535 | ||
8536 | u8 reserved_at_40[0x40]; | |
8537 | }; | |
8538 | ||
8539 | struct mlx5_ifc_modify_lag_in_bits { | |
8540 | u8 opcode[0x10]; | |
8541 | u8 reserved_at_10[0x10]; | |
8542 | ||
8543 | u8 reserved_at_20[0x10]; | |
8544 | u8 op_mod[0x10]; | |
8545 | ||
8546 | u8 reserved_at_40[0x20]; | |
8547 | u8 field_select[0x20]; | |
8548 | ||
8549 | struct mlx5_ifc_lagc_bits ctx; | |
8550 | }; | |
8551 | ||
8552 | struct mlx5_ifc_query_lag_out_bits { | |
8553 | u8 status[0x8]; | |
8554 | u8 reserved_at_8[0x18]; | |
8555 | ||
8556 | u8 syndrome[0x20]; | |
8557 | ||
8558 | u8 reserved_at_40[0x40]; | |
8559 | ||
8560 | struct mlx5_ifc_lagc_bits ctx; | |
8561 | }; | |
8562 | ||
8563 | struct mlx5_ifc_query_lag_in_bits { | |
8564 | u8 opcode[0x10]; | |
8565 | u8 reserved_at_10[0x10]; | |
8566 | ||
8567 | u8 reserved_at_20[0x10]; | |
8568 | u8 op_mod[0x10]; | |
8569 | ||
8570 | u8 reserved_at_40[0x40]; | |
8571 | }; | |
8572 | ||
8573 | struct mlx5_ifc_destroy_lag_out_bits { | |
8574 | u8 status[0x8]; | |
8575 | u8 reserved_at_8[0x18]; | |
8576 | ||
8577 | u8 syndrome[0x20]; | |
8578 | ||
8579 | u8 reserved_at_40[0x40]; | |
8580 | }; | |
8581 | ||
8582 | struct mlx5_ifc_destroy_lag_in_bits { | |
8583 | u8 opcode[0x10]; | |
8584 | u8 reserved_at_10[0x10]; | |
8585 | ||
8586 | u8 reserved_at_20[0x10]; | |
8587 | u8 op_mod[0x10]; | |
8588 | ||
8589 | u8 reserved_at_40[0x40]; | |
8590 | }; | |
8591 | ||
8592 | struct mlx5_ifc_create_vport_lag_out_bits { | |
8593 | u8 status[0x8]; | |
8594 | u8 reserved_at_8[0x18]; | |
8595 | ||
8596 | u8 syndrome[0x20]; | |
8597 | ||
8598 | u8 reserved_at_40[0x40]; | |
8599 | }; | |
8600 | ||
8601 | struct mlx5_ifc_create_vport_lag_in_bits { | |
8602 | u8 opcode[0x10]; | |
8603 | u8 reserved_at_10[0x10]; | |
8604 | ||
8605 | u8 reserved_at_20[0x10]; | |
8606 | u8 op_mod[0x10]; | |
8607 | ||
8608 | u8 reserved_at_40[0x40]; | |
8609 | }; | |
8610 | ||
8611 | struct mlx5_ifc_destroy_vport_lag_out_bits { | |
8612 | u8 status[0x8]; | |
8613 | u8 reserved_at_8[0x18]; | |
8614 | ||
8615 | u8 syndrome[0x20]; | |
8616 | ||
8617 | u8 reserved_at_40[0x40]; | |
8618 | }; | |
8619 | ||
8620 | struct mlx5_ifc_destroy_vport_lag_in_bits { | |
8621 | u8 opcode[0x10]; | |
8622 | u8 reserved_at_10[0x10]; | |
8623 | ||
8624 | u8 reserved_at_20[0x10]; | |
8625 | u8 op_mod[0x10]; | |
8626 | ||
8627 | u8 reserved_at_40[0x40]; | |
8628 | }; | |
8629 | ||
d29b796a | 8630 | #endif /* MLX5_IFC_H */ |