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net/mlx5_core: Firmware commands to support flow counters
[mirror_ubuntu-bionic-kernel.git] / include / linux / mlx5 / mlx5_ifc.h
CommitLineData
d29b796a 1/*
e281682b 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
d29b796a
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
e281682b 31*/
d29b796a
EC		 32#ifndef MLX5_IFC_H
33#define MLX5_IFC_H
34
e281682b
SM		 35enum {
36 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
37 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
38 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
39 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
40 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
41 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
42 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
43 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
44 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
45 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
46 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
47 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
48 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
49 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
50 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
51 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
52 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
53 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
54 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
55 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
56 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
57 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
58 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
59 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb
60};
61
62enum {
63 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
64 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
65 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
66 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
67};
68
f91e6d89
EBE		 69enum {
70 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
71 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
72};
73
d29b796a
EC		 74enum {
75 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
76 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
77 MLX5_CMD_OP_INIT_HCA = 0x102,
78 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
79 MLX5_CMD_OP_ENABLE_HCA = 0x104,
80 MLX5_CMD_OP_DISABLE_HCA = 0x105,
81 MLX5_CMD_OP_QUERY_PAGES = 0x107,
82 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
83 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
e281682b
SM		 84 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
85 MLX5_CMD_OP_SET_ISSI = 0x10b,
d29b796a
EC		 86 MLX5_CMD_OP_CREATE_MKEY = 0x200,
87 MLX5_CMD_OP_QUERY_MKEY = 0x201,
88 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
89 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
90 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
91 MLX5_CMD_OP_CREATE_EQ = 0x301,
92 MLX5_CMD_OP_DESTROY_EQ = 0x302,
93 MLX5_CMD_OP_QUERY_EQ = 0x303,
94 MLX5_CMD_OP_GEN_EQE = 0x304,
95 MLX5_CMD_OP_CREATE_CQ = 0x400,
96 MLX5_CMD_OP_DESTROY_CQ = 0x401,
97 MLX5_CMD_OP_QUERY_CQ = 0x402,
98 MLX5_CMD_OP_MODIFY_CQ = 0x403,
99 MLX5_CMD_OP_CREATE_QP = 0x500,
100 MLX5_CMD_OP_DESTROY_QP = 0x501,
101 MLX5_CMD_OP_RST2INIT_QP = 0x502,
102 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
103 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
104 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
105 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
106 MLX5_CMD_OP_2ERR_QP = 0x507,
107 MLX5_CMD_OP_2RST_QP = 0x50a,
108 MLX5_CMD_OP_QUERY_QP = 0x50b,
e281682b 109 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
d29b796a
EC		 110 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
111 MLX5_CMD_OP_CREATE_PSV = 0x600,
112 MLX5_CMD_OP_DESTROY_PSV = 0x601,
113 MLX5_CMD_OP_CREATE_SRQ = 0x700,
114 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
115 MLX5_CMD_OP_QUERY_SRQ = 0x702,
116 MLX5_CMD_OP_ARM_RQ = 0x703,
e281682b
SM		 117 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
118 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
119 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
120 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
d29b796a
EC		 121 MLX5_CMD_OP_CREATE_DCT = 0x710,
122 MLX5_CMD_OP_DESTROY_DCT = 0x711,
123 MLX5_CMD_OP_DRAIN_DCT = 0x712,
124 MLX5_CMD_OP_QUERY_DCT = 0x713,
125 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
126 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
127 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
128 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
129 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
130 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
131 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
e281682b 132 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
d29b796a 133 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
e281682b
SM		 134 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
135 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
136 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
137 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
d29b796a
EC		 138 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
139 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
140 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
141 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
142 MLX5_CMD_OP_ALLOC_PD = 0x800,
143 MLX5_CMD_OP_DEALLOC_PD = 0x801,
144 MLX5_CMD_OP_ALLOC_UAR = 0x802,
145 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
146 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
147 MLX5_CMD_OP_ACCESS_REG = 0x805,
148 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
e281682b 149 MLX5_CMD_OP_DETTACH_FROM_MCG = 0x807,
d29b796a
EC		 150 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
151 MLX5_CMD_OP_MAD_IFC = 0x50d,
152 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
153 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
154 MLX5_CMD_OP_NOP = 0x80d,
155 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
156 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
e281682b
SM		 157 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
158 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
159 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
160 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
161 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
162 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
163 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
164 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
165 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
166 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
167 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
168 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
928cfe87
TT		 169 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
170 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
d29b796a
EC		 171 MLX5_CMD_OP_CREATE_TIR = 0x900,
172 MLX5_CMD_OP_MODIFY_TIR = 0x901,
173 MLX5_CMD_OP_DESTROY_TIR = 0x902,
174 MLX5_CMD_OP_QUERY_TIR = 0x903,
d29b796a
EC		 175 MLX5_CMD_OP_CREATE_SQ = 0x904,
176 MLX5_CMD_OP_MODIFY_SQ = 0x905,
177 MLX5_CMD_OP_DESTROY_SQ = 0x906,
178 MLX5_CMD_OP_QUERY_SQ = 0x907,
179 MLX5_CMD_OP_CREATE_RQ = 0x908,
180 MLX5_CMD_OP_MODIFY_RQ = 0x909,
181 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
182 MLX5_CMD_OP_QUERY_RQ = 0x90b,
183 MLX5_CMD_OP_CREATE_RMP = 0x90c,
184 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
185 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
186 MLX5_CMD_OP_QUERY_RMP = 0x90f,
e281682b
SM		 187 MLX5_CMD_OP_CREATE_TIS = 0x912,
188 MLX5_CMD_OP_MODIFY_TIS = 0x913,
189 MLX5_CMD_OP_DESTROY_TIS = 0x914,
190 MLX5_CMD_OP_QUERY_TIS = 0x915,
191 MLX5_CMD_OP_CREATE_RQT = 0x916,
192 MLX5_CMD_OP_MODIFY_RQT = 0x917,
193 MLX5_CMD_OP_DESTROY_RQT = 0x918,
194 MLX5_CMD_OP_QUERY_RQT = 0x919,
2cc43b49 195 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
e281682b
SM		 196 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
197 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
198 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
199 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
200 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
201 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
202 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
203 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
34a40e68 204 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
9dc0b289
AV		 205 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
206 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
207 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
34a40e68 208 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c
e281682b
SM		 209};
210
211struct mlx5_ifc_flow_table_fields_supported_bits {
212 u8 outer_dmac[0x1];
213 u8 outer_smac[0x1];
214 u8 outer_ether_type[0x1];
b4ff3a36 215 u8 reserved_at_3[0x1];
e281682b
SM		 216 u8 outer_first_prio[0x1];
217 u8 outer_first_cfi[0x1];
218 u8 outer_first_vid[0x1];
b4ff3a36 219 u8 reserved_at_7[0x1];
e281682b
SM		 220 u8 outer_second_prio[0x1];
221 u8 outer_second_cfi[0x1];
222 u8 outer_second_vid[0x1];
b4ff3a36 223 u8 reserved_at_b[0x1];
e281682b
SM		 224 u8 outer_sip[0x1];
225 u8 outer_dip[0x1];
226 u8 outer_frag[0x1];
227 u8 outer_ip_protocol[0x1];
228 u8 outer_ip_ecn[0x1];
229 u8 outer_ip_dscp[0x1];
230 u8 outer_udp_sport[0x1];
231 u8 outer_udp_dport[0x1];
232 u8 outer_tcp_sport[0x1];
233 u8 outer_tcp_dport[0x1];
234 u8 outer_tcp_flags[0x1];
235 u8 outer_gre_protocol[0x1];
236 u8 outer_gre_key[0x1];
237 u8 outer_vxlan_vni[0x1];
b4ff3a36 238 u8 reserved_at_1a[0x5];
e281682b
SM		 239 u8 source_eswitch_port[0x1];
240
241 u8 inner_dmac[0x1];
242 u8 inner_smac[0x1];
243 u8 inner_ether_type[0x1];
b4ff3a36 244 u8 reserved_at_23[0x1];
e281682b
SM		 245 u8 inner_first_prio[0x1];
246 u8 inner_first_cfi[0x1];
247 u8 inner_first_vid[0x1];
b4ff3a36 248 u8 reserved_at_27[0x1];
e281682b
SM		 249 u8 inner_second_prio[0x1];
250 u8 inner_second_cfi[0x1];
251 u8 inner_second_vid[0x1];
b4ff3a36 252 u8 reserved_at_2b[0x1];
e281682b
SM		 253 u8 inner_sip[0x1];
254 u8 inner_dip[0x1];
255 u8 inner_frag[0x1];
256 u8 inner_ip_protocol[0x1];
257 u8 inner_ip_ecn[0x1];
258 u8 inner_ip_dscp[0x1];
259 u8 inner_udp_sport[0x1];
260 u8 inner_udp_dport[0x1];
261 u8 inner_tcp_sport[0x1];
262 u8 inner_tcp_dport[0x1];
263 u8 inner_tcp_flags[0x1];
b4ff3a36 264 u8 reserved_at_37[0x9];
e281682b 265
b4ff3a36 266 u8 reserved_at_40[0x40];
e281682b
SM		 267};
268
269struct mlx5_ifc_flow_table_prop_layout_bits {
270 u8 ft_support[0x1];
9dc0b289
AV		 271 u8 reserved_at_1[0x1];
272 u8 flow_counter[0x1];
26a81453 273 u8 flow_modify_en[0x1];
2cc43b49 274 u8 modify_root[0x1];
34a40e68
MG		 275 u8 identified_miss_table_mode[0x1];
276 u8 flow_table_modify[0x1];
b4ff3a36 277 u8 reserved_at_7[0x19];
e281682b 278
b4ff3a36 279 u8 reserved_at_20[0x2];
e281682b 280 u8 log_max_ft_size[0x6];
b4ff3a36 281 u8 reserved_at_28[0x10];
e281682b
SM		 282 u8 max_ft_level[0x8];
283
b4ff3a36 284 u8 reserved_at_40[0x20];
e281682b 285
b4ff3a36 286 u8 reserved_at_60[0x18];
e281682b
SM		 287 u8 log_max_ft_num[0x8];
288
b4ff3a36 289 u8 reserved_at_80[0x18];
e281682b
SM		 290 u8 log_max_destination[0x8];
291
b4ff3a36 292 u8 reserved_at_a0[0x18];
e281682b
SM		 293 u8 log_max_flow[0x8];
294
b4ff3a36 295 u8 reserved_at_c0[0x40];
e281682b
SM		 296
297 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
298
299 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
300};
301
302struct mlx5_ifc_odp_per_transport_service_cap_bits {
303 u8 send[0x1];
304 u8 receive[0x1];
305 u8 write[0x1];
306 u8 read[0x1];
b4ff3a36 307 u8 reserved_at_4[0x1];
e281682b 308 u8 srq_receive[0x1];
b4ff3a36 309 u8 reserved_at_6[0x1a];
e281682b
SM		 310};
311
b4d1f032 312struct mlx5_ifc_ipv4_layout_bits {
b4ff3a36 313 u8 reserved_at_0[0x60];
b4d1f032
MG		 314
315 u8 ipv4[0x20];
316};
317
318struct mlx5_ifc_ipv6_layout_bits {
319 u8 ipv6[16][0x8];
320};
321
322union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
323 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
324 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
b4ff3a36 325 u8 reserved_at_0[0x80];
b4d1f032
MG		 326};
327
e281682b
SM		 328struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
329 u8 smac_47_16[0x20];
330
331 u8 smac_15_0[0x10];
332 u8 ethertype[0x10];
333
334 u8 dmac_47_16[0x20];
335
336 u8 dmac_15_0[0x10];
337 u8 first_prio[0x3];
338 u8 first_cfi[0x1];
339 u8 first_vid[0xc];
340
341 u8 ip_protocol[0x8];
342 u8 ip_dscp[0x6];
343 u8 ip_ecn[0x2];
344 u8 vlan_tag[0x1];
b4ff3a36 345 u8 reserved_at_91[0x1];
e281682b 346 u8 frag[0x1];
b4ff3a36 347 u8 reserved_at_93[0x4];
e281682b
SM		 348 u8 tcp_flags[0x9];
349
350 u8 tcp_sport[0x10];
351 u8 tcp_dport[0x10];
352
b4ff3a36 353 u8 reserved_at_c0[0x20];
e281682b
SM		 354
355 u8 udp_sport[0x10];
356 u8 udp_dport[0x10];
357
b4d1f032 358 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
e281682b 359
b4d1f032 360 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
e281682b
SM		 361};
362
363struct mlx5_ifc_fte_match_set_misc_bits {
b4ff3a36 364 u8 reserved_at_0[0x20];
e281682b 365
b4ff3a36 366 u8 reserved_at_20[0x10];
e281682b
SM		 367 u8 source_port[0x10];
368
369 u8 outer_second_prio[0x3];
370 u8 outer_second_cfi[0x1];
371 u8 outer_second_vid[0xc];
372 u8 inner_second_prio[0x3];
373 u8 inner_second_cfi[0x1];
374 u8 inner_second_vid[0xc];
375
376 u8 outer_second_vlan_tag[0x1];
377 u8 inner_second_vlan_tag[0x1];
b4ff3a36 378 u8 reserved_at_62[0xe];
e281682b
SM		 379 u8 gre_protocol[0x10];
380
381 u8 gre_key_h[0x18];
382 u8 gre_key_l[0x8];
383
384 u8 vxlan_vni[0x18];
b4ff3a36 385 u8 reserved_at_b8[0x8];
e281682b 386
b4ff3a36 387 u8 reserved_at_c0[0x20];
e281682b 388
b4ff3a36 389 u8 reserved_at_e0[0xc];
e281682b
SM		 390 u8 outer_ipv6_flow_label[0x14];
391
b4ff3a36 392 u8 reserved_at_100[0xc];
e281682b
SM		 393 u8 inner_ipv6_flow_label[0x14];
394
b4ff3a36 395 u8 reserved_at_120[0xe0];
e281682b
SM		 396};
397
398struct mlx5_ifc_cmd_pas_bits {
399 u8 pa_h[0x20];
400
401 u8 pa_l[0x14];
b4ff3a36 402 u8 reserved_at_34[0xc];
e281682b
SM		 403};
404
405struct mlx5_ifc_uint64_bits {
406 u8 hi[0x20];
407
408 u8 lo[0x20];
409};
410
411enum {
412 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
413 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
414 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
415 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
416 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
417 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
418 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
419 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
420 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
421 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
422};
423
424struct mlx5_ifc_ads_bits {
425 u8 fl[0x1];
426 u8 free_ar[0x1];
b4ff3a36 427 u8 reserved_at_2[0xe];
e281682b
SM		 428 u8 pkey_index[0x10];
429
b4ff3a36 430 u8 reserved_at_20[0x8];
e281682b
SM		 431 u8 grh[0x1];
432 u8 mlid[0x7];
433 u8 rlid[0x10];
434
435 u8 ack_timeout[0x5];
b4ff3a36 436 u8 reserved_at_45[0x3];
e281682b 437 u8 src_addr_index[0x8];
b4ff3a36 438 u8 reserved_at_50[0x4];
e281682b
SM		 439 u8 stat_rate[0x4];
440 u8 hop_limit[0x8];
441
b4ff3a36 442 u8 reserved_at_60[0x4];
e281682b
SM		 443 u8 tclass[0x8];
444 u8 flow_label[0x14];
445
446 u8 rgid_rip[16][0x8];
447
b4ff3a36 448 u8 reserved_at_100[0x4];
e281682b
SM		 449 u8 f_dscp[0x1];
450 u8 f_ecn[0x1];
b4ff3a36 451 u8 reserved_at_106[0x1];
e281682b
SM		 452 u8 f_eth_prio[0x1];
453 u8 ecn[0x2];
454 u8 dscp[0x6];
455 u8 udp_sport[0x10];
456
457 u8 dei_cfi[0x1];
458 u8 eth_prio[0x3];
459 u8 sl[0x4];
460 u8 port[0x8];
461 u8 rmac_47_32[0x10];
462
463 u8 rmac_31_0[0x20];
464};
465
466struct mlx5_ifc_flow_table_nic_cap_bits {
b3638e1a
MG		 467 u8 nic_rx_multi_path_tirs[0x1];
468 u8 reserved_at_1[0x1ff];
e281682b
SM		 469
470 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
471
b4ff3a36 472 u8 reserved_at_400[0x200];
e281682b
SM		 473
474 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
475
476 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
477
b4ff3a36 478 u8 reserved_at_a00[0x200];
e281682b
SM		 479
480 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
481
b4ff3a36 482 u8 reserved_at_e00[0x7200];
e281682b
SM		 483};
484
495716b1 485struct mlx5_ifc_flow_table_eswitch_cap_bits {
b4ff3a36 486 u8 reserved_at_0[0x200];
495716b1
SM		 487
488 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
489
490 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
491
492 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
493
b4ff3a36 494 u8 reserved_at_800[0x7800];
495716b1
SM		 495};
496
d6666753
SM		 497struct mlx5_ifc_e_switch_cap_bits {
498 u8 vport_svlan_strip[0x1];
499 u8 vport_cvlan_strip[0x1];
500 u8 vport_svlan_insert[0x1];
501 u8 vport_cvlan_insert_if_not_exist[0x1];
502 u8 vport_cvlan_insert_overwrite[0x1];
b4ff3a36 503 u8 reserved_at_5[0x1b];
d6666753 504
b4ff3a36 505 u8 reserved_at_20[0x7e0];
d6666753
SM		 506};
507
e281682b
SM		 508struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
509 u8 csum_cap[0x1];
510 u8 vlan_cap[0x1];
511 u8 lro_cap[0x1];
512 u8 lro_psh_flag[0x1];
513 u8 lro_time_stamp[0x1];
b4ff3a36 514 u8 reserved_at_5[0x3];
66189961 515 u8 self_lb_en_modifiable[0x1];
b4ff3a36 516 u8 reserved_at_9[0x2];
e281682b 517 u8 max_lso_cap[0x5];
b4ff3a36 518 u8 reserved_at_10[0x4];
e281682b 519 u8 rss_ind_tbl_cap[0x4];
7d5e1423
SM		 520 u8 reg_umr_sq[0x1];
521 u8 scatter_fcs[0x1];
522 u8 reserved_at_1a[0x1];
e281682b 523 u8 tunnel_lso_const_out_ip_id[0x1];
b4ff3a36 524 u8 reserved_at_1c[0x2];
e281682b
SM		 525 u8 tunnel_statless_gre[0x1];
526 u8 tunnel_stateless_vxlan[0x1];
527
b4ff3a36 528 u8 reserved_at_20[0x20];
e281682b 529
b4ff3a36 530 u8 reserved_at_40[0x10];
e281682b
SM		 531 u8 lro_min_mss_size[0x10];
532
b4ff3a36 533 u8 reserved_at_60[0x120];
e281682b
SM		 534
535 u8 lro_timer_supported_periods[4][0x20];
536
b4ff3a36 537 u8 reserved_at_200[0x600];
e281682b
SM		 538};
539
540struct mlx5_ifc_roce_cap_bits {
541 u8 roce_apm[0x1];
b4ff3a36 542 u8 reserved_at_1[0x1f];
e281682b 543
b4ff3a36 544 u8 reserved_at_20[0x60];
e281682b 545
b4ff3a36 546 u8 reserved_at_80[0xc];
e281682b 547 u8 l3_type[0x4];
b4ff3a36 548 u8 reserved_at_90[0x8];
e281682b
SM		 549 u8 roce_version[0x8];
550
b4ff3a36 551 u8 reserved_at_a0[0x10];
e281682b
SM		 552 u8 r_roce_dest_udp_port[0x10];
553
554 u8 r_roce_max_src_udp_port[0x10];
555 u8 r_roce_min_src_udp_port[0x10];
556
b4ff3a36 557 u8 reserved_at_e0[0x10];
e281682b
SM		 558 u8 roce_address_table_size[0x10];
559
b4ff3a36 560 u8 reserved_at_100[0x700];
e281682b
SM		 561};
562
563enum {
564 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
565 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
566 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
567 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
568 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
569 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
570 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
571 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
572 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
573};
574
575enum {
576 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
577 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
578 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
579 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
580 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
581 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
582 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
583 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
584 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
585};
586
587struct mlx5_ifc_atomic_caps_bits {
b4ff3a36 588 u8 reserved_at_0[0x40];
e281682b 589
f91e6d89 590 u8 atomic_req_8B_endianess_mode[0x2];
b4ff3a36 591 u8 reserved_at_42[0x4];
f91e6d89 592 u8 supported_atomic_req_8B_endianess_mode_1[0x1];
e281682b 593
b4ff3a36 594 u8 reserved_at_47[0x19];
e281682b 595
b4ff3a36 596 u8 reserved_at_60[0x20];
e281682b 597
b4ff3a36 598 u8 reserved_at_80[0x10];
f91e6d89 599 u8 atomic_operations[0x10];
e281682b 600
b4ff3a36 601 u8 reserved_at_a0[0x10];
f91e6d89
EBE		 602 u8 atomic_size_qp[0x10];
603
b4ff3a36 604 u8 reserved_at_c0[0x10];
e281682b
SM		 605 u8 atomic_size_dc[0x10];
606
b4ff3a36 607 u8 reserved_at_e0[0x720];
e281682b
SM		 608};
609
610struct mlx5_ifc_odp_cap_bits {
b4ff3a36 611 u8 reserved_at_0[0x40];
e281682b
SM		 612
613 u8 sig[0x1];
b4ff3a36 614 u8 reserved_at_41[0x1f];
e281682b 615
b4ff3a36 616 u8 reserved_at_60[0x20];
e281682b
SM		 617
618 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
619
620 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
621
622 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
623
b4ff3a36 624 u8 reserved_at_e0[0x720];
e281682b
SM		 625};
626
3f0393a5
SG		 627struct mlx5_ifc_calc_op {
628 u8 reserved_at_0[0x10];
629 u8 reserved_at_10[0x9];
630 u8 op_swap_endianness[0x1];
631 u8 op_min[0x1];
632 u8 op_xor[0x1];
633 u8 op_or[0x1];
634 u8 op_and[0x1];
635 u8 op_max[0x1];
636 u8 op_add[0x1];
637};
638
639struct mlx5_ifc_vector_calc_cap_bits {
640 u8 calc_matrix[0x1];
641 u8 reserved_at_1[0x1f];
642 u8 reserved_at_20[0x8];
643 u8 max_vec_count[0x8];
644 u8 reserved_at_30[0xd];
645 u8 max_chunk_size[0x3];
646 struct mlx5_ifc_calc_op calc0;
647 struct mlx5_ifc_calc_op calc1;
648 struct mlx5_ifc_calc_op calc2;
649 struct mlx5_ifc_calc_op calc3;
650
651 u8 reserved_at_e0[0x720];
652};
653
e281682b
SM		 654enum {
655 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
656 MLX5_WQ_TYPE_CYCLIC = 0x1,
7d5e1423 657 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
e281682b
SM		 658};
659
660enum {
661 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
662 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
663};
664
665enum {
666 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
667 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
668 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
669 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
670 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
671};
672
673enum {
674 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
675 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
676 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
677 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
678 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
679 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
680};
681
682enum {
683 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
684 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
685};
686
687enum {
688 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
689 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
690 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
691};
692
693enum {
694 MLX5_CAP_PORT_TYPE_IB = 0x0,
695 MLX5_CAP_PORT_TYPE_ETH = 0x1,
d29b796a
EC		 696};
697
b775516b 698struct mlx5_ifc_cmd_hca_cap_bits {
b4ff3a36 699 u8 reserved_at_0[0x80];
b775516b
EC		 700
701 u8 log_max_srq_sz[0x8];
702 u8 log_max_qp_sz[0x8];
b4ff3a36 703 u8 reserved_at_90[0xb];
b775516b
EC		 704 u8 log_max_qp[0x5];
705
b4ff3a36 706 u8 reserved_at_a0[0xb];
e281682b 707 u8 log_max_srq[0x5];
b4ff3a36 708 u8 reserved_at_b0[0x10];
b775516b 709
b4ff3a36 710 u8 reserved_at_c0[0x8];
b775516b 711 u8 log_max_cq_sz[0x8];
b4ff3a36 712 u8 reserved_at_d0[0xb];
b775516b
EC		 713 u8 log_max_cq[0x5];
714
715 u8 log_max_eq_sz[0x8];
b4ff3a36 716 u8 reserved_at_e8[0x2];
b775516b 717 u8 log_max_mkey[0x6];
b4ff3a36 718 u8 reserved_at_f0[0xc];
b775516b
EC		 719 u8 log_max_eq[0x4];
720
721 u8 max_indirection[0x8];
b4ff3a36 722 u8 reserved_at_108[0x1];
b775516b 723 u8 log_max_mrw_sz[0x7];
b4ff3a36 724 u8 reserved_at_110[0x2];
b775516b 725 u8 log_max_bsf_list_size[0x6];
b4ff3a36 726 u8 reserved_at_118[0x2];
b775516b
EC		 727 u8 log_max_klm_list_size[0x6];
728
b4ff3a36 729 u8 reserved_at_120[0xa];
b775516b 730 u8 log_max_ra_req_dc[0x6];
b4ff3a36 731 u8 reserved_at_130[0xa];
b775516b
EC		 732 u8 log_max_ra_res_dc[0x6];
733
b4ff3a36 734 u8 reserved_at_140[0xa];
b775516b 735 u8 log_max_ra_req_qp[0x6];
b4ff3a36 736 u8 reserved_at_150[0xa];
b775516b
EC		 737 u8 log_max_ra_res_qp[0x6];
738
739 u8 pad_cap[0x1];
740 u8 cc_query_allowed[0x1];
741 u8 cc_modify_allowed[0x1];
b4ff3a36 742 u8 reserved_at_163[0xd];
e281682b 743 u8 gid_table_size[0x10];
b775516b 744
e281682b
SM		 745 u8 out_of_seq_cnt[0x1];
746 u8 vport_counters[0x1];
b4ff3a36 747 u8 reserved_at_182[0x4];
b775516b
EC		 748 u8 max_qp_cnt[0xa];
749 u8 pkey_table_size[0x10];
750
e281682b
SM		 751 u8 vport_group_manager[0x1];
752 u8 vhca_group_manager[0x1];
753 u8 ib_virt[0x1];
754 u8 eth_virt[0x1];
b4ff3a36 755 u8 reserved_at_1a4[0x1];
e281682b
SM		 756 u8 ets[0x1];
757 u8 nic_flow_table[0x1];
54f0a411 758 u8 eswitch_flow_table[0x1];
e1c9c62b
TT		 759 u8 early_vf_enable[0x1];
760 u8 reserved_at_1a9[0x2];
b775516b 761 u8 local_ca_ack_delay[0x5];
7d5e1423
SM		 762 u8 reserved_at_1af[0x2];
763 u8 ports_check[0x1];
764 u8 reserved_at_1b2[0x1];
765 u8 disable_link_up[0x1];
766 u8 beacon_led[0x1];
e281682b 767 u8 port_type[0x2];
b775516b
EC		 768 u8 num_ports[0x8];
769
e1c9c62b 770 u8 reserved_at_1c0[0x3];
b775516b 771 u8 log_max_msg[0x5];
e1c9c62b 772 u8 reserved_at_1c8[0x4];
4f3961ee 773 u8 max_tc[0x4];
e1c9c62b 774 u8 reserved_at_1d0[0x6];
928cfe87
TT		 775 u8 rol_s[0x1];
776 u8 rol_g[0x1];
e1c9c62b 777 u8 reserved_at_1d8[0x1];
928cfe87
TT		 778 u8 wol_s[0x1];
779 u8 wol_g[0x1];
780 u8 wol_a[0x1];
781 u8 wol_b[0x1];
782 u8 wol_m[0x1];
783 u8 wol_u[0x1];
784 u8 wol_p[0x1];
b775516b
EC		 785
786 u8 stat_rate_support[0x10];
e1c9c62b 787 u8 reserved_at_1f0[0xc];
e281682b 788 u8 cqe_version[0x4];
b775516b 789
e281682b 790 u8 compact_address_vector[0x1];
7d5e1423
SM		 791 u8 striding_rq[0x1];
792 u8 reserved_at_201[0x2];
1015c2e8 793 u8 ipoib_basic_offloads[0x1];
e1c9c62b 794 u8 reserved_at_205[0xa];
e281682b 795 u8 drain_sigerr[0x1];
b775516b
EC		 796 u8 cmdif_checksum[0x2];
797 u8 sigerr_cqe[0x1];
e1c9c62b 798 u8 reserved_at_213[0x1];
b775516b
EC		 799 u8 wq_signature[0x1];
800 u8 sctr_data_cqe[0x1];
e1c9c62b 801 u8 reserved_at_216[0x1];
b775516b
EC		 802 u8 sho[0x1];
803 u8 tph[0x1];
804 u8 rf[0x1];
e281682b 805 u8 dct[0x1];
e1c9c62b 806 u8 reserved_at_21b[0x1];
e281682b 807 u8 eth_net_offloads[0x1];
b775516b
EC		 808 u8 roce[0x1];
809 u8 atomic[0x1];
e1c9c62b 810 u8 reserved_at_21f[0x1];
b775516b
EC		 811
812 u8 cq_oi[0x1];
813 u8 cq_resize[0x1];
814 u8 cq_moderation[0x1];
e1c9c62b 815 u8 reserved_at_223[0x3];
e281682b 816 u8 cq_eq_remap[0x1];
b775516b
EC		 817 u8 pg[0x1];
818 u8 block_lb_mc[0x1];
e1c9c62b 819 u8 reserved_at_229[0x1];
e281682b 820 u8 scqe_break_moderation[0x1];
7d5e1423 821 u8 cq_period_start_from_cqe[0x1];
b775516b 822 u8 cd[0x1];
e1c9c62b 823 u8 reserved_at_22d[0x1];
b775516b 824 u8 apm[0x1];
3f0393a5 825 u8 vector_calc[0x1];
7d5e1423 826 u8 umr_ptr_rlky[0x1];
d2370e0a 827 u8 imaicl[0x1];
e1c9c62b 828 u8 reserved_at_232[0x4];
b775516b
EC		 829 u8 qkv[0x1];
830 u8 pkv[0x1];
b11a4f9c
HE		 831 u8 set_deth_sqpn[0x1];
832 u8 reserved_at_239[0x3];
b775516b
EC		 833 u8 xrc[0x1];
834 u8 ud[0x1];
835 u8 uc[0x1];
836 u8 rc[0x1];
837
e1c9c62b 838 u8 reserved_at_240[0xa];
b775516b 839 u8 uar_sz[0x6];
e1c9c62b 840 u8 reserved_at_250[0x8];
b775516b
EC		 841 u8 log_pg_sz[0x8];
842
843 u8 bf[0x1];
e1c9c62b 844 u8 reserved_at_261[0x1];
e281682b 845 u8 pad_tx_eth_packet[0x1];
e1c9c62b 846 u8 reserved_at_263[0x8];
b775516b 847 u8 log_bf_reg_size[0x5];
e1c9c62b 848 u8 reserved_at_270[0x10];
b775516b 849
e1c9c62b 850 u8 reserved_at_280[0x10];
b775516b
EC		 851 u8 max_wqe_sz_sq[0x10];
852
e1c9c62b 853 u8 reserved_at_2a0[0x10];
b775516b
EC		 854 u8 max_wqe_sz_rq[0x10];
855
e1c9c62b 856 u8 reserved_at_2c0[0x10];
b775516b
EC		 857 u8 max_wqe_sz_sq_dc[0x10];
858
e1c9c62b 859 u8 reserved_at_2e0[0x7];
b775516b
EC		 860 u8 max_qp_mcg[0x19];
861
e1c9c62b 862 u8 reserved_at_300[0x18];
b775516b
EC		 863 u8 log_max_mcg[0x8];
864
e1c9c62b 865 u8 reserved_at_320[0x3];
e281682b 866 u8 log_max_transport_domain[0x5];
e1c9c62b 867 u8 reserved_at_328[0x3];
b775516b 868 u8 log_max_pd[0x5];
e1c9c62b 869 u8 reserved_at_330[0xb];
b775516b
EC		 870 u8 log_max_xrcd[0x5];
871
e1c9c62b 872 u8 reserved_at_340[0x20];
b775516b 873
e1c9c62b 874 u8 reserved_at_360[0x3];
b775516b 875 u8 log_max_rq[0x5];
e1c9c62b 876 u8 reserved_at_368[0x3];
b775516b 877 u8 log_max_sq[0x5];
e1c9c62b 878 u8 reserved_at_370[0x3];
b775516b 879 u8 log_max_tir[0x5];
e1c9c62b 880 u8 reserved_at_378[0x3];
b775516b
EC		 881 u8 log_max_tis[0x5];
882
e281682b 883 u8 basic_cyclic_rcv_wqe[0x1];
e1c9c62b 884 u8 reserved_at_381[0x2];
e281682b 885 u8 log_max_rmp[0x5];
e1c9c62b 886 u8 reserved_at_388[0x3];
e281682b 887 u8 log_max_rqt[0x5];
e1c9c62b 888 u8 reserved_at_390[0x3];
e281682b 889 u8 log_max_rqt_size[0x5];
e1c9c62b 890 u8 reserved_at_398[0x3];
b775516b
EC		 891 u8 log_max_tis_per_sq[0x5];
892
e1c9c62b 893 u8 reserved_at_3a0[0x3];
e281682b 894 u8 log_max_stride_sz_rq[0x5];
e1c9c62b 895 u8 reserved_at_3a8[0x3];
e281682b 896 u8 log_min_stride_sz_rq[0x5];
e1c9c62b 897 u8 reserved_at_3b0[0x3];
e281682b 898 u8 log_max_stride_sz_sq[0x5];
e1c9c62b 899 u8 reserved_at_3b8[0x3];
e281682b
SM		 900 u8 log_min_stride_sz_sq[0x5];
901
e1c9c62b 902 u8 reserved_at_3c0[0x1b];
e281682b
SM		 903 u8 log_max_wq_sz[0x5];
904
54f0a411 905 u8 nic_vport_change_event[0x1];
e1c9c62b 906 u8 reserved_at_3e1[0xa];
54f0a411 907 u8 log_max_vlan_list[0x5];
e1c9c62b 908 u8 reserved_at_3f0[0x3];
54f0a411 909 u8 log_max_current_mc_list[0x5];
e1c9c62b 910 u8 reserved_at_3f8[0x3];
54f0a411
SM		 911 u8 log_max_current_uc_list[0x5];
912
e1c9c62b 913 u8 reserved_at_400[0x80];
54f0a411 914
e1c9c62b 915 u8 reserved_at_480[0x3];
e281682b 916 u8 log_max_l2_table[0x5];
e1c9c62b 917 u8 reserved_at_488[0x8];
b775516b
EC		 918 u8 log_uar_page_sz[0x10];
919
e1c9c62b 920 u8 reserved_at_4a0[0x20];
048ccca8 921 u8 device_frequency_mhz[0x20];
b0844444 922 u8 device_frequency_khz[0x20];
e1c9c62b
TT		 923
924 u8 reserved_at_500[0x80];
925
926 u8 reserved_at_580[0x3f];
7d5e1423 927 u8 cqe_compression[0x1];
b775516b 928
7d5e1423
SM		 929 u8 cqe_compression_timeout[0x10];
930 u8 cqe_compression_max_num[0x10];
b775516b 931
e1c9c62b 932 u8 reserved_at_5e0[0x220];
b775516b
EC		 933};
934
81848731
SM		 935enum mlx5_flow_destination_type {
936 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
937 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
938 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
e281682b 939};
b775516b 940
e281682b
SM		 941struct mlx5_ifc_dest_format_struct_bits {
942 u8 destination_type[0x8];
943 u8 destination_id[0x18];
b775516b 944
b4ff3a36 945 u8 reserved_at_20[0x20];
e281682b
SM		 946};
947
9dc0b289
AV		 948struct mlx5_ifc_flow_counter_list_bits {
949 u8 reserved_at_0[0x10];
950 u8 flow_counter_id[0x10];
951
952 u8 reserved_at_20[0x20];
953};
954
955union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
956 struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
957 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
958 u8 reserved_at_0[0x40];
959};
960
e281682b
SM		 961struct mlx5_ifc_fte_match_param_bits {
962 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
963
964 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
965
966 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
b775516b 967
b4ff3a36 968 u8 reserved_at_600[0xa00];
b775516b
EC		 969};
970
e281682b
SM		 971enum {
972 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
973 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
974 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
975 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
976 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
977};
b775516b 978
e281682b
SM		 979struct mlx5_ifc_rx_hash_field_select_bits {
980 u8 l3_prot_type[0x1];
981 u8 l4_prot_type[0x1];
982 u8 selected_fields[0x1e];
983};
b775516b 984
e281682b
SM		 985enum {
986 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
987 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
b775516b
EC		 988};
989
e281682b
SM		 990enum {
991 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
992 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
993};
994
995struct mlx5_ifc_wq_bits {
996 u8 wq_type[0x4];
997 u8 wq_signature[0x1];
998 u8 end_padding_mode[0x2];
999 u8 cd_slave[0x1];
b4ff3a36 1000 u8 reserved_at_8[0x18];
b775516b 1001
e281682b
SM		 1002 u8 hds_skip_first_sge[0x1];
1003 u8 log2_hds_buf_size[0x3];
b4ff3a36 1004 u8 reserved_at_24[0x7];
e281682b
SM		 1005 u8 page_offset[0x5];
1006 u8 lwm[0x10];
b775516b 1007
b4ff3a36 1008 u8 reserved_at_40[0x8];
e281682b
SM		 1009 u8 pd[0x18];
1010
b4ff3a36 1011 u8 reserved_at_60[0x8];
e281682b
SM		 1012 u8 uar_page[0x18];
1013
1014 u8 dbr_addr[0x40];
1015
1016 u8 hw_counter[0x20];
1017
1018 u8 sw_counter[0x20];
1019
b4ff3a36 1020 u8 reserved_at_100[0xc];
e281682b 1021 u8 log_wq_stride[0x4];
b4ff3a36 1022 u8 reserved_at_110[0x3];
e281682b 1023 u8 log_wq_pg_sz[0x5];
b4ff3a36 1024 u8 reserved_at_118[0x3];
e281682b
SM		 1025 u8 log_wq_sz[0x5];
1026
7d5e1423
SM		 1027 u8 reserved_at_120[0x15];
1028 u8 log_wqe_num_of_strides[0x3];
1029 u8 two_byte_shift_en[0x1];
1030 u8 reserved_at_139[0x4];
1031 u8 log_wqe_stride_size[0x3];
1032
1033 u8 reserved_at_140[0x4c0];
b775516b 1034
e281682b 1035 struct mlx5_ifc_cmd_pas_bits pas[0];
b775516b
EC		 1036};
1037
e281682b 1038struct mlx5_ifc_rq_num_bits {
b4ff3a36 1039 u8 reserved_at_0[0x8];
e281682b
SM		 1040 u8 rq_num[0x18];
1041};
b775516b 1042
e281682b 1043struct mlx5_ifc_mac_address_layout_bits {
b4ff3a36 1044 u8 reserved_at_0[0x10];
e281682b 1045 u8 mac_addr_47_32[0x10];
b775516b 1046
e281682b
SM		 1047 u8 mac_addr_31_0[0x20];
1048};
1049
c0046cf7 1050struct mlx5_ifc_vlan_layout_bits {
b4ff3a36 1051 u8 reserved_at_0[0x14];
c0046cf7
SM		 1052 u8 vlan[0x0c];
1053
b4ff3a36 1054 u8 reserved_at_20[0x20];
c0046cf7
SM		 1055};
1056
e281682b 1057struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
b4ff3a36 1058 u8 reserved_at_0[0xa0];
e281682b
SM		 1059
1060 u8 min_time_between_cnps[0x20];
1061
b4ff3a36 1062 u8 reserved_at_c0[0x12];
e281682b 1063 u8 cnp_dscp[0x6];
b4ff3a36 1064 u8 reserved_at_d8[0x5];
e281682b
SM		 1065 u8 cnp_802p_prio[0x3];
1066
b4ff3a36 1067 u8 reserved_at_e0[0x720];
e281682b
SM		 1068};
1069
1070struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
b4ff3a36 1071 u8 reserved_at_0[0x60];
e281682b 1072
b4ff3a36 1073 u8 reserved_at_60[0x4];
e281682b 1074 u8 clamp_tgt_rate[0x1];
b4ff3a36 1075 u8 reserved_at_65[0x3];
e281682b 1076 u8 clamp_tgt_rate_after_time_inc[0x1];
b4ff3a36 1077 u8 reserved_at_69[0x17];
e281682b 1078
b4ff3a36 1079 u8 reserved_at_80[0x20];
e281682b
SM		 1080
1081 u8 rpg_time_reset[0x20];
1082
1083 u8 rpg_byte_reset[0x20];
1084
1085 u8 rpg_threshold[0x20];
1086
1087 u8 rpg_max_rate[0x20];
1088
1089 u8 rpg_ai_rate[0x20];
1090
1091 u8 rpg_hai_rate[0x20];
1092
1093 u8 rpg_gd[0x20];
1094
1095 u8 rpg_min_dec_fac[0x20];
1096
1097 u8 rpg_min_rate[0x20];
1098
b4ff3a36 1099 u8 reserved_at_1c0[0xe0];
e281682b
SM		 1100
1101 u8 rate_to_set_on_first_cnp[0x20];
1102
1103 u8 dce_tcp_g[0x20];
1104
1105 u8 dce_tcp_rtt[0x20];
1106
1107 u8 rate_reduce_monitor_period[0x20];
1108
b4ff3a36 1109 u8 reserved_at_320[0x20];
e281682b
SM		 1110
1111 u8 initial_alpha_value[0x20];
1112
b4ff3a36 1113 u8 reserved_at_360[0x4a0];
e281682b
SM		 1114};
1115
1116struct mlx5_ifc_cong_control_802_1qau_rp_bits {
b4ff3a36 1117 u8 reserved_at_0[0x80];
e281682b
SM		 1118
1119 u8 rppp_max_rps[0x20];
1120
1121 u8 rpg_time_reset[0x20];
1122
1123 u8 rpg_byte_reset[0x20];
1124
1125 u8 rpg_threshold[0x20];
1126
1127 u8 rpg_max_rate[0x20];
1128
1129 u8 rpg_ai_rate[0x20];
1130
1131 u8 rpg_hai_rate[0x20];
1132
1133 u8 rpg_gd[0x20];
1134
1135 u8 rpg_min_dec_fac[0x20];
1136
1137 u8 rpg_min_rate[0x20];
1138
b4ff3a36 1139 u8 reserved_at_1c0[0x640];
e281682b
SM		 1140};
1141
1142enum {
1143 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1144 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1145 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1146};
1147
1148struct mlx5_ifc_resize_field_select_bits {
1149 u8 resize_field_select[0x20];
1150};
1151
1152enum {
1153 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1154 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1155 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1156 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1157};
1158
1159struct mlx5_ifc_modify_field_select_bits {
1160 u8 modify_field_select[0x20];
1161};
1162
1163struct mlx5_ifc_field_select_r_roce_np_bits {
1164 u8 field_select_r_roce_np[0x20];
1165};
1166
1167struct mlx5_ifc_field_select_r_roce_rp_bits {
1168 u8 field_select_r_roce_rp[0x20];
1169};
1170
1171enum {
1172 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1173 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1174 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1175 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1176 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1177 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1178 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1179 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1180 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1181 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1182};
1183
1184struct mlx5_ifc_field_select_802_1qau_rp_bits {
1185 u8 field_select_8021qaurp[0x20];
1186};
1187
1188struct mlx5_ifc_phys_layer_cntrs_bits {
1189 u8 time_since_last_clear_high[0x20];
1190
1191 u8 time_since_last_clear_low[0x20];
1192
1193 u8 symbol_errors_high[0x20];
1194
1195 u8 symbol_errors_low[0x20];
1196
1197 u8 sync_headers_errors_high[0x20];
1198
1199 u8 sync_headers_errors_low[0x20];
1200
1201 u8 edpl_bip_errors_lane0_high[0x20];
1202
1203 u8 edpl_bip_errors_lane0_low[0x20];
1204
1205 u8 edpl_bip_errors_lane1_high[0x20];
1206
1207 u8 edpl_bip_errors_lane1_low[0x20];
1208
1209 u8 edpl_bip_errors_lane2_high[0x20];
1210
1211 u8 edpl_bip_errors_lane2_low[0x20];
1212
1213 u8 edpl_bip_errors_lane3_high[0x20];
1214
1215 u8 edpl_bip_errors_lane3_low[0x20];
1216
1217 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1218
1219 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1220
1221 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1222
1223 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1224
1225 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1226
1227 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1228
1229 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1230
1231 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1232
1233 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1234
1235 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1236
1237 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1238
1239 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1240
1241 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1242
1243 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1244
1245 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1246
1247 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1248
1249 u8 rs_fec_corrected_blocks_high[0x20];
1250
1251 u8 rs_fec_corrected_blocks_low[0x20];
1252
1253 u8 rs_fec_uncorrectable_blocks_high[0x20];
1254
1255 u8 rs_fec_uncorrectable_blocks_low[0x20];
1256
1257 u8 rs_fec_no_errors_blocks_high[0x20];
1258
1259 u8 rs_fec_no_errors_blocks_low[0x20];
1260
1261 u8 rs_fec_single_error_blocks_high[0x20];
1262
1263 u8 rs_fec_single_error_blocks_low[0x20];
1264
1265 u8 rs_fec_corrected_symbols_total_high[0x20];
1266
1267 u8 rs_fec_corrected_symbols_total_low[0x20];
1268
1269 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1270
1271 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1272
1273 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1274
1275 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1276
1277 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1278
1279 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1280
1281 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1282
1283 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1284
1285 u8 link_down_events[0x20];
1286
1287 u8 successful_recovery_events[0x20];
1288
b4ff3a36 1289 u8 reserved_at_640[0x180];
e281682b
SM		 1290};
1291
1c64bf6f
MY		 1292struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1293 u8 symbol_error_counter[0x10];
1294
1295 u8 link_error_recovery_counter[0x8];
1296
1297 u8 link_downed_counter[0x8];
1298
1299 u8 port_rcv_errors[0x10];
1300
1301 u8 port_rcv_remote_physical_errors[0x10];
1302
1303 u8 port_rcv_switch_relay_errors[0x10];
1304
1305 u8 port_xmit_discards[0x10];
1306
1307 u8 port_xmit_constraint_errors[0x8];
1308
1309 u8 port_rcv_constraint_errors[0x8];
1310
1311 u8 reserved_at_70[0x8];
1312
1313 u8 link_overrun_errors[0x8];
1314
1315 u8 reserved_at_80[0x10];
1316
1317 u8 vl_15_dropped[0x10];
1318
1319 u8 reserved_at_a0[0xa0];
1320};
1321
e281682b
SM		 1322struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1323 u8 transmit_queue_high[0x20];
1324
1325 u8 transmit_queue_low[0x20];
1326
b4ff3a36 1327 u8 reserved_at_40[0x780];
e281682b
SM		 1328};
1329
1330struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1331 u8 rx_octets_high[0x20];
1332
1333 u8 rx_octets_low[0x20];
1334
b4ff3a36 1335 u8 reserved_at_40[0xc0];
e281682b
SM		 1336
1337 u8 rx_frames_high[0x20];
1338
1339 u8 rx_frames_low[0x20];
1340
1341 u8 tx_octets_high[0x20];
1342
1343 u8 tx_octets_low[0x20];
1344
b4ff3a36 1345 u8 reserved_at_180[0xc0];
e281682b
SM		 1346
1347 u8 tx_frames_high[0x20];
1348
1349 u8 tx_frames_low[0x20];
1350
1351 u8 rx_pause_high[0x20];
1352
1353 u8 rx_pause_low[0x20];
1354
1355 u8 rx_pause_duration_high[0x20];
1356
1357 u8 rx_pause_duration_low[0x20];
1358
1359 u8 tx_pause_high[0x20];
1360
1361 u8 tx_pause_low[0x20];
1362
1363 u8 tx_pause_duration_high[0x20];
1364
1365 u8 tx_pause_duration_low[0x20];
1366
1367 u8 rx_pause_transition_high[0x20];
1368
1369 u8 rx_pause_transition_low[0x20];
1370
b4ff3a36 1371 u8 reserved_at_3c0[0x400];
e281682b
SM		 1372};
1373
1374struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1375 u8 port_transmit_wait_high[0x20];
1376
1377 u8 port_transmit_wait_low[0x20];
1378
b4ff3a36 1379 u8 reserved_at_40[0x780];
e281682b
SM		 1380};
1381
1382struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1383 u8 dot3stats_alignment_errors_high[0x20];
1384
1385 u8 dot3stats_alignment_errors_low[0x20];
1386
1387 u8 dot3stats_fcs_errors_high[0x20];
1388
1389 u8 dot3stats_fcs_errors_low[0x20];
1390
1391 u8 dot3stats_single_collision_frames_high[0x20];
1392
1393 u8 dot3stats_single_collision_frames_low[0x20];
1394
1395 u8 dot3stats_multiple_collision_frames_high[0x20];
1396
1397 u8 dot3stats_multiple_collision_frames_low[0x20];
1398
1399 u8 dot3stats_sqe_test_errors_high[0x20];
1400
1401 u8 dot3stats_sqe_test_errors_low[0x20];
1402
1403 u8 dot3stats_deferred_transmissions_high[0x20];
1404
1405 u8 dot3stats_deferred_transmissions_low[0x20];
1406
1407 u8 dot3stats_late_collisions_high[0x20];
1408
1409 u8 dot3stats_late_collisions_low[0x20];
1410
1411 u8 dot3stats_excessive_collisions_high[0x20];
1412
1413 u8 dot3stats_excessive_collisions_low[0x20];
1414
1415 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1416
1417 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1418
1419 u8 dot3stats_carrier_sense_errors_high[0x20];
1420
1421 u8 dot3stats_carrier_sense_errors_low[0x20];
1422
1423 u8 dot3stats_frame_too_longs_high[0x20];
1424
1425 u8 dot3stats_frame_too_longs_low[0x20];
1426
1427 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1428
1429 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1430
1431 u8 dot3stats_symbol_errors_high[0x20];
1432
1433 u8 dot3stats_symbol_errors_low[0x20];
1434
1435 u8 dot3control_in_unknown_opcodes_high[0x20];
1436
1437 u8 dot3control_in_unknown_opcodes_low[0x20];
1438
1439 u8 dot3in_pause_frames_high[0x20];
1440
1441 u8 dot3in_pause_frames_low[0x20];
1442
1443 u8 dot3out_pause_frames_high[0x20];
1444
1445 u8 dot3out_pause_frames_low[0x20];
1446
b4ff3a36 1447 u8 reserved_at_400[0x3c0];
e281682b
SM		 1448};
1449
1450struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1451 u8 ether_stats_drop_events_high[0x20];
1452
1453 u8 ether_stats_drop_events_low[0x20];
1454
1455 u8 ether_stats_octets_high[0x20];
1456
1457 u8 ether_stats_octets_low[0x20];
1458
1459 u8 ether_stats_pkts_high[0x20];
1460
1461 u8 ether_stats_pkts_low[0x20];
1462
1463 u8 ether_stats_broadcast_pkts_high[0x20];
1464
1465 u8 ether_stats_broadcast_pkts_low[0x20];
1466
1467 u8 ether_stats_multicast_pkts_high[0x20];
1468
1469 u8 ether_stats_multicast_pkts_low[0x20];
1470
1471 u8 ether_stats_crc_align_errors_high[0x20];
1472
1473 u8 ether_stats_crc_align_errors_low[0x20];
1474
1475 u8 ether_stats_undersize_pkts_high[0x20];
1476
1477 u8 ether_stats_undersize_pkts_low[0x20];
1478
1479 u8 ether_stats_oversize_pkts_high[0x20];
1480
1481 u8 ether_stats_oversize_pkts_low[0x20];
1482
1483 u8 ether_stats_fragments_high[0x20];
1484
1485 u8 ether_stats_fragments_low[0x20];
1486
1487 u8 ether_stats_jabbers_high[0x20];
1488
1489 u8 ether_stats_jabbers_low[0x20];
1490
1491 u8 ether_stats_collisions_high[0x20];
1492
1493 u8 ether_stats_collisions_low[0x20];
1494
1495 u8 ether_stats_pkts64octets_high[0x20];
1496
1497 u8 ether_stats_pkts64octets_low[0x20];
1498
1499 u8 ether_stats_pkts65to127octets_high[0x20];
1500
1501 u8 ether_stats_pkts65to127octets_low[0x20];
1502
1503 u8 ether_stats_pkts128to255octets_high[0x20];
1504
1505 u8 ether_stats_pkts128to255octets_low[0x20];
1506
1507 u8 ether_stats_pkts256to511octets_high[0x20];
1508
1509 u8 ether_stats_pkts256to511octets_low[0x20];
1510
1511 u8 ether_stats_pkts512to1023octets_high[0x20];
1512
1513 u8 ether_stats_pkts512to1023octets_low[0x20];
1514
1515 u8 ether_stats_pkts1024to1518octets_high[0x20];
1516
1517 u8 ether_stats_pkts1024to1518octets_low[0x20];
1518
1519 u8 ether_stats_pkts1519to2047octets_high[0x20];
1520
1521 u8 ether_stats_pkts1519to2047octets_low[0x20];
1522
1523 u8 ether_stats_pkts2048to4095octets_high[0x20];
1524
1525 u8 ether_stats_pkts2048to4095octets_low[0x20];
1526
1527 u8 ether_stats_pkts4096to8191octets_high[0x20];
1528
1529 u8 ether_stats_pkts4096to8191octets_low[0x20];
1530
1531 u8 ether_stats_pkts8192to10239octets_high[0x20];
1532
1533 u8 ether_stats_pkts8192to10239octets_low[0x20];
1534
b4ff3a36 1535 u8 reserved_at_540[0x280];
e281682b
SM		 1536};
1537
1538struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1539 u8 if_in_octets_high[0x20];
1540
1541 u8 if_in_octets_low[0x20];
1542
1543 u8 if_in_ucast_pkts_high[0x20];
1544
1545 u8 if_in_ucast_pkts_low[0x20];
1546
1547 u8 if_in_discards_high[0x20];
1548
1549 u8 if_in_discards_low[0x20];
1550
1551 u8 if_in_errors_high[0x20];
1552
1553 u8 if_in_errors_low[0x20];
1554
1555 u8 if_in_unknown_protos_high[0x20];
1556
1557 u8 if_in_unknown_protos_low[0x20];
1558
1559 u8 if_out_octets_high[0x20];
1560
1561 u8 if_out_octets_low[0x20];
1562
1563 u8 if_out_ucast_pkts_high[0x20];
1564
1565 u8 if_out_ucast_pkts_low[0x20];
1566
1567 u8 if_out_discards_high[0x20];
1568
1569 u8 if_out_discards_low[0x20];
1570
1571 u8 if_out_errors_high[0x20];
1572
1573 u8 if_out_errors_low[0x20];
1574
1575 u8 if_in_multicast_pkts_high[0x20];
1576
1577 u8 if_in_multicast_pkts_low[0x20];
1578
1579 u8 if_in_broadcast_pkts_high[0x20];
1580
1581 u8 if_in_broadcast_pkts_low[0x20];
1582
1583 u8 if_out_multicast_pkts_high[0x20];
1584
1585 u8 if_out_multicast_pkts_low[0x20];
1586
1587 u8 if_out_broadcast_pkts_high[0x20];
1588
1589 u8 if_out_broadcast_pkts_low[0x20];
1590
b4ff3a36 1591 u8 reserved_at_340[0x480];
e281682b
SM		 1592};
1593
1594struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1595 u8 a_frames_transmitted_ok_high[0x20];
1596
1597 u8 a_frames_transmitted_ok_low[0x20];
1598
1599 u8 a_frames_received_ok_high[0x20];
1600
1601 u8 a_frames_received_ok_low[0x20];
1602
1603 u8 a_frame_check_sequence_errors_high[0x20];
1604
1605 u8 a_frame_check_sequence_errors_low[0x20];
1606
1607 u8 a_alignment_errors_high[0x20];
1608
1609 u8 a_alignment_errors_low[0x20];
1610
1611 u8 a_octets_transmitted_ok_high[0x20];
1612
1613 u8 a_octets_transmitted_ok_low[0x20];
1614
1615 u8 a_octets_received_ok_high[0x20];
1616
1617 u8 a_octets_received_ok_low[0x20];
1618
1619 u8 a_multicast_frames_xmitted_ok_high[0x20];
1620
1621 u8 a_multicast_frames_xmitted_ok_low[0x20];
1622
1623 u8 a_broadcast_frames_xmitted_ok_high[0x20];
1624
1625 u8 a_broadcast_frames_xmitted_ok_low[0x20];
1626
1627 u8 a_multicast_frames_received_ok_high[0x20];
1628
1629 u8 a_multicast_frames_received_ok_low[0x20];
1630
1631 u8 a_broadcast_frames_received_ok_high[0x20];
1632
1633 u8 a_broadcast_frames_received_ok_low[0x20];
1634
1635 u8 a_in_range_length_errors_high[0x20];
1636
1637 u8 a_in_range_length_errors_low[0x20];
1638
1639 u8 a_out_of_range_length_field_high[0x20];
1640
1641 u8 a_out_of_range_length_field_low[0x20];
1642
1643 u8 a_frame_too_long_errors_high[0x20];
1644
1645 u8 a_frame_too_long_errors_low[0x20];
1646
1647 u8 a_symbol_error_during_carrier_high[0x20];
1648
1649 u8 a_symbol_error_during_carrier_low[0x20];
1650
1651 u8 a_mac_control_frames_transmitted_high[0x20];
1652
1653 u8 a_mac_control_frames_transmitted_low[0x20];
1654
1655 u8 a_mac_control_frames_received_high[0x20];
1656
1657 u8 a_mac_control_frames_received_low[0x20];
1658
1659 u8 a_unsupported_opcodes_received_high[0x20];
1660
1661 u8 a_unsupported_opcodes_received_low[0x20];
1662
1663 u8 a_pause_mac_ctrl_frames_received_high[0x20];
1664
1665 u8 a_pause_mac_ctrl_frames_received_low[0x20];
1666
1667 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
1668
1669 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
1670
b4ff3a36 1671 u8 reserved_at_4c0[0x300];
e281682b
SM		 1672};
1673
1674struct mlx5_ifc_cmd_inter_comp_event_bits {
1675 u8 command_completion_vector[0x20];
1676
b4ff3a36 1677 u8 reserved_at_20[0xc0];
e281682b
SM		 1678};
1679
1680struct mlx5_ifc_stall_vl_event_bits {
b4ff3a36 1681 u8 reserved_at_0[0x18];
e281682b 1682 u8 port_num[0x1];
b4ff3a36 1683 u8 reserved_at_19[0x3];
e281682b
SM		 1684 u8 vl[0x4];
1685
b4ff3a36 1686 u8 reserved_at_20[0xa0];
e281682b
SM		 1687};
1688
1689struct mlx5_ifc_db_bf_congestion_event_bits {
1690 u8 event_subtype[0x8];
b4ff3a36 1691 u8 reserved_at_8[0x8];
e281682b 1692 u8 congestion_level[0x8];
b4ff3a36 1693 u8 reserved_at_18[0x8];
e281682b 1694
b4ff3a36 1695 u8 reserved_at_20[0xa0];
e281682b
SM		 1696};
1697
1698struct mlx5_ifc_gpio_event_bits {
b4ff3a36 1699 u8 reserved_at_0[0x60];
e281682b
SM		 1700
1701 u8 gpio_event_hi[0x20];
1702
1703 u8 gpio_event_lo[0x20];
1704
b4ff3a36 1705 u8 reserved_at_a0[0x40];
e281682b
SM		 1706};
1707
1708struct mlx5_ifc_port_state_change_event_bits {
b4ff3a36 1709 u8 reserved_at_0[0x40];
e281682b
SM		 1710
1711 u8 port_num[0x4];
b4ff3a36 1712 u8 reserved_at_44[0x1c];
e281682b 1713
b4ff3a36 1714 u8 reserved_at_60[0x80];
e281682b
SM		 1715};
1716
1717struct mlx5_ifc_dropped_packet_logged_bits {
b4ff3a36 1718 u8 reserved_at_0[0xe0];
e281682b
SM		 1719};
1720
1721enum {
1722 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
1723 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
1724};
1725
1726struct mlx5_ifc_cq_error_bits {
b4ff3a36 1727 u8 reserved_at_0[0x8];
e281682b
SM		 1728 u8 cqn[0x18];
1729
b4ff3a36 1730 u8 reserved_at_20[0x20];
e281682b 1731
b4ff3a36 1732 u8 reserved_at_40[0x18];
e281682b
SM		 1733 u8 syndrome[0x8];
1734
b4ff3a36 1735 u8 reserved_at_60[0x80];
e281682b
SM		 1736};
1737
1738struct mlx5_ifc_rdma_page_fault_event_bits {
1739 u8 bytes_committed[0x20];
1740
1741 u8 r_key[0x20];
1742
b4ff3a36 1743 u8 reserved_at_40[0x10];
e281682b
SM		 1744 u8 packet_len[0x10];
1745
1746 u8 rdma_op_len[0x20];
1747
1748 u8 rdma_va[0x40];
1749
b4ff3a36 1750 u8 reserved_at_c0[0x5];
e281682b
SM		 1751 u8 rdma[0x1];
1752 u8 write[0x1];
1753 u8 requestor[0x1];
1754 u8 qp_number[0x18];
1755};
1756
1757struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1758 u8 bytes_committed[0x20];
1759
b4ff3a36 1760 u8 reserved_at_20[0x10];
e281682b
SM		 1761 u8 wqe_index[0x10];
1762
b4ff3a36 1763 u8 reserved_at_40[0x10];
e281682b
SM		 1764 u8 len[0x10];
1765
b4ff3a36 1766 u8 reserved_at_60[0x60];
e281682b 1767
b4ff3a36 1768 u8 reserved_at_c0[0x5];
e281682b
SM		 1769 u8 rdma[0x1];
1770 u8 write_read[0x1];
1771 u8 requestor[0x1];
1772 u8 qpn[0x18];
1773};
1774
1775struct mlx5_ifc_qp_events_bits {
b4ff3a36 1776 u8 reserved_at_0[0xa0];
e281682b
SM		 1777
1778 u8 type[0x8];
b4ff3a36 1779 u8 reserved_at_a8[0x18];
e281682b 1780
b4ff3a36 1781 u8 reserved_at_c0[0x8];
e281682b
SM		 1782 u8 qpn_rqn_sqn[0x18];
1783};
1784
1785struct mlx5_ifc_dct_events_bits {
b4ff3a36 1786 u8 reserved_at_0[0xc0];
e281682b 1787
b4ff3a36 1788 u8 reserved_at_c0[0x8];
e281682b
SM		 1789 u8 dct_number[0x18];
1790};
1791
1792struct mlx5_ifc_comp_event_bits {
b4ff3a36 1793 u8 reserved_at_0[0xc0];
e281682b 1794
b4ff3a36 1795 u8 reserved_at_c0[0x8];
e281682b
SM		 1796 u8 cq_number[0x18];
1797};
1798
1799enum {
1800 MLX5_QPC_STATE_RST = 0x0,
1801 MLX5_QPC_STATE_INIT = 0x1,
1802 MLX5_QPC_STATE_RTR = 0x2,
1803 MLX5_QPC_STATE_RTS = 0x3,
1804 MLX5_QPC_STATE_SQER = 0x4,
1805 MLX5_QPC_STATE_ERR = 0x6,
1806 MLX5_QPC_STATE_SQD = 0x7,
1807 MLX5_QPC_STATE_SUSPENDED = 0x9,
1808};
1809
1810enum {
1811 MLX5_QPC_ST_RC = 0x0,
1812 MLX5_QPC_ST_UC = 0x1,
1813 MLX5_QPC_ST_UD = 0x2,
1814 MLX5_QPC_ST_XRC = 0x3,
1815 MLX5_QPC_ST_DCI = 0x5,
1816 MLX5_QPC_ST_QP0 = 0x7,
1817 MLX5_QPC_ST_QP1 = 0x8,
1818 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
1819 MLX5_QPC_ST_REG_UMR = 0xc,
1820};
1821
1822enum {
1823 MLX5_QPC_PM_STATE_ARMED = 0x0,
1824 MLX5_QPC_PM_STATE_REARM = 0x1,
1825 MLX5_QPC_PM_STATE_RESERVED = 0x2,
1826 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
1827};
1828
1829enum {
1830 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
1831 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
1832};
1833
1834enum {
1835 MLX5_QPC_MTU_256_BYTES = 0x1,
1836 MLX5_QPC_MTU_512_BYTES = 0x2,
1837 MLX5_QPC_MTU_1K_BYTES = 0x3,
1838 MLX5_QPC_MTU_2K_BYTES = 0x4,
1839 MLX5_QPC_MTU_4K_BYTES = 0x5,
1840 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
1841};
1842
1843enum {
1844 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
1845 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
1846 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
1847 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
1848 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
1849 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
1850 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
1851 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
1852};
1853
1854enum {
1855 MLX5_QPC_CS_REQ_DISABLE = 0x0,
1856 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
1857 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
1858};
1859
1860enum {
1861 MLX5_QPC_CS_RES_DISABLE = 0x0,
1862 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
1863 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
1864};
1865
1866struct mlx5_ifc_qpc_bits {
1867 u8 state[0x4];
b4ff3a36 1868 u8 reserved_at_4[0x4];
e281682b 1869 u8 st[0x8];
b4ff3a36 1870 u8 reserved_at_10[0x3];
e281682b 1871 u8 pm_state[0x2];
b4ff3a36 1872 u8 reserved_at_15[0x7];
e281682b 1873 u8 end_padding_mode[0x2];
b4ff3a36 1874 u8 reserved_at_1e[0x2];
e281682b
SM		 1875
1876 u8 wq_signature[0x1];
1877 u8 block_lb_mc[0x1];
1878 u8 atomic_like_write_en[0x1];
1879 u8 latency_sensitive[0x1];
b4ff3a36 1880 u8 reserved_at_24[0x1];
e281682b 1881 u8 drain_sigerr[0x1];
b4ff3a36 1882 u8 reserved_at_26[0x2];
e281682b
SM		 1883 u8 pd[0x18];
1884
1885 u8 mtu[0x3];
1886 u8 log_msg_max[0x5];
b4ff3a36 1887 u8 reserved_at_48[0x1];
e281682b
SM		 1888 u8 log_rq_size[0x4];
1889 u8 log_rq_stride[0x3];
1890 u8 no_sq[0x1];
1891 u8 log_sq_size[0x4];
b4ff3a36 1892 u8 reserved_at_55[0x6];
e281682b 1893 u8 rlky[0x1];
1015c2e8 1894 u8 ulp_stateless_offload_mode[0x4];
e281682b
SM		 1895
1896 u8 counter_set_id[0x8];
1897 u8 uar_page[0x18];
1898
b4ff3a36 1899 u8 reserved_at_80[0x8];
e281682b
SM		 1900 u8 user_index[0x18];
1901
b4ff3a36 1902 u8 reserved_at_a0[0x3];
e281682b
SM		 1903 u8 log_page_size[0x5];
1904 u8 remote_qpn[0x18];
1905
1906 struct mlx5_ifc_ads_bits primary_address_path;
1907
1908 struct mlx5_ifc_ads_bits secondary_address_path;
1909
1910 u8 log_ack_req_freq[0x4];
b4ff3a36 1911 u8 reserved_at_384[0x4];
e281682b 1912 u8 log_sra_max[0x3];
b4ff3a36 1913 u8 reserved_at_38b[0x2];
e281682b
SM		 1914 u8 retry_count[0x3];
1915 u8 rnr_retry[0x3];
b4ff3a36 1916 u8 reserved_at_393[0x1];
e281682b
SM		 1917 u8 fre[0x1];
1918 u8 cur_rnr_retry[0x3];
1919 u8 cur_retry_count[0x3];
b4ff3a36 1920 u8 reserved_at_39b[0x5];
e281682b 1921
b4ff3a36 1922 u8 reserved_at_3a0[0x20];
e281682b 1923
b4ff3a36 1924 u8 reserved_at_3c0[0x8];
e281682b
SM		 1925 u8 next_send_psn[0x18];
1926
b4ff3a36 1927 u8 reserved_at_3e0[0x8];
e281682b
SM		 1928 u8 cqn_snd[0x18];
1929
b4ff3a36 1930 u8 reserved_at_400[0x40];
e281682b 1931
b4ff3a36 1932 u8 reserved_at_440[0x8];
e281682b
SM		 1933 u8 last_acked_psn[0x18];
1934
b4ff3a36 1935 u8 reserved_at_460[0x8];
e281682b
SM		 1936 u8 ssn[0x18];
1937
b4ff3a36 1938 u8 reserved_at_480[0x8];
e281682b 1939 u8 log_rra_max[0x3];
b4ff3a36 1940 u8 reserved_at_48b[0x1];
e281682b
SM		 1941 u8 atomic_mode[0x4];
1942 u8 rre[0x1];
1943 u8 rwe[0x1];
1944 u8 rae[0x1];
b4ff3a36 1945 u8 reserved_at_493[0x1];
e281682b 1946 u8 page_offset[0x6];
b4ff3a36 1947 u8 reserved_at_49a[0x3];
e281682b
SM		 1948 u8 cd_slave_receive[0x1];
1949 u8 cd_slave_send[0x1];
1950 u8 cd_master[0x1];
1951
b4ff3a36 1952 u8 reserved_at_4a0[0x3];
e281682b
SM		 1953 u8 min_rnr_nak[0x5];
1954 u8 next_rcv_psn[0x18];
1955
b4ff3a36 1956 u8 reserved_at_4c0[0x8];
e281682b
SM		 1957 u8 xrcd[0x18];
1958
b4ff3a36 1959 u8 reserved_at_4e0[0x8];
e281682b
SM		 1960 u8 cqn_rcv[0x18];
1961
1962 u8 dbr_addr[0x40];
1963
1964 u8 q_key[0x20];
1965
b4ff3a36 1966 u8 reserved_at_560[0x5];
e281682b
SM		 1967 u8 rq_type[0x3];
1968 u8 srqn_rmpn[0x18];
1969
b4ff3a36 1970 u8 reserved_at_580[0x8];
e281682b
SM		 1971 u8 rmsn[0x18];
1972
1973 u8 hw_sq_wqebb_counter[0x10];
1974 u8 sw_sq_wqebb_counter[0x10];
1975
1976 u8 hw_rq_counter[0x20];
1977
1978 u8 sw_rq_counter[0x20];
1979
b4ff3a36 1980 u8 reserved_at_600[0x20];
e281682b 1981
b4ff3a36 1982 u8 reserved_at_620[0xf];
e281682b
SM		 1983 u8 cgs[0x1];
1984 u8 cs_req[0x8];
1985 u8 cs_res[0x8];
1986
1987 u8 dc_access_key[0x40];
1988
b4ff3a36 1989 u8 reserved_at_680[0xc0];
e281682b
SM		 1990};
1991
1992struct mlx5_ifc_roce_addr_layout_bits {
1993 u8 source_l3_address[16][0x8];
1994
b4ff3a36 1995 u8 reserved_at_80[0x3];
e281682b
SM		 1996 u8 vlan_valid[0x1];
1997 u8 vlan_id[0xc];
1998 u8 source_mac_47_32[0x10];
1999
2000 u8 source_mac_31_0[0x20];
2001
b4ff3a36 2002 u8 reserved_at_c0[0x14];
e281682b
SM		 2003 u8 roce_l3_type[0x4];
2004 u8 roce_version[0x8];
2005
b4ff3a36 2006 u8 reserved_at_e0[0x20];
e281682b
SM		 2007};
2008
2009union mlx5_ifc_hca_cap_union_bits {
2010 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2011 struct mlx5_ifc_odp_cap_bits odp_cap;
2012 struct mlx5_ifc_atomic_caps_bits atomic_caps;
2013 struct mlx5_ifc_roce_cap_bits roce_cap;
2014 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2015 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
495716b1 2016 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
d6666753 2017 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
3f0393a5 2018 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
b4ff3a36 2019 u8 reserved_at_0[0x8000];
e281682b
SM		 2020};
2021
2022enum {
2023 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
2024 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
2025 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
9dc0b289 2026 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
e281682b
SM		 2027};
2028
2029struct mlx5_ifc_flow_context_bits {
b4ff3a36 2030 u8 reserved_at_0[0x20];
e281682b
SM		 2031
2032 u8 group_id[0x20];
2033
b4ff3a36 2034 u8 reserved_at_40[0x8];
e281682b
SM		 2035 u8 flow_tag[0x18];
2036
b4ff3a36 2037 u8 reserved_at_60[0x10];
e281682b
SM		 2038 u8 action[0x10];
2039
b4ff3a36 2040 u8 reserved_at_80[0x8];
e281682b
SM		 2041 u8 destination_list_size[0x18];
2042
9dc0b289
AV		 2043 u8 reserved_at_a0[0x8];
2044 u8 flow_counter_list_size[0x18];
2045
2046 u8 reserved_at_c0[0x140];
e281682b
SM		 2047
2048 struct mlx5_ifc_fte_match_param_bits match_value;
2049
b4ff3a36 2050 u8 reserved_at_1200[0x600];
e281682b 2051
9dc0b289 2052 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
e281682b
SM		 2053};
2054
2055enum {
2056 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
2057 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
2058};
2059
2060struct mlx5_ifc_xrc_srqc_bits {
2061 u8 state[0x4];
2062 u8 log_xrc_srq_size[0x4];
b4ff3a36 2063 u8 reserved_at_8[0x18];
e281682b
SM		 2064
2065 u8 wq_signature[0x1];
2066 u8 cont_srq[0x1];
b4ff3a36 2067 u8 reserved_at_22[0x1];
e281682b
SM		 2068 u8 rlky[0x1];
2069 u8 basic_cyclic_rcv_wqe[0x1];
2070 u8 log_rq_stride[0x3];
2071 u8 xrcd[0x18];
2072
2073 u8 page_offset[0x6];
b4ff3a36 2074 u8 reserved_at_46[0x2];
e281682b
SM		 2075 u8 cqn[0x18];
2076
b4ff3a36 2077 u8 reserved_at_60[0x20];
e281682b
SM		 2078
2079 u8 user_index_equal_xrc_srqn[0x1];
b4ff3a36 2080 u8 reserved_at_81[0x1];
e281682b
SM		 2081 u8 log_page_size[0x6];
2082 u8 user_index[0x18];
2083
b4ff3a36 2084 u8 reserved_at_a0[0x20];
e281682b 2085
b4ff3a36 2086 u8 reserved_at_c0[0x8];
e281682b
SM		 2087 u8 pd[0x18];
2088
2089 u8 lwm[0x10];
2090 u8 wqe_cnt[0x10];
2091
b4ff3a36 2092 u8 reserved_at_100[0x40];
e281682b
SM		 2093
2094 u8 db_record_addr_h[0x20];
2095
2096 u8 db_record_addr_l[0x1e];
b4ff3a36 2097 u8 reserved_at_17e[0x2];
e281682b 2098
b4ff3a36 2099 u8 reserved_at_180[0x80];
e281682b
SM		 2100};
2101
2102struct mlx5_ifc_traffic_counter_bits {
2103 u8 packets[0x40];
2104
2105 u8 octets[0x40];
2106};
2107
2108struct mlx5_ifc_tisc_bits {
b4ff3a36 2109 u8 reserved_at_0[0xc];
e281682b 2110 u8 prio[0x4];
b4ff3a36 2111 u8 reserved_at_10[0x10];
e281682b 2112
b4ff3a36 2113 u8 reserved_at_20[0x100];
e281682b 2114
b4ff3a36 2115 u8 reserved_at_120[0x8];
e281682b
SM		 2116 u8 transport_domain[0x18];
2117
b4ff3a36 2118 u8 reserved_at_140[0x3c0];
e281682b
SM		 2119};
2120
2121enum {
2122 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2123 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2124};
2125
2126enum {
2127 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2128 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2129};
2130
2131enum {
2be6967c
SM		 2132 MLX5_RX_HASH_FN_NONE = 0x0,
2133 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
2134 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
e281682b
SM		 2135};
2136
2137enum {
2138 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1,
2139 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2,
2140};
2141
2142struct mlx5_ifc_tirc_bits {
b4ff3a36 2143 u8 reserved_at_0[0x20];
e281682b
SM		 2144
2145 u8 disp_type[0x4];
b4ff3a36 2146 u8 reserved_at_24[0x1c];
e281682b 2147
b4ff3a36 2148 u8 reserved_at_40[0x40];
e281682b 2149
b4ff3a36 2150 u8 reserved_at_80[0x4];
e281682b
SM		 2151 u8 lro_timeout_period_usecs[0x10];
2152 u8 lro_enable_mask[0x4];
2153 u8 lro_max_ip_payload_size[0x8];
2154
b4ff3a36 2155 u8 reserved_at_a0[0x40];
e281682b 2156
b4ff3a36 2157 u8 reserved_at_e0[0x8];
e281682b
SM		 2158 u8 inline_rqn[0x18];
2159
2160 u8 rx_hash_symmetric[0x1];
b4ff3a36 2161 u8 reserved_at_101[0x1];
e281682b 2162 u8 tunneled_offload_en[0x1];
b4ff3a36 2163 u8 reserved_at_103[0x5];
e281682b
SM		 2164 u8 indirect_table[0x18];
2165
2166 u8 rx_hash_fn[0x4];
b4ff3a36 2167 u8 reserved_at_124[0x2];
e281682b
SM		 2168 u8 self_lb_block[0x2];
2169 u8 transport_domain[0x18];
2170
2171 u8 rx_hash_toeplitz_key[10][0x20];
2172
2173 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2174
2175 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2176
b4ff3a36 2177 u8 reserved_at_2c0[0x4c0];
e281682b
SM		 2178};
2179
2180enum {
2181 MLX5_SRQC_STATE_GOOD = 0x0,
2182 MLX5_SRQC_STATE_ERROR = 0x1,
2183};
2184
2185struct mlx5_ifc_srqc_bits {
2186 u8 state[0x4];
2187 u8 log_srq_size[0x4];
b4ff3a36 2188 u8 reserved_at_8[0x18];
e281682b
SM		 2189
2190 u8 wq_signature[0x1];
2191 u8 cont_srq[0x1];
b4ff3a36 2192 u8 reserved_at_22[0x1];
e281682b 2193 u8 rlky[0x1];
b4ff3a36 2194 u8 reserved_at_24[0x1];
e281682b
SM		 2195 u8 log_rq_stride[0x3];
2196 u8 xrcd[0x18];
2197
2198 u8 page_offset[0x6];
b4ff3a36 2199 u8 reserved_at_46[0x2];
e281682b
SM		 2200 u8 cqn[0x18];
2201
b4ff3a36 2202 u8 reserved_at_60[0x20];
e281682b 2203
b4ff3a36 2204 u8 reserved_at_80[0x2];
e281682b 2205 u8 log_page_size[0x6];
b4ff3a36 2206 u8 reserved_at_88[0x18];
e281682b 2207
b4ff3a36 2208 u8 reserved_at_a0[0x20];
e281682b 2209
b4ff3a36 2210 u8 reserved_at_c0[0x8];
e281682b
SM		 2211 u8 pd[0x18];
2212
2213 u8 lwm[0x10];
2214 u8 wqe_cnt[0x10];
2215
b4ff3a36 2216 u8 reserved_at_100[0x40];
e281682b 2217
01949d01 2218 u8 dbr_addr[0x40];
e281682b 2219
b4ff3a36 2220 u8 reserved_at_180[0x80];
e281682b
SM		 2221};
2222
2223enum {
2224 MLX5_SQC_STATE_RST = 0x0,
2225 MLX5_SQC_STATE_RDY = 0x1,
2226 MLX5_SQC_STATE_ERR = 0x3,
2227};
2228
2229struct mlx5_ifc_sqc_bits {
2230 u8 rlky[0x1];
2231 u8 cd_master[0x1];
2232 u8 fre[0x1];
2233 u8 flush_in_error_en[0x1];
b4ff3a36 2234 u8 reserved_at_4[0x4];
e281682b 2235 u8 state[0x4];
7d5e1423
SM		 2236 u8 reg_umr[0x1];
2237 u8 reserved_at_d[0x13];
e281682b 2238
b4ff3a36 2239 u8 reserved_at_20[0x8];
e281682b
SM		 2240 u8 user_index[0x18];
2241
b4ff3a36 2242 u8 reserved_at_40[0x8];
e281682b
SM		 2243 u8 cqn[0x18];
2244
b4ff3a36 2245 u8 reserved_at_60[0xa0];
e281682b
SM		 2246
2247 u8 tis_lst_sz[0x10];
b4ff3a36 2248 u8 reserved_at_110[0x10];
e281682b 2249
b4ff3a36 2250 u8 reserved_at_120[0x40];
e281682b 2251
b4ff3a36 2252 u8 reserved_at_160[0x8];
e281682b
SM		 2253 u8 tis_num_0[0x18];
2254
2255 struct mlx5_ifc_wq_bits wq;
2256};
2257
2258struct mlx5_ifc_rqtc_bits {
b4ff3a36 2259 u8 reserved_at_0[0xa0];
e281682b 2260
b4ff3a36 2261 u8 reserved_at_a0[0x10];
e281682b
SM		 2262 u8 rqt_max_size[0x10];
2263
b4ff3a36 2264 u8 reserved_at_c0[0x10];
e281682b
SM		 2265 u8 rqt_actual_size[0x10];
2266
b4ff3a36 2267 u8 reserved_at_e0[0x6a0];
e281682b
SM		 2268
2269 struct mlx5_ifc_rq_num_bits rq_num[0];
2270};
2271
2272enum {
2273 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2274 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2275};
2276
2277enum {
2278 MLX5_RQC_STATE_RST = 0x0,
2279 MLX5_RQC_STATE_RDY = 0x1,
2280 MLX5_RQC_STATE_ERR = 0x3,
2281};
2282
2283struct mlx5_ifc_rqc_bits {
2284 u8 rlky[0x1];
7d5e1423
SM		 2285 u8 reserved_at_1[0x1];
2286 u8 scatter_fcs[0x1];
e281682b
SM		 2287 u8 vsd[0x1];
2288 u8 mem_rq_type[0x4];
2289 u8 state[0x4];
b4ff3a36 2290 u8 reserved_at_c[0x1];
e281682b 2291 u8 flush_in_error_en[0x1];
b4ff3a36 2292 u8 reserved_at_e[0x12];
e281682b 2293
b4ff3a36 2294 u8 reserved_at_20[0x8];
e281682b
SM		 2295 u8 user_index[0x18];
2296
b4ff3a36 2297 u8 reserved_at_40[0x8];
e281682b
SM		 2298 u8 cqn[0x18];
2299
2300 u8 counter_set_id[0x8];
b4ff3a36 2301 u8 reserved_at_68[0x18];
e281682b 2302
b4ff3a36 2303 u8 reserved_at_80[0x8];
e281682b
SM		 2304 u8 rmpn[0x18];
2305
b4ff3a36 2306 u8 reserved_at_a0[0xe0];
e281682b
SM		 2307
2308 struct mlx5_ifc_wq_bits wq;
2309};
2310
2311enum {
2312 MLX5_RMPC_STATE_RDY = 0x1,
2313 MLX5_RMPC_STATE_ERR = 0x3,
2314};
2315
2316struct mlx5_ifc_rmpc_bits {
b4ff3a36 2317 u8 reserved_at_0[0x8];
e281682b 2318 u8 state[0x4];
b4ff3a36 2319 u8 reserved_at_c[0x14];
e281682b
SM		 2320
2321 u8 basic_cyclic_rcv_wqe[0x1];
b4ff3a36 2322 u8 reserved_at_21[0x1f];
e281682b 2323
b4ff3a36 2324 u8 reserved_at_40[0x140];
e281682b
SM		 2325
2326 struct mlx5_ifc_wq_bits wq;
2327};
2328
e281682b 2329struct mlx5_ifc_nic_vport_context_bits {
b4ff3a36 2330 u8 reserved_at_0[0x1f];
e281682b
SM		 2331 u8 roce_en[0x1];
2332
d82b7318 2333 u8 arm_change_event[0x1];
b4ff3a36 2334 u8 reserved_at_21[0x1a];
d82b7318
SM		 2335 u8 event_on_mtu[0x1];
2336 u8 event_on_promisc_change[0x1];
2337 u8 event_on_vlan_change[0x1];
2338 u8 event_on_mc_address_change[0x1];
2339 u8 event_on_uc_address_change[0x1];
e281682b 2340
b4ff3a36 2341 u8 reserved_at_40[0xf0];
d82b7318
SM		 2342
2343 u8 mtu[0x10];
2344
9efa7525
AS		 2345 u8 system_image_guid[0x40];
2346 u8 port_guid[0x40];
2347 u8 node_guid[0x40];
2348
b4ff3a36 2349 u8 reserved_at_200[0x140];
9efa7525 2350 u8 qkey_violation_counter[0x10];
b4ff3a36 2351 u8 reserved_at_350[0x430];
d82b7318
SM		 2352
2353 u8 promisc_uc[0x1];
2354 u8 promisc_mc[0x1];
2355 u8 promisc_all[0x1];
b4ff3a36 2356 u8 reserved_at_783[0x2];
e281682b 2357 u8 allowed_list_type[0x3];
b4ff3a36 2358 u8 reserved_at_788[0xc];
e281682b
SM		 2359 u8 allowed_list_size[0xc];
2360
2361 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2362
b4ff3a36 2363 u8 reserved_at_7e0[0x20];
e281682b
SM		 2364
2365 u8 current_uc_mac_address[0][0x40];
2366};
2367
2368enum {
2369 MLX5_MKC_ACCESS_MODE_PA = 0x0,
2370 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
2371 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
2372};
2373
2374struct mlx5_ifc_mkc_bits {
b4ff3a36 2375 u8 reserved_at_0[0x1];
e281682b 2376 u8 free[0x1];
b4ff3a36 2377 u8 reserved_at_2[0xd];
e281682b
SM		 2378 u8 small_fence_on_rdma_read_response[0x1];
2379 u8 umr_en[0x1];
2380 u8 a[0x1];
2381 u8 rw[0x1];
2382 u8 rr[0x1];
2383 u8 lw[0x1];
2384 u8 lr[0x1];
2385 u8 access_mode[0x2];
b4ff3a36 2386 u8 reserved_at_18[0x8];
e281682b
SM		 2387
2388 u8 qpn[0x18];
2389 u8 mkey_7_0[0x8];
2390
b4ff3a36 2391 u8 reserved_at_40[0x20];
e281682b
SM		 2392
2393 u8 length64[0x1];
2394 u8 bsf_en[0x1];
2395 u8 sync_umr[0x1];
b4ff3a36 2396 u8 reserved_at_63[0x2];
e281682b 2397 u8 expected_sigerr_count[0x1];
b4ff3a36 2398 u8 reserved_at_66[0x1];
e281682b
SM		 2399 u8 en_rinval[0x1];
2400 u8 pd[0x18];
2401
2402 u8 start_addr[0x40];
2403
2404 u8 len[0x40];
2405
2406 u8 bsf_octword_size[0x20];
2407
b4ff3a36 2408 u8 reserved_at_120[0x80];
e281682b
SM		 2409
2410 u8 translations_octword_size[0x20];
2411
b4ff3a36 2412 u8 reserved_at_1c0[0x1b];
e281682b
SM		 2413 u8 log_page_size[0x5];
2414
b4ff3a36 2415 u8 reserved_at_1e0[0x20];
e281682b
SM		 2416};
2417
2418struct mlx5_ifc_pkey_bits {
b4ff3a36 2419 u8 reserved_at_0[0x10];
e281682b
SM		 2420 u8 pkey[0x10];
2421};
2422
2423struct mlx5_ifc_array128_auto_bits {
2424 u8 array128_auto[16][0x8];
2425};
2426
2427struct mlx5_ifc_hca_vport_context_bits {
2428 u8 field_select[0x20];
2429
b4ff3a36 2430 u8 reserved_at_20[0xe0];
e281682b
SM		 2431
2432 u8 sm_virt_aware[0x1];
2433 u8 has_smi[0x1];
2434 u8 has_raw[0x1];
2435 u8 grh_required[0x1];
b4ff3a36 2436 u8 reserved_at_104[0xc];
707c4602
MD		 2437 u8 port_physical_state[0x4];
2438 u8 vport_state_policy[0x4];
2439 u8 port_state[0x4];
e281682b
SM		 2440 u8 vport_state[0x4];
2441
b4ff3a36 2442 u8 reserved_at_120[0x20];
707c4602
MD		 2443
2444 u8 system_image_guid[0x40];
e281682b
SM		 2445
2446 u8 port_guid[0x40];
2447
2448 u8 node_guid[0x40];
2449
2450 u8 cap_mask1[0x20];
2451
2452 u8 cap_mask1_field_select[0x20];
2453
2454 u8 cap_mask2[0x20];
2455
2456 u8 cap_mask2_field_select[0x20];
2457
b4ff3a36 2458 u8 reserved_at_280[0x80];
e281682b
SM		 2459
2460 u8 lid[0x10];
b4ff3a36 2461 u8 reserved_at_310[0x4];
e281682b
SM		 2462 u8 init_type_reply[0x4];
2463 u8 lmc[0x3];
2464 u8 subnet_timeout[0x5];
2465
2466 u8 sm_lid[0x10];
2467 u8 sm_sl[0x4];
b4ff3a36 2468 u8 reserved_at_334[0xc];
e281682b
SM		 2469
2470 u8 qkey_violation_counter[0x10];
2471 u8 pkey_violation_counter[0x10];
2472
b4ff3a36 2473 u8 reserved_at_360[0xca0];
e281682b
SM		 2474};
2475
d6666753 2476struct mlx5_ifc_esw_vport_context_bits {
b4ff3a36 2477 u8 reserved_at_0[0x3];
d6666753
SM		 2478 u8 vport_svlan_strip[0x1];
2479 u8 vport_cvlan_strip[0x1];
2480 u8 vport_svlan_insert[0x1];
2481 u8 vport_cvlan_insert[0x2];
b4ff3a36 2482 u8 reserved_at_8[0x18];
d6666753 2483
b4ff3a36 2484 u8 reserved_at_20[0x20];
d6666753
SM		 2485
2486 u8 svlan_cfi[0x1];
2487 u8 svlan_pcp[0x3];
2488 u8 svlan_id[0xc];
2489 u8 cvlan_cfi[0x1];
2490 u8 cvlan_pcp[0x3];
2491 u8 cvlan_id[0xc];
2492
b4ff3a36 2493 u8 reserved_at_60[0x7a0];
d6666753
SM		 2494};
2495
e281682b
SM		 2496enum {
2497 MLX5_EQC_STATUS_OK = 0x0,
2498 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
2499};
2500
2501enum {
2502 MLX5_EQC_ST_ARMED = 0x9,
2503 MLX5_EQC_ST_FIRED = 0xa,
2504};
2505
2506struct mlx5_ifc_eqc_bits {
2507 u8 status[0x4];
b4ff3a36 2508 u8 reserved_at_4[0x9];
e281682b
SM		 2509 u8 ec[0x1];
2510 u8 oi[0x1];
b4ff3a36 2511 u8 reserved_at_f[0x5];
e281682b 2512 u8 st[0x4];
b4ff3a36 2513 u8 reserved_at_18[0x8];
e281682b 2514
b4ff3a36 2515 u8 reserved_at_20[0x20];
e281682b 2516
b4ff3a36 2517 u8 reserved_at_40[0x14];
e281682b 2518 u8 page_offset[0x6];
b4ff3a36 2519 u8 reserved_at_5a[0x6];
e281682b 2520
b4ff3a36 2521 u8 reserved_at_60[0x3];
e281682b
SM		 2522 u8 log_eq_size[0x5];
2523 u8 uar_page[0x18];
2524
b4ff3a36 2525 u8 reserved_at_80[0x20];
e281682b 2526
b4ff3a36 2527 u8 reserved_at_a0[0x18];
e281682b
SM		 2528 u8 intr[0x8];
2529
b4ff3a36 2530 u8 reserved_at_c0[0x3];
e281682b 2531 u8 log_page_size[0x5];
b4ff3a36 2532 u8 reserved_at_c8[0x18];
e281682b 2533
b4ff3a36 2534 u8 reserved_at_e0[0x60];
e281682b 2535
b4ff3a36 2536 u8 reserved_at_140[0x8];
e281682b
SM		 2537 u8 consumer_counter[0x18];
2538
b4ff3a36 2539 u8 reserved_at_160[0x8];
e281682b
SM		 2540 u8 producer_counter[0x18];
2541
b4ff3a36 2542 u8 reserved_at_180[0x80];
e281682b
SM		 2543};
2544
2545enum {
2546 MLX5_DCTC_STATE_ACTIVE = 0x0,
2547 MLX5_DCTC_STATE_DRAINING = 0x1,
2548 MLX5_DCTC_STATE_DRAINED = 0x2,
2549};
2550
2551enum {
2552 MLX5_DCTC_CS_RES_DISABLE = 0x0,
2553 MLX5_DCTC_CS_RES_NA = 0x1,
2554 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
2555};
2556
2557enum {
2558 MLX5_DCTC_MTU_256_BYTES = 0x1,
2559 MLX5_DCTC_MTU_512_BYTES = 0x2,
2560 MLX5_DCTC_MTU_1K_BYTES = 0x3,
2561 MLX5_DCTC_MTU_2K_BYTES = 0x4,
2562 MLX5_DCTC_MTU_4K_BYTES = 0x5,
2563};
2564
2565struct mlx5_ifc_dctc_bits {
b4ff3a36 2566 u8 reserved_at_0[0x4];
e281682b 2567 u8 state[0x4];
b4ff3a36 2568 u8 reserved_at_8[0x18];
e281682b 2569
b4ff3a36 2570 u8 reserved_at_20[0x8];
e281682b
SM		 2571 u8 user_index[0x18];
2572
b4ff3a36 2573 u8 reserved_at_40[0x8];
e281682b
SM		 2574 u8 cqn[0x18];
2575
2576 u8 counter_set_id[0x8];
2577 u8 atomic_mode[0x4];
2578 u8 rre[0x1];
2579 u8 rwe[0x1];
2580 u8 rae[0x1];
2581 u8 atomic_like_write_en[0x1];
2582 u8 latency_sensitive[0x1];
2583 u8 rlky[0x1];
2584 u8 free_ar[0x1];
b4ff3a36 2585 u8 reserved_at_73[0xd];
e281682b 2586
b4ff3a36 2587 u8 reserved_at_80[0x8];
e281682b 2588 u8 cs_res[0x8];
b4ff3a36 2589 u8 reserved_at_90[0x3];
e281682b 2590 u8 min_rnr_nak[0x5];
b4ff3a36 2591 u8 reserved_at_98[0x8];
e281682b 2592
b4ff3a36 2593 u8 reserved_at_a0[0x8];
e281682b
SM		 2594 u8 srqn[0x18];
2595
b4ff3a36 2596 u8 reserved_at_c0[0x8];
e281682b
SM		 2597 u8 pd[0x18];
2598
2599 u8 tclass[0x8];
b4ff3a36 2600 u8 reserved_at_e8[0x4];
e281682b
SM		 2601 u8 flow_label[0x14];
2602
2603 u8 dc_access_key[0x40];
2604
b4ff3a36 2605 u8 reserved_at_140[0x5];
e281682b
SM		 2606 u8 mtu[0x3];
2607 u8 port[0x8];
2608 u8 pkey_index[0x10];
2609
b4ff3a36 2610 u8 reserved_at_160[0x8];
e281682b 2611 u8 my_addr_index[0x8];
b4ff3a36 2612 u8 reserved_at_170[0x8];
e281682b
SM		 2613 u8 hop_limit[0x8];
2614
2615 u8 dc_access_key_violation_count[0x20];
2616
b4ff3a36 2617 u8 reserved_at_1a0[0x14];
e281682b
SM		 2618 u8 dei_cfi[0x1];
2619 u8 eth_prio[0x3];
2620 u8 ecn[0x2];
2621 u8 dscp[0x6];
2622
b4ff3a36 2623 u8 reserved_at_1c0[0x40];
e281682b
SM		 2624};
2625
2626enum {
2627 MLX5_CQC_STATUS_OK = 0x0,
2628 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
2629 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
2630};
2631
2632enum {
2633 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
2634 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
2635};
2636
2637enum {
2638 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
2639 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
2640 MLX5_CQC_ST_FIRED = 0xa,
2641};
2642
7d5e1423
SM		 2643enum {
2644 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
2645 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
2646};
2647
e281682b
SM		 2648struct mlx5_ifc_cqc_bits {
2649 u8 status[0x4];
b4ff3a36 2650 u8 reserved_at_4[0x4];
e281682b
SM		 2651 u8 cqe_sz[0x3];
2652 u8 cc[0x1];
b4ff3a36 2653 u8 reserved_at_c[0x1];
e281682b
SM		 2654 u8 scqe_break_moderation_en[0x1];
2655 u8 oi[0x1];
7d5e1423
SM		 2656 u8 cq_period_mode[0x2];
2657 u8 cqe_comp_en[0x1];
e281682b
SM		 2658 u8 mini_cqe_res_format[0x2];
2659 u8 st[0x4];
b4ff3a36 2660 u8 reserved_at_18[0x8];
e281682b 2661
b4ff3a36 2662 u8 reserved_at_20[0x20];
e281682b 2663
b4ff3a36 2664 u8 reserved_at_40[0x14];
e281682b 2665 u8 page_offset[0x6];
b4ff3a36 2666 u8 reserved_at_5a[0x6];
e281682b 2667
b4ff3a36 2668 u8 reserved_at_60[0x3];
e281682b
SM		 2669 u8 log_cq_size[0x5];
2670 u8 uar_page[0x18];
2671
b4ff3a36 2672 u8 reserved_at_80[0x4];
e281682b
SM		 2673 u8 cq_period[0xc];
2674 u8 cq_max_count[0x10];
2675
b4ff3a36 2676 u8 reserved_at_a0[0x18];
e281682b
SM		 2677 u8 c_eqn[0x8];
2678
b4ff3a36 2679 u8 reserved_at_c0[0x3];
e281682b 2680 u8 log_page_size[0x5];
b4ff3a36 2681 u8 reserved_at_c8[0x18];
e281682b 2682
b4ff3a36 2683 u8 reserved_at_e0[0x20];
e281682b 2684
b4ff3a36 2685 u8 reserved_at_100[0x8];
e281682b
SM		 2686 u8 last_notified_index[0x18];
2687
b4ff3a36 2688 u8 reserved_at_120[0x8];
e281682b
SM		 2689 u8 last_solicit_index[0x18];
2690
b4ff3a36 2691 u8 reserved_at_140[0x8];
e281682b
SM		 2692 u8 consumer_counter[0x18];
2693
b4ff3a36 2694 u8 reserved_at_160[0x8];
e281682b
SM		 2695 u8 producer_counter[0x18];
2696
b4ff3a36 2697 u8 reserved_at_180[0x40];
e281682b
SM		 2698
2699 u8 dbr_addr[0x40];
2700};
2701
2702union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2703 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2704 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2705 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
b4ff3a36 2706 u8 reserved_at_0[0x800];
e281682b
SM		 2707};
2708
2709struct mlx5_ifc_query_adapter_param_block_bits {
b4ff3a36 2710 u8 reserved_at_0[0xc0];
e281682b 2711
b4ff3a36 2712 u8 reserved_at_c0[0x8];
211e6c80
MD		 2713 u8 ieee_vendor_id[0x18];
2714
b4ff3a36 2715 u8 reserved_at_e0[0x10];
e281682b
SM		 2716 u8 vsd_vendor_id[0x10];
2717
2718 u8 vsd[208][0x8];
2719
2720 u8 vsd_contd_psid[16][0x8];
2721};
2722
2723union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2724 struct mlx5_ifc_modify_field_select_bits modify_field_select;
2725 struct mlx5_ifc_resize_field_select_bits resize_field_select;
b4ff3a36 2726 u8 reserved_at_0[0x20];
e281682b
SM		 2727};
2728
2729union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2730 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2731 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2732 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
b4ff3a36 2733 u8 reserved_at_0[0x20];
e281682b
SM		 2734};
2735
2736union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
2737 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
2738 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
2739 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
2740 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
2741 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
2742 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
2743 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
1c64bf6f 2744 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b 2745 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
b4ff3a36 2746 u8 reserved_at_0[0x7c0];
e281682b
SM		 2747};
2748
2749union mlx5_ifc_event_auto_bits {
2750 struct mlx5_ifc_comp_event_bits comp_event;
2751 struct mlx5_ifc_dct_events_bits dct_events;
2752 struct mlx5_ifc_qp_events_bits qp_events;
2753 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
2754 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
2755 struct mlx5_ifc_cq_error_bits cq_error;
2756 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
2757 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
2758 struct mlx5_ifc_gpio_event_bits gpio_event;
2759 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
2760 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
2761 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
b4ff3a36 2762 u8 reserved_at_0[0xe0];
e281682b
SM		 2763};
2764
2765struct mlx5_ifc_health_buffer_bits {
b4ff3a36 2766 u8 reserved_at_0[0x100];
e281682b
SM		 2767
2768 u8 assert_existptr[0x20];
2769
2770 u8 assert_callra[0x20];
2771
b4ff3a36 2772 u8 reserved_at_140[0x40];
e281682b
SM		 2773
2774 u8 fw_version[0x20];
2775
2776 u8 hw_id[0x20];
2777
b4ff3a36 2778 u8 reserved_at_1c0[0x20];
e281682b
SM		 2779
2780 u8 irisc_index[0x8];
2781 u8 synd[0x8];
2782 u8 ext_synd[0x10];
2783};
2784
2785struct mlx5_ifc_register_loopback_control_bits {
2786 u8 no_lb[0x1];
b4ff3a36 2787 u8 reserved_at_1[0x7];
e281682b 2788 u8 port[0x8];
b4ff3a36 2789 u8 reserved_at_10[0x10];
e281682b 2790
b4ff3a36 2791 u8 reserved_at_20[0x60];
e281682b
SM		 2792};
2793
2794struct mlx5_ifc_teardown_hca_out_bits {
2795 u8 status[0x8];
b4ff3a36 2796 u8 reserved_at_8[0x18];
e281682b
SM		 2797
2798 u8 syndrome[0x20];
2799
b4ff3a36 2800 u8 reserved_at_40[0x40];
e281682b
SM		 2801};
2802
2803enum {
2804 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
2805 MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE = 0x1,
2806};
2807
2808struct mlx5_ifc_teardown_hca_in_bits {
2809 u8 opcode[0x10];
b4ff3a36 2810 u8 reserved_at_10[0x10];
e281682b 2811
b4ff3a36 2812 u8 reserved_at_20[0x10];
e281682b
SM		 2813 u8 op_mod[0x10];
2814
b4ff3a36 2815 u8 reserved_at_40[0x10];
e281682b
SM		 2816 u8 profile[0x10];
2817
b4ff3a36 2818 u8 reserved_at_60[0x20];
e281682b
SM		 2819};
2820
2821struct mlx5_ifc_sqerr2rts_qp_out_bits {
2822 u8 status[0x8];
b4ff3a36 2823 u8 reserved_at_8[0x18];
e281682b
SM		 2824
2825 u8 syndrome[0x20];
2826
b4ff3a36 2827 u8 reserved_at_40[0x40];
e281682b
SM		 2828};
2829
2830struct mlx5_ifc_sqerr2rts_qp_in_bits {
2831 u8 opcode[0x10];
b4ff3a36 2832 u8 reserved_at_10[0x10];
e281682b 2833
b4ff3a36 2834 u8 reserved_at_20[0x10];
e281682b
SM		 2835 u8 op_mod[0x10];
2836
b4ff3a36 2837 u8 reserved_at_40[0x8];
e281682b
SM		 2838 u8 qpn[0x18];
2839
b4ff3a36 2840 u8 reserved_at_60[0x20];
e281682b
SM		 2841
2842 u8 opt_param_mask[0x20];
2843
b4ff3a36 2844 u8 reserved_at_a0[0x20];
e281682b
SM		 2845
2846 struct mlx5_ifc_qpc_bits qpc;
2847
b4ff3a36 2848 u8 reserved_at_800[0x80];
e281682b
SM		 2849};
2850
2851struct mlx5_ifc_sqd2rts_qp_out_bits {
2852 u8 status[0x8];
b4ff3a36 2853 u8 reserved_at_8[0x18];
e281682b
SM		 2854
2855 u8 syndrome[0x20];
2856
b4ff3a36 2857 u8 reserved_at_40[0x40];
e281682b
SM		 2858};
2859
2860struct mlx5_ifc_sqd2rts_qp_in_bits {
2861 u8 opcode[0x10];
b4ff3a36 2862 u8 reserved_at_10[0x10];
e281682b 2863
b4ff3a36 2864 u8 reserved_at_20[0x10];
e281682b
SM		 2865 u8 op_mod[0x10];
2866
b4ff3a36 2867 u8 reserved_at_40[0x8];
e281682b
SM		 2868 u8 qpn[0x18];
2869
b4ff3a36 2870 u8 reserved_at_60[0x20];
e281682b
SM		 2871
2872 u8 opt_param_mask[0x20];
2873
b4ff3a36 2874 u8 reserved_at_a0[0x20];
e281682b
SM		 2875
2876 struct mlx5_ifc_qpc_bits qpc;
2877
b4ff3a36 2878 u8 reserved_at_800[0x80];
e281682b
SM		 2879};
2880
2881struct mlx5_ifc_set_roce_address_out_bits {
2882 u8 status[0x8];
b4ff3a36 2883 u8 reserved_at_8[0x18];
e281682b
SM		 2884
2885 u8 syndrome[0x20];
2886
b4ff3a36 2887 u8 reserved_at_40[0x40];
e281682b
SM		 2888};
2889
2890struct mlx5_ifc_set_roce_address_in_bits {
2891 u8 opcode[0x10];
b4ff3a36 2892 u8 reserved_at_10[0x10];
e281682b 2893
b4ff3a36 2894 u8 reserved_at_20[0x10];
e281682b
SM		 2895 u8 op_mod[0x10];
2896
2897 u8 roce_address_index[0x10];
b4ff3a36 2898 u8 reserved_at_50[0x10];
e281682b 2899
b4ff3a36 2900 u8 reserved_at_60[0x20];
e281682b
SM		 2901
2902 struct mlx5_ifc_roce_addr_layout_bits roce_address;
2903};
2904
2905struct mlx5_ifc_set_mad_demux_out_bits {
2906 u8 status[0x8];
b4ff3a36 2907 u8 reserved_at_8[0x18];
e281682b
SM		 2908
2909 u8 syndrome[0x20];
2910
b4ff3a36 2911 u8 reserved_at_40[0x40];
e281682b
SM		 2912};
2913
2914enum {
2915 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
2916 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
2917};
2918
2919struct mlx5_ifc_set_mad_demux_in_bits {
2920 u8 opcode[0x10];
b4ff3a36 2921 u8 reserved_at_10[0x10];
e281682b 2922
b4ff3a36 2923 u8 reserved_at_20[0x10];
e281682b
SM		 2924 u8 op_mod[0x10];
2925
b4ff3a36 2926 u8 reserved_at_40[0x20];
e281682b 2927
b4ff3a36 2928 u8 reserved_at_60[0x6];
e281682b 2929 u8 demux_mode[0x2];
b4ff3a36 2930 u8 reserved_at_68[0x18];
e281682b
SM		 2931};
2932
2933struct mlx5_ifc_set_l2_table_entry_out_bits {
2934 u8 status[0x8];
b4ff3a36 2935 u8 reserved_at_8[0x18];
e281682b
SM		 2936
2937 u8 syndrome[0x20];
2938
b4ff3a36 2939 u8 reserved_at_40[0x40];
e281682b
SM		 2940};
2941
2942struct mlx5_ifc_set_l2_table_entry_in_bits {
2943 u8 opcode[0x10];
b4ff3a36 2944 u8 reserved_at_10[0x10];
e281682b 2945
b4ff3a36 2946 u8 reserved_at_20[0x10];
e281682b
SM		 2947 u8 op_mod[0x10];
2948
b4ff3a36 2949 u8 reserved_at_40[0x60];
e281682b 2950
b4ff3a36 2951 u8 reserved_at_a0[0x8];
e281682b
SM		 2952 u8 table_index[0x18];
2953
b4ff3a36 2954 u8 reserved_at_c0[0x20];
e281682b 2955
b4ff3a36 2956 u8 reserved_at_e0[0x13];
e281682b
SM		 2957 u8 vlan_valid[0x1];
2958 u8 vlan[0xc];
2959
2960 struct mlx5_ifc_mac_address_layout_bits mac_address;
2961
b4ff3a36 2962 u8 reserved_at_140[0xc0];
e281682b
SM		 2963};
2964
2965struct mlx5_ifc_set_issi_out_bits {
2966 u8 status[0x8];
b4ff3a36 2967 u8 reserved_at_8[0x18];
e281682b
SM		 2968
2969 u8 syndrome[0x20];
2970
b4ff3a36 2971 u8 reserved_at_40[0x40];
e281682b
SM		 2972};
2973
2974struct mlx5_ifc_set_issi_in_bits {
2975 u8 opcode[0x10];
b4ff3a36 2976 u8 reserved_at_10[0x10];
e281682b 2977
b4ff3a36 2978 u8 reserved_at_20[0x10];
e281682b
SM		 2979 u8 op_mod[0x10];
2980
b4ff3a36 2981 u8 reserved_at_40[0x10];
e281682b
SM		 2982 u8 current_issi[0x10];
2983
b4ff3a36 2984 u8 reserved_at_60[0x20];
e281682b
SM		 2985};
2986
2987struct mlx5_ifc_set_hca_cap_out_bits {
2988 u8 status[0x8];
b4ff3a36 2989 u8 reserved_at_8[0x18];
e281682b
SM		 2990
2991 u8 syndrome[0x20];
2992
b4ff3a36 2993 u8 reserved_at_40[0x40];
e281682b
SM		 2994};
2995
2996struct mlx5_ifc_set_hca_cap_in_bits {
2997 u8 opcode[0x10];
b4ff3a36 2998 u8 reserved_at_10[0x10];
e281682b 2999
b4ff3a36 3000 u8 reserved_at_20[0x10];
e281682b
SM		 3001 u8 op_mod[0x10];
3002
b4ff3a36 3003 u8 reserved_at_40[0x40];
e281682b
SM		 3004
3005 union mlx5_ifc_hca_cap_union_bits capability;
3006};
3007
26a81453
MG		 3008enum {
3009 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
3010 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
3011 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
3012 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
3013};
3014
e281682b
SM		 3015struct mlx5_ifc_set_fte_out_bits {
3016 u8 status[0x8];
b4ff3a36 3017 u8 reserved_at_8[0x18];
e281682b
SM		 3018
3019 u8 syndrome[0x20];
3020
b4ff3a36 3021 u8 reserved_at_40[0x40];
e281682b
SM		 3022};
3023
3024struct mlx5_ifc_set_fte_in_bits {
3025 u8 opcode[0x10];
b4ff3a36 3026 u8 reserved_at_10[0x10];
e281682b 3027
b4ff3a36 3028 u8 reserved_at_20[0x10];
e281682b
SM		 3029 u8 op_mod[0x10];
3030
7d5e1423
SM		 3031 u8 other_vport[0x1];
3032 u8 reserved_at_41[0xf];
3033 u8 vport_number[0x10];
3034
3035 u8 reserved_at_60[0x20];
e281682b
SM		 3036
3037 u8 table_type[0x8];
b4ff3a36 3038 u8 reserved_at_88[0x18];
e281682b 3039
b4ff3a36 3040 u8 reserved_at_a0[0x8];
e281682b
SM		 3041 u8 table_id[0x18];
3042
b4ff3a36 3043 u8 reserved_at_c0[0x18];
26a81453
MG		 3044 u8 modify_enable_mask[0x8];
3045
b4ff3a36 3046 u8 reserved_at_e0[0x20];
e281682b
SM		 3047
3048 u8 flow_index[0x20];
3049
b4ff3a36 3050 u8 reserved_at_120[0xe0];
e281682b
SM		 3051
3052 struct mlx5_ifc_flow_context_bits flow_context;
3053};
3054
3055struct mlx5_ifc_rts2rts_qp_out_bits {
3056 u8 status[0x8];
b4ff3a36 3057 u8 reserved_at_8[0x18];
e281682b
SM		 3058
3059 u8 syndrome[0x20];
3060
b4ff3a36 3061 u8 reserved_at_40[0x40];
e281682b
SM		 3062};
3063
3064struct mlx5_ifc_rts2rts_qp_in_bits {
3065 u8 opcode[0x10];
b4ff3a36 3066 u8 reserved_at_10[0x10];
e281682b 3067
b4ff3a36 3068 u8 reserved_at_20[0x10];
e281682b
SM		 3069 u8 op_mod[0x10];
3070
b4ff3a36 3071 u8 reserved_at_40[0x8];
e281682b
SM		 3072 u8 qpn[0x18];
3073
b4ff3a36 3074 u8 reserved_at_60[0x20];
e281682b
SM		 3075
3076 u8 opt_param_mask[0x20];
3077
b4ff3a36 3078 u8 reserved_at_a0[0x20];
e281682b
SM		 3079
3080 struct mlx5_ifc_qpc_bits qpc;
3081
b4ff3a36 3082 u8 reserved_at_800[0x80];
e281682b
SM		 3083};
3084
3085struct mlx5_ifc_rtr2rts_qp_out_bits {
3086 u8 status[0x8];
b4ff3a36 3087 u8 reserved_at_8[0x18];
e281682b
SM		 3088
3089 u8 syndrome[0x20];
3090
b4ff3a36 3091 u8 reserved_at_40[0x40];
e281682b
SM		 3092};
3093
3094struct mlx5_ifc_rtr2rts_qp_in_bits {
3095 u8 opcode[0x10];
b4ff3a36 3096 u8 reserved_at_10[0x10];
e281682b 3097
b4ff3a36 3098 u8 reserved_at_20[0x10];
e281682b
SM		 3099 u8 op_mod[0x10];
3100
b4ff3a36 3101 u8 reserved_at_40[0x8];
e281682b
SM		 3102 u8 qpn[0x18];
3103
b4ff3a36 3104 u8 reserved_at_60[0x20];
e281682b
SM		 3105
3106 u8 opt_param_mask[0x20];
3107
b4ff3a36 3108 u8 reserved_at_a0[0x20];
e281682b
SM		 3109
3110 struct mlx5_ifc_qpc_bits qpc;
3111
b4ff3a36 3112 u8 reserved_at_800[0x80];
e281682b
SM		 3113};
3114
3115struct mlx5_ifc_rst2init_qp_out_bits {
3116 u8 status[0x8];
b4ff3a36 3117 u8 reserved_at_8[0x18];
e281682b
SM		 3118
3119 u8 syndrome[0x20];
3120
b4ff3a36 3121 u8 reserved_at_40[0x40];
e281682b
SM		 3122};
3123
3124struct mlx5_ifc_rst2init_qp_in_bits {
3125 u8 opcode[0x10];
b4ff3a36 3126 u8 reserved_at_10[0x10];
e281682b 3127
b4ff3a36 3128 u8 reserved_at_20[0x10];
e281682b
SM		 3129 u8 op_mod[0x10];
3130
b4ff3a36 3131 u8 reserved_at_40[0x8];
e281682b
SM		 3132 u8 qpn[0x18];
3133
b4ff3a36 3134 u8 reserved_at_60[0x20];
e281682b
SM		 3135
3136 u8 opt_param_mask[0x20];
3137
b4ff3a36 3138 u8 reserved_at_a0[0x20];
e281682b
SM		 3139
3140 struct mlx5_ifc_qpc_bits qpc;
3141
b4ff3a36 3142 u8 reserved_at_800[0x80];
e281682b
SM		 3143};
3144
3145struct mlx5_ifc_query_xrc_srq_out_bits {
3146 u8 status[0x8];
b4ff3a36 3147 u8 reserved_at_8[0x18];
e281682b
SM		 3148
3149 u8 syndrome[0x20];
3150
b4ff3a36 3151 u8 reserved_at_40[0x40];
e281682b
SM		 3152
3153 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3154
b4ff3a36 3155 u8 reserved_at_280[0x600];
e281682b
SM		 3156
3157 u8 pas[0][0x40];
3158};
3159
3160struct mlx5_ifc_query_xrc_srq_in_bits {
3161 u8 opcode[0x10];
b4ff3a36 3162 u8 reserved_at_10[0x10];
e281682b 3163
b4ff3a36 3164 u8 reserved_at_20[0x10];
e281682b
SM		 3165 u8 op_mod[0x10];
3166
b4ff3a36 3167 u8 reserved_at_40[0x8];
e281682b
SM		 3168 u8 xrc_srqn[0x18];
3169
b4ff3a36 3170 u8 reserved_at_60[0x20];
e281682b
SM		 3171};
3172
3173enum {
3174 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
3175 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
3176};
3177
3178struct mlx5_ifc_query_vport_state_out_bits {
3179 u8 status[0x8];
b4ff3a36 3180 u8 reserved_at_8[0x18];
e281682b
SM		 3181
3182 u8 syndrome[0x20];
3183
b4ff3a36 3184 u8 reserved_at_40[0x20];
e281682b 3185
b4ff3a36 3186 u8 reserved_at_60[0x18];
e281682b
SM		 3187 u8 admin_state[0x4];
3188 u8 state[0x4];
3189};
3190
3191enum {
3192 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0,
e7546514 3193 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1,
e281682b
SM		 3194};
3195
3196struct mlx5_ifc_query_vport_state_in_bits {
3197 u8 opcode[0x10];
b4ff3a36 3198 u8 reserved_at_10[0x10];
e281682b 3199
b4ff3a36 3200 u8 reserved_at_20[0x10];
e281682b
SM		 3201 u8 op_mod[0x10];
3202
3203 u8 other_vport[0x1];
b4ff3a36 3204 u8 reserved_at_41[0xf];
e281682b
SM		 3205 u8 vport_number[0x10];
3206
b4ff3a36 3207 u8 reserved_at_60[0x20];
e281682b
SM		 3208};
3209
3210struct mlx5_ifc_query_vport_counter_out_bits {
3211 u8 status[0x8];
b4ff3a36 3212 u8 reserved_at_8[0x18];
e281682b
SM		 3213
3214 u8 syndrome[0x20];
3215
b4ff3a36 3216 u8 reserved_at_40[0x40];
e281682b
SM		 3217
3218 struct mlx5_ifc_traffic_counter_bits received_errors;
3219
3220 struct mlx5_ifc_traffic_counter_bits transmit_errors;
3221
3222 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3223
3224 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3225
3226 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3227
3228 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3229
3230 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3231
3232 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3233
3234 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3235
3236 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3237
3238 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3239
3240 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3241
b4ff3a36 3242 u8 reserved_at_680[0xa00];
e281682b
SM		 3243};
3244
3245enum {
3246 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
3247};
3248
3249struct mlx5_ifc_query_vport_counter_in_bits {
3250 u8 opcode[0x10];
b4ff3a36 3251 u8 reserved_at_10[0x10];
e281682b 3252
b4ff3a36 3253 u8 reserved_at_20[0x10];
e281682b
SM		 3254 u8 op_mod[0x10];
3255
3256 u8 other_vport[0x1];
b54ba277
MY		 3257 u8 reserved_at_41[0xb];
3258 u8 port_num[0x4];
e281682b
SM		 3259 u8 vport_number[0x10];
3260
b4ff3a36 3261 u8 reserved_at_60[0x60];
e281682b
SM		 3262
3263 u8 clear[0x1];
b4ff3a36 3264 u8 reserved_at_c1[0x1f];
e281682b 3265
b4ff3a36 3266 u8 reserved_at_e0[0x20];
e281682b
SM		 3267};
3268
3269struct mlx5_ifc_query_tis_out_bits {
3270 u8 status[0x8];
b4ff3a36 3271 u8 reserved_at_8[0x18];
e281682b
SM		 3272
3273 u8 syndrome[0x20];
3274
b4ff3a36 3275 u8 reserved_at_40[0x40];
e281682b
SM		 3276
3277 struct mlx5_ifc_tisc_bits tis_context;
3278};
3279
3280struct mlx5_ifc_query_tis_in_bits {
3281 u8 opcode[0x10];
b4ff3a36 3282 u8 reserved_at_10[0x10];
e281682b 3283
b4ff3a36 3284 u8 reserved_at_20[0x10];
e281682b
SM		 3285 u8 op_mod[0x10];
3286
b4ff3a36 3287 u8 reserved_at_40[0x8];
e281682b
SM		 3288 u8 tisn[0x18];
3289
b4ff3a36 3290 u8 reserved_at_60[0x20];
e281682b
SM		 3291};
3292
3293struct mlx5_ifc_query_tir_out_bits {
3294 u8 status[0x8];
b4ff3a36 3295 u8 reserved_at_8[0x18];
e281682b
SM		 3296
3297 u8 syndrome[0x20];
3298
b4ff3a36 3299 u8 reserved_at_40[0xc0];
e281682b
SM		 3300
3301 struct mlx5_ifc_tirc_bits tir_context;
3302};
3303
3304struct mlx5_ifc_query_tir_in_bits {
3305 u8 opcode[0x10];
b4ff3a36 3306 u8 reserved_at_10[0x10];
e281682b 3307
b4ff3a36 3308 u8 reserved_at_20[0x10];
e281682b
SM		 3309 u8 op_mod[0x10];
3310
b4ff3a36 3311 u8 reserved_at_40[0x8];
e281682b
SM		 3312 u8 tirn[0x18];
3313
b4ff3a36 3314 u8 reserved_at_60[0x20];
e281682b
SM		 3315};
3316
3317struct mlx5_ifc_query_srq_out_bits {
3318 u8 status[0x8];
b4ff3a36 3319 u8 reserved_at_8[0x18];
e281682b
SM		 3320
3321 u8 syndrome[0x20];
3322
b4ff3a36 3323 u8 reserved_at_40[0x40];
e281682b
SM		 3324
3325 struct mlx5_ifc_srqc_bits srq_context_entry;
3326
b4ff3a36 3327 u8 reserved_at_280[0x600];
e281682b
SM		 3328
3329 u8 pas[0][0x40];
3330};
3331
3332struct mlx5_ifc_query_srq_in_bits {
3333 u8 opcode[0x10];
b4ff3a36 3334 u8 reserved_at_10[0x10];
e281682b 3335
b4ff3a36 3336 u8 reserved_at_20[0x10];
e281682b
SM		 3337 u8 op_mod[0x10];
3338
b4ff3a36 3339 u8 reserved_at_40[0x8];
e281682b
SM		 3340 u8 srqn[0x18];
3341
b4ff3a36 3342 u8 reserved_at_60[0x20];
e281682b
SM		 3343};
3344
3345struct mlx5_ifc_query_sq_out_bits {
3346 u8 status[0x8];
b4ff3a36 3347 u8 reserved_at_8[0x18];
e281682b
SM		 3348
3349 u8 syndrome[0x20];
3350
b4ff3a36 3351 u8 reserved_at_40[0xc0];
e281682b
SM		 3352
3353 struct mlx5_ifc_sqc_bits sq_context;
3354};
3355
3356struct mlx5_ifc_query_sq_in_bits {
3357 u8 opcode[0x10];
b4ff3a36 3358 u8 reserved_at_10[0x10];
e281682b 3359
b4ff3a36 3360 u8 reserved_at_20[0x10];
e281682b
SM		 3361 u8 op_mod[0x10];
3362
b4ff3a36 3363 u8 reserved_at_40[0x8];
e281682b
SM		 3364 u8 sqn[0x18];
3365
b4ff3a36 3366 u8 reserved_at_60[0x20];
e281682b
SM		 3367};
3368
3369struct mlx5_ifc_query_special_contexts_out_bits {
3370 u8 status[0x8];
b4ff3a36 3371 u8 reserved_at_8[0x18];
e281682b
SM		 3372
3373 u8 syndrome[0x20];
3374
b4ff3a36 3375 u8 reserved_at_40[0x20];
e281682b
SM		 3376
3377 u8 resd_lkey[0x20];
3378};
3379
3380struct mlx5_ifc_query_special_contexts_in_bits {
3381 u8 opcode[0x10];
b4ff3a36 3382 u8 reserved_at_10[0x10];
e281682b 3383
b4ff3a36 3384 u8 reserved_at_20[0x10];
e281682b
SM		 3385 u8 op_mod[0x10];
3386
b4ff3a36 3387 u8 reserved_at_40[0x40];
e281682b
SM		 3388};
3389
3390struct mlx5_ifc_query_rqt_out_bits {
3391 u8 status[0x8];
b4ff3a36 3392 u8 reserved_at_8[0x18];
e281682b
SM		 3393
3394 u8 syndrome[0x20];
3395
b4ff3a36 3396 u8 reserved_at_40[0xc0];
e281682b
SM		 3397
3398 struct mlx5_ifc_rqtc_bits rqt_context;
3399};
3400
3401struct mlx5_ifc_query_rqt_in_bits {
3402 u8 opcode[0x10];
b4ff3a36 3403 u8 reserved_at_10[0x10];
e281682b 3404
b4ff3a36 3405 u8 reserved_at_20[0x10];
e281682b
SM		 3406 u8 op_mod[0x10];
3407
b4ff3a36 3408 u8 reserved_at_40[0x8];
e281682b
SM		 3409 u8 rqtn[0x18];
3410
b4ff3a36 3411 u8 reserved_at_60[0x20];
e281682b
SM		 3412};
3413
3414struct mlx5_ifc_query_rq_out_bits {
3415 u8 status[0x8];
b4ff3a36 3416 u8 reserved_at_8[0x18];
e281682b
SM		 3417
3418 u8 syndrome[0x20];
3419
b4ff3a36 3420 u8 reserved_at_40[0xc0];
e281682b
SM		 3421
3422 struct mlx5_ifc_rqc_bits rq_context;
3423};
3424
3425struct mlx5_ifc_query_rq_in_bits {
3426 u8 opcode[0x10];
b4ff3a36 3427 u8 reserved_at_10[0x10];
e281682b 3428
b4ff3a36 3429 u8 reserved_at_20[0x10];
e281682b
SM		 3430 u8 op_mod[0x10];
3431
b4ff3a36 3432 u8 reserved_at_40[0x8];
e281682b
SM		 3433 u8 rqn[0x18];
3434
b4ff3a36 3435 u8 reserved_at_60[0x20];
e281682b
SM		 3436};
3437
3438struct mlx5_ifc_query_roce_address_out_bits {
3439 u8 status[0x8];
b4ff3a36 3440 u8 reserved_at_8[0x18];
e281682b
SM		 3441
3442 u8 syndrome[0x20];
3443
b4ff3a36 3444 u8 reserved_at_40[0x40];
e281682b
SM		 3445
3446 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3447};
3448
3449struct mlx5_ifc_query_roce_address_in_bits {
3450 u8 opcode[0x10];
b4ff3a36 3451 u8 reserved_at_10[0x10];
e281682b 3452
b4ff3a36 3453 u8 reserved_at_20[0x10];
e281682b
SM		 3454 u8 op_mod[0x10];
3455
3456 u8 roce_address_index[0x10];
b4ff3a36 3457 u8 reserved_at_50[0x10];
e281682b 3458
b4ff3a36 3459 u8 reserved_at_60[0x20];
e281682b
SM		 3460};
3461
3462struct mlx5_ifc_query_rmp_out_bits {
3463 u8 status[0x8];
b4ff3a36 3464 u8 reserved_at_8[0x18];
e281682b
SM		 3465
3466 u8 syndrome[0x20];
3467
b4ff3a36 3468 u8 reserved_at_40[0xc0];
e281682b
SM		 3469
3470 struct mlx5_ifc_rmpc_bits rmp_context;
3471};
3472
3473struct mlx5_ifc_query_rmp_in_bits {
3474 u8 opcode[0x10];
b4ff3a36 3475 u8 reserved_at_10[0x10];
e281682b 3476
b4ff3a36 3477 u8 reserved_at_20[0x10];
e281682b
SM		 3478 u8 op_mod[0x10];
3479
b4ff3a36 3480 u8 reserved_at_40[0x8];
e281682b
SM		 3481 u8 rmpn[0x18];
3482
b4ff3a36 3483 u8 reserved_at_60[0x20];
e281682b
SM		 3484};
3485
3486struct mlx5_ifc_query_qp_out_bits {
3487 u8 status[0x8];
b4ff3a36 3488 u8 reserved_at_8[0x18];
e281682b
SM		 3489
3490 u8 syndrome[0x20];
3491
b4ff3a36 3492 u8 reserved_at_40[0x40];
e281682b
SM		 3493
3494 u8 opt_param_mask[0x20];
3495
b4ff3a36 3496 u8 reserved_at_a0[0x20];
e281682b
SM		 3497
3498 struct mlx5_ifc_qpc_bits qpc;
3499
b4ff3a36 3500 u8 reserved_at_800[0x80];
e281682b
SM		 3501
3502 u8 pas[0][0x40];
3503};
3504
3505struct mlx5_ifc_query_qp_in_bits {
3506 u8 opcode[0x10];
b4ff3a36 3507 u8 reserved_at_10[0x10];
e281682b 3508
b4ff3a36 3509 u8 reserved_at_20[0x10];
e281682b
SM		 3510 u8 op_mod[0x10];
3511
b4ff3a36 3512 u8 reserved_at_40[0x8];
e281682b
SM		 3513 u8 qpn[0x18];
3514
b4ff3a36 3515 u8 reserved_at_60[0x20];
e281682b
SM		 3516};
3517
3518struct mlx5_ifc_query_q_counter_out_bits {
3519 u8 status[0x8];
b4ff3a36 3520 u8 reserved_at_8[0x18];
e281682b
SM		 3521
3522 u8 syndrome[0x20];
3523
b4ff3a36 3524 u8 reserved_at_40[0x40];
e281682b
SM		 3525
3526 u8 rx_write_requests[0x20];
3527
b4ff3a36 3528 u8 reserved_at_a0[0x20];
e281682b
SM		 3529
3530 u8 rx_read_requests[0x20];
3531
b4ff3a36 3532 u8 reserved_at_e0[0x20];
e281682b
SM		 3533
3534 u8 rx_atomic_requests[0x20];
3535
b4ff3a36 3536 u8 reserved_at_120[0x20];
e281682b
SM		 3537
3538 u8 rx_dct_connect[0x20];
3539
b4ff3a36 3540 u8 reserved_at_160[0x20];
e281682b
SM		 3541
3542 u8 out_of_buffer[0x20];
3543
b4ff3a36 3544 u8 reserved_at_1a0[0x20];
e281682b
SM		 3545
3546 u8 out_of_sequence[0x20];
3547
b4ff3a36 3548 u8 reserved_at_1e0[0x620];
e281682b
SM		 3549};
3550
3551struct mlx5_ifc_query_q_counter_in_bits {
3552 u8 opcode[0x10];
b4ff3a36 3553 u8 reserved_at_10[0x10];
e281682b 3554
b4ff3a36 3555 u8 reserved_at_20[0x10];
e281682b
SM		 3556 u8 op_mod[0x10];
3557
b4ff3a36 3558 u8 reserved_at_40[0x80];
e281682b
SM		 3559
3560 u8 clear[0x1];
b4ff3a36 3561 u8 reserved_at_c1[0x1f];
e281682b 3562
b4ff3a36 3563 u8 reserved_at_e0[0x18];
e281682b
SM		 3564 u8 counter_set_id[0x8];
3565};
3566
3567struct mlx5_ifc_query_pages_out_bits {
3568 u8 status[0x8];
b4ff3a36 3569 u8 reserved_at_8[0x18];
e281682b
SM		 3570
3571 u8 syndrome[0x20];
3572
b4ff3a36 3573 u8 reserved_at_40[0x10];
e281682b
SM		 3574 u8 function_id[0x10];
3575
3576 u8 num_pages[0x20];
3577};
3578
3579enum {
3580 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
3581 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
3582 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
3583};
3584
3585struct mlx5_ifc_query_pages_in_bits {
3586 u8 opcode[0x10];
b4ff3a36 3587 u8 reserved_at_10[0x10];
e281682b 3588
b4ff3a36 3589 u8 reserved_at_20[0x10];
e281682b
SM		 3590 u8 op_mod[0x10];
3591
b4ff3a36 3592 u8 reserved_at_40[0x10];
e281682b
SM		 3593 u8 function_id[0x10];
3594
b4ff3a36 3595 u8 reserved_at_60[0x20];
e281682b
SM		 3596};
3597
3598struct mlx5_ifc_query_nic_vport_context_out_bits {
3599 u8 status[0x8];
b4ff3a36 3600 u8 reserved_at_8[0x18];
e281682b
SM		 3601
3602 u8 syndrome[0x20];
3603
b4ff3a36 3604 u8 reserved_at_40[0x40];
e281682b
SM		 3605
3606 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
3607};
3608
3609struct mlx5_ifc_query_nic_vport_context_in_bits {
3610 u8 opcode[0x10];
b4ff3a36 3611 u8 reserved_at_10[0x10];
e281682b 3612
b4ff3a36 3613 u8 reserved_at_20[0x10];
e281682b
SM		 3614 u8 op_mod[0x10];
3615
3616 u8 other_vport[0x1];
b4ff3a36 3617 u8 reserved_at_41[0xf];
e281682b
SM		 3618 u8 vport_number[0x10];
3619
b4ff3a36 3620 u8 reserved_at_60[0x5];
e281682b 3621 u8 allowed_list_type[0x3];
b4ff3a36 3622 u8 reserved_at_68[0x18];
e281682b
SM		 3623};
3624
3625struct mlx5_ifc_query_mkey_out_bits {
3626 u8 status[0x8];
b4ff3a36 3627 u8 reserved_at_8[0x18];
e281682b
SM		 3628
3629 u8 syndrome[0x20];
3630
b4ff3a36 3631 u8 reserved_at_40[0x40];
e281682b
SM		 3632
3633 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
3634
b4ff3a36 3635 u8 reserved_at_280[0x600];
e281682b
SM		 3636
3637 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
3638
3639 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
3640};
3641
3642struct mlx5_ifc_query_mkey_in_bits {
3643 u8 opcode[0x10];
b4ff3a36 3644 u8 reserved_at_10[0x10];
e281682b 3645
b4ff3a36 3646 u8 reserved_at_20[0x10];
e281682b
SM		 3647 u8 op_mod[0x10];
3648
b4ff3a36 3649 u8 reserved_at_40[0x8];
e281682b
SM		 3650 u8 mkey_index[0x18];
3651
3652 u8 pg_access[0x1];
b4ff3a36 3653 u8 reserved_at_61[0x1f];
e281682b
SM		 3654};
3655
3656struct mlx5_ifc_query_mad_demux_out_bits {
3657 u8 status[0x8];
b4ff3a36 3658 u8 reserved_at_8[0x18];
e281682b
SM		 3659
3660 u8 syndrome[0x20];
3661
b4ff3a36 3662 u8 reserved_at_40[0x40];
e281682b
SM		 3663
3664 u8 mad_dumux_parameters_block[0x20];
3665};
3666
3667struct mlx5_ifc_query_mad_demux_in_bits {
3668 u8 opcode[0x10];
b4ff3a36 3669 u8 reserved_at_10[0x10];
e281682b 3670
b4ff3a36 3671 u8 reserved_at_20[0x10];
e281682b
SM		 3672 u8 op_mod[0x10];
3673
b4ff3a36 3674 u8 reserved_at_40[0x40];
e281682b
SM		 3675};
3676
3677struct mlx5_ifc_query_l2_table_entry_out_bits {
3678 u8 status[0x8];
b4ff3a36 3679 u8 reserved_at_8[0x18];
e281682b
SM		 3680
3681 u8 syndrome[0x20];
3682
b4ff3a36 3683 u8 reserved_at_40[0xa0];
e281682b 3684
b4ff3a36 3685 u8 reserved_at_e0[0x13];
e281682b
SM		 3686 u8 vlan_valid[0x1];
3687 u8 vlan[0xc];
3688
3689 struct mlx5_ifc_mac_address_layout_bits mac_address;
3690
b4ff3a36 3691 u8 reserved_at_140[0xc0];
e281682b
SM		 3692};
3693
3694struct mlx5_ifc_query_l2_table_entry_in_bits {
3695 u8 opcode[0x10];
b4ff3a36 3696 u8 reserved_at_10[0x10];
e281682b 3697
b4ff3a36 3698 u8 reserved_at_20[0x10];
e281682b
SM		 3699 u8 op_mod[0x10];
3700
b4ff3a36 3701 u8 reserved_at_40[0x60];
e281682b 3702
b4ff3a36 3703 u8 reserved_at_a0[0x8];
e281682b
SM		 3704 u8 table_index[0x18];
3705
b4ff3a36 3706 u8 reserved_at_c0[0x140];
e281682b
SM		 3707};
3708
3709struct mlx5_ifc_query_issi_out_bits {
3710 u8 status[0x8];
b4ff3a36 3711 u8 reserved_at_8[0x18];
e281682b
SM		 3712
3713 u8 syndrome[0x20];
3714
b4ff3a36 3715 u8 reserved_at_40[0x10];
e281682b
SM		 3716 u8 current_issi[0x10];
3717
b4ff3a36 3718 u8 reserved_at_60[0xa0];
e281682b 3719
b4ff3a36 3720 u8 reserved_at_100[76][0x8];
e281682b
SM		 3721 u8 supported_issi_dw0[0x20];
3722};
3723
3724struct mlx5_ifc_query_issi_in_bits {
3725 u8 opcode[0x10];
b4ff3a36 3726 u8 reserved_at_10[0x10];
e281682b 3727
b4ff3a36 3728 u8 reserved_at_20[0x10];
e281682b
SM		 3729 u8 op_mod[0x10];
3730
b4ff3a36 3731 u8 reserved_at_40[0x40];
e281682b
SM		 3732};
3733
3734struct mlx5_ifc_query_hca_vport_pkey_out_bits {
3735 u8 status[0x8];
b4ff3a36 3736 u8 reserved_at_8[0x18];
e281682b
SM		 3737
3738 u8 syndrome[0x20];
3739
b4ff3a36 3740 u8 reserved_at_40[0x40];
e281682b
SM		 3741
3742 struct mlx5_ifc_pkey_bits pkey[0];
3743};
3744
3745struct mlx5_ifc_query_hca_vport_pkey_in_bits {
3746 u8 opcode[0x10];
b4ff3a36 3747 u8 reserved_at_10[0x10];
e281682b 3748
b4ff3a36 3749 u8 reserved_at_20[0x10];
e281682b
SM		 3750 u8 op_mod[0x10];
3751
3752 u8 other_vport[0x1];
b4ff3a36 3753 u8 reserved_at_41[0xb];
707c4602 3754 u8 port_num[0x4];
e281682b
SM		 3755 u8 vport_number[0x10];
3756
b4ff3a36 3757 u8 reserved_at_60[0x10];
e281682b
SM		 3758 u8 pkey_index[0x10];
3759};
3760
eff901d3
EC		 3761enum {
3762 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
3763 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
3764 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
3765};
3766
e281682b
SM		 3767struct mlx5_ifc_query_hca_vport_gid_out_bits {
3768 u8 status[0x8];
b4ff3a36 3769 u8 reserved_at_8[0x18];
e281682b
SM		 3770
3771 u8 syndrome[0x20];
3772
b4ff3a36 3773 u8 reserved_at_40[0x20];
e281682b
SM		 3774
3775 u8 gids_num[0x10];
b4ff3a36 3776 u8 reserved_at_70[0x10];
e281682b
SM		 3777
3778 struct mlx5_ifc_array128_auto_bits gid[0];
3779};
3780
3781struct mlx5_ifc_query_hca_vport_gid_in_bits {
3782 u8 opcode[0x10];
b4ff3a36 3783 u8 reserved_at_10[0x10];
e281682b 3784
b4ff3a36 3785 u8 reserved_at_20[0x10];
e281682b
SM		 3786 u8 op_mod[0x10];
3787
3788 u8 other_vport[0x1];
b4ff3a36 3789 u8 reserved_at_41[0xb];
707c4602 3790 u8 port_num[0x4];
e281682b
SM		 3791 u8 vport_number[0x10];
3792
b4ff3a36 3793 u8 reserved_at_60[0x10];
e281682b
SM		 3794 u8 gid_index[0x10];
3795};
3796
3797struct mlx5_ifc_query_hca_vport_context_out_bits {
3798 u8 status[0x8];
b4ff3a36 3799 u8 reserved_at_8[0x18];
e281682b
SM		 3800
3801 u8 syndrome[0x20];
3802
b4ff3a36 3803 u8 reserved_at_40[0x40];
e281682b
SM		 3804
3805 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
3806};
3807
3808struct mlx5_ifc_query_hca_vport_context_in_bits {
3809 u8 opcode[0x10];
b4ff3a36 3810 u8 reserved_at_10[0x10];
e281682b 3811
b4ff3a36 3812 u8 reserved_at_20[0x10];
e281682b
SM		 3813 u8 op_mod[0x10];
3814
3815 u8 other_vport[0x1];
b4ff3a36 3816 u8 reserved_at_41[0xb];
707c4602 3817 u8 port_num[0x4];
e281682b
SM		 3818 u8 vport_number[0x10];
3819
b4ff3a36 3820 u8 reserved_at_60[0x20];
e281682b
SM		 3821};
3822
3823struct mlx5_ifc_query_hca_cap_out_bits {
3824 u8 status[0x8];
b4ff3a36 3825 u8 reserved_at_8[0x18];
e281682b
SM		 3826
3827 u8 syndrome[0x20];
3828
b4ff3a36 3829 u8 reserved_at_40[0x40];
e281682b
SM		 3830
3831 union mlx5_ifc_hca_cap_union_bits capability;
3832};
3833
3834struct mlx5_ifc_query_hca_cap_in_bits {
3835 u8 opcode[0x10];
b4ff3a36 3836 u8 reserved_at_10[0x10];
e281682b 3837
b4ff3a36 3838 u8 reserved_at_20[0x10];
e281682b
SM		 3839 u8 op_mod[0x10];
3840
b4ff3a36 3841 u8 reserved_at_40[0x40];
e281682b
SM		 3842};
3843
3844struct mlx5_ifc_query_flow_table_out_bits {
3845 u8 status[0x8];
b4ff3a36 3846 u8 reserved_at_8[0x18];
e281682b
SM		 3847
3848 u8 syndrome[0x20];
3849
b4ff3a36 3850 u8 reserved_at_40[0x80];
e281682b 3851
b4ff3a36 3852 u8 reserved_at_c0[0x8];
e281682b 3853 u8 level[0x8];
b4ff3a36 3854 u8 reserved_at_d0[0x8];
e281682b
SM		 3855 u8 log_size[0x8];
3856
b4ff3a36 3857 u8 reserved_at_e0[0x120];
e281682b
SM		 3858};
3859
3860struct mlx5_ifc_query_flow_table_in_bits {
3861 u8 opcode[0x10];
b4ff3a36 3862 u8 reserved_at_10[0x10];
e281682b 3863
b4ff3a36 3864 u8 reserved_at_20[0x10];
e281682b
SM		 3865 u8 op_mod[0x10];
3866
b4ff3a36 3867 u8 reserved_at_40[0x40];
e281682b
SM		 3868
3869 u8 table_type[0x8];
b4ff3a36 3870 u8 reserved_at_88[0x18];
e281682b 3871
b4ff3a36 3872 u8 reserved_at_a0[0x8];
e281682b
SM		 3873 u8 table_id[0x18];
3874
b4ff3a36 3875 u8 reserved_at_c0[0x140];
e281682b
SM		 3876};
3877
3878struct mlx5_ifc_query_fte_out_bits {
3879 u8 status[0x8];
b4ff3a36 3880 u8 reserved_at_8[0x18];
e281682b
SM		 3881
3882 u8 syndrome[0x20];
3883
b4ff3a36 3884 u8 reserved_at_40[0x1c0];
e281682b
SM		 3885
3886 struct mlx5_ifc_flow_context_bits flow_context;
3887};
3888
3889struct mlx5_ifc_query_fte_in_bits {
3890 u8 opcode[0x10];
b4ff3a36 3891 u8 reserved_at_10[0x10];
e281682b 3892
b4ff3a36 3893 u8 reserved_at_20[0x10];
e281682b
SM		 3894 u8 op_mod[0x10];
3895
b4ff3a36 3896 u8 reserved_at_40[0x40];
e281682b
SM		 3897
3898 u8 table_type[0x8];
b4ff3a36 3899 u8 reserved_at_88[0x18];
e281682b 3900
b4ff3a36 3901 u8 reserved_at_a0[0x8];
e281682b
SM		 3902 u8 table_id[0x18];
3903
b4ff3a36 3904 u8 reserved_at_c0[0x40];
e281682b
SM		 3905
3906 u8 flow_index[0x20];
3907
b4ff3a36 3908 u8 reserved_at_120[0xe0];
e281682b
SM		 3909};
3910
3911enum {
3912 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
3913 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
3914 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
3915};
3916
3917struct mlx5_ifc_query_flow_group_out_bits {
3918 u8 status[0x8];
b4ff3a36 3919 u8 reserved_at_8[0x18];
e281682b
SM		 3920
3921 u8 syndrome[0x20];
3922
b4ff3a36 3923 u8 reserved_at_40[0xa0];
e281682b
SM		 3924
3925 u8 start_flow_index[0x20];
3926
b4ff3a36 3927 u8 reserved_at_100[0x20];
e281682b
SM		 3928
3929 u8 end_flow_index[0x20];
3930
b4ff3a36 3931 u8 reserved_at_140[0xa0];
e281682b 3932
b4ff3a36 3933 u8 reserved_at_1e0[0x18];
e281682b
SM		 3934 u8 match_criteria_enable[0x8];
3935
3936 struct mlx5_ifc_fte_match_param_bits match_criteria;
3937
b4ff3a36 3938 u8 reserved_at_1200[0xe00];
e281682b
SM		 3939};
3940
3941struct mlx5_ifc_query_flow_group_in_bits {
3942 u8 opcode[0x10];
b4ff3a36 3943 u8 reserved_at_10[0x10];
e281682b 3944
b4ff3a36 3945 u8 reserved_at_20[0x10];
e281682b
SM		 3946 u8 op_mod[0x10];
3947
b4ff3a36 3948 u8 reserved_at_40[0x40];
e281682b
SM		 3949
3950 u8 table_type[0x8];
b4ff3a36 3951 u8 reserved_at_88[0x18];
e281682b 3952
b4ff3a36 3953 u8 reserved_at_a0[0x8];
e281682b
SM		 3954 u8 table_id[0x18];
3955
3956 u8 group_id[0x20];
3957
b4ff3a36 3958 u8 reserved_at_e0[0x120];
e281682b
SM		 3959};
3960
9dc0b289
AV		 3961struct mlx5_ifc_query_flow_counter_out_bits {
3962 u8 status[0x8];
3963 u8 reserved_at_8[0x18];
3964
3965 u8 syndrome[0x20];
3966
3967 u8 reserved_at_40[0x40];
3968
3969 struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
3970};
3971
3972struct mlx5_ifc_query_flow_counter_in_bits {
3973 u8 opcode[0x10];
3974 u8 reserved_at_10[0x10];
3975
3976 u8 reserved_at_20[0x10];
3977 u8 op_mod[0x10];
3978
3979 u8 reserved_at_40[0x80];
3980
3981 u8 clear[0x1];
3982 u8 reserved_at_c1[0xf];
3983 u8 num_of_counters[0x10];
3984
3985 u8 reserved_at_e0[0x10];
3986 u8 flow_counter_id[0x10];
3987};
3988
d6666753
SM		 3989struct mlx5_ifc_query_esw_vport_context_out_bits {
3990 u8 status[0x8];
b4ff3a36 3991 u8 reserved_at_8[0x18];
d6666753
SM		 3992
3993 u8 syndrome[0x20];
3994
b4ff3a36 3995 u8 reserved_at_40[0x40];
d6666753
SM		 3996
3997 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
3998};
3999
4000struct mlx5_ifc_query_esw_vport_context_in_bits {
4001 u8 opcode[0x10];
b4ff3a36 4002 u8 reserved_at_10[0x10];
d6666753 4003
b4ff3a36 4004 u8 reserved_at_20[0x10];
d6666753
SM		 4005 u8 op_mod[0x10];
4006
4007 u8 other_vport[0x1];
b4ff3a36 4008 u8 reserved_at_41[0xf];
d6666753
SM		 4009 u8 vport_number[0x10];
4010
b4ff3a36 4011 u8 reserved_at_60[0x20];
d6666753
SM		 4012};
4013
4014struct mlx5_ifc_modify_esw_vport_context_out_bits {
4015 u8 status[0x8];
b4ff3a36 4016 u8 reserved_at_8[0x18];
d6666753
SM		 4017
4018 u8 syndrome[0x20];
4019
b4ff3a36 4020 u8 reserved_at_40[0x40];
d6666753
SM		 4021};
4022
4023struct mlx5_ifc_esw_vport_context_fields_select_bits {
b4ff3a36 4024 u8 reserved_at_0[0x1c];
d6666753
SM		 4025 u8 vport_cvlan_insert[0x1];
4026 u8 vport_svlan_insert[0x1];
4027 u8 vport_cvlan_strip[0x1];
4028 u8 vport_svlan_strip[0x1];
4029};
4030
4031struct mlx5_ifc_modify_esw_vport_context_in_bits {
4032 u8 opcode[0x10];
b4ff3a36 4033 u8 reserved_at_10[0x10];
d6666753 4034
b4ff3a36 4035 u8 reserved_at_20[0x10];
d6666753
SM		 4036 u8 op_mod[0x10];
4037
4038 u8 other_vport[0x1];
b4ff3a36 4039 u8 reserved_at_41[0xf];
d6666753
SM		 4040 u8 vport_number[0x10];
4041
4042 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4043
4044 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4045};
4046
e281682b
SM		 4047struct mlx5_ifc_query_eq_out_bits {
4048 u8 status[0x8];
b4ff3a36 4049 u8 reserved_at_8[0x18];
e281682b
SM		 4050
4051 u8 syndrome[0x20];
4052
b4ff3a36 4053 u8 reserved_at_40[0x40];
e281682b
SM		 4054
4055 struct mlx5_ifc_eqc_bits eq_context_entry;
4056
b4ff3a36 4057 u8 reserved_at_280[0x40];
e281682b
SM		 4058
4059 u8 event_bitmask[0x40];
4060
b4ff3a36 4061 u8 reserved_at_300[0x580];
e281682b
SM		 4062
4063 u8 pas[0][0x40];
4064};
4065
4066struct mlx5_ifc_query_eq_in_bits {
4067 u8 opcode[0x10];
b4ff3a36 4068 u8 reserved_at_10[0x10];
e281682b 4069
b4ff3a36 4070 u8 reserved_at_20[0x10];
e281682b
SM		 4071 u8 op_mod[0x10];
4072
b4ff3a36 4073 u8 reserved_at_40[0x18];
e281682b
SM		 4074 u8 eq_number[0x8];
4075
b4ff3a36 4076 u8 reserved_at_60[0x20];
e281682b
SM		 4077};
4078
4079struct mlx5_ifc_query_dct_out_bits {
4080 u8 status[0x8];
b4ff3a36 4081 u8 reserved_at_8[0x18];
e281682b
SM		 4082
4083 u8 syndrome[0x20];
4084
b4ff3a36 4085 u8 reserved_at_40[0x40];
e281682b
SM		 4086
4087 struct mlx5_ifc_dctc_bits dct_context_entry;
4088
b4ff3a36 4089 u8 reserved_at_280[0x180];
e281682b
SM		 4090};
4091
4092struct mlx5_ifc_query_dct_in_bits {
4093 u8 opcode[0x10];
b4ff3a36 4094 u8 reserved_at_10[0x10];
e281682b 4095
b4ff3a36 4096 u8 reserved_at_20[0x10];
e281682b
SM		 4097 u8 op_mod[0x10];
4098
b4ff3a36 4099 u8 reserved_at_40[0x8];
e281682b
SM		 4100 u8 dctn[0x18];
4101
b4ff3a36 4102 u8 reserved_at_60[0x20];
e281682b
SM		 4103};
4104
4105struct mlx5_ifc_query_cq_out_bits {
4106 u8 status[0x8];
b4ff3a36 4107 u8 reserved_at_8[0x18];
e281682b
SM		 4108
4109 u8 syndrome[0x20];
4110
b4ff3a36 4111 u8 reserved_at_40[0x40];
e281682b
SM		 4112
4113 struct mlx5_ifc_cqc_bits cq_context;
4114
b4ff3a36 4115 u8 reserved_at_280[0x600];
e281682b
SM		 4116
4117 u8 pas[0][0x40];
4118};
4119
4120struct mlx5_ifc_query_cq_in_bits {
4121 u8 opcode[0x10];
b4ff3a36 4122 u8 reserved_at_10[0x10];
e281682b 4123
b4ff3a36 4124 u8 reserved_at_20[0x10];
e281682b
SM		 4125 u8 op_mod[0x10];
4126
b4ff3a36 4127 u8 reserved_at_40[0x8];
e281682b
SM		 4128 u8 cqn[0x18];
4129
b4ff3a36 4130 u8 reserved_at_60[0x20];
e281682b
SM		 4131};
4132
4133struct mlx5_ifc_query_cong_status_out_bits {
4134 u8 status[0x8];
b4ff3a36 4135 u8 reserved_at_8[0x18];
e281682b
SM		 4136
4137 u8 syndrome[0x20];
4138
b4ff3a36 4139 u8 reserved_at_40[0x20];
e281682b
SM		 4140
4141 u8 enable[0x1];
4142 u8 tag_enable[0x1];
b4ff3a36 4143 u8 reserved_at_62[0x1e];
e281682b
SM		 4144};
4145
4146struct mlx5_ifc_query_cong_status_in_bits {
4147 u8 opcode[0x10];
b4ff3a36 4148 u8 reserved_at_10[0x10];
e281682b 4149
b4ff3a36 4150 u8 reserved_at_20[0x10];
e281682b
SM		 4151 u8 op_mod[0x10];
4152
b4ff3a36 4153 u8 reserved_at_40[0x18];
e281682b
SM		 4154 u8 priority[0x4];
4155 u8 cong_protocol[0x4];
4156
b4ff3a36 4157 u8 reserved_at_60[0x20];
e281682b
SM		 4158};
4159
4160struct mlx5_ifc_query_cong_statistics_out_bits {
4161 u8 status[0x8];
b4ff3a36 4162 u8 reserved_at_8[0x18];
e281682b
SM		 4163
4164 u8 syndrome[0x20];
4165
b4ff3a36 4166 u8 reserved_at_40[0x40];
e281682b
SM		 4167
4168 u8 cur_flows[0x20];
4169
4170 u8 sum_flows[0x20];
4171
4172 u8 cnp_ignored_high[0x20];
4173
4174 u8 cnp_ignored_low[0x20];
4175
4176 u8 cnp_handled_high[0x20];
4177
4178 u8 cnp_handled_low[0x20];
4179
b4ff3a36 4180 u8 reserved_at_140[0x100];
e281682b
SM		 4181
4182 u8 time_stamp_high[0x20];
4183
4184 u8 time_stamp_low[0x20];
4185
4186 u8 accumulators_period[0x20];
4187
4188 u8 ecn_marked_roce_packets_high[0x20];
4189
4190 u8 ecn_marked_roce_packets_low[0x20];
4191
4192 u8 cnps_sent_high[0x20];
4193
4194 u8 cnps_sent_low[0x20];
4195
b4ff3a36 4196 u8 reserved_at_320[0x560];
e281682b
SM		 4197};
4198
4199struct mlx5_ifc_query_cong_statistics_in_bits {
4200 u8 opcode[0x10];
b4ff3a36 4201 u8 reserved_at_10[0x10];
e281682b 4202
b4ff3a36 4203 u8 reserved_at_20[0x10];
e281682b
SM		 4204 u8 op_mod[0x10];
4205
4206 u8 clear[0x1];
b4ff3a36 4207 u8 reserved_at_41[0x1f];
e281682b 4208
b4ff3a36 4209 u8 reserved_at_60[0x20];
e281682b
SM		 4210};
4211
4212struct mlx5_ifc_query_cong_params_out_bits {
4213 u8 status[0x8];
b4ff3a36 4214 u8 reserved_at_8[0x18];
e281682b
SM		 4215
4216 u8 syndrome[0x20];
4217
b4ff3a36 4218 u8 reserved_at_40[0x40];
e281682b
SM		 4219
4220 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4221};
4222
4223struct mlx5_ifc_query_cong_params_in_bits {
4224 u8 opcode[0x10];
b4ff3a36 4225 u8 reserved_at_10[0x10];
e281682b 4226
b4ff3a36 4227 u8 reserved_at_20[0x10];
e281682b
SM		 4228 u8 op_mod[0x10];
4229
b4ff3a36 4230 u8 reserved_at_40[0x1c];
e281682b
SM		 4231 u8 cong_protocol[0x4];
4232
b4ff3a36 4233 u8 reserved_at_60[0x20];
e281682b
SM		 4234};
4235
4236struct mlx5_ifc_query_adapter_out_bits {
4237 u8 status[0x8];
b4ff3a36 4238 u8 reserved_at_8[0x18];
e281682b
SM		 4239
4240 u8 syndrome[0x20];
4241
b4ff3a36 4242 u8 reserved_at_40[0x40];
e281682b
SM		 4243
4244 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4245};
4246
4247struct mlx5_ifc_query_adapter_in_bits {
4248 u8 opcode[0x10];
b4ff3a36 4249 u8 reserved_at_10[0x10];
e281682b 4250
b4ff3a36 4251 u8 reserved_at_20[0x10];
e281682b
SM		 4252 u8 op_mod[0x10];
4253
b4ff3a36 4254 u8 reserved_at_40[0x40];
e281682b
SM		 4255};
4256
4257struct mlx5_ifc_qp_2rst_out_bits {
4258 u8 status[0x8];
b4ff3a36 4259 u8 reserved_at_8[0x18];
e281682b
SM		 4260
4261 u8 syndrome[0x20];
4262
b4ff3a36 4263 u8 reserved_at_40[0x40];
e281682b
SM		 4264};
4265
4266struct mlx5_ifc_qp_2rst_in_bits {
4267 u8 opcode[0x10];
b4ff3a36 4268 u8 reserved_at_10[0x10];
e281682b 4269
b4ff3a36 4270 u8 reserved_at_20[0x10];
e281682b
SM		 4271 u8 op_mod[0x10];
4272
b4ff3a36 4273 u8 reserved_at_40[0x8];
e281682b
SM		 4274 u8 qpn[0x18];
4275
b4ff3a36 4276 u8 reserved_at_60[0x20];
e281682b
SM		 4277};
4278
4279struct mlx5_ifc_qp_2err_out_bits {
4280 u8 status[0x8];
b4ff3a36 4281 u8 reserved_at_8[0x18];
e281682b
SM		 4282
4283 u8 syndrome[0x20];
4284
b4ff3a36 4285 u8 reserved_at_40[0x40];
e281682b
SM		 4286};
4287
4288struct mlx5_ifc_qp_2err_in_bits {
4289 u8 opcode[0x10];
b4ff3a36 4290 u8 reserved_at_10[0x10];
e281682b 4291
b4ff3a36 4292 u8 reserved_at_20[0x10];
e281682b
SM		 4293 u8 op_mod[0x10];
4294
b4ff3a36 4295 u8 reserved_at_40[0x8];
e281682b
SM		 4296 u8 qpn[0x18];
4297
b4ff3a36 4298 u8 reserved_at_60[0x20];
e281682b
SM		 4299};
4300
4301struct mlx5_ifc_page_fault_resume_out_bits {
4302 u8 status[0x8];
b4ff3a36 4303 u8 reserved_at_8[0x18];
e281682b
SM		 4304
4305 u8 syndrome[0x20];
4306
b4ff3a36 4307 u8 reserved_at_40[0x40];
e281682b
SM		 4308};
4309
4310struct mlx5_ifc_page_fault_resume_in_bits {
4311 u8 opcode[0x10];
b4ff3a36 4312 u8 reserved_at_10[0x10];
e281682b 4313
b4ff3a36 4314 u8 reserved_at_20[0x10];
e281682b
SM		 4315 u8 op_mod[0x10];
4316
4317 u8 error[0x1];
b4ff3a36 4318 u8 reserved_at_41[0x4];
e281682b
SM		 4319 u8 rdma[0x1];
4320 u8 read_write[0x1];
4321 u8 req_res[0x1];
4322 u8 qpn[0x18];
4323
b4ff3a36 4324 u8 reserved_at_60[0x20];
e281682b
SM		 4325};
4326
4327struct mlx5_ifc_nop_out_bits {
4328 u8 status[0x8];
b4ff3a36 4329 u8 reserved_at_8[0x18];
e281682b
SM		 4330
4331 u8 syndrome[0x20];
4332
b4ff3a36 4333 u8 reserved_at_40[0x40];
e281682b
SM		 4334};
4335
4336struct mlx5_ifc_nop_in_bits {
4337 u8 opcode[0x10];
b4ff3a36 4338 u8 reserved_at_10[0x10];
e281682b 4339
b4ff3a36 4340 u8 reserved_at_20[0x10];
e281682b
SM		 4341 u8 op_mod[0x10];
4342
b4ff3a36 4343 u8 reserved_at_40[0x40];
e281682b
SM		 4344};
4345
4346struct mlx5_ifc_modify_vport_state_out_bits {
4347 u8 status[0x8];
b4ff3a36 4348 u8 reserved_at_8[0x18];
e281682b
SM		 4349
4350 u8 syndrome[0x20];
4351
b4ff3a36 4352 u8 reserved_at_40[0x40];
e281682b
SM		 4353};
4354
4355struct mlx5_ifc_modify_vport_state_in_bits {
4356 u8 opcode[0x10];
b4ff3a36 4357 u8 reserved_at_10[0x10];
e281682b 4358
b4ff3a36 4359 u8 reserved_at_20[0x10];
e281682b
SM		 4360 u8 op_mod[0x10];
4361
4362 u8 other_vport[0x1];
b4ff3a36 4363 u8 reserved_at_41[0xf];
e281682b
SM		 4364 u8 vport_number[0x10];
4365
b4ff3a36 4366 u8 reserved_at_60[0x18];
e281682b 4367 u8 admin_state[0x4];
b4ff3a36 4368 u8 reserved_at_7c[0x4];
e281682b
SM		 4369};
4370
4371struct mlx5_ifc_modify_tis_out_bits {
4372 u8 status[0x8];
b4ff3a36 4373 u8 reserved_at_8[0x18];
e281682b
SM		 4374
4375 u8 syndrome[0x20];
4376
b4ff3a36 4377 u8 reserved_at_40[0x40];
e281682b
SM		 4378};
4379
75850d0b 4380struct mlx5_ifc_modify_tis_bitmask_bits {
b4ff3a36 4381 u8 reserved_at_0[0x20];
75850d0b 4382
b4ff3a36 4383 u8 reserved_at_20[0x1f];
75850d0b 4384 u8 prio[0x1];
4385};
4386
e281682b
SM		 4387struct mlx5_ifc_modify_tis_in_bits {
4388 u8 opcode[0x10];
b4ff3a36 4389 u8 reserved_at_10[0x10];
e281682b 4390
b4ff3a36 4391 u8 reserved_at_20[0x10];
e281682b
SM		 4392 u8 op_mod[0x10];
4393
b4ff3a36 4394 u8 reserved_at_40[0x8];
e281682b
SM		 4395 u8 tisn[0x18];
4396
b4ff3a36 4397 u8 reserved_at_60[0x20];
e281682b 4398
75850d0b 4399 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
e281682b 4400
b4ff3a36 4401 u8 reserved_at_c0[0x40];
e281682b
SM		 4402
4403 struct mlx5_ifc_tisc_bits ctx;
4404};
4405
d9eea403 4406struct mlx5_ifc_modify_tir_bitmask_bits {
b4ff3a36 4407 u8 reserved_at_0[0x20];
d9eea403 4408
b4ff3a36 4409 u8 reserved_at_20[0x1b];
66189961 4410 u8 self_lb_en[0x1];
bdfc028d
TT		 4411 u8 reserved_at_3c[0x1];
4412 u8 hash[0x1];
4413 u8 reserved_at_3e[0x1];
d9eea403
AS		 4414 u8 lro[0x1];
4415};
4416
e281682b
SM		 4417struct mlx5_ifc_modify_tir_out_bits {
4418 u8 status[0x8];
b4ff3a36 4419 u8 reserved_at_8[0x18];
e281682b
SM		 4420
4421 u8 syndrome[0x20];
4422
b4ff3a36 4423 u8 reserved_at_40[0x40];
e281682b
SM		 4424};
4425
4426struct mlx5_ifc_modify_tir_in_bits {
4427 u8 opcode[0x10];
b4ff3a36 4428 u8 reserved_at_10[0x10];
e281682b 4429
b4ff3a36 4430 u8 reserved_at_20[0x10];
e281682b
SM		 4431 u8 op_mod[0x10];
4432
b4ff3a36 4433 u8 reserved_at_40[0x8];
e281682b
SM		 4434 u8 tirn[0x18];
4435
b4ff3a36 4436 u8 reserved_at_60[0x20];
e281682b 4437
d9eea403 4438 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
e281682b 4439
b4ff3a36 4440 u8 reserved_at_c0[0x40];
e281682b
SM		 4441
4442 struct mlx5_ifc_tirc_bits ctx;
4443};
4444
4445struct mlx5_ifc_modify_sq_out_bits {
4446 u8 status[0x8];
b4ff3a36 4447 u8 reserved_at_8[0x18];
e281682b
SM		 4448
4449 u8 syndrome[0x20];
4450
b4ff3a36 4451 u8 reserved_at_40[0x40];
e281682b
SM		 4452};
4453
4454struct mlx5_ifc_modify_sq_in_bits {
4455 u8 opcode[0x10];
b4ff3a36 4456 u8 reserved_at_10[0x10];
e281682b 4457
b4ff3a36 4458 u8 reserved_at_20[0x10];
e281682b
SM		 4459 u8 op_mod[0x10];
4460
4461 u8 sq_state[0x4];
b4ff3a36 4462 u8 reserved_at_44[0x4];
e281682b
SM		 4463 u8 sqn[0x18];
4464
b4ff3a36 4465 u8 reserved_at_60[0x20];
e281682b
SM		 4466
4467 u8 modify_bitmask[0x40];
4468
b4ff3a36 4469 u8 reserved_at_c0[0x40];
e281682b
SM		 4470
4471 struct mlx5_ifc_sqc_bits ctx;
4472};
4473
4474struct mlx5_ifc_modify_rqt_out_bits {
4475 u8 status[0x8];
b4ff3a36 4476 u8 reserved_at_8[0x18];
e281682b
SM		 4477
4478 u8 syndrome[0x20];
4479
b4ff3a36 4480 u8 reserved_at_40[0x40];
e281682b
SM		 4481};
4482
5c50368f 4483struct mlx5_ifc_rqt_bitmask_bits {
b4ff3a36 4484 u8 reserved_at_0[0x20];
5c50368f 4485
b4ff3a36 4486 u8 reserved_at_20[0x1f];
5c50368f
AS		 4487 u8 rqn_list[0x1];
4488};
4489
e281682b
SM		 4490struct mlx5_ifc_modify_rqt_in_bits {
4491 u8 opcode[0x10];
b4ff3a36 4492 u8 reserved_at_10[0x10];
e281682b 4493
b4ff3a36 4494 u8 reserved_at_20[0x10];
e281682b
SM		 4495 u8 op_mod[0x10];
4496
b4ff3a36 4497 u8 reserved_at_40[0x8];
e281682b
SM		 4498 u8 rqtn[0x18];
4499
b4ff3a36 4500 u8 reserved_at_60[0x20];
e281682b 4501
5c50368f 4502 struct mlx5_ifc_rqt_bitmask_bits bitmask;
e281682b 4503
b4ff3a36 4504 u8 reserved_at_c0[0x40];
e281682b
SM		 4505
4506 struct mlx5_ifc_rqtc_bits ctx;
4507};
4508
4509struct mlx5_ifc_modify_rq_out_bits {
4510 u8 status[0x8];
b4ff3a36 4511 u8 reserved_at_8[0x18];
e281682b
SM		 4512
4513 u8 syndrome[0x20];
4514
b4ff3a36 4515 u8 reserved_at_40[0x40];
e281682b
SM		 4516};
4517
4518struct mlx5_ifc_modify_rq_in_bits {
4519 u8 opcode[0x10];
b4ff3a36 4520 u8 reserved_at_10[0x10];
e281682b 4521
b4ff3a36 4522 u8 reserved_at_20[0x10];
e281682b
SM		 4523 u8 op_mod[0x10];
4524
4525 u8 rq_state[0x4];
b4ff3a36 4526 u8 reserved_at_44[0x4];
e281682b
SM		 4527 u8 rqn[0x18];
4528
b4ff3a36 4529 u8 reserved_at_60[0x20];
e281682b
SM		 4530
4531 u8 modify_bitmask[0x40];
4532
b4ff3a36 4533 u8 reserved_at_c0[0x40];
e281682b
SM		 4534
4535 struct mlx5_ifc_rqc_bits ctx;
4536};
4537
4538struct mlx5_ifc_modify_rmp_out_bits {
4539 u8 status[0x8];
b4ff3a36 4540 u8 reserved_at_8[0x18];
e281682b
SM		 4541
4542 u8 syndrome[0x20];
4543
b4ff3a36 4544 u8 reserved_at_40[0x40];
e281682b
SM		 4545};
4546
01949d01 4547struct mlx5_ifc_rmp_bitmask_bits {
b4ff3a36 4548 u8 reserved_at_0[0x20];
01949d01 4549
b4ff3a36 4550 u8 reserved_at_20[0x1f];
01949d01
HA		 4551 u8 lwm[0x1];
4552};
4553
e281682b
SM		 4554struct mlx5_ifc_modify_rmp_in_bits {
4555 u8 opcode[0x10];
b4ff3a36 4556 u8 reserved_at_10[0x10];
e281682b 4557
b4ff3a36 4558 u8 reserved_at_20[0x10];
e281682b
SM		 4559 u8 op_mod[0x10];
4560
4561 u8 rmp_state[0x4];
b4ff3a36 4562 u8 reserved_at_44[0x4];
e281682b
SM		 4563 u8 rmpn[0x18];
4564
b4ff3a36 4565 u8 reserved_at_60[0x20];
e281682b 4566
01949d01 4567 struct mlx5_ifc_rmp_bitmask_bits bitmask;
e281682b 4568
b4ff3a36 4569 u8 reserved_at_c0[0x40];
e281682b
SM		 4570
4571 struct mlx5_ifc_rmpc_bits ctx;
4572};
4573
4574struct mlx5_ifc_modify_nic_vport_context_out_bits {
4575 u8 status[0x8];
b4ff3a36 4576 u8 reserved_at_8[0x18];
e281682b
SM		 4577
4578 u8 syndrome[0x20];
4579
b4ff3a36 4580 u8 reserved_at_40[0x40];
e281682b
SM		 4581};
4582
4583struct mlx5_ifc_modify_nic_vport_field_select_bits {
b4ff3a36 4584 u8 reserved_at_0[0x19];
d82b7318
SM		 4585 u8 mtu[0x1];
4586 u8 change_event[0x1];
4587 u8 promisc[0x1];
e281682b
SM		 4588 u8 permanent_address[0x1];
4589 u8 addresses_list[0x1];
4590 u8 roce_en[0x1];
b4ff3a36 4591 u8 reserved_at_1f[0x1];
e281682b
SM		 4592};
4593
4594struct mlx5_ifc_modify_nic_vport_context_in_bits {
4595 u8 opcode[0x10];
b4ff3a36 4596 u8 reserved_at_10[0x10];
e281682b 4597
b4ff3a36 4598 u8 reserved_at_20[0x10];
e281682b
SM		 4599 u8 op_mod[0x10];
4600
4601 u8 other_vport[0x1];
b4ff3a36 4602 u8 reserved_at_41[0xf];
e281682b
SM		 4603 u8 vport_number[0x10];
4604
4605 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
4606
b4ff3a36 4607 u8 reserved_at_80[0x780];
e281682b
SM		 4608
4609 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4610};
4611
4612struct mlx5_ifc_modify_hca_vport_context_out_bits {
4613 u8 status[0x8];
b4ff3a36 4614 u8 reserved_at_8[0x18];
e281682b
SM		 4615
4616 u8 syndrome[0x20];
4617
b4ff3a36 4618 u8 reserved_at_40[0x40];
e281682b
SM		 4619};
4620
4621struct mlx5_ifc_modify_hca_vport_context_in_bits {
4622 u8 opcode[0x10];
b4ff3a36 4623 u8 reserved_at_10[0x10];
e281682b 4624
b4ff3a36 4625 u8 reserved_at_20[0x10];
e281682b
SM		 4626 u8 op_mod[0x10];
4627
4628 u8 other_vport[0x1];
b4ff3a36 4629 u8 reserved_at_41[0xb];
707c4602 4630 u8 port_num[0x4];
e281682b
SM		 4631 u8 vport_number[0x10];
4632
b4ff3a36 4633 u8 reserved_at_60[0x20];
e281682b
SM		 4634
4635 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4636};
4637
4638struct mlx5_ifc_modify_cq_out_bits {
4639 u8 status[0x8];
b4ff3a36 4640 u8 reserved_at_8[0x18];
e281682b
SM		 4641
4642 u8 syndrome[0x20];
4643
b4ff3a36 4644 u8 reserved_at_40[0x40];
e281682b
SM		 4645};
4646
4647enum {
4648 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
4649 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
4650};
4651
4652struct mlx5_ifc_modify_cq_in_bits {
4653 u8 opcode[0x10];
b4ff3a36 4654 u8 reserved_at_10[0x10];
e281682b 4655
b4ff3a36 4656 u8 reserved_at_20[0x10];
e281682b
SM		 4657 u8 op_mod[0x10];
4658
b4ff3a36 4659 u8 reserved_at_40[0x8];
e281682b
SM		 4660 u8 cqn[0x18];
4661
4662 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
4663
4664 struct mlx5_ifc_cqc_bits cq_context;
4665
b4ff3a36 4666 u8 reserved_at_280[0x600];
e281682b
SM		 4667
4668 u8 pas[0][0x40];
4669};
4670
4671struct mlx5_ifc_modify_cong_status_out_bits {
4672 u8 status[0x8];
b4ff3a36 4673 u8 reserved_at_8[0x18];
e281682b
SM		 4674
4675 u8 syndrome[0x20];
4676
b4ff3a36 4677 u8 reserved_at_40[0x40];
e281682b
SM		 4678};
4679
4680struct mlx5_ifc_modify_cong_status_in_bits {
4681 u8 opcode[0x10];
b4ff3a36 4682 u8 reserved_at_10[0x10];
e281682b 4683
b4ff3a36 4684 u8 reserved_at_20[0x10];
e281682b
SM		 4685 u8 op_mod[0x10];
4686
b4ff3a36 4687 u8 reserved_at_40[0x18];
e281682b
SM		 4688 u8 priority[0x4];
4689 u8 cong_protocol[0x4];
4690
4691 u8 enable[0x1];
4692 u8 tag_enable[0x1];
b4ff3a36 4693 u8 reserved_at_62[0x1e];
e281682b
SM		 4694};
4695
4696struct mlx5_ifc_modify_cong_params_out_bits {
4697 u8 status[0x8];
b4ff3a36 4698 u8 reserved_at_8[0x18];
e281682b
SM		 4699
4700 u8 syndrome[0x20];
4701
b4ff3a36 4702 u8 reserved_at_40[0x40];
e281682b
SM		 4703};
4704
4705struct mlx5_ifc_modify_cong_params_in_bits {
4706 u8 opcode[0x10];
b4ff3a36 4707 u8 reserved_at_10[0x10];
e281682b 4708
b4ff3a36 4709 u8 reserved_at_20[0x10];
e281682b
SM		 4710 u8 op_mod[0x10];
4711
b4ff3a36 4712 u8 reserved_at_40[0x1c];
e281682b
SM		 4713 u8 cong_protocol[0x4];
4714
4715 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
4716
b4ff3a36 4717 u8 reserved_at_80[0x80];
e281682b
SM		 4718
4719 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4720};
4721
4722struct mlx5_ifc_manage_pages_out_bits {
4723 u8 status[0x8];
b4ff3a36 4724 u8 reserved_at_8[0x18];
e281682b
SM		 4725
4726 u8 syndrome[0x20];
4727
4728 u8 output_num_entries[0x20];
4729
b4ff3a36 4730 u8 reserved_at_60[0x20];
e281682b
SM		 4731
4732 u8 pas[0][0x40];
4733};
4734
4735enum {
4736 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
4737 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
4738 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
4739};
4740
4741struct mlx5_ifc_manage_pages_in_bits {
4742 u8 opcode[0x10];
b4ff3a36 4743 u8 reserved_at_10[0x10];
e281682b 4744
b4ff3a36 4745 u8 reserved_at_20[0x10];
e281682b
SM		 4746 u8 op_mod[0x10];
4747
b4ff3a36 4748 u8 reserved_at_40[0x10];
e281682b
SM		 4749 u8 function_id[0x10];
4750
4751 u8 input_num_entries[0x20];
4752
4753 u8 pas[0][0x40];
4754};
4755
4756struct mlx5_ifc_mad_ifc_out_bits {
4757 u8 status[0x8];
b4ff3a36 4758 u8 reserved_at_8[0x18];
e281682b
SM		 4759
4760 u8 syndrome[0x20];
4761
b4ff3a36 4762 u8 reserved_at_40[0x40];
e281682b
SM		 4763
4764 u8 response_mad_packet[256][0x8];
4765};
4766
4767struct mlx5_ifc_mad_ifc_in_bits {
4768 u8 opcode[0x10];
b4ff3a36 4769 u8 reserved_at_10[0x10];
e281682b 4770
b4ff3a36 4771 u8 reserved_at_20[0x10];
e281682b
SM		 4772 u8 op_mod[0x10];
4773
4774 u8 remote_lid[0x10];
b4ff3a36 4775 u8 reserved_at_50[0x8];
e281682b
SM		 4776 u8 port[0x8];
4777
b4ff3a36 4778 u8 reserved_at_60[0x20];
e281682b
SM		 4779
4780 u8 mad[256][0x8];
4781};
4782
4783struct mlx5_ifc_init_hca_out_bits {
4784 u8 status[0x8];
b4ff3a36 4785 u8 reserved_at_8[0x18];
e281682b
SM		 4786
4787 u8 syndrome[0x20];
4788
b4ff3a36 4789 u8 reserved_at_40[0x40];
e281682b
SM		 4790};
4791
4792struct mlx5_ifc_init_hca_in_bits {
4793 u8 opcode[0x10];
b4ff3a36 4794 u8 reserved_at_10[0x10];
e281682b 4795
b4ff3a36 4796 u8 reserved_at_20[0x10];
e281682b
SM		 4797 u8 op_mod[0x10];
4798
b4ff3a36 4799 u8 reserved_at_40[0x40];
e281682b
SM		 4800};
4801
4802struct mlx5_ifc_init2rtr_qp_out_bits {
4803 u8 status[0x8];
b4ff3a36 4804 u8 reserved_at_8[0x18];
e281682b
SM		 4805
4806 u8 syndrome[0x20];
4807
b4ff3a36 4808 u8 reserved_at_40[0x40];
e281682b
SM		 4809};
4810
4811struct mlx5_ifc_init2rtr_qp_in_bits {
4812 u8 opcode[0x10];
b4ff3a36 4813 u8 reserved_at_10[0x10];
e281682b 4814
b4ff3a36 4815 u8 reserved_at_20[0x10];
e281682b
SM		 4816 u8 op_mod[0x10];
4817
b4ff3a36 4818 u8 reserved_at_40[0x8];
e281682b
SM		 4819 u8 qpn[0x18];
4820
b4ff3a36 4821 u8 reserved_at_60[0x20];
e281682b
SM		 4822
4823 u8 opt_param_mask[0x20];
4824
b4ff3a36 4825 u8 reserved_at_a0[0x20];
e281682b
SM		 4826
4827 struct mlx5_ifc_qpc_bits qpc;
4828
b4ff3a36 4829 u8 reserved_at_800[0x80];
e281682b
SM		 4830};
4831
4832struct mlx5_ifc_init2init_qp_out_bits {
4833 u8 status[0x8];
b4ff3a36 4834 u8 reserved_at_8[0x18];
e281682b
SM		 4835
4836 u8 syndrome[0x20];
4837
b4ff3a36 4838 u8 reserved_at_40[0x40];
e281682b
SM		 4839};
4840
4841struct mlx5_ifc_init2init_qp_in_bits {
4842 u8 opcode[0x10];
b4ff3a36 4843 u8 reserved_at_10[0x10];
e281682b 4844
b4ff3a36 4845 u8 reserved_at_20[0x10];
e281682b
SM		 4846 u8 op_mod[0x10];
4847
b4ff3a36 4848 u8 reserved_at_40[0x8];
e281682b
SM		 4849 u8 qpn[0x18];
4850
b4ff3a36 4851 u8 reserved_at_60[0x20];
e281682b
SM		 4852
4853 u8 opt_param_mask[0x20];
4854
b4ff3a36 4855 u8 reserved_at_a0[0x20];
e281682b
SM		 4856
4857 struct mlx5_ifc_qpc_bits qpc;
4858
b4ff3a36 4859 u8 reserved_at_800[0x80];
e281682b
SM		 4860};
4861
4862struct mlx5_ifc_get_dropped_packet_log_out_bits {
4863 u8 status[0x8];
b4ff3a36 4864 u8 reserved_at_8[0x18];
e281682b
SM		 4865
4866 u8 syndrome[0x20];
4867
b4ff3a36 4868 u8 reserved_at_40[0x40];
e281682b
SM		 4869
4870 u8 packet_headers_log[128][0x8];
4871
4872 u8 packet_syndrome[64][0x8];
4873};
4874
4875struct mlx5_ifc_get_dropped_packet_log_in_bits {
4876 u8 opcode[0x10];
b4ff3a36 4877 u8 reserved_at_10[0x10];
e281682b 4878
b4ff3a36 4879 u8 reserved_at_20[0x10];
e281682b
SM		 4880 u8 op_mod[0x10];
4881
b4ff3a36 4882 u8 reserved_at_40[0x40];
e281682b
SM		 4883};
4884
4885struct mlx5_ifc_gen_eqe_in_bits {
4886 u8 opcode[0x10];
b4ff3a36 4887 u8 reserved_at_10[0x10];
e281682b 4888
b4ff3a36 4889 u8 reserved_at_20[0x10];
e281682b
SM		 4890 u8 op_mod[0x10];
4891
b4ff3a36 4892 u8 reserved_at_40[0x18];
e281682b
SM		 4893 u8 eq_number[0x8];
4894
b4ff3a36 4895 u8 reserved_at_60[0x20];
e281682b
SM		 4896
4897 u8 eqe[64][0x8];
4898};
4899
4900struct mlx5_ifc_gen_eq_out_bits {
4901 u8 status[0x8];
b4ff3a36 4902 u8 reserved_at_8[0x18];
e281682b
SM		 4903
4904 u8 syndrome[0x20];
4905
b4ff3a36 4906 u8 reserved_at_40[0x40];
e281682b
SM		 4907};
4908
4909struct mlx5_ifc_enable_hca_out_bits {
4910 u8 status[0x8];
b4ff3a36 4911 u8 reserved_at_8[0x18];
e281682b
SM		 4912
4913 u8 syndrome[0x20];
4914
b4ff3a36 4915 u8 reserved_at_40[0x20];
e281682b
SM		 4916};
4917
4918struct mlx5_ifc_enable_hca_in_bits {
4919 u8 opcode[0x10];
b4ff3a36 4920 u8 reserved_at_10[0x10];
e281682b 4921
b4ff3a36 4922 u8 reserved_at_20[0x10];
e281682b
SM		 4923 u8 op_mod[0x10];
4924
b4ff3a36 4925 u8 reserved_at_40[0x10];
e281682b
SM		 4926 u8 function_id[0x10];
4927
b4ff3a36 4928 u8 reserved_at_60[0x20];
e281682b
SM		 4929};
4930
4931struct mlx5_ifc_drain_dct_out_bits {
4932 u8 status[0x8];
b4ff3a36 4933 u8 reserved_at_8[0x18];
e281682b
SM		 4934
4935 u8 syndrome[0x20];
4936
b4ff3a36 4937 u8 reserved_at_40[0x40];
e281682b
SM		 4938};
4939
4940struct mlx5_ifc_drain_dct_in_bits {
4941 u8 opcode[0x10];
b4ff3a36 4942 u8 reserved_at_10[0x10];
e281682b 4943
b4ff3a36 4944 u8 reserved_at_20[0x10];
e281682b
SM		 4945 u8 op_mod[0x10];
4946
b4ff3a36 4947 u8 reserved_at_40[0x8];
e281682b
SM		 4948 u8 dctn[0x18];
4949
b4ff3a36 4950 u8 reserved_at_60[0x20];
e281682b
SM		 4951};
4952
4953struct mlx5_ifc_disable_hca_out_bits {
4954 u8 status[0x8];
b4ff3a36 4955 u8 reserved_at_8[0x18];
e281682b
SM		 4956
4957 u8 syndrome[0x20];
4958
b4ff3a36 4959 u8 reserved_at_40[0x20];
e281682b
SM		 4960};
4961
4962struct mlx5_ifc_disable_hca_in_bits {
4963 u8 opcode[0x10];
b4ff3a36 4964 u8 reserved_at_10[0x10];
e281682b 4965
b4ff3a36 4966 u8 reserved_at_20[0x10];
e281682b
SM		 4967 u8 op_mod[0x10];
4968
b4ff3a36 4969 u8 reserved_at_40[0x10];
e281682b
SM		 4970 u8 function_id[0x10];
4971
b4ff3a36 4972 u8 reserved_at_60[0x20];
e281682b
SM		 4973};
4974
4975struct mlx5_ifc_detach_from_mcg_out_bits {
4976 u8 status[0x8];
b4ff3a36 4977 u8 reserved_at_8[0x18];
e281682b
SM		 4978
4979 u8 syndrome[0x20];
4980
b4ff3a36 4981 u8 reserved_at_40[0x40];
e281682b
SM		 4982};
4983
4984struct mlx5_ifc_detach_from_mcg_in_bits {
4985 u8 opcode[0x10];
b4ff3a36 4986 u8 reserved_at_10[0x10];
e281682b 4987
b4ff3a36 4988 u8 reserved_at_20[0x10];
e281682b
SM		 4989 u8 op_mod[0x10];
4990
b4ff3a36 4991 u8 reserved_at_40[0x8];
e281682b
SM		 4992 u8 qpn[0x18];
4993
b4ff3a36 4994 u8 reserved_at_60[0x20];
e281682b
SM		 4995
4996 u8 multicast_gid[16][0x8];
4997};
4998
4999struct mlx5_ifc_destroy_xrc_srq_out_bits {
5000 u8 status[0x8];
b4ff3a36 5001 u8 reserved_at_8[0x18];
e281682b
SM		 5002
5003 u8 syndrome[0x20];
5004
b4ff3a36 5005 u8 reserved_at_40[0x40];
e281682b
SM		 5006};
5007
5008struct mlx5_ifc_destroy_xrc_srq_in_bits {
5009 u8 opcode[0x10];
b4ff3a36 5010 u8 reserved_at_10[0x10];
e281682b 5011
b4ff3a36 5012 u8 reserved_at_20[0x10];
e281682b
SM		 5013 u8 op_mod[0x10];
5014
b4ff3a36 5015 u8 reserved_at_40[0x8];
e281682b
SM		 5016 u8 xrc_srqn[0x18];
5017
b4ff3a36 5018 u8 reserved_at_60[0x20];
e281682b
SM		 5019};
5020
5021struct mlx5_ifc_destroy_tis_out_bits {
5022 u8 status[0x8];
b4ff3a36 5023 u8 reserved_at_8[0x18];
e281682b
SM		 5024
5025 u8 syndrome[0x20];
5026
b4ff3a36 5027 u8 reserved_at_40[0x40];
e281682b
SM		 5028};
5029
5030struct mlx5_ifc_destroy_tis_in_bits {
5031 u8 opcode[0x10];
b4ff3a36 5032 u8 reserved_at_10[0x10];
e281682b 5033
b4ff3a36 5034 u8 reserved_at_20[0x10];
e281682b
SM		 5035 u8 op_mod[0x10];
5036
b4ff3a36 5037 u8 reserved_at_40[0x8];
e281682b
SM		 5038 u8 tisn[0x18];
5039
b4ff3a36 5040 u8 reserved_at_60[0x20];
e281682b
SM		 5041};
5042
5043struct mlx5_ifc_destroy_tir_out_bits {
5044 u8 status[0x8];
b4ff3a36 5045 u8 reserved_at_8[0x18];
e281682b
SM		 5046
5047 u8 syndrome[0x20];
5048
b4ff3a36 5049 u8 reserved_at_40[0x40];
e281682b
SM		 5050};
5051
5052struct mlx5_ifc_destroy_tir_in_bits {
5053 u8 opcode[0x10];
b4ff3a36 5054 u8 reserved_at_10[0x10];
e281682b 5055
b4ff3a36 5056 u8 reserved_at_20[0x10];
e281682b
SM		 5057 u8 op_mod[0x10];
5058
b4ff3a36 5059 u8 reserved_at_40[0x8];
e281682b
SM		 5060 u8 tirn[0x18];
5061
b4ff3a36 5062 u8 reserved_at_60[0x20];
e281682b
SM		 5063};
5064
5065struct mlx5_ifc_destroy_srq_out_bits {
5066 u8 status[0x8];
b4ff3a36 5067 u8 reserved_at_8[0x18];
e281682b
SM		 5068
5069 u8 syndrome[0x20];
5070
b4ff3a36 5071 u8 reserved_at_40[0x40];
e281682b
SM		 5072};
5073
5074struct mlx5_ifc_destroy_srq_in_bits {
5075 u8 opcode[0x10];
b4ff3a36 5076 u8 reserved_at_10[0x10];
e281682b 5077
b4ff3a36 5078 u8 reserved_at_20[0x10];
e281682b
SM		 5079 u8 op_mod[0x10];
5080
b4ff3a36 5081 u8 reserved_at_40[0x8];
e281682b
SM		 5082 u8 srqn[0x18];
5083
b4ff3a36 5084 u8 reserved_at_60[0x20];
e281682b
SM		 5085};
5086
5087struct mlx5_ifc_destroy_sq_out_bits {
5088 u8 status[0x8];
b4ff3a36 5089 u8 reserved_at_8[0x18];
e281682b
SM		 5090
5091 u8 syndrome[0x20];
5092
b4ff3a36 5093 u8 reserved_at_40[0x40];
e281682b
SM		 5094};
5095
5096struct mlx5_ifc_destroy_sq_in_bits {
5097 u8 opcode[0x10];
b4ff3a36 5098 u8 reserved_at_10[0x10];
e281682b 5099
b4ff3a36 5100 u8 reserved_at_20[0x10];
e281682b
SM		 5101 u8 op_mod[0x10];
5102
b4ff3a36 5103 u8 reserved_at_40[0x8];
e281682b
SM		 5104 u8 sqn[0x18];
5105
b4ff3a36 5106 u8 reserved_at_60[0x20];
e281682b
SM		 5107};
5108
5109struct mlx5_ifc_destroy_rqt_out_bits {
5110 u8 status[0x8];
b4ff3a36 5111 u8 reserved_at_8[0x18];
e281682b
SM		 5112
5113 u8 syndrome[0x20];
5114
b4ff3a36 5115 u8 reserved_at_40[0x40];
e281682b
SM		 5116};
5117
5118struct mlx5_ifc_destroy_rqt_in_bits {
5119 u8 opcode[0x10];
b4ff3a36 5120 u8 reserved_at_10[0x10];
e281682b 5121
b4ff3a36 5122 u8 reserved_at_20[0x10];
e281682b
SM		 5123 u8 op_mod[0x10];
5124
b4ff3a36 5125 u8 reserved_at_40[0x8];
e281682b
SM		 5126 u8 rqtn[0x18];
5127
b4ff3a36 5128 u8 reserved_at_60[0x20];
e281682b
SM		 5129};
5130
5131struct mlx5_ifc_destroy_rq_out_bits {
5132 u8 status[0x8];
b4ff3a36 5133 u8 reserved_at_8[0x18];
e281682b
SM		 5134
5135 u8 syndrome[0x20];
5136
b4ff3a36 5137 u8 reserved_at_40[0x40];
e281682b
SM		 5138};
5139
5140struct mlx5_ifc_destroy_rq_in_bits {
5141 u8 opcode[0x10];
b4ff3a36 5142 u8 reserved_at_10[0x10];
e281682b 5143
b4ff3a36 5144 u8 reserved_at_20[0x10];
e281682b
SM		 5145 u8 op_mod[0x10];
5146
b4ff3a36 5147 u8 reserved_at_40[0x8];
e281682b
SM		 5148 u8 rqn[0x18];
5149
b4ff3a36 5150 u8 reserved_at_60[0x20];
e281682b
SM		 5151};
5152
5153struct mlx5_ifc_destroy_rmp_out_bits {
5154 u8 status[0x8];
b4ff3a36 5155 u8 reserved_at_8[0x18];
e281682b
SM		 5156
5157 u8 syndrome[0x20];
5158
b4ff3a36 5159 u8 reserved_at_40[0x40];
e281682b
SM		 5160};
5161
5162struct mlx5_ifc_destroy_rmp_in_bits {
5163 u8 opcode[0x10];
b4ff3a36 5164 u8 reserved_at_10[0x10];
e281682b 5165
b4ff3a36 5166 u8 reserved_at_20[0x10];
e281682b
SM		 5167 u8 op_mod[0x10];
5168
b4ff3a36 5169 u8 reserved_at_40[0x8];
e281682b
SM		 5170 u8 rmpn[0x18];
5171
b4ff3a36 5172 u8 reserved_at_60[0x20];
e281682b
SM		 5173};
5174
5175struct mlx5_ifc_destroy_qp_out_bits {
5176 u8 status[0x8];
b4ff3a36 5177 u8 reserved_at_8[0x18];
e281682b
SM		 5178
5179 u8 syndrome[0x20];
5180
b4ff3a36 5181 u8 reserved_at_40[0x40];
e281682b
SM		 5182};
5183
5184struct mlx5_ifc_destroy_qp_in_bits {
5185 u8 opcode[0x10];
b4ff3a36 5186 u8 reserved_at_10[0x10];
e281682b 5187
b4ff3a36 5188 u8 reserved_at_20[0x10];
e281682b
SM		 5189 u8 op_mod[0x10];
5190
b4ff3a36 5191 u8 reserved_at_40[0x8];
e281682b
SM		 5192 u8 qpn[0x18];
5193
b4ff3a36 5194 u8 reserved_at_60[0x20];
e281682b
SM		 5195};
5196
5197struct mlx5_ifc_destroy_psv_out_bits {
5198 u8 status[0x8];
b4ff3a36 5199 u8 reserved_at_8[0x18];
e281682b
SM		 5200
5201 u8 syndrome[0x20];
5202
b4ff3a36 5203 u8 reserved_at_40[0x40];
e281682b
SM		 5204};
5205
5206struct mlx5_ifc_destroy_psv_in_bits {
5207 u8 opcode[0x10];
b4ff3a36 5208 u8 reserved_at_10[0x10];
e281682b 5209
b4ff3a36 5210 u8 reserved_at_20[0x10];
e281682b
SM		 5211 u8 op_mod[0x10];
5212
b4ff3a36 5213 u8 reserved_at_40[0x8];
e281682b
SM		 5214 u8 psvn[0x18];
5215
b4ff3a36 5216 u8 reserved_at_60[0x20];
e281682b
SM		 5217};
5218
5219struct mlx5_ifc_destroy_mkey_out_bits {
5220 u8 status[0x8];
b4ff3a36 5221 u8 reserved_at_8[0x18];
e281682b
SM		 5222
5223 u8 syndrome[0x20];
5224
b4ff3a36 5225 u8 reserved_at_40[0x40];
e281682b
SM		 5226};
5227
5228struct mlx5_ifc_destroy_mkey_in_bits {
5229 u8 opcode[0x10];
b4ff3a36 5230 u8 reserved_at_10[0x10];
e281682b 5231
b4ff3a36 5232 u8 reserved_at_20[0x10];
e281682b
SM		 5233 u8 op_mod[0x10];
5234
b4ff3a36 5235 u8 reserved_at_40[0x8];
e281682b
SM		 5236 u8 mkey_index[0x18];
5237
b4ff3a36 5238 u8 reserved_at_60[0x20];
e281682b
SM		 5239};
5240
5241struct mlx5_ifc_destroy_flow_table_out_bits {
5242 u8 status[0x8];
b4ff3a36 5243 u8 reserved_at_8[0x18];
e281682b
SM		 5244
5245 u8 syndrome[0x20];
5246
b4ff3a36 5247 u8 reserved_at_40[0x40];
e281682b
SM		 5248};
5249
5250struct mlx5_ifc_destroy_flow_table_in_bits {
5251 u8 opcode[0x10];
b4ff3a36 5252 u8 reserved_at_10[0x10];
e281682b 5253
b4ff3a36 5254 u8 reserved_at_20[0x10];
e281682b
SM		 5255 u8 op_mod[0x10];
5256
7d5e1423
SM		 5257 u8 other_vport[0x1];
5258 u8 reserved_at_41[0xf];
5259 u8 vport_number[0x10];
5260
5261 u8 reserved_at_60[0x20];
e281682b
SM		 5262
5263 u8 table_type[0x8];
b4ff3a36 5264 u8 reserved_at_88[0x18];
e281682b 5265
b4ff3a36 5266 u8 reserved_at_a0[0x8];
e281682b
SM		 5267 u8 table_id[0x18];
5268
b4ff3a36 5269 u8 reserved_at_c0[0x140];
e281682b
SM		 5270};
5271
5272struct mlx5_ifc_destroy_flow_group_out_bits {
5273 u8 status[0x8];
b4ff3a36 5274 u8 reserved_at_8[0x18];
e281682b
SM		 5275
5276 u8 syndrome[0x20];
5277
b4ff3a36 5278 u8 reserved_at_40[0x40];
e281682b
SM		 5279};
5280
5281struct mlx5_ifc_destroy_flow_group_in_bits {
5282 u8 opcode[0x10];
b4ff3a36 5283 u8 reserved_at_10[0x10];
e281682b 5284
b4ff3a36 5285 u8 reserved_at_20[0x10];
e281682b
SM		 5286 u8 op_mod[0x10];
5287
7d5e1423
SM		 5288 u8 other_vport[0x1];
5289 u8 reserved_at_41[0xf];
5290 u8 vport_number[0x10];
5291
5292 u8 reserved_at_60[0x20];
e281682b
SM		 5293
5294 u8 table_type[0x8];
b4ff3a36 5295 u8 reserved_at_88[0x18];
e281682b 5296
b4ff3a36 5297 u8 reserved_at_a0[0x8];
e281682b
SM		 5298 u8 table_id[0x18];
5299
5300 u8 group_id[0x20];
5301
b4ff3a36 5302 u8 reserved_at_e0[0x120];
e281682b
SM		 5303};
5304
5305struct mlx5_ifc_destroy_eq_out_bits {
5306 u8 status[0x8];
b4ff3a36 5307 u8 reserved_at_8[0x18];
e281682b
SM		 5308
5309 u8 syndrome[0x20];
5310
b4ff3a36 5311 u8 reserved_at_40[0x40];
e281682b
SM		 5312};
5313
5314struct mlx5_ifc_destroy_eq_in_bits {
5315 u8 opcode[0x10];
b4ff3a36 5316 u8 reserved_at_10[0x10];
e281682b 5317
b4ff3a36 5318 u8 reserved_at_20[0x10];
e281682b
SM		 5319 u8 op_mod[0x10];
5320
b4ff3a36 5321 u8 reserved_at_40[0x18];
e281682b
SM		 5322 u8 eq_number[0x8];
5323
b4ff3a36 5324 u8 reserved_at_60[0x20];
e281682b
SM		 5325};
5326
5327struct mlx5_ifc_destroy_dct_out_bits {
5328 u8 status[0x8];
b4ff3a36 5329 u8 reserved_at_8[0x18];
e281682b
SM		 5330
5331 u8 syndrome[0x20];
5332
b4ff3a36 5333 u8 reserved_at_40[0x40];
e281682b
SM		 5334};
5335
5336struct mlx5_ifc_destroy_dct_in_bits {
5337 u8 opcode[0x10];
b4ff3a36 5338 u8 reserved_at_10[0x10];
e281682b 5339
b4ff3a36 5340 u8 reserved_at_20[0x10];
e281682b
SM		 5341 u8 op_mod[0x10];
5342
b4ff3a36 5343 u8 reserved_at_40[0x8];
e281682b
SM		 5344 u8 dctn[0x18];
5345
b4ff3a36 5346 u8 reserved_at_60[0x20];
e281682b
SM		 5347};
5348
5349struct mlx5_ifc_destroy_cq_out_bits {
5350 u8 status[0x8];
b4ff3a36 5351 u8 reserved_at_8[0x18];
e281682b
SM		 5352
5353 u8 syndrome[0x20];
5354
b4ff3a36 5355 u8 reserved_at_40[0x40];
e281682b
SM		 5356};
5357
5358struct mlx5_ifc_destroy_cq_in_bits {
5359 u8 opcode[0x10];
b4ff3a36 5360 u8 reserved_at_10[0x10];
e281682b 5361
b4ff3a36 5362 u8 reserved_at_20[0x10];
e281682b
SM		 5363 u8 op_mod[0x10];
5364
b4ff3a36 5365 u8 reserved_at_40[0x8];
e281682b
SM		 5366 u8 cqn[0x18];
5367
b4ff3a36 5368 u8 reserved_at_60[0x20];
e281682b
SM		 5369};
5370
5371struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
5372 u8 status[0x8];
b4ff3a36 5373 u8 reserved_at_8[0x18];
e281682b
SM		 5374
5375 u8 syndrome[0x20];
5376
b4ff3a36 5377 u8 reserved_at_40[0x40];
e281682b
SM		 5378};
5379
5380struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
5381 u8 opcode[0x10];
b4ff3a36 5382 u8 reserved_at_10[0x10];
e281682b 5383
b4ff3a36 5384 u8 reserved_at_20[0x10];
e281682b
SM		 5385 u8 op_mod[0x10];
5386
b4ff3a36 5387 u8 reserved_at_40[0x20];
e281682b 5388
b4ff3a36 5389 u8 reserved_at_60[0x10];
e281682b
SM		 5390 u8 vxlan_udp_port[0x10];
5391};
5392
5393struct mlx5_ifc_delete_l2_table_entry_out_bits {
5394 u8 status[0x8];
b4ff3a36 5395 u8 reserved_at_8[0x18];
e281682b
SM		 5396
5397 u8 syndrome[0x20];
5398
b4ff3a36 5399 u8 reserved_at_40[0x40];
e281682b
SM		 5400};
5401
5402struct mlx5_ifc_delete_l2_table_entry_in_bits {
5403 u8 opcode[0x10];
b4ff3a36 5404 u8 reserved_at_10[0x10];
e281682b 5405
b4ff3a36 5406 u8 reserved_at_20[0x10];
e281682b
SM		 5407 u8 op_mod[0x10];
5408
b4ff3a36 5409 u8 reserved_at_40[0x60];
e281682b 5410
b4ff3a36 5411 u8 reserved_at_a0[0x8];
e281682b
SM		 5412 u8 table_index[0x18];
5413
b4ff3a36 5414 u8 reserved_at_c0[0x140];
e281682b
SM		 5415};
5416
5417struct mlx5_ifc_delete_fte_out_bits {
5418 u8 status[0x8];
b4ff3a36 5419 u8 reserved_at_8[0x18];
e281682b
SM		 5420
5421 u8 syndrome[0x20];
5422
b4ff3a36 5423 u8 reserved_at_40[0x40];
e281682b
SM		 5424};
5425
5426struct mlx5_ifc_delete_fte_in_bits {
5427 u8 opcode[0x10];
b4ff3a36 5428 u8 reserved_at_10[0x10];
e281682b 5429
b4ff3a36 5430 u8 reserved_at_20[0x10];
e281682b
SM		 5431 u8 op_mod[0x10];
5432
7d5e1423
SM		 5433 u8 other_vport[0x1];
5434 u8 reserved_at_41[0xf];
5435 u8 vport_number[0x10];
5436
5437 u8 reserved_at_60[0x20];
e281682b
SM		 5438
5439 u8 table_type[0x8];
b4ff3a36 5440 u8 reserved_at_88[0x18];
e281682b 5441
b4ff3a36 5442 u8 reserved_at_a0[0x8];
e281682b
SM		 5443 u8 table_id[0x18];
5444
b4ff3a36 5445 u8 reserved_at_c0[0x40];
e281682b
SM		 5446
5447 u8 flow_index[0x20];
5448
b4ff3a36 5449 u8 reserved_at_120[0xe0];
e281682b
SM		 5450};
5451
5452struct mlx5_ifc_dealloc_xrcd_out_bits {
5453 u8 status[0x8];
b4ff3a36 5454 u8 reserved_at_8[0x18];
e281682b
SM		 5455
5456 u8 syndrome[0x20];
5457
b4ff3a36 5458 u8 reserved_at_40[0x40];
e281682b
SM		 5459};
5460
5461struct mlx5_ifc_dealloc_xrcd_in_bits {
5462 u8 opcode[0x10];
b4ff3a36 5463 u8 reserved_at_10[0x10];
e281682b 5464
b4ff3a36 5465 u8 reserved_at_20[0x10];
e281682b
SM		 5466 u8 op_mod[0x10];
5467
b4ff3a36 5468 u8 reserved_at_40[0x8];
e281682b
SM		 5469 u8 xrcd[0x18];
5470
b4ff3a36 5471 u8 reserved_at_60[0x20];
e281682b
SM		 5472};
5473
5474struct mlx5_ifc_dealloc_uar_out_bits {
5475 u8 status[0x8];
b4ff3a36 5476 u8 reserved_at_8[0x18];
e281682b
SM		 5477
5478 u8 syndrome[0x20];
5479
b4ff3a36 5480 u8 reserved_at_40[0x40];
e281682b
SM		 5481};
5482
5483struct mlx5_ifc_dealloc_uar_in_bits {
5484 u8 opcode[0x10];
b4ff3a36 5485 u8 reserved_at_10[0x10];
e281682b 5486
b4ff3a36 5487 u8 reserved_at_20[0x10];
e281682b
SM		 5488 u8 op_mod[0x10];
5489
b4ff3a36 5490 u8 reserved_at_40[0x8];
e281682b
SM		 5491 u8 uar[0x18];
5492
b4ff3a36 5493 u8 reserved_at_60[0x20];
e281682b
SM		 5494};
5495
5496struct mlx5_ifc_dealloc_transport_domain_out_bits {
5497 u8 status[0x8];
b4ff3a36 5498 u8 reserved_at_8[0x18];
e281682b
SM		 5499
5500 u8 syndrome[0x20];
5501
b4ff3a36 5502 u8 reserved_at_40[0x40];
e281682b
SM		 5503};
5504
5505struct mlx5_ifc_dealloc_transport_domain_in_bits {
5506 u8 opcode[0x10];
b4ff3a36 5507 u8 reserved_at_10[0x10];
e281682b 5508
b4ff3a36 5509 u8 reserved_at_20[0x10];
e281682b
SM		 5510 u8 op_mod[0x10];
5511
b4ff3a36 5512 u8 reserved_at_40[0x8];
e281682b
SM		 5513 u8 transport_domain[0x18];
5514
b4ff3a36 5515 u8 reserved_at_60[0x20];
e281682b
SM		 5516};
5517
5518struct mlx5_ifc_dealloc_q_counter_out_bits {
5519 u8 status[0x8];
b4ff3a36 5520 u8 reserved_at_8[0x18];
e281682b
SM		 5521
5522 u8 syndrome[0x20];
5523
b4ff3a36 5524 u8 reserved_at_40[0x40];
e281682b
SM		 5525};
5526
5527struct mlx5_ifc_dealloc_q_counter_in_bits {
5528 u8 opcode[0x10];
b4ff3a36 5529 u8 reserved_at_10[0x10];
e281682b 5530
b4ff3a36 5531 u8 reserved_at_20[0x10];
e281682b
SM		 5532 u8 op_mod[0x10];
5533
b4ff3a36 5534 u8 reserved_at_40[0x18];
e281682b
SM		 5535 u8 counter_set_id[0x8];
5536
b4ff3a36 5537 u8 reserved_at_60[0x20];
e281682b
SM		 5538};
5539
5540struct mlx5_ifc_dealloc_pd_out_bits {
5541 u8 status[0x8];
b4ff3a36 5542 u8 reserved_at_8[0x18];
e281682b
SM		 5543
5544 u8 syndrome[0x20];
5545
b4ff3a36 5546 u8 reserved_at_40[0x40];
e281682b
SM		 5547};
5548
5549struct mlx5_ifc_dealloc_pd_in_bits {
5550 u8 opcode[0x10];
b4ff3a36 5551 u8 reserved_at_10[0x10];
e281682b 5552
b4ff3a36 5553 u8 reserved_at_20[0x10];
e281682b
SM		 5554 u8 op_mod[0x10];
5555
b4ff3a36 5556 u8 reserved_at_40[0x8];
e281682b
SM		 5557 u8 pd[0x18];
5558
b4ff3a36 5559 u8 reserved_at_60[0x20];
e281682b
SM		 5560};
5561
9dc0b289
AV		 5562struct mlx5_ifc_dealloc_flow_counter_out_bits {
5563 u8 status[0x8];
5564 u8 reserved_at_8[0x18];
5565
5566 u8 syndrome[0x20];
5567
5568 u8 reserved_at_40[0x40];
5569};
5570
5571struct mlx5_ifc_dealloc_flow_counter_in_bits {
5572 u8 opcode[0x10];
5573 u8 reserved_at_10[0x10];
5574
5575 u8 reserved_at_20[0x10];
5576 u8 op_mod[0x10];
5577
5578 u8 reserved_at_40[0x10];
5579 u8 flow_counter_id[0x10];
5580
5581 u8 reserved_at_60[0x20];
5582};
5583
e281682b
SM		 5584struct mlx5_ifc_create_xrc_srq_out_bits {
5585 u8 status[0x8];
b4ff3a36 5586 u8 reserved_at_8[0x18];
e281682b
SM		 5587
5588 u8 syndrome[0x20];
5589
b4ff3a36 5590 u8 reserved_at_40[0x8];
e281682b
SM		 5591 u8 xrc_srqn[0x18];
5592
b4ff3a36 5593 u8 reserved_at_60[0x20];
e281682b
SM		 5594};
5595
5596struct mlx5_ifc_create_xrc_srq_in_bits {
5597 u8 opcode[0x10];
b4ff3a36 5598 u8 reserved_at_10[0x10];
e281682b 5599
b4ff3a36 5600 u8 reserved_at_20[0x10];
e281682b
SM		 5601 u8 op_mod[0x10];
5602
b4ff3a36 5603 u8 reserved_at_40[0x40];
e281682b
SM		 5604
5605 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
5606
b4ff3a36 5607 u8 reserved_at_280[0x600];
e281682b
SM		 5608
5609 u8 pas[0][0x40];
5610};
5611
5612struct mlx5_ifc_create_tis_out_bits {
5613 u8 status[0x8];
b4ff3a36 5614 u8 reserved_at_8[0x18];
e281682b
SM		 5615
5616 u8 syndrome[0x20];
5617
b4ff3a36 5618 u8 reserved_at_40[0x8];
e281682b
SM		 5619 u8 tisn[0x18];
5620
b4ff3a36 5621 u8 reserved_at_60[0x20];
e281682b
SM		 5622};
5623
5624struct mlx5_ifc_create_tis_in_bits {
5625 u8 opcode[0x10];
b4ff3a36 5626 u8 reserved_at_10[0x10];
e281682b 5627
b4ff3a36 5628 u8 reserved_at_20[0x10];
e281682b
SM		 5629 u8 op_mod[0x10];
5630
b4ff3a36 5631 u8 reserved_at_40[0xc0];
e281682b
SM		 5632
5633 struct mlx5_ifc_tisc_bits ctx;
5634};
5635
5636struct mlx5_ifc_create_tir_out_bits {
5637 u8 status[0x8];
b4ff3a36 5638 u8 reserved_at_8[0x18];
e281682b
SM		 5639
5640 u8 syndrome[0x20];
5641
b4ff3a36 5642 u8 reserved_at_40[0x8];
e281682b
SM		 5643 u8 tirn[0x18];
5644
b4ff3a36 5645 u8 reserved_at_60[0x20];
e281682b
SM		 5646};
5647
5648struct mlx5_ifc_create_tir_in_bits {
5649 u8 opcode[0x10];
b4ff3a36 5650 u8 reserved_at_10[0x10];
e281682b 5651
b4ff3a36 5652 u8 reserved_at_20[0x10];
e281682b
SM		 5653 u8 op_mod[0x10];
5654
b4ff3a36 5655 u8 reserved_at_40[0xc0];
e281682b
SM		 5656
5657 struct mlx5_ifc_tirc_bits ctx;
5658};
5659
5660struct mlx5_ifc_create_srq_out_bits {
5661 u8 status[0x8];
b4ff3a36 5662 u8 reserved_at_8[0x18];
e281682b
SM		 5663
5664 u8 syndrome[0x20];
5665
b4ff3a36 5666 u8 reserved_at_40[0x8];
e281682b
SM		 5667 u8 srqn[0x18];
5668
b4ff3a36 5669 u8 reserved_at_60[0x20];
e281682b
SM		 5670};
5671
5672struct mlx5_ifc_create_srq_in_bits {
5673 u8 opcode[0x10];
b4ff3a36 5674 u8 reserved_at_10[0x10];
e281682b 5675
b4ff3a36 5676 u8 reserved_at_20[0x10];
e281682b
SM		 5677 u8 op_mod[0x10];
5678
b4ff3a36 5679 u8 reserved_at_40[0x40];
e281682b
SM		 5680
5681 struct mlx5_ifc_srqc_bits srq_context_entry;
5682
b4ff3a36 5683 u8 reserved_at_280[0x600];
e281682b
SM		 5684
5685 u8 pas[0][0x40];
5686};
5687
5688struct mlx5_ifc_create_sq_out_bits {
5689 u8 status[0x8];
b4ff3a36 5690 u8 reserved_at_8[0x18];
e281682b
SM		 5691
5692 u8 syndrome[0x20];
5693
b4ff3a36 5694 u8 reserved_at_40[0x8];
e281682b
SM		 5695 u8 sqn[0x18];
5696
b4ff3a36 5697 u8 reserved_at_60[0x20];
e281682b
SM		 5698};
5699
5700struct mlx5_ifc_create_sq_in_bits {
5701 u8 opcode[0x10];
b4ff3a36 5702 u8 reserved_at_10[0x10];
e281682b 5703
b4ff3a36 5704 u8 reserved_at_20[0x10];
e281682b
SM		 5705 u8 op_mod[0x10];
5706
b4ff3a36 5707 u8 reserved_at_40[0xc0];
e281682b
SM		 5708
5709 struct mlx5_ifc_sqc_bits ctx;
5710};
5711
5712struct mlx5_ifc_create_rqt_out_bits {
5713 u8 status[0x8];
b4ff3a36 5714 u8 reserved_at_8[0x18];
e281682b
SM		 5715
5716 u8 syndrome[0x20];
5717
b4ff3a36 5718 u8 reserved_at_40[0x8];
e281682b
SM		 5719 u8 rqtn[0x18];
5720
b4ff3a36 5721 u8 reserved_at_60[0x20];
e281682b
SM		 5722};
5723
5724struct mlx5_ifc_create_rqt_in_bits {
5725 u8 opcode[0x10];
b4ff3a36 5726 u8 reserved_at_10[0x10];
e281682b 5727
b4ff3a36 5728 u8 reserved_at_20[0x10];
e281682b
SM		 5729 u8 op_mod[0x10];
5730
b4ff3a36 5731 u8 reserved_at_40[0xc0];
e281682b
SM		 5732
5733 struct mlx5_ifc_rqtc_bits rqt_context;
5734};
5735
5736struct mlx5_ifc_create_rq_out_bits {
5737 u8 status[0x8];
b4ff3a36 5738 u8 reserved_at_8[0x18];
e281682b
SM		 5739
5740 u8 syndrome[0x20];
5741
b4ff3a36 5742 u8 reserved_at_40[0x8];
e281682b
SM		 5743 u8 rqn[0x18];
5744
b4ff3a36 5745 u8 reserved_at_60[0x20];
e281682b
SM		 5746};
5747
5748struct mlx5_ifc_create_rq_in_bits {
5749 u8 opcode[0x10];
b4ff3a36 5750 u8 reserved_at_10[0x10];
e281682b 5751
b4ff3a36 5752 u8 reserved_at_20[0x10];
e281682b
SM		 5753 u8 op_mod[0x10];
5754
b4ff3a36 5755 u8 reserved_at_40[0xc0];
e281682b
SM		 5756
5757 struct mlx5_ifc_rqc_bits ctx;
5758};
5759
5760struct mlx5_ifc_create_rmp_out_bits {
5761 u8 status[0x8];
b4ff3a36 5762 u8 reserved_at_8[0x18];
e281682b
SM		 5763
5764 u8 syndrome[0x20];
5765
b4ff3a36 5766 u8 reserved_at_40[0x8];
e281682b
SM		 5767 u8 rmpn[0x18];
5768
b4ff3a36 5769 u8 reserved_at_60[0x20];
e281682b
SM		 5770};
5771
5772struct mlx5_ifc_create_rmp_in_bits {
5773 u8 opcode[0x10];
b4ff3a36 5774 u8 reserved_at_10[0x10];
e281682b 5775
b4ff3a36 5776 u8 reserved_at_20[0x10];
e281682b
SM		 5777 u8 op_mod[0x10];
5778
b4ff3a36 5779 u8 reserved_at_40[0xc0];
e281682b
SM		 5780
5781 struct mlx5_ifc_rmpc_bits ctx;
5782};
5783
5784struct mlx5_ifc_create_qp_out_bits {
5785 u8 status[0x8];
b4ff3a36 5786 u8 reserved_at_8[0x18];
e281682b
SM		 5787
5788 u8 syndrome[0x20];
5789
b4ff3a36 5790 u8 reserved_at_40[0x8];
e281682b
SM		 5791 u8 qpn[0x18];
5792
b4ff3a36 5793 u8 reserved_at_60[0x20];
e281682b
SM		 5794};
5795
5796struct mlx5_ifc_create_qp_in_bits {
5797 u8 opcode[0x10];
b4ff3a36 5798 u8 reserved_at_10[0x10];
e281682b 5799
b4ff3a36 5800 u8 reserved_at_20[0x10];
e281682b
SM		 5801 u8 op_mod[0x10];
5802
b4ff3a36 5803 u8 reserved_at_40[0x40];
e281682b
SM		 5804
5805 u8 opt_param_mask[0x20];
5806
b4ff3a36 5807 u8 reserved_at_a0[0x20];
e281682b
SM		 5808
5809 struct mlx5_ifc_qpc_bits qpc;
5810
b4ff3a36 5811 u8 reserved_at_800[0x80];
e281682b
SM		 5812
5813 u8 pas[0][0x40];
5814};
5815
5816struct mlx5_ifc_create_psv_out_bits {
5817 u8 status[0x8];
b4ff3a36 5818 u8 reserved_at_8[0x18];
e281682b
SM		 5819
5820 u8 syndrome[0x20];
5821
b4ff3a36 5822 u8 reserved_at_40[0x40];
e281682b 5823
b4ff3a36 5824 u8 reserved_at_80[0x8];
e281682b
SM		 5825 u8 psv0_index[0x18];
5826
b4ff3a36 5827 u8 reserved_at_a0[0x8];
e281682b
SM		 5828 u8 psv1_index[0x18];
5829
b4ff3a36 5830 u8 reserved_at_c0[0x8];
e281682b
SM		 5831 u8 psv2_index[0x18];
5832
b4ff3a36 5833 u8 reserved_at_e0[0x8];
e281682b
SM		 5834 u8 psv3_index[0x18];
5835};
5836
5837struct mlx5_ifc_create_psv_in_bits {
5838 u8 opcode[0x10];
b4ff3a36 5839 u8 reserved_at_10[0x10];
e281682b 5840
b4ff3a36 5841 u8 reserved_at_20[0x10];
e281682b
SM		 5842 u8 op_mod[0x10];
5843
5844 u8 num_psv[0x4];
b4ff3a36 5845 u8 reserved_at_44[0x4];
e281682b
SM		 5846 u8 pd[0x18];
5847
b4ff3a36 5848 u8 reserved_at_60[0x20];
e281682b
SM		 5849};
5850
5851struct mlx5_ifc_create_mkey_out_bits {
5852 u8 status[0x8];
b4ff3a36 5853 u8 reserved_at_8[0x18];
e281682b
SM		 5854
5855 u8 syndrome[0x20];
5856
b4ff3a36 5857 u8 reserved_at_40[0x8];
e281682b
SM		 5858 u8 mkey_index[0x18];
5859
b4ff3a36 5860 u8 reserved_at_60[0x20];
e281682b
SM		 5861};
5862
5863struct mlx5_ifc_create_mkey_in_bits {
5864 u8 opcode[0x10];
b4ff3a36 5865 u8 reserved_at_10[0x10];
e281682b 5866
b4ff3a36 5867 u8 reserved_at_20[0x10];
e281682b
SM		 5868 u8 op_mod[0x10];
5869
b4ff3a36 5870 u8 reserved_at_40[0x20];
e281682b
SM		 5871
5872 u8 pg_access[0x1];
b4ff3a36 5873 u8 reserved_at_61[0x1f];
e281682b
SM		 5874
5875 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5876
b4ff3a36 5877 u8 reserved_at_280[0x80];
e281682b
SM		 5878
5879 u8 translations_octword_actual_size[0x20];
5880
b4ff3a36 5881 u8 reserved_at_320[0x560];
e281682b
SM		 5882
5883 u8 klm_pas_mtt[0][0x20];
5884};
5885
5886struct mlx5_ifc_create_flow_table_out_bits {
5887 u8 status[0x8];
b4ff3a36 5888 u8 reserved_at_8[0x18];
e281682b
SM		 5889
5890 u8 syndrome[0x20];
5891
b4ff3a36 5892 u8 reserved_at_40[0x8];
e281682b
SM		 5893 u8 table_id[0x18];
5894
b4ff3a36 5895 u8 reserved_at_60[0x20];
e281682b
SM		 5896};
5897
5898struct mlx5_ifc_create_flow_table_in_bits {
5899 u8 opcode[0x10];
b4ff3a36 5900 u8 reserved_at_10[0x10];
e281682b 5901
b4ff3a36 5902 u8 reserved_at_20[0x10];
e281682b
SM		 5903 u8 op_mod[0x10];
5904
7d5e1423
SM		 5905 u8 other_vport[0x1];
5906 u8 reserved_at_41[0xf];
5907 u8 vport_number[0x10];
5908
5909 u8 reserved_at_60[0x20];
e281682b
SM		 5910
5911 u8 table_type[0x8];
b4ff3a36 5912 u8 reserved_at_88[0x18];
e281682b 5913
b4ff3a36 5914 u8 reserved_at_a0[0x20];
e281682b 5915
b4ff3a36 5916 u8 reserved_at_c0[0x4];
34a40e68 5917 u8 table_miss_mode[0x4];
e281682b 5918 u8 level[0x8];
b4ff3a36 5919 u8 reserved_at_d0[0x8];
e281682b
SM		 5920 u8 log_size[0x8];
5921
b4ff3a36 5922 u8 reserved_at_e0[0x8];
34a40e68
MG		 5923 u8 table_miss_id[0x18];
5924
b4ff3a36 5925 u8 reserved_at_100[0x100];
e281682b
SM		 5926};
5927
5928struct mlx5_ifc_create_flow_group_out_bits {
5929 u8 status[0x8];
b4ff3a36 5930 u8 reserved_at_8[0x18];
e281682b
SM		 5931
5932 u8 syndrome[0x20];
5933
b4ff3a36 5934 u8 reserved_at_40[0x8];
e281682b
SM		 5935 u8 group_id[0x18];
5936
b4ff3a36 5937 u8 reserved_at_60[0x20];
e281682b
SM		 5938};
5939
5940enum {
5941 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
5942 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
5943 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
5944};
5945
5946struct mlx5_ifc_create_flow_group_in_bits {
5947 u8 opcode[0x10];
b4ff3a36 5948 u8 reserved_at_10[0x10];
e281682b 5949
b4ff3a36 5950 u8 reserved_at_20[0x10];
e281682b
SM		 5951 u8 op_mod[0x10];
5952
7d5e1423
SM		 5953 u8 other_vport[0x1];
5954 u8 reserved_at_41[0xf];
5955 u8 vport_number[0x10];
5956
5957 u8 reserved_at_60[0x20];
e281682b
SM		 5958
5959 u8 table_type[0x8];
b4ff3a36 5960 u8 reserved_at_88[0x18];
e281682b 5961
b4ff3a36 5962 u8 reserved_at_a0[0x8];
e281682b
SM		 5963 u8 table_id[0x18];
5964
b4ff3a36 5965 u8 reserved_at_c0[0x20];
e281682b
SM		 5966
5967 u8 start_flow_index[0x20];
5968
b4ff3a36 5969 u8 reserved_at_100[0x20];
e281682b
SM		 5970
5971 u8 end_flow_index[0x20];
5972
b4ff3a36 5973 u8 reserved_at_140[0xa0];
e281682b 5974
b4ff3a36 5975 u8 reserved_at_1e0[0x18];
e281682b
SM		 5976 u8 match_criteria_enable[0x8];
5977
5978 struct mlx5_ifc_fte_match_param_bits match_criteria;
5979
b4ff3a36 5980 u8 reserved_at_1200[0xe00];
e281682b
SM		 5981};
5982
5983struct mlx5_ifc_create_eq_out_bits {
5984 u8 status[0x8];
b4ff3a36 5985 u8 reserved_at_8[0x18];
e281682b
SM		 5986
5987 u8 syndrome[0x20];
5988
b4ff3a36 5989 u8 reserved_at_40[0x18];
e281682b
SM		 5990 u8 eq_number[0x8];
5991
b4ff3a36 5992 u8 reserved_at_60[0x20];
e281682b
SM		 5993};
5994
5995struct mlx5_ifc_create_eq_in_bits {
5996 u8 opcode[0x10];
b4ff3a36 5997 u8 reserved_at_10[0x10];
e281682b 5998
b4ff3a36 5999 u8 reserved_at_20[0x10];
e281682b
SM		 6000 u8 op_mod[0x10];
6001
b4ff3a36 6002 u8 reserved_at_40[0x40];
e281682b
SM		 6003
6004 struct mlx5_ifc_eqc_bits eq_context_entry;
6005
b4ff3a36 6006 u8 reserved_at_280[0x40];
e281682b
SM		 6007
6008 u8 event_bitmask[0x40];
6009
b4ff3a36 6010 u8 reserved_at_300[0x580];
e281682b
SM		 6011
6012 u8 pas[0][0x40];
6013};
6014
6015struct mlx5_ifc_create_dct_out_bits {
6016 u8 status[0x8];
b4ff3a36 6017 u8 reserved_at_8[0x18];
e281682b
SM		 6018
6019 u8 syndrome[0x20];
6020
b4ff3a36 6021 u8 reserved_at_40[0x8];
e281682b
SM		 6022 u8 dctn[0x18];
6023
b4ff3a36 6024 u8 reserved_at_60[0x20];
e281682b
SM		 6025};
6026
6027struct mlx5_ifc_create_dct_in_bits {
6028 u8 opcode[0x10];
b4ff3a36 6029 u8 reserved_at_10[0x10];
e281682b 6030
b4ff3a36 6031 u8 reserved_at_20[0x10];
e281682b
SM		 6032 u8 op_mod[0x10];
6033
b4ff3a36 6034 u8 reserved_at_40[0x40];
e281682b
SM		 6035
6036 struct mlx5_ifc_dctc_bits dct_context_entry;
6037
b4ff3a36 6038 u8 reserved_at_280[0x180];
e281682b
SM		 6039};
6040
6041struct mlx5_ifc_create_cq_out_bits {
6042 u8 status[0x8];
b4ff3a36 6043 u8 reserved_at_8[0x18];
e281682b
SM		 6044
6045 u8 syndrome[0x20];
6046
b4ff3a36 6047 u8 reserved_at_40[0x8];
e281682b
SM		 6048 u8 cqn[0x18];
6049
b4ff3a36 6050 u8 reserved_at_60[0x20];
e281682b
SM		 6051};
6052
6053struct mlx5_ifc_create_cq_in_bits {
6054 u8 opcode[0x10];
b4ff3a36 6055 u8 reserved_at_10[0x10];
e281682b 6056
b4ff3a36 6057 u8 reserved_at_20[0x10];
e281682b
SM		 6058 u8 op_mod[0x10];
6059
b4ff3a36 6060 u8 reserved_at_40[0x40];
e281682b
SM		 6061
6062 struct mlx5_ifc_cqc_bits cq_context;
6063
b4ff3a36 6064 u8 reserved_at_280[0x600];
e281682b
SM		 6065
6066 u8 pas[0][0x40];
6067};
6068
6069struct mlx5_ifc_config_int_moderation_out_bits {
6070 u8 status[0x8];
b4ff3a36 6071 u8 reserved_at_8[0x18];
e281682b
SM		 6072
6073 u8 syndrome[0x20];
6074
b4ff3a36 6075 u8 reserved_at_40[0x4];
e281682b
SM		 6076 u8 min_delay[0xc];
6077 u8 int_vector[0x10];
6078
b4ff3a36 6079 u8 reserved_at_60[0x20];
e281682b
SM		 6080};
6081
6082enum {
6083 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
6084 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
6085};
6086
6087struct mlx5_ifc_config_int_moderation_in_bits {
6088 u8 opcode[0x10];
b4ff3a36 6089 u8 reserved_at_10[0x10];
e281682b 6090
b4ff3a36 6091 u8 reserved_at_20[0x10];
e281682b
SM		 6092 u8 op_mod[0x10];
6093
b4ff3a36 6094 u8 reserved_at_40[0x4];
e281682b
SM		 6095 u8 min_delay[0xc];
6096 u8 int_vector[0x10];
6097
b4ff3a36 6098 u8 reserved_at_60[0x20];
e281682b
SM		 6099};
6100
6101struct mlx5_ifc_attach_to_mcg_out_bits {
6102 u8 status[0x8];
b4ff3a36 6103 u8 reserved_at_8[0x18];
e281682b
SM		 6104
6105 u8 syndrome[0x20];
6106
b4ff3a36 6107 u8 reserved_at_40[0x40];
e281682b
SM		 6108};
6109
6110struct mlx5_ifc_attach_to_mcg_in_bits {
6111 u8 opcode[0x10];
b4ff3a36 6112 u8 reserved_at_10[0x10];
e281682b 6113
b4ff3a36 6114 u8 reserved_at_20[0x10];
e281682b
SM		 6115 u8 op_mod[0x10];
6116
b4ff3a36 6117 u8 reserved_at_40[0x8];
e281682b
SM		 6118 u8 qpn[0x18];
6119
b4ff3a36 6120 u8 reserved_at_60[0x20];
e281682b
SM		 6121
6122 u8 multicast_gid[16][0x8];
6123};
6124
6125struct mlx5_ifc_arm_xrc_srq_out_bits {
6126 u8 status[0x8];
b4ff3a36 6127 u8 reserved_at_8[0x18];
e281682b
SM		 6128
6129 u8 syndrome[0x20];
6130
b4ff3a36 6131 u8 reserved_at_40[0x40];
e281682b
SM		 6132};
6133
6134enum {
6135 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
6136};
6137
6138struct mlx5_ifc_arm_xrc_srq_in_bits {
6139 u8 opcode[0x10];
b4ff3a36 6140 u8 reserved_at_10[0x10];
e281682b 6141
b4ff3a36 6142 u8 reserved_at_20[0x10];
e281682b
SM		 6143 u8 op_mod[0x10];
6144
b4ff3a36 6145 u8 reserved_at_40[0x8];
e281682b
SM		 6146 u8 xrc_srqn[0x18];
6147
b4ff3a36 6148 u8 reserved_at_60[0x10];
e281682b
SM		 6149 u8 lwm[0x10];
6150};
6151
6152struct mlx5_ifc_arm_rq_out_bits {
6153 u8 status[0x8];
b4ff3a36 6154 u8 reserved_at_8[0x18];
e281682b
SM		 6155
6156 u8 syndrome[0x20];
6157
b4ff3a36 6158 u8 reserved_at_40[0x40];
e281682b
SM		 6159};
6160
6161enum {
6162 MLX5_ARM_RQ_IN_OP_MOD_SRQ_ = 0x1,
6163};
6164
6165struct mlx5_ifc_arm_rq_in_bits {
6166 u8 opcode[0x10];
b4ff3a36 6167 u8 reserved_at_10[0x10];
e281682b 6168
b4ff3a36 6169 u8 reserved_at_20[0x10];
e281682b
SM		 6170 u8 op_mod[0x10];
6171
b4ff3a36 6172 u8 reserved_at_40[0x8];
e281682b
SM		 6173 u8 srq_number[0x18];
6174
b4ff3a36 6175 u8 reserved_at_60[0x10];
e281682b
SM		 6176 u8 lwm[0x10];
6177};
6178
6179struct mlx5_ifc_arm_dct_out_bits {
6180 u8 status[0x8];
b4ff3a36 6181 u8 reserved_at_8[0x18];
e281682b
SM		 6182
6183 u8 syndrome[0x20];
6184
b4ff3a36 6185 u8 reserved_at_40[0x40];
e281682b
SM		 6186};
6187
6188struct mlx5_ifc_arm_dct_in_bits {
6189 u8 opcode[0x10];
b4ff3a36 6190 u8 reserved_at_10[0x10];
e281682b 6191
b4ff3a36 6192 u8 reserved_at_20[0x10];
e281682b
SM		 6193 u8 op_mod[0x10];
6194
b4ff3a36 6195 u8 reserved_at_40[0x8];
e281682b
SM		 6196 u8 dct_number[0x18];
6197
b4ff3a36 6198 u8 reserved_at_60[0x20];
e281682b
SM		 6199};
6200
6201struct mlx5_ifc_alloc_xrcd_out_bits {
6202 u8 status[0x8];
b4ff3a36 6203 u8 reserved_at_8[0x18];
e281682b
SM		 6204
6205 u8 syndrome[0x20];
6206
b4ff3a36 6207 u8 reserved_at_40[0x8];
e281682b
SM		 6208 u8 xrcd[0x18];
6209
b4ff3a36 6210 u8 reserved_at_60[0x20];
e281682b
SM		 6211};
6212
6213struct mlx5_ifc_alloc_xrcd_in_bits {
6214 u8 opcode[0x10];
b4ff3a36 6215 u8 reserved_at_10[0x10];
e281682b 6216
b4ff3a36 6217 u8 reserved_at_20[0x10];
e281682b
SM		 6218 u8 op_mod[0x10];
6219
b4ff3a36 6220 u8 reserved_at_40[0x40];
e281682b
SM		 6221};
6222
6223struct mlx5_ifc_alloc_uar_out_bits {
6224 u8 status[0x8];
b4ff3a36 6225 u8 reserved_at_8[0x18];
e281682b
SM		 6226
6227 u8 syndrome[0x20];
6228
b4ff3a36 6229 u8 reserved_at_40[0x8];
e281682b
SM		 6230 u8 uar[0x18];
6231
b4ff3a36 6232 u8 reserved_at_60[0x20];
e281682b
SM		 6233};
6234
6235struct mlx5_ifc_alloc_uar_in_bits {
6236 u8 opcode[0x10];
b4ff3a36 6237 u8 reserved_at_10[0x10];
e281682b 6238
b4ff3a36 6239 u8 reserved_at_20[0x10];
e281682b
SM		 6240 u8 op_mod[0x10];
6241
b4ff3a36 6242 u8 reserved_at_40[0x40];
e281682b
SM		 6243};
6244
6245struct mlx5_ifc_alloc_transport_domain_out_bits {
6246 u8 status[0x8];
b4ff3a36 6247 u8 reserved_at_8[0x18];
e281682b
SM		 6248
6249 u8 syndrome[0x20];
6250
b4ff3a36 6251 u8 reserved_at_40[0x8];
e281682b
SM		 6252 u8 transport_domain[0x18];
6253
b4ff3a36 6254 u8 reserved_at_60[0x20];
e281682b
SM		 6255};
6256
6257struct mlx5_ifc_alloc_transport_domain_in_bits {
6258 u8 opcode[0x10];
b4ff3a36 6259 u8 reserved_at_10[0x10];
e281682b 6260
b4ff3a36 6261 u8 reserved_at_20[0x10];
e281682b
SM		 6262 u8 op_mod[0x10];
6263
b4ff3a36 6264 u8 reserved_at_40[0x40];
e281682b
SM		 6265};
6266
6267struct mlx5_ifc_alloc_q_counter_out_bits {
6268 u8 status[0x8];
b4ff3a36 6269 u8 reserved_at_8[0x18];
e281682b
SM		 6270
6271 u8 syndrome[0x20];
6272
b4ff3a36 6273 u8 reserved_at_40[0x18];
e281682b
SM		 6274 u8 counter_set_id[0x8];
6275
b4ff3a36 6276 u8 reserved_at_60[0x20];
e281682b
SM		 6277};
6278
6279struct mlx5_ifc_alloc_q_counter_in_bits {
6280 u8 opcode[0x10];
b4ff3a36 6281 u8 reserved_at_10[0x10];
e281682b 6282
b4ff3a36 6283 u8 reserved_at_20[0x10];
e281682b
SM		 6284 u8 op_mod[0x10];
6285
b4ff3a36 6286 u8 reserved_at_40[0x40];
e281682b
SM		 6287};
6288
6289struct mlx5_ifc_alloc_pd_out_bits {
6290 u8 status[0x8];
b4ff3a36 6291 u8 reserved_at_8[0x18];
e281682b
SM		 6292
6293 u8 syndrome[0x20];
6294
b4ff3a36 6295 u8 reserved_at_40[0x8];
e281682b
SM		 6296 u8 pd[0x18];
6297
b4ff3a36 6298 u8 reserved_at_60[0x20];
e281682b
SM		 6299};
6300
6301struct mlx5_ifc_alloc_pd_in_bits {
9dc0b289
AV		 6302 u8 opcode[0x10];
6303 u8 reserved_at_10[0x10];
6304
6305 u8 reserved_at_20[0x10];
6306 u8 op_mod[0x10];
6307
6308 u8 reserved_at_40[0x40];
6309};
6310
6311struct mlx5_ifc_alloc_flow_counter_out_bits {
6312 u8 status[0x8];
6313 u8 reserved_at_8[0x18];
6314
6315 u8 syndrome[0x20];
6316
6317 u8 reserved_at_40[0x10];
6318 u8 flow_counter_id[0x10];
6319
6320 u8 reserved_at_60[0x20];
6321};
6322
6323struct mlx5_ifc_alloc_flow_counter_in_bits {
e281682b 6324 u8 opcode[0x10];
b4ff3a36 6325 u8 reserved_at_10[0x10];
e281682b 6326
b4ff3a36 6327 u8 reserved_at_20[0x10];
e281682b
SM		 6328 u8 op_mod[0x10];
6329
b4ff3a36 6330 u8 reserved_at_40[0x40];
e281682b
SM		 6331};
6332
6333struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
6334 u8 status[0x8];
b4ff3a36 6335 u8 reserved_at_8[0x18];
e281682b
SM		 6336
6337 u8 syndrome[0x20];
6338
b4ff3a36 6339 u8 reserved_at_40[0x40];
e281682b
SM		 6340};
6341
6342struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
6343 u8 opcode[0x10];
b4ff3a36 6344 u8 reserved_at_10[0x10];
e281682b 6345
b4ff3a36 6346 u8 reserved_at_20[0x10];
e281682b
SM		 6347 u8 op_mod[0x10];
6348
b4ff3a36 6349 u8 reserved_at_40[0x20];
e281682b 6350
b4ff3a36 6351 u8 reserved_at_60[0x10];
e281682b
SM		 6352 u8 vxlan_udp_port[0x10];
6353};
6354
6355struct mlx5_ifc_access_register_out_bits {
6356 u8 status[0x8];
b4ff3a36 6357 u8 reserved_at_8[0x18];
e281682b
SM		 6358
6359 u8 syndrome[0x20];
6360
b4ff3a36 6361 u8 reserved_at_40[0x40];
e281682b
SM		 6362
6363 u8 register_data[0][0x20];
6364};
6365
6366enum {
6367 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
6368 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
6369};
6370
6371struct mlx5_ifc_access_register_in_bits {
6372 u8 opcode[0x10];
b4ff3a36 6373 u8 reserved_at_10[0x10];
e281682b 6374
b4ff3a36 6375 u8 reserved_at_20[0x10];
e281682b
SM		 6376 u8 op_mod[0x10];
6377
b4ff3a36 6378 u8 reserved_at_40[0x10];
e281682b
SM		 6379 u8 register_id[0x10];
6380
6381 u8 argument[0x20];
6382
6383 u8 register_data[0][0x20];
6384};
6385
6386struct mlx5_ifc_sltp_reg_bits {
6387 u8 status[0x4];
6388 u8 version[0x4];
6389 u8 local_port[0x8];
6390 u8 pnat[0x2];
b4ff3a36 6391 u8 reserved_at_12[0x2];
e281682b 6392 u8 lane[0x4];
b4ff3a36 6393 u8 reserved_at_18[0x8];
e281682b 6394
b4ff3a36 6395 u8 reserved_at_20[0x20];
e281682b 6396
b4ff3a36 6397 u8 reserved_at_40[0x7];
e281682b
SM		 6398 u8 polarity[0x1];
6399 u8 ob_tap0[0x8];
6400 u8 ob_tap1[0x8];
6401 u8 ob_tap2[0x8];
6402
b4ff3a36 6403 u8 reserved_at_60[0xc];
e281682b
SM		 6404 u8 ob_preemp_mode[0x4];
6405 u8 ob_reg[0x8];
6406 u8 ob_bias[0x8];
6407
b4ff3a36 6408 u8 reserved_at_80[0x20];
e281682b
SM		 6409};
6410
6411struct mlx5_ifc_slrg_reg_bits {
6412 u8 status[0x4];
6413 u8 version[0x4];
6414 u8 local_port[0x8];
6415 u8 pnat[0x2];
b4ff3a36 6416 u8 reserved_at_12[0x2];
e281682b 6417 u8 lane[0x4];
b4ff3a36 6418 u8 reserved_at_18[0x8];
e281682b
SM		 6419
6420 u8 time_to_link_up[0x10];
b4ff3a36 6421 u8 reserved_at_30[0xc];
e281682b
SM		 6422 u8 grade_lane_speed[0x4];
6423
6424 u8 grade_version[0x8];
6425 u8 grade[0x18];
6426
b4ff3a36 6427 u8 reserved_at_60[0x4];
e281682b
SM		 6428 u8 height_grade_type[0x4];
6429 u8 height_grade[0x18];
6430
6431 u8 height_dz[0x10];
6432 u8 height_dv[0x10];
6433
b4ff3a36 6434 u8 reserved_at_a0[0x10];
e281682b
SM		 6435 u8 height_sigma[0x10];
6436
b4ff3a36 6437 u8 reserved_at_c0[0x20];
e281682b 6438
b4ff3a36 6439 u8 reserved_at_e0[0x4];
e281682b
SM		 6440 u8 phase_grade_type[0x4];
6441 u8 phase_grade[0x18];
6442
b4ff3a36 6443 u8 reserved_at_100[0x8];
e281682b 6444 u8 phase_eo_pos[0x8];
b4ff3a36 6445 u8 reserved_at_110[0x8];
e281682b
SM		 6446 u8 phase_eo_neg[0x8];
6447
6448 u8 ffe_set_tested[0x10];
6449 u8 test_errors_per_lane[0x10];
6450};
6451
6452struct mlx5_ifc_pvlc_reg_bits {
b4ff3a36 6453 u8 reserved_at_0[0x8];
e281682b 6454 u8 local_port[0x8];
b4ff3a36 6455 u8 reserved_at_10[0x10];
e281682b 6456
b4ff3a36 6457 u8 reserved_at_20[0x1c];
e281682b
SM		 6458 u8 vl_hw_cap[0x4];
6459
b4ff3a36 6460 u8 reserved_at_40[0x1c];
e281682b
SM		 6461 u8 vl_admin[0x4];
6462
b4ff3a36 6463 u8 reserved_at_60[0x1c];
e281682b
SM		 6464 u8 vl_operational[0x4];
6465};
6466
6467struct mlx5_ifc_pude_reg_bits {
6468 u8 swid[0x8];
6469 u8 local_port[0x8];
b4ff3a36 6470 u8 reserved_at_10[0x4];
e281682b 6471 u8 admin_status[0x4];
b4ff3a36 6472 u8 reserved_at_18[0x4];
e281682b
SM		 6473 u8 oper_status[0x4];
6474
b4ff3a36 6475 u8 reserved_at_20[0x60];
e281682b
SM		 6476};
6477
6478struct mlx5_ifc_ptys_reg_bits {
b4ff3a36 6479 u8 reserved_at_0[0x8];
e281682b 6480 u8 local_port[0x8];
b4ff3a36 6481 u8 reserved_at_10[0xd];
e281682b
SM		 6482 u8 proto_mask[0x3];
6483
b4ff3a36 6484 u8 reserved_at_20[0x40];
e281682b
SM		 6485
6486 u8 eth_proto_capability[0x20];
6487
6488 u8 ib_link_width_capability[0x10];
6489 u8 ib_proto_capability[0x10];
6490
b4ff3a36 6491 u8 reserved_at_a0[0x20];
e281682b
SM		 6492
6493 u8 eth_proto_admin[0x20];
6494
6495 u8 ib_link_width_admin[0x10];
6496 u8 ib_proto_admin[0x10];
6497
b4ff3a36 6498 u8 reserved_at_100[0x20];
e281682b
SM		 6499
6500 u8 eth_proto_oper[0x20];
6501
6502 u8 ib_link_width_oper[0x10];
6503 u8 ib_proto_oper[0x10];
6504
b4ff3a36 6505 u8 reserved_at_160[0x20];
e281682b
SM		 6506
6507 u8 eth_proto_lp_advertise[0x20];
6508
b4ff3a36 6509 u8 reserved_at_1a0[0x60];
e281682b
SM		 6510};
6511
7d5e1423
SM		 6512struct mlx5_ifc_mlcr_reg_bits {
6513 u8 reserved_at_0[0x8];
6514 u8 local_port[0x8];
6515 u8 reserved_at_10[0x20];
6516
6517 u8 beacon_duration[0x10];
6518 u8 reserved_at_40[0x10];
6519
6520 u8 beacon_remain[0x10];
6521};
6522
e281682b 6523struct mlx5_ifc_ptas_reg_bits {
b4ff3a36 6524 u8 reserved_at_0[0x20];
e281682b
SM		 6525
6526 u8 algorithm_options[0x10];
b4ff3a36 6527 u8 reserved_at_30[0x4];
e281682b
SM		 6528 u8 repetitions_mode[0x4];
6529 u8 num_of_repetitions[0x8];
6530
6531 u8 grade_version[0x8];
6532 u8 height_grade_type[0x4];
6533 u8 phase_grade_type[0x4];
6534 u8 height_grade_weight[0x8];
6535 u8 phase_grade_weight[0x8];
6536
6537 u8 gisim_measure_bits[0x10];
6538 u8 adaptive_tap_measure_bits[0x10];
6539
6540 u8 ber_bath_high_error_threshold[0x10];
6541 u8 ber_bath_mid_error_threshold[0x10];
6542
6543 u8 ber_bath_low_error_threshold[0x10];
6544 u8 one_ratio_high_threshold[0x10];
6545
6546 u8 one_ratio_high_mid_threshold[0x10];
6547 u8 one_ratio_low_mid_threshold[0x10];
6548
6549 u8 one_ratio_low_threshold[0x10];
6550 u8 ndeo_error_threshold[0x10];
6551
6552 u8 mixer_offset_step_size[0x10];
b4ff3a36 6553 u8 reserved_at_110[0x8];
e281682b
SM		 6554 u8 mix90_phase_for_voltage_bath[0x8];
6555
6556 u8 mixer_offset_start[0x10];
6557 u8 mixer_offset_end[0x10];
6558
b4ff3a36 6559 u8 reserved_at_140[0x15];
e281682b
SM		 6560 u8 ber_test_time[0xb];
6561};
6562
6563struct mlx5_ifc_pspa_reg_bits {
6564 u8 swid[0x8];
6565 u8 local_port[0x8];
6566 u8 sub_port[0x8];
b4ff3a36 6567 u8 reserved_at_18[0x8];
e281682b 6568
b4ff3a36 6569 u8 reserved_at_20[0x20];
e281682b
SM		 6570};
6571
6572struct mlx5_ifc_pqdr_reg_bits {
b4ff3a36 6573 u8 reserved_at_0[0x8];
e281682b 6574 u8 local_port[0x8];
b4ff3a36 6575 u8 reserved_at_10[0x5];
e281682b 6576 u8 prio[0x3];
b4ff3a36 6577 u8 reserved_at_18[0x6];
e281682b
SM		 6578 u8 mode[0x2];
6579
b4ff3a36 6580 u8 reserved_at_20[0x20];
e281682b 6581
b4ff3a36 6582 u8 reserved_at_40[0x10];
e281682b
SM		 6583 u8 min_threshold[0x10];
6584
b4ff3a36 6585 u8 reserved_at_60[0x10];
e281682b
SM		 6586 u8 max_threshold[0x10];
6587
b4ff3a36 6588 u8 reserved_at_80[0x10];
e281682b
SM		 6589 u8 mark_probability_denominator[0x10];
6590
b4ff3a36 6591 u8 reserved_at_a0[0x60];
e281682b
SM		 6592};
6593
6594struct mlx5_ifc_ppsc_reg_bits {
b4ff3a36 6595 u8 reserved_at_0[0x8];
e281682b 6596 u8 local_port[0x8];
b4ff3a36 6597 u8 reserved_at_10[0x10];
e281682b 6598
b4ff3a36 6599 u8 reserved_at_20[0x60];
e281682b 6600
b4ff3a36 6601 u8 reserved_at_80[0x1c];
e281682b
SM		 6602 u8 wrps_admin[0x4];
6603
b4ff3a36 6604 u8 reserved_at_a0[0x1c];
e281682b
SM		 6605 u8 wrps_status[0x4];
6606
b4ff3a36 6607 u8 reserved_at_c0[0x8];
e281682b 6608 u8 up_threshold[0x8];
b4ff3a36 6609 u8 reserved_at_d0[0x8];
e281682b
SM		 6610 u8 down_threshold[0x8];
6611
b4ff3a36 6612 u8 reserved_at_e0[0x20];
e281682b 6613
b4ff3a36 6614 u8 reserved_at_100[0x1c];
e281682b
SM		 6615 u8 srps_admin[0x4];
6616
b4ff3a36 6617 u8 reserved_at_120[0x1c];
e281682b
SM		 6618 u8 srps_status[0x4];
6619
b4ff3a36 6620 u8 reserved_at_140[0x40];
e281682b
SM		 6621};
6622
6623struct mlx5_ifc_pplr_reg_bits {
b4ff3a36 6624 u8 reserved_at_0[0x8];
e281682b 6625 u8 local_port[0x8];
b4ff3a36 6626 u8 reserved_at_10[0x10];
e281682b 6627
b4ff3a36 6628 u8 reserved_at_20[0x8];
e281682b 6629 u8 lb_cap[0x8];
b4ff3a36 6630 u8 reserved_at_30[0x8];
e281682b
SM		 6631 u8 lb_en[0x8];
6632};
6633
6634struct mlx5_ifc_pplm_reg_bits {
b4ff3a36 6635 u8 reserved_at_0[0x8];
e281682b 6636 u8 local_port[0x8];
b4ff3a36 6637 u8 reserved_at_10[0x10];
e281682b 6638
b4ff3a36 6639 u8 reserved_at_20[0x20];
e281682b
SM		 6640
6641 u8 port_profile_mode[0x8];
6642 u8 static_port_profile[0x8];
6643 u8 active_port_profile[0x8];
b4ff3a36 6644 u8 reserved_at_58[0x8];
e281682b
SM		 6645
6646 u8 retransmission_active[0x8];
6647 u8 fec_mode_active[0x18];
6648
b4ff3a36 6649 u8 reserved_at_80[0x20];
e281682b
SM		 6650};
6651
6652struct mlx5_ifc_ppcnt_reg_bits {
6653 u8 swid[0x8];
6654 u8 local_port[0x8];
6655 u8 pnat[0x2];
b4ff3a36 6656 u8 reserved_at_12[0x8];
e281682b
SM		 6657 u8 grp[0x6];
6658
6659 u8 clr[0x1];
b4ff3a36 6660 u8 reserved_at_21[0x1c];
e281682b
SM		 6661 u8 prio_tc[0x3];
6662
6663 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
6664};
6665
6666struct mlx5_ifc_ppad_reg_bits {
b4ff3a36 6667 u8 reserved_at_0[0x3];
e281682b 6668 u8 single_mac[0x1];
b4ff3a36 6669 u8 reserved_at_4[0x4];
e281682b
SM		 6670 u8 local_port[0x8];
6671 u8 mac_47_32[0x10];
6672
6673 u8 mac_31_0[0x20];
6674
b4ff3a36 6675 u8 reserved_at_40[0x40];
e281682b
SM		 6676};
6677
6678struct mlx5_ifc_pmtu_reg_bits {
b4ff3a36 6679 u8 reserved_at_0[0x8];
e281682b 6680 u8 local_port[0x8];
b4ff3a36 6681 u8 reserved_at_10[0x10];
e281682b
SM		 6682
6683 u8 max_mtu[0x10];
b4ff3a36 6684 u8 reserved_at_30[0x10];
e281682b
SM		 6685
6686 u8 admin_mtu[0x10];
b4ff3a36 6687 u8 reserved_at_50[0x10];
e281682b
SM		 6688
6689 u8 oper_mtu[0x10];
b4ff3a36 6690 u8 reserved_at_70[0x10];
e281682b
SM		 6691};
6692
6693struct mlx5_ifc_pmpr_reg_bits {
b4ff3a36 6694 u8 reserved_at_0[0x8];
e281682b 6695 u8 module[0x8];
b4ff3a36 6696 u8 reserved_at_10[0x10];
e281682b 6697
b4ff3a36 6698 u8 reserved_at_20[0x18];
e281682b
SM		 6699 u8 attenuation_5g[0x8];
6700
b4ff3a36 6701 u8 reserved_at_40[0x18];
e281682b
SM		 6702 u8 attenuation_7g[0x8];
6703
b4ff3a36 6704 u8 reserved_at_60[0x18];
e281682b
SM		 6705 u8 attenuation_12g[0x8];
6706};
6707
6708struct mlx5_ifc_pmpe_reg_bits {
b4ff3a36 6709 u8 reserved_at_0[0x8];
e281682b 6710 u8 module[0x8];
b4ff3a36 6711 u8 reserved_at_10[0xc];
e281682b
SM		 6712 u8 module_status[0x4];
6713
b4ff3a36 6714 u8 reserved_at_20[0x60];
e281682b
SM		 6715};
6716
6717struct mlx5_ifc_pmpc_reg_bits {
6718 u8 module_state_updated[32][0x8];
6719};
6720
6721struct mlx5_ifc_pmlpn_reg_bits {
b4ff3a36 6722 u8 reserved_at_0[0x4];
e281682b
SM		 6723 u8 mlpn_status[0x4];
6724 u8 local_port[0x8];
b4ff3a36 6725 u8 reserved_at_10[0x10];
e281682b
SM		 6726
6727 u8 e[0x1];
b4ff3a36 6728 u8 reserved_at_21[0x1f];
e281682b
SM		 6729};
6730
6731struct mlx5_ifc_pmlp_reg_bits {
6732 u8 rxtx[0x1];
b4ff3a36 6733 u8 reserved_at_1[0x7];
e281682b 6734 u8 local_port[0x8];
b4ff3a36 6735 u8 reserved_at_10[0x8];
e281682b
SM		 6736 u8 width[0x8];
6737
6738 u8 lane0_module_mapping[0x20];
6739
6740 u8 lane1_module_mapping[0x20];
6741
6742 u8 lane2_module_mapping[0x20];
6743
6744 u8 lane3_module_mapping[0x20];
6745
b4ff3a36 6746 u8 reserved_at_a0[0x160];
e281682b
SM		 6747};
6748
6749struct mlx5_ifc_pmaos_reg_bits {
b4ff3a36 6750 u8 reserved_at_0[0x8];
e281682b 6751 u8 module[0x8];
b4ff3a36 6752 u8 reserved_at_10[0x4];
e281682b 6753 u8 admin_status[0x4];
b4ff3a36 6754 u8 reserved_at_18[0x4];
e281682b
SM		 6755 u8 oper_status[0x4];
6756
6757 u8 ase[0x1];
6758 u8 ee[0x1];
b4ff3a36 6759 u8 reserved_at_22[0x1c];
e281682b
SM		 6760 u8 e[0x2];
6761
b4ff3a36 6762 u8 reserved_at_40[0x40];
e281682b
SM		 6763};
6764
6765struct mlx5_ifc_plpc_reg_bits {
b4ff3a36 6766 u8 reserved_at_0[0x4];
e281682b 6767 u8 profile_id[0xc];
b4ff3a36 6768 u8 reserved_at_10[0x4];
e281682b 6769 u8 proto_mask[0x4];
b4ff3a36 6770 u8 reserved_at_18[0x8];
e281682b 6771
b4ff3a36 6772 u8 reserved_at_20[0x10];
e281682b
SM		 6773 u8 lane_speed[0x10];
6774
b4ff3a36 6775 u8 reserved_at_40[0x17];
e281682b
SM		 6776 u8 lpbf[0x1];
6777 u8 fec_mode_policy[0x8];
6778
6779 u8 retransmission_capability[0x8];
6780 u8 fec_mode_capability[0x18];
6781
6782 u8 retransmission_support_admin[0x8];
6783 u8 fec_mode_support_admin[0x18];
6784
6785 u8 retransmission_request_admin[0x8];
6786 u8 fec_mode_request_admin[0x18];
6787
b4ff3a36 6788 u8 reserved_at_c0[0x80];
e281682b
SM		 6789};
6790
6791struct mlx5_ifc_plib_reg_bits {
b4ff3a36 6792 u8 reserved_at_0[0x8];
e281682b 6793 u8 local_port[0x8];
b4ff3a36 6794 u8 reserved_at_10[0x8];
e281682b
SM		 6795 u8 ib_port[0x8];
6796
b4ff3a36 6797 u8 reserved_at_20[0x60];
e281682b
SM		 6798};
6799
6800struct mlx5_ifc_plbf_reg_bits {
b4ff3a36 6801 u8 reserved_at_0[0x8];
e281682b 6802 u8 local_port[0x8];
b4ff3a36 6803 u8 reserved_at_10[0xd];
e281682b
SM		 6804 u8 lbf_mode[0x3];
6805
b4ff3a36 6806 u8 reserved_at_20[0x20];
e281682b
SM		 6807};
6808
6809struct mlx5_ifc_pipg_reg_bits {
b4ff3a36 6810 u8 reserved_at_0[0x8];
e281682b 6811 u8 local_port[0x8];
b4ff3a36 6812 u8 reserved_at_10[0x10];
e281682b
SM		 6813
6814 u8 dic[0x1];
b4ff3a36 6815 u8 reserved_at_21[0x19];
e281682b 6816 u8 ipg[0x4];
b4ff3a36 6817 u8 reserved_at_3e[0x2];
e281682b
SM		 6818};
6819
6820struct mlx5_ifc_pifr_reg_bits {
b4ff3a36 6821 u8 reserved_at_0[0x8];
e281682b 6822 u8 local_port[0x8];
b4ff3a36 6823 u8 reserved_at_10[0x10];
e281682b 6824
b4ff3a36 6825 u8 reserved_at_20[0xe0];
e281682b
SM		 6826
6827 u8 port_filter[8][0x20];
6828
6829 u8 port_filter_update_en[8][0x20];
6830};
6831
6832struct mlx5_ifc_pfcc_reg_bits {
b4ff3a36 6833 u8 reserved_at_0[0x8];
e281682b 6834 u8 local_port[0x8];
b4ff3a36 6835 u8 reserved_at_10[0x10];
e281682b
SM		 6836
6837 u8 ppan[0x4];
b4ff3a36 6838 u8 reserved_at_24[0x4];
e281682b 6839 u8 prio_mask_tx[0x8];
b4ff3a36 6840 u8 reserved_at_30[0x8];
e281682b
SM		 6841 u8 prio_mask_rx[0x8];
6842
6843 u8 pptx[0x1];
6844 u8 aptx[0x1];
b4ff3a36 6845 u8 reserved_at_42[0x6];
e281682b 6846 u8 pfctx[0x8];
b4ff3a36 6847 u8 reserved_at_50[0x10];
e281682b
SM		 6848
6849 u8 pprx[0x1];
6850 u8 aprx[0x1];
b4ff3a36 6851 u8 reserved_at_62[0x6];
e281682b 6852 u8 pfcrx[0x8];
b4ff3a36 6853 u8 reserved_at_70[0x10];
e281682b 6854
b4ff3a36 6855 u8 reserved_at_80[0x80];
e281682b
SM		 6856};
6857
6858struct mlx5_ifc_pelc_reg_bits {
6859 u8 op[0x4];
b4ff3a36 6860 u8 reserved_at_4[0x4];
e281682b 6861 u8 local_port[0x8];
b4ff3a36 6862 u8 reserved_at_10[0x10];
e281682b
SM		 6863
6864 u8 op_admin[0x8];
6865 u8 op_capability[0x8];
6866 u8 op_request[0x8];
6867 u8 op_active[0x8];
6868
6869 u8 admin[0x40];
6870
6871 u8 capability[0x40];
6872
6873 u8 request[0x40];
6874
6875 u8 active[0x40];
6876
b4ff3a36 6877 u8 reserved_at_140[0x80];
e281682b
SM		 6878};
6879
6880struct mlx5_ifc_peir_reg_bits {
b4ff3a36 6881 u8 reserved_at_0[0x8];
e281682b 6882 u8 local_port[0x8];
b4ff3a36 6883 u8 reserved_at_10[0x10];
e281682b 6884
b4ff3a36 6885 u8 reserved_at_20[0xc];
e281682b 6886 u8 error_count[0x4];
b4ff3a36 6887 u8 reserved_at_30[0x10];
e281682b 6888
b4ff3a36 6889 u8 reserved_at_40[0xc];
e281682b 6890 u8 lane[0x4];
b4ff3a36 6891 u8 reserved_at_50[0x8];
e281682b
SM		 6892 u8 error_type[0x8];
6893};
6894
6895struct mlx5_ifc_pcap_reg_bits {
b4ff3a36 6896 u8 reserved_at_0[0x8];
e281682b 6897 u8 local_port[0x8];
b4ff3a36 6898 u8 reserved_at_10[0x10];
e281682b
SM		 6899
6900 u8 port_capability_mask[4][0x20];
6901};
6902
6903struct mlx5_ifc_paos_reg_bits {
6904 u8 swid[0x8];
6905 u8 local_port[0x8];
b4ff3a36 6906 u8 reserved_at_10[0x4];
e281682b 6907 u8 admin_status[0x4];
b4ff3a36 6908 u8 reserved_at_18[0x4];
e281682b
SM		 6909 u8 oper_status[0x4];
6910
6911 u8 ase[0x1];
6912 u8 ee[0x1];
b4ff3a36 6913 u8 reserved_at_22[0x1c];
e281682b
SM		 6914 u8 e[0x2];
6915
b4ff3a36 6916 u8 reserved_at_40[0x40];
e281682b
SM		 6917};
6918
6919struct mlx5_ifc_pamp_reg_bits {
b4ff3a36 6920 u8 reserved_at_0[0x8];
e281682b 6921 u8 opamp_group[0x8];
b4ff3a36 6922 u8 reserved_at_10[0xc];
e281682b
SM		 6923 u8 opamp_group_type[0x4];
6924
6925 u8 start_index[0x10];
b4ff3a36 6926 u8 reserved_at_30[0x4];
e281682b
SM		 6927 u8 num_of_indices[0xc];
6928
6929 u8 index_data[18][0x10];
6930};
6931
7d5e1423
SM		 6932struct mlx5_ifc_pcmr_reg_bits {
6933 u8 reserved_at_0[0x8];
6934 u8 local_port[0x8];
6935 u8 reserved_at_10[0x2e];
6936 u8 fcs_cap[0x1];
6937 u8 reserved_at_3f[0x1f];
6938 u8 fcs_chk[0x1];
6939 u8 reserved_at_5f[0x1];
6940};
6941
e281682b 6942struct mlx5_ifc_lane_2_module_mapping_bits {
b4ff3a36 6943 u8 reserved_at_0[0x6];
e281682b 6944 u8 rx_lane[0x2];
b4ff3a36 6945 u8 reserved_at_8[0x6];
e281682b 6946 u8 tx_lane[0x2];
b4ff3a36 6947 u8 reserved_at_10[0x8];
e281682b
SM		 6948 u8 module[0x8];
6949};
6950
6951struct mlx5_ifc_bufferx_reg_bits {
b4ff3a36 6952 u8 reserved_at_0[0x6];
e281682b
SM		 6953 u8 lossy[0x1];
6954 u8 epsb[0x1];
b4ff3a36 6955 u8 reserved_at_8[0xc];
e281682b
SM		 6956 u8 size[0xc];
6957
6958 u8 xoff_threshold[0x10];
6959 u8 xon_threshold[0x10];
6960};
6961
6962struct mlx5_ifc_set_node_in_bits {
6963 u8 node_description[64][0x8];
6964};
6965
6966struct mlx5_ifc_register_power_settings_bits {
b4ff3a36 6967 u8 reserved_at_0[0x18];
e281682b
SM		 6968 u8 power_settings_level[0x8];
6969
b4ff3a36 6970 u8 reserved_at_20[0x60];
e281682b
SM		 6971};
6972
6973struct mlx5_ifc_register_host_endianness_bits {
6974 u8 he[0x1];
b4ff3a36 6975 u8 reserved_at_1[0x1f];
e281682b 6976
b4ff3a36 6977 u8 reserved_at_20[0x60];
e281682b
SM		 6978};
6979
6980struct mlx5_ifc_umr_pointer_desc_argument_bits {
b4ff3a36 6981 u8 reserved_at_0[0x20];
e281682b
SM		 6982
6983 u8 mkey[0x20];
6984
6985 u8 addressh_63_32[0x20];
6986
6987 u8 addressl_31_0[0x20];
6988};
6989
6990struct mlx5_ifc_ud_adrs_vector_bits {
6991 u8 dc_key[0x40];
6992
6993 u8 ext[0x1];
b4ff3a36 6994 u8 reserved_at_41[0x7];
e281682b
SM		 6995 u8 destination_qp_dct[0x18];
6996
6997 u8 static_rate[0x4];
6998 u8 sl_eth_prio[0x4];
6999 u8 fl[0x1];
7000 u8 mlid[0x7];
7001 u8 rlid_udp_sport[0x10];
7002
b4ff3a36 7003 u8 reserved_at_80[0x20];
e281682b
SM		 7004
7005 u8 rmac_47_16[0x20];
7006
7007 u8 rmac_15_0[0x10];
7008 u8 tclass[0x8];
7009 u8 hop_limit[0x8];
7010
b4ff3a36 7011 u8 reserved_at_e0[0x1];
e281682b 7012 u8 grh[0x1];
b4ff3a36 7013 u8 reserved_at_e2[0x2];
e281682b
SM		 7014 u8 src_addr_index[0x8];
7015 u8 flow_label[0x14];
7016
7017 u8 rgid_rip[16][0x8];
7018};
7019
7020struct mlx5_ifc_pages_req_event_bits {
b4ff3a36 7021 u8 reserved_at_0[0x10];
e281682b
SM		 7022 u8 function_id[0x10];
7023
7024 u8 num_pages[0x20];
7025
b4ff3a36 7026 u8 reserved_at_40[0xa0];
e281682b
SM		 7027};
7028
7029struct mlx5_ifc_eqe_bits {
b4ff3a36 7030 u8 reserved_at_0[0x8];
e281682b 7031 u8 event_type[0x8];
b4ff3a36 7032 u8 reserved_at_10[0x8];
e281682b
SM		 7033 u8 event_sub_type[0x8];
7034
b4ff3a36 7035 u8 reserved_at_20[0xe0];
e281682b
SM		 7036
7037 union mlx5_ifc_event_auto_bits event_data;
7038
b4ff3a36 7039 u8 reserved_at_1e0[0x10];
e281682b 7040 u8 signature[0x8];
b4ff3a36 7041 u8 reserved_at_1f8[0x7];
e281682b
SM		 7042 u8 owner[0x1];
7043};
7044
7045enum {
7046 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
7047};
7048
7049struct mlx5_ifc_cmd_queue_entry_bits {
7050 u8 type[0x8];
b4ff3a36 7051 u8 reserved_at_8[0x18];
e281682b
SM		 7052
7053 u8 input_length[0x20];
7054
7055 u8 input_mailbox_pointer_63_32[0x20];
7056
7057 u8 input_mailbox_pointer_31_9[0x17];
b4ff3a36 7058 u8 reserved_at_77[0x9];
e281682b
SM		 7059
7060 u8 command_input_inline_data[16][0x8];
7061
7062 u8 command_output_inline_data[16][0x8];
7063
7064 u8 output_mailbox_pointer_63_32[0x20];
7065
7066 u8 output_mailbox_pointer_31_9[0x17];
b4ff3a36 7067 u8 reserved_at_1b7[0x9];
e281682b
SM		 7068
7069 u8 output_length[0x20];
7070
7071 u8 token[0x8];
7072 u8 signature[0x8];
b4ff3a36 7073 u8 reserved_at_1f0[0x8];
e281682b
SM		 7074 u8 status[0x7];
7075 u8 ownership[0x1];
7076};
7077
7078struct mlx5_ifc_cmd_out_bits {
7079 u8 status[0x8];
b4ff3a36 7080 u8 reserved_at_8[0x18];
e281682b
SM		 7081
7082 u8 syndrome[0x20];
7083
7084 u8 command_output[0x20];
7085};
7086
7087struct mlx5_ifc_cmd_in_bits {
7088 u8 opcode[0x10];
b4ff3a36 7089 u8 reserved_at_10[0x10];
e281682b 7090
b4ff3a36 7091 u8 reserved_at_20[0x10];
e281682b
SM		 7092 u8 op_mod[0x10];
7093
7094 u8 command[0][0x20];
7095};
7096
7097struct mlx5_ifc_cmd_if_box_bits {
7098 u8 mailbox_data[512][0x8];
7099
b4ff3a36 7100 u8 reserved_at_1000[0x180];
e281682b
SM		 7101
7102 u8 next_pointer_63_32[0x20];
7103
7104 u8 next_pointer_31_10[0x16];
b4ff3a36 7105 u8 reserved_at_11b6[0xa];
e281682b
SM		 7106
7107 u8 block_number[0x20];
7108
b4ff3a36 7109 u8 reserved_at_11e0[0x8];
e281682b
SM		 7110 u8 token[0x8];
7111 u8 ctrl_signature[0x8];
7112 u8 signature[0x8];
7113};
7114
7115struct mlx5_ifc_mtt_bits {
7116 u8 ptag_63_32[0x20];
7117
7118 u8 ptag_31_8[0x18];
b4ff3a36 7119 u8 reserved_at_38[0x6];
e281682b
SM		 7120 u8 wr_en[0x1];
7121 u8 rd_en[0x1];
7122};
7123
928cfe87
TT		 7124struct mlx5_ifc_query_wol_rol_out_bits {
7125 u8 status[0x8];
7126 u8 reserved_at_8[0x18];
7127
7128 u8 syndrome[0x20];
7129
7130 u8 reserved_at_40[0x10];
7131 u8 rol_mode[0x8];
7132 u8 wol_mode[0x8];
7133
7134 u8 reserved_at_60[0x20];
7135};
7136
7137struct mlx5_ifc_query_wol_rol_in_bits {
7138 u8 opcode[0x10];
7139 u8 reserved_at_10[0x10];
7140
7141 u8 reserved_at_20[0x10];
7142 u8 op_mod[0x10];
7143
7144 u8 reserved_at_40[0x40];
7145};
7146
7147struct mlx5_ifc_set_wol_rol_out_bits {
7148 u8 status[0x8];
7149 u8 reserved_at_8[0x18];
7150
7151 u8 syndrome[0x20];
7152
7153 u8 reserved_at_40[0x40];
7154};
7155
7156struct mlx5_ifc_set_wol_rol_in_bits {
7157 u8 opcode[0x10];
7158 u8 reserved_at_10[0x10];
7159
7160 u8 reserved_at_20[0x10];
7161 u8 op_mod[0x10];
7162
7163 u8 rol_mode_valid[0x1];
7164 u8 wol_mode_valid[0x1];
7165 u8 reserved_at_42[0xe];
7166 u8 rol_mode[0x8];
7167 u8 wol_mode[0x8];
7168
7169 u8 reserved_at_60[0x20];
7170};
7171
e281682b
SM		 7172enum {
7173 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
7174 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
7175 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
7176};
7177
7178enum {
7179 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
7180 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
7181 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
7182};
7183
7184enum {
7185 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
7186 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
7187 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
7188 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
7189 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
7190 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
7191 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
7192 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
7193 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
7194 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
7195 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
7196};
7197
7198struct mlx5_ifc_initial_seg_bits {
7199 u8 fw_rev_minor[0x10];
7200 u8 fw_rev_major[0x10];
7201
7202 u8 cmd_interface_rev[0x10];
7203 u8 fw_rev_subminor[0x10];
7204
b4ff3a36 7205 u8 reserved_at_40[0x40];
e281682b
SM		 7206
7207 u8 cmdq_phy_addr_63_32[0x20];
7208
7209 u8 cmdq_phy_addr_31_12[0x14];
b4ff3a36 7210 u8 reserved_at_b4[0x2];
e281682b
SM		 7211 u8 nic_interface[0x2];
7212 u8 log_cmdq_size[0x4];
7213 u8 log_cmdq_stride[0x4];
7214
7215 u8 command_doorbell_vector[0x20];
7216
b4ff3a36 7217 u8 reserved_at_e0[0xf00];
e281682b
SM		 7218
7219 u8 initializing[0x1];
b4ff3a36 7220 u8 reserved_at_fe1[0x4];
e281682b 7221 u8 nic_interface_supported[0x3];
b4ff3a36 7222 u8 reserved_at_fe8[0x18];
e281682b
SM		 7223
7224 struct mlx5_ifc_health_buffer_bits health_buffer;
7225
7226 u8 no_dram_nic_offset[0x20];
7227
b4ff3a36 7228 u8 reserved_at_1220[0x6e40];
e281682b 7229
b4ff3a36 7230 u8 reserved_at_8060[0x1f];
e281682b
SM		 7231 u8 clear_int[0x1];
7232
7233 u8 health_syndrome[0x8];
7234 u8 health_counter[0x18];
7235
b4ff3a36 7236 u8 reserved_at_80a0[0x17fc0];
e281682b
SM		 7237};
7238
7239union mlx5_ifc_ports_control_registers_document_bits {
7240 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
7241 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
7242 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
7243 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
7244 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
7245 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
7246 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
7247 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
7248 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
7249 struct mlx5_ifc_pamp_reg_bits pamp_reg;
7250 struct mlx5_ifc_paos_reg_bits paos_reg;
7251 struct mlx5_ifc_pcap_reg_bits pcap_reg;
7252 struct mlx5_ifc_peir_reg_bits peir_reg;
7253 struct mlx5_ifc_pelc_reg_bits pelc_reg;
7254 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
1c64bf6f 7255 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b
SM		 7256 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
7257 struct mlx5_ifc_pifr_reg_bits pifr_reg;
7258 struct mlx5_ifc_pipg_reg_bits pipg_reg;
7259 struct mlx5_ifc_plbf_reg_bits plbf_reg;
7260 struct mlx5_ifc_plib_reg_bits plib_reg;
7261 struct mlx5_ifc_plpc_reg_bits plpc_reg;
7262 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
7263 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
7264 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
7265 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
7266 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
7267 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
7268 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
7269 struct mlx5_ifc_ppad_reg_bits ppad_reg;
7270 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
7271 struct mlx5_ifc_pplm_reg_bits pplm_reg;
7272 struct mlx5_ifc_pplr_reg_bits pplr_reg;
7273 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
7274 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
7275 struct mlx5_ifc_pspa_reg_bits pspa_reg;
7276 struct mlx5_ifc_ptas_reg_bits ptas_reg;
7277 struct mlx5_ifc_ptys_reg_bits ptys_reg;
7d5e1423 7278 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
e281682b
SM		 7279 struct mlx5_ifc_pude_reg_bits pude_reg;
7280 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
7281 struct mlx5_ifc_slrg_reg_bits slrg_reg;
7282 struct mlx5_ifc_sltp_reg_bits sltp_reg;
b4ff3a36 7283 u8 reserved_at_0[0x60e0];
e281682b
SM		 7284};
7285
7286union mlx5_ifc_debug_enhancements_document_bits {
7287 struct mlx5_ifc_health_buffer_bits health_buffer;
b4ff3a36 7288 u8 reserved_at_0[0x200];
e281682b
SM		 7289};
7290
7291union mlx5_ifc_uplink_pci_interface_document_bits {
7292 struct mlx5_ifc_initial_seg_bits initial_seg;
b4ff3a36 7293 u8 reserved_at_0[0x20060];
b775516b
EC		 7294};
7295
2cc43b49
MG		 7296struct mlx5_ifc_set_flow_table_root_out_bits {
7297 u8 status[0x8];
b4ff3a36 7298 u8 reserved_at_8[0x18];
2cc43b49
MG		 7299
7300 u8 syndrome[0x20];
7301
b4ff3a36 7302 u8 reserved_at_40[0x40];
2cc43b49
MG		 7303};
7304
7305struct mlx5_ifc_set_flow_table_root_in_bits {
7306 u8 opcode[0x10];
b4ff3a36 7307 u8 reserved_at_10[0x10];
2cc43b49 7308
b4ff3a36 7309 u8 reserved_at_20[0x10];
2cc43b49
MG		 7310 u8 op_mod[0x10];
7311
7d5e1423
SM		 7312 u8 other_vport[0x1];
7313 u8 reserved_at_41[0xf];
7314 u8 vport_number[0x10];
7315
7316 u8 reserved_at_60[0x20];
2cc43b49
MG		 7317
7318 u8 table_type[0x8];
b4ff3a36 7319 u8 reserved_at_88[0x18];
2cc43b49 7320
b4ff3a36 7321 u8 reserved_at_a0[0x8];
2cc43b49
MG		 7322 u8 table_id[0x18];
7323
b4ff3a36 7324 u8 reserved_at_c0[0x140];
2cc43b49
MG		 7325};
7326
34a40e68
MG		 7327enum {
7328 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = 0x1,
7329};
7330
7331struct mlx5_ifc_modify_flow_table_out_bits {
7332 u8 status[0x8];
b4ff3a36 7333 u8 reserved_at_8[0x18];
34a40e68
MG		 7334
7335 u8 syndrome[0x20];
7336
b4ff3a36 7337 u8 reserved_at_40[0x40];
34a40e68
MG		 7338};
7339
7340struct mlx5_ifc_modify_flow_table_in_bits {
7341 u8 opcode[0x10];
b4ff3a36 7342 u8 reserved_at_10[0x10];
34a40e68 7343
b4ff3a36 7344 u8 reserved_at_20[0x10];
34a40e68
MG		 7345 u8 op_mod[0x10];
7346
7d5e1423
SM		 7347 u8 other_vport[0x1];
7348 u8 reserved_at_41[0xf];
7349 u8 vport_number[0x10];
34a40e68 7350
b4ff3a36 7351 u8 reserved_at_60[0x10];
34a40e68
MG		 7352 u8 modify_field_select[0x10];
7353
7354 u8 table_type[0x8];
b4ff3a36 7355 u8 reserved_at_88[0x18];
34a40e68 7356
b4ff3a36 7357 u8 reserved_at_a0[0x8];
34a40e68
MG		 7358 u8 table_id[0x18];
7359
b4ff3a36 7360 u8 reserved_at_c0[0x4];
34a40e68 7361 u8 table_miss_mode[0x4];
b4ff3a36 7362 u8 reserved_at_c8[0x18];
34a40e68 7363
b4ff3a36 7364 u8 reserved_at_e0[0x8];
34a40e68
MG		 7365 u8 table_miss_id[0x18];
7366
b4ff3a36 7367 u8 reserved_at_100[0x100];
34a40e68
MG		 7368};
7369
4f3961ee
SM		 7370struct mlx5_ifc_ets_tcn_config_reg_bits {
7371 u8 g[0x1];
7372 u8 b[0x1];
7373 u8 r[0x1];
7374 u8 reserved_at_3[0x9];
7375 u8 group[0x4];
7376 u8 reserved_at_10[0x9];
7377 u8 bw_allocation[0x7];
7378
7379 u8 reserved_at_20[0xc];
7380 u8 max_bw_units[0x4];
7381 u8 reserved_at_30[0x8];
7382 u8 max_bw_value[0x8];
7383};
7384
7385struct mlx5_ifc_ets_global_config_reg_bits {
7386 u8 reserved_at_0[0x2];
7387 u8 r[0x1];
7388 u8 reserved_at_3[0x1d];
7389
7390 u8 reserved_at_20[0xc];
7391 u8 max_bw_units[0x4];
7392 u8 reserved_at_30[0x8];
7393 u8 max_bw_value[0x8];
7394};
7395
7396struct mlx5_ifc_qetc_reg_bits {
7397 u8 reserved_at_0[0x8];
7398 u8 port_number[0x8];
7399 u8 reserved_at_10[0x30];
7400
7401 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
7402 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
7403};
7404
7405struct mlx5_ifc_qtct_reg_bits {
7406 u8 reserved_at_0[0x8];
7407 u8 port_number[0x8];
7408 u8 reserved_at_10[0xd];
7409 u8 prio[0x3];
7410
7411 u8 reserved_at_20[0x1d];
7412 u8 tclass[0x3];
7413};
7414
7d5e1423
SM		 7415struct mlx5_ifc_mcia_reg_bits {
7416 u8 l[0x1];
7417 u8 reserved_at_1[0x7];
7418 u8 module[0x8];
7419 u8 reserved_at_10[0x8];
7420 u8 status[0x8];
7421
7422 u8 i2c_device_address[0x8];
7423 u8 page_number[0x8];
7424 u8 device_address[0x10];
7425
7426 u8 reserved_at_40[0x10];
7427 u8 size[0x10];
7428
7429 u8 reserved_at_60[0x20];
7430
7431 u8 dword_0[0x20];
7432 u8 dword_1[0x20];
7433 u8 dword_2[0x20];
7434 u8 dword_3[0x20];
7435 u8 dword_4[0x20];
7436 u8 dword_5[0x20];
7437 u8 dword_6[0x20];
7438 u8 dword_7[0x20];
7439 u8 dword_8[0x20];
7440 u8 dword_9[0x20];
7441 u8 dword_10[0x20];
7442 u8 dword_11[0x20];
7443};
7444
d29b796a 7445#endif /* MLX5_IFC_H */
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