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IB/mthca: Check validity of output parameter pointer
[mirror_ubuntu-bionic-kernel.git] / include / linux / mlx5 / mlx5_ifc.h
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d29b796a 1/*
e281682b 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
d29b796a
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
e281682b 31*/
d29b796a
EC		 32#ifndef MLX5_IFC_H
33#define MLX5_IFC_H
34
e281682b
SM		 35enum {
36 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
37 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
38 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
39 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
40 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
41 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
42 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
43 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
44 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
45 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
46 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
47 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
48 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
49 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
50 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
51 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
52 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
53 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
54 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
55 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
56 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
57 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
58 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
59 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb
60};
61
62enum {
63 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
64 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
65 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
66 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
67};
68
f91e6d89
EBE		 69enum {
70 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
71 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
72};
73
d29b796a
EC		 74enum {
75 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
76 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
77 MLX5_CMD_OP_INIT_HCA = 0x102,
78 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
79 MLX5_CMD_OP_ENABLE_HCA = 0x104,
80 MLX5_CMD_OP_DISABLE_HCA = 0x105,
81 MLX5_CMD_OP_QUERY_PAGES = 0x107,
82 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
83 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
e281682b
SM		 84 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
85 MLX5_CMD_OP_SET_ISSI = 0x10b,
0dbc6fe0 86 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
d29b796a
EC		 87 MLX5_CMD_OP_CREATE_MKEY = 0x200,
88 MLX5_CMD_OP_QUERY_MKEY = 0x201,
89 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
90 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
91 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
92 MLX5_CMD_OP_CREATE_EQ = 0x301,
93 MLX5_CMD_OP_DESTROY_EQ = 0x302,
94 MLX5_CMD_OP_QUERY_EQ = 0x303,
95 MLX5_CMD_OP_GEN_EQE = 0x304,
96 MLX5_CMD_OP_CREATE_CQ = 0x400,
97 MLX5_CMD_OP_DESTROY_CQ = 0x401,
98 MLX5_CMD_OP_QUERY_CQ = 0x402,
99 MLX5_CMD_OP_MODIFY_CQ = 0x403,
100 MLX5_CMD_OP_CREATE_QP = 0x500,
101 MLX5_CMD_OP_DESTROY_QP = 0x501,
102 MLX5_CMD_OP_RST2INIT_QP = 0x502,
103 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
104 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
105 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
106 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
107 MLX5_CMD_OP_2ERR_QP = 0x507,
108 MLX5_CMD_OP_2RST_QP = 0x50a,
109 MLX5_CMD_OP_QUERY_QP = 0x50b,
e281682b 110 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
d29b796a
EC		 111 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
112 MLX5_CMD_OP_CREATE_PSV = 0x600,
113 MLX5_CMD_OP_DESTROY_PSV = 0x601,
114 MLX5_CMD_OP_CREATE_SRQ = 0x700,
115 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
116 MLX5_CMD_OP_QUERY_SRQ = 0x702,
117 MLX5_CMD_OP_ARM_RQ = 0x703,
e281682b
SM		 118 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
119 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
120 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
121 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
d29b796a
EC		 122 MLX5_CMD_OP_CREATE_DCT = 0x710,
123 MLX5_CMD_OP_DESTROY_DCT = 0x711,
124 MLX5_CMD_OP_DRAIN_DCT = 0x712,
125 MLX5_CMD_OP_QUERY_DCT = 0x713,
126 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
7486216b
SM		 127 MLX5_CMD_OP_CREATE_XRQ = 0x717,
128 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
129 MLX5_CMD_OP_QUERY_XRQ = 0x719,
130 MLX5_CMD_OP_ARM_XRQ = 0x71a,
d29b796a
EC		 131 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
132 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
133 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
134 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
135 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
136 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
e281682b 137 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
d29b796a 138 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
e281682b
SM		 139 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
140 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
141 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
142 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
d29b796a
EC		 143 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
144 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
145 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
146 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
7486216b
SM		 147 MLX5_CMD_OP_SET_RATE_LIMIT = 0x780,
148 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
813f8540
MHY		 149 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
150 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
151 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
152 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
153 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
154 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
d29b796a
EC		 155 MLX5_CMD_OP_ALLOC_PD = 0x800,
156 MLX5_CMD_OP_DEALLOC_PD = 0x801,
157 MLX5_CMD_OP_ALLOC_UAR = 0x802,
158 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
159 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
160 MLX5_CMD_OP_ACCESS_REG = 0x805,
161 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
20bb566b 162 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
d29b796a
EC		 163 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
164 MLX5_CMD_OP_MAD_IFC = 0x50d,
165 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
166 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
167 MLX5_CMD_OP_NOP = 0x80d,
168 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
169 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
e281682b
SM		 170 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
171 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
172 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
173 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
174 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
175 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
176 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
177 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
178 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
179 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
180 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
181 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
928cfe87
TT		 182 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
183 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
84df61eb
AH		 184 MLX5_CMD_OP_CREATE_LAG = 0x840,
185 MLX5_CMD_OP_MODIFY_LAG = 0x841,
186 MLX5_CMD_OP_QUERY_LAG = 0x842,
187 MLX5_CMD_OP_DESTROY_LAG = 0x843,
188 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
189 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
d29b796a
EC		 190 MLX5_CMD_OP_CREATE_TIR = 0x900,
191 MLX5_CMD_OP_MODIFY_TIR = 0x901,
192 MLX5_CMD_OP_DESTROY_TIR = 0x902,
193 MLX5_CMD_OP_QUERY_TIR = 0x903,
d29b796a
EC		 194 MLX5_CMD_OP_CREATE_SQ = 0x904,
195 MLX5_CMD_OP_MODIFY_SQ = 0x905,
196 MLX5_CMD_OP_DESTROY_SQ = 0x906,
197 MLX5_CMD_OP_QUERY_SQ = 0x907,
198 MLX5_CMD_OP_CREATE_RQ = 0x908,
199 MLX5_CMD_OP_MODIFY_RQ = 0x909,
200 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
201 MLX5_CMD_OP_QUERY_RQ = 0x90b,
202 MLX5_CMD_OP_CREATE_RMP = 0x90c,
203 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
204 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
205 MLX5_CMD_OP_QUERY_RMP = 0x90f,
e281682b
SM		 206 MLX5_CMD_OP_CREATE_TIS = 0x912,
207 MLX5_CMD_OP_MODIFY_TIS = 0x913,
208 MLX5_CMD_OP_DESTROY_TIS = 0x914,
209 MLX5_CMD_OP_QUERY_TIS = 0x915,
210 MLX5_CMD_OP_CREATE_RQT = 0x916,
211 MLX5_CMD_OP_MODIFY_RQT = 0x917,
212 MLX5_CMD_OP_DESTROY_RQT = 0x918,
213 MLX5_CMD_OP_QUERY_RQT = 0x919,
2cc43b49 214 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
e281682b
SM		 215 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
216 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
217 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
218 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
219 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
220 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
221 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
222 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
34a40e68 223 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
9dc0b289
AV		 224 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
225 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
226 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
86d56a1a 227 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
7adbde20
HHZ		 228 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d,
229 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e,
2a69cb9f
OG		 230 MLX5_CMD_OP_ALLOC_MODIFY_HEADER_CONTEXT = 0x940,
231 MLX5_CMD_OP_DEALLOC_MODIFY_HEADER_CONTEXT = 0x941,
86d56a1a 232 MLX5_CMD_OP_MAX
e281682b
SM		 233};
234
235struct mlx5_ifc_flow_table_fields_supported_bits {
236 u8 outer_dmac[0x1];
237 u8 outer_smac[0x1];
238 u8 outer_ether_type[0x1];
19cc7524 239 u8 outer_ip_version[0x1];
e281682b
SM		 240 u8 outer_first_prio[0x1];
241 u8 outer_first_cfi[0x1];
242 u8 outer_first_vid[0x1];
b4ff3a36 243 u8 reserved_at_7[0x1];
e281682b
SM		 244 u8 outer_second_prio[0x1];
245 u8 outer_second_cfi[0x1];
246 u8 outer_second_vid[0x1];
b4ff3a36 247 u8 reserved_at_b[0x1];
e281682b
SM		 248 u8 outer_sip[0x1];
249 u8 outer_dip[0x1];
250 u8 outer_frag[0x1];
251 u8 outer_ip_protocol[0x1];
252 u8 outer_ip_ecn[0x1];
253 u8 outer_ip_dscp[0x1];
254 u8 outer_udp_sport[0x1];
255 u8 outer_udp_dport[0x1];
256 u8 outer_tcp_sport[0x1];
257 u8 outer_tcp_dport[0x1];
258 u8 outer_tcp_flags[0x1];
259 u8 outer_gre_protocol[0x1];
260 u8 outer_gre_key[0x1];
261 u8 outer_vxlan_vni[0x1];
b4ff3a36 262 u8 reserved_at_1a[0x5];
e281682b
SM		 263 u8 source_eswitch_port[0x1];
264
265 u8 inner_dmac[0x1];
266 u8 inner_smac[0x1];
267 u8 inner_ether_type[0x1];
19cc7524 268 u8 inner_ip_version[0x1];
e281682b
SM		 269 u8 inner_first_prio[0x1];
270 u8 inner_first_cfi[0x1];
271 u8 inner_first_vid[0x1];
b4ff3a36 272 u8 reserved_at_27[0x1];
e281682b
SM		 273 u8 inner_second_prio[0x1];
274 u8 inner_second_cfi[0x1];
275 u8 inner_second_vid[0x1];
b4ff3a36 276 u8 reserved_at_2b[0x1];
e281682b
SM		 277 u8 inner_sip[0x1];
278 u8 inner_dip[0x1];
279 u8 inner_frag[0x1];
280 u8 inner_ip_protocol[0x1];
281 u8 inner_ip_ecn[0x1];
282 u8 inner_ip_dscp[0x1];
283 u8 inner_udp_sport[0x1];
284 u8 inner_udp_dport[0x1];
285 u8 inner_tcp_sport[0x1];
286 u8 inner_tcp_dport[0x1];
287 u8 inner_tcp_flags[0x1];
b4ff3a36 288 u8 reserved_at_37[0x9];
e281682b 289
b4ff3a36 290 u8 reserved_at_40[0x40];
e281682b
SM		 291};
292
293struct mlx5_ifc_flow_table_prop_layout_bits {
294 u8 ft_support[0x1];
9dc0b289
AV		 295 u8 reserved_at_1[0x1];
296 u8 flow_counter[0x1];
26a81453 297 u8 flow_modify_en[0x1];
2cc43b49 298 u8 modify_root[0x1];
34a40e68
MG		 299 u8 identified_miss_table_mode[0x1];
300 u8 flow_table_modify[0x1];
7adbde20
HHZ		 301 u8 encap[0x1];
302 u8 decap[0x1];
303 u8 reserved_at_9[0x17];
e281682b 304
b4ff3a36 305 u8 reserved_at_20[0x2];
e281682b 306 u8 log_max_ft_size[0x6];
2a69cb9f
OG		 307 u8 log_max_modify_header_context[0x8];
308 u8 max_modify_header_actions[0x8];
e281682b
SM		 309 u8 max_ft_level[0x8];
310
b4ff3a36 311 u8 reserved_at_40[0x20];
e281682b 312
b4ff3a36 313 u8 reserved_at_60[0x18];
e281682b
SM		 314 u8 log_max_ft_num[0x8];
315
b4ff3a36 316 u8 reserved_at_80[0x18];
e281682b
SM		 317 u8 log_max_destination[0x8];
318
b4ff3a36 319 u8 reserved_at_a0[0x18];
e281682b
SM		 320 u8 log_max_flow[0x8];
321
b4ff3a36 322 u8 reserved_at_c0[0x40];
e281682b
SM		 323
324 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
325
326 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
327};
328
329struct mlx5_ifc_odp_per_transport_service_cap_bits {
330 u8 send[0x1];
331 u8 receive[0x1];
332 u8 write[0x1];
333 u8 read[0x1];
17d2f88f 334 u8 atomic[0x1];
e281682b 335 u8 srq_receive[0x1];
b4ff3a36 336 u8 reserved_at_6[0x1a];
e281682b
SM		 337};
338
b4d1f032 339struct mlx5_ifc_ipv4_layout_bits {
b4ff3a36 340 u8 reserved_at_0[0x60];
b4d1f032
MG		 341
342 u8 ipv4[0x20];
343};
344
345struct mlx5_ifc_ipv6_layout_bits {
346 u8 ipv6[16][0x8];
347};
348
349union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
350 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
351 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
b4ff3a36 352 u8 reserved_at_0[0x80];
b4d1f032
MG		 353};
354
e281682b
SM		 355struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
356 u8 smac_47_16[0x20];
357
358 u8 smac_15_0[0x10];
359 u8 ethertype[0x10];
360
361 u8 dmac_47_16[0x20];
362
363 u8 dmac_15_0[0x10];
364 u8 first_prio[0x3];
365 u8 first_cfi[0x1];
366 u8 first_vid[0xc];
367
368 u8 ip_protocol[0x8];
369 u8 ip_dscp[0x6];
370 u8 ip_ecn[0x2];
10543365
MHY		 371 u8 cvlan_tag[0x1];
372 u8 svlan_tag[0x1];
e281682b 373 u8 frag[0x1];
19cc7524 374 u8 ip_version[0x4];
e281682b
SM		 375 u8 tcp_flags[0x9];
376
377 u8 tcp_sport[0x10];
378 u8 tcp_dport[0x10];
379
b4ff3a36 380 u8 reserved_at_c0[0x20];
e281682b
SM		 381
382 u8 udp_sport[0x10];
383 u8 udp_dport[0x10];
384
b4d1f032 385 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
e281682b 386
b4d1f032 387 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
e281682b
SM		 388};
389
390struct mlx5_ifc_fte_match_set_misc_bits {
7486216b
SM		 391 u8 reserved_at_0[0x8];
392 u8 source_sqn[0x18];
e281682b 393
b4ff3a36 394 u8 reserved_at_20[0x10];
e281682b
SM		 395 u8 source_port[0x10];
396
397 u8 outer_second_prio[0x3];
398 u8 outer_second_cfi[0x1];
399 u8 outer_second_vid[0xc];
400 u8 inner_second_prio[0x3];
401 u8 inner_second_cfi[0x1];
402 u8 inner_second_vid[0xc];
403
10543365
MHY		 404 u8 outer_second_cvlan_tag[0x1];
405 u8 inner_second_cvlan_tag[0x1];
406 u8 outer_second_svlan_tag[0x1];
407 u8 inner_second_svlan_tag[0x1];
408 u8 reserved_at_64[0xc];
e281682b
SM		 409 u8 gre_protocol[0x10];
410
411 u8 gre_key_h[0x18];
412 u8 gre_key_l[0x8];
413
414 u8 vxlan_vni[0x18];
b4ff3a36 415 u8 reserved_at_b8[0x8];
e281682b 416
b4ff3a36 417 u8 reserved_at_c0[0x20];
e281682b 418
b4ff3a36 419 u8 reserved_at_e0[0xc];
e281682b
SM		 420 u8 outer_ipv6_flow_label[0x14];
421
b4ff3a36 422 u8 reserved_at_100[0xc];
e281682b
SM		 423 u8 inner_ipv6_flow_label[0x14];
424
b4ff3a36 425 u8 reserved_at_120[0xe0];
e281682b
SM		 426};
427
428struct mlx5_ifc_cmd_pas_bits {
429 u8 pa_h[0x20];
430
431 u8 pa_l[0x14];
b4ff3a36 432 u8 reserved_at_34[0xc];
e281682b
SM		 433};
434
435struct mlx5_ifc_uint64_bits {
436 u8 hi[0x20];
437
438 u8 lo[0x20];
439};
440
441enum {
442 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
443 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
444 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
445 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
446 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
447 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
448 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
449 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
450 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
451 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
452};
453
454struct mlx5_ifc_ads_bits {
455 u8 fl[0x1];
456 u8 free_ar[0x1];
b4ff3a36 457 u8 reserved_at_2[0xe];
e281682b
SM		 458 u8 pkey_index[0x10];
459
b4ff3a36 460 u8 reserved_at_20[0x8];
e281682b
SM		 461 u8 grh[0x1];
462 u8 mlid[0x7];
463 u8 rlid[0x10];
464
465 u8 ack_timeout[0x5];
b4ff3a36 466 u8 reserved_at_45[0x3];
e281682b 467 u8 src_addr_index[0x8];
b4ff3a36 468 u8 reserved_at_50[0x4];
e281682b
SM		 469 u8 stat_rate[0x4];
470 u8 hop_limit[0x8];
471
b4ff3a36 472 u8 reserved_at_60[0x4];
e281682b
SM		 473 u8 tclass[0x8];
474 u8 flow_label[0x14];
475
476 u8 rgid_rip[16][0x8];
477
b4ff3a36 478 u8 reserved_at_100[0x4];
e281682b
SM		 479 u8 f_dscp[0x1];
480 u8 f_ecn[0x1];
b4ff3a36 481 u8 reserved_at_106[0x1];
e281682b
SM		 482 u8 f_eth_prio[0x1];
483 u8 ecn[0x2];
484 u8 dscp[0x6];
485 u8 udp_sport[0x10];
486
487 u8 dei_cfi[0x1];
488 u8 eth_prio[0x3];
489 u8 sl[0x4];
490 u8 port[0x8];
491 u8 rmac_47_32[0x10];
492
493 u8 rmac_31_0[0x20];
494};
495
496struct mlx5_ifc_flow_table_nic_cap_bits {
b3638e1a 497 u8 nic_rx_multi_path_tirs[0x1];
cea824d4
MG		 498 u8 nic_rx_multi_path_tirs_fts[0x1];
499 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
500 u8 reserved_at_3[0x1fd];
e281682b
SM		 501
502 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
503
b4ff3a36 504 u8 reserved_at_400[0x200];
e281682b
SM		 505
506 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
507
508 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
509
b4ff3a36 510 u8 reserved_at_a00[0x200];
e281682b
SM		 511
512 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
513
b4ff3a36 514 u8 reserved_at_e00[0x7200];
e281682b
SM		 515};
516
495716b1 517struct mlx5_ifc_flow_table_eswitch_cap_bits {
b4ff3a36 518 u8 reserved_at_0[0x200];
495716b1
SM		 519
520 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
521
522 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
523
524 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
525
b4ff3a36 526 u8 reserved_at_800[0x7800];
495716b1
SM		 527};
528
d6666753
SM		 529struct mlx5_ifc_e_switch_cap_bits {
530 u8 vport_svlan_strip[0x1];
531 u8 vport_cvlan_strip[0x1];
532 u8 vport_svlan_insert[0x1];
533 u8 vport_cvlan_insert_if_not_exist[0x1];
534 u8 vport_cvlan_insert_overwrite[0x1];
23898c76
NO		 535 u8 reserved_at_5[0x19];
536 u8 nic_vport_node_guid_modify[0x1];
537 u8 nic_vport_port_guid_modify[0x1];
d6666753 538
7adbde20
HHZ		 539 u8 vxlan_encap_decap[0x1];
540 u8 nvgre_encap_decap[0x1];
541 u8 reserved_at_22[0x9];
542 u8 log_max_encap_headers[0x5];
543 u8 reserved_2b[0x6];
544 u8 max_encap_header_size[0xa];
545
546 u8 reserved_40[0x7c0];
547
d6666753
SM		 548};
549
7486216b
SM		 550struct mlx5_ifc_qos_cap_bits {
551 u8 packet_pacing[0x1];
813f8540 552 u8 esw_scheduling[0x1];
c9497c98
MHY		 553 u8 esw_bw_share[0x1];
554 u8 esw_rate_limit[0x1];
555 u8 reserved_at_4[0x1c];
813f8540
MHY		 556
557 u8 reserved_at_20[0x20];
558
7486216b 559 u8 packet_pacing_max_rate[0x20];
813f8540 560
7486216b 561 u8 packet_pacing_min_rate[0x20];
813f8540
MHY		 562
563 u8 reserved_at_80[0x10];
7486216b 564 u8 packet_pacing_rate_table_size[0x10];
813f8540
MHY		 565
566 u8 esw_element_type[0x10];
567 u8 esw_tsar_type[0x10];
568
569 u8 reserved_at_c0[0x10];
570 u8 max_qos_para_vport[0x10];
571
572 u8 max_tsar_bw_share[0x20];
573
574 u8 reserved_at_100[0x700];
7486216b
SM		 575};
576
e281682b
SM		 577struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
578 u8 csum_cap[0x1];
579 u8 vlan_cap[0x1];
580 u8 lro_cap[0x1];
581 u8 lro_psh_flag[0x1];
582 u8 lro_time_stamp[0x1];
2b31f7ae
SM		 583 u8 reserved_at_5[0x2];
584 u8 wqe_vlan_insert[0x1];
66189961 585 u8 self_lb_en_modifiable[0x1];
b4ff3a36 586 u8 reserved_at_9[0x2];
e281682b 587 u8 max_lso_cap[0x5];
c226dc22 588 u8 multi_pkt_send_wqe[0x2];
cff92d7c 589 u8 wqe_inline_mode[0x2];
e281682b 590 u8 rss_ind_tbl_cap[0x4];
7d5e1423
SM		 591 u8 reg_umr_sq[0x1];
592 u8 scatter_fcs[0x1];
593 u8 reserved_at_1a[0x1];
e281682b 594 u8 tunnel_lso_const_out_ip_id[0x1];
b4ff3a36 595 u8 reserved_at_1c[0x2];
e281682b
SM		 596 u8 tunnel_statless_gre[0x1];
597 u8 tunnel_stateless_vxlan[0x1];
598
b4ff3a36 599 u8 reserved_at_20[0x20];
e281682b 600
b4ff3a36 601 u8 reserved_at_40[0x10];
e281682b
SM		 602 u8 lro_min_mss_size[0x10];
603
b4ff3a36 604 u8 reserved_at_60[0x120];
e281682b
SM		 605
606 u8 lro_timer_supported_periods[4][0x20];
607
b4ff3a36 608 u8 reserved_at_200[0x600];
e281682b
SM		 609};
610
611struct mlx5_ifc_roce_cap_bits {
612 u8 roce_apm[0x1];
b4ff3a36 613 u8 reserved_at_1[0x1f];
e281682b 614
b4ff3a36 615 u8 reserved_at_20[0x60];
e281682b 616
b4ff3a36 617 u8 reserved_at_80[0xc];
e281682b 618 u8 l3_type[0x4];
b4ff3a36 619 u8 reserved_at_90[0x8];
e281682b
SM		 620 u8 roce_version[0x8];
621
b4ff3a36 622 u8 reserved_at_a0[0x10];
e281682b
SM		 623 u8 r_roce_dest_udp_port[0x10];
624
625 u8 r_roce_max_src_udp_port[0x10];
626 u8 r_roce_min_src_udp_port[0x10];
627
b4ff3a36 628 u8 reserved_at_e0[0x10];
e281682b
SM		 629 u8 roce_address_table_size[0x10];
630
b4ff3a36 631 u8 reserved_at_100[0x700];
e281682b
SM		 632};
633
634enum {
635 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
636 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
637 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
638 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
639 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
640 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
641 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
642 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
643 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
644};
645
646enum {
647 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
648 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
649 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
650 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
651 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
652 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
653 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
654 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
655 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
656};
657
658struct mlx5_ifc_atomic_caps_bits {
b4ff3a36 659 u8 reserved_at_0[0x40];
e281682b 660
f91e6d89 661 u8 atomic_req_8B_endianess_mode[0x2];
b4ff3a36 662 u8 reserved_at_42[0x4];
f91e6d89 663 u8 supported_atomic_req_8B_endianess_mode_1[0x1];
e281682b 664
b4ff3a36 665 u8 reserved_at_47[0x19];
e281682b 666
b4ff3a36 667 u8 reserved_at_60[0x20];
e281682b 668
b4ff3a36 669 u8 reserved_at_80[0x10];
f91e6d89 670 u8 atomic_operations[0x10];
e281682b 671
b4ff3a36 672 u8 reserved_at_a0[0x10];
f91e6d89
EBE		 673 u8 atomic_size_qp[0x10];
674
b4ff3a36 675 u8 reserved_at_c0[0x10];
e281682b
SM		 676 u8 atomic_size_dc[0x10];
677
b4ff3a36 678 u8 reserved_at_e0[0x720];
e281682b
SM		 679};
680
681struct mlx5_ifc_odp_cap_bits {
b4ff3a36 682 u8 reserved_at_0[0x40];
e281682b
SM		 683
684 u8 sig[0x1];
b4ff3a36 685 u8 reserved_at_41[0x1f];
e281682b 686
b4ff3a36 687 u8 reserved_at_60[0x20];
e281682b
SM		 688
689 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
690
691 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
692
693 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
694
b4ff3a36 695 u8 reserved_at_e0[0x720];
e281682b
SM		 696};
697
3f0393a5
SG		 698struct mlx5_ifc_calc_op {
699 u8 reserved_at_0[0x10];
700 u8 reserved_at_10[0x9];
701 u8 op_swap_endianness[0x1];
702 u8 op_min[0x1];
703 u8 op_xor[0x1];
704 u8 op_or[0x1];
705 u8 op_and[0x1];
706 u8 op_max[0x1];
707 u8 op_add[0x1];
708};
709
710struct mlx5_ifc_vector_calc_cap_bits {
711 u8 calc_matrix[0x1];
712 u8 reserved_at_1[0x1f];
713 u8 reserved_at_20[0x8];
714 u8 max_vec_count[0x8];
715 u8 reserved_at_30[0xd];
716 u8 max_chunk_size[0x3];
717 struct mlx5_ifc_calc_op calc0;
718 struct mlx5_ifc_calc_op calc1;
719 struct mlx5_ifc_calc_op calc2;
720 struct mlx5_ifc_calc_op calc3;
721
722 u8 reserved_at_e0[0x720];
723};
724
e281682b
SM		 725enum {
726 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
727 MLX5_WQ_TYPE_CYCLIC = 0x1,
7d5e1423 728 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
e281682b
SM		 729};
730
731enum {
732 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
733 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
734};
735
736enum {
737 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
738 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
739 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
740 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
741 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
742};
743
744enum {
745 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
746 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
747 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
748 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
749 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
750 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
751};
752
753enum {
754 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
755 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
756};
757
758enum {
759 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
760 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
761 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
762};
763
764enum {
765 MLX5_CAP_PORT_TYPE_IB = 0x0,
766 MLX5_CAP_PORT_TYPE_ETH = 0x1,
d29b796a
EC		 767};
768
b775516b 769struct mlx5_ifc_cmd_hca_cap_bits {
b4ff3a36 770 u8 reserved_at_0[0x80];
b775516b
EC		 771
772 u8 log_max_srq_sz[0x8];
773 u8 log_max_qp_sz[0x8];
b4ff3a36 774 u8 reserved_at_90[0xb];
b775516b
EC		 775 u8 log_max_qp[0x5];
776
b4ff3a36 777 u8 reserved_at_a0[0xb];
e281682b 778 u8 log_max_srq[0x5];
b4ff3a36 779 u8 reserved_at_b0[0x10];
b775516b 780
b4ff3a36 781 u8 reserved_at_c0[0x8];
b775516b 782 u8 log_max_cq_sz[0x8];
b4ff3a36 783 u8 reserved_at_d0[0xb];
b775516b
EC		 784 u8 log_max_cq[0x5];
785
786 u8 log_max_eq_sz[0x8];
b4ff3a36 787 u8 reserved_at_e8[0x2];
b775516b 788 u8 log_max_mkey[0x6];
b4ff3a36 789 u8 reserved_at_f0[0xc];
b775516b
EC		 790 u8 log_max_eq[0x4];
791
792 u8 max_indirection[0x8];
bcda1aca 793 u8 fixed_buffer_size[0x1];
b775516b 794 u8 log_max_mrw_sz[0x7];
b4ff3a36 795 u8 reserved_at_110[0x2];
b775516b 796 u8 log_max_bsf_list_size[0x6];
bcda1aca
AK		 797 u8 umr_extended_translation_offset[0x1];
798 u8 null_mkey[0x1];
b775516b
EC		 799 u8 log_max_klm_list_size[0x6];
800
b4ff3a36 801 u8 reserved_at_120[0xa];
b775516b 802 u8 log_max_ra_req_dc[0x6];
b4ff3a36 803 u8 reserved_at_130[0xa];
b775516b
EC		 804 u8 log_max_ra_res_dc[0x6];
805
b4ff3a36 806 u8 reserved_at_140[0xa];
b775516b 807 u8 log_max_ra_req_qp[0x6];
b4ff3a36 808 u8 reserved_at_150[0xa];
b775516b
EC		 809 u8 log_max_ra_res_qp[0x6];
810
f32f5bd2 811 u8 end_pad[0x1];
b775516b
EC		 812 u8 cc_query_allowed[0x1];
813 u8 cc_modify_allowed[0x1];
f32f5bd2
DJ		 814 u8 start_pad[0x1];
815 u8 cache_line_128byte[0x1];
816 u8 reserved_at_163[0xb];
e281682b 817 u8 gid_table_size[0x10];
b775516b 818
e281682b
SM		 819 u8 out_of_seq_cnt[0x1];
820 u8 vport_counters[0x1];
7486216b 821 u8 retransmission_q_counters[0x1];
83b502a1
AV		 822 u8 reserved_at_183[0x1];
823 u8 modify_rq_counter_set_id[0x1];
824 u8 reserved_at_185[0x1];
b775516b
EC		 825 u8 max_qp_cnt[0xa];
826 u8 pkey_table_size[0x10];
827
e281682b
SM		 828 u8 vport_group_manager[0x1];
829 u8 vhca_group_manager[0x1];
830 u8 ib_virt[0x1];
831 u8 eth_virt[0x1];
b4ff3a36 832 u8 reserved_at_1a4[0x1];
e281682b
SM		 833 u8 ets[0x1];
834 u8 nic_flow_table[0x1];
54f0a411 835 u8 eswitch_flow_table[0x1];
e1c9c62b 836 u8 early_vf_enable[0x1];
cfdcbcea
GP		 837 u8 mcam_reg[0x1];
838 u8 pcam_reg[0x1];
b775516b 839 u8 local_ca_ack_delay[0x5];
4ce3bf2f 840 u8 port_module_event[0x1];
7b13558f 841 u8 reserved_at_1b1[0x1];
7d5e1423 842 u8 ports_check[0x1];
7b13558f 843 u8 reserved_at_1b3[0x1];
7d5e1423
SM		 844 u8 disable_link_up[0x1];
845 u8 beacon_led[0x1];
e281682b 846 u8 port_type[0x2];
b775516b
EC		 847 u8 num_ports[0x8];
848
f9a1ef72
EE		 849 u8 reserved_at_1c0[0x1];
850 u8 pps[0x1];
851 u8 pps_modify[0x1];
b775516b 852 u8 log_max_msg[0x5];
e1c9c62b 853 u8 reserved_at_1c8[0x4];
4f3961ee 854 u8 max_tc[0x4];
7486216b
SM		 855 u8 reserved_at_1d0[0x1];
856 u8 dcbx[0x1];
857 u8 reserved_at_1d2[0x4];
928cfe87
TT		 858 u8 rol_s[0x1];
859 u8 rol_g[0x1];
e1c9c62b 860 u8 reserved_at_1d8[0x1];
928cfe87
TT		 861 u8 wol_s[0x1];
862 u8 wol_g[0x1];
863 u8 wol_a[0x1];
864 u8 wol_b[0x1];
865 u8 wol_m[0x1];
866 u8 wol_u[0x1];
867 u8 wol_p[0x1];
b775516b
EC		 868
869 u8 stat_rate_support[0x10];
e1c9c62b 870 u8 reserved_at_1f0[0xc];
e281682b 871 u8 cqe_version[0x4];
b775516b 872
e281682b 873 u8 compact_address_vector[0x1];
7d5e1423 874 u8 striding_rq[0x1];
500a3d0d
ES		 875 u8 reserved_at_202[0x1];
876 u8 ipoib_enhanced_offloads[0x1];
1015c2e8 877 u8 ipoib_basic_offloads[0x1];
e1c9c62b 878 u8 reserved_at_205[0xa];
e281682b 879 u8 drain_sigerr[0x1];
b775516b
EC		 880 u8 cmdif_checksum[0x2];
881 u8 sigerr_cqe[0x1];
e1c9c62b 882 u8 reserved_at_213[0x1];
b775516b
EC		 883 u8 wq_signature[0x1];
884 u8 sctr_data_cqe[0x1];
e1c9c62b 885 u8 reserved_at_216[0x1];
b775516b
EC		 886 u8 sho[0x1];
887 u8 tph[0x1];
888 u8 rf[0x1];
e281682b 889 u8 dct[0x1];
7486216b 890 u8 qos[0x1];
e281682b 891 u8 eth_net_offloads[0x1];
b775516b
EC		 892 u8 roce[0x1];
893 u8 atomic[0x1];
e1c9c62b 894 u8 reserved_at_21f[0x1];
b775516b
EC		 895
896 u8 cq_oi[0x1];
897 u8 cq_resize[0x1];
898 u8 cq_moderation[0x1];
e1c9c62b 899 u8 reserved_at_223[0x3];
e281682b 900 u8 cq_eq_remap[0x1];
b775516b
EC		 901 u8 pg[0x1];
902 u8 block_lb_mc[0x1];
e1c9c62b 903 u8 reserved_at_229[0x1];
e281682b 904 u8 scqe_break_moderation[0x1];
7d5e1423 905 u8 cq_period_start_from_cqe[0x1];
b775516b 906 u8 cd[0x1];
e1c9c62b 907 u8 reserved_at_22d[0x1];
b775516b 908 u8 apm[0x1];
3f0393a5 909 u8 vector_calc[0x1];
7d5e1423 910 u8 umr_ptr_rlky[0x1];
d2370e0a 911 u8 imaicl[0x1];
e1c9c62b 912 u8 reserved_at_232[0x4];
b775516b
EC		 913 u8 qkv[0x1];
914 u8 pkv[0x1];
b11a4f9c
HE		 915 u8 set_deth_sqpn[0x1];
916 u8 reserved_at_239[0x3];
b775516b
EC		 917 u8 xrc[0x1];
918 u8 ud[0x1];
919 u8 uc[0x1];
920 u8 rc[0x1];
921
a6d51b68
EC		 922 u8 uar_4k[0x1];
923 u8 reserved_at_241[0x9];
b775516b 924 u8 uar_sz[0x6];
e1c9c62b 925 u8 reserved_at_250[0x8];
b775516b
EC		 926 u8 log_pg_sz[0x8];
927
928 u8 bf[0x1];
0dbc6fe0 929 u8 driver_version[0x1];
e281682b 930 u8 pad_tx_eth_packet[0x1];
e1c9c62b 931 u8 reserved_at_263[0x8];
b775516b 932 u8 log_bf_reg_size[0x5];
84df61eb
AH		 933
934 u8 reserved_at_270[0xb];
935 u8 lag_master[0x1];
936 u8 num_lag_ports[0x4];
b775516b 937
e1c9c62b 938 u8 reserved_at_280[0x10];
b775516b
EC		 939 u8 max_wqe_sz_sq[0x10];
940
e1c9c62b 941 u8 reserved_at_2a0[0x10];
b775516b
EC		 942 u8 max_wqe_sz_rq[0x10];
943
e1c9c62b 944 u8 reserved_at_2c0[0x10];
b775516b
EC		 945 u8 max_wqe_sz_sq_dc[0x10];
946
e1c9c62b 947 u8 reserved_at_2e0[0x7];
b775516b
EC		 948 u8 max_qp_mcg[0x19];
949
e1c9c62b 950 u8 reserved_at_300[0x18];
b775516b
EC		 951 u8 log_max_mcg[0x8];
952
e1c9c62b 953 u8 reserved_at_320[0x3];
e281682b 954 u8 log_max_transport_domain[0x5];
e1c9c62b 955 u8 reserved_at_328[0x3];
b775516b 956 u8 log_max_pd[0x5];
e1c9c62b 957 u8 reserved_at_330[0xb];
b775516b
EC		 958 u8 log_max_xrcd[0x5];
959
a351a1b0
AV		 960 u8 reserved_at_340[0x8];
961 u8 log_max_flow_counter_bulk[0x8];
962 u8 max_flow_counter[0x10];
963
b775516b 964
e1c9c62b 965 u8 reserved_at_360[0x3];
b775516b 966 u8 log_max_rq[0x5];
e1c9c62b 967 u8 reserved_at_368[0x3];
b775516b 968 u8 log_max_sq[0x5];
e1c9c62b 969 u8 reserved_at_370[0x3];
b775516b 970 u8 log_max_tir[0x5];
e1c9c62b 971 u8 reserved_at_378[0x3];
b775516b
EC		 972 u8 log_max_tis[0x5];
973
e281682b 974 u8 basic_cyclic_rcv_wqe[0x1];
e1c9c62b 975 u8 reserved_at_381[0x2];
e281682b 976 u8 log_max_rmp[0x5];
e1c9c62b 977 u8 reserved_at_388[0x3];
e281682b 978 u8 log_max_rqt[0x5];
e1c9c62b 979 u8 reserved_at_390[0x3];
e281682b 980 u8 log_max_rqt_size[0x5];
e1c9c62b 981 u8 reserved_at_398[0x3];
b775516b
EC		 982 u8 log_max_tis_per_sq[0x5];
983
e1c9c62b 984 u8 reserved_at_3a0[0x3];
e281682b 985 u8 log_max_stride_sz_rq[0x5];
e1c9c62b 986 u8 reserved_at_3a8[0x3];
e281682b 987 u8 log_min_stride_sz_rq[0x5];
e1c9c62b 988 u8 reserved_at_3b0[0x3];
e281682b 989 u8 log_max_stride_sz_sq[0x5];
e1c9c62b 990 u8 reserved_at_3b8[0x3];
e281682b
SM		 991 u8 log_min_stride_sz_sq[0x5];
992
e1c9c62b 993 u8 reserved_at_3c0[0x1b];
e281682b
SM		 994 u8 log_max_wq_sz[0x5];
995
54f0a411 996 u8 nic_vport_change_event[0x1];
e1c9c62b 997 u8 reserved_at_3e1[0xa];
54f0a411 998 u8 log_max_vlan_list[0x5];
e1c9c62b 999 u8 reserved_at_3f0[0x3];
54f0a411 1000 u8 log_max_current_mc_list[0x5];
e1c9c62b 1001 u8 reserved_at_3f8[0x3];
54f0a411
SM		 1002 u8 log_max_current_uc_list[0x5];
1003
e1c9c62b 1004 u8 reserved_at_400[0x80];
54f0a411 1005
e1c9c62b 1006 u8 reserved_at_480[0x3];
e281682b 1007 u8 log_max_l2_table[0x5];
e1c9c62b 1008 u8 reserved_at_488[0x8];
b775516b
EC		 1009 u8 log_uar_page_sz[0x10];
1010
e1c9c62b 1011 u8 reserved_at_4a0[0x20];
048ccca8 1012 u8 device_frequency_mhz[0x20];
b0844444 1013 u8 device_frequency_khz[0x20];
e1c9c62b 1014
a6d51b68
EC		 1015 u8 reserved_at_500[0x20];
1016 u8 num_of_uars_per_page[0x20];
1017 u8 reserved_at_540[0x40];
e1c9c62b
TT		 1018
1019 u8 reserved_at_580[0x3f];
7d5e1423 1020 u8 cqe_compression[0x1];
b775516b 1021
7d5e1423
SM		 1022 u8 cqe_compression_timeout[0x10];
1023 u8 cqe_compression_max_num[0x10];
b775516b 1024
7486216b
SM		 1025 u8 reserved_at_5e0[0x10];
1026 u8 tag_matching[0x1];
1027 u8 rndv_offload_rc[0x1];
1028 u8 rndv_offload_dc[0x1];
1029 u8 log_tag_matching_list_sz[0x5];
7b13558f 1030 u8 reserved_at_5f8[0x3];
7486216b
SM		 1031 u8 log_max_xrq[0x5];
1032
7b13558f 1033 u8 reserved_at_600[0x200];
b775516b
EC		 1034};
1035
81848731
SM		 1036enum mlx5_flow_destination_type {
1037 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1038 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1039 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
bd5251db
AV		 1040
1041 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
e281682b 1042};
b775516b 1043
e281682b
SM		 1044struct mlx5_ifc_dest_format_struct_bits {
1045 u8 destination_type[0x8];
1046 u8 destination_id[0x18];
b775516b 1047
b4ff3a36 1048 u8 reserved_at_20[0x20];
e281682b
SM		 1049};
1050
9dc0b289 1051struct mlx5_ifc_flow_counter_list_bits {
a351a1b0
AV		 1052 u8 clear[0x1];
1053 u8 num_of_counters[0xf];
9dc0b289
AV		 1054 u8 flow_counter_id[0x10];
1055
1056 u8 reserved_at_20[0x20];
1057};
1058
1059union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1060 struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1061 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1062 u8 reserved_at_0[0x40];
1063};
1064
e281682b
SM		 1065struct mlx5_ifc_fte_match_param_bits {
1066 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1067
1068 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1069
1070 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
b775516b 1071
b4ff3a36 1072 u8 reserved_at_600[0xa00];
b775516b
EC		 1073};
1074
e281682b
SM		 1075enum {
1076 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1077 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1078 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1079 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1080 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1081};
b775516b 1082
e281682b
SM		 1083struct mlx5_ifc_rx_hash_field_select_bits {
1084 u8 l3_prot_type[0x1];
1085 u8 l4_prot_type[0x1];
1086 u8 selected_fields[0x1e];
1087};
b775516b 1088
e281682b
SM		 1089enum {
1090 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
1091 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
b775516b
EC		 1092};
1093
e281682b
SM		 1094enum {
1095 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
1096 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
1097};
1098
1099struct mlx5_ifc_wq_bits {
1100 u8 wq_type[0x4];
1101 u8 wq_signature[0x1];
1102 u8 end_padding_mode[0x2];
1103 u8 cd_slave[0x1];
b4ff3a36 1104 u8 reserved_at_8[0x18];
b775516b 1105
e281682b
SM		 1106 u8 hds_skip_first_sge[0x1];
1107 u8 log2_hds_buf_size[0x3];
b4ff3a36 1108 u8 reserved_at_24[0x7];
e281682b
SM		 1109 u8 page_offset[0x5];
1110 u8 lwm[0x10];
b775516b 1111
b4ff3a36 1112 u8 reserved_at_40[0x8];
e281682b
SM		 1113 u8 pd[0x18];
1114
b4ff3a36 1115 u8 reserved_at_60[0x8];
e281682b
SM		 1116 u8 uar_page[0x18];
1117
1118 u8 dbr_addr[0x40];
1119
1120 u8 hw_counter[0x20];
1121
1122 u8 sw_counter[0x20];
1123
b4ff3a36 1124 u8 reserved_at_100[0xc];
e281682b 1125 u8 log_wq_stride[0x4];
b4ff3a36 1126 u8 reserved_at_110[0x3];
e281682b 1127 u8 log_wq_pg_sz[0x5];
b4ff3a36 1128 u8 reserved_at_118[0x3];
e281682b
SM		 1129 u8 log_wq_sz[0x5];
1130
7d5e1423
SM		 1131 u8 reserved_at_120[0x15];
1132 u8 log_wqe_num_of_strides[0x3];
1133 u8 two_byte_shift_en[0x1];
1134 u8 reserved_at_139[0x4];
1135 u8 log_wqe_stride_size[0x3];
1136
1137 u8 reserved_at_140[0x4c0];
b775516b 1138
e281682b 1139 struct mlx5_ifc_cmd_pas_bits pas[0];
b775516b
EC		 1140};
1141
e281682b 1142struct mlx5_ifc_rq_num_bits {
b4ff3a36 1143 u8 reserved_at_0[0x8];
e281682b
SM		 1144 u8 rq_num[0x18];
1145};
b775516b 1146
e281682b 1147struct mlx5_ifc_mac_address_layout_bits {
b4ff3a36 1148 u8 reserved_at_0[0x10];
e281682b 1149 u8 mac_addr_47_32[0x10];
b775516b 1150
e281682b
SM		 1151 u8 mac_addr_31_0[0x20];
1152};
1153
c0046cf7 1154struct mlx5_ifc_vlan_layout_bits {
b4ff3a36 1155 u8 reserved_at_0[0x14];
c0046cf7
SM		 1156 u8 vlan[0x0c];
1157
b4ff3a36 1158 u8 reserved_at_20[0x20];
c0046cf7
SM		 1159};
1160
e281682b 1161struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
b4ff3a36 1162 u8 reserved_at_0[0xa0];
e281682b
SM		 1163
1164 u8 min_time_between_cnps[0x20];
1165
b4ff3a36 1166 u8 reserved_at_c0[0x12];
e281682b 1167 u8 cnp_dscp[0x6];
b4ff3a36 1168 u8 reserved_at_d8[0x5];
e281682b
SM		 1169 u8 cnp_802p_prio[0x3];
1170
b4ff3a36 1171 u8 reserved_at_e0[0x720];
e281682b
SM		 1172};
1173
1174struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
b4ff3a36 1175 u8 reserved_at_0[0x60];
e281682b 1176
b4ff3a36 1177 u8 reserved_at_60[0x4];
e281682b 1178 u8 clamp_tgt_rate[0x1];
b4ff3a36 1179 u8 reserved_at_65[0x3];
e281682b 1180 u8 clamp_tgt_rate_after_time_inc[0x1];
b4ff3a36 1181 u8 reserved_at_69[0x17];
e281682b 1182
b4ff3a36 1183 u8 reserved_at_80[0x20];
e281682b
SM		 1184
1185 u8 rpg_time_reset[0x20];
1186
1187 u8 rpg_byte_reset[0x20];
1188
1189 u8 rpg_threshold[0x20];
1190
1191 u8 rpg_max_rate[0x20];
1192
1193 u8 rpg_ai_rate[0x20];
1194
1195 u8 rpg_hai_rate[0x20];
1196
1197 u8 rpg_gd[0x20];
1198
1199 u8 rpg_min_dec_fac[0x20];
1200
1201 u8 rpg_min_rate[0x20];
1202
b4ff3a36 1203 u8 reserved_at_1c0[0xe0];
e281682b
SM		 1204
1205 u8 rate_to_set_on_first_cnp[0x20];
1206
1207 u8 dce_tcp_g[0x20];
1208
1209 u8 dce_tcp_rtt[0x20];
1210
1211 u8 rate_reduce_monitor_period[0x20];
1212
b4ff3a36 1213 u8 reserved_at_320[0x20];
e281682b
SM		 1214
1215 u8 initial_alpha_value[0x20];
1216
b4ff3a36 1217 u8 reserved_at_360[0x4a0];
e281682b
SM		 1218};
1219
1220struct mlx5_ifc_cong_control_802_1qau_rp_bits {
b4ff3a36 1221 u8 reserved_at_0[0x80];
e281682b
SM		 1222
1223 u8 rppp_max_rps[0x20];
1224
1225 u8 rpg_time_reset[0x20];
1226
1227 u8 rpg_byte_reset[0x20];
1228
1229 u8 rpg_threshold[0x20];
1230
1231 u8 rpg_max_rate[0x20];
1232
1233 u8 rpg_ai_rate[0x20];
1234
1235 u8 rpg_hai_rate[0x20];
1236
1237 u8 rpg_gd[0x20];
1238
1239 u8 rpg_min_dec_fac[0x20];
1240
1241 u8 rpg_min_rate[0x20];
1242
b4ff3a36 1243 u8 reserved_at_1c0[0x640];
e281682b
SM		 1244};
1245
1246enum {
1247 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1248 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1249 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1250};
1251
1252struct mlx5_ifc_resize_field_select_bits {
1253 u8 resize_field_select[0x20];
1254};
1255
1256enum {
1257 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1258 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1259 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1260 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1261};
1262
1263struct mlx5_ifc_modify_field_select_bits {
1264 u8 modify_field_select[0x20];
1265};
1266
1267struct mlx5_ifc_field_select_r_roce_np_bits {
1268 u8 field_select_r_roce_np[0x20];
1269};
1270
1271struct mlx5_ifc_field_select_r_roce_rp_bits {
1272 u8 field_select_r_roce_rp[0x20];
1273};
1274
1275enum {
1276 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1277 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1278 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1279 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1280 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1281 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1282 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1283 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1284 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1285 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1286};
1287
1288struct mlx5_ifc_field_select_802_1qau_rp_bits {
1289 u8 field_select_8021qaurp[0x20];
1290};
1291
1292struct mlx5_ifc_phys_layer_cntrs_bits {
1293 u8 time_since_last_clear_high[0x20];
1294
1295 u8 time_since_last_clear_low[0x20];
1296
1297 u8 symbol_errors_high[0x20];
1298
1299 u8 symbol_errors_low[0x20];
1300
1301 u8 sync_headers_errors_high[0x20];
1302
1303 u8 sync_headers_errors_low[0x20];
1304
1305 u8 edpl_bip_errors_lane0_high[0x20];
1306
1307 u8 edpl_bip_errors_lane0_low[0x20];
1308
1309 u8 edpl_bip_errors_lane1_high[0x20];
1310
1311 u8 edpl_bip_errors_lane1_low[0x20];
1312
1313 u8 edpl_bip_errors_lane2_high[0x20];
1314
1315 u8 edpl_bip_errors_lane2_low[0x20];
1316
1317 u8 edpl_bip_errors_lane3_high[0x20];
1318
1319 u8 edpl_bip_errors_lane3_low[0x20];
1320
1321 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1322
1323 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1324
1325 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1326
1327 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1328
1329 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1330
1331 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1332
1333 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1334
1335 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1336
1337 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1338
1339 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1340
1341 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1342
1343 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1344
1345 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1346
1347 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1348
1349 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1350
1351 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1352
1353 u8 rs_fec_corrected_blocks_high[0x20];
1354
1355 u8 rs_fec_corrected_blocks_low[0x20];
1356
1357 u8 rs_fec_uncorrectable_blocks_high[0x20];
1358
1359 u8 rs_fec_uncorrectable_blocks_low[0x20];
1360
1361 u8 rs_fec_no_errors_blocks_high[0x20];
1362
1363 u8 rs_fec_no_errors_blocks_low[0x20];
1364
1365 u8 rs_fec_single_error_blocks_high[0x20];
1366
1367 u8 rs_fec_single_error_blocks_low[0x20];
1368
1369 u8 rs_fec_corrected_symbols_total_high[0x20];
1370
1371 u8 rs_fec_corrected_symbols_total_low[0x20];
1372
1373 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1374
1375 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1376
1377 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1378
1379 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1380
1381 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1382
1383 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1384
1385 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1386
1387 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1388
1389 u8 link_down_events[0x20];
1390
1391 u8 successful_recovery_events[0x20];
1392
b4ff3a36 1393 u8 reserved_at_640[0x180];
e281682b
SM		 1394};
1395
d8dc0508
GP		 1396struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1397 u8 time_since_last_clear_high[0x20];
1398
1399 u8 time_since_last_clear_low[0x20];
1400
1401 u8 phy_received_bits_high[0x20];
1402
1403 u8 phy_received_bits_low[0x20];
1404
1405 u8 phy_symbol_errors_high[0x20];
1406
1407 u8 phy_symbol_errors_low[0x20];
1408
1409 u8 phy_corrected_bits_high[0x20];
1410
1411 u8 phy_corrected_bits_low[0x20];
1412
1413 u8 phy_corrected_bits_lane0_high[0x20];
1414
1415 u8 phy_corrected_bits_lane0_low[0x20];
1416
1417 u8 phy_corrected_bits_lane1_high[0x20];
1418
1419 u8 phy_corrected_bits_lane1_low[0x20];
1420
1421 u8 phy_corrected_bits_lane2_high[0x20];
1422
1423 u8 phy_corrected_bits_lane2_low[0x20];
1424
1425 u8 phy_corrected_bits_lane3_high[0x20];
1426
1427 u8 phy_corrected_bits_lane3_low[0x20];
1428
1429 u8 reserved_at_200[0x5c0];
1430};
1431
1c64bf6f
MY		 1432struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1433 u8 symbol_error_counter[0x10];
1434
1435 u8 link_error_recovery_counter[0x8];
1436
1437 u8 link_downed_counter[0x8];
1438
1439 u8 port_rcv_errors[0x10];
1440
1441 u8 port_rcv_remote_physical_errors[0x10];
1442
1443 u8 port_rcv_switch_relay_errors[0x10];
1444
1445 u8 port_xmit_discards[0x10];
1446
1447 u8 port_xmit_constraint_errors[0x8];
1448
1449 u8 port_rcv_constraint_errors[0x8];
1450
1451 u8 reserved_at_70[0x8];
1452
1453 u8 link_overrun_errors[0x8];
1454
1455 u8 reserved_at_80[0x10];
1456
1457 u8 vl_15_dropped[0x10];
1458
1459 u8 reserved_at_a0[0xa0];
1460};
1461
e281682b
SM		 1462struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1463 u8 transmit_queue_high[0x20];
1464
1465 u8 transmit_queue_low[0x20];
1466
b4ff3a36 1467 u8 reserved_at_40[0x780];
e281682b
SM		 1468};
1469
1470struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1471 u8 rx_octets_high[0x20];
1472
1473 u8 rx_octets_low[0x20];
1474
b4ff3a36 1475 u8 reserved_at_40[0xc0];
e281682b
SM		 1476
1477 u8 rx_frames_high[0x20];
1478
1479 u8 rx_frames_low[0x20];
1480
1481 u8 tx_octets_high[0x20];
1482
1483 u8 tx_octets_low[0x20];
1484
b4ff3a36 1485 u8 reserved_at_180[0xc0];
e281682b
SM		 1486
1487 u8 tx_frames_high[0x20];
1488
1489 u8 tx_frames_low[0x20];
1490
1491 u8 rx_pause_high[0x20];
1492
1493 u8 rx_pause_low[0x20];
1494
1495 u8 rx_pause_duration_high[0x20];
1496
1497 u8 rx_pause_duration_low[0x20];
1498
1499 u8 tx_pause_high[0x20];
1500
1501 u8 tx_pause_low[0x20];
1502
1503 u8 tx_pause_duration_high[0x20];
1504
1505 u8 tx_pause_duration_low[0x20];
1506
1507 u8 rx_pause_transition_high[0x20];
1508
1509 u8 rx_pause_transition_low[0x20];
1510
b4ff3a36 1511 u8 reserved_at_3c0[0x400];
e281682b
SM		 1512};
1513
1514struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1515 u8 port_transmit_wait_high[0x20];
1516
1517 u8 port_transmit_wait_low[0x20];
1518
b4ff3a36 1519 u8 reserved_at_40[0x780];
e281682b
SM		 1520};
1521
1522struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1523 u8 dot3stats_alignment_errors_high[0x20];
1524
1525 u8 dot3stats_alignment_errors_low[0x20];
1526
1527 u8 dot3stats_fcs_errors_high[0x20];
1528
1529 u8 dot3stats_fcs_errors_low[0x20];
1530
1531 u8 dot3stats_single_collision_frames_high[0x20];
1532
1533 u8 dot3stats_single_collision_frames_low[0x20];
1534
1535 u8 dot3stats_multiple_collision_frames_high[0x20];
1536
1537 u8 dot3stats_multiple_collision_frames_low[0x20];
1538
1539 u8 dot3stats_sqe_test_errors_high[0x20];
1540
1541 u8 dot3stats_sqe_test_errors_low[0x20];
1542
1543 u8 dot3stats_deferred_transmissions_high[0x20];
1544
1545 u8 dot3stats_deferred_transmissions_low[0x20];
1546
1547 u8 dot3stats_late_collisions_high[0x20];
1548
1549 u8 dot3stats_late_collisions_low[0x20];
1550
1551 u8 dot3stats_excessive_collisions_high[0x20];
1552
1553 u8 dot3stats_excessive_collisions_low[0x20];
1554
1555 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1556
1557 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1558
1559 u8 dot3stats_carrier_sense_errors_high[0x20];
1560
1561 u8 dot3stats_carrier_sense_errors_low[0x20];
1562
1563 u8 dot3stats_frame_too_longs_high[0x20];
1564
1565 u8 dot3stats_frame_too_longs_low[0x20];
1566
1567 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1568
1569 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1570
1571 u8 dot3stats_symbol_errors_high[0x20];
1572
1573 u8 dot3stats_symbol_errors_low[0x20];
1574
1575 u8 dot3control_in_unknown_opcodes_high[0x20];
1576
1577 u8 dot3control_in_unknown_opcodes_low[0x20];
1578
1579 u8 dot3in_pause_frames_high[0x20];
1580
1581 u8 dot3in_pause_frames_low[0x20];
1582
1583 u8 dot3out_pause_frames_high[0x20];
1584
1585 u8 dot3out_pause_frames_low[0x20];
1586
b4ff3a36 1587 u8 reserved_at_400[0x3c0];
e281682b
SM		 1588};
1589
1590struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1591 u8 ether_stats_drop_events_high[0x20];
1592
1593 u8 ether_stats_drop_events_low[0x20];
1594
1595 u8 ether_stats_octets_high[0x20];
1596
1597 u8 ether_stats_octets_low[0x20];
1598
1599 u8 ether_stats_pkts_high[0x20];
1600
1601 u8 ether_stats_pkts_low[0x20];
1602
1603 u8 ether_stats_broadcast_pkts_high[0x20];
1604
1605 u8 ether_stats_broadcast_pkts_low[0x20];
1606
1607 u8 ether_stats_multicast_pkts_high[0x20];
1608
1609 u8 ether_stats_multicast_pkts_low[0x20];
1610
1611 u8 ether_stats_crc_align_errors_high[0x20];
1612
1613 u8 ether_stats_crc_align_errors_low[0x20];
1614
1615 u8 ether_stats_undersize_pkts_high[0x20];
1616
1617 u8 ether_stats_undersize_pkts_low[0x20];
1618
1619 u8 ether_stats_oversize_pkts_high[0x20];
1620
1621 u8 ether_stats_oversize_pkts_low[0x20];
1622
1623 u8 ether_stats_fragments_high[0x20];
1624
1625 u8 ether_stats_fragments_low[0x20];
1626
1627 u8 ether_stats_jabbers_high[0x20];
1628
1629 u8 ether_stats_jabbers_low[0x20];
1630
1631 u8 ether_stats_collisions_high[0x20];
1632
1633 u8 ether_stats_collisions_low[0x20];
1634
1635 u8 ether_stats_pkts64octets_high[0x20];
1636
1637 u8 ether_stats_pkts64octets_low[0x20];
1638
1639 u8 ether_stats_pkts65to127octets_high[0x20];
1640
1641 u8 ether_stats_pkts65to127octets_low[0x20];
1642
1643 u8 ether_stats_pkts128to255octets_high[0x20];
1644
1645 u8 ether_stats_pkts128to255octets_low[0x20];
1646
1647 u8 ether_stats_pkts256to511octets_high[0x20];
1648
1649 u8 ether_stats_pkts256to511octets_low[0x20];
1650
1651 u8 ether_stats_pkts512to1023octets_high[0x20];
1652
1653 u8 ether_stats_pkts512to1023octets_low[0x20];
1654
1655 u8 ether_stats_pkts1024to1518octets_high[0x20];
1656
1657 u8 ether_stats_pkts1024to1518octets_low[0x20];
1658
1659 u8 ether_stats_pkts1519to2047octets_high[0x20];
1660
1661 u8 ether_stats_pkts1519to2047octets_low[0x20];
1662
1663 u8 ether_stats_pkts2048to4095octets_high[0x20];
1664
1665 u8 ether_stats_pkts2048to4095octets_low[0x20];
1666
1667 u8 ether_stats_pkts4096to8191octets_high[0x20];
1668
1669 u8 ether_stats_pkts4096to8191octets_low[0x20];
1670
1671 u8 ether_stats_pkts8192to10239octets_high[0x20];
1672
1673 u8 ether_stats_pkts8192to10239octets_low[0x20];
1674
b4ff3a36 1675 u8 reserved_at_540[0x280];
e281682b
SM		 1676};
1677
1678struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1679 u8 if_in_octets_high[0x20];
1680
1681 u8 if_in_octets_low[0x20];
1682
1683 u8 if_in_ucast_pkts_high[0x20];
1684
1685 u8 if_in_ucast_pkts_low[0x20];
1686
1687 u8 if_in_discards_high[0x20];
1688
1689 u8 if_in_discards_low[0x20];
1690
1691 u8 if_in_errors_high[0x20];
1692
1693 u8 if_in_errors_low[0x20];
1694
1695 u8 if_in_unknown_protos_high[0x20];
1696
1697 u8 if_in_unknown_protos_low[0x20];
1698
1699 u8 if_out_octets_high[0x20];
1700
1701 u8 if_out_octets_low[0x20];
1702
1703 u8 if_out_ucast_pkts_high[0x20];
1704
1705 u8 if_out_ucast_pkts_low[0x20];
1706
1707 u8 if_out_discards_high[0x20];
1708
1709 u8 if_out_discards_low[0x20];
1710
1711 u8 if_out_errors_high[0x20];
1712
1713 u8 if_out_errors_low[0x20];
1714
1715 u8 if_in_multicast_pkts_high[0x20];
1716
1717 u8 if_in_multicast_pkts_low[0x20];
1718
1719 u8 if_in_broadcast_pkts_high[0x20];
1720
1721 u8 if_in_broadcast_pkts_low[0x20];
1722
1723 u8 if_out_multicast_pkts_high[0x20];
1724
1725 u8 if_out_multicast_pkts_low[0x20];
1726
1727 u8 if_out_broadcast_pkts_high[0x20];
1728
1729 u8 if_out_broadcast_pkts_low[0x20];
1730
b4ff3a36 1731 u8 reserved_at_340[0x480];
e281682b
SM		 1732};
1733
1734struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1735 u8 a_frames_transmitted_ok_high[0x20];
1736
1737 u8 a_frames_transmitted_ok_low[0x20];
1738
1739 u8 a_frames_received_ok_high[0x20];
1740
1741 u8 a_frames_received_ok_low[0x20];
1742
1743 u8 a_frame_check_sequence_errors_high[0x20];
1744
1745 u8 a_frame_check_sequence_errors_low[0x20];
1746
1747 u8 a_alignment_errors_high[0x20];
1748
1749 u8 a_alignment_errors_low[0x20];
1750
1751 u8 a_octets_transmitted_ok_high[0x20];
1752
1753 u8 a_octets_transmitted_ok_low[0x20];
1754
1755 u8 a_octets_received_ok_high[0x20];
1756
1757 u8 a_octets_received_ok_low[0x20];
1758
1759 u8 a_multicast_frames_xmitted_ok_high[0x20];
1760
1761 u8 a_multicast_frames_xmitted_ok_low[0x20];
1762
1763 u8 a_broadcast_frames_xmitted_ok_high[0x20];
1764
1765 u8 a_broadcast_frames_xmitted_ok_low[0x20];
1766
1767 u8 a_multicast_frames_received_ok_high[0x20];
1768
1769 u8 a_multicast_frames_received_ok_low[0x20];
1770
1771 u8 a_broadcast_frames_received_ok_high[0x20];
1772
1773 u8 a_broadcast_frames_received_ok_low[0x20];
1774
1775 u8 a_in_range_length_errors_high[0x20];
1776
1777 u8 a_in_range_length_errors_low[0x20];
1778
1779 u8 a_out_of_range_length_field_high[0x20];
1780
1781 u8 a_out_of_range_length_field_low[0x20];
1782
1783 u8 a_frame_too_long_errors_high[0x20];
1784
1785 u8 a_frame_too_long_errors_low[0x20];
1786
1787 u8 a_symbol_error_during_carrier_high[0x20];
1788
1789 u8 a_symbol_error_during_carrier_low[0x20];
1790
1791 u8 a_mac_control_frames_transmitted_high[0x20];
1792
1793 u8 a_mac_control_frames_transmitted_low[0x20];
1794
1795 u8 a_mac_control_frames_received_high[0x20];
1796
1797 u8 a_mac_control_frames_received_low[0x20];
1798
1799 u8 a_unsupported_opcodes_received_high[0x20];
1800
1801 u8 a_unsupported_opcodes_received_low[0x20];
1802
1803 u8 a_pause_mac_ctrl_frames_received_high[0x20];
1804
1805 u8 a_pause_mac_ctrl_frames_received_low[0x20];
1806
1807 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
1808
1809 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
1810
b4ff3a36 1811 u8 reserved_at_4c0[0x300];
e281682b
SM		 1812};
1813
8ed1a630
GP		 1814struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
1815 u8 life_time_counter_high[0x20];
1816
1817 u8 life_time_counter_low[0x20];
1818
1819 u8 rx_errors[0x20];
1820
1821 u8 tx_errors[0x20];
1822
1823 u8 l0_to_recovery_eieos[0x20];
1824
1825 u8 l0_to_recovery_ts[0x20];
1826
1827 u8 l0_to_recovery_framing[0x20];
1828
1829 u8 l0_to_recovery_retrain[0x20];
1830
1831 u8 crc_error_dllp[0x20];
1832
1833 u8 crc_error_tlp[0x20];
1834
1835 u8 reserved_at_140[0x680];
1836};
1837
e281682b
SM		 1838struct mlx5_ifc_cmd_inter_comp_event_bits {
1839 u8 command_completion_vector[0x20];
1840
b4ff3a36 1841 u8 reserved_at_20[0xc0];
e281682b
SM		 1842};
1843
1844struct mlx5_ifc_stall_vl_event_bits {
b4ff3a36 1845 u8 reserved_at_0[0x18];
e281682b 1846 u8 port_num[0x1];
b4ff3a36 1847 u8 reserved_at_19[0x3];
e281682b
SM		 1848 u8 vl[0x4];
1849
b4ff3a36 1850 u8 reserved_at_20[0xa0];
e281682b
SM		 1851};
1852
1853struct mlx5_ifc_db_bf_congestion_event_bits {
1854 u8 event_subtype[0x8];
b4ff3a36 1855 u8 reserved_at_8[0x8];
e281682b 1856 u8 congestion_level[0x8];
b4ff3a36 1857 u8 reserved_at_18[0x8];
e281682b 1858
b4ff3a36 1859 u8 reserved_at_20[0xa0];
e281682b
SM		 1860};
1861
1862struct mlx5_ifc_gpio_event_bits {
b4ff3a36 1863 u8 reserved_at_0[0x60];
e281682b
SM		 1864
1865 u8 gpio_event_hi[0x20];
1866
1867 u8 gpio_event_lo[0x20];
1868
b4ff3a36 1869 u8 reserved_at_a0[0x40];
e281682b
SM		 1870};
1871
1872struct mlx5_ifc_port_state_change_event_bits {
b4ff3a36 1873 u8 reserved_at_0[0x40];
e281682b
SM		 1874
1875 u8 port_num[0x4];
b4ff3a36 1876 u8 reserved_at_44[0x1c];
e281682b 1877
b4ff3a36 1878 u8 reserved_at_60[0x80];
e281682b
SM		 1879};
1880
1881struct mlx5_ifc_dropped_packet_logged_bits {
b4ff3a36 1882 u8 reserved_at_0[0xe0];
e281682b
SM		 1883};
1884
1885enum {
1886 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
1887 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
1888};
1889
1890struct mlx5_ifc_cq_error_bits {
b4ff3a36 1891 u8 reserved_at_0[0x8];
e281682b
SM		 1892 u8 cqn[0x18];
1893
b4ff3a36 1894 u8 reserved_at_20[0x20];
e281682b 1895
b4ff3a36 1896 u8 reserved_at_40[0x18];
e281682b
SM		 1897 u8 syndrome[0x8];
1898
b4ff3a36 1899 u8 reserved_at_60[0x80];
e281682b
SM		 1900};
1901
1902struct mlx5_ifc_rdma_page_fault_event_bits {
1903 u8 bytes_committed[0x20];
1904
1905 u8 r_key[0x20];
1906
b4ff3a36 1907 u8 reserved_at_40[0x10];
e281682b
SM		 1908 u8 packet_len[0x10];
1909
1910 u8 rdma_op_len[0x20];
1911
1912 u8 rdma_va[0x40];
1913
b4ff3a36 1914 u8 reserved_at_c0[0x5];
e281682b
SM		 1915 u8 rdma[0x1];
1916 u8 write[0x1];
1917 u8 requestor[0x1];
1918 u8 qp_number[0x18];
1919};
1920
1921struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1922 u8 bytes_committed[0x20];
1923
b4ff3a36 1924 u8 reserved_at_20[0x10];
e281682b
SM		 1925 u8 wqe_index[0x10];
1926
b4ff3a36 1927 u8 reserved_at_40[0x10];
e281682b
SM		 1928 u8 len[0x10];
1929
b4ff3a36 1930 u8 reserved_at_60[0x60];
e281682b 1931
b4ff3a36 1932 u8 reserved_at_c0[0x5];
e281682b
SM		 1933 u8 rdma[0x1];
1934 u8 write_read[0x1];
1935 u8 requestor[0x1];
1936 u8 qpn[0x18];
1937};
1938
1939struct mlx5_ifc_qp_events_bits {
b4ff3a36 1940 u8 reserved_at_0[0xa0];
e281682b
SM		 1941
1942 u8 type[0x8];
b4ff3a36 1943 u8 reserved_at_a8[0x18];
e281682b 1944
b4ff3a36 1945 u8 reserved_at_c0[0x8];
e281682b
SM		 1946 u8 qpn_rqn_sqn[0x18];
1947};
1948
1949struct mlx5_ifc_dct_events_bits {
b4ff3a36 1950 u8 reserved_at_0[0xc0];
e281682b 1951
b4ff3a36 1952 u8 reserved_at_c0[0x8];
e281682b
SM		 1953 u8 dct_number[0x18];
1954};
1955
1956struct mlx5_ifc_comp_event_bits {
b4ff3a36 1957 u8 reserved_at_0[0xc0];
e281682b 1958
b4ff3a36 1959 u8 reserved_at_c0[0x8];
e281682b
SM		 1960 u8 cq_number[0x18];
1961};
1962
1963enum {
1964 MLX5_QPC_STATE_RST = 0x0,
1965 MLX5_QPC_STATE_INIT = 0x1,
1966 MLX5_QPC_STATE_RTR = 0x2,
1967 MLX5_QPC_STATE_RTS = 0x3,
1968 MLX5_QPC_STATE_SQER = 0x4,
1969 MLX5_QPC_STATE_ERR = 0x6,
1970 MLX5_QPC_STATE_SQD = 0x7,
1971 MLX5_QPC_STATE_SUSPENDED = 0x9,
1972};
1973
1974enum {
1975 MLX5_QPC_ST_RC = 0x0,
1976 MLX5_QPC_ST_UC = 0x1,
1977 MLX5_QPC_ST_UD = 0x2,
1978 MLX5_QPC_ST_XRC = 0x3,
1979 MLX5_QPC_ST_DCI = 0x5,
1980 MLX5_QPC_ST_QP0 = 0x7,
1981 MLX5_QPC_ST_QP1 = 0x8,
1982 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
1983 MLX5_QPC_ST_REG_UMR = 0xc,
1984};
1985
1986enum {
1987 MLX5_QPC_PM_STATE_ARMED = 0x0,
1988 MLX5_QPC_PM_STATE_REARM = 0x1,
1989 MLX5_QPC_PM_STATE_RESERVED = 0x2,
1990 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
1991};
1992
1993enum {
1994 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
1995 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
1996};
1997
1998enum {
1999 MLX5_QPC_MTU_256_BYTES = 0x1,
2000 MLX5_QPC_MTU_512_BYTES = 0x2,
2001 MLX5_QPC_MTU_1K_BYTES = 0x3,
2002 MLX5_QPC_MTU_2K_BYTES = 0x4,
2003 MLX5_QPC_MTU_4K_BYTES = 0x5,
2004 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
2005};
2006
2007enum {
2008 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
2009 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
2010 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
2011 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
2012 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
2013 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
2014 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
2015 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
2016};
2017
2018enum {
2019 MLX5_QPC_CS_REQ_DISABLE = 0x0,
2020 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
2021 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
2022};
2023
2024enum {
2025 MLX5_QPC_CS_RES_DISABLE = 0x0,
2026 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
2027 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
2028};
2029
2030struct mlx5_ifc_qpc_bits {
2031 u8 state[0x4];
84df61eb 2032 u8 lag_tx_port_affinity[0x4];
e281682b 2033 u8 st[0x8];
b4ff3a36 2034 u8 reserved_at_10[0x3];
e281682b 2035 u8 pm_state[0x2];
b4ff3a36 2036 u8 reserved_at_15[0x7];
e281682b 2037 u8 end_padding_mode[0x2];
b4ff3a36 2038 u8 reserved_at_1e[0x2];
e281682b
SM		 2039
2040 u8 wq_signature[0x1];
2041 u8 block_lb_mc[0x1];
2042 u8 atomic_like_write_en[0x1];
2043 u8 latency_sensitive[0x1];
b4ff3a36 2044 u8 reserved_at_24[0x1];
e281682b 2045 u8 drain_sigerr[0x1];
b4ff3a36 2046 u8 reserved_at_26[0x2];
e281682b
SM		 2047 u8 pd[0x18];
2048
2049 u8 mtu[0x3];
2050 u8 log_msg_max[0x5];
b4ff3a36 2051 u8 reserved_at_48[0x1];
e281682b
SM		 2052 u8 log_rq_size[0x4];
2053 u8 log_rq_stride[0x3];
2054 u8 no_sq[0x1];
2055 u8 log_sq_size[0x4];
b4ff3a36 2056 u8 reserved_at_55[0x6];
e281682b 2057 u8 rlky[0x1];
1015c2e8 2058 u8 ulp_stateless_offload_mode[0x4];
e281682b
SM		 2059
2060 u8 counter_set_id[0x8];
2061 u8 uar_page[0x18];
2062
b4ff3a36 2063 u8 reserved_at_80[0x8];
e281682b
SM		 2064 u8 user_index[0x18];
2065
b4ff3a36 2066 u8 reserved_at_a0[0x3];
e281682b
SM		 2067 u8 log_page_size[0x5];
2068 u8 remote_qpn[0x18];
2069
2070 struct mlx5_ifc_ads_bits primary_address_path;
2071
2072 struct mlx5_ifc_ads_bits secondary_address_path;
2073
2074 u8 log_ack_req_freq[0x4];
b4ff3a36 2075 u8 reserved_at_384[0x4];
e281682b 2076 u8 log_sra_max[0x3];
b4ff3a36 2077 u8 reserved_at_38b[0x2];
e281682b
SM		 2078 u8 retry_count[0x3];
2079 u8 rnr_retry[0x3];
b4ff3a36 2080 u8 reserved_at_393[0x1];
e281682b
SM		 2081 u8 fre[0x1];
2082 u8 cur_rnr_retry[0x3];
2083 u8 cur_retry_count[0x3];
b4ff3a36 2084 u8 reserved_at_39b[0x5];
e281682b 2085
b4ff3a36 2086 u8 reserved_at_3a0[0x20];
e281682b 2087
b4ff3a36 2088 u8 reserved_at_3c0[0x8];
e281682b
SM		 2089 u8 next_send_psn[0x18];
2090
b4ff3a36 2091 u8 reserved_at_3e0[0x8];
e281682b
SM		 2092 u8 cqn_snd[0x18];
2093
09a7d9ec
SM		 2094 u8 reserved_at_400[0x8];
2095 u8 deth_sqpn[0x18];
2096
2097 u8 reserved_at_420[0x20];
e281682b 2098
b4ff3a36 2099 u8 reserved_at_440[0x8];
e281682b
SM		 2100 u8 last_acked_psn[0x18];
2101
b4ff3a36 2102 u8 reserved_at_460[0x8];
e281682b
SM		 2103 u8 ssn[0x18];
2104
b4ff3a36 2105 u8 reserved_at_480[0x8];
e281682b 2106 u8 log_rra_max[0x3];
b4ff3a36 2107 u8 reserved_at_48b[0x1];
e281682b
SM		 2108 u8 atomic_mode[0x4];
2109 u8 rre[0x1];
2110 u8 rwe[0x1];
2111 u8 rae[0x1];
b4ff3a36 2112 u8 reserved_at_493[0x1];
e281682b 2113 u8 page_offset[0x6];
b4ff3a36 2114 u8 reserved_at_49a[0x3];
e281682b
SM		 2115 u8 cd_slave_receive[0x1];
2116 u8 cd_slave_send[0x1];
2117 u8 cd_master[0x1];
2118
b4ff3a36 2119 u8 reserved_at_4a0[0x3];
e281682b
SM		 2120 u8 min_rnr_nak[0x5];
2121 u8 next_rcv_psn[0x18];
2122
b4ff3a36 2123 u8 reserved_at_4c0[0x8];
e281682b
SM		 2124 u8 xrcd[0x18];
2125
b4ff3a36 2126 u8 reserved_at_4e0[0x8];
e281682b
SM		 2127 u8 cqn_rcv[0x18];
2128
2129 u8 dbr_addr[0x40];
2130
2131 u8 q_key[0x20];
2132
b4ff3a36 2133 u8 reserved_at_560[0x5];
e281682b 2134 u8 rq_type[0x3];
7486216b 2135 u8 srqn_rmpn_xrqn[0x18];
e281682b 2136
b4ff3a36 2137 u8 reserved_at_580[0x8];
e281682b
SM		 2138 u8 rmsn[0x18];
2139
2140 u8 hw_sq_wqebb_counter[0x10];
2141 u8 sw_sq_wqebb_counter[0x10];
2142
2143 u8 hw_rq_counter[0x20];
2144
2145 u8 sw_rq_counter[0x20];
2146
b4ff3a36 2147 u8 reserved_at_600[0x20];
e281682b 2148
b4ff3a36 2149 u8 reserved_at_620[0xf];
e281682b
SM		 2150 u8 cgs[0x1];
2151 u8 cs_req[0x8];
2152 u8 cs_res[0x8];
2153
2154 u8 dc_access_key[0x40];
2155
b4ff3a36 2156 u8 reserved_at_680[0xc0];
e281682b
SM		 2157};
2158
2159struct mlx5_ifc_roce_addr_layout_bits {
2160 u8 source_l3_address[16][0x8];
2161
b4ff3a36 2162 u8 reserved_at_80[0x3];
e281682b
SM		 2163 u8 vlan_valid[0x1];
2164 u8 vlan_id[0xc];
2165 u8 source_mac_47_32[0x10];
2166
2167 u8 source_mac_31_0[0x20];
2168
b4ff3a36 2169 u8 reserved_at_c0[0x14];
e281682b
SM		 2170 u8 roce_l3_type[0x4];
2171 u8 roce_version[0x8];
2172
b4ff3a36 2173 u8 reserved_at_e0[0x20];
e281682b
SM		 2174};
2175
2176union mlx5_ifc_hca_cap_union_bits {
2177 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2178 struct mlx5_ifc_odp_cap_bits odp_cap;
2179 struct mlx5_ifc_atomic_caps_bits atomic_caps;
2180 struct mlx5_ifc_roce_cap_bits roce_cap;
2181 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2182 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
495716b1 2183 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
d6666753 2184 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
3f0393a5 2185 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
7486216b 2186 struct mlx5_ifc_qos_cap_bits qos_cap;
b4ff3a36 2187 u8 reserved_at_0[0x8000];
e281682b
SM		 2188};
2189
2190enum {
2191 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
2192 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
2193 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
9dc0b289 2194 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
7adbde20
HHZ		 2195 MLX5_FLOW_CONTEXT_ACTION_ENCAP = 0x10,
2196 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
2a69cb9f 2197 MLX5_FLOW_CONTEXT_ACTION_MOD_HDR = 0x40,
e281682b
SM		 2198};
2199
2200struct mlx5_ifc_flow_context_bits {
b4ff3a36 2201 u8 reserved_at_0[0x20];
e281682b
SM		 2202
2203 u8 group_id[0x20];
2204
b4ff3a36 2205 u8 reserved_at_40[0x8];
e281682b
SM		 2206 u8 flow_tag[0x18];
2207
b4ff3a36 2208 u8 reserved_at_60[0x10];
e281682b
SM		 2209 u8 action[0x10];
2210
b4ff3a36 2211 u8 reserved_at_80[0x8];
e281682b
SM		 2212 u8 destination_list_size[0x18];
2213
9dc0b289
AV		 2214 u8 reserved_at_a0[0x8];
2215 u8 flow_counter_list_size[0x18];
2216
7adbde20
HHZ		 2217 u8 encap_id[0x20];
2218
2a69cb9f
OG		 2219 u8 modify_header_id[0x20];
2220
2221 u8 reserved_at_100[0x100];
e281682b
SM		 2222
2223 struct mlx5_ifc_fte_match_param_bits match_value;
2224
b4ff3a36 2225 u8 reserved_at_1200[0x600];
e281682b 2226
9dc0b289 2227 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
e281682b
SM		 2228};
2229
2230enum {
2231 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
2232 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
2233};
2234
2235struct mlx5_ifc_xrc_srqc_bits {
2236 u8 state[0x4];
2237 u8 log_xrc_srq_size[0x4];
b4ff3a36 2238 u8 reserved_at_8[0x18];
e281682b
SM		 2239
2240 u8 wq_signature[0x1];
2241 u8 cont_srq[0x1];
b4ff3a36 2242 u8 reserved_at_22[0x1];
e281682b
SM		 2243 u8 rlky[0x1];
2244 u8 basic_cyclic_rcv_wqe[0x1];
2245 u8 log_rq_stride[0x3];
2246 u8 xrcd[0x18];
2247
2248 u8 page_offset[0x6];
b4ff3a36 2249 u8 reserved_at_46[0x2];
e281682b
SM		 2250 u8 cqn[0x18];
2251
b4ff3a36 2252 u8 reserved_at_60[0x20];
e281682b
SM		 2253
2254 u8 user_index_equal_xrc_srqn[0x1];
b4ff3a36 2255 u8 reserved_at_81[0x1];
e281682b
SM		 2256 u8 log_page_size[0x6];
2257 u8 user_index[0x18];
2258
b4ff3a36 2259 u8 reserved_at_a0[0x20];
e281682b 2260
b4ff3a36 2261 u8 reserved_at_c0[0x8];
e281682b
SM		 2262 u8 pd[0x18];
2263
2264 u8 lwm[0x10];
2265 u8 wqe_cnt[0x10];
2266
b4ff3a36 2267 u8 reserved_at_100[0x40];
e281682b
SM		 2268
2269 u8 db_record_addr_h[0x20];
2270
2271 u8 db_record_addr_l[0x1e];
b4ff3a36 2272 u8 reserved_at_17e[0x2];
e281682b 2273
b4ff3a36 2274 u8 reserved_at_180[0x80];
e281682b
SM		 2275};
2276
2277struct mlx5_ifc_traffic_counter_bits {
2278 u8 packets[0x40];
2279
2280 u8 octets[0x40];
2281};
2282
2283struct mlx5_ifc_tisc_bits {
84df61eb
AH		 2284 u8 strict_lag_tx_port_affinity[0x1];
2285 u8 reserved_at_1[0x3];
2286 u8 lag_tx_port_affinity[0x04];
2287
2288 u8 reserved_at_8[0x4];
e281682b 2289 u8 prio[0x4];
b4ff3a36 2290 u8 reserved_at_10[0x10];
e281682b 2291
b4ff3a36 2292 u8 reserved_at_20[0x100];
e281682b 2293
b4ff3a36 2294 u8 reserved_at_120[0x8];
e281682b
SM		 2295 u8 transport_domain[0x18];
2296
500a3d0d
ES		 2297 u8 reserved_at_140[0x8];
2298 u8 underlay_qpn[0x18];
2299 u8 reserved_at_160[0x3a0];
e281682b
SM		 2300};
2301
2302enum {
2303 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2304 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2305};
2306
2307enum {
2308 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2309 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2310};
2311
2312enum {
2be6967c
SM		 2313 MLX5_RX_HASH_FN_NONE = 0x0,
2314 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
2315 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
e281682b
SM		 2316};
2317
2318enum {
2319 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1,
2320 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2,
2321};
2322
2323struct mlx5_ifc_tirc_bits {
b4ff3a36 2324 u8 reserved_at_0[0x20];
e281682b
SM		 2325
2326 u8 disp_type[0x4];
b4ff3a36 2327 u8 reserved_at_24[0x1c];
e281682b 2328
b4ff3a36 2329 u8 reserved_at_40[0x40];
e281682b 2330
b4ff3a36 2331 u8 reserved_at_80[0x4];
e281682b
SM		 2332 u8 lro_timeout_period_usecs[0x10];
2333 u8 lro_enable_mask[0x4];
2334 u8 lro_max_ip_payload_size[0x8];
2335
b4ff3a36 2336 u8 reserved_at_a0[0x40];
e281682b 2337
b4ff3a36 2338 u8 reserved_at_e0[0x8];
e281682b
SM		 2339 u8 inline_rqn[0x18];
2340
2341 u8 rx_hash_symmetric[0x1];
b4ff3a36 2342 u8 reserved_at_101[0x1];
e281682b 2343 u8 tunneled_offload_en[0x1];
b4ff3a36 2344 u8 reserved_at_103[0x5];
e281682b
SM		 2345 u8 indirect_table[0x18];
2346
2347 u8 rx_hash_fn[0x4];
b4ff3a36 2348 u8 reserved_at_124[0x2];
e281682b
SM		 2349 u8 self_lb_block[0x2];
2350 u8 transport_domain[0x18];
2351
2352 u8 rx_hash_toeplitz_key[10][0x20];
2353
2354 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2355
2356 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2357
b4ff3a36 2358 u8 reserved_at_2c0[0x4c0];
e281682b
SM		 2359};
2360
2361enum {
2362 MLX5_SRQC_STATE_GOOD = 0x0,
2363 MLX5_SRQC_STATE_ERROR = 0x1,
2364};
2365
2366struct mlx5_ifc_srqc_bits {
2367 u8 state[0x4];
2368 u8 log_srq_size[0x4];
b4ff3a36 2369 u8 reserved_at_8[0x18];
e281682b
SM		 2370
2371 u8 wq_signature[0x1];
2372 u8 cont_srq[0x1];
b4ff3a36 2373 u8 reserved_at_22[0x1];
e281682b 2374 u8 rlky[0x1];
b4ff3a36 2375 u8 reserved_at_24[0x1];
e281682b
SM		 2376 u8 log_rq_stride[0x3];
2377 u8 xrcd[0x18];
2378
2379 u8 page_offset[0x6];
b4ff3a36 2380 u8 reserved_at_46[0x2];
e281682b
SM		 2381 u8 cqn[0x18];
2382
b4ff3a36 2383 u8 reserved_at_60[0x20];
e281682b 2384
b4ff3a36 2385 u8 reserved_at_80[0x2];
e281682b 2386 u8 log_page_size[0x6];
b4ff3a36 2387 u8 reserved_at_88[0x18];
e281682b 2388
b4ff3a36 2389 u8 reserved_at_a0[0x20];
e281682b 2390
b4ff3a36 2391 u8 reserved_at_c0[0x8];
e281682b
SM		 2392 u8 pd[0x18];
2393
2394 u8 lwm[0x10];
2395 u8 wqe_cnt[0x10];
2396
b4ff3a36 2397 u8 reserved_at_100[0x40];
e281682b 2398
01949d01 2399 u8 dbr_addr[0x40];
e281682b 2400
b4ff3a36 2401 u8 reserved_at_180[0x80];
e281682b
SM		 2402};
2403
2404enum {
2405 MLX5_SQC_STATE_RST = 0x0,
2406 MLX5_SQC_STATE_RDY = 0x1,
2407 MLX5_SQC_STATE_ERR = 0x3,
2408};
2409
2410struct mlx5_ifc_sqc_bits {
2411 u8 rlky[0x1];
2412 u8 cd_master[0x1];
2413 u8 fre[0x1];
2414 u8 flush_in_error_en[0x1];
cff92d7c
HHZ		 2415 u8 reserved_at_4[0x1];
2416 u8 min_wqe_inline_mode[0x3];
e281682b 2417 u8 state[0x4];
7d5e1423
SM		 2418 u8 reg_umr[0x1];
2419 u8 reserved_at_d[0x13];
e281682b 2420
b4ff3a36 2421 u8 reserved_at_20[0x8];
e281682b
SM		 2422 u8 user_index[0x18];
2423
b4ff3a36 2424 u8 reserved_at_40[0x8];
e281682b
SM		 2425 u8 cqn[0x18];
2426
7486216b 2427 u8 reserved_at_60[0x90];
e281682b 2428
7486216b 2429 u8 packet_pacing_rate_limit_index[0x10];
e281682b 2430 u8 tis_lst_sz[0x10];
b4ff3a36 2431 u8 reserved_at_110[0x10];
e281682b 2432
b4ff3a36 2433 u8 reserved_at_120[0x40];
e281682b 2434
b4ff3a36 2435 u8 reserved_at_160[0x8];
e281682b
SM		 2436 u8 tis_num_0[0x18];
2437
2438 struct mlx5_ifc_wq_bits wq;
2439};
2440
813f8540
MHY		 2441enum {
2442 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2443 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2444 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2445 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2446};
2447
2448struct mlx5_ifc_scheduling_context_bits {
2449 u8 element_type[0x8];
2450 u8 reserved_at_8[0x18];
2451
2452 u8 element_attributes[0x20];
2453
2454 u8 parent_element_id[0x20];
2455
2456 u8 reserved_at_60[0x40];
2457
2458 u8 bw_share[0x20];
2459
2460 u8 max_average_bw[0x20];
2461
2462 u8 reserved_at_e0[0x120];
2463};
2464
e281682b 2465struct mlx5_ifc_rqtc_bits {
b4ff3a36 2466 u8 reserved_at_0[0xa0];
e281682b 2467
b4ff3a36 2468 u8 reserved_at_a0[0x10];
e281682b
SM		 2469 u8 rqt_max_size[0x10];
2470
b4ff3a36 2471 u8 reserved_at_c0[0x10];
e281682b
SM		 2472 u8 rqt_actual_size[0x10];
2473
b4ff3a36 2474 u8 reserved_at_e0[0x6a0];
e281682b
SM		 2475
2476 struct mlx5_ifc_rq_num_bits rq_num[0];
2477};
2478
2479enum {
2480 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2481 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2482};
2483
2484enum {
2485 MLX5_RQC_STATE_RST = 0x0,
2486 MLX5_RQC_STATE_RDY = 0x1,
2487 MLX5_RQC_STATE_ERR = 0x3,
2488};
2489
2490struct mlx5_ifc_rqc_bits {
2491 u8 rlky[0x1];
7d5e1423
SM		 2492 u8 reserved_at_1[0x1];
2493 u8 scatter_fcs[0x1];
e281682b
SM		 2494 u8 vsd[0x1];
2495 u8 mem_rq_type[0x4];
2496 u8 state[0x4];
b4ff3a36 2497 u8 reserved_at_c[0x1];
e281682b 2498 u8 flush_in_error_en[0x1];
b4ff3a36 2499 u8 reserved_at_e[0x12];
e281682b 2500
b4ff3a36 2501 u8 reserved_at_20[0x8];
e281682b
SM		 2502 u8 user_index[0x18];
2503
b4ff3a36 2504 u8 reserved_at_40[0x8];
e281682b
SM		 2505 u8 cqn[0x18];
2506
2507 u8 counter_set_id[0x8];
b4ff3a36 2508 u8 reserved_at_68[0x18];
e281682b 2509
b4ff3a36 2510 u8 reserved_at_80[0x8];
e281682b
SM		 2511 u8 rmpn[0x18];
2512
b4ff3a36 2513 u8 reserved_at_a0[0xe0];
e281682b
SM		 2514
2515 struct mlx5_ifc_wq_bits wq;
2516};
2517
2518enum {
2519 MLX5_RMPC_STATE_RDY = 0x1,
2520 MLX5_RMPC_STATE_ERR = 0x3,
2521};
2522
2523struct mlx5_ifc_rmpc_bits {
b4ff3a36 2524 u8 reserved_at_0[0x8];
e281682b 2525 u8 state[0x4];
b4ff3a36 2526 u8 reserved_at_c[0x14];
e281682b
SM		 2527
2528 u8 basic_cyclic_rcv_wqe[0x1];
b4ff3a36 2529 u8 reserved_at_21[0x1f];
e281682b 2530
b4ff3a36 2531 u8 reserved_at_40[0x140];
e281682b
SM		 2532
2533 struct mlx5_ifc_wq_bits wq;
2534};
2535
e281682b 2536struct mlx5_ifc_nic_vport_context_bits {
cff92d7c
HHZ		 2537 u8 reserved_at_0[0x5];
2538 u8 min_wqe_inline_mode[0x3];
2539 u8 reserved_at_8[0x17];
e281682b
SM		 2540 u8 roce_en[0x1];
2541
d82b7318 2542 u8 arm_change_event[0x1];
b4ff3a36 2543 u8 reserved_at_21[0x1a];
d82b7318
SM		 2544 u8 event_on_mtu[0x1];
2545 u8 event_on_promisc_change[0x1];
2546 u8 event_on_vlan_change[0x1];
2547 u8 event_on_mc_address_change[0x1];
2548 u8 event_on_uc_address_change[0x1];
e281682b 2549
b4ff3a36 2550 u8 reserved_at_40[0xf0];
d82b7318
SM		 2551
2552 u8 mtu[0x10];
2553
9efa7525
AS		 2554 u8 system_image_guid[0x40];
2555 u8 port_guid[0x40];
2556 u8 node_guid[0x40];
2557
b4ff3a36 2558 u8 reserved_at_200[0x140];
9efa7525 2559 u8 qkey_violation_counter[0x10];
b4ff3a36 2560 u8 reserved_at_350[0x430];
d82b7318
SM		 2561
2562 u8 promisc_uc[0x1];
2563 u8 promisc_mc[0x1];
2564 u8 promisc_all[0x1];
b4ff3a36 2565 u8 reserved_at_783[0x2];
e281682b 2566 u8 allowed_list_type[0x3];
b4ff3a36 2567 u8 reserved_at_788[0xc];
e281682b
SM		 2568 u8 allowed_list_size[0xc];
2569
2570 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2571
b4ff3a36 2572 u8 reserved_at_7e0[0x20];
e281682b
SM		 2573
2574 u8 current_uc_mac_address[0][0x40];
2575};
2576
2577enum {
2578 MLX5_MKC_ACCESS_MODE_PA = 0x0,
2579 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
2580 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
bcda1aca 2581 MLX5_MKC_ACCESS_MODE_KSM = 0x3,
e281682b
SM		 2582};
2583
2584struct mlx5_ifc_mkc_bits {
b4ff3a36 2585 u8 reserved_at_0[0x1];
e281682b 2586 u8 free[0x1];
b4ff3a36 2587 u8 reserved_at_2[0xd];
e281682b
SM		 2588 u8 small_fence_on_rdma_read_response[0x1];
2589 u8 umr_en[0x1];
2590 u8 a[0x1];
2591 u8 rw[0x1];
2592 u8 rr[0x1];
2593 u8 lw[0x1];
2594 u8 lr[0x1];
2595 u8 access_mode[0x2];
b4ff3a36 2596 u8 reserved_at_18[0x8];
e281682b
SM		 2597
2598 u8 qpn[0x18];
2599 u8 mkey_7_0[0x8];
2600
b4ff3a36 2601 u8 reserved_at_40[0x20];
e281682b
SM		 2602
2603 u8 length64[0x1];
2604 u8 bsf_en[0x1];
2605 u8 sync_umr[0x1];
b4ff3a36 2606 u8 reserved_at_63[0x2];
e281682b 2607 u8 expected_sigerr_count[0x1];
b4ff3a36 2608 u8 reserved_at_66[0x1];
e281682b
SM		 2609 u8 en_rinval[0x1];
2610 u8 pd[0x18];
2611
2612 u8 start_addr[0x40];
2613
2614 u8 len[0x40];
2615
2616 u8 bsf_octword_size[0x20];
2617
b4ff3a36 2618 u8 reserved_at_120[0x80];
e281682b
SM		 2619
2620 u8 translations_octword_size[0x20];
2621
b4ff3a36 2622 u8 reserved_at_1c0[0x1b];
e281682b
SM		 2623 u8 log_page_size[0x5];
2624
b4ff3a36 2625 u8 reserved_at_1e0[0x20];
e281682b
SM		 2626};
2627
2628struct mlx5_ifc_pkey_bits {
b4ff3a36 2629 u8 reserved_at_0[0x10];
e281682b
SM		 2630 u8 pkey[0x10];
2631};
2632
2633struct mlx5_ifc_array128_auto_bits {
2634 u8 array128_auto[16][0x8];
2635};
2636
2637struct mlx5_ifc_hca_vport_context_bits {
2638 u8 field_select[0x20];
2639
b4ff3a36 2640 u8 reserved_at_20[0xe0];
e281682b
SM		 2641
2642 u8 sm_virt_aware[0x1];
2643 u8 has_smi[0x1];
2644 u8 has_raw[0x1];
2645 u8 grh_required[0x1];
b4ff3a36 2646 u8 reserved_at_104[0xc];
707c4602
MD		 2647 u8 port_physical_state[0x4];
2648 u8 vport_state_policy[0x4];
2649 u8 port_state[0x4];
e281682b
SM		 2650 u8 vport_state[0x4];
2651
b4ff3a36 2652 u8 reserved_at_120[0x20];
707c4602
MD		 2653
2654 u8 system_image_guid[0x40];
e281682b
SM		 2655
2656 u8 port_guid[0x40];
2657
2658 u8 node_guid[0x40];
2659
2660 u8 cap_mask1[0x20];
2661
2662 u8 cap_mask1_field_select[0x20];
2663
2664 u8 cap_mask2[0x20];
2665
2666 u8 cap_mask2_field_select[0x20];
2667
b4ff3a36 2668 u8 reserved_at_280[0x80];
e281682b
SM		 2669
2670 u8 lid[0x10];
b4ff3a36 2671 u8 reserved_at_310[0x4];
e281682b
SM		 2672 u8 init_type_reply[0x4];
2673 u8 lmc[0x3];
2674 u8 subnet_timeout[0x5];
2675
2676 u8 sm_lid[0x10];
2677 u8 sm_sl[0x4];
b4ff3a36 2678 u8 reserved_at_334[0xc];
e281682b
SM		 2679
2680 u8 qkey_violation_counter[0x10];
2681 u8 pkey_violation_counter[0x10];
2682
b4ff3a36 2683 u8 reserved_at_360[0xca0];
e281682b
SM		 2684};
2685
d6666753 2686struct mlx5_ifc_esw_vport_context_bits {
b4ff3a36 2687 u8 reserved_at_0[0x3];
d6666753
SM		 2688 u8 vport_svlan_strip[0x1];
2689 u8 vport_cvlan_strip[0x1];
2690 u8 vport_svlan_insert[0x1];
2691 u8 vport_cvlan_insert[0x2];
b4ff3a36 2692 u8 reserved_at_8[0x18];
d6666753 2693
b4ff3a36 2694 u8 reserved_at_20[0x20];
d6666753
SM		 2695
2696 u8 svlan_cfi[0x1];
2697 u8 svlan_pcp[0x3];
2698 u8 svlan_id[0xc];
2699 u8 cvlan_cfi[0x1];
2700 u8 cvlan_pcp[0x3];
2701 u8 cvlan_id[0xc];
2702
b4ff3a36 2703 u8 reserved_at_60[0x7a0];
d6666753
SM		 2704};
2705
e281682b
SM		 2706enum {
2707 MLX5_EQC_STATUS_OK = 0x0,
2708 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
2709};
2710
2711enum {
2712 MLX5_EQC_ST_ARMED = 0x9,
2713 MLX5_EQC_ST_FIRED = 0xa,
2714};
2715
2716struct mlx5_ifc_eqc_bits {
2717 u8 status[0x4];
b4ff3a36 2718 u8 reserved_at_4[0x9];
e281682b
SM		 2719 u8 ec[0x1];
2720 u8 oi[0x1];
b4ff3a36 2721 u8 reserved_at_f[0x5];
e281682b 2722 u8 st[0x4];
b4ff3a36 2723 u8 reserved_at_18[0x8];
e281682b 2724
b4ff3a36 2725 u8 reserved_at_20[0x20];
e281682b 2726
b4ff3a36 2727 u8 reserved_at_40[0x14];
e281682b 2728 u8 page_offset[0x6];
b4ff3a36 2729 u8 reserved_at_5a[0x6];
e281682b 2730
b4ff3a36 2731 u8 reserved_at_60[0x3];
e281682b
SM		 2732 u8 log_eq_size[0x5];
2733 u8 uar_page[0x18];
2734
b4ff3a36 2735 u8 reserved_at_80[0x20];
e281682b 2736
b4ff3a36 2737 u8 reserved_at_a0[0x18];
e281682b
SM		 2738 u8 intr[0x8];
2739
b4ff3a36 2740 u8 reserved_at_c0[0x3];
e281682b 2741 u8 log_page_size[0x5];
b4ff3a36 2742 u8 reserved_at_c8[0x18];
e281682b 2743
b4ff3a36 2744 u8 reserved_at_e0[0x60];
e281682b 2745
b4ff3a36 2746 u8 reserved_at_140[0x8];
e281682b
SM		 2747 u8 consumer_counter[0x18];
2748
b4ff3a36 2749 u8 reserved_at_160[0x8];
e281682b
SM		 2750 u8 producer_counter[0x18];
2751
b4ff3a36 2752 u8 reserved_at_180[0x80];
e281682b
SM		 2753};
2754
2755enum {
2756 MLX5_DCTC_STATE_ACTIVE = 0x0,
2757 MLX5_DCTC_STATE_DRAINING = 0x1,
2758 MLX5_DCTC_STATE_DRAINED = 0x2,
2759};
2760
2761enum {
2762 MLX5_DCTC_CS_RES_DISABLE = 0x0,
2763 MLX5_DCTC_CS_RES_NA = 0x1,
2764 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
2765};
2766
2767enum {
2768 MLX5_DCTC_MTU_256_BYTES = 0x1,
2769 MLX5_DCTC_MTU_512_BYTES = 0x2,
2770 MLX5_DCTC_MTU_1K_BYTES = 0x3,
2771 MLX5_DCTC_MTU_2K_BYTES = 0x4,
2772 MLX5_DCTC_MTU_4K_BYTES = 0x5,
2773};
2774
2775struct mlx5_ifc_dctc_bits {
b4ff3a36 2776 u8 reserved_at_0[0x4];
e281682b 2777 u8 state[0x4];
b4ff3a36 2778 u8 reserved_at_8[0x18];
e281682b 2779
b4ff3a36 2780 u8 reserved_at_20[0x8];
e281682b
SM		 2781 u8 user_index[0x18];
2782
b4ff3a36 2783 u8 reserved_at_40[0x8];
e281682b
SM		 2784 u8 cqn[0x18];
2785
2786 u8 counter_set_id[0x8];
2787 u8 atomic_mode[0x4];
2788 u8 rre[0x1];
2789 u8 rwe[0x1];
2790 u8 rae[0x1];
2791 u8 atomic_like_write_en[0x1];
2792 u8 latency_sensitive[0x1];
2793 u8 rlky[0x1];
2794 u8 free_ar[0x1];
b4ff3a36 2795 u8 reserved_at_73[0xd];
e281682b 2796
b4ff3a36 2797 u8 reserved_at_80[0x8];
e281682b 2798 u8 cs_res[0x8];
b4ff3a36 2799 u8 reserved_at_90[0x3];
e281682b 2800 u8 min_rnr_nak[0x5];
b4ff3a36 2801 u8 reserved_at_98[0x8];
e281682b 2802
b4ff3a36 2803 u8 reserved_at_a0[0x8];
7486216b 2804 u8 srqn_xrqn[0x18];
e281682b 2805
b4ff3a36 2806 u8 reserved_at_c0[0x8];
e281682b
SM		 2807 u8 pd[0x18];
2808
2809 u8 tclass[0x8];
b4ff3a36 2810 u8 reserved_at_e8[0x4];
e281682b
SM		 2811 u8 flow_label[0x14];
2812
2813 u8 dc_access_key[0x40];
2814
b4ff3a36 2815 u8 reserved_at_140[0x5];
e281682b
SM		 2816 u8 mtu[0x3];
2817 u8 port[0x8];
2818 u8 pkey_index[0x10];
2819
b4ff3a36 2820 u8 reserved_at_160[0x8];
e281682b 2821 u8 my_addr_index[0x8];
b4ff3a36 2822 u8 reserved_at_170[0x8];
e281682b
SM		 2823 u8 hop_limit[0x8];
2824
2825 u8 dc_access_key_violation_count[0x20];
2826
b4ff3a36 2827 u8 reserved_at_1a0[0x14];
e281682b
SM		 2828 u8 dei_cfi[0x1];
2829 u8 eth_prio[0x3];
2830 u8 ecn[0x2];
2831 u8 dscp[0x6];
2832
b4ff3a36 2833 u8 reserved_at_1c0[0x40];
e281682b
SM		 2834};
2835
2836enum {
2837 MLX5_CQC_STATUS_OK = 0x0,
2838 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
2839 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
2840};
2841
2842enum {
2843 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
2844 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
2845};
2846
2847enum {
2848 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
2849 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
2850 MLX5_CQC_ST_FIRED = 0xa,
2851};
2852
7d5e1423
SM		 2853enum {
2854 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
2855 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
7486216b 2856 MLX5_CQ_PERIOD_NUM_MODES
7d5e1423
SM		 2857};
2858
e281682b
SM		 2859struct mlx5_ifc_cqc_bits {
2860 u8 status[0x4];
b4ff3a36 2861 u8 reserved_at_4[0x4];
e281682b
SM		 2862 u8 cqe_sz[0x3];
2863 u8 cc[0x1];
b4ff3a36 2864 u8 reserved_at_c[0x1];
e281682b
SM		 2865 u8 scqe_break_moderation_en[0x1];
2866 u8 oi[0x1];
7d5e1423
SM		 2867 u8 cq_period_mode[0x2];
2868 u8 cqe_comp_en[0x1];
e281682b
SM		 2869 u8 mini_cqe_res_format[0x2];
2870 u8 st[0x4];
b4ff3a36 2871 u8 reserved_at_18[0x8];
e281682b 2872
b4ff3a36 2873 u8 reserved_at_20[0x20];
e281682b 2874
b4ff3a36 2875 u8 reserved_at_40[0x14];
e281682b 2876 u8 page_offset[0x6];
b4ff3a36 2877 u8 reserved_at_5a[0x6];
e281682b 2878
b4ff3a36 2879 u8 reserved_at_60[0x3];
e281682b
SM		 2880 u8 log_cq_size[0x5];
2881 u8 uar_page[0x18];
2882
b4ff3a36 2883 u8 reserved_at_80[0x4];
e281682b
SM		 2884 u8 cq_period[0xc];
2885 u8 cq_max_count[0x10];
2886
b4ff3a36 2887 u8 reserved_at_a0[0x18];
e281682b
SM		 2888 u8 c_eqn[0x8];
2889
b4ff3a36 2890 u8 reserved_at_c0[0x3];
e281682b 2891 u8 log_page_size[0x5];
b4ff3a36 2892 u8 reserved_at_c8[0x18];
e281682b 2893
b4ff3a36 2894 u8 reserved_at_e0[0x20];
e281682b 2895
b4ff3a36 2896 u8 reserved_at_100[0x8];
e281682b
SM		 2897 u8 last_notified_index[0x18];
2898
b4ff3a36 2899 u8 reserved_at_120[0x8];
e281682b
SM		 2900 u8 last_solicit_index[0x18];
2901
b4ff3a36 2902 u8 reserved_at_140[0x8];
e281682b
SM		 2903 u8 consumer_counter[0x18];
2904
b4ff3a36 2905 u8 reserved_at_160[0x8];
e281682b
SM		 2906 u8 producer_counter[0x18];
2907
b4ff3a36 2908 u8 reserved_at_180[0x40];
e281682b
SM		 2909
2910 u8 dbr_addr[0x40];
2911};
2912
2913union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2914 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2915 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2916 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
b4ff3a36 2917 u8 reserved_at_0[0x800];
e281682b
SM		 2918};
2919
2920struct mlx5_ifc_query_adapter_param_block_bits {
b4ff3a36 2921 u8 reserved_at_0[0xc0];
e281682b 2922
b4ff3a36 2923 u8 reserved_at_c0[0x8];
211e6c80
MD		 2924 u8 ieee_vendor_id[0x18];
2925
b4ff3a36 2926 u8 reserved_at_e0[0x10];
e281682b
SM		 2927 u8 vsd_vendor_id[0x10];
2928
2929 u8 vsd[208][0x8];
2930
2931 u8 vsd_contd_psid[16][0x8];
2932};
2933
7486216b
SM		 2934enum {
2935 MLX5_XRQC_STATE_GOOD = 0x0,
2936 MLX5_XRQC_STATE_ERROR = 0x1,
2937};
2938
2939enum {
2940 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
2941 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
2942};
2943
2944enum {
2945 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
2946};
2947
2948struct mlx5_ifc_tag_matching_topology_context_bits {
2949 u8 log_matching_list_sz[0x4];
2950 u8 reserved_at_4[0xc];
2951 u8 append_next_index[0x10];
2952
2953 u8 sw_phase_cnt[0x10];
2954 u8 hw_phase_cnt[0x10];
2955
2956 u8 reserved_at_40[0x40];
2957};
2958
2959struct mlx5_ifc_xrqc_bits {
2960 u8 state[0x4];
2961 u8 rlkey[0x1];
2962 u8 reserved_at_5[0xf];
2963 u8 topology[0x4];
2964 u8 reserved_at_18[0x4];
2965 u8 offload[0x4];
2966
2967 u8 reserved_at_20[0x8];
2968 u8 user_index[0x18];
2969
2970 u8 reserved_at_40[0x8];
2971 u8 cqn[0x18];
2972
2973 u8 reserved_at_60[0xa0];
2974
2975 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
2976
5579e151 2977 u8 reserved_at_180[0x880];
7486216b
SM		 2978
2979 struct mlx5_ifc_wq_bits wq;
2980};
2981
e281682b
SM		 2982union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2983 struct mlx5_ifc_modify_field_select_bits modify_field_select;
2984 struct mlx5_ifc_resize_field_select_bits resize_field_select;
b4ff3a36 2985 u8 reserved_at_0[0x20];
e281682b
SM		 2986};
2987
2988union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2989 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2990 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2991 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
b4ff3a36 2992 u8 reserved_at_0[0x20];
e281682b
SM		 2993};
2994
2995union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
2996 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
2997 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
2998 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
2999 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
3000 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
3001 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
3002 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
1c64bf6f 3003 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b 3004 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
d8dc0508 3005 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
b4ff3a36 3006 u8 reserved_at_0[0x7c0];
e281682b
SM		 3007};
3008
8ed1a630
GP		 3009union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
3010 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
3011 u8 reserved_at_0[0x7c0];
3012};
3013
e281682b
SM		 3014union mlx5_ifc_event_auto_bits {
3015 struct mlx5_ifc_comp_event_bits comp_event;
3016 struct mlx5_ifc_dct_events_bits dct_events;
3017 struct mlx5_ifc_qp_events_bits qp_events;
3018 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3019 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3020 struct mlx5_ifc_cq_error_bits cq_error;
3021 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3022 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3023 struct mlx5_ifc_gpio_event_bits gpio_event;
3024 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3025 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3026 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
b4ff3a36 3027 u8 reserved_at_0[0xe0];
e281682b
SM		 3028};
3029
3030struct mlx5_ifc_health_buffer_bits {
b4ff3a36 3031 u8 reserved_at_0[0x100];
e281682b
SM		 3032
3033 u8 assert_existptr[0x20];
3034
3035 u8 assert_callra[0x20];
3036
b4ff3a36 3037 u8 reserved_at_140[0x40];
e281682b
SM		 3038
3039 u8 fw_version[0x20];
3040
3041 u8 hw_id[0x20];
3042
b4ff3a36 3043 u8 reserved_at_1c0[0x20];
e281682b
SM		 3044
3045 u8 irisc_index[0x8];
3046 u8 synd[0x8];
3047 u8 ext_synd[0x10];
3048};
3049
3050struct mlx5_ifc_register_loopback_control_bits {
3051 u8 no_lb[0x1];
b4ff3a36 3052 u8 reserved_at_1[0x7];
e281682b 3053 u8 port[0x8];
b4ff3a36 3054 u8 reserved_at_10[0x10];
e281682b 3055
b4ff3a36 3056 u8 reserved_at_20[0x60];
e281682b
SM		 3057};
3058
813f8540
MHY		 3059struct mlx5_ifc_vport_tc_element_bits {
3060 u8 traffic_class[0x4];
3061 u8 reserved_at_4[0xc];
3062 u8 vport_number[0x10];
3063};
3064
3065struct mlx5_ifc_vport_element_bits {
3066 u8 reserved_at_0[0x10];
3067 u8 vport_number[0x10];
3068};
3069
3070enum {
3071 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3072 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3073 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3074};
3075
3076struct mlx5_ifc_tsar_element_bits {
3077 u8 reserved_at_0[0x8];
3078 u8 tsar_type[0x8];
3079 u8 reserved_at_10[0x10];
3080};
3081
e281682b
SM		 3082struct mlx5_ifc_teardown_hca_out_bits {
3083 u8 status[0x8];
b4ff3a36 3084 u8 reserved_at_8[0x18];
e281682b
SM		 3085
3086 u8 syndrome[0x20];
3087
b4ff3a36 3088 u8 reserved_at_40[0x40];
e281682b
SM		 3089};
3090
3091enum {
3092 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
3093 MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE = 0x1,
3094};
3095
3096struct mlx5_ifc_teardown_hca_in_bits {
3097 u8 opcode[0x10];
b4ff3a36 3098 u8 reserved_at_10[0x10];
e281682b 3099
b4ff3a36 3100 u8 reserved_at_20[0x10];
e281682b
SM		 3101 u8 op_mod[0x10];
3102
b4ff3a36 3103 u8 reserved_at_40[0x10];
e281682b
SM		 3104 u8 profile[0x10];
3105
b4ff3a36 3106 u8 reserved_at_60[0x20];
e281682b
SM		 3107};
3108
3109struct mlx5_ifc_sqerr2rts_qp_out_bits {
3110 u8 status[0x8];
b4ff3a36 3111 u8 reserved_at_8[0x18];
e281682b
SM		 3112
3113 u8 syndrome[0x20];
3114
b4ff3a36 3115 u8 reserved_at_40[0x40];
e281682b
SM		 3116};
3117
3118struct mlx5_ifc_sqerr2rts_qp_in_bits {
3119 u8 opcode[0x10];
b4ff3a36 3120 u8 reserved_at_10[0x10];
e281682b 3121
b4ff3a36 3122 u8 reserved_at_20[0x10];
e281682b
SM		 3123 u8 op_mod[0x10];
3124
b4ff3a36 3125 u8 reserved_at_40[0x8];
e281682b
SM		 3126 u8 qpn[0x18];
3127
b4ff3a36 3128 u8 reserved_at_60[0x20];
e281682b
SM		 3129
3130 u8 opt_param_mask[0x20];
3131
b4ff3a36 3132 u8 reserved_at_a0[0x20];
e281682b
SM		 3133
3134 struct mlx5_ifc_qpc_bits qpc;
3135
b4ff3a36 3136 u8 reserved_at_800[0x80];
e281682b
SM		 3137};
3138
3139struct mlx5_ifc_sqd2rts_qp_out_bits {
3140 u8 status[0x8];
b4ff3a36 3141 u8 reserved_at_8[0x18];
e281682b
SM		 3142
3143 u8 syndrome[0x20];
3144
b4ff3a36 3145 u8 reserved_at_40[0x40];
e281682b
SM		 3146};
3147
3148struct mlx5_ifc_sqd2rts_qp_in_bits {
3149 u8 opcode[0x10];
b4ff3a36 3150 u8 reserved_at_10[0x10];
e281682b 3151
b4ff3a36 3152 u8 reserved_at_20[0x10];
e281682b
SM		 3153 u8 op_mod[0x10];
3154
b4ff3a36 3155 u8 reserved_at_40[0x8];
e281682b
SM		 3156 u8 qpn[0x18];
3157
b4ff3a36 3158 u8 reserved_at_60[0x20];
e281682b
SM		 3159
3160 u8 opt_param_mask[0x20];
3161
b4ff3a36 3162 u8 reserved_at_a0[0x20];
e281682b
SM		 3163
3164 struct mlx5_ifc_qpc_bits qpc;
3165
b4ff3a36 3166 u8 reserved_at_800[0x80];
e281682b
SM		 3167};
3168
3169struct mlx5_ifc_set_roce_address_out_bits {
3170 u8 status[0x8];
b4ff3a36 3171 u8 reserved_at_8[0x18];
e281682b
SM		 3172
3173 u8 syndrome[0x20];
3174
b4ff3a36 3175 u8 reserved_at_40[0x40];
e281682b
SM		 3176};
3177
3178struct mlx5_ifc_set_roce_address_in_bits {
3179 u8 opcode[0x10];
b4ff3a36 3180 u8 reserved_at_10[0x10];
e281682b 3181
b4ff3a36 3182 u8 reserved_at_20[0x10];
e281682b
SM		 3183 u8 op_mod[0x10];
3184
3185 u8 roce_address_index[0x10];
b4ff3a36 3186 u8 reserved_at_50[0x10];
e281682b 3187
b4ff3a36 3188 u8 reserved_at_60[0x20];
e281682b
SM		 3189
3190 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3191};
3192
3193struct mlx5_ifc_set_mad_demux_out_bits {
3194 u8 status[0x8];
b4ff3a36 3195 u8 reserved_at_8[0x18];
e281682b
SM		 3196
3197 u8 syndrome[0x20];
3198
b4ff3a36 3199 u8 reserved_at_40[0x40];
e281682b
SM		 3200};
3201
3202enum {
3203 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
3204 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
3205};
3206
3207struct mlx5_ifc_set_mad_demux_in_bits {
3208 u8 opcode[0x10];
b4ff3a36 3209 u8 reserved_at_10[0x10];
e281682b 3210
b4ff3a36 3211 u8 reserved_at_20[0x10];
e281682b
SM		 3212 u8 op_mod[0x10];
3213
b4ff3a36 3214 u8 reserved_at_40[0x20];
e281682b 3215
b4ff3a36 3216 u8 reserved_at_60[0x6];
e281682b 3217 u8 demux_mode[0x2];
b4ff3a36 3218 u8 reserved_at_68[0x18];
e281682b
SM		 3219};
3220
3221struct mlx5_ifc_set_l2_table_entry_out_bits {
3222 u8 status[0x8];
b4ff3a36 3223 u8 reserved_at_8[0x18];
e281682b
SM		 3224
3225 u8 syndrome[0x20];
3226
b4ff3a36 3227 u8 reserved_at_40[0x40];
e281682b
SM		 3228};
3229
3230struct mlx5_ifc_set_l2_table_entry_in_bits {
3231 u8 opcode[0x10];
b4ff3a36 3232 u8 reserved_at_10[0x10];
e281682b 3233
b4ff3a36 3234 u8 reserved_at_20[0x10];
e281682b
SM		 3235 u8 op_mod[0x10];
3236
b4ff3a36 3237 u8 reserved_at_40[0x60];
e281682b 3238
b4ff3a36 3239 u8 reserved_at_a0[0x8];
e281682b
SM		 3240 u8 table_index[0x18];
3241
b4ff3a36 3242 u8 reserved_at_c0[0x20];
e281682b 3243
b4ff3a36 3244 u8 reserved_at_e0[0x13];
e281682b
SM		 3245 u8 vlan_valid[0x1];
3246 u8 vlan[0xc];
3247
3248 struct mlx5_ifc_mac_address_layout_bits mac_address;
3249
b4ff3a36 3250 u8 reserved_at_140[0xc0];
e281682b
SM		 3251};
3252
3253struct mlx5_ifc_set_issi_out_bits {
3254 u8 status[0x8];
b4ff3a36 3255 u8 reserved_at_8[0x18];
e281682b
SM		 3256
3257 u8 syndrome[0x20];
3258
b4ff3a36 3259 u8 reserved_at_40[0x40];
e281682b
SM		 3260};
3261
3262struct mlx5_ifc_set_issi_in_bits {
3263 u8 opcode[0x10];
b4ff3a36 3264 u8 reserved_at_10[0x10];
e281682b 3265
b4ff3a36 3266 u8 reserved_at_20[0x10];
e281682b
SM		 3267 u8 op_mod[0x10];
3268
b4ff3a36 3269 u8 reserved_at_40[0x10];
e281682b
SM		 3270 u8 current_issi[0x10];
3271
b4ff3a36 3272 u8 reserved_at_60[0x20];
e281682b
SM		 3273};
3274
3275struct mlx5_ifc_set_hca_cap_out_bits {
3276 u8 status[0x8];
b4ff3a36 3277 u8 reserved_at_8[0x18];
e281682b
SM		 3278
3279 u8 syndrome[0x20];
3280
b4ff3a36 3281 u8 reserved_at_40[0x40];
e281682b
SM		 3282};
3283
3284struct mlx5_ifc_set_hca_cap_in_bits {
3285 u8 opcode[0x10];
b4ff3a36 3286 u8 reserved_at_10[0x10];
e281682b 3287
b4ff3a36 3288 u8 reserved_at_20[0x10];
e281682b
SM		 3289 u8 op_mod[0x10];
3290
b4ff3a36 3291 u8 reserved_at_40[0x40];
e281682b
SM		 3292
3293 union mlx5_ifc_hca_cap_union_bits capability;
3294};
3295
26a81453
MG		 3296enum {
3297 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
3298 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
3299 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
3300 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
3301};
3302
e281682b
SM		 3303struct mlx5_ifc_set_fte_out_bits {
3304 u8 status[0x8];
b4ff3a36 3305 u8 reserved_at_8[0x18];
e281682b
SM		 3306
3307 u8 syndrome[0x20];
3308
b4ff3a36 3309 u8 reserved_at_40[0x40];
e281682b
SM		 3310};
3311
3312struct mlx5_ifc_set_fte_in_bits {
3313 u8 opcode[0x10];
b4ff3a36 3314 u8 reserved_at_10[0x10];
e281682b 3315
b4ff3a36 3316 u8 reserved_at_20[0x10];
e281682b
SM		 3317 u8 op_mod[0x10];
3318
7d5e1423
SM		 3319 u8 other_vport[0x1];
3320 u8 reserved_at_41[0xf];
3321 u8 vport_number[0x10];
3322
3323 u8 reserved_at_60[0x20];
e281682b
SM		 3324
3325 u8 table_type[0x8];
b4ff3a36 3326 u8 reserved_at_88[0x18];
e281682b 3327
b4ff3a36 3328 u8 reserved_at_a0[0x8];
e281682b
SM		 3329 u8 table_id[0x18];
3330
b4ff3a36 3331 u8 reserved_at_c0[0x18];
26a81453
MG		 3332 u8 modify_enable_mask[0x8];
3333
b4ff3a36 3334 u8 reserved_at_e0[0x20];
e281682b
SM		 3335
3336 u8 flow_index[0x20];
3337
b4ff3a36 3338 u8 reserved_at_120[0xe0];
e281682b
SM		 3339
3340 struct mlx5_ifc_flow_context_bits flow_context;
3341};
3342
3343struct mlx5_ifc_rts2rts_qp_out_bits {
3344 u8 status[0x8];
b4ff3a36 3345 u8 reserved_at_8[0x18];
e281682b
SM		 3346
3347 u8 syndrome[0x20];
3348
b4ff3a36 3349 u8 reserved_at_40[0x40];
e281682b
SM		 3350};
3351
3352struct mlx5_ifc_rts2rts_qp_in_bits {
3353 u8 opcode[0x10];
b4ff3a36 3354 u8 reserved_at_10[0x10];
e281682b 3355
b4ff3a36 3356 u8 reserved_at_20[0x10];
e281682b
SM		 3357 u8 op_mod[0x10];
3358
b4ff3a36 3359 u8 reserved_at_40[0x8];
e281682b
SM		 3360 u8 qpn[0x18];
3361
b4ff3a36 3362 u8 reserved_at_60[0x20];
e281682b
SM		 3363
3364 u8 opt_param_mask[0x20];
3365
b4ff3a36 3366 u8 reserved_at_a0[0x20];
e281682b
SM		 3367
3368 struct mlx5_ifc_qpc_bits qpc;
3369
b4ff3a36 3370 u8 reserved_at_800[0x80];
e281682b
SM		 3371};
3372
3373struct mlx5_ifc_rtr2rts_qp_out_bits {
3374 u8 status[0x8];
b4ff3a36 3375 u8 reserved_at_8[0x18];
e281682b
SM		 3376
3377 u8 syndrome[0x20];
3378
b4ff3a36 3379 u8 reserved_at_40[0x40];
e281682b
SM		 3380};
3381
3382struct mlx5_ifc_rtr2rts_qp_in_bits {
3383 u8 opcode[0x10];
b4ff3a36 3384 u8 reserved_at_10[0x10];
e281682b 3385
b4ff3a36 3386 u8 reserved_at_20[0x10];
e281682b
SM		 3387 u8 op_mod[0x10];
3388
b4ff3a36 3389 u8 reserved_at_40[0x8];
e281682b
SM		 3390 u8 qpn[0x18];
3391
b4ff3a36 3392 u8 reserved_at_60[0x20];
e281682b
SM		 3393
3394 u8 opt_param_mask[0x20];
3395
b4ff3a36 3396 u8 reserved_at_a0[0x20];
e281682b
SM		 3397
3398 struct mlx5_ifc_qpc_bits qpc;
3399
b4ff3a36 3400 u8 reserved_at_800[0x80];
e281682b
SM		 3401};
3402
3403struct mlx5_ifc_rst2init_qp_out_bits {
3404 u8 status[0x8];
b4ff3a36 3405 u8 reserved_at_8[0x18];
e281682b
SM		 3406
3407 u8 syndrome[0x20];
3408
b4ff3a36 3409 u8 reserved_at_40[0x40];
e281682b
SM		 3410};
3411
3412struct mlx5_ifc_rst2init_qp_in_bits {
3413 u8 opcode[0x10];
b4ff3a36 3414 u8 reserved_at_10[0x10];
e281682b 3415
b4ff3a36 3416 u8 reserved_at_20[0x10];
e281682b
SM		 3417 u8 op_mod[0x10];
3418
b4ff3a36 3419 u8 reserved_at_40[0x8];
e281682b
SM		 3420 u8 qpn[0x18];
3421
b4ff3a36 3422 u8 reserved_at_60[0x20];
e281682b
SM		 3423
3424 u8 opt_param_mask[0x20];
3425
b4ff3a36 3426 u8 reserved_at_a0[0x20];
e281682b
SM		 3427
3428 struct mlx5_ifc_qpc_bits qpc;
3429
b4ff3a36 3430 u8 reserved_at_800[0x80];
e281682b
SM		 3431};
3432
7486216b
SM		 3433struct mlx5_ifc_query_xrq_out_bits {
3434 u8 status[0x8];
3435 u8 reserved_at_8[0x18];
3436
3437 u8 syndrome[0x20];
3438
3439 u8 reserved_at_40[0x40];
3440
3441 struct mlx5_ifc_xrqc_bits xrq_context;
3442};
3443
3444struct mlx5_ifc_query_xrq_in_bits {
3445 u8 opcode[0x10];
3446 u8 reserved_at_10[0x10];
3447
3448 u8 reserved_at_20[0x10];
3449 u8 op_mod[0x10];
3450
3451 u8 reserved_at_40[0x8];
3452 u8 xrqn[0x18];
3453
3454 u8 reserved_at_60[0x20];
3455};
3456
e281682b
SM		 3457struct mlx5_ifc_query_xrc_srq_out_bits {
3458 u8 status[0x8];
b4ff3a36 3459 u8 reserved_at_8[0x18];
e281682b
SM		 3460
3461 u8 syndrome[0x20];
3462
b4ff3a36 3463 u8 reserved_at_40[0x40];
e281682b
SM		 3464
3465 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3466
b4ff3a36 3467 u8 reserved_at_280[0x600];
e281682b
SM		 3468
3469 u8 pas[0][0x40];
3470};
3471
3472struct mlx5_ifc_query_xrc_srq_in_bits {
3473 u8 opcode[0x10];
b4ff3a36 3474 u8 reserved_at_10[0x10];
e281682b 3475
b4ff3a36 3476 u8 reserved_at_20[0x10];
e281682b
SM		 3477 u8 op_mod[0x10];
3478
b4ff3a36 3479 u8 reserved_at_40[0x8];
e281682b
SM		 3480 u8 xrc_srqn[0x18];
3481
b4ff3a36 3482 u8 reserved_at_60[0x20];
e281682b
SM		 3483};
3484
3485enum {
3486 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
3487 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
3488};
3489
3490struct mlx5_ifc_query_vport_state_out_bits {
3491 u8 status[0x8];
b4ff3a36 3492 u8 reserved_at_8[0x18];
e281682b
SM		 3493
3494 u8 syndrome[0x20];
3495
b4ff3a36 3496 u8 reserved_at_40[0x20];
e281682b 3497
b4ff3a36 3498 u8 reserved_at_60[0x18];
e281682b
SM		 3499 u8 admin_state[0x4];
3500 u8 state[0x4];
3501};
3502
3503enum {
3504 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0,
e7546514 3505 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1,
e281682b
SM		 3506};
3507
3508struct mlx5_ifc_query_vport_state_in_bits {
3509 u8 opcode[0x10];
b4ff3a36 3510 u8 reserved_at_10[0x10];
e281682b 3511
b4ff3a36 3512 u8 reserved_at_20[0x10];
e281682b
SM		 3513 u8 op_mod[0x10];
3514
3515 u8 other_vport[0x1];
b4ff3a36 3516 u8 reserved_at_41[0xf];
e281682b
SM		 3517 u8 vport_number[0x10];
3518
b4ff3a36 3519 u8 reserved_at_60[0x20];
e281682b
SM		 3520};
3521
3522struct mlx5_ifc_query_vport_counter_out_bits {
3523 u8 status[0x8];
b4ff3a36 3524 u8 reserved_at_8[0x18];
e281682b
SM		 3525
3526 u8 syndrome[0x20];
3527
b4ff3a36 3528 u8 reserved_at_40[0x40];
e281682b
SM		 3529
3530 struct mlx5_ifc_traffic_counter_bits received_errors;
3531
3532 struct mlx5_ifc_traffic_counter_bits transmit_errors;
3533
3534 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3535
3536 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3537
3538 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3539
3540 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3541
3542 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3543
3544 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3545
3546 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3547
3548 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3549
3550 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3551
3552 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3553
b4ff3a36 3554 u8 reserved_at_680[0xa00];
e281682b
SM		 3555};
3556
3557enum {
3558 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
3559};
3560
3561struct mlx5_ifc_query_vport_counter_in_bits {
3562 u8 opcode[0x10];
b4ff3a36 3563 u8 reserved_at_10[0x10];
e281682b 3564
b4ff3a36 3565 u8 reserved_at_20[0x10];
e281682b
SM		 3566 u8 op_mod[0x10];
3567
3568 u8 other_vport[0x1];
b54ba277
MY		 3569 u8 reserved_at_41[0xb];
3570 u8 port_num[0x4];
e281682b
SM		 3571 u8 vport_number[0x10];
3572
b4ff3a36 3573 u8 reserved_at_60[0x60];
e281682b
SM		 3574
3575 u8 clear[0x1];
b4ff3a36 3576 u8 reserved_at_c1[0x1f];
e281682b 3577
b4ff3a36 3578 u8 reserved_at_e0[0x20];
e281682b
SM		 3579};
3580
3581struct mlx5_ifc_query_tis_out_bits {
3582 u8 status[0x8];
b4ff3a36 3583 u8 reserved_at_8[0x18];
e281682b
SM		 3584
3585 u8 syndrome[0x20];
3586
b4ff3a36 3587 u8 reserved_at_40[0x40];
e281682b
SM		 3588
3589 struct mlx5_ifc_tisc_bits tis_context;
3590};
3591
3592struct mlx5_ifc_query_tis_in_bits {
3593 u8 opcode[0x10];
b4ff3a36 3594 u8 reserved_at_10[0x10];
e281682b 3595
b4ff3a36 3596 u8 reserved_at_20[0x10];
e281682b
SM		 3597 u8 op_mod[0x10];
3598
b4ff3a36 3599 u8 reserved_at_40[0x8];
e281682b
SM		 3600 u8 tisn[0x18];
3601
b4ff3a36 3602 u8 reserved_at_60[0x20];
e281682b
SM		 3603};
3604
3605struct mlx5_ifc_query_tir_out_bits {
3606 u8 status[0x8];
b4ff3a36 3607 u8 reserved_at_8[0x18];
e281682b
SM		 3608
3609 u8 syndrome[0x20];
3610
b4ff3a36 3611 u8 reserved_at_40[0xc0];
e281682b
SM		 3612
3613 struct mlx5_ifc_tirc_bits tir_context;
3614};
3615
3616struct mlx5_ifc_query_tir_in_bits {
3617 u8 opcode[0x10];
b4ff3a36 3618 u8 reserved_at_10[0x10];
e281682b 3619
b4ff3a36 3620 u8 reserved_at_20[0x10];
e281682b
SM		 3621 u8 op_mod[0x10];
3622
b4ff3a36 3623 u8 reserved_at_40[0x8];
e281682b
SM		 3624 u8 tirn[0x18];
3625
b4ff3a36 3626 u8 reserved_at_60[0x20];
e281682b
SM		 3627};
3628
3629struct mlx5_ifc_query_srq_out_bits {
3630 u8 status[0x8];
b4ff3a36 3631 u8 reserved_at_8[0x18];
e281682b
SM		 3632
3633 u8 syndrome[0x20];
3634
b4ff3a36 3635 u8 reserved_at_40[0x40];
e281682b
SM		 3636
3637 struct mlx5_ifc_srqc_bits srq_context_entry;
3638
b4ff3a36 3639 u8 reserved_at_280[0x600];
e281682b
SM		 3640
3641 u8 pas[0][0x40];
3642};
3643
3644struct mlx5_ifc_query_srq_in_bits {
3645 u8 opcode[0x10];
b4ff3a36 3646 u8 reserved_at_10[0x10];
e281682b 3647
b4ff3a36 3648 u8 reserved_at_20[0x10];
e281682b
SM		 3649 u8 op_mod[0x10];
3650
b4ff3a36 3651 u8 reserved_at_40[0x8];
e281682b
SM		 3652 u8 srqn[0x18];
3653
b4ff3a36 3654 u8 reserved_at_60[0x20];
e281682b
SM		 3655};
3656
3657struct mlx5_ifc_query_sq_out_bits {
3658 u8 status[0x8];
b4ff3a36 3659 u8 reserved_at_8[0x18];
e281682b
SM		 3660
3661 u8 syndrome[0x20];
3662
b4ff3a36 3663 u8 reserved_at_40[0xc0];
e281682b
SM		 3664
3665 struct mlx5_ifc_sqc_bits sq_context;
3666};
3667
3668struct mlx5_ifc_query_sq_in_bits {
3669 u8 opcode[0x10];
b4ff3a36 3670 u8 reserved_at_10[0x10];
e281682b 3671
b4ff3a36 3672 u8 reserved_at_20[0x10];
e281682b
SM		 3673 u8 op_mod[0x10];
3674
b4ff3a36 3675 u8 reserved_at_40[0x8];
e281682b
SM		 3676 u8 sqn[0x18];
3677
b4ff3a36 3678 u8 reserved_at_60[0x20];
e281682b
SM		 3679};
3680
3681struct mlx5_ifc_query_special_contexts_out_bits {
3682 u8 status[0x8];
b4ff3a36 3683 u8 reserved_at_8[0x18];
e281682b
SM		 3684
3685 u8 syndrome[0x20];
3686
ec22eb53 3687 u8 dump_fill_mkey[0x20];
e281682b
SM		 3688
3689 u8 resd_lkey[0x20];
bcda1aca
AK		 3690
3691 u8 null_mkey[0x20];
3692
3693 u8 reserved_at_a0[0x60];
e281682b
SM		 3694};
3695
3696struct mlx5_ifc_query_special_contexts_in_bits {
3697 u8 opcode[0x10];
b4ff3a36 3698 u8 reserved_at_10[0x10];
e281682b 3699
b4ff3a36 3700 u8 reserved_at_20[0x10];
e281682b
SM		 3701 u8 op_mod[0x10];
3702
b4ff3a36 3703 u8 reserved_at_40[0x40];
e281682b
SM		 3704};
3705
813f8540
MHY		 3706struct mlx5_ifc_query_scheduling_element_out_bits {
3707 u8 opcode[0x10];
3708 u8 reserved_at_10[0x10];
3709
3710 u8 reserved_at_20[0x10];
3711 u8 op_mod[0x10];
3712
3713 u8 reserved_at_40[0xc0];
3714
3715 struct mlx5_ifc_scheduling_context_bits scheduling_context;
3716
3717 u8 reserved_at_300[0x100];
3718};
3719
3720enum {
3721 SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
3722};
3723
3724struct mlx5_ifc_query_scheduling_element_in_bits {
3725 u8 opcode[0x10];
3726 u8 reserved_at_10[0x10];
3727
3728 u8 reserved_at_20[0x10];
3729 u8 op_mod[0x10];
3730
3731 u8 scheduling_hierarchy[0x8];
3732 u8 reserved_at_48[0x18];
3733
3734 u8 scheduling_element_id[0x20];
3735
3736 u8 reserved_at_80[0x180];
3737};
3738
e281682b
SM		 3739struct mlx5_ifc_query_rqt_out_bits {
3740 u8 status[0x8];
b4ff3a36 3741 u8 reserved_at_8[0x18];
e281682b
SM		 3742
3743 u8 syndrome[0x20];
3744
b4ff3a36 3745 u8 reserved_at_40[0xc0];
e281682b
SM		 3746
3747 struct mlx5_ifc_rqtc_bits rqt_context;
3748};
3749
3750struct mlx5_ifc_query_rqt_in_bits {
3751 u8 opcode[0x10];
b4ff3a36 3752 u8 reserved_at_10[0x10];
e281682b 3753
b4ff3a36 3754 u8 reserved_at_20[0x10];
e281682b
SM		 3755 u8 op_mod[0x10];
3756
b4ff3a36 3757 u8 reserved_at_40[0x8];
e281682b
SM		 3758 u8 rqtn[0x18];
3759
b4ff3a36 3760 u8 reserved_at_60[0x20];
e281682b
SM		 3761};
3762
3763struct mlx5_ifc_query_rq_out_bits {
3764 u8 status[0x8];
b4ff3a36 3765 u8 reserved_at_8[0x18];
e281682b
SM		 3766
3767 u8 syndrome[0x20];
3768
b4ff3a36 3769 u8 reserved_at_40[0xc0];
e281682b
SM		 3770
3771 struct mlx5_ifc_rqc_bits rq_context;
3772};
3773
3774struct mlx5_ifc_query_rq_in_bits {
3775 u8 opcode[0x10];
b4ff3a36 3776 u8 reserved_at_10[0x10];
e281682b 3777
b4ff3a36 3778 u8 reserved_at_20[0x10];
e281682b
SM		 3779 u8 op_mod[0x10];
3780
b4ff3a36 3781 u8 reserved_at_40[0x8];
e281682b
SM		 3782 u8 rqn[0x18];
3783
b4ff3a36 3784 u8 reserved_at_60[0x20];
e281682b
SM		 3785};
3786
3787struct mlx5_ifc_query_roce_address_out_bits {
3788 u8 status[0x8];
b4ff3a36 3789 u8 reserved_at_8[0x18];
e281682b
SM		 3790
3791 u8 syndrome[0x20];
3792
b4ff3a36 3793 u8 reserved_at_40[0x40];
e281682b
SM		 3794
3795 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3796};
3797
3798struct mlx5_ifc_query_roce_address_in_bits {
3799 u8 opcode[0x10];
b4ff3a36 3800 u8 reserved_at_10[0x10];
e281682b 3801
b4ff3a36 3802 u8 reserved_at_20[0x10];
e281682b
SM		 3803 u8 op_mod[0x10];
3804
3805 u8 roce_address_index[0x10];
b4ff3a36 3806 u8 reserved_at_50[0x10];
e281682b 3807
b4ff3a36 3808 u8 reserved_at_60[0x20];
e281682b
SM		 3809};
3810
3811struct mlx5_ifc_query_rmp_out_bits {
3812 u8 status[0x8];
b4ff3a36 3813 u8 reserved_at_8[0x18];
e281682b
SM		 3814
3815 u8 syndrome[0x20];
3816
b4ff3a36 3817 u8 reserved_at_40[0xc0];
e281682b
SM		 3818
3819 struct mlx5_ifc_rmpc_bits rmp_context;
3820};
3821
3822struct mlx5_ifc_query_rmp_in_bits {
3823 u8 opcode[0x10];
b4ff3a36 3824 u8 reserved_at_10[0x10];
e281682b 3825
b4ff3a36 3826 u8 reserved_at_20[0x10];
e281682b
SM		 3827 u8 op_mod[0x10];
3828
b4ff3a36 3829 u8 reserved_at_40[0x8];
e281682b
SM		 3830 u8 rmpn[0x18];
3831
b4ff3a36 3832 u8 reserved_at_60[0x20];
e281682b
SM		 3833};
3834
3835struct mlx5_ifc_query_qp_out_bits {
3836 u8 status[0x8];
b4ff3a36 3837 u8 reserved_at_8[0x18];
e281682b
SM		 3838
3839 u8 syndrome[0x20];
3840
b4ff3a36 3841 u8 reserved_at_40[0x40];
e281682b
SM		 3842
3843 u8 opt_param_mask[0x20];
3844
b4ff3a36 3845 u8 reserved_at_a0[0x20];
e281682b
SM		 3846
3847 struct mlx5_ifc_qpc_bits qpc;
3848
b4ff3a36 3849 u8 reserved_at_800[0x80];
e281682b
SM		 3850
3851 u8 pas[0][0x40];
3852};
3853
3854struct mlx5_ifc_query_qp_in_bits {
3855 u8 opcode[0x10];
b4ff3a36 3856 u8 reserved_at_10[0x10];
e281682b 3857
b4ff3a36 3858 u8 reserved_at_20[0x10];
e281682b
SM		 3859 u8 op_mod[0x10];
3860
b4ff3a36 3861 u8 reserved_at_40[0x8];
e281682b
SM		 3862 u8 qpn[0x18];
3863
b4ff3a36 3864 u8 reserved_at_60[0x20];
e281682b
SM		 3865};
3866
3867struct mlx5_ifc_query_q_counter_out_bits {
3868 u8 status[0x8];
b4ff3a36 3869 u8 reserved_at_8[0x18];
e281682b
SM		 3870
3871 u8 syndrome[0x20];
3872
b4ff3a36 3873 u8 reserved_at_40[0x40];
e281682b
SM		 3874
3875 u8 rx_write_requests[0x20];
3876
b4ff3a36 3877 u8 reserved_at_a0[0x20];
e281682b
SM		 3878
3879 u8 rx_read_requests[0x20];
3880
b4ff3a36 3881 u8 reserved_at_e0[0x20];
e281682b
SM		 3882
3883 u8 rx_atomic_requests[0x20];
3884
b4ff3a36 3885 u8 reserved_at_120[0x20];
e281682b
SM		 3886
3887 u8 rx_dct_connect[0x20];
3888
b4ff3a36 3889 u8 reserved_at_160[0x20];
e281682b
SM		 3890
3891 u8 out_of_buffer[0x20];
3892
b4ff3a36 3893 u8 reserved_at_1a0[0x20];
e281682b
SM		 3894
3895 u8 out_of_sequence[0x20];
3896
7486216b
SM		 3897 u8 reserved_at_1e0[0x20];
3898
3899 u8 duplicate_request[0x20];
3900
3901 u8 reserved_at_220[0x20];
3902
3903 u8 rnr_nak_retry_err[0x20];
3904
3905 u8 reserved_at_260[0x20];
3906
3907 u8 packet_seq_err[0x20];
3908
3909 u8 reserved_at_2a0[0x20];
3910
3911 u8 implied_nak_seq_err[0x20];
3912
3913 u8 reserved_at_2e0[0x20];
3914
3915 u8 local_ack_timeout_err[0x20];
3916
3917 u8 reserved_at_320[0x4e0];
e281682b
SM		 3918};
3919
3920struct mlx5_ifc_query_q_counter_in_bits {
3921 u8 opcode[0x10];
b4ff3a36 3922 u8 reserved_at_10[0x10];
e281682b 3923
b4ff3a36 3924 u8 reserved_at_20[0x10];
e281682b
SM		 3925 u8 op_mod[0x10];
3926
b4ff3a36 3927 u8 reserved_at_40[0x80];
e281682b
SM		 3928
3929 u8 clear[0x1];
b4ff3a36 3930 u8 reserved_at_c1[0x1f];
e281682b 3931
b4ff3a36 3932 u8 reserved_at_e0[0x18];
e281682b
SM		 3933 u8 counter_set_id[0x8];
3934};
3935
3936struct mlx5_ifc_query_pages_out_bits {
3937 u8 status[0x8];
b4ff3a36 3938 u8 reserved_at_8[0x18];
e281682b
SM		 3939
3940 u8 syndrome[0x20];
3941
b4ff3a36 3942 u8 reserved_at_40[0x10];
e281682b
SM		 3943 u8 function_id[0x10];
3944
3945 u8 num_pages[0x20];
3946};
3947
3948enum {
3949 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
3950 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
3951 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
3952};
3953
3954struct mlx5_ifc_query_pages_in_bits {
3955 u8 opcode[0x10];
b4ff3a36 3956 u8 reserved_at_10[0x10];
e281682b 3957
b4ff3a36 3958 u8 reserved_at_20[0x10];
e281682b
SM		 3959 u8 op_mod[0x10];
3960
b4ff3a36 3961 u8 reserved_at_40[0x10];
e281682b
SM		 3962 u8 function_id[0x10];
3963
b4ff3a36 3964 u8 reserved_at_60[0x20];
e281682b
SM		 3965};
3966
3967struct mlx5_ifc_query_nic_vport_context_out_bits {
3968 u8 status[0x8];
b4ff3a36 3969 u8 reserved_at_8[0x18];
e281682b
SM		 3970
3971 u8 syndrome[0x20];
3972
b4ff3a36 3973 u8 reserved_at_40[0x40];
e281682b
SM		 3974
3975 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
3976};
3977
3978struct mlx5_ifc_query_nic_vport_context_in_bits {
3979 u8 opcode[0x10];
b4ff3a36 3980 u8 reserved_at_10[0x10];
e281682b 3981
b4ff3a36 3982 u8 reserved_at_20[0x10];
e281682b
SM		 3983 u8 op_mod[0x10];
3984
3985 u8 other_vport[0x1];
b4ff3a36 3986 u8 reserved_at_41[0xf];
e281682b
SM		 3987 u8 vport_number[0x10];
3988
b4ff3a36 3989 u8 reserved_at_60[0x5];
e281682b 3990 u8 allowed_list_type[0x3];
b4ff3a36 3991 u8 reserved_at_68[0x18];
e281682b
SM		 3992};
3993
3994struct mlx5_ifc_query_mkey_out_bits {
3995 u8 status[0x8];
b4ff3a36 3996 u8 reserved_at_8[0x18];
e281682b
SM		 3997
3998 u8 syndrome[0x20];
3999
b4ff3a36 4000 u8 reserved_at_40[0x40];
e281682b
SM		 4001
4002 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
4003
b4ff3a36 4004 u8 reserved_at_280[0x600];
e281682b
SM		 4005
4006 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
4007
4008 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
4009};
4010
4011struct mlx5_ifc_query_mkey_in_bits {
4012 u8 opcode[0x10];
b4ff3a36 4013 u8 reserved_at_10[0x10];
e281682b 4014
b4ff3a36 4015 u8 reserved_at_20[0x10];
e281682b
SM		 4016 u8 op_mod[0x10];
4017
b4ff3a36 4018 u8 reserved_at_40[0x8];
e281682b
SM		 4019 u8 mkey_index[0x18];
4020
4021 u8 pg_access[0x1];
b4ff3a36 4022 u8 reserved_at_61[0x1f];
e281682b
SM		 4023};
4024
4025struct mlx5_ifc_query_mad_demux_out_bits {
4026 u8 status[0x8];
b4ff3a36 4027 u8 reserved_at_8[0x18];
e281682b
SM		 4028
4029 u8 syndrome[0x20];
4030
b4ff3a36 4031 u8 reserved_at_40[0x40];
e281682b
SM		 4032
4033 u8 mad_dumux_parameters_block[0x20];
4034};
4035
4036struct mlx5_ifc_query_mad_demux_in_bits {
4037 u8 opcode[0x10];
b4ff3a36 4038 u8 reserved_at_10[0x10];
e281682b 4039
b4ff3a36 4040 u8 reserved_at_20[0x10];
e281682b
SM		 4041 u8 op_mod[0x10];
4042
b4ff3a36 4043 u8 reserved_at_40[0x40];
e281682b
SM		 4044};
4045
4046struct mlx5_ifc_query_l2_table_entry_out_bits {
4047 u8 status[0x8];
b4ff3a36 4048 u8 reserved_at_8[0x18];
e281682b
SM		 4049
4050 u8 syndrome[0x20];
4051
b4ff3a36 4052 u8 reserved_at_40[0xa0];
e281682b 4053
b4ff3a36 4054 u8 reserved_at_e0[0x13];
e281682b
SM		 4055 u8 vlan_valid[0x1];
4056 u8 vlan[0xc];
4057
4058 struct mlx5_ifc_mac_address_layout_bits mac_address;
4059
b4ff3a36 4060 u8 reserved_at_140[0xc0];
e281682b
SM		 4061};
4062
4063struct mlx5_ifc_query_l2_table_entry_in_bits {
4064 u8 opcode[0x10];
b4ff3a36 4065 u8 reserved_at_10[0x10];
e281682b 4066
b4ff3a36 4067 u8 reserved_at_20[0x10];
e281682b
SM		 4068 u8 op_mod[0x10];
4069
b4ff3a36 4070 u8 reserved_at_40[0x60];
e281682b 4071
b4ff3a36 4072 u8 reserved_at_a0[0x8];
e281682b
SM		 4073 u8 table_index[0x18];
4074
b4ff3a36 4075 u8 reserved_at_c0[0x140];
e281682b
SM		 4076};
4077
4078struct mlx5_ifc_query_issi_out_bits {
4079 u8 status[0x8];
b4ff3a36 4080 u8 reserved_at_8[0x18];
e281682b
SM		 4081
4082 u8 syndrome[0x20];
4083
b4ff3a36 4084 u8 reserved_at_40[0x10];
e281682b
SM		 4085 u8 current_issi[0x10];
4086
b4ff3a36 4087 u8 reserved_at_60[0xa0];
e281682b 4088
b4ff3a36 4089 u8 reserved_at_100[76][0x8];
e281682b
SM		 4090 u8 supported_issi_dw0[0x20];
4091};
4092
4093struct mlx5_ifc_query_issi_in_bits {
4094 u8 opcode[0x10];
b4ff3a36 4095 u8 reserved_at_10[0x10];
e281682b 4096
b4ff3a36 4097 u8 reserved_at_20[0x10];
e281682b
SM		 4098 u8 op_mod[0x10];
4099
b4ff3a36 4100 u8 reserved_at_40[0x40];
e281682b
SM		 4101};
4102
0dbc6fe0
SM		 4103struct mlx5_ifc_set_driver_version_out_bits {
4104 u8 status[0x8];
4105 u8 reserved_0[0x18];
4106
4107 u8 syndrome[0x20];
4108 u8 reserved_1[0x40];
4109};
4110
4111struct mlx5_ifc_set_driver_version_in_bits {
4112 u8 opcode[0x10];
4113 u8 reserved_0[0x10];
4114
4115 u8 reserved_1[0x10];
4116 u8 op_mod[0x10];
4117
4118 u8 reserved_2[0x40];
4119 u8 driver_version[64][0x8];
4120};
4121
e281682b
SM		 4122struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4123 u8 status[0x8];
b4ff3a36 4124 u8 reserved_at_8[0x18];
e281682b
SM		 4125
4126 u8 syndrome[0x20];
4127
b4ff3a36 4128 u8 reserved_at_40[0x40];
e281682b
SM		 4129
4130 struct mlx5_ifc_pkey_bits pkey[0];
4131};
4132
4133struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4134 u8 opcode[0x10];
b4ff3a36 4135 u8 reserved_at_10[0x10];
e281682b 4136
b4ff3a36 4137 u8 reserved_at_20[0x10];
e281682b
SM		 4138 u8 op_mod[0x10];
4139
4140 u8 other_vport[0x1];
b4ff3a36 4141 u8 reserved_at_41[0xb];
707c4602 4142 u8 port_num[0x4];
e281682b
SM		 4143 u8 vport_number[0x10];
4144
b4ff3a36 4145 u8 reserved_at_60[0x10];
e281682b
SM		 4146 u8 pkey_index[0x10];
4147};
4148
eff901d3
EC		 4149enum {
4150 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
4151 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
4152 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4153};
4154
e281682b
SM		 4155struct mlx5_ifc_query_hca_vport_gid_out_bits {
4156 u8 status[0x8];
b4ff3a36 4157 u8 reserved_at_8[0x18];
e281682b
SM		 4158
4159 u8 syndrome[0x20];
4160
b4ff3a36 4161 u8 reserved_at_40[0x20];
e281682b
SM		 4162
4163 u8 gids_num[0x10];
b4ff3a36 4164 u8 reserved_at_70[0x10];
e281682b
SM		 4165
4166 struct mlx5_ifc_array128_auto_bits gid[0];
4167};
4168
4169struct mlx5_ifc_query_hca_vport_gid_in_bits {
4170 u8 opcode[0x10];
b4ff3a36 4171 u8 reserved_at_10[0x10];
e281682b 4172
b4ff3a36 4173 u8 reserved_at_20[0x10];
e281682b
SM		 4174 u8 op_mod[0x10];
4175
4176 u8 other_vport[0x1];
b4ff3a36 4177 u8 reserved_at_41[0xb];
707c4602 4178 u8 port_num[0x4];
e281682b
SM		 4179 u8 vport_number[0x10];
4180
b4ff3a36 4181 u8 reserved_at_60[0x10];
e281682b
SM		 4182 u8 gid_index[0x10];
4183};
4184
4185struct mlx5_ifc_query_hca_vport_context_out_bits {
4186 u8 status[0x8];
b4ff3a36 4187 u8 reserved_at_8[0x18];
e281682b
SM		 4188
4189 u8 syndrome[0x20];
4190
b4ff3a36 4191 u8 reserved_at_40[0x40];
e281682b
SM		 4192
4193 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4194};
4195
4196struct mlx5_ifc_query_hca_vport_context_in_bits {
4197 u8 opcode[0x10];
b4ff3a36 4198 u8 reserved_at_10[0x10];
e281682b 4199
b4ff3a36 4200 u8 reserved_at_20[0x10];
e281682b
SM		 4201 u8 op_mod[0x10];
4202
4203 u8 other_vport[0x1];
b4ff3a36 4204 u8 reserved_at_41[0xb];
707c4602 4205 u8 port_num[0x4];
e281682b
SM		 4206 u8 vport_number[0x10];
4207
b4ff3a36 4208 u8 reserved_at_60[0x20];
e281682b
SM		 4209};
4210
4211struct mlx5_ifc_query_hca_cap_out_bits {
4212 u8 status[0x8];
b4ff3a36 4213 u8 reserved_at_8[0x18];
e281682b
SM		 4214
4215 u8 syndrome[0x20];
4216
b4ff3a36 4217 u8 reserved_at_40[0x40];
e281682b
SM		 4218
4219 union mlx5_ifc_hca_cap_union_bits capability;
4220};
4221
4222struct mlx5_ifc_query_hca_cap_in_bits {
4223 u8 opcode[0x10];
b4ff3a36 4224 u8 reserved_at_10[0x10];
e281682b 4225
b4ff3a36 4226 u8 reserved_at_20[0x10];
e281682b
SM		 4227 u8 op_mod[0x10];
4228
b4ff3a36 4229 u8 reserved_at_40[0x40];
e281682b
SM		 4230};
4231
4232struct mlx5_ifc_query_flow_table_out_bits {
4233 u8 status[0x8];
b4ff3a36 4234 u8 reserved_at_8[0x18];
e281682b
SM		 4235
4236 u8 syndrome[0x20];
4237
b4ff3a36 4238 u8 reserved_at_40[0x80];
e281682b 4239
b4ff3a36 4240 u8 reserved_at_c0[0x8];
e281682b 4241 u8 level[0x8];
b4ff3a36 4242 u8 reserved_at_d0[0x8];
e281682b
SM		 4243 u8 log_size[0x8];
4244
b4ff3a36 4245 u8 reserved_at_e0[0x120];
e281682b
SM		 4246};
4247
4248struct mlx5_ifc_query_flow_table_in_bits {
4249 u8 opcode[0x10];
b4ff3a36 4250 u8 reserved_at_10[0x10];
e281682b 4251
b4ff3a36 4252 u8 reserved_at_20[0x10];
e281682b
SM		 4253 u8 op_mod[0x10];
4254
b4ff3a36 4255 u8 reserved_at_40[0x40];
e281682b
SM		 4256
4257 u8 table_type[0x8];
b4ff3a36 4258 u8 reserved_at_88[0x18];
e281682b 4259
b4ff3a36 4260 u8 reserved_at_a0[0x8];
e281682b
SM		 4261 u8 table_id[0x18];
4262
b4ff3a36 4263 u8 reserved_at_c0[0x140];
e281682b
SM		 4264};
4265
4266struct mlx5_ifc_query_fte_out_bits {
4267 u8 status[0x8];
b4ff3a36 4268 u8 reserved_at_8[0x18];
e281682b
SM		 4269
4270 u8 syndrome[0x20];
4271
b4ff3a36 4272 u8 reserved_at_40[0x1c0];
e281682b
SM		 4273
4274 struct mlx5_ifc_flow_context_bits flow_context;
4275};
4276
4277struct mlx5_ifc_query_fte_in_bits {
4278 u8 opcode[0x10];
b4ff3a36 4279 u8 reserved_at_10[0x10];
e281682b 4280
b4ff3a36 4281 u8 reserved_at_20[0x10];
e281682b
SM		 4282 u8 op_mod[0x10];
4283
b4ff3a36 4284 u8 reserved_at_40[0x40];
e281682b
SM		 4285
4286 u8 table_type[0x8];
b4ff3a36 4287 u8 reserved_at_88[0x18];
e281682b 4288
b4ff3a36 4289 u8 reserved_at_a0[0x8];
e281682b
SM		 4290 u8 table_id[0x18];
4291
b4ff3a36 4292 u8 reserved_at_c0[0x40];
e281682b
SM		 4293
4294 u8 flow_index[0x20];
4295
b4ff3a36 4296 u8 reserved_at_120[0xe0];
e281682b
SM		 4297};
4298
4299enum {
4300 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
4301 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
4302 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
4303};
4304
4305struct mlx5_ifc_query_flow_group_out_bits {
4306 u8 status[0x8];
b4ff3a36 4307 u8 reserved_at_8[0x18];
e281682b
SM		 4308
4309 u8 syndrome[0x20];
4310
b4ff3a36 4311 u8 reserved_at_40[0xa0];
e281682b
SM		 4312
4313 u8 start_flow_index[0x20];
4314
b4ff3a36 4315 u8 reserved_at_100[0x20];
e281682b
SM		 4316
4317 u8 end_flow_index[0x20];
4318
b4ff3a36 4319 u8 reserved_at_140[0xa0];
e281682b 4320
b4ff3a36 4321 u8 reserved_at_1e0[0x18];
e281682b
SM		 4322 u8 match_criteria_enable[0x8];
4323
4324 struct mlx5_ifc_fte_match_param_bits match_criteria;
4325
b4ff3a36 4326 u8 reserved_at_1200[0xe00];
e281682b
SM		 4327};
4328
4329struct mlx5_ifc_query_flow_group_in_bits {
4330 u8 opcode[0x10];
b4ff3a36 4331 u8 reserved_at_10[0x10];
e281682b 4332
b4ff3a36 4333 u8 reserved_at_20[0x10];
e281682b
SM		 4334 u8 op_mod[0x10];
4335
b4ff3a36 4336 u8 reserved_at_40[0x40];
e281682b
SM		 4337
4338 u8 table_type[0x8];
b4ff3a36 4339 u8 reserved_at_88[0x18];
e281682b 4340
b4ff3a36 4341 u8 reserved_at_a0[0x8];
e281682b
SM		 4342 u8 table_id[0x18];
4343
4344 u8 group_id[0x20];
4345
b4ff3a36 4346 u8 reserved_at_e0[0x120];
e281682b
SM		 4347};
4348
9dc0b289
AV		 4349struct mlx5_ifc_query_flow_counter_out_bits {
4350 u8 status[0x8];
4351 u8 reserved_at_8[0x18];
4352
4353 u8 syndrome[0x20];
4354
4355 u8 reserved_at_40[0x40];
4356
4357 struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4358};
4359
4360struct mlx5_ifc_query_flow_counter_in_bits {
4361 u8 opcode[0x10];
4362 u8 reserved_at_10[0x10];
4363
4364 u8 reserved_at_20[0x10];
4365 u8 op_mod[0x10];
4366
4367 u8 reserved_at_40[0x80];
4368
4369 u8 clear[0x1];
4370 u8 reserved_at_c1[0xf];
4371 u8 num_of_counters[0x10];
4372
4373 u8 reserved_at_e0[0x10];
4374 u8 flow_counter_id[0x10];
4375};
4376
d6666753
SM		 4377struct mlx5_ifc_query_esw_vport_context_out_bits {
4378 u8 status[0x8];
b4ff3a36 4379 u8 reserved_at_8[0x18];
d6666753
SM		 4380
4381 u8 syndrome[0x20];
4382
b4ff3a36 4383 u8 reserved_at_40[0x40];
d6666753
SM		 4384
4385 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4386};
4387
4388struct mlx5_ifc_query_esw_vport_context_in_bits {
4389 u8 opcode[0x10];
b4ff3a36 4390 u8 reserved_at_10[0x10];
d6666753 4391
b4ff3a36 4392 u8 reserved_at_20[0x10];
d6666753
SM		 4393 u8 op_mod[0x10];
4394
4395 u8 other_vport[0x1];
b4ff3a36 4396 u8 reserved_at_41[0xf];
d6666753
SM		 4397 u8 vport_number[0x10];
4398
b4ff3a36 4399 u8 reserved_at_60[0x20];
d6666753
SM		 4400};
4401
4402struct mlx5_ifc_modify_esw_vport_context_out_bits {
4403 u8 status[0x8];
b4ff3a36 4404 u8 reserved_at_8[0x18];
d6666753
SM		 4405
4406 u8 syndrome[0x20];
4407
b4ff3a36 4408 u8 reserved_at_40[0x40];
d6666753
SM		 4409};
4410
4411struct mlx5_ifc_esw_vport_context_fields_select_bits {
b4ff3a36 4412 u8 reserved_at_0[0x1c];
d6666753
SM		 4413 u8 vport_cvlan_insert[0x1];
4414 u8 vport_svlan_insert[0x1];
4415 u8 vport_cvlan_strip[0x1];
4416 u8 vport_svlan_strip[0x1];
4417};
4418
4419struct mlx5_ifc_modify_esw_vport_context_in_bits {
4420 u8 opcode[0x10];
b4ff3a36 4421 u8 reserved_at_10[0x10];
d6666753 4422
b4ff3a36 4423 u8 reserved_at_20[0x10];
d6666753
SM		 4424 u8 op_mod[0x10];
4425
4426 u8 other_vport[0x1];
b4ff3a36 4427 u8 reserved_at_41[0xf];
d6666753
SM		 4428 u8 vport_number[0x10];
4429
4430 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4431
4432 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4433};
4434
e281682b
SM		 4435struct mlx5_ifc_query_eq_out_bits {
4436 u8 status[0x8];
b4ff3a36 4437 u8 reserved_at_8[0x18];
e281682b
SM		 4438
4439 u8 syndrome[0x20];
4440
b4ff3a36 4441 u8 reserved_at_40[0x40];
e281682b
SM		 4442
4443 struct mlx5_ifc_eqc_bits eq_context_entry;
4444
b4ff3a36 4445 u8 reserved_at_280[0x40];
e281682b
SM		 4446
4447 u8 event_bitmask[0x40];
4448
b4ff3a36 4449 u8 reserved_at_300[0x580];
e281682b
SM		 4450
4451 u8 pas[0][0x40];
4452};
4453
4454struct mlx5_ifc_query_eq_in_bits {
4455 u8 opcode[0x10];
b4ff3a36 4456 u8 reserved_at_10[0x10];
e281682b 4457
b4ff3a36 4458 u8 reserved_at_20[0x10];
e281682b
SM		 4459 u8 op_mod[0x10];
4460
b4ff3a36 4461 u8 reserved_at_40[0x18];
e281682b
SM		 4462 u8 eq_number[0x8];
4463
b4ff3a36 4464 u8 reserved_at_60[0x20];
e281682b
SM		 4465};
4466
7adbde20
HHZ		 4467struct mlx5_ifc_encap_header_in_bits {
4468 u8 reserved_at_0[0x5];
4469 u8 header_type[0x3];
4470 u8 reserved_at_8[0xe];
4471 u8 encap_header_size[0xa];
4472
4473 u8 reserved_at_20[0x10];
4474 u8 encap_header[2][0x8];
4475
4476 u8 more_encap_header[0][0x8];
4477};
4478
4479struct mlx5_ifc_query_encap_header_out_bits {
4480 u8 status[0x8];
4481 u8 reserved_at_8[0x18];
4482
4483 u8 syndrome[0x20];
4484
4485 u8 reserved_at_40[0xa0];
4486
4487 struct mlx5_ifc_encap_header_in_bits encap_header[0];
4488};
4489
4490struct mlx5_ifc_query_encap_header_in_bits {
4491 u8 opcode[0x10];
4492 u8 reserved_at_10[0x10];
4493
4494 u8 reserved_at_20[0x10];
4495 u8 op_mod[0x10];
4496
4497 u8 encap_id[0x20];
4498
4499 u8 reserved_at_60[0xa0];
4500};
4501
4502struct mlx5_ifc_alloc_encap_header_out_bits {
4503 u8 status[0x8];
4504 u8 reserved_at_8[0x18];
4505
4506 u8 syndrome[0x20];
4507
4508 u8 encap_id[0x20];
4509
4510 u8 reserved_at_60[0x20];
4511};
4512
4513struct mlx5_ifc_alloc_encap_header_in_bits {
4514 u8 opcode[0x10];
4515 u8 reserved_at_10[0x10];
4516
4517 u8 reserved_at_20[0x10];
4518 u8 op_mod[0x10];
4519
4520 u8 reserved_at_40[0xa0];
4521
4522 struct mlx5_ifc_encap_header_in_bits encap_header;
4523};
4524
4525struct mlx5_ifc_dealloc_encap_header_out_bits {
4526 u8 status[0x8];
4527 u8 reserved_at_8[0x18];
4528
4529 u8 syndrome[0x20];
4530
4531 u8 reserved_at_40[0x40];
4532};
4533
4534struct mlx5_ifc_dealloc_encap_header_in_bits {
4535 u8 opcode[0x10];
4536 u8 reserved_at_10[0x10];
4537
4538 u8 reserved_20[0x10];
4539 u8 op_mod[0x10];
4540
4541 u8 encap_id[0x20];
4542
4543 u8 reserved_60[0x20];
4544};
4545
2a69cb9f
OG		 4546struct mlx5_ifc_set_action_in_bits {
4547 u8 action_type[0x4];
4548 u8 field[0xc];
4549 u8 reserved_at_10[0x3];
4550 u8 offset[0x5];
4551 u8 reserved_at_18[0x3];
4552 u8 length[0x5];
4553
4554 u8 data[0x20];
4555};
4556
4557struct mlx5_ifc_add_action_in_bits {
4558 u8 action_type[0x4];
4559 u8 field[0xc];
4560 u8 reserved_at_10[0x10];
4561
4562 u8 data[0x20];
4563};
4564
4565union mlx5_ifc_set_action_in_add_action_in_auto_bits {
4566 struct mlx5_ifc_set_action_in_bits set_action_in;
4567 struct mlx5_ifc_add_action_in_bits add_action_in;
4568 u8 reserved_at_0[0x40];
4569};
4570
4571enum {
4572 MLX5_ACTION_TYPE_SET = 0x1,
4573 MLX5_ACTION_TYPE_ADD = 0x2,
4574};
4575
4576enum {
4577 MLX5_ACTION_IN_FIELD_OUT_SMAC_47_16 = 0x1,
4578 MLX5_ACTION_IN_FIELD_OUT_SMAC_15_0 = 0x2,
4579 MLX5_ACTION_IN_FIELD_OUT_ETHERTYPE = 0x3,
4580 MLX5_ACTION_IN_FIELD_OUT_DMAC_47_16 = 0x4,
4581 MLX5_ACTION_IN_FIELD_OUT_DMAC_15_0 = 0x5,
4582 MLX5_ACTION_IN_FIELD_OUT_IP_DSCP = 0x6,
4583 MLX5_ACTION_IN_FIELD_OUT_TCP_FLAGS = 0x7,
4584 MLX5_ACTION_IN_FIELD_OUT_TCP_SPORT = 0x8,
4585 MLX5_ACTION_IN_FIELD_OUT_TCP_DPORT = 0x9,
4586 MLX5_ACTION_IN_FIELD_OUT_IP_TTL = 0xa,
4587 MLX5_ACTION_IN_FIELD_OUT_UDP_SPORT = 0xb,
4588 MLX5_ACTION_IN_FIELD_OUT_UDP_DPORT = 0xc,
4589 MLX5_ACTION_IN_FIELD_OUT_SIPV6_127_96 = 0xd,
4590 MLX5_ACTION_IN_FIELD_OUT_SIPV6_95_64 = 0xe,
4591 MLX5_ACTION_IN_FIELD_OUT_SIPV6_63_32 = 0xf,
4592 MLX5_ACTION_IN_FIELD_OUT_SIPV6_31_0 = 0x10,
4593 MLX5_ACTION_IN_FIELD_OUT_DIPV6_127_96 = 0x11,
4594 MLX5_ACTION_IN_FIELD_OUT_DIPV6_95_64 = 0x12,
4595 MLX5_ACTION_IN_FIELD_OUT_DIPV6_63_32 = 0x13,
4596 MLX5_ACTION_IN_FIELD_OUT_DIPV6_31_0 = 0x14,
4597 MLX5_ACTION_IN_FIELD_OUT_SIPV4 = 0x15,
4598 MLX5_ACTION_IN_FIELD_OUT_DIPV4 = 0x16,
4599};
4600
4601struct mlx5_ifc_alloc_modify_header_context_out_bits {
4602 u8 status[0x8];
4603 u8 reserved_at_8[0x18];
4604
4605 u8 syndrome[0x20];
4606
4607 u8 modify_header_id[0x20];
4608
4609 u8 reserved_at_60[0x20];
4610};
4611
4612struct mlx5_ifc_alloc_modify_header_context_in_bits {
4613 u8 opcode[0x10];
4614 u8 reserved_at_10[0x10];
4615
4616 u8 reserved_at_20[0x10];
4617 u8 op_mod[0x10];
4618
4619 u8 reserved_at_40[0x20];
4620
4621 u8 table_type[0x8];
4622 u8 reserved_at_68[0x10];
4623 u8 num_of_actions[0x8];
4624
4625 union mlx5_ifc_set_action_in_add_action_in_auto_bits actions[0];
4626};
4627
4628struct mlx5_ifc_dealloc_modify_header_context_out_bits {
4629 u8 status[0x8];
4630 u8 reserved_at_8[0x18];
4631
4632 u8 syndrome[0x20];
4633
4634 u8 reserved_at_40[0x40];
4635};
4636
4637struct mlx5_ifc_dealloc_modify_header_context_in_bits {
4638 u8 opcode[0x10];
4639 u8 reserved_at_10[0x10];
4640
4641 u8 reserved_at_20[0x10];
4642 u8 op_mod[0x10];
4643
4644 u8 modify_header_id[0x20];
4645
4646 u8 reserved_at_60[0x20];
4647};
4648
e281682b
SM		 4649struct mlx5_ifc_query_dct_out_bits {
4650 u8 status[0x8];
b4ff3a36 4651 u8 reserved_at_8[0x18];
e281682b
SM		 4652
4653 u8 syndrome[0x20];
4654
b4ff3a36 4655 u8 reserved_at_40[0x40];
e281682b
SM		 4656
4657 struct mlx5_ifc_dctc_bits dct_context_entry;
4658
b4ff3a36 4659 u8 reserved_at_280[0x180];
e281682b
SM		 4660};
4661
4662struct mlx5_ifc_query_dct_in_bits {
4663 u8 opcode[0x10];
b4ff3a36 4664 u8 reserved_at_10[0x10];
e281682b 4665
b4ff3a36 4666 u8 reserved_at_20[0x10];
e281682b
SM		 4667 u8 op_mod[0x10];
4668
b4ff3a36 4669 u8 reserved_at_40[0x8];
e281682b
SM		 4670 u8 dctn[0x18];
4671
b4ff3a36 4672 u8 reserved_at_60[0x20];
e281682b
SM		 4673};
4674
4675struct mlx5_ifc_query_cq_out_bits {
4676 u8 status[0x8];
b4ff3a36 4677 u8 reserved_at_8[0x18];
e281682b
SM		 4678
4679 u8 syndrome[0x20];
4680
b4ff3a36 4681 u8 reserved_at_40[0x40];
e281682b
SM		 4682
4683 struct mlx5_ifc_cqc_bits cq_context;
4684
b4ff3a36 4685 u8 reserved_at_280[0x600];
e281682b
SM		 4686
4687 u8 pas[0][0x40];
4688};
4689
4690struct mlx5_ifc_query_cq_in_bits {
4691 u8 opcode[0x10];
b4ff3a36 4692 u8 reserved_at_10[0x10];
e281682b 4693
b4ff3a36 4694 u8 reserved_at_20[0x10];
e281682b
SM		 4695 u8 op_mod[0x10];
4696
b4ff3a36 4697 u8 reserved_at_40[0x8];
e281682b
SM		 4698 u8 cqn[0x18];
4699
b4ff3a36 4700 u8 reserved_at_60[0x20];
e281682b
SM		 4701};
4702
4703struct mlx5_ifc_query_cong_status_out_bits {
4704 u8 status[0x8];
b4ff3a36 4705 u8 reserved_at_8[0x18];
e281682b
SM		 4706
4707 u8 syndrome[0x20];
4708
b4ff3a36 4709 u8 reserved_at_40[0x20];
e281682b
SM		 4710
4711 u8 enable[0x1];
4712 u8 tag_enable[0x1];
b4ff3a36 4713 u8 reserved_at_62[0x1e];
e281682b
SM		 4714};
4715
4716struct mlx5_ifc_query_cong_status_in_bits {
4717 u8 opcode[0x10];
b4ff3a36 4718 u8 reserved_at_10[0x10];
e281682b 4719
b4ff3a36 4720 u8 reserved_at_20[0x10];
e281682b
SM		 4721 u8 op_mod[0x10];
4722
b4ff3a36 4723 u8 reserved_at_40[0x18];
e281682b
SM		 4724 u8 priority[0x4];
4725 u8 cong_protocol[0x4];
4726
b4ff3a36 4727 u8 reserved_at_60[0x20];
e281682b
SM		 4728};
4729
4730struct mlx5_ifc_query_cong_statistics_out_bits {
4731 u8 status[0x8];
b4ff3a36 4732 u8 reserved_at_8[0x18];
e281682b
SM		 4733
4734 u8 syndrome[0x20];
4735
b4ff3a36 4736 u8 reserved_at_40[0x40];
e281682b
SM		 4737
4738 u8 cur_flows[0x20];
4739
4740 u8 sum_flows[0x20];
4741
4742 u8 cnp_ignored_high[0x20];
4743
4744 u8 cnp_ignored_low[0x20];
4745
4746 u8 cnp_handled_high[0x20];
4747
4748 u8 cnp_handled_low[0x20];
4749
b4ff3a36 4750 u8 reserved_at_140[0x100];
e281682b
SM		 4751
4752 u8 time_stamp_high[0x20];
4753
4754 u8 time_stamp_low[0x20];
4755
4756 u8 accumulators_period[0x20];
4757
4758 u8 ecn_marked_roce_packets_high[0x20];
4759
4760 u8 ecn_marked_roce_packets_low[0x20];
4761
4762 u8 cnps_sent_high[0x20];
4763
4764 u8 cnps_sent_low[0x20];
4765
b4ff3a36 4766 u8 reserved_at_320[0x560];
e281682b
SM		 4767};
4768
4769struct mlx5_ifc_query_cong_statistics_in_bits {
4770 u8 opcode[0x10];
b4ff3a36 4771 u8 reserved_at_10[0x10];
e281682b 4772
b4ff3a36 4773 u8 reserved_at_20[0x10];
e281682b
SM		 4774 u8 op_mod[0x10];
4775
4776 u8 clear[0x1];
b4ff3a36 4777 u8 reserved_at_41[0x1f];
e281682b 4778
b4ff3a36 4779 u8 reserved_at_60[0x20];
e281682b
SM		 4780};
4781
4782struct mlx5_ifc_query_cong_params_out_bits {
4783 u8 status[0x8];
b4ff3a36 4784 u8 reserved_at_8[0x18];
e281682b
SM		 4785
4786 u8 syndrome[0x20];
4787
b4ff3a36 4788 u8 reserved_at_40[0x40];
e281682b
SM		 4789
4790 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4791};
4792
4793struct mlx5_ifc_query_cong_params_in_bits {
4794 u8 opcode[0x10];
b4ff3a36 4795 u8 reserved_at_10[0x10];
e281682b 4796
b4ff3a36 4797 u8 reserved_at_20[0x10];
e281682b
SM		 4798 u8 op_mod[0x10];
4799
b4ff3a36 4800 u8 reserved_at_40[0x1c];
e281682b
SM		 4801 u8 cong_protocol[0x4];
4802
b4ff3a36 4803 u8 reserved_at_60[0x20];
e281682b
SM		 4804};
4805
4806struct mlx5_ifc_query_adapter_out_bits {
4807 u8 status[0x8];
b4ff3a36 4808 u8 reserved_at_8[0x18];
e281682b
SM		 4809
4810 u8 syndrome[0x20];
4811
b4ff3a36 4812 u8 reserved_at_40[0x40];
e281682b
SM		 4813
4814 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4815};
4816
4817struct mlx5_ifc_query_adapter_in_bits {
4818 u8 opcode[0x10];
b4ff3a36 4819 u8 reserved_at_10[0x10];
e281682b 4820
b4ff3a36 4821 u8 reserved_at_20[0x10];
e281682b
SM		 4822 u8 op_mod[0x10];
4823
b4ff3a36 4824 u8 reserved_at_40[0x40];
e281682b
SM		 4825};
4826
4827struct mlx5_ifc_qp_2rst_out_bits {
4828 u8 status[0x8];
b4ff3a36 4829 u8 reserved_at_8[0x18];
e281682b
SM		 4830
4831 u8 syndrome[0x20];
4832
b4ff3a36 4833 u8 reserved_at_40[0x40];
e281682b
SM		 4834};
4835
4836struct mlx5_ifc_qp_2rst_in_bits {
4837 u8 opcode[0x10];
b4ff3a36 4838 u8 reserved_at_10[0x10];
e281682b 4839
b4ff3a36 4840 u8 reserved_at_20[0x10];
e281682b
SM		 4841 u8 op_mod[0x10];
4842
b4ff3a36 4843 u8 reserved_at_40[0x8];
e281682b
SM		 4844 u8 qpn[0x18];
4845
b4ff3a36 4846 u8 reserved_at_60[0x20];
e281682b
SM		 4847};
4848
4849struct mlx5_ifc_qp_2err_out_bits {
4850 u8 status[0x8];
b4ff3a36 4851 u8 reserved_at_8[0x18];
e281682b
SM		 4852
4853 u8 syndrome[0x20];
4854
b4ff3a36 4855 u8 reserved_at_40[0x40];
e281682b
SM		 4856};
4857
4858struct mlx5_ifc_qp_2err_in_bits {
4859 u8 opcode[0x10];
b4ff3a36 4860 u8 reserved_at_10[0x10];
e281682b 4861
b4ff3a36 4862 u8 reserved_at_20[0x10];
e281682b
SM		 4863 u8 op_mod[0x10];
4864
b4ff3a36 4865 u8 reserved_at_40[0x8];
e281682b
SM		 4866 u8 qpn[0x18];
4867
b4ff3a36 4868 u8 reserved_at_60[0x20];
e281682b
SM		 4869};
4870
4871struct mlx5_ifc_page_fault_resume_out_bits {
4872 u8 status[0x8];
b4ff3a36 4873 u8 reserved_at_8[0x18];
e281682b
SM		 4874
4875 u8 syndrome[0x20];
4876
b4ff3a36 4877 u8 reserved_at_40[0x40];
e281682b
SM		 4878};
4879
4880struct mlx5_ifc_page_fault_resume_in_bits {
4881 u8 opcode[0x10];
b4ff3a36 4882 u8 reserved_at_10[0x10];
e281682b 4883
b4ff3a36 4884 u8 reserved_at_20[0x10];
e281682b
SM		 4885 u8 op_mod[0x10];
4886
4887 u8 error[0x1];
b4ff3a36 4888 u8 reserved_at_41[0x4];
223cdc72
AK		 4889 u8 page_fault_type[0x3];
4890 u8 wq_number[0x18];
e281682b 4891
223cdc72
AK		 4892 u8 reserved_at_60[0x8];
4893 u8 token[0x18];
e281682b
SM		 4894};
4895
4896struct mlx5_ifc_nop_out_bits {
4897 u8 status[0x8];
b4ff3a36 4898 u8 reserved_at_8[0x18];
e281682b
SM		 4899
4900 u8 syndrome[0x20];
4901
b4ff3a36 4902 u8 reserved_at_40[0x40];
e281682b
SM		 4903};
4904
4905struct mlx5_ifc_nop_in_bits {
4906 u8 opcode[0x10];
b4ff3a36 4907 u8 reserved_at_10[0x10];
e281682b 4908
b4ff3a36 4909 u8 reserved_at_20[0x10];
e281682b
SM		 4910 u8 op_mod[0x10];
4911
b4ff3a36 4912 u8 reserved_at_40[0x40];
e281682b
SM		 4913};
4914
4915struct mlx5_ifc_modify_vport_state_out_bits {
4916 u8 status[0x8];
b4ff3a36 4917 u8 reserved_at_8[0x18];
e281682b
SM		 4918
4919 u8 syndrome[0x20];
4920
b4ff3a36 4921 u8 reserved_at_40[0x40];
e281682b
SM		 4922};
4923
4924struct mlx5_ifc_modify_vport_state_in_bits {
4925 u8 opcode[0x10];
b4ff3a36 4926 u8 reserved_at_10[0x10];
e281682b 4927
b4ff3a36 4928 u8 reserved_at_20[0x10];
e281682b
SM		 4929 u8 op_mod[0x10];
4930
4931 u8 other_vport[0x1];
b4ff3a36 4932 u8 reserved_at_41[0xf];
e281682b
SM		 4933 u8 vport_number[0x10];
4934
b4ff3a36 4935 u8 reserved_at_60[0x18];
e281682b 4936 u8 admin_state[0x4];
b4ff3a36 4937 u8 reserved_at_7c[0x4];
e281682b
SM		 4938};
4939
4940struct mlx5_ifc_modify_tis_out_bits {
4941 u8 status[0x8];
b4ff3a36 4942 u8 reserved_at_8[0x18];
e281682b
SM		 4943
4944 u8 syndrome[0x20];
4945
b4ff3a36 4946 u8 reserved_at_40[0x40];
e281682b
SM		 4947};
4948
75850d0b 4949struct mlx5_ifc_modify_tis_bitmask_bits {
b4ff3a36 4950 u8 reserved_at_0[0x20];
75850d0b 4951
84df61eb
AH		 4952 u8 reserved_at_20[0x1d];
4953 u8 lag_tx_port_affinity[0x1];
4954 u8 strict_lag_tx_port_affinity[0x1];
75850d0b 4955 u8 prio[0x1];
4956};
4957
e281682b
SM		 4958struct mlx5_ifc_modify_tis_in_bits {
4959 u8 opcode[0x10];
b4ff3a36 4960 u8 reserved_at_10[0x10];
e281682b 4961
b4ff3a36 4962 u8 reserved_at_20[0x10];
e281682b
SM		 4963 u8 op_mod[0x10];
4964
b4ff3a36 4965 u8 reserved_at_40[0x8];
e281682b
SM		 4966 u8 tisn[0x18];
4967
b4ff3a36 4968 u8 reserved_at_60[0x20];
e281682b 4969
75850d0b 4970 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
e281682b 4971
b4ff3a36 4972 u8 reserved_at_c0[0x40];
e281682b
SM		 4973
4974 struct mlx5_ifc_tisc_bits ctx;
4975};
4976
d9eea403 4977struct mlx5_ifc_modify_tir_bitmask_bits {
b4ff3a36 4978 u8 reserved_at_0[0x20];
d9eea403 4979
b4ff3a36 4980 u8 reserved_at_20[0x1b];
66189961 4981 u8 self_lb_en[0x1];
bdfc028d
TT		 4982 u8 reserved_at_3c[0x1];
4983 u8 hash[0x1];
4984 u8 reserved_at_3e[0x1];
d9eea403
AS		 4985 u8 lro[0x1];
4986};
4987
e281682b
SM		 4988struct mlx5_ifc_modify_tir_out_bits {
4989 u8 status[0x8];
b4ff3a36 4990 u8 reserved_at_8[0x18];
e281682b
SM		 4991
4992 u8 syndrome[0x20];
4993
b4ff3a36 4994 u8 reserved_at_40[0x40];
e281682b
SM		 4995};
4996
4997struct mlx5_ifc_modify_tir_in_bits {
4998 u8 opcode[0x10];
b4ff3a36 4999 u8 reserved_at_10[0x10];
e281682b 5000
b4ff3a36 5001 u8 reserved_at_20[0x10];
e281682b
SM		 5002 u8 op_mod[0x10];
5003
b4ff3a36 5004 u8 reserved_at_40[0x8];
e281682b
SM		 5005 u8 tirn[0x18];
5006
b4ff3a36 5007 u8 reserved_at_60[0x20];
e281682b 5008
d9eea403 5009 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
e281682b 5010
b4ff3a36 5011 u8 reserved_at_c0[0x40];
e281682b
SM		 5012
5013 struct mlx5_ifc_tirc_bits ctx;
5014};
5015
5016struct mlx5_ifc_modify_sq_out_bits {
5017 u8 status[0x8];
b4ff3a36 5018 u8 reserved_at_8[0x18];
e281682b
SM		 5019
5020 u8 syndrome[0x20];
5021
b4ff3a36 5022 u8 reserved_at_40[0x40];
e281682b
SM		 5023};
5024
5025struct mlx5_ifc_modify_sq_in_bits {
5026 u8 opcode[0x10];
b4ff3a36 5027 u8 reserved_at_10[0x10];
e281682b 5028
b4ff3a36 5029 u8 reserved_at_20[0x10];
e281682b
SM		 5030 u8 op_mod[0x10];
5031
5032 u8 sq_state[0x4];
b4ff3a36 5033 u8 reserved_at_44[0x4];
e281682b
SM		 5034 u8 sqn[0x18];
5035
b4ff3a36 5036 u8 reserved_at_60[0x20];
e281682b
SM		 5037
5038 u8 modify_bitmask[0x40];
5039
b4ff3a36 5040 u8 reserved_at_c0[0x40];
e281682b
SM		 5041
5042 struct mlx5_ifc_sqc_bits ctx;
5043};
5044
813f8540
MHY		 5045struct mlx5_ifc_modify_scheduling_element_out_bits {
5046 u8 status[0x8];
5047 u8 reserved_at_8[0x18];
5048
5049 u8 syndrome[0x20];
5050
5051 u8 reserved_at_40[0x1c0];
5052};
5053
5054enum {
5055 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
5056 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
5057};
5058
5059struct mlx5_ifc_modify_scheduling_element_in_bits {
5060 u8 opcode[0x10];
5061 u8 reserved_at_10[0x10];
5062
5063 u8 reserved_at_20[0x10];
5064 u8 op_mod[0x10];
5065
5066 u8 scheduling_hierarchy[0x8];
5067 u8 reserved_at_48[0x18];
5068
5069 u8 scheduling_element_id[0x20];
5070
5071 u8 reserved_at_80[0x20];
5072
5073 u8 modify_bitmask[0x20];
5074
5075 u8 reserved_at_c0[0x40];
5076
5077 struct mlx5_ifc_scheduling_context_bits scheduling_context;
5078
5079 u8 reserved_at_300[0x100];
5080};
5081
e281682b
SM		 5082struct mlx5_ifc_modify_rqt_out_bits {
5083 u8 status[0x8];
b4ff3a36 5084 u8 reserved_at_8[0x18];
e281682b
SM		 5085
5086 u8 syndrome[0x20];
5087
b4ff3a36 5088 u8 reserved_at_40[0x40];
e281682b
SM		 5089};
5090
5c50368f 5091struct mlx5_ifc_rqt_bitmask_bits {
b4ff3a36 5092 u8 reserved_at_0[0x20];
5c50368f 5093
b4ff3a36 5094 u8 reserved_at_20[0x1f];
5c50368f
AS		 5095 u8 rqn_list[0x1];
5096};
5097
e281682b
SM		 5098struct mlx5_ifc_modify_rqt_in_bits {
5099 u8 opcode[0x10];
b4ff3a36 5100 u8 reserved_at_10[0x10];
e281682b 5101
b4ff3a36 5102 u8 reserved_at_20[0x10];
e281682b
SM		 5103 u8 op_mod[0x10];
5104
b4ff3a36 5105 u8 reserved_at_40[0x8];
e281682b
SM		 5106 u8 rqtn[0x18];
5107
b4ff3a36 5108 u8 reserved_at_60[0x20];
e281682b 5109
5c50368f 5110 struct mlx5_ifc_rqt_bitmask_bits bitmask;
e281682b 5111
b4ff3a36 5112 u8 reserved_at_c0[0x40];
e281682b
SM		 5113
5114 struct mlx5_ifc_rqtc_bits ctx;
5115};
5116
5117struct mlx5_ifc_modify_rq_out_bits {
5118 u8 status[0x8];
b4ff3a36 5119 u8 reserved_at_8[0x18];
e281682b
SM		 5120
5121 u8 syndrome[0x20];
5122
b4ff3a36 5123 u8 reserved_at_40[0x40];
e281682b
SM		 5124};
5125
83b502a1
AV		 5126enum {
5127 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
102722fc 5128 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS = 1ULL << 2,
23a6964e 5129 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID = 1ULL << 3,
83b502a1
AV		 5130};
5131
e281682b
SM		 5132struct mlx5_ifc_modify_rq_in_bits {
5133 u8 opcode[0x10];
b4ff3a36 5134 u8 reserved_at_10[0x10];
e281682b 5135
b4ff3a36 5136 u8 reserved_at_20[0x10];
e281682b
SM		 5137 u8 op_mod[0x10];
5138
5139 u8 rq_state[0x4];
b4ff3a36 5140 u8 reserved_at_44[0x4];
e281682b
SM		 5141 u8 rqn[0x18];
5142
b4ff3a36 5143 u8 reserved_at_60[0x20];
e281682b
SM		 5144
5145 u8 modify_bitmask[0x40];
5146
b4ff3a36 5147 u8 reserved_at_c0[0x40];
e281682b
SM		 5148
5149 struct mlx5_ifc_rqc_bits ctx;
5150};
5151
5152struct mlx5_ifc_modify_rmp_out_bits {
5153 u8 status[0x8];
b4ff3a36 5154 u8 reserved_at_8[0x18];
e281682b
SM		 5155
5156 u8 syndrome[0x20];
5157
b4ff3a36 5158 u8 reserved_at_40[0x40];
e281682b
SM		 5159};
5160
01949d01 5161struct mlx5_ifc_rmp_bitmask_bits {
b4ff3a36 5162 u8 reserved_at_0[0x20];
01949d01 5163
b4ff3a36 5164 u8 reserved_at_20[0x1f];
01949d01
HA		 5165 u8 lwm[0x1];
5166};
5167
e281682b
SM		 5168struct mlx5_ifc_modify_rmp_in_bits {
5169 u8 opcode[0x10];
b4ff3a36 5170 u8 reserved_at_10[0x10];
e281682b 5171
b4ff3a36 5172 u8 reserved_at_20[0x10];
e281682b
SM		 5173 u8 op_mod[0x10];
5174
5175 u8 rmp_state[0x4];
b4ff3a36 5176 u8 reserved_at_44[0x4];
e281682b
SM		 5177 u8 rmpn[0x18];
5178
b4ff3a36 5179 u8 reserved_at_60[0x20];
e281682b 5180
01949d01 5181 struct mlx5_ifc_rmp_bitmask_bits bitmask;
e281682b 5182
b4ff3a36 5183 u8 reserved_at_c0[0x40];
e281682b
SM		 5184
5185 struct mlx5_ifc_rmpc_bits ctx;
5186};
5187
5188struct mlx5_ifc_modify_nic_vport_context_out_bits {
5189 u8 status[0x8];
b4ff3a36 5190 u8 reserved_at_8[0x18];
e281682b
SM		 5191
5192 u8 syndrome[0x20];
5193
b4ff3a36 5194 u8 reserved_at_40[0x40];
e281682b
SM		 5195};
5196
5197struct mlx5_ifc_modify_nic_vport_field_select_bits {
23898c76
NO		 5198 u8 reserved_at_0[0x16];
5199 u8 node_guid[0x1];
5200 u8 port_guid[0x1];
9def7121 5201 u8 min_inline[0x1];
d82b7318
SM		 5202 u8 mtu[0x1];
5203 u8 change_event[0x1];
5204 u8 promisc[0x1];
e281682b
SM		 5205 u8 permanent_address[0x1];
5206 u8 addresses_list[0x1];
5207 u8 roce_en[0x1];
b4ff3a36 5208 u8 reserved_at_1f[0x1];
e281682b
SM		 5209};
5210
5211struct mlx5_ifc_modify_nic_vport_context_in_bits {
5212 u8 opcode[0x10];
b4ff3a36 5213 u8 reserved_at_10[0x10];
e281682b 5214
b4ff3a36 5215 u8 reserved_at_20[0x10];
e281682b
SM		 5216 u8 op_mod[0x10];
5217
5218 u8 other_vport[0x1];
b4ff3a36 5219 u8 reserved_at_41[0xf];
e281682b
SM		 5220 u8 vport_number[0x10];
5221
5222 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5223
b4ff3a36 5224 u8 reserved_at_80[0x780];
e281682b
SM		 5225
5226 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5227};
5228
5229struct mlx5_ifc_modify_hca_vport_context_out_bits {
5230 u8 status[0x8];
b4ff3a36 5231 u8 reserved_at_8[0x18];
e281682b
SM		 5232
5233 u8 syndrome[0x20];
5234
b4ff3a36 5235 u8 reserved_at_40[0x40];
e281682b
SM		 5236};
5237
5238struct mlx5_ifc_modify_hca_vport_context_in_bits {
5239 u8 opcode[0x10];
b4ff3a36 5240 u8 reserved_at_10[0x10];
e281682b 5241
b4ff3a36 5242 u8 reserved_at_20[0x10];
e281682b
SM		 5243 u8 op_mod[0x10];
5244
5245 u8 other_vport[0x1];
b4ff3a36 5246 u8 reserved_at_41[0xb];
707c4602 5247 u8 port_num[0x4];
e281682b
SM		 5248 u8 vport_number[0x10];
5249
b4ff3a36 5250 u8 reserved_at_60[0x20];
e281682b
SM		 5251
5252 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5253};
5254
5255struct mlx5_ifc_modify_cq_out_bits {
5256 u8 status[0x8];
b4ff3a36 5257 u8 reserved_at_8[0x18];
e281682b
SM		 5258
5259 u8 syndrome[0x20];
5260
b4ff3a36 5261 u8 reserved_at_40[0x40];
e281682b
SM		 5262};
5263
5264enum {
5265 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
5266 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
5267};
5268
5269struct mlx5_ifc_modify_cq_in_bits {
5270 u8 opcode[0x10];
b4ff3a36 5271 u8 reserved_at_10[0x10];
e281682b 5272
b4ff3a36 5273 u8 reserved_at_20[0x10];
e281682b
SM		 5274 u8 op_mod[0x10];
5275
b4ff3a36 5276 u8 reserved_at_40[0x8];
e281682b
SM		 5277 u8 cqn[0x18];
5278
5279 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5280
5281 struct mlx5_ifc_cqc_bits cq_context;
5282
b4ff3a36 5283 u8 reserved_at_280[0x600];
e281682b
SM		 5284
5285 u8 pas[0][0x40];
5286};
5287
5288struct mlx5_ifc_modify_cong_status_out_bits {
5289 u8 status[0x8];
b4ff3a36 5290 u8 reserved_at_8[0x18];
e281682b
SM		 5291
5292 u8 syndrome[0x20];
5293
b4ff3a36 5294 u8 reserved_at_40[0x40];
e281682b
SM		 5295};
5296
5297struct mlx5_ifc_modify_cong_status_in_bits {
5298 u8 opcode[0x10];
b4ff3a36 5299 u8 reserved_at_10[0x10];
e281682b 5300
b4ff3a36 5301 u8 reserved_at_20[0x10];
e281682b
SM		 5302 u8 op_mod[0x10];
5303
b4ff3a36 5304 u8 reserved_at_40[0x18];
e281682b
SM		 5305 u8 priority[0x4];
5306 u8 cong_protocol[0x4];
5307
5308 u8 enable[0x1];
5309 u8 tag_enable[0x1];
b4ff3a36 5310 u8 reserved_at_62[0x1e];
e281682b
SM		 5311};
5312
5313struct mlx5_ifc_modify_cong_params_out_bits {
5314 u8 status[0x8];
b4ff3a36 5315 u8 reserved_at_8[0x18];
e281682b
SM		 5316
5317 u8 syndrome[0x20];
5318
b4ff3a36 5319 u8 reserved_at_40[0x40];
e281682b
SM		 5320};
5321
5322struct mlx5_ifc_modify_cong_params_in_bits {
5323 u8 opcode[0x10];
b4ff3a36 5324 u8 reserved_at_10[0x10];
e281682b 5325
b4ff3a36 5326 u8 reserved_at_20[0x10];
e281682b
SM		 5327 u8 op_mod[0x10];
5328
b4ff3a36 5329 u8 reserved_at_40[0x1c];
e281682b
SM		 5330 u8 cong_protocol[0x4];
5331
5332 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5333
b4ff3a36 5334 u8 reserved_at_80[0x80];
e281682b
SM		 5335
5336 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5337};
5338
5339struct mlx5_ifc_manage_pages_out_bits {
5340 u8 status[0x8];
b4ff3a36 5341 u8 reserved_at_8[0x18];
e281682b
SM		 5342
5343 u8 syndrome[0x20];
5344
5345 u8 output_num_entries[0x20];
5346
b4ff3a36 5347 u8 reserved_at_60[0x20];
e281682b
SM		 5348
5349 u8 pas[0][0x40];
5350};
5351
5352enum {
5353 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
5354 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
5355 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
5356};
5357
5358struct mlx5_ifc_manage_pages_in_bits {
5359 u8 opcode[0x10];
b4ff3a36 5360 u8 reserved_at_10[0x10];
e281682b 5361
b4ff3a36 5362 u8 reserved_at_20[0x10];
e281682b
SM		 5363 u8 op_mod[0x10];
5364
b4ff3a36 5365 u8 reserved_at_40[0x10];
e281682b
SM		 5366 u8 function_id[0x10];
5367
5368 u8 input_num_entries[0x20];
5369
5370 u8 pas[0][0x40];
5371};
5372
5373struct mlx5_ifc_mad_ifc_out_bits {
5374 u8 status[0x8];
b4ff3a36 5375 u8 reserved_at_8[0x18];
e281682b
SM		 5376
5377 u8 syndrome[0x20];
5378
b4ff3a36 5379 u8 reserved_at_40[0x40];
e281682b
SM		 5380
5381 u8 response_mad_packet[256][0x8];
5382};
5383
5384struct mlx5_ifc_mad_ifc_in_bits {
5385 u8 opcode[0x10];
b4ff3a36 5386 u8 reserved_at_10[0x10];
e281682b 5387
b4ff3a36 5388 u8 reserved_at_20[0x10];
e281682b
SM		 5389 u8 op_mod[0x10];
5390
5391 u8 remote_lid[0x10];
b4ff3a36 5392 u8 reserved_at_50[0x8];
e281682b
SM		 5393 u8 port[0x8];
5394
b4ff3a36 5395 u8 reserved_at_60[0x20];
e281682b
SM		 5396
5397 u8 mad[256][0x8];
5398};
5399
5400struct mlx5_ifc_init_hca_out_bits {
5401 u8 status[0x8];
b4ff3a36 5402 u8 reserved_at_8[0x18];
e281682b
SM		 5403
5404 u8 syndrome[0x20];
5405
b4ff3a36 5406 u8 reserved_at_40[0x40];
e281682b
SM		 5407};
5408
5409struct mlx5_ifc_init_hca_in_bits {
5410 u8 opcode[0x10];
b4ff3a36 5411 u8 reserved_at_10[0x10];
e281682b 5412
b4ff3a36 5413 u8 reserved_at_20[0x10];
e281682b
SM		 5414 u8 op_mod[0x10];
5415
b4ff3a36 5416 u8 reserved_at_40[0x40];
e281682b
SM		 5417};
5418
5419struct mlx5_ifc_init2rtr_qp_out_bits {
5420 u8 status[0x8];
b4ff3a36 5421 u8 reserved_at_8[0x18];
e281682b
SM		 5422
5423 u8 syndrome[0x20];
5424
b4ff3a36 5425 u8 reserved_at_40[0x40];
e281682b
SM		 5426};
5427
5428struct mlx5_ifc_init2rtr_qp_in_bits {
5429 u8 opcode[0x10];
b4ff3a36 5430 u8 reserved_at_10[0x10];
e281682b 5431
b4ff3a36 5432 u8 reserved_at_20[0x10];
e281682b
SM		 5433 u8 op_mod[0x10];
5434
b4ff3a36 5435 u8 reserved_at_40[0x8];
e281682b
SM		 5436 u8 qpn[0x18];
5437
b4ff3a36 5438 u8 reserved_at_60[0x20];
e281682b
SM		 5439
5440 u8 opt_param_mask[0x20];
5441
b4ff3a36 5442 u8 reserved_at_a0[0x20];
e281682b
SM		 5443
5444 struct mlx5_ifc_qpc_bits qpc;
5445
b4ff3a36 5446 u8 reserved_at_800[0x80];
e281682b
SM		 5447};
5448
5449struct mlx5_ifc_init2init_qp_out_bits {
5450 u8 status[0x8];
b4ff3a36 5451 u8 reserved_at_8[0x18];
e281682b
SM		 5452
5453 u8 syndrome[0x20];
5454
b4ff3a36 5455 u8 reserved_at_40[0x40];
e281682b
SM		 5456};
5457
5458struct mlx5_ifc_init2init_qp_in_bits {
5459 u8 opcode[0x10];
b4ff3a36 5460 u8 reserved_at_10[0x10];
e281682b 5461
b4ff3a36 5462 u8 reserved_at_20[0x10];
e281682b
SM		 5463 u8 op_mod[0x10];
5464
b4ff3a36 5465 u8 reserved_at_40[0x8];
e281682b
SM		 5466 u8 qpn[0x18];
5467
b4ff3a36 5468 u8 reserved_at_60[0x20];
e281682b
SM		 5469
5470 u8 opt_param_mask[0x20];
5471
b4ff3a36 5472 u8 reserved_at_a0[0x20];
e281682b
SM		 5473
5474 struct mlx5_ifc_qpc_bits qpc;
5475
b4ff3a36 5476 u8 reserved_at_800[0x80];
e281682b
SM		 5477};
5478
5479struct mlx5_ifc_get_dropped_packet_log_out_bits {
5480 u8 status[0x8];
b4ff3a36 5481 u8 reserved_at_8[0x18];
e281682b
SM		 5482
5483 u8 syndrome[0x20];
5484
b4ff3a36 5485 u8 reserved_at_40[0x40];
e281682b
SM		 5486
5487 u8 packet_headers_log[128][0x8];
5488
5489 u8 packet_syndrome[64][0x8];
5490};
5491
5492struct mlx5_ifc_get_dropped_packet_log_in_bits {
5493 u8 opcode[0x10];
b4ff3a36 5494 u8 reserved_at_10[0x10];
e281682b 5495
b4ff3a36 5496 u8 reserved_at_20[0x10];
e281682b
SM		 5497 u8 op_mod[0x10];
5498
b4ff3a36 5499 u8 reserved_at_40[0x40];
e281682b
SM		 5500};
5501
5502struct mlx5_ifc_gen_eqe_in_bits {
5503 u8 opcode[0x10];
b4ff3a36 5504 u8 reserved_at_10[0x10];
e281682b 5505
b4ff3a36 5506 u8 reserved_at_20[0x10];
e281682b
SM		 5507 u8 op_mod[0x10];
5508
b4ff3a36 5509 u8 reserved_at_40[0x18];
e281682b
SM		 5510 u8 eq_number[0x8];
5511
b4ff3a36 5512 u8 reserved_at_60[0x20];
e281682b
SM		 5513
5514 u8 eqe[64][0x8];
5515};
5516
5517struct mlx5_ifc_gen_eq_out_bits {
5518 u8 status[0x8];
b4ff3a36 5519 u8 reserved_at_8[0x18];
e281682b
SM		 5520
5521 u8 syndrome[0x20];
5522
b4ff3a36 5523 u8 reserved_at_40[0x40];
e281682b
SM		 5524};
5525
5526struct mlx5_ifc_enable_hca_out_bits {
5527 u8 status[0x8];
b4ff3a36 5528 u8 reserved_at_8[0x18];
e281682b
SM		 5529
5530 u8 syndrome[0x20];
5531
b4ff3a36 5532 u8 reserved_at_40[0x20];
e281682b
SM		 5533};
5534
5535struct mlx5_ifc_enable_hca_in_bits {
5536 u8 opcode[0x10];
b4ff3a36 5537 u8 reserved_at_10[0x10];
e281682b 5538
b4ff3a36 5539 u8 reserved_at_20[0x10];
e281682b
SM		 5540 u8 op_mod[0x10];
5541
b4ff3a36 5542 u8 reserved_at_40[0x10];
e281682b
SM		 5543 u8 function_id[0x10];
5544
b4ff3a36 5545 u8 reserved_at_60[0x20];
e281682b
SM		 5546};
5547
5548struct mlx5_ifc_drain_dct_out_bits {
5549 u8 status[0x8];
b4ff3a36 5550 u8 reserved_at_8[0x18];
e281682b
SM		 5551
5552 u8 syndrome[0x20];
5553
b4ff3a36 5554 u8 reserved_at_40[0x40];
e281682b
SM		 5555};
5556
5557struct mlx5_ifc_drain_dct_in_bits {
5558 u8 opcode[0x10];
b4ff3a36 5559 u8 reserved_at_10[0x10];
e281682b 5560
b4ff3a36 5561 u8 reserved_at_20[0x10];
e281682b
SM		 5562 u8 op_mod[0x10];
5563
b4ff3a36 5564 u8 reserved_at_40[0x8];
e281682b
SM		 5565 u8 dctn[0x18];
5566
b4ff3a36 5567 u8 reserved_at_60[0x20];
e281682b
SM		 5568};
5569
5570struct mlx5_ifc_disable_hca_out_bits {
5571 u8 status[0x8];
b4ff3a36 5572 u8 reserved_at_8[0x18];
e281682b
SM		 5573
5574 u8 syndrome[0x20];
5575
b4ff3a36 5576 u8 reserved_at_40[0x20];
e281682b
SM		 5577};
5578
5579struct mlx5_ifc_disable_hca_in_bits {
5580 u8 opcode[0x10];
b4ff3a36 5581 u8 reserved_at_10[0x10];
e281682b 5582
b4ff3a36 5583 u8 reserved_at_20[0x10];
e281682b
SM		 5584 u8 op_mod[0x10];
5585
b4ff3a36 5586 u8 reserved_at_40[0x10];
e281682b
SM		 5587 u8 function_id[0x10];
5588
b4ff3a36 5589 u8 reserved_at_60[0x20];
e281682b
SM		 5590};
5591
5592struct mlx5_ifc_detach_from_mcg_out_bits {
5593 u8 status[0x8];
b4ff3a36 5594 u8 reserved_at_8[0x18];
e281682b
SM		 5595
5596 u8 syndrome[0x20];
5597
b4ff3a36 5598 u8 reserved_at_40[0x40];
e281682b
SM		 5599};
5600
5601struct mlx5_ifc_detach_from_mcg_in_bits {
5602 u8 opcode[0x10];
b4ff3a36 5603 u8 reserved_at_10[0x10];
e281682b 5604
b4ff3a36 5605 u8 reserved_at_20[0x10];
e281682b
SM		 5606 u8 op_mod[0x10];
5607
b4ff3a36 5608 u8 reserved_at_40[0x8];
e281682b
SM		 5609 u8 qpn[0x18];
5610
b4ff3a36 5611 u8 reserved_at_60[0x20];
e281682b
SM		 5612
5613 u8 multicast_gid[16][0x8];
5614};
5615
7486216b
SM		 5616struct mlx5_ifc_destroy_xrq_out_bits {
5617 u8 status[0x8];
5618 u8 reserved_at_8[0x18];
5619
5620 u8 syndrome[0x20];
5621
5622 u8 reserved_at_40[0x40];
5623};
5624
5625struct mlx5_ifc_destroy_xrq_in_bits {
5626 u8 opcode[0x10];
5627 u8 reserved_at_10[0x10];
5628
5629 u8 reserved_at_20[0x10];
5630 u8 op_mod[0x10];
5631
5632 u8 reserved_at_40[0x8];
5633 u8 xrqn[0x18];
5634
5635 u8 reserved_at_60[0x20];
5636};
5637
e281682b
SM		 5638struct mlx5_ifc_destroy_xrc_srq_out_bits {
5639 u8 status[0x8];
b4ff3a36 5640 u8 reserved_at_8[0x18];
e281682b
SM		 5641
5642 u8 syndrome[0x20];
5643
b4ff3a36 5644 u8 reserved_at_40[0x40];
e281682b
SM		 5645};
5646
5647struct mlx5_ifc_destroy_xrc_srq_in_bits {
5648 u8 opcode[0x10];
b4ff3a36 5649 u8 reserved_at_10[0x10];
e281682b 5650
b4ff3a36 5651 u8 reserved_at_20[0x10];
e281682b
SM		 5652 u8 op_mod[0x10];
5653
b4ff3a36 5654 u8 reserved_at_40[0x8];
e281682b
SM		 5655 u8 xrc_srqn[0x18];
5656
b4ff3a36 5657 u8 reserved_at_60[0x20];
e281682b
SM		 5658};
5659
5660struct mlx5_ifc_destroy_tis_out_bits {
5661 u8 status[0x8];
b4ff3a36 5662 u8 reserved_at_8[0x18];
e281682b
SM		 5663
5664 u8 syndrome[0x20];
5665
b4ff3a36 5666 u8 reserved_at_40[0x40];
e281682b
SM		 5667};
5668
5669struct mlx5_ifc_destroy_tis_in_bits {
5670 u8 opcode[0x10];
b4ff3a36 5671 u8 reserved_at_10[0x10];
e281682b 5672
b4ff3a36 5673 u8 reserved_at_20[0x10];
e281682b
SM		 5674 u8 op_mod[0x10];
5675
b4ff3a36 5676 u8 reserved_at_40[0x8];
e281682b
SM		 5677 u8 tisn[0x18];
5678
b4ff3a36 5679 u8 reserved_at_60[0x20];
e281682b
SM		 5680};
5681
5682struct mlx5_ifc_destroy_tir_out_bits {
5683 u8 status[0x8];
b4ff3a36 5684 u8 reserved_at_8[0x18];
e281682b
SM		 5685
5686 u8 syndrome[0x20];
5687
b4ff3a36 5688 u8 reserved_at_40[0x40];
e281682b
SM		 5689};
5690
5691struct mlx5_ifc_destroy_tir_in_bits {
5692 u8 opcode[0x10];
b4ff3a36 5693 u8 reserved_at_10[0x10];
e281682b 5694
b4ff3a36 5695 u8 reserved_at_20[0x10];
e281682b
SM		 5696 u8 op_mod[0x10];
5697
b4ff3a36 5698 u8 reserved_at_40[0x8];
e281682b
SM		 5699 u8 tirn[0x18];
5700
b4ff3a36 5701 u8 reserved_at_60[0x20];
e281682b
SM		 5702};
5703
5704struct mlx5_ifc_destroy_srq_out_bits {
5705 u8 status[0x8];
b4ff3a36 5706 u8 reserved_at_8[0x18];
e281682b
SM		 5707
5708 u8 syndrome[0x20];
5709
b4ff3a36 5710 u8 reserved_at_40[0x40];
e281682b
SM		 5711};
5712
5713struct mlx5_ifc_destroy_srq_in_bits {
5714 u8 opcode[0x10];
b4ff3a36 5715 u8 reserved_at_10[0x10];
e281682b 5716
b4ff3a36 5717 u8 reserved_at_20[0x10];
e281682b
SM		 5718 u8 op_mod[0x10];
5719
b4ff3a36 5720 u8 reserved_at_40[0x8];
e281682b
SM		 5721 u8 srqn[0x18];
5722
b4ff3a36 5723 u8 reserved_at_60[0x20];
e281682b
SM		 5724};
5725
5726struct mlx5_ifc_destroy_sq_out_bits {
5727 u8 status[0x8];
b4ff3a36 5728 u8 reserved_at_8[0x18];
e281682b
SM		 5729
5730 u8 syndrome[0x20];
5731
b4ff3a36 5732 u8 reserved_at_40[0x40];
e281682b
SM		 5733};
5734
5735struct mlx5_ifc_destroy_sq_in_bits {
5736 u8 opcode[0x10];
b4ff3a36 5737 u8 reserved_at_10[0x10];
e281682b 5738
b4ff3a36 5739 u8 reserved_at_20[0x10];
e281682b
SM		 5740 u8 op_mod[0x10];
5741
b4ff3a36 5742 u8 reserved_at_40[0x8];
e281682b
SM		 5743 u8 sqn[0x18];
5744
b4ff3a36 5745 u8 reserved_at_60[0x20];
e281682b
SM		 5746};
5747
813f8540
MHY		 5748struct mlx5_ifc_destroy_scheduling_element_out_bits {
5749 u8 status[0x8];
5750 u8 reserved_at_8[0x18];
5751
5752 u8 syndrome[0x20];
5753
5754 u8 reserved_at_40[0x1c0];
5755};
5756
5757struct mlx5_ifc_destroy_scheduling_element_in_bits {
5758 u8 opcode[0x10];
5759 u8 reserved_at_10[0x10];
5760
5761 u8 reserved_at_20[0x10];
5762 u8 op_mod[0x10];
5763
5764 u8 scheduling_hierarchy[0x8];
5765 u8 reserved_at_48[0x18];
5766
5767 u8 scheduling_element_id[0x20];
5768
5769 u8 reserved_at_80[0x180];
5770};
5771
e281682b
SM		 5772struct mlx5_ifc_destroy_rqt_out_bits {
5773 u8 status[0x8];
b4ff3a36 5774 u8 reserved_at_8[0x18];
e281682b
SM		 5775
5776 u8 syndrome[0x20];
5777
b4ff3a36 5778 u8 reserved_at_40[0x40];
e281682b
SM		 5779};
5780
5781struct mlx5_ifc_destroy_rqt_in_bits {
5782 u8 opcode[0x10];
b4ff3a36 5783 u8 reserved_at_10[0x10];
e281682b 5784
b4ff3a36 5785 u8 reserved_at_20[0x10];
e281682b
SM		 5786 u8 op_mod[0x10];
5787
b4ff3a36 5788 u8 reserved_at_40[0x8];
e281682b
SM		 5789 u8 rqtn[0x18];
5790
b4ff3a36 5791 u8 reserved_at_60[0x20];
e281682b
SM		 5792};
5793
5794struct mlx5_ifc_destroy_rq_out_bits {
5795 u8 status[0x8];
b4ff3a36 5796 u8 reserved_at_8[0x18];
e281682b
SM		 5797
5798 u8 syndrome[0x20];
5799
b4ff3a36 5800 u8 reserved_at_40[0x40];
e281682b
SM		 5801};
5802
5803struct mlx5_ifc_destroy_rq_in_bits {
5804 u8 opcode[0x10];
b4ff3a36 5805 u8 reserved_at_10[0x10];
e281682b 5806
b4ff3a36 5807 u8 reserved_at_20[0x10];
e281682b
SM		 5808 u8 op_mod[0x10];
5809
b4ff3a36 5810 u8 reserved_at_40[0x8];
e281682b
SM		 5811 u8 rqn[0x18];
5812
b4ff3a36 5813 u8 reserved_at_60[0x20];
e281682b
SM		 5814};
5815
5816struct mlx5_ifc_destroy_rmp_out_bits {
5817 u8 status[0x8];
b4ff3a36 5818 u8 reserved_at_8[0x18];
e281682b
SM		 5819
5820 u8 syndrome[0x20];
5821
b4ff3a36 5822 u8 reserved_at_40[0x40];
e281682b
SM		 5823};
5824
5825struct mlx5_ifc_destroy_rmp_in_bits {
5826 u8 opcode[0x10];
b4ff3a36 5827 u8 reserved_at_10[0x10];
e281682b 5828
b4ff3a36 5829 u8 reserved_at_20[0x10];
e281682b
SM		 5830 u8 op_mod[0x10];
5831
b4ff3a36 5832 u8 reserved_at_40[0x8];
e281682b
SM		 5833 u8 rmpn[0x18];
5834
b4ff3a36 5835 u8 reserved_at_60[0x20];
e281682b
SM		 5836};
5837
5838struct mlx5_ifc_destroy_qp_out_bits {
5839 u8 status[0x8];
b4ff3a36 5840 u8 reserved_at_8[0x18];
e281682b
SM		 5841
5842 u8 syndrome[0x20];
5843
b4ff3a36 5844 u8 reserved_at_40[0x40];
e281682b
SM		 5845};
5846
5847struct mlx5_ifc_destroy_qp_in_bits {
5848 u8 opcode[0x10];
b4ff3a36 5849 u8 reserved_at_10[0x10];
e281682b 5850
b4ff3a36 5851 u8 reserved_at_20[0x10];
e281682b
SM		 5852 u8 op_mod[0x10];
5853
b4ff3a36 5854 u8 reserved_at_40[0x8];
e281682b
SM		 5855 u8 qpn[0x18];
5856
b4ff3a36 5857 u8 reserved_at_60[0x20];
e281682b
SM		 5858};
5859
5860struct mlx5_ifc_destroy_psv_out_bits {
5861 u8 status[0x8];
b4ff3a36 5862 u8 reserved_at_8[0x18];
e281682b
SM		 5863
5864 u8 syndrome[0x20];
5865
b4ff3a36 5866 u8 reserved_at_40[0x40];
e281682b
SM		 5867};
5868
5869struct mlx5_ifc_destroy_psv_in_bits {
5870 u8 opcode[0x10];
b4ff3a36 5871 u8 reserved_at_10[0x10];
e281682b 5872
b4ff3a36 5873 u8 reserved_at_20[0x10];
e281682b
SM		 5874 u8 op_mod[0x10];
5875
b4ff3a36 5876 u8 reserved_at_40[0x8];
e281682b
SM		 5877 u8 psvn[0x18];
5878
b4ff3a36 5879 u8 reserved_at_60[0x20];
e281682b
SM		 5880};
5881
5882struct mlx5_ifc_destroy_mkey_out_bits {
5883 u8 status[0x8];
b4ff3a36 5884 u8 reserved_at_8[0x18];
e281682b
SM		 5885
5886 u8 syndrome[0x20];
5887
b4ff3a36 5888 u8 reserved_at_40[0x40];
e281682b
SM		 5889};
5890
5891struct mlx5_ifc_destroy_mkey_in_bits {
5892 u8 opcode[0x10];
b4ff3a36 5893 u8 reserved_at_10[0x10];
e281682b 5894
b4ff3a36 5895 u8 reserved_at_20[0x10];
e281682b
SM		 5896 u8 op_mod[0x10];
5897
b4ff3a36 5898 u8 reserved_at_40[0x8];
e281682b
SM		 5899 u8 mkey_index[0x18];
5900
b4ff3a36 5901 u8 reserved_at_60[0x20];
e281682b
SM		 5902};
5903
5904struct mlx5_ifc_destroy_flow_table_out_bits {
5905 u8 status[0x8];
b4ff3a36 5906 u8 reserved_at_8[0x18];
e281682b
SM		 5907
5908 u8 syndrome[0x20];
5909
b4ff3a36 5910 u8 reserved_at_40[0x40];
e281682b
SM		 5911};
5912
5913struct mlx5_ifc_destroy_flow_table_in_bits {
5914 u8 opcode[0x10];
b4ff3a36 5915 u8 reserved_at_10[0x10];
e281682b 5916
b4ff3a36 5917 u8 reserved_at_20[0x10];
e281682b
SM		 5918 u8 op_mod[0x10];
5919
7d5e1423
SM		 5920 u8 other_vport[0x1];
5921 u8 reserved_at_41[0xf];
5922 u8 vport_number[0x10];
5923
5924 u8 reserved_at_60[0x20];
e281682b
SM		 5925
5926 u8 table_type[0x8];
b4ff3a36 5927 u8 reserved_at_88[0x18];
e281682b 5928
b4ff3a36 5929 u8 reserved_at_a0[0x8];
e281682b
SM		 5930 u8 table_id[0x18];
5931
b4ff3a36 5932 u8 reserved_at_c0[0x140];
e281682b
SM		 5933};
5934
5935struct mlx5_ifc_destroy_flow_group_out_bits {
5936 u8 status[0x8];
b4ff3a36 5937 u8 reserved_at_8[0x18];
e281682b
SM		 5938
5939 u8 syndrome[0x20];
5940
b4ff3a36 5941 u8 reserved_at_40[0x40];
e281682b
SM		 5942};
5943
5944struct mlx5_ifc_destroy_flow_group_in_bits {
5945 u8 opcode[0x10];
b4ff3a36 5946 u8 reserved_at_10[0x10];
e281682b 5947
b4ff3a36 5948 u8 reserved_at_20[0x10];
e281682b
SM		 5949 u8 op_mod[0x10];
5950
7d5e1423
SM		 5951 u8 other_vport[0x1];
5952 u8 reserved_at_41[0xf];
5953 u8 vport_number[0x10];
5954
5955 u8 reserved_at_60[0x20];
e281682b
SM		 5956
5957 u8 table_type[0x8];
b4ff3a36 5958 u8 reserved_at_88[0x18];
e281682b 5959
b4ff3a36 5960 u8 reserved_at_a0[0x8];
e281682b
SM		 5961 u8 table_id[0x18];
5962
5963 u8 group_id[0x20];
5964
b4ff3a36 5965 u8 reserved_at_e0[0x120];
e281682b
SM		 5966};
5967
5968struct mlx5_ifc_destroy_eq_out_bits {
5969 u8 status[0x8];
b4ff3a36 5970 u8 reserved_at_8[0x18];
e281682b
SM		 5971
5972 u8 syndrome[0x20];
5973
b4ff3a36 5974 u8 reserved_at_40[0x40];
e281682b
SM		 5975};
5976
5977struct mlx5_ifc_destroy_eq_in_bits {
5978 u8 opcode[0x10];
b4ff3a36 5979 u8 reserved_at_10[0x10];
e281682b 5980
b4ff3a36 5981 u8 reserved_at_20[0x10];
e281682b
SM		 5982 u8 op_mod[0x10];
5983
b4ff3a36 5984 u8 reserved_at_40[0x18];
e281682b
SM		 5985 u8 eq_number[0x8];
5986
b4ff3a36 5987 u8 reserved_at_60[0x20];
e281682b
SM		 5988};
5989
5990struct mlx5_ifc_destroy_dct_out_bits {
5991 u8 status[0x8];
b4ff3a36 5992 u8 reserved_at_8[0x18];
e281682b
SM		 5993
5994 u8 syndrome[0x20];
5995
b4ff3a36 5996 u8 reserved_at_40[0x40];
e281682b
SM		 5997};
5998
5999struct mlx5_ifc_destroy_dct_in_bits {
6000 u8 opcode[0x10];
b4ff3a36 6001 u8 reserved_at_10[0x10];
e281682b 6002
b4ff3a36 6003 u8 reserved_at_20[0x10];
e281682b
SM		 6004 u8 op_mod[0x10];
6005
b4ff3a36 6006 u8 reserved_at_40[0x8];
e281682b
SM		 6007 u8 dctn[0x18];
6008
b4ff3a36 6009 u8 reserved_at_60[0x20];
e281682b
SM		 6010};
6011
6012struct mlx5_ifc_destroy_cq_out_bits {
6013 u8 status[0x8];
b4ff3a36 6014 u8 reserved_at_8[0x18];
e281682b
SM		 6015
6016 u8 syndrome[0x20];
6017
b4ff3a36 6018 u8 reserved_at_40[0x40];
e281682b
SM		 6019};
6020
6021struct mlx5_ifc_destroy_cq_in_bits {
6022 u8 opcode[0x10];
b4ff3a36 6023 u8 reserved_at_10[0x10];
e281682b 6024
b4ff3a36 6025 u8 reserved_at_20[0x10];
e281682b
SM		 6026 u8 op_mod[0x10];
6027
b4ff3a36 6028 u8 reserved_at_40[0x8];
e281682b
SM		 6029 u8 cqn[0x18];
6030
b4ff3a36 6031 u8 reserved_at_60[0x20];
e281682b
SM		 6032};
6033
6034struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
6035 u8 status[0x8];
b4ff3a36 6036 u8 reserved_at_8[0x18];
e281682b
SM		 6037
6038 u8 syndrome[0x20];
6039
b4ff3a36 6040 u8 reserved_at_40[0x40];
e281682b
SM		 6041};
6042
6043struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
6044 u8 opcode[0x10];
b4ff3a36 6045 u8 reserved_at_10[0x10];
e281682b 6046
b4ff3a36 6047 u8 reserved_at_20[0x10];
e281682b
SM		 6048 u8 op_mod[0x10];
6049
b4ff3a36 6050 u8 reserved_at_40[0x20];
e281682b 6051
b4ff3a36 6052 u8 reserved_at_60[0x10];
e281682b
SM		 6053 u8 vxlan_udp_port[0x10];
6054};
6055
6056struct mlx5_ifc_delete_l2_table_entry_out_bits {
6057 u8 status[0x8];
b4ff3a36 6058 u8 reserved_at_8[0x18];
e281682b
SM		 6059
6060 u8 syndrome[0x20];
6061
b4ff3a36 6062 u8 reserved_at_40[0x40];
e281682b
SM		 6063};
6064
6065struct mlx5_ifc_delete_l2_table_entry_in_bits {
6066 u8 opcode[0x10];
b4ff3a36 6067 u8 reserved_at_10[0x10];
e281682b 6068
b4ff3a36 6069 u8 reserved_at_20[0x10];
e281682b
SM		 6070 u8 op_mod[0x10];
6071
b4ff3a36 6072 u8 reserved_at_40[0x60];
e281682b 6073
b4ff3a36 6074 u8 reserved_at_a0[0x8];
e281682b
SM		 6075 u8 table_index[0x18];
6076
b4ff3a36 6077 u8 reserved_at_c0[0x140];
e281682b
SM		 6078};
6079
6080struct mlx5_ifc_delete_fte_out_bits {
6081 u8 status[0x8];
b4ff3a36 6082 u8 reserved_at_8[0x18];
e281682b
SM		 6083
6084 u8 syndrome[0x20];
6085
b4ff3a36 6086 u8 reserved_at_40[0x40];
e281682b
SM		 6087};
6088
6089struct mlx5_ifc_delete_fte_in_bits {
6090 u8 opcode[0x10];
b4ff3a36 6091 u8 reserved_at_10[0x10];
e281682b 6092
b4ff3a36 6093 u8 reserved_at_20[0x10];
e281682b
SM		 6094 u8 op_mod[0x10];
6095
7d5e1423
SM		 6096 u8 other_vport[0x1];
6097 u8 reserved_at_41[0xf];
6098 u8 vport_number[0x10];
6099
6100 u8 reserved_at_60[0x20];
e281682b
SM		 6101
6102 u8 table_type[0x8];
b4ff3a36 6103 u8 reserved_at_88[0x18];
e281682b 6104
b4ff3a36 6105 u8 reserved_at_a0[0x8];
e281682b
SM		 6106 u8 table_id[0x18];
6107
b4ff3a36 6108 u8 reserved_at_c0[0x40];
e281682b
SM		 6109
6110 u8 flow_index[0x20];
6111
b4ff3a36 6112 u8 reserved_at_120[0xe0];
e281682b
SM		 6113};
6114
6115struct mlx5_ifc_dealloc_xrcd_out_bits {
6116 u8 status[0x8];
b4ff3a36 6117 u8 reserved_at_8[0x18];
e281682b
SM		 6118
6119 u8 syndrome[0x20];
6120
b4ff3a36 6121 u8 reserved_at_40[0x40];
e281682b
SM		 6122};
6123
6124struct mlx5_ifc_dealloc_xrcd_in_bits {
6125 u8 opcode[0x10];
b4ff3a36 6126 u8 reserved_at_10[0x10];
e281682b 6127
b4ff3a36 6128 u8 reserved_at_20[0x10];
e281682b
SM		 6129 u8 op_mod[0x10];
6130
b4ff3a36 6131 u8 reserved_at_40[0x8];
e281682b
SM		 6132 u8 xrcd[0x18];
6133
b4ff3a36 6134 u8 reserved_at_60[0x20];
e281682b
SM		 6135};
6136
6137struct mlx5_ifc_dealloc_uar_out_bits {
6138 u8 status[0x8];
b4ff3a36 6139 u8 reserved_at_8[0x18];
e281682b
SM		 6140
6141 u8 syndrome[0x20];
6142
b4ff3a36 6143 u8 reserved_at_40[0x40];
e281682b
SM		 6144};
6145
6146struct mlx5_ifc_dealloc_uar_in_bits {
6147 u8 opcode[0x10];
b4ff3a36 6148 u8 reserved_at_10[0x10];
e281682b 6149
b4ff3a36 6150 u8 reserved_at_20[0x10];
e281682b
SM		 6151 u8 op_mod[0x10];
6152
b4ff3a36 6153 u8 reserved_at_40[0x8];
e281682b
SM		 6154 u8 uar[0x18];
6155
b4ff3a36 6156 u8 reserved_at_60[0x20];
e281682b
SM		 6157};
6158
6159struct mlx5_ifc_dealloc_transport_domain_out_bits {
6160 u8 status[0x8];
b4ff3a36 6161 u8 reserved_at_8[0x18];
e281682b
SM		 6162
6163 u8 syndrome[0x20];
6164
b4ff3a36 6165 u8 reserved_at_40[0x40];
e281682b
SM		 6166};
6167
6168struct mlx5_ifc_dealloc_transport_domain_in_bits {
6169 u8 opcode[0x10];
b4ff3a36 6170 u8 reserved_at_10[0x10];
e281682b 6171
b4ff3a36 6172 u8 reserved_at_20[0x10];
e281682b
SM		 6173 u8 op_mod[0x10];
6174
b4ff3a36 6175 u8 reserved_at_40[0x8];
e281682b
SM		 6176 u8 transport_domain[0x18];
6177
b4ff3a36 6178 u8 reserved_at_60[0x20];
e281682b
SM		 6179};
6180
6181struct mlx5_ifc_dealloc_q_counter_out_bits {
6182 u8 status[0x8];
b4ff3a36 6183 u8 reserved_at_8[0x18];
e281682b
SM		 6184
6185 u8 syndrome[0x20];
6186
b4ff3a36 6187 u8 reserved_at_40[0x40];
e281682b
SM		 6188};
6189
6190struct mlx5_ifc_dealloc_q_counter_in_bits {
6191 u8 opcode[0x10];
b4ff3a36 6192 u8 reserved_at_10[0x10];
e281682b 6193
b4ff3a36 6194 u8 reserved_at_20[0x10];
e281682b
SM		 6195 u8 op_mod[0x10];
6196
b4ff3a36 6197 u8 reserved_at_40[0x18];
e281682b
SM		 6198 u8 counter_set_id[0x8];
6199
b4ff3a36 6200 u8 reserved_at_60[0x20];
e281682b
SM		 6201};
6202
6203struct mlx5_ifc_dealloc_pd_out_bits {
6204 u8 status[0x8];
b4ff3a36 6205 u8 reserved_at_8[0x18];
e281682b
SM		 6206
6207 u8 syndrome[0x20];
6208
b4ff3a36 6209 u8 reserved_at_40[0x40];
e281682b
SM		 6210};
6211
6212struct mlx5_ifc_dealloc_pd_in_bits {
6213 u8 opcode[0x10];
b4ff3a36 6214 u8 reserved_at_10[0x10];
e281682b 6215
b4ff3a36 6216 u8 reserved_at_20[0x10];
e281682b
SM		 6217 u8 op_mod[0x10];
6218
b4ff3a36 6219 u8 reserved_at_40[0x8];
e281682b
SM		 6220 u8 pd[0x18];
6221
b4ff3a36 6222 u8 reserved_at_60[0x20];
e281682b
SM		 6223};
6224
9dc0b289
AV		 6225struct mlx5_ifc_dealloc_flow_counter_out_bits {
6226 u8 status[0x8];
6227 u8 reserved_at_8[0x18];
6228
6229 u8 syndrome[0x20];
6230
6231 u8 reserved_at_40[0x40];
6232};
6233
6234struct mlx5_ifc_dealloc_flow_counter_in_bits {
6235 u8 opcode[0x10];
6236 u8 reserved_at_10[0x10];
6237
6238 u8 reserved_at_20[0x10];
6239 u8 op_mod[0x10];
6240
6241 u8 reserved_at_40[0x10];
6242 u8 flow_counter_id[0x10];
6243
6244 u8 reserved_at_60[0x20];
6245};
6246
7486216b
SM		 6247struct mlx5_ifc_create_xrq_out_bits {
6248 u8 status[0x8];
6249 u8 reserved_at_8[0x18];
6250
6251 u8 syndrome[0x20];
6252
6253 u8 reserved_at_40[0x8];
6254 u8 xrqn[0x18];
6255
6256 u8 reserved_at_60[0x20];
6257};
6258
6259struct mlx5_ifc_create_xrq_in_bits {
6260 u8 opcode[0x10];
6261 u8 reserved_at_10[0x10];
6262
6263 u8 reserved_at_20[0x10];
6264 u8 op_mod[0x10];
6265
6266 u8 reserved_at_40[0x40];
6267
6268 struct mlx5_ifc_xrqc_bits xrq_context;
6269};
6270
e281682b
SM		 6271struct mlx5_ifc_create_xrc_srq_out_bits {
6272 u8 status[0x8];
b4ff3a36 6273 u8 reserved_at_8[0x18];
e281682b
SM		 6274
6275 u8 syndrome[0x20];
6276
b4ff3a36 6277 u8 reserved_at_40[0x8];
e281682b
SM		 6278 u8 xrc_srqn[0x18];
6279
b4ff3a36 6280 u8 reserved_at_60[0x20];
e281682b
SM		 6281};
6282
6283struct mlx5_ifc_create_xrc_srq_in_bits {
6284 u8 opcode[0x10];
b4ff3a36 6285 u8 reserved_at_10[0x10];
e281682b 6286
b4ff3a36 6287 u8 reserved_at_20[0x10];
e281682b
SM		 6288 u8 op_mod[0x10];
6289
b4ff3a36 6290 u8 reserved_at_40[0x40];
e281682b
SM		 6291
6292 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6293
b4ff3a36 6294 u8 reserved_at_280[0x600];
e281682b
SM		 6295
6296 u8 pas[0][0x40];
6297};
6298
6299struct mlx5_ifc_create_tis_out_bits {
6300 u8 status[0x8];
b4ff3a36 6301 u8 reserved_at_8[0x18];
e281682b
SM		 6302
6303 u8 syndrome[0x20];
6304
b4ff3a36 6305 u8 reserved_at_40[0x8];
e281682b
SM		 6306 u8 tisn[0x18];
6307
b4ff3a36 6308 u8 reserved_at_60[0x20];
e281682b
SM		 6309};
6310
6311struct mlx5_ifc_create_tis_in_bits {
6312 u8 opcode[0x10];
b4ff3a36 6313 u8 reserved_at_10[0x10];
e281682b 6314
b4ff3a36 6315 u8 reserved_at_20[0x10];
e281682b
SM		 6316 u8 op_mod[0x10];
6317
b4ff3a36 6318 u8 reserved_at_40[0xc0];
e281682b
SM		 6319
6320 struct mlx5_ifc_tisc_bits ctx;
6321};
6322
6323struct mlx5_ifc_create_tir_out_bits {
6324 u8 status[0x8];
b4ff3a36 6325 u8 reserved_at_8[0x18];
e281682b
SM		 6326
6327 u8 syndrome[0x20];
6328
b4ff3a36 6329 u8 reserved_at_40[0x8];
e281682b
SM		 6330 u8 tirn[0x18];
6331
b4ff3a36 6332 u8 reserved_at_60[0x20];
e281682b
SM		 6333};
6334
6335struct mlx5_ifc_create_tir_in_bits {
6336 u8 opcode[0x10];
b4ff3a36 6337 u8 reserved_at_10[0x10];
e281682b 6338
b4ff3a36 6339 u8 reserved_at_20[0x10];
e281682b
SM		 6340 u8 op_mod[0x10];
6341
b4ff3a36 6342 u8 reserved_at_40[0xc0];
e281682b
SM		 6343
6344 struct mlx5_ifc_tirc_bits ctx;
6345};
6346
6347struct mlx5_ifc_create_srq_out_bits {
6348 u8 status[0x8];
b4ff3a36 6349 u8 reserved_at_8[0x18];
e281682b
SM		 6350
6351 u8 syndrome[0x20];
6352
b4ff3a36 6353 u8 reserved_at_40[0x8];
e281682b
SM		 6354 u8 srqn[0x18];
6355
b4ff3a36 6356 u8 reserved_at_60[0x20];
e281682b
SM		 6357};
6358
6359struct mlx5_ifc_create_srq_in_bits {
6360 u8 opcode[0x10];
b4ff3a36 6361 u8 reserved_at_10[0x10];
e281682b 6362
b4ff3a36 6363 u8 reserved_at_20[0x10];
e281682b
SM		 6364 u8 op_mod[0x10];
6365
b4ff3a36 6366 u8 reserved_at_40[0x40];
e281682b
SM		 6367
6368 struct mlx5_ifc_srqc_bits srq_context_entry;
6369
b4ff3a36 6370 u8 reserved_at_280[0x600];
e281682b
SM		 6371
6372 u8 pas[0][0x40];
6373};
6374
6375struct mlx5_ifc_create_sq_out_bits {
6376 u8 status[0x8];
b4ff3a36 6377 u8 reserved_at_8[0x18];
e281682b
SM		 6378
6379 u8 syndrome[0x20];
6380
b4ff3a36 6381 u8 reserved_at_40[0x8];
e281682b
SM		 6382 u8 sqn[0x18];
6383
b4ff3a36 6384 u8 reserved_at_60[0x20];
e281682b
SM		 6385};
6386
6387struct mlx5_ifc_create_sq_in_bits {
6388 u8 opcode[0x10];
b4ff3a36 6389 u8 reserved_at_10[0x10];
e281682b 6390
b4ff3a36 6391 u8 reserved_at_20[0x10];
e281682b
SM		 6392 u8 op_mod[0x10];
6393
b4ff3a36 6394 u8 reserved_at_40[0xc0];
e281682b
SM		 6395
6396 struct mlx5_ifc_sqc_bits ctx;
6397};
6398
813f8540
MHY		 6399struct mlx5_ifc_create_scheduling_element_out_bits {
6400 u8 status[0x8];
6401 u8 reserved_at_8[0x18];
6402
6403 u8 syndrome[0x20];
6404
6405 u8 reserved_at_40[0x40];
6406
6407 u8 scheduling_element_id[0x20];
6408
6409 u8 reserved_at_a0[0x160];
6410};
6411
6412struct mlx5_ifc_create_scheduling_element_in_bits {
6413 u8 opcode[0x10];
6414 u8 reserved_at_10[0x10];
6415
6416 u8 reserved_at_20[0x10];
6417 u8 op_mod[0x10];
6418
6419 u8 scheduling_hierarchy[0x8];
6420 u8 reserved_at_48[0x18];
6421
6422 u8 reserved_at_60[0xa0];
6423
6424 struct mlx5_ifc_scheduling_context_bits scheduling_context;
6425
6426 u8 reserved_at_300[0x100];
6427};
6428
e281682b
SM		 6429struct mlx5_ifc_create_rqt_out_bits {
6430 u8 status[0x8];
b4ff3a36 6431 u8 reserved_at_8[0x18];
e281682b
SM		 6432
6433 u8 syndrome[0x20];
6434
b4ff3a36 6435 u8 reserved_at_40[0x8];
e281682b
SM		 6436 u8 rqtn[0x18];
6437
b4ff3a36 6438 u8 reserved_at_60[0x20];
e281682b
SM		 6439};
6440
6441struct mlx5_ifc_create_rqt_in_bits {
6442 u8 opcode[0x10];
b4ff3a36 6443 u8 reserved_at_10[0x10];
e281682b 6444
b4ff3a36 6445 u8 reserved_at_20[0x10];
e281682b
SM		 6446 u8 op_mod[0x10];
6447
b4ff3a36 6448 u8 reserved_at_40[0xc0];
e281682b
SM		 6449
6450 struct mlx5_ifc_rqtc_bits rqt_context;
6451};
6452
6453struct mlx5_ifc_create_rq_out_bits {
6454 u8 status[0x8];
b4ff3a36 6455 u8 reserved_at_8[0x18];
e281682b
SM		 6456
6457 u8 syndrome[0x20];
6458
b4ff3a36 6459 u8 reserved_at_40[0x8];
e281682b
SM		 6460 u8 rqn[0x18];
6461
b4ff3a36 6462 u8 reserved_at_60[0x20];
e281682b
SM		 6463};
6464
6465struct mlx5_ifc_create_rq_in_bits {
6466 u8 opcode[0x10];
b4ff3a36 6467 u8 reserved_at_10[0x10];
e281682b 6468
b4ff3a36 6469 u8 reserved_at_20[0x10];
e281682b
SM		 6470 u8 op_mod[0x10];
6471
b4ff3a36 6472 u8 reserved_at_40[0xc0];
e281682b
SM		 6473
6474 struct mlx5_ifc_rqc_bits ctx;
6475};
6476
6477struct mlx5_ifc_create_rmp_out_bits {
6478 u8 status[0x8];
b4ff3a36 6479 u8 reserved_at_8[0x18];
e281682b
SM		 6480
6481 u8 syndrome[0x20];
6482
b4ff3a36 6483 u8 reserved_at_40[0x8];
e281682b
SM		 6484 u8 rmpn[0x18];
6485
b4ff3a36 6486 u8 reserved_at_60[0x20];
e281682b
SM		 6487};
6488
6489struct mlx5_ifc_create_rmp_in_bits {
6490 u8 opcode[0x10];
b4ff3a36 6491 u8 reserved_at_10[0x10];
e281682b 6492
b4ff3a36 6493 u8 reserved_at_20[0x10];
e281682b
SM		 6494 u8 op_mod[0x10];
6495
b4ff3a36 6496 u8 reserved_at_40[0xc0];
e281682b
SM		 6497
6498 struct mlx5_ifc_rmpc_bits ctx;
6499};
6500
6501struct mlx5_ifc_create_qp_out_bits {
6502 u8 status[0x8];
b4ff3a36 6503 u8 reserved_at_8[0x18];
e281682b
SM		 6504
6505 u8 syndrome[0x20];
6506
b4ff3a36 6507 u8 reserved_at_40[0x8];
e281682b
SM		 6508 u8 qpn[0x18];
6509
b4ff3a36 6510 u8 reserved_at_60[0x20];
e281682b
SM		 6511};
6512
6513struct mlx5_ifc_create_qp_in_bits {
6514 u8 opcode[0x10];
b4ff3a36 6515 u8 reserved_at_10[0x10];
e281682b 6516
b4ff3a36 6517 u8 reserved_at_20[0x10];
e281682b
SM		 6518 u8 op_mod[0x10];
6519
b4ff3a36 6520 u8 reserved_at_40[0x40];
e281682b
SM		 6521
6522 u8 opt_param_mask[0x20];
6523
b4ff3a36 6524 u8 reserved_at_a0[0x20];
e281682b
SM		 6525
6526 struct mlx5_ifc_qpc_bits qpc;
6527
b4ff3a36 6528 u8 reserved_at_800[0x80];
e281682b
SM		 6529
6530 u8 pas[0][0x40];
6531};
6532
6533struct mlx5_ifc_create_psv_out_bits {
6534 u8 status[0x8];
b4ff3a36 6535 u8 reserved_at_8[0x18];
e281682b
SM		 6536
6537 u8 syndrome[0x20];
6538
b4ff3a36 6539 u8 reserved_at_40[0x40];
e281682b 6540
b4ff3a36 6541 u8 reserved_at_80[0x8];
e281682b
SM		 6542 u8 psv0_index[0x18];
6543
b4ff3a36 6544 u8 reserved_at_a0[0x8];
e281682b
SM		 6545 u8 psv1_index[0x18];
6546
b4ff3a36 6547 u8 reserved_at_c0[0x8];
e281682b
SM		 6548 u8 psv2_index[0x18];
6549
b4ff3a36 6550 u8 reserved_at_e0[0x8];
e281682b
SM		 6551 u8 psv3_index[0x18];
6552};
6553
6554struct mlx5_ifc_create_psv_in_bits {
6555 u8 opcode[0x10];
b4ff3a36 6556 u8 reserved_at_10[0x10];
e281682b 6557
b4ff3a36 6558 u8 reserved_at_20[0x10];
e281682b
SM		 6559 u8 op_mod[0x10];
6560
6561 u8 num_psv[0x4];
b4ff3a36 6562 u8 reserved_at_44[0x4];
e281682b
SM		 6563 u8 pd[0x18];
6564
b4ff3a36 6565 u8 reserved_at_60[0x20];
e281682b
SM		 6566};
6567
6568struct mlx5_ifc_create_mkey_out_bits {
6569 u8 status[0x8];
b4ff3a36 6570 u8 reserved_at_8[0x18];
e281682b
SM		 6571
6572 u8 syndrome[0x20];
6573
b4ff3a36 6574 u8 reserved_at_40[0x8];
e281682b
SM		 6575 u8 mkey_index[0x18];
6576
b4ff3a36 6577 u8 reserved_at_60[0x20];
e281682b
SM		 6578};
6579
6580struct mlx5_ifc_create_mkey_in_bits {
6581 u8 opcode[0x10];
b4ff3a36 6582 u8 reserved_at_10[0x10];
e281682b 6583
b4ff3a36 6584 u8 reserved_at_20[0x10];
e281682b
SM		 6585 u8 op_mod[0x10];
6586
b4ff3a36 6587 u8 reserved_at_40[0x20];
e281682b
SM		 6588
6589 u8 pg_access[0x1];
b4ff3a36 6590 u8 reserved_at_61[0x1f];
e281682b
SM		 6591
6592 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6593
b4ff3a36 6594 u8 reserved_at_280[0x80];
e281682b
SM		 6595
6596 u8 translations_octword_actual_size[0x20];
6597
b4ff3a36 6598 u8 reserved_at_320[0x560];
e281682b
SM		 6599
6600 u8 klm_pas_mtt[0][0x20];
6601};
6602
6603struct mlx5_ifc_create_flow_table_out_bits {
6604 u8 status[0x8];
b4ff3a36 6605 u8 reserved_at_8[0x18];
e281682b
SM		 6606
6607 u8 syndrome[0x20];
6608
b4ff3a36 6609 u8 reserved_at_40[0x8];
e281682b
SM		 6610 u8 table_id[0x18];
6611
b4ff3a36 6612 u8 reserved_at_60[0x20];
e281682b
SM		 6613};
6614
6615struct mlx5_ifc_create_flow_table_in_bits {
6616 u8 opcode[0x10];
b4ff3a36 6617 u8 reserved_at_10[0x10];
e281682b 6618
b4ff3a36 6619 u8 reserved_at_20[0x10];
e281682b
SM		 6620 u8 op_mod[0x10];
6621
7d5e1423
SM		 6622 u8 other_vport[0x1];
6623 u8 reserved_at_41[0xf];
6624 u8 vport_number[0x10];
6625
6626 u8 reserved_at_60[0x20];
e281682b
SM		 6627
6628 u8 table_type[0x8];
b4ff3a36 6629 u8 reserved_at_88[0x18];
e281682b 6630
b4ff3a36 6631 u8 reserved_at_a0[0x20];
e281682b 6632
7adbde20
HHZ		 6633 u8 encap_en[0x1];
6634 u8 decap_en[0x1];
6635 u8 reserved_at_c2[0x2];
34a40e68 6636 u8 table_miss_mode[0x4];
e281682b 6637 u8 level[0x8];
b4ff3a36 6638 u8 reserved_at_d0[0x8];
e281682b
SM		 6639 u8 log_size[0x8];
6640
b4ff3a36 6641 u8 reserved_at_e0[0x8];
34a40e68
MG		 6642 u8 table_miss_id[0x18];
6643
84df61eb
AH		 6644 u8 reserved_at_100[0x8];
6645 u8 lag_master_next_table_id[0x18];
6646
6647 u8 reserved_at_120[0x80];
e281682b
SM		 6648};
6649
6650struct mlx5_ifc_create_flow_group_out_bits {
6651 u8 status[0x8];
b4ff3a36 6652 u8 reserved_at_8[0x18];
e281682b
SM		 6653
6654 u8 syndrome[0x20];
6655
b4ff3a36 6656 u8 reserved_at_40[0x8];
e281682b
SM		 6657 u8 group_id[0x18];
6658
b4ff3a36 6659 u8 reserved_at_60[0x20];
e281682b
SM		 6660};
6661
6662enum {
6663 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
6664 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
6665 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
6666};
6667
6668struct mlx5_ifc_create_flow_group_in_bits {
6669 u8 opcode[0x10];
b4ff3a36 6670 u8 reserved_at_10[0x10];
e281682b 6671
b4ff3a36 6672 u8 reserved_at_20[0x10];
e281682b
SM		 6673 u8 op_mod[0x10];
6674
7d5e1423
SM		 6675 u8 other_vport[0x1];
6676 u8 reserved_at_41[0xf];
6677 u8 vport_number[0x10];
6678
6679 u8 reserved_at_60[0x20];
e281682b
SM		 6680
6681 u8 table_type[0x8];
b4ff3a36 6682 u8 reserved_at_88[0x18];
e281682b 6683
b4ff3a36 6684 u8 reserved_at_a0[0x8];
e281682b
SM		 6685 u8 table_id[0x18];
6686
b4ff3a36 6687 u8 reserved_at_c0[0x20];
e281682b
SM		 6688
6689 u8 start_flow_index[0x20];
6690
b4ff3a36 6691 u8 reserved_at_100[0x20];
e281682b
SM		 6692
6693 u8 end_flow_index[0x20];
6694
b4ff3a36 6695 u8 reserved_at_140[0xa0];
e281682b 6696
b4ff3a36 6697 u8 reserved_at_1e0[0x18];
e281682b
SM		 6698 u8 match_criteria_enable[0x8];
6699
6700 struct mlx5_ifc_fte_match_param_bits match_criteria;
6701
b4ff3a36 6702 u8 reserved_at_1200[0xe00];
e281682b
SM		 6703};
6704
6705struct mlx5_ifc_create_eq_out_bits {
6706 u8 status[0x8];
b4ff3a36 6707 u8 reserved_at_8[0x18];
e281682b
SM		 6708
6709 u8 syndrome[0x20];
6710
b4ff3a36 6711 u8 reserved_at_40[0x18];
e281682b
SM		 6712 u8 eq_number[0x8];
6713
b4ff3a36 6714 u8 reserved_at_60[0x20];
e281682b
SM		 6715};
6716
6717struct mlx5_ifc_create_eq_in_bits {
6718 u8 opcode[0x10];
b4ff3a36 6719 u8 reserved_at_10[0x10];
e281682b 6720
b4ff3a36 6721 u8 reserved_at_20[0x10];
e281682b
SM		 6722 u8 op_mod[0x10];
6723
b4ff3a36 6724 u8 reserved_at_40[0x40];
e281682b
SM		 6725
6726 struct mlx5_ifc_eqc_bits eq_context_entry;
6727
b4ff3a36 6728 u8 reserved_at_280[0x40];
e281682b
SM		 6729
6730 u8 event_bitmask[0x40];
6731
b4ff3a36 6732 u8 reserved_at_300[0x580];
e281682b
SM		 6733
6734 u8 pas[0][0x40];
6735};
6736
6737struct mlx5_ifc_create_dct_out_bits {
6738 u8 status[0x8];
b4ff3a36 6739 u8 reserved_at_8[0x18];
e281682b
SM		 6740
6741 u8 syndrome[0x20];
6742
b4ff3a36 6743 u8 reserved_at_40[0x8];
e281682b
SM		 6744 u8 dctn[0x18];
6745
b4ff3a36 6746 u8 reserved_at_60[0x20];
e281682b
SM		 6747};
6748
6749struct mlx5_ifc_create_dct_in_bits {
6750 u8 opcode[0x10];
b4ff3a36 6751 u8 reserved_at_10[0x10];
e281682b 6752
b4ff3a36 6753 u8 reserved_at_20[0x10];
e281682b
SM		 6754 u8 op_mod[0x10];
6755
b4ff3a36 6756 u8 reserved_at_40[0x40];
e281682b
SM		 6757
6758 struct mlx5_ifc_dctc_bits dct_context_entry;
6759
b4ff3a36 6760 u8 reserved_at_280[0x180];
e281682b
SM		 6761};
6762
6763struct mlx5_ifc_create_cq_out_bits {
6764 u8 status[0x8];
b4ff3a36 6765 u8 reserved_at_8[0x18];
e281682b
SM		 6766
6767 u8 syndrome[0x20];
6768
b4ff3a36 6769 u8 reserved_at_40[0x8];
e281682b
SM		 6770 u8 cqn[0x18];
6771
b4ff3a36 6772 u8 reserved_at_60[0x20];
e281682b
SM		 6773};
6774
6775struct mlx5_ifc_create_cq_in_bits {
6776 u8 opcode[0x10];
b4ff3a36 6777 u8 reserved_at_10[0x10];
e281682b 6778
b4ff3a36 6779 u8 reserved_at_20[0x10];
e281682b
SM		 6780 u8 op_mod[0x10];
6781
b4ff3a36 6782 u8 reserved_at_40[0x40];
e281682b
SM		 6783
6784 struct mlx5_ifc_cqc_bits cq_context;
6785
b4ff3a36 6786 u8 reserved_at_280[0x600];
e281682b
SM		 6787
6788 u8 pas[0][0x40];
6789};
6790
6791struct mlx5_ifc_config_int_moderation_out_bits {
6792 u8 status[0x8];
b4ff3a36 6793 u8 reserved_at_8[0x18];
e281682b
SM		 6794
6795 u8 syndrome[0x20];
6796
b4ff3a36 6797 u8 reserved_at_40[0x4];
e281682b
SM		 6798 u8 min_delay[0xc];
6799 u8 int_vector[0x10];
6800
b4ff3a36 6801 u8 reserved_at_60[0x20];
e281682b
SM		 6802};
6803
6804enum {
6805 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
6806 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
6807};
6808
6809struct mlx5_ifc_config_int_moderation_in_bits {
6810 u8 opcode[0x10];
b4ff3a36 6811 u8 reserved_at_10[0x10];
e281682b 6812
b4ff3a36 6813 u8 reserved_at_20[0x10];
e281682b
SM		 6814 u8 op_mod[0x10];
6815
b4ff3a36 6816 u8 reserved_at_40[0x4];
e281682b
SM		 6817 u8 min_delay[0xc];
6818 u8 int_vector[0x10];
6819
b4ff3a36 6820 u8 reserved_at_60[0x20];
e281682b
SM		 6821};
6822
6823struct mlx5_ifc_attach_to_mcg_out_bits {
6824 u8 status[0x8];
b4ff3a36 6825 u8 reserved_at_8[0x18];
e281682b
SM		 6826
6827 u8 syndrome[0x20];
6828
b4ff3a36 6829 u8 reserved_at_40[0x40];
e281682b
SM		 6830};
6831
6832struct mlx5_ifc_attach_to_mcg_in_bits {
6833 u8 opcode[0x10];
b4ff3a36 6834 u8 reserved_at_10[0x10];
e281682b 6835
b4ff3a36 6836 u8 reserved_at_20[0x10];
e281682b
SM		 6837 u8 op_mod[0x10];
6838
b4ff3a36 6839 u8 reserved_at_40[0x8];
e281682b
SM		 6840 u8 qpn[0x18];
6841
b4ff3a36 6842 u8 reserved_at_60[0x20];
e281682b
SM		 6843
6844 u8 multicast_gid[16][0x8];
6845};
6846
7486216b
SM		 6847struct mlx5_ifc_arm_xrq_out_bits {
6848 u8 status[0x8];
6849 u8 reserved_at_8[0x18];
6850
6851 u8 syndrome[0x20];
6852
6853 u8 reserved_at_40[0x40];
6854};
6855
6856struct mlx5_ifc_arm_xrq_in_bits {
6857 u8 opcode[0x10];
6858 u8 reserved_at_10[0x10];
6859
6860 u8 reserved_at_20[0x10];
6861 u8 op_mod[0x10];
6862
6863 u8 reserved_at_40[0x8];
6864 u8 xrqn[0x18];
6865
6866 u8 reserved_at_60[0x10];
6867 u8 lwm[0x10];
6868};
6869
e281682b
SM		 6870struct mlx5_ifc_arm_xrc_srq_out_bits {
6871 u8 status[0x8];
b4ff3a36 6872 u8 reserved_at_8[0x18];
e281682b
SM		 6873
6874 u8 syndrome[0x20];
6875
b4ff3a36 6876 u8 reserved_at_40[0x40];
e281682b
SM		 6877};
6878
6879enum {
6880 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
6881};
6882
6883struct mlx5_ifc_arm_xrc_srq_in_bits {
6884 u8 opcode[0x10];
b4ff3a36 6885 u8 reserved_at_10[0x10];
e281682b 6886
b4ff3a36 6887 u8 reserved_at_20[0x10];
e281682b
SM		 6888 u8 op_mod[0x10];
6889
b4ff3a36 6890 u8 reserved_at_40[0x8];
e281682b
SM		 6891 u8 xrc_srqn[0x18];
6892
b4ff3a36 6893 u8 reserved_at_60[0x10];
e281682b
SM		 6894 u8 lwm[0x10];
6895};
6896
6897struct mlx5_ifc_arm_rq_out_bits {
6898 u8 status[0x8];
b4ff3a36 6899 u8 reserved_at_8[0x18];
e281682b
SM		 6900
6901 u8 syndrome[0x20];
6902
b4ff3a36 6903 u8 reserved_at_40[0x40];
e281682b
SM		 6904};
6905
6906enum {
7486216b
SM		 6907 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
6908 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
e281682b
SM		 6909};
6910
6911struct mlx5_ifc_arm_rq_in_bits {
6912 u8 opcode[0x10];
b4ff3a36 6913 u8 reserved_at_10[0x10];
e281682b 6914
b4ff3a36 6915 u8 reserved_at_20[0x10];
e281682b
SM		 6916 u8 op_mod[0x10];
6917
b4ff3a36 6918 u8 reserved_at_40[0x8];
e281682b
SM		 6919 u8 srq_number[0x18];
6920
b4ff3a36 6921 u8 reserved_at_60[0x10];
e281682b
SM		 6922 u8 lwm[0x10];
6923};
6924
6925struct mlx5_ifc_arm_dct_out_bits {
6926 u8 status[0x8];
b4ff3a36 6927 u8 reserved_at_8[0x18];
e281682b
SM		 6928
6929 u8 syndrome[0x20];
6930
b4ff3a36 6931 u8 reserved_at_40[0x40];
e281682b
SM		 6932};
6933
6934struct mlx5_ifc_arm_dct_in_bits {
6935 u8 opcode[0x10];
b4ff3a36 6936 u8 reserved_at_10[0x10];
e281682b 6937
b4ff3a36 6938 u8 reserved_at_20[0x10];
e281682b
SM		 6939 u8 op_mod[0x10];
6940
b4ff3a36 6941 u8 reserved_at_40[0x8];
e281682b
SM		 6942 u8 dct_number[0x18];
6943
b4ff3a36 6944 u8 reserved_at_60[0x20];
e281682b
SM		 6945};
6946
6947struct mlx5_ifc_alloc_xrcd_out_bits {
6948 u8 status[0x8];
b4ff3a36 6949 u8 reserved_at_8[0x18];
e281682b
SM		 6950
6951 u8 syndrome[0x20];
6952
b4ff3a36 6953 u8 reserved_at_40[0x8];
e281682b
SM		 6954 u8 xrcd[0x18];
6955
b4ff3a36 6956 u8 reserved_at_60[0x20];
e281682b
SM		 6957};
6958
6959struct mlx5_ifc_alloc_xrcd_in_bits {
6960 u8 opcode[0x10];
b4ff3a36 6961 u8 reserved_at_10[0x10];
e281682b 6962
b4ff3a36 6963 u8 reserved_at_20[0x10];
e281682b
SM		 6964 u8 op_mod[0x10];
6965
b4ff3a36 6966 u8 reserved_at_40[0x40];
e281682b
SM		 6967};
6968
6969struct mlx5_ifc_alloc_uar_out_bits {
6970 u8 status[0x8];
b4ff3a36 6971 u8 reserved_at_8[0x18];
e281682b
SM		 6972
6973 u8 syndrome[0x20];
6974
b4ff3a36 6975 u8 reserved_at_40[0x8];
e281682b
SM		 6976 u8 uar[0x18];
6977
b4ff3a36 6978 u8 reserved_at_60[0x20];
e281682b
SM		 6979};
6980
6981struct mlx5_ifc_alloc_uar_in_bits {
6982 u8 opcode[0x10];
b4ff3a36 6983 u8 reserved_at_10[0x10];
e281682b 6984
b4ff3a36 6985 u8 reserved_at_20[0x10];
e281682b
SM		 6986 u8 op_mod[0x10];
6987
b4ff3a36 6988 u8 reserved_at_40[0x40];
e281682b
SM		 6989};
6990
6991struct mlx5_ifc_alloc_transport_domain_out_bits {
6992 u8 status[0x8];
b4ff3a36 6993 u8 reserved_at_8[0x18];
e281682b
SM		 6994
6995 u8 syndrome[0x20];
6996
b4ff3a36 6997 u8 reserved_at_40[0x8];
e281682b
SM		 6998 u8 transport_domain[0x18];
6999
b4ff3a36 7000 u8 reserved_at_60[0x20];
e281682b
SM		 7001};
7002
7003struct mlx5_ifc_alloc_transport_domain_in_bits {
7004 u8 opcode[0x10];
b4ff3a36 7005 u8 reserved_at_10[0x10];
e281682b 7006
b4ff3a36 7007 u8 reserved_at_20[0x10];
e281682b
SM		 7008 u8 op_mod[0x10];
7009
b4ff3a36 7010 u8 reserved_at_40[0x40];
e281682b
SM		 7011};
7012
7013struct mlx5_ifc_alloc_q_counter_out_bits {
7014 u8 status[0x8];
b4ff3a36 7015 u8 reserved_at_8[0x18];
e281682b
SM		 7016
7017 u8 syndrome[0x20];
7018
b4ff3a36 7019 u8 reserved_at_40[0x18];
e281682b
SM		 7020 u8 counter_set_id[0x8];
7021
b4ff3a36 7022 u8 reserved_at_60[0x20];
e281682b
SM		 7023};
7024
7025struct mlx5_ifc_alloc_q_counter_in_bits {
7026 u8 opcode[0x10];
b4ff3a36 7027 u8 reserved_at_10[0x10];
e281682b 7028
b4ff3a36 7029 u8 reserved_at_20[0x10];
e281682b
SM		 7030 u8 op_mod[0x10];
7031
b4ff3a36 7032 u8 reserved_at_40[0x40];
e281682b
SM		 7033};
7034
7035struct mlx5_ifc_alloc_pd_out_bits {
7036 u8 status[0x8];
b4ff3a36 7037 u8 reserved_at_8[0x18];
e281682b
SM		 7038
7039 u8 syndrome[0x20];
7040
b4ff3a36 7041 u8 reserved_at_40[0x8];
e281682b
SM		 7042 u8 pd[0x18];
7043
b4ff3a36 7044 u8 reserved_at_60[0x20];
e281682b
SM		 7045};
7046
7047struct mlx5_ifc_alloc_pd_in_bits {
9dc0b289
AV		 7048 u8 opcode[0x10];
7049 u8 reserved_at_10[0x10];
7050
7051 u8 reserved_at_20[0x10];
7052 u8 op_mod[0x10];
7053
7054 u8 reserved_at_40[0x40];
7055};
7056
7057struct mlx5_ifc_alloc_flow_counter_out_bits {
7058 u8 status[0x8];
7059 u8 reserved_at_8[0x18];
7060
7061 u8 syndrome[0x20];
7062
7063 u8 reserved_at_40[0x10];
7064 u8 flow_counter_id[0x10];
7065
7066 u8 reserved_at_60[0x20];
7067};
7068
7069struct mlx5_ifc_alloc_flow_counter_in_bits {
e281682b 7070 u8 opcode[0x10];
b4ff3a36 7071 u8 reserved_at_10[0x10];
e281682b 7072
b4ff3a36 7073 u8 reserved_at_20[0x10];
e281682b
SM		 7074 u8 op_mod[0x10];
7075
b4ff3a36 7076 u8 reserved_at_40[0x40];
e281682b
SM		 7077};
7078
7079struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
7080 u8 status[0x8];
b4ff3a36 7081 u8 reserved_at_8[0x18];
e281682b
SM		 7082
7083 u8 syndrome[0x20];
7084
b4ff3a36 7085 u8 reserved_at_40[0x40];
e281682b
SM		 7086};
7087
7088struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
7089 u8 opcode[0x10];
b4ff3a36 7090 u8 reserved_at_10[0x10];
e281682b 7091
b4ff3a36 7092 u8 reserved_at_20[0x10];
e281682b
SM		 7093 u8 op_mod[0x10];
7094
b4ff3a36 7095 u8 reserved_at_40[0x20];
e281682b 7096
b4ff3a36 7097 u8 reserved_at_60[0x10];
e281682b
SM		 7098 u8 vxlan_udp_port[0x10];
7099};
7100
7486216b
SM		 7101struct mlx5_ifc_set_rate_limit_out_bits {
7102 u8 status[0x8];
7103 u8 reserved_at_8[0x18];
7104
7105 u8 syndrome[0x20];
7106
7107 u8 reserved_at_40[0x40];
7108};
7109
7110struct mlx5_ifc_set_rate_limit_in_bits {
7111 u8 opcode[0x10];
7112 u8 reserved_at_10[0x10];
7113
7114 u8 reserved_at_20[0x10];
7115 u8 op_mod[0x10];
7116
7117 u8 reserved_at_40[0x10];
7118 u8 rate_limit_index[0x10];
7119
7120 u8 reserved_at_60[0x20];
7121
7122 u8 rate_limit[0x20];
7123};
7124
e281682b
SM		 7125struct mlx5_ifc_access_register_out_bits {
7126 u8 status[0x8];
b4ff3a36 7127 u8 reserved_at_8[0x18];
e281682b
SM		 7128
7129 u8 syndrome[0x20];
7130
b4ff3a36 7131 u8 reserved_at_40[0x40];
e281682b
SM		 7132
7133 u8 register_data[0][0x20];
7134};
7135
7136enum {
7137 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
7138 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
7139};
7140
7141struct mlx5_ifc_access_register_in_bits {
7142 u8 opcode[0x10];
b4ff3a36 7143 u8 reserved_at_10[0x10];
e281682b 7144
b4ff3a36 7145 u8 reserved_at_20[0x10];
e281682b
SM		 7146 u8 op_mod[0x10];
7147
b4ff3a36 7148 u8 reserved_at_40[0x10];
e281682b
SM		 7149 u8 register_id[0x10];
7150
7151 u8 argument[0x20];
7152
7153 u8 register_data[0][0x20];
7154};
7155
7156struct mlx5_ifc_sltp_reg_bits {
7157 u8 status[0x4];
7158 u8 version[0x4];
7159 u8 local_port[0x8];
7160 u8 pnat[0x2];
b4ff3a36 7161 u8 reserved_at_12[0x2];
e281682b 7162 u8 lane[0x4];
b4ff3a36 7163 u8 reserved_at_18[0x8];
e281682b 7164
b4ff3a36 7165 u8 reserved_at_20[0x20];
e281682b 7166
b4ff3a36 7167 u8 reserved_at_40[0x7];
e281682b
SM		 7168 u8 polarity[0x1];
7169 u8 ob_tap0[0x8];
7170 u8 ob_tap1[0x8];
7171 u8 ob_tap2[0x8];
7172
b4ff3a36 7173 u8 reserved_at_60[0xc];
e281682b
SM		 7174 u8 ob_preemp_mode[0x4];
7175 u8 ob_reg[0x8];
7176 u8 ob_bias[0x8];
7177
b4ff3a36 7178 u8 reserved_at_80[0x20];
e281682b
SM		 7179};
7180
7181struct mlx5_ifc_slrg_reg_bits {
7182 u8 status[0x4];
7183 u8 version[0x4];
7184 u8 local_port[0x8];
7185 u8 pnat[0x2];
b4ff3a36 7186 u8 reserved_at_12[0x2];
e281682b 7187 u8 lane[0x4];
b4ff3a36 7188 u8 reserved_at_18[0x8];
e281682b
SM		 7189
7190 u8 time_to_link_up[0x10];
b4ff3a36 7191 u8 reserved_at_30[0xc];
e281682b
SM		 7192 u8 grade_lane_speed[0x4];
7193
7194 u8 grade_version[0x8];
7195 u8 grade[0x18];
7196
b4ff3a36 7197 u8 reserved_at_60[0x4];
e281682b
SM		 7198 u8 height_grade_type[0x4];
7199 u8 height_grade[0x18];
7200
7201 u8 height_dz[0x10];
7202 u8 height_dv[0x10];
7203
b4ff3a36 7204 u8 reserved_at_a0[0x10];
e281682b
SM		 7205 u8 height_sigma[0x10];
7206
b4ff3a36 7207 u8 reserved_at_c0[0x20];
e281682b 7208
b4ff3a36 7209 u8 reserved_at_e0[0x4];
e281682b
SM		 7210 u8 phase_grade_type[0x4];
7211 u8 phase_grade[0x18];
7212
b4ff3a36 7213 u8 reserved_at_100[0x8];
e281682b 7214 u8 phase_eo_pos[0x8];
b4ff3a36 7215 u8 reserved_at_110[0x8];
e281682b
SM		 7216 u8 phase_eo_neg[0x8];
7217
7218 u8 ffe_set_tested[0x10];
7219 u8 test_errors_per_lane[0x10];
7220};
7221
7222struct mlx5_ifc_pvlc_reg_bits {
b4ff3a36 7223 u8 reserved_at_0[0x8];
e281682b 7224 u8 local_port[0x8];
b4ff3a36 7225 u8 reserved_at_10[0x10];
e281682b 7226
b4ff3a36 7227 u8 reserved_at_20[0x1c];
e281682b
SM		 7228 u8 vl_hw_cap[0x4];
7229
b4ff3a36 7230 u8 reserved_at_40[0x1c];
e281682b
SM		 7231 u8 vl_admin[0x4];
7232
b4ff3a36 7233 u8 reserved_at_60[0x1c];
e281682b
SM		 7234 u8 vl_operational[0x4];
7235};
7236
7237struct mlx5_ifc_pude_reg_bits {
7238 u8 swid[0x8];
7239 u8 local_port[0x8];
b4ff3a36 7240 u8 reserved_at_10[0x4];
e281682b 7241 u8 admin_status[0x4];
b4ff3a36 7242 u8 reserved_at_18[0x4];
e281682b
SM		 7243 u8 oper_status[0x4];
7244
b4ff3a36 7245 u8 reserved_at_20[0x60];
e281682b
SM		 7246};
7247
7248struct mlx5_ifc_ptys_reg_bits {
e7e31ca4 7249 u8 reserved_at_0[0x1];
7486216b 7250 u8 an_disable_admin[0x1];
e7e31ca4
BW		 7251 u8 an_disable_cap[0x1];
7252 u8 reserved_at_3[0x5];
e281682b 7253 u8 local_port[0x8];
b4ff3a36 7254 u8 reserved_at_10[0xd];
e281682b
SM		 7255 u8 proto_mask[0x3];
7256
7486216b
SM		 7257 u8 an_status[0x4];
7258 u8 reserved_at_24[0x3c];
e281682b
SM		 7259
7260 u8 eth_proto_capability[0x20];
7261
7262 u8 ib_link_width_capability[0x10];
7263 u8 ib_proto_capability[0x10];
7264
b4ff3a36 7265 u8 reserved_at_a0[0x20];
e281682b
SM		 7266
7267 u8 eth_proto_admin[0x20];
7268
7269 u8 ib_link_width_admin[0x10];
7270 u8 ib_proto_admin[0x10];
7271
b4ff3a36 7272 u8 reserved_at_100[0x20];
e281682b
SM		 7273
7274 u8 eth_proto_oper[0x20];
7275
7276 u8 ib_link_width_oper[0x10];
7277 u8 ib_proto_oper[0x10];
7278
b4ff3a36 7279 u8 reserved_at_160[0x20];
e281682b
SM		 7280
7281 u8 eth_proto_lp_advertise[0x20];
7282
b4ff3a36 7283 u8 reserved_at_1a0[0x60];
e281682b
SM		 7284};
7285
7d5e1423
SM		 7286struct mlx5_ifc_mlcr_reg_bits {
7287 u8 reserved_at_0[0x8];
7288 u8 local_port[0x8];
7289 u8 reserved_at_10[0x20];
7290
7291 u8 beacon_duration[0x10];
7292 u8 reserved_at_40[0x10];
7293
7294 u8 beacon_remain[0x10];
7295};
7296
e281682b 7297struct mlx5_ifc_ptas_reg_bits {
b4ff3a36 7298 u8 reserved_at_0[0x20];
e281682b
SM		 7299
7300 u8 algorithm_options[0x10];
b4ff3a36 7301 u8 reserved_at_30[0x4];
e281682b
SM		 7302 u8 repetitions_mode[0x4];
7303 u8 num_of_repetitions[0x8];
7304
7305 u8 grade_version[0x8];
7306 u8 height_grade_type[0x4];
7307 u8 phase_grade_type[0x4];
7308 u8 height_grade_weight[0x8];
7309 u8 phase_grade_weight[0x8];
7310
7311 u8 gisim_measure_bits[0x10];
7312 u8 adaptive_tap_measure_bits[0x10];
7313
7314 u8 ber_bath_high_error_threshold[0x10];
7315 u8 ber_bath_mid_error_threshold[0x10];
7316
7317 u8 ber_bath_low_error_threshold[0x10];
7318 u8 one_ratio_high_threshold[0x10];
7319
7320 u8 one_ratio_high_mid_threshold[0x10];
7321 u8 one_ratio_low_mid_threshold[0x10];
7322
7323 u8 one_ratio_low_threshold[0x10];
7324 u8 ndeo_error_threshold[0x10];
7325
7326 u8 mixer_offset_step_size[0x10];
b4ff3a36 7327 u8 reserved_at_110[0x8];
e281682b
SM		 7328 u8 mix90_phase_for_voltage_bath[0x8];
7329
7330 u8 mixer_offset_start[0x10];
7331 u8 mixer_offset_end[0x10];
7332
b4ff3a36 7333 u8 reserved_at_140[0x15];
e281682b
SM		 7334 u8 ber_test_time[0xb];
7335};
7336
7337struct mlx5_ifc_pspa_reg_bits {
7338 u8 swid[0x8];
7339 u8 local_port[0x8];
7340 u8 sub_port[0x8];
b4ff3a36 7341 u8 reserved_at_18[0x8];
e281682b 7342
b4ff3a36 7343 u8 reserved_at_20[0x20];
e281682b
SM		 7344};
7345
7346struct mlx5_ifc_pqdr_reg_bits {
b4ff3a36 7347 u8 reserved_at_0[0x8];
e281682b 7348 u8 local_port[0x8];
b4ff3a36 7349 u8 reserved_at_10[0x5];
e281682b 7350 u8 prio[0x3];
b4ff3a36 7351 u8 reserved_at_18[0x6];
e281682b
SM		 7352 u8 mode[0x2];
7353
b4ff3a36 7354 u8 reserved_at_20[0x20];
e281682b 7355
b4ff3a36 7356 u8 reserved_at_40[0x10];
e281682b
SM		 7357 u8 min_threshold[0x10];
7358
b4ff3a36 7359 u8 reserved_at_60[0x10];
e281682b
SM		 7360 u8 max_threshold[0x10];
7361
b4ff3a36 7362 u8 reserved_at_80[0x10];
e281682b
SM		 7363 u8 mark_probability_denominator[0x10];
7364
b4ff3a36 7365 u8 reserved_at_a0[0x60];
e281682b
SM		 7366};
7367
7368struct mlx5_ifc_ppsc_reg_bits {
b4ff3a36 7369 u8 reserved_at_0[0x8];
e281682b 7370 u8 local_port[0x8];
b4ff3a36 7371 u8 reserved_at_10[0x10];
e281682b 7372
b4ff3a36 7373 u8 reserved_at_20[0x60];
e281682b 7374
b4ff3a36 7375 u8 reserved_at_80[0x1c];
e281682b
SM		 7376 u8 wrps_admin[0x4];
7377
b4ff3a36 7378 u8 reserved_at_a0[0x1c];
e281682b
SM		 7379 u8 wrps_status[0x4];
7380
b4ff3a36 7381 u8 reserved_at_c0[0x8];
e281682b 7382 u8 up_threshold[0x8];
b4ff3a36 7383 u8 reserved_at_d0[0x8];
e281682b
SM		 7384 u8 down_threshold[0x8];
7385
b4ff3a36 7386 u8 reserved_at_e0[0x20];
e281682b 7387
b4ff3a36 7388 u8 reserved_at_100[0x1c];
e281682b
SM		 7389 u8 srps_admin[0x4];
7390
b4ff3a36 7391 u8 reserved_at_120[0x1c];
e281682b
SM		 7392 u8 srps_status[0x4];
7393
b4ff3a36 7394 u8 reserved_at_140[0x40];
e281682b
SM		 7395};
7396
7397struct mlx5_ifc_pplr_reg_bits {
b4ff3a36 7398 u8 reserved_at_0[0x8];
e281682b 7399 u8 local_port[0x8];
b4ff3a36 7400 u8 reserved_at_10[0x10];
e281682b 7401
b4ff3a36 7402 u8 reserved_at_20[0x8];
e281682b 7403 u8 lb_cap[0x8];
b4ff3a36 7404 u8 reserved_at_30[0x8];
e281682b
SM		 7405 u8 lb_en[0x8];
7406};
7407
7408struct mlx5_ifc_pplm_reg_bits {
b4ff3a36 7409 u8 reserved_at_0[0x8];
e281682b 7410 u8 local_port[0x8];
b4ff3a36 7411 u8 reserved_at_10[0x10];
e281682b 7412
b4ff3a36 7413 u8 reserved_at_20[0x20];
e281682b
SM		 7414
7415 u8 port_profile_mode[0x8];
7416 u8 static_port_profile[0x8];
7417 u8 active_port_profile[0x8];
b4ff3a36 7418 u8 reserved_at_58[0x8];
e281682b
SM		 7419
7420 u8 retransmission_active[0x8];
7421 u8 fec_mode_active[0x18];
7422
b4ff3a36 7423 u8 reserved_at_80[0x20];
e281682b
SM		 7424};
7425
7426struct mlx5_ifc_ppcnt_reg_bits {
7427 u8 swid[0x8];
7428 u8 local_port[0x8];
7429 u8 pnat[0x2];
b4ff3a36 7430 u8 reserved_at_12[0x8];
e281682b
SM		 7431 u8 grp[0x6];
7432
7433 u8 clr[0x1];
b4ff3a36 7434 u8 reserved_at_21[0x1c];
e281682b
SM		 7435 u8 prio_tc[0x3];
7436
7437 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
7438};
7439
8ed1a630
GP		 7440struct mlx5_ifc_mpcnt_reg_bits {
7441 u8 reserved_at_0[0x8];
7442 u8 pcie_index[0x8];
7443 u8 reserved_at_10[0xa];
7444 u8 grp[0x6];
7445
7446 u8 clr[0x1];
7447 u8 reserved_at_21[0x1f];
7448
7449 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
7450};
7451
e281682b 7452struct mlx5_ifc_ppad_reg_bits {
b4ff3a36 7453 u8 reserved_at_0[0x3];
e281682b 7454 u8 single_mac[0x1];
b4ff3a36 7455 u8 reserved_at_4[0x4];
e281682b
SM		 7456 u8 local_port[0x8];
7457 u8 mac_47_32[0x10];
7458
7459 u8 mac_31_0[0x20];
7460
b4ff3a36 7461 u8 reserved_at_40[0x40];
e281682b
SM		 7462};
7463
7464struct mlx5_ifc_pmtu_reg_bits {
b4ff3a36 7465 u8 reserved_at_0[0x8];
e281682b 7466 u8 local_port[0x8];
b4ff3a36 7467 u8 reserved_at_10[0x10];
e281682b
SM		 7468
7469 u8 max_mtu[0x10];
b4ff3a36 7470 u8 reserved_at_30[0x10];
e281682b
SM		 7471
7472 u8 admin_mtu[0x10];
b4ff3a36 7473 u8 reserved_at_50[0x10];
e281682b
SM		 7474
7475 u8 oper_mtu[0x10];
b4ff3a36 7476 u8 reserved_at_70[0x10];
e281682b
SM		 7477};
7478
7479struct mlx5_ifc_pmpr_reg_bits {
b4ff3a36 7480 u8 reserved_at_0[0x8];
e281682b 7481 u8 module[0x8];
b4ff3a36 7482 u8 reserved_at_10[0x10];
e281682b 7483
b4ff3a36 7484 u8 reserved_at_20[0x18];
e281682b
SM		 7485 u8 attenuation_5g[0x8];
7486
b4ff3a36 7487 u8 reserved_at_40[0x18];
e281682b
SM		 7488 u8 attenuation_7g[0x8];
7489
b4ff3a36 7490 u8 reserved_at_60[0x18];
e281682b
SM		 7491 u8 attenuation_12g[0x8];
7492};
7493
7494struct mlx5_ifc_pmpe_reg_bits {
b4ff3a36 7495 u8 reserved_at_0[0x8];
e281682b 7496 u8 module[0x8];
b4ff3a36 7497 u8 reserved_at_10[0xc];
e281682b
SM		 7498 u8 module_status[0x4];
7499
b4ff3a36 7500 u8 reserved_at_20[0x60];
e281682b
SM		 7501};
7502
7503struct mlx5_ifc_pmpc_reg_bits {
7504 u8 module_state_updated[32][0x8];
7505};
7506
7507struct mlx5_ifc_pmlpn_reg_bits {
b4ff3a36 7508 u8 reserved_at_0[0x4];
e281682b
SM		 7509 u8 mlpn_status[0x4];
7510 u8 local_port[0x8];
b4ff3a36 7511 u8 reserved_at_10[0x10];
e281682b
SM		 7512
7513 u8 e[0x1];
b4ff3a36 7514 u8 reserved_at_21[0x1f];
e281682b
SM		 7515};
7516
7517struct mlx5_ifc_pmlp_reg_bits {
7518 u8 rxtx[0x1];
b4ff3a36 7519 u8 reserved_at_1[0x7];
e281682b 7520 u8 local_port[0x8];
b4ff3a36 7521 u8 reserved_at_10[0x8];
e281682b
SM		 7522 u8 width[0x8];
7523
7524 u8 lane0_module_mapping[0x20];
7525
7526 u8 lane1_module_mapping[0x20];
7527
7528 u8 lane2_module_mapping[0x20];
7529
7530 u8 lane3_module_mapping[0x20];
7531
b4ff3a36 7532 u8 reserved_at_a0[0x160];
e281682b
SM		 7533};
7534
7535struct mlx5_ifc_pmaos_reg_bits {
b4ff3a36 7536 u8 reserved_at_0[0x8];
e281682b 7537 u8 module[0x8];
b4ff3a36 7538 u8 reserved_at_10[0x4];
e281682b 7539 u8 admin_status[0x4];
b4ff3a36 7540 u8 reserved_at_18[0x4];
e281682b
SM		 7541 u8 oper_status[0x4];
7542
7543 u8 ase[0x1];
7544 u8 ee[0x1];
b4ff3a36 7545 u8 reserved_at_22[0x1c];
e281682b
SM		 7546 u8 e[0x2];
7547
b4ff3a36 7548 u8 reserved_at_40[0x40];
e281682b
SM		 7549};
7550
7551struct mlx5_ifc_plpc_reg_bits {
b4ff3a36 7552 u8 reserved_at_0[0x4];
e281682b 7553 u8 profile_id[0xc];
b4ff3a36 7554 u8 reserved_at_10[0x4];
e281682b 7555 u8 proto_mask[0x4];
b4ff3a36 7556 u8 reserved_at_18[0x8];
e281682b 7557
b4ff3a36 7558 u8 reserved_at_20[0x10];
e281682b
SM		 7559 u8 lane_speed[0x10];
7560
b4ff3a36 7561 u8 reserved_at_40[0x17];
e281682b
SM		 7562 u8 lpbf[0x1];
7563 u8 fec_mode_policy[0x8];
7564
7565 u8 retransmission_capability[0x8];
7566 u8 fec_mode_capability[0x18];
7567
7568 u8 retransmission_support_admin[0x8];
7569 u8 fec_mode_support_admin[0x18];
7570
7571 u8 retransmission_request_admin[0x8];
7572 u8 fec_mode_request_admin[0x18];
7573
b4ff3a36 7574 u8 reserved_at_c0[0x80];
e281682b
SM		 7575};
7576
7577struct mlx5_ifc_plib_reg_bits {
b4ff3a36 7578 u8 reserved_at_0[0x8];
e281682b 7579 u8 local_port[0x8];
b4ff3a36 7580 u8 reserved_at_10[0x8];
e281682b
SM		 7581 u8 ib_port[0x8];
7582
b4ff3a36 7583 u8 reserved_at_20[0x60];
e281682b
SM		 7584};
7585
7586struct mlx5_ifc_plbf_reg_bits {
b4ff3a36 7587 u8 reserved_at_0[0x8];
e281682b 7588 u8 local_port[0x8];
b4ff3a36 7589 u8 reserved_at_10[0xd];
e281682b
SM		 7590 u8 lbf_mode[0x3];
7591
b4ff3a36 7592 u8 reserved_at_20[0x20];
e281682b
SM		 7593};
7594
7595struct mlx5_ifc_pipg_reg_bits {
b4ff3a36 7596 u8 reserved_at_0[0x8];
e281682b 7597 u8 local_port[0x8];
b4ff3a36 7598 u8 reserved_at_10[0x10];
e281682b
SM		 7599
7600 u8 dic[0x1];
b4ff3a36 7601 u8 reserved_at_21[0x19];
e281682b 7602 u8 ipg[0x4];
b4ff3a36 7603 u8 reserved_at_3e[0x2];
e281682b
SM		 7604};
7605
7606struct mlx5_ifc_pifr_reg_bits {
b4ff3a36 7607 u8 reserved_at_0[0x8];
e281682b 7608 u8 local_port[0x8];
b4ff3a36 7609 u8 reserved_at_10[0x10];
e281682b 7610
b4ff3a36 7611 u8 reserved_at_20[0xe0];
e281682b
SM		 7612
7613 u8 port_filter[8][0x20];
7614
7615 u8 port_filter_update_en[8][0x20];
7616};
7617
7618struct mlx5_ifc_pfcc_reg_bits {
b4ff3a36 7619 u8 reserved_at_0[0x8];
e281682b 7620 u8 local_port[0x8];
b4ff3a36 7621 u8 reserved_at_10[0x10];
e281682b
SM		 7622
7623 u8 ppan[0x4];
b4ff3a36 7624 u8 reserved_at_24[0x4];
e281682b 7625 u8 prio_mask_tx[0x8];
b4ff3a36 7626 u8 reserved_at_30[0x8];
e281682b
SM		 7627 u8 prio_mask_rx[0x8];
7628
7629 u8 pptx[0x1];
7630 u8 aptx[0x1];
b4ff3a36 7631 u8 reserved_at_42[0x6];
e281682b 7632 u8 pfctx[0x8];
b4ff3a36 7633 u8 reserved_at_50[0x10];
e281682b
SM		 7634
7635 u8 pprx[0x1];
7636 u8 aprx[0x1];
b4ff3a36 7637 u8 reserved_at_62[0x6];
e281682b 7638 u8 pfcrx[0x8];
b4ff3a36 7639 u8 reserved_at_70[0x10];
e281682b 7640
b4ff3a36 7641 u8 reserved_at_80[0x80];
e281682b
SM		 7642};
7643
7644struct mlx5_ifc_pelc_reg_bits {
7645 u8 op[0x4];
b4ff3a36 7646 u8 reserved_at_4[0x4];
e281682b 7647 u8 local_port[0x8];
b4ff3a36 7648 u8 reserved_at_10[0x10];
e281682b
SM		 7649
7650 u8 op_admin[0x8];
7651 u8 op_capability[0x8];
7652 u8 op_request[0x8];
7653 u8 op_active[0x8];
7654
7655 u8 admin[0x40];
7656
7657 u8 capability[0x40];
7658
7659 u8 request[0x40];
7660
7661 u8 active[0x40];
7662
b4ff3a36 7663 u8 reserved_at_140[0x80];
e281682b
SM		 7664};
7665
7666struct mlx5_ifc_peir_reg_bits {
b4ff3a36 7667 u8 reserved_at_0[0x8];
e281682b 7668 u8 local_port[0x8];
b4ff3a36 7669 u8 reserved_at_10[0x10];
e281682b 7670
b4ff3a36 7671 u8 reserved_at_20[0xc];
e281682b 7672 u8 error_count[0x4];
b4ff3a36 7673 u8 reserved_at_30[0x10];
e281682b 7674
b4ff3a36 7675 u8 reserved_at_40[0xc];
e281682b 7676 u8 lane[0x4];
b4ff3a36 7677 u8 reserved_at_50[0x8];
e281682b
SM		 7678 u8 error_type[0x8];
7679};
7680
cfdcbcea
GP		 7681struct mlx5_ifc_pcam_enhanced_features_bits {
7682 u8 reserved_at_0[0x7e];
7683
7684 u8 ppcnt_discard_group[0x1];
7685 u8 ppcnt_statistical_group[0x1];
7686};
7687
7688struct mlx5_ifc_pcam_reg_bits {
7689 u8 reserved_at_0[0x8];
7690 u8 feature_group[0x8];
7691 u8 reserved_at_10[0x8];
7692 u8 access_reg_group[0x8];
7693
7694 u8 reserved_at_20[0x20];
7695
7696 union {
7697 u8 reserved_at_0[0x80];
7698 } port_access_reg_cap_mask;
7699
7700 u8 reserved_at_c0[0x80];
7701
7702 union {
7703 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
7704 u8 reserved_at_0[0x80];
7705 } feature_cap_mask;
7706
7707 u8 reserved_at_1c0[0xc0];
7708};
7709
7710struct mlx5_ifc_mcam_enhanced_features_bits {
7711 u8 reserved_at_0[0x7f];
7712
7713 u8 pcie_performance_group[0x1];
7714};
7715
7716struct mlx5_ifc_mcam_reg_bits {
7717 u8 reserved_at_0[0x8];
7718 u8 feature_group[0x8];
7719 u8 reserved_at_10[0x8];
7720 u8 access_reg_group[0x8];
7721
7722 u8 reserved_at_20[0x20];
7723
7724 union {
7725 u8 reserved_at_0[0x80];
7726 } mng_access_reg_cap_mask;
7727
7728 u8 reserved_at_c0[0x80];
7729
7730 union {
7731 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
7732 u8 reserved_at_0[0x80];
7733 } mng_feature_cap_mask;
7734
7735 u8 reserved_at_1c0[0x80];
7736};
7737
e281682b 7738struct mlx5_ifc_pcap_reg_bits {
b4ff3a36 7739 u8 reserved_at_0[0x8];
e281682b 7740 u8 local_port[0x8];
b4ff3a36 7741 u8 reserved_at_10[0x10];
e281682b
SM		 7742
7743 u8 port_capability_mask[4][0x20];
7744};
7745
7746struct mlx5_ifc_paos_reg_bits {
7747 u8 swid[0x8];
7748 u8 local_port[0x8];
b4ff3a36 7749 u8 reserved_at_10[0x4];
e281682b 7750 u8 admin_status[0x4];
b4ff3a36 7751 u8 reserved_at_18[0x4];
e281682b
SM		 7752 u8 oper_status[0x4];
7753
7754 u8 ase[0x1];
7755 u8 ee[0x1];
b4ff3a36 7756 u8 reserved_at_22[0x1c];
e281682b
SM		 7757 u8 e[0x2];
7758
b4ff3a36 7759 u8 reserved_at_40[0x40];
e281682b
SM		 7760};
7761
7762struct mlx5_ifc_pamp_reg_bits {
b4ff3a36 7763 u8 reserved_at_0[0x8];
e281682b 7764 u8 opamp_group[0x8];
b4ff3a36 7765 u8 reserved_at_10[0xc];
e281682b
SM		 7766 u8 opamp_group_type[0x4];
7767
7768 u8 start_index[0x10];
b4ff3a36 7769 u8 reserved_at_30[0x4];
e281682b
SM		 7770 u8 num_of_indices[0xc];
7771
7772 u8 index_data[18][0x10];
7773};
7774
7d5e1423
SM		 7775struct mlx5_ifc_pcmr_reg_bits {
7776 u8 reserved_at_0[0x8];
7777 u8 local_port[0x8];
7778 u8 reserved_at_10[0x2e];
7779 u8 fcs_cap[0x1];
7780 u8 reserved_at_3f[0x1f];
7781 u8 fcs_chk[0x1];
7782 u8 reserved_at_5f[0x1];
7783};
7784
e281682b 7785struct mlx5_ifc_lane_2_module_mapping_bits {
b4ff3a36 7786 u8 reserved_at_0[0x6];
e281682b 7787 u8 rx_lane[0x2];
b4ff3a36 7788 u8 reserved_at_8[0x6];
e281682b 7789 u8 tx_lane[0x2];
b4ff3a36 7790 u8 reserved_at_10[0x8];
e281682b
SM		 7791 u8 module[0x8];
7792};
7793
7794struct mlx5_ifc_bufferx_reg_bits {
b4ff3a36 7795 u8 reserved_at_0[0x6];
e281682b
SM		 7796 u8 lossy[0x1];
7797 u8 epsb[0x1];
b4ff3a36 7798 u8 reserved_at_8[0xc];
e281682b
SM		 7799 u8 size[0xc];
7800
7801 u8 xoff_threshold[0x10];
7802 u8 xon_threshold[0x10];
7803};
7804
7805struct mlx5_ifc_set_node_in_bits {
7806 u8 node_description[64][0x8];
7807};
7808
7809struct mlx5_ifc_register_power_settings_bits {
b4ff3a36 7810 u8 reserved_at_0[0x18];
e281682b
SM		 7811 u8 power_settings_level[0x8];
7812
b4ff3a36 7813 u8 reserved_at_20[0x60];
e281682b
SM		 7814};
7815
7816struct mlx5_ifc_register_host_endianness_bits {
7817 u8 he[0x1];
b4ff3a36 7818 u8 reserved_at_1[0x1f];
e281682b 7819
b4ff3a36 7820 u8 reserved_at_20[0x60];
e281682b
SM		 7821};
7822
7823struct mlx5_ifc_umr_pointer_desc_argument_bits {
b4ff3a36 7824 u8 reserved_at_0[0x20];
e281682b
SM		 7825
7826 u8 mkey[0x20];
7827
7828 u8 addressh_63_32[0x20];
7829
7830 u8 addressl_31_0[0x20];
7831};
7832
7833struct mlx5_ifc_ud_adrs_vector_bits {
7834 u8 dc_key[0x40];
7835
7836 u8 ext[0x1];
b4ff3a36 7837 u8 reserved_at_41[0x7];
e281682b
SM		 7838 u8 destination_qp_dct[0x18];
7839
7840 u8 static_rate[0x4];
7841 u8 sl_eth_prio[0x4];
7842 u8 fl[0x1];
7843 u8 mlid[0x7];
7844 u8 rlid_udp_sport[0x10];
7845
b4ff3a36 7846 u8 reserved_at_80[0x20];
e281682b
SM		 7847
7848 u8 rmac_47_16[0x20];
7849
7850 u8 rmac_15_0[0x10];
7851 u8 tclass[0x8];
7852 u8 hop_limit[0x8];
7853
b4ff3a36 7854 u8 reserved_at_e0[0x1];
e281682b 7855 u8 grh[0x1];
b4ff3a36 7856 u8 reserved_at_e2[0x2];
e281682b
SM		 7857 u8 src_addr_index[0x8];
7858 u8 flow_label[0x14];
7859
7860 u8 rgid_rip[16][0x8];
7861};
7862
7863struct mlx5_ifc_pages_req_event_bits {
b4ff3a36 7864 u8 reserved_at_0[0x10];
e281682b
SM		 7865 u8 function_id[0x10];
7866
7867 u8 num_pages[0x20];
7868
b4ff3a36 7869 u8 reserved_at_40[0xa0];
e281682b
SM		 7870};
7871
7872struct mlx5_ifc_eqe_bits {
b4ff3a36 7873 u8 reserved_at_0[0x8];
e281682b 7874 u8 event_type[0x8];
b4ff3a36 7875 u8 reserved_at_10[0x8];
e281682b
SM		 7876 u8 event_sub_type[0x8];
7877
b4ff3a36 7878 u8 reserved_at_20[0xe0];
e281682b
SM		 7879
7880 union mlx5_ifc_event_auto_bits event_data;
7881
b4ff3a36 7882 u8 reserved_at_1e0[0x10];
e281682b 7883 u8 signature[0x8];
b4ff3a36 7884 u8 reserved_at_1f8[0x7];
e281682b
SM		 7885 u8 owner[0x1];
7886};
7887
7888enum {
7889 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
7890};
7891
7892struct mlx5_ifc_cmd_queue_entry_bits {
7893 u8 type[0x8];
b4ff3a36 7894 u8 reserved_at_8[0x18];
e281682b
SM		 7895
7896 u8 input_length[0x20];
7897
7898 u8 input_mailbox_pointer_63_32[0x20];
7899
7900 u8 input_mailbox_pointer_31_9[0x17];
b4ff3a36 7901 u8 reserved_at_77[0x9];
e281682b
SM		 7902
7903 u8 command_input_inline_data[16][0x8];
7904
7905 u8 command_output_inline_data[16][0x8];
7906
7907 u8 output_mailbox_pointer_63_32[0x20];
7908
7909 u8 output_mailbox_pointer_31_9[0x17];
b4ff3a36 7910 u8 reserved_at_1b7[0x9];
e281682b
SM		 7911
7912 u8 output_length[0x20];
7913
7914 u8 token[0x8];
7915 u8 signature[0x8];
b4ff3a36 7916 u8 reserved_at_1f0[0x8];
e281682b
SM		 7917 u8 status[0x7];
7918 u8 ownership[0x1];
7919};
7920
7921struct mlx5_ifc_cmd_out_bits {
7922 u8 status[0x8];
b4ff3a36 7923 u8 reserved_at_8[0x18];
e281682b
SM		 7924
7925 u8 syndrome[0x20];
7926
7927 u8 command_output[0x20];
7928};
7929
7930struct mlx5_ifc_cmd_in_bits {
7931 u8 opcode[0x10];
b4ff3a36 7932 u8 reserved_at_10[0x10];
e281682b 7933
b4ff3a36 7934 u8 reserved_at_20[0x10];
e281682b
SM		 7935 u8 op_mod[0x10];
7936
7937 u8 command[0][0x20];
7938};
7939
7940struct mlx5_ifc_cmd_if_box_bits {
7941 u8 mailbox_data[512][0x8];
7942
b4ff3a36 7943 u8 reserved_at_1000[0x180];
e281682b
SM		 7944
7945 u8 next_pointer_63_32[0x20];
7946
7947 u8 next_pointer_31_10[0x16];
b4ff3a36 7948 u8 reserved_at_11b6[0xa];
e281682b
SM		 7949
7950 u8 block_number[0x20];
7951
b4ff3a36 7952 u8 reserved_at_11e0[0x8];
e281682b
SM		 7953 u8 token[0x8];
7954 u8 ctrl_signature[0x8];
7955 u8 signature[0x8];
7956};
7957
7958struct mlx5_ifc_mtt_bits {
7959 u8 ptag_63_32[0x20];
7960
7961 u8 ptag_31_8[0x18];
b4ff3a36 7962 u8 reserved_at_38[0x6];
e281682b
SM		 7963 u8 wr_en[0x1];
7964 u8 rd_en[0x1];
7965};
7966
928cfe87
TT		 7967struct mlx5_ifc_query_wol_rol_out_bits {
7968 u8 status[0x8];
7969 u8 reserved_at_8[0x18];
7970
7971 u8 syndrome[0x20];
7972
7973 u8 reserved_at_40[0x10];
7974 u8 rol_mode[0x8];
7975 u8 wol_mode[0x8];
7976
7977 u8 reserved_at_60[0x20];
7978};
7979
7980struct mlx5_ifc_query_wol_rol_in_bits {
7981 u8 opcode[0x10];
7982 u8 reserved_at_10[0x10];
7983
7984 u8 reserved_at_20[0x10];
7985 u8 op_mod[0x10];
7986
7987 u8 reserved_at_40[0x40];
7988};
7989
7990struct mlx5_ifc_set_wol_rol_out_bits {
7991 u8 status[0x8];
7992 u8 reserved_at_8[0x18];
7993
7994 u8 syndrome[0x20];
7995
7996 u8 reserved_at_40[0x40];
7997};
7998
7999struct mlx5_ifc_set_wol_rol_in_bits {
8000 u8 opcode[0x10];
8001 u8 reserved_at_10[0x10];
8002
8003 u8 reserved_at_20[0x10];
8004 u8 op_mod[0x10];
8005
8006 u8 rol_mode_valid[0x1];
8007 u8 wol_mode_valid[0x1];
8008 u8 reserved_at_42[0xe];
8009 u8 rol_mode[0x8];
8010 u8 wol_mode[0x8];
8011
8012 u8 reserved_at_60[0x20];
8013};
8014
e281682b
SM		 8015enum {
8016 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
8017 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
8018 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
8019};
8020
8021enum {
8022 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
8023 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
8024 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
8025};
8026
8027enum {
8028 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
8029 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
8030 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
8031 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
8032 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
8033 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
8034 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
8035 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
8036 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
8037 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
8038 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
8039};
8040
8041struct mlx5_ifc_initial_seg_bits {
8042 u8 fw_rev_minor[0x10];
8043 u8 fw_rev_major[0x10];
8044
8045 u8 cmd_interface_rev[0x10];
8046 u8 fw_rev_subminor[0x10];
8047
b4ff3a36 8048 u8 reserved_at_40[0x40];
e281682b
SM		 8049
8050 u8 cmdq_phy_addr_63_32[0x20];
8051
8052 u8 cmdq_phy_addr_31_12[0x14];
b4ff3a36 8053 u8 reserved_at_b4[0x2];
e281682b
SM		 8054 u8 nic_interface[0x2];
8055 u8 log_cmdq_size[0x4];
8056 u8 log_cmdq_stride[0x4];
8057
8058 u8 command_doorbell_vector[0x20];
8059
b4ff3a36 8060 u8 reserved_at_e0[0xf00];
e281682b
SM		 8061
8062 u8 initializing[0x1];
b4ff3a36 8063 u8 reserved_at_fe1[0x4];
e281682b 8064 u8 nic_interface_supported[0x3];
b4ff3a36 8065 u8 reserved_at_fe8[0x18];
e281682b
SM		 8066
8067 struct mlx5_ifc_health_buffer_bits health_buffer;
8068
8069 u8 no_dram_nic_offset[0x20];
8070
b4ff3a36 8071 u8 reserved_at_1220[0x6e40];
e281682b 8072
b4ff3a36 8073 u8 reserved_at_8060[0x1f];
e281682b
SM		 8074 u8 clear_int[0x1];
8075
8076 u8 health_syndrome[0x8];
8077 u8 health_counter[0x18];
8078
b4ff3a36 8079 u8 reserved_at_80a0[0x17fc0];
e281682b
SM		 8080};
8081
f9a1ef72
EE		 8082struct mlx5_ifc_mtpps_reg_bits {
8083 u8 reserved_at_0[0xc];
8084 u8 cap_number_of_pps_pins[0x4];
8085 u8 reserved_at_10[0x4];
8086 u8 cap_max_num_of_pps_in_pins[0x4];
8087 u8 reserved_at_18[0x4];
8088 u8 cap_max_num_of_pps_out_pins[0x4];
8089
8090 u8 reserved_at_20[0x24];
8091 u8 cap_pin_3_mode[0x4];
8092 u8 reserved_at_48[0x4];
8093 u8 cap_pin_2_mode[0x4];
8094 u8 reserved_at_50[0x4];
8095 u8 cap_pin_1_mode[0x4];
8096 u8 reserved_at_58[0x4];
8097 u8 cap_pin_0_mode[0x4];
8098
8099 u8 reserved_at_60[0x4];
8100 u8 cap_pin_7_mode[0x4];
8101 u8 reserved_at_68[0x4];
8102 u8 cap_pin_6_mode[0x4];
8103 u8 reserved_at_70[0x4];
8104 u8 cap_pin_5_mode[0x4];
8105 u8 reserved_at_78[0x4];
8106 u8 cap_pin_4_mode[0x4];
8107
8108 u8 reserved_at_80[0x80];
8109
8110 u8 enable[0x1];
8111 u8 reserved_at_101[0xb];
8112 u8 pattern[0x4];
8113 u8 reserved_at_110[0x4];
8114 u8 pin_mode[0x4];
8115 u8 pin[0x8];
8116
8117 u8 reserved_at_120[0x20];
8118
8119 u8 time_stamp[0x40];
8120
8121 u8 out_pulse_duration[0x10];
8122 u8 out_periodic_adjustment[0x10];
8123
8124 u8 reserved_at_1a0[0x60];
8125};
8126
8127struct mlx5_ifc_mtppse_reg_bits {
8128 u8 reserved_at_0[0x18];
8129 u8 pin[0x8];
8130 u8 event_arm[0x1];
8131 u8 reserved_at_21[0x1b];
8132 u8 event_generation_mode[0x4];
8133 u8 reserved_at_40[0x40];
8134};
8135
e281682b
SM		 8136union mlx5_ifc_ports_control_registers_document_bits {
8137 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
8138 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
8139 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
8140 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
8141 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
8142 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
8143 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
8144 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
8145 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
8146 struct mlx5_ifc_pamp_reg_bits pamp_reg;
8147 struct mlx5_ifc_paos_reg_bits paos_reg;
8148 struct mlx5_ifc_pcap_reg_bits pcap_reg;
8149 struct mlx5_ifc_peir_reg_bits peir_reg;
8150 struct mlx5_ifc_pelc_reg_bits pelc_reg;
8151 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
1c64bf6f 8152 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b
SM		 8153 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
8154 struct mlx5_ifc_pifr_reg_bits pifr_reg;
8155 struct mlx5_ifc_pipg_reg_bits pipg_reg;
8156 struct mlx5_ifc_plbf_reg_bits plbf_reg;
8157 struct mlx5_ifc_plib_reg_bits plib_reg;
8158 struct mlx5_ifc_plpc_reg_bits plpc_reg;
8159 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
8160 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
8161 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
8162 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
8163 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
8164 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
8165 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
8166 struct mlx5_ifc_ppad_reg_bits ppad_reg;
8167 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
8ed1a630 8168 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
e281682b
SM		 8169 struct mlx5_ifc_pplm_reg_bits pplm_reg;
8170 struct mlx5_ifc_pplr_reg_bits pplr_reg;
8171 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
8172 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
8173 struct mlx5_ifc_pspa_reg_bits pspa_reg;
8174 struct mlx5_ifc_ptas_reg_bits ptas_reg;
8175 struct mlx5_ifc_ptys_reg_bits ptys_reg;
7d5e1423 8176 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
e281682b
SM		 8177 struct mlx5_ifc_pude_reg_bits pude_reg;
8178 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
8179 struct mlx5_ifc_slrg_reg_bits slrg_reg;
8180 struct mlx5_ifc_sltp_reg_bits sltp_reg;
f9a1ef72
EE		 8181 struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
8182 struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
b4ff3a36 8183 u8 reserved_at_0[0x60e0];
e281682b
SM		 8184};
8185
8186union mlx5_ifc_debug_enhancements_document_bits {
8187 struct mlx5_ifc_health_buffer_bits health_buffer;
b4ff3a36 8188 u8 reserved_at_0[0x200];
e281682b
SM		 8189};
8190
8191union mlx5_ifc_uplink_pci_interface_document_bits {
8192 struct mlx5_ifc_initial_seg_bits initial_seg;
b4ff3a36 8193 u8 reserved_at_0[0x20060];
b775516b
EC		 8194};
8195
2cc43b49
MG		 8196struct mlx5_ifc_set_flow_table_root_out_bits {
8197 u8 status[0x8];
b4ff3a36 8198 u8 reserved_at_8[0x18];
2cc43b49
MG		 8199
8200 u8 syndrome[0x20];
8201
b4ff3a36 8202 u8 reserved_at_40[0x40];
2cc43b49
MG		 8203};
8204
8205struct mlx5_ifc_set_flow_table_root_in_bits {
8206 u8 opcode[0x10];
b4ff3a36 8207 u8 reserved_at_10[0x10];
2cc43b49 8208
b4ff3a36 8209 u8 reserved_at_20[0x10];
2cc43b49
MG		 8210 u8 op_mod[0x10];
8211
7d5e1423
SM		 8212 u8 other_vport[0x1];
8213 u8 reserved_at_41[0xf];
8214 u8 vport_number[0x10];
8215
8216 u8 reserved_at_60[0x20];
2cc43b49
MG		 8217
8218 u8 table_type[0x8];
b4ff3a36 8219 u8 reserved_at_88[0x18];
2cc43b49 8220
b4ff3a36 8221 u8 reserved_at_a0[0x8];
2cc43b49
MG		 8222 u8 table_id[0x18];
8223
500a3d0d
ES		 8224 u8 reserved_at_c0[0x8];
8225 u8 underlay_qpn[0x18];
8226 u8 reserved_at_e0[0x120];
2cc43b49
MG		 8227};
8228
34a40e68 8229enum {
84df61eb
AH		 8230 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
8231 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
34a40e68
MG		 8232};
8233
8234struct mlx5_ifc_modify_flow_table_out_bits {
8235 u8 status[0x8];
b4ff3a36 8236 u8 reserved_at_8[0x18];
34a40e68
MG		 8237
8238 u8 syndrome[0x20];
8239
b4ff3a36 8240 u8 reserved_at_40[0x40];
34a40e68
MG		 8241};
8242
8243struct mlx5_ifc_modify_flow_table_in_bits {
8244 u8 opcode[0x10];
b4ff3a36 8245 u8 reserved_at_10[0x10];
34a40e68 8246
b4ff3a36 8247 u8 reserved_at_20[0x10];
34a40e68
MG		 8248 u8 op_mod[0x10];
8249
7d5e1423
SM		 8250 u8 other_vport[0x1];
8251 u8 reserved_at_41[0xf];
8252 u8 vport_number[0x10];
34a40e68 8253
b4ff3a36 8254 u8 reserved_at_60[0x10];
34a40e68
MG		 8255 u8 modify_field_select[0x10];
8256
8257 u8 table_type[0x8];
b4ff3a36 8258 u8 reserved_at_88[0x18];
34a40e68 8259
b4ff3a36 8260 u8 reserved_at_a0[0x8];
34a40e68
MG		 8261 u8 table_id[0x18];
8262
b4ff3a36 8263 u8 reserved_at_c0[0x4];
34a40e68 8264 u8 table_miss_mode[0x4];
b4ff3a36 8265 u8 reserved_at_c8[0x18];
34a40e68 8266
b4ff3a36 8267 u8 reserved_at_e0[0x8];
34a40e68
MG		 8268 u8 table_miss_id[0x18];
8269
84df61eb
AH		 8270 u8 reserved_at_100[0x8];
8271 u8 lag_master_next_table_id[0x18];
8272
8273 u8 reserved_at_120[0x80];
34a40e68
MG		 8274};
8275
4f3961ee
SM		 8276struct mlx5_ifc_ets_tcn_config_reg_bits {
8277 u8 g[0x1];
8278 u8 b[0x1];
8279 u8 r[0x1];
8280 u8 reserved_at_3[0x9];
8281 u8 group[0x4];
8282 u8 reserved_at_10[0x9];
8283 u8 bw_allocation[0x7];
8284
8285 u8 reserved_at_20[0xc];
8286 u8 max_bw_units[0x4];
8287 u8 reserved_at_30[0x8];
8288 u8 max_bw_value[0x8];
8289};
8290
8291struct mlx5_ifc_ets_global_config_reg_bits {
8292 u8 reserved_at_0[0x2];
8293 u8 r[0x1];
8294 u8 reserved_at_3[0x1d];
8295
8296 u8 reserved_at_20[0xc];
8297 u8 max_bw_units[0x4];
8298 u8 reserved_at_30[0x8];
8299 u8 max_bw_value[0x8];
8300};
8301
8302struct mlx5_ifc_qetc_reg_bits {
8303 u8 reserved_at_0[0x8];
8304 u8 port_number[0x8];
8305 u8 reserved_at_10[0x30];
8306
8307 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
8308 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
8309};
8310
8311struct mlx5_ifc_qtct_reg_bits {
8312 u8 reserved_at_0[0x8];
8313 u8 port_number[0x8];
8314 u8 reserved_at_10[0xd];
8315 u8 prio[0x3];
8316
8317 u8 reserved_at_20[0x1d];
8318 u8 tclass[0x3];
8319};
8320
7d5e1423
SM		 8321struct mlx5_ifc_mcia_reg_bits {
8322 u8 l[0x1];
8323 u8 reserved_at_1[0x7];
8324 u8 module[0x8];
8325 u8 reserved_at_10[0x8];
8326 u8 status[0x8];
8327
8328 u8 i2c_device_address[0x8];
8329 u8 page_number[0x8];
8330 u8 device_address[0x10];
8331
8332 u8 reserved_at_40[0x10];
8333 u8 size[0x10];
8334
8335 u8 reserved_at_60[0x20];
8336
8337 u8 dword_0[0x20];
8338 u8 dword_1[0x20];
8339 u8 dword_2[0x20];
8340 u8 dword_3[0x20];
8341 u8 dword_4[0x20];
8342 u8 dword_5[0x20];
8343 u8 dword_6[0x20];
8344 u8 dword_7[0x20];
8345 u8 dword_8[0x20];
8346 u8 dword_9[0x20];
8347 u8 dword_10[0x20];
8348 u8 dword_11[0x20];
8349};
8350
7486216b
SM		 8351struct mlx5_ifc_dcbx_param_bits {
8352 u8 dcbx_cee_cap[0x1];
8353 u8 dcbx_ieee_cap[0x1];
8354 u8 dcbx_standby_cap[0x1];
8355 u8 reserved_at_0[0x5];
8356 u8 port_number[0x8];
8357 u8 reserved_at_10[0xa];
8358 u8 max_application_table_size[6];
8359 u8 reserved_at_20[0x15];
8360 u8 version_oper[0x3];
8361 u8 reserved_at_38[5];
8362 u8 version_admin[0x3];
8363 u8 willing_admin[0x1];
8364 u8 reserved_at_41[0x3];
8365 u8 pfc_cap_oper[0x4];
8366 u8 reserved_at_48[0x4];
8367 u8 pfc_cap_admin[0x4];
8368 u8 reserved_at_50[0x4];
8369 u8 num_of_tc_oper[0x4];
8370 u8 reserved_at_58[0x4];
8371 u8 num_of_tc_admin[0x4];
8372 u8 remote_willing[0x1];
8373 u8 reserved_at_61[3];
8374 u8 remote_pfc_cap[4];
8375 u8 reserved_at_68[0x14];
8376 u8 remote_num_of_tc[0x4];
8377 u8 reserved_at_80[0x18];
8378 u8 error[0x8];
8379 u8 reserved_at_a0[0x160];
8380};
84df61eb
AH		 8381
8382struct mlx5_ifc_lagc_bits {
8383 u8 reserved_at_0[0x1d];
8384 u8 lag_state[0x3];
8385
8386 u8 reserved_at_20[0x14];
8387 u8 tx_remap_affinity_2[0x4];
8388 u8 reserved_at_38[0x4];
8389 u8 tx_remap_affinity_1[0x4];
8390};
8391
8392struct mlx5_ifc_create_lag_out_bits {
8393 u8 status[0x8];
8394 u8 reserved_at_8[0x18];
8395
8396 u8 syndrome[0x20];
8397
8398 u8 reserved_at_40[0x40];
8399};
8400
8401struct mlx5_ifc_create_lag_in_bits {
8402 u8 opcode[0x10];
8403 u8 reserved_at_10[0x10];
8404
8405 u8 reserved_at_20[0x10];
8406 u8 op_mod[0x10];
8407
8408 struct mlx5_ifc_lagc_bits ctx;
8409};
8410
8411struct mlx5_ifc_modify_lag_out_bits {
8412 u8 status[0x8];
8413 u8 reserved_at_8[0x18];
8414
8415 u8 syndrome[0x20];
8416
8417 u8 reserved_at_40[0x40];
8418};
8419
8420struct mlx5_ifc_modify_lag_in_bits {
8421 u8 opcode[0x10];
8422 u8 reserved_at_10[0x10];
8423
8424 u8 reserved_at_20[0x10];
8425 u8 op_mod[0x10];
8426
8427 u8 reserved_at_40[0x20];
8428 u8 field_select[0x20];
8429
8430 struct mlx5_ifc_lagc_bits ctx;
8431};
8432
8433struct mlx5_ifc_query_lag_out_bits {
8434 u8 status[0x8];
8435 u8 reserved_at_8[0x18];
8436
8437 u8 syndrome[0x20];
8438
8439 u8 reserved_at_40[0x40];
8440
8441 struct mlx5_ifc_lagc_bits ctx;
8442};
8443
8444struct mlx5_ifc_query_lag_in_bits {
8445 u8 opcode[0x10];
8446 u8 reserved_at_10[0x10];
8447
8448 u8 reserved_at_20[0x10];
8449 u8 op_mod[0x10];
8450
8451 u8 reserved_at_40[0x40];
8452};
8453
8454struct mlx5_ifc_destroy_lag_out_bits {
8455 u8 status[0x8];
8456 u8 reserved_at_8[0x18];
8457
8458 u8 syndrome[0x20];
8459
8460 u8 reserved_at_40[0x40];
8461};
8462
8463struct mlx5_ifc_destroy_lag_in_bits {
8464 u8 opcode[0x10];
8465 u8 reserved_at_10[0x10];
8466
8467 u8 reserved_at_20[0x10];
8468 u8 op_mod[0x10];
8469
8470 u8 reserved_at_40[0x40];
8471};
8472
8473struct mlx5_ifc_create_vport_lag_out_bits {
8474 u8 status[0x8];
8475 u8 reserved_at_8[0x18];
8476
8477 u8 syndrome[0x20];
8478
8479 u8 reserved_at_40[0x40];
8480};
8481
8482struct mlx5_ifc_create_vport_lag_in_bits {
8483 u8 opcode[0x10];
8484 u8 reserved_at_10[0x10];
8485
8486 u8 reserved_at_20[0x10];
8487 u8 op_mod[0x10];
8488
8489 u8 reserved_at_40[0x40];
8490};
8491
8492struct mlx5_ifc_destroy_vport_lag_out_bits {
8493 u8 status[0x8];
8494 u8 reserved_at_8[0x18];
8495
8496 u8 syndrome[0x20];
8497
8498 u8 reserved_at_40[0x40];
8499};
8500
8501struct mlx5_ifc_destroy_vport_lag_in_bits {
8502 u8 opcode[0x10];
8503 u8 reserved_at_10[0x10];
8504
8505 u8 reserved_at_20[0x10];
8506 u8 op_mod[0x10];
8507
8508 u8 reserved_at_40[0x40];
8509};
8510
d29b796a 8511#endif /* MLX5_IFC_H */
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