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net/mlx5: Fix static checker warnings
[mirror_ubuntu-artful-kernel.git] / include / linux / mlx5 / mlx5_ifc.h
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d29b796a 1/*
e281682b 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
d29b796a
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
e281682b 31*/
d29b796a
EC		 32#ifndef MLX5_IFC_H
33#define MLX5_IFC_H
34
e281682b
SM		 35enum {
36 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
37 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
38 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
39 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
40 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
41 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
42 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
43 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
44 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
45 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
46 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
47 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
48 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
49 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
50 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
51 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
52 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
53 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
54 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
55 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
56 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
57 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
58 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
59 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb
60};
61
62enum {
63 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
64 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
65 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
66 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
67};
68
f91e6d89
EBE		 69enum {
70 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
71 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
72};
73
d29b796a
EC		 74enum {
75 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
76 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
77 MLX5_CMD_OP_INIT_HCA = 0x102,
78 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
79 MLX5_CMD_OP_ENABLE_HCA = 0x104,
80 MLX5_CMD_OP_DISABLE_HCA = 0x105,
81 MLX5_CMD_OP_QUERY_PAGES = 0x107,
82 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
83 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
e281682b
SM		 84 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
85 MLX5_CMD_OP_SET_ISSI = 0x10b,
0dbc6fe0 86 MLX5_CMD_OP_SET_DRIVER_VERSION = 0x10d,
d29b796a
EC		 87 MLX5_CMD_OP_CREATE_MKEY = 0x200,
88 MLX5_CMD_OP_QUERY_MKEY = 0x201,
89 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
90 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
91 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
92 MLX5_CMD_OP_CREATE_EQ = 0x301,
93 MLX5_CMD_OP_DESTROY_EQ = 0x302,
94 MLX5_CMD_OP_QUERY_EQ = 0x303,
95 MLX5_CMD_OP_GEN_EQE = 0x304,
96 MLX5_CMD_OP_CREATE_CQ = 0x400,
97 MLX5_CMD_OP_DESTROY_CQ = 0x401,
98 MLX5_CMD_OP_QUERY_CQ = 0x402,
99 MLX5_CMD_OP_MODIFY_CQ = 0x403,
100 MLX5_CMD_OP_CREATE_QP = 0x500,
101 MLX5_CMD_OP_DESTROY_QP = 0x501,
102 MLX5_CMD_OP_RST2INIT_QP = 0x502,
103 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
104 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
105 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
106 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
107 MLX5_CMD_OP_2ERR_QP = 0x507,
108 MLX5_CMD_OP_2RST_QP = 0x50a,
109 MLX5_CMD_OP_QUERY_QP = 0x50b,
e281682b 110 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
d29b796a
EC		 111 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
112 MLX5_CMD_OP_CREATE_PSV = 0x600,
113 MLX5_CMD_OP_DESTROY_PSV = 0x601,
114 MLX5_CMD_OP_CREATE_SRQ = 0x700,
115 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
116 MLX5_CMD_OP_QUERY_SRQ = 0x702,
117 MLX5_CMD_OP_ARM_RQ = 0x703,
e281682b
SM		 118 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
119 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
120 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
121 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
d29b796a
EC		 122 MLX5_CMD_OP_CREATE_DCT = 0x710,
123 MLX5_CMD_OP_DESTROY_DCT = 0x711,
124 MLX5_CMD_OP_DRAIN_DCT = 0x712,
125 MLX5_CMD_OP_QUERY_DCT = 0x713,
126 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
7486216b
SM		 127 MLX5_CMD_OP_CREATE_XRQ = 0x717,
128 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
129 MLX5_CMD_OP_QUERY_XRQ = 0x719,
130 MLX5_CMD_OP_ARM_XRQ = 0x71a,
d29b796a
EC		 131 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
132 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
133 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
134 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
135 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
136 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
e281682b 137 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
d29b796a 138 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
e281682b
SM		 139 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
140 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
141 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
142 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
d29b796a
EC		 143 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
144 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
145 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
146 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
7486216b
SM		 147 MLX5_CMD_OP_SET_RATE_LIMIT = 0x780,
148 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
813f8540
MHY		 149 MLX5_CMD_OP_CREATE_SCHEDULING_ELEMENT = 0x782,
150 MLX5_CMD_OP_DESTROY_SCHEDULING_ELEMENT = 0x783,
151 MLX5_CMD_OP_QUERY_SCHEDULING_ELEMENT = 0x784,
152 MLX5_CMD_OP_MODIFY_SCHEDULING_ELEMENT = 0x785,
153 MLX5_CMD_OP_CREATE_QOS_PARA_VPORT = 0x786,
154 MLX5_CMD_OP_DESTROY_QOS_PARA_VPORT = 0x787,
d29b796a
EC		 155 MLX5_CMD_OP_ALLOC_PD = 0x800,
156 MLX5_CMD_OP_DEALLOC_PD = 0x801,
157 MLX5_CMD_OP_ALLOC_UAR = 0x802,
158 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
159 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
160 MLX5_CMD_OP_ACCESS_REG = 0x805,
161 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
20bb566b 162 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
d29b796a
EC		 163 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
164 MLX5_CMD_OP_MAD_IFC = 0x50d,
165 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
166 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
167 MLX5_CMD_OP_NOP = 0x80d,
168 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
169 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
e281682b
SM		 170 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
171 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
172 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
173 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
174 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
175 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
176 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
177 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
178 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
179 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
180 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
181 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
928cfe87
TT		 182 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
183 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
84df61eb
AH		 184 MLX5_CMD_OP_CREATE_LAG = 0x840,
185 MLX5_CMD_OP_MODIFY_LAG = 0x841,
186 MLX5_CMD_OP_QUERY_LAG = 0x842,
187 MLX5_CMD_OP_DESTROY_LAG = 0x843,
188 MLX5_CMD_OP_CREATE_VPORT_LAG = 0x844,
189 MLX5_CMD_OP_DESTROY_VPORT_LAG = 0x845,
d29b796a
EC		 190 MLX5_CMD_OP_CREATE_TIR = 0x900,
191 MLX5_CMD_OP_MODIFY_TIR = 0x901,
192 MLX5_CMD_OP_DESTROY_TIR = 0x902,
193 MLX5_CMD_OP_QUERY_TIR = 0x903,
d29b796a
EC		 194 MLX5_CMD_OP_CREATE_SQ = 0x904,
195 MLX5_CMD_OP_MODIFY_SQ = 0x905,
196 MLX5_CMD_OP_DESTROY_SQ = 0x906,
197 MLX5_CMD_OP_QUERY_SQ = 0x907,
198 MLX5_CMD_OP_CREATE_RQ = 0x908,
199 MLX5_CMD_OP_MODIFY_RQ = 0x909,
200 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
201 MLX5_CMD_OP_QUERY_RQ = 0x90b,
202 MLX5_CMD_OP_CREATE_RMP = 0x90c,
203 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
204 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
205 MLX5_CMD_OP_QUERY_RMP = 0x90f,
e281682b
SM		 206 MLX5_CMD_OP_CREATE_TIS = 0x912,
207 MLX5_CMD_OP_MODIFY_TIS = 0x913,
208 MLX5_CMD_OP_DESTROY_TIS = 0x914,
209 MLX5_CMD_OP_QUERY_TIS = 0x915,
210 MLX5_CMD_OP_CREATE_RQT = 0x916,
211 MLX5_CMD_OP_MODIFY_RQT = 0x917,
212 MLX5_CMD_OP_DESTROY_RQT = 0x918,
213 MLX5_CMD_OP_QUERY_RQT = 0x919,
2cc43b49 214 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
e281682b
SM		 215 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
216 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
217 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
218 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
219 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
220 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
221 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
222 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
34a40e68 223 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
9dc0b289
AV		 224 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
225 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
226 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
86d56a1a 227 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
7adbde20
HHZ		 228 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d,
229 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e,
86d56a1a 230 MLX5_CMD_OP_MAX
e281682b
SM		 231};
232
233struct mlx5_ifc_flow_table_fields_supported_bits {
234 u8 outer_dmac[0x1];
235 u8 outer_smac[0x1];
236 u8 outer_ether_type[0x1];
b4ff3a36 237 u8 reserved_at_3[0x1];
e281682b
SM		 238 u8 outer_first_prio[0x1];
239 u8 outer_first_cfi[0x1];
240 u8 outer_first_vid[0x1];
b4ff3a36 241 u8 reserved_at_7[0x1];
e281682b
SM		 242 u8 outer_second_prio[0x1];
243 u8 outer_second_cfi[0x1];
244 u8 outer_second_vid[0x1];
b4ff3a36 245 u8 reserved_at_b[0x1];
e281682b
SM		 246 u8 outer_sip[0x1];
247 u8 outer_dip[0x1];
248 u8 outer_frag[0x1];
249 u8 outer_ip_protocol[0x1];
250 u8 outer_ip_ecn[0x1];
251 u8 outer_ip_dscp[0x1];
252 u8 outer_udp_sport[0x1];
253 u8 outer_udp_dport[0x1];
254 u8 outer_tcp_sport[0x1];
255 u8 outer_tcp_dport[0x1];
256 u8 outer_tcp_flags[0x1];
257 u8 outer_gre_protocol[0x1];
258 u8 outer_gre_key[0x1];
259 u8 outer_vxlan_vni[0x1];
b4ff3a36 260 u8 reserved_at_1a[0x5];
e281682b
SM		 261 u8 source_eswitch_port[0x1];
262
263 u8 inner_dmac[0x1];
264 u8 inner_smac[0x1];
265 u8 inner_ether_type[0x1];
b4ff3a36 266 u8 reserved_at_23[0x1];
e281682b
SM		 267 u8 inner_first_prio[0x1];
268 u8 inner_first_cfi[0x1];
269 u8 inner_first_vid[0x1];
b4ff3a36 270 u8 reserved_at_27[0x1];
e281682b
SM		 271 u8 inner_second_prio[0x1];
272 u8 inner_second_cfi[0x1];
273 u8 inner_second_vid[0x1];
b4ff3a36 274 u8 reserved_at_2b[0x1];
e281682b
SM		 275 u8 inner_sip[0x1];
276 u8 inner_dip[0x1];
277 u8 inner_frag[0x1];
278 u8 inner_ip_protocol[0x1];
279 u8 inner_ip_ecn[0x1];
280 u8 inner_ip_dscp[0x1];
281 u8 inner_udp_sport[0x1];
282 u8 inner_udp_dport[0x1];
283 u8 inner_tcp_sport[0x1];
284 u8 inner_tcp_dport[0x1];
285 u8 inner_tcp_flags[0x1];
b4ff3a36 286 u8 reserved_at_37[0x9];
e281682b 287
b4ff3a36 288 u8 reserved_at_40[0x40];
e281682b
SM		 289};
290
291struct mlx5_ifc_flow_table_prop_layout_bits {
292 u8 ft_support[0x1];
9dc0b289
AV		 293 u8 reserved_at_1[0x1];
294 u8 flow_counter[0x1];
26a81453 295 u8 flow_modify_en[0x1];
2cc43b49 296 u8 modify_root[0x1];
34a40e68
MG		 297 u8 identified_miss_table_mode[0x1];
298 u8 flow_table_modify[0x1];
7adbde20
HHZ		 299 u8 encap[0x1];
300 u8 decap[0x1];
301 u8 reserved_at_9[0x17];
e281682b 302
b4ff3a36 303 u8 reserved_at_20[0x2];
e281682b 304 u8 log_max_ft_size[0x6];
b4ff3a36 305 u8 reserved_at_28[0x10];
e281682b
SM		 306 u8 max_ft_level[0x8];
307
b4ff3a36 308 u8 reserved_at_40[0x20];
e281682b 309
b4ff3a36 310 u8 reserved_at_60[0x18];
e281682b
SM		 311 u8 log_max_ft_num[0x8];
312
b4ff3a36 313 u8 reserved_at_80[0x18];
e281682b
SM		 314 u8 log_max_destination[0x8];
315
b4ff3a36 316 u8 reserved_at_a0[0x18];
e281682b
SM		 317 u8 log_max_flow[0x8];
318
b4ff3a36 319 u8 reserved_at_c0[0x40];
e281682b
SM		 320
321 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
322
323 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
324};
325
326struct mlx5_ifc_odp_per_transport_service_cap_bits {
327 u8 send[0x1];
328 u8 receive[0x1];
329 u8 write[0x1];
330 u8 read[0x1];
17d2f88f 331 u8 atomic[0x1];
e281682b 332 u8 srq_receive[0x1];
b4ff3a36 333 u8 reserved_at_6[0x1a];
e281682b
SM		 334};
335
b4d1f032 336struct mlx5_ifc_ipv4_layout_bits {
b4ff3a36 337 u8 reserved_at_0[0x60];
b4d1f032
MG		 338
339 u8 ipv4[0x20];
340};
341
342struct mlx5_ifc_ipv6_layout_bits {
343 u8 ipv6[16][0x8];
344};
345
346union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
347 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
348 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
b4ff3a36 349 u8 reserved_at_0[0x80];
b4d1f032
MG		 350};
351
e281682b
SM		 352struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
353 u8 smac_47_16[0x20];
354
355 u8 smac_15_0[0x10];
356 u8 ethertype[0x10];
357
358 u8 dmac_47_16[0x20];
359
360 u8 dmac_15_0[0x10];
361 u8 first_prio[0x3];
362 u8 first_cfi[0x1];
363 u8 first_vid[0xc];
364
365 u8 ip_protocol[0x8];
366 u8 ip_dscp[0x6];
367 u8 ip_ecn[0x2];
10543365
MHY		 368 u8 cvlan_tag[0x1];
369 u8 svlan_tag[0x1];
e281682b 370 u8 frag[0x1];
b4ff3a36 371 u8 reserved_at_93[0x4];
e281682b
SM		 372 u8 tcp_flags[0x9];
373
374 u8 tcp_sport[0x10];
375 u8 tcp_dport[0x10];
376
b4ff3a36 377 u8 reserved_at_c0[0x20];
e281682b
SM		 378
379 u8 udp_sport[0x10];
380 u8 udp_dport[0x10];
381
b4d1f032 382 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
e281682b 383
b4d1f032 384 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
e281682b
SM		 385};
386
387struct mlx5_ifc_fte_match_set_misc_bits {
7486216b
SM		 388 u8 reserved_at_0[0x8];
389 u8 source_sqn[0x18];
e281682b 390
b4ff3a36 391 u8 reserved_at_20[0x10];
e281682b
SM		 392 u8 source_port[0x10];
393
394 u8 outer_second_prio[0x3];
395 u8 outer_second_cfi[0x1];
396 u8 outer_second_vid[0xc];
397 u8 inner_second_prio[0x3];
398 u8 inner_second_cfi[0x1];
399 u8 inner_second_vid[0xc];
400
10543365
MHY		 401 u8 outer_second_cvlan_tag[0x1];
402 u8 inner_second_cvlan_tag[0x1];
403 u8 outer_second_svlan_tag[0x1];
404 u8 inner_second_svlan_tag[0x1];
405 u8 reserved_at_64[0xc];
e281682b
SM		 406 u8 gre_protocol[0x10];
407
408 u8 gre_key_h[0x18];
409 u8 gre_key_l[0x8];
410
411 u8 vxlan_vni[0x18];
b4ff3a36 412 u8 reserved_at_b8[0x8];
e281682b 413
b4ff3a36 414 u8 reserved_at_c0[0x20];
e281682b 415
b4ff3a36 416 u8 reserved_at_e0[0xc];
e281682b
SM		 417 u8 outer_ipv6_flow_label[0x14];
418
b4ff3a36 419 u8 reserved_at_100[0xc];
e281682b
SM		 420 u8 inner_ipv6_flow_label[0x14];
421
b4ff3a36 422 u8 reserved_at_120[0xe0];
e281682b
SM		 423};
424
425struct mlx5_ifc_cmd_pas_bits {
426 u8 pa_h[0x20];
427
428 u8 pa_l[0x14];
b4ff3a36 429 u8 reserved_at_34[0xc];
e281682b
SM		 430};
431
432struct mlx5_ifc_uint64_bits {
433 u8 hi[0x20];
434
435 u8 lo[0x20];
436};
437
438enum {
439 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
440 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
441 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
442 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
443 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
444 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
445 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
446 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
447 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
448 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
449};
450
451struct mlx5_ifc_ads_bits {
452 u8 fl[0x1];
453 u8 free_ar[0x1];
b4ff3a36 454 u8 reserved_at_2[0xe];
e281682b
SM		 455 u8 pkey_index[0x10];
456
b4ff3a36 457 u8 reserved_at_20[0x8];
e281682b
SM		 458 u8 grh[0x1];
459 u8 mlid[0x7];
460 u8 rlid[0x10];
461
462 u8 ack_timeout[0x5];
b4ff3a36 463 u8 reserved_at_45[0x3];
e281682b 464 u8 src_addr_index[0x8];
b4ff3a36 465 u8 reserved_at_50[0x4];
e281682b
SM		 466 u8 stat_rate[0x4];
467 u8 hop_limit[0x8];
468
b4ff3a36 469 u8 reserved_at_60[0x4];
e281682b
SM		 470 u8 tclass[0x8];
471 u8 flow_label[0x14];
472
473 u8 rgid_rip[16][0x8];
474
b4ff3a36 475 u8 reserved_at_100[0x4];
e281682b
SM		 476 u8 f_dscp[0x1];
477 u8 f_ecn[0x1];
b4ff3a36 478 u8 reserved_at_106[0x1];
e281682b
SM		 479 u8 f_eth_prio[0x1];
480 u8 ecn[0x2];
481 u8 dscp[0x6];
482 u8 udp_sport[0x10];
483
484 u8 dei_cfi[0x1];
485 u8 eth_prio[0x3];
486 u8 sl[0x4];
487 u8 port[0x8];
488 u8 rmac_47_32[0x10];
489
490 u8 rmac_31_0[0x20];
491};
492
493struct mlx5_ifc_flow_table_nic_cap_bits {
b3638e1a 494 u8 nic_rx_multi_path_tirs[0x1];
cea824d4
MG		 495 u8 nic_rx_multi_path_tirs_fts[0x1];
496 u8 allow_sniffer_and_nic_rx_shared_tir[0x1];
497 u8 reserved_at_3[0x1fd];
e281682b
SM		 498
499 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
500
b4ff3a36 501 u8 reserved_at_400[0x200];
e281682b
SM		 502
503 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
504
505 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
506
b4ff3a36 507 u8 reserved_at_a00[0x200];
e281682b
SM		 508
509 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
510
b4ff3a36 511 u8 reserved_at_e00[0x7200];
e281682b
SM		 512};
513
495716b1 514struct mlx5_ifc_flow_table_eswitch_cap_bits {
b4ff3a36 515 u8 reserved_at_0[0x200];
495716b1
SM		 516
517 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
518
519 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
520
521 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
522
b4ff3a36 523 u8 reserved_at_800[0x7800];
495716b1
SM		 524};
525
d6666753
SM		 526struct mlx5_ifc_e_switch_cap_bits {
527 u8 vport_svlan_strip[0x1];
528 u8 vport_cvlan_strip[0x1];
529 u8 vport_svlan_insert[0x1];
530 u8 vport_cvlan_insert_if_not_exist[0x1];
531 u8 vport_cvlan_insert_overwrite[0x1];
23898c76
NO		 532 u8 reserved_at_5[0x19];
533 u8 nic_vport_node_guid_modify[0x1];
534 u8 nic_vport_port_guid_modify[0x1];
d6666753 535
7adbde20
HHZ		 536 u8 vxlan_encap_decap[0x1];
537 u8 nvgre_encap_decap[0x1];
538 u8 reserved_at_22[0x9];
539 u8 log_max_encap_headers[0x5];
540 u8 reserved_2b[0x6];
541 u8 max_encap_header_size[0xa];
542
543 u8 reserved_40[0x7c0];
544
d6666753
SM		 545};
546
7486216b
SM		 547struct mlx5_ifc_qos_cap_bits {
548 u8 packet_pacing[0x1];
813f8540 549 u8 esw_scheduling[0x1];
c9497c98
MHY		 550 u8 esw_bw_share[0x1];
551 u8 esw_rate_limit[0x1];
552 u8 reserved_at_4[0x1c];
813f8540
MHY		 553
554 u8 reserved_at_20[0x20];
555
7486216b 556 u8 packet_pacing_max_rate[0x20];
813f8540 557
7486216b 558 u8 packet_pacing_min_rate[0x20];
813f8540
MHY		 559
560 u8 reserved_at_80[0x10];
7486216b 561 u8 packet_pacing_rate_table_size[0x10];
813f8540
MHY		 562
563 u8 esw_element_type[0x10];
564 u8 esw_tsar_type[0x10];
565
566 u8 reserved_at_c0[0x10];
567 u8 max_qos_para_vport[0x10];
568
569 u8 max_tsar_bw_share[0x20];
570
571 u8 reserved_at_100[0x700];
7486216b
SM		 572};
573
e281682b
SM		 574struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
575 u8 csum_cap[0x1];
576 u8 vlan_cap[0x1];
577 u8 lro_cap[0x1];
578 u8 lro_psh_flag[0x1];
579 u8 lro_time_stamp[0x1];
b4ff3a36 580 u8 reserved_at_5[0x3];
66189961 581 u8 self_lb_en_modifiable[0x1];
b4ff3a36 582 u8 reserved_at_9[0x2];
e281682b 583 u8 max_lso_cap[0x5];
c226dc22 584 u8 multi_pkt_send_wqe[0x2];
cff92d7c 585 u8 wqe_inline_mode[0x2];
e281682b 586 u8 rss_ind_tbl_cap[0x4];
7d5e1423
SM		 587 u8 reg_umr_sq[0x1];
588 u8 scatter_fcs[0x1];
589 u8 reserved_at_1a[0x1];
e281682b 590 u8 tunnel_lso_const_out_ip_id[0x1];
b4ff3a36 591 u8 reserved_at_1c[0x2];
e281682b
SM		 592 u8 tunnel_statless_gre[0x1];
593 u8 tunnel_stateless_vxlan[0x1];
594
b4ff3a36 595 u8 reserved_at_20[0x20];
e281682b 596
b4ff3a36 597 u8 reserved_at_40[0x10];
e281682b
SM		 598 u8 lro_min_mss_size[0x10];
599
b4ff3a36 600 u8 reserved_at_60[0x120];
e281682b
SM		 601
602 u8 lro_timer_supported_periods[4][0x20];
603
b4ff3a36 604 u8 reserved_at_200[0x600];
e281682b
SM		 605};
606
607struct mlx5_ifc_roce_cap_bits {
608 u8 roce_apm[0x1];
b4ff3a36 609 u8 reserved_at_1[0x1f];
e281682b 610
b4ff3a36 611 u8 reserved_at_20[0x60];
e281682b 612
b4ff3a36 613 u8 reserved_at_80[0xc];
e281682b 614 u8 l3_type[0x4];
b4ff3a36 615 u8 reserved_at_90[0x8];
e281682b
SM		 616 u8 roce_version[0x8];
617
b4ff3a36 618 u8 reserved_at_a0[0x10];
e281682b
SM		 619 u8 r_roce_dest_udp_port[0x10];
620
621 u8 r_roce_max_src_udp_port[0x10];
622 u8 r_roce_min_src_udp_port[0x10];
623
b4ff3a36 624 u8 reserved_at_e0[0x10];
e281682b
SM		 625 u8 roce_address_table_size[0x10];
626
b4ff3a36 627 u8 reserved_at_100[0x700];
e281682b
SM		 628};
629
630enum {
631 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
632 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
633 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
634 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
635 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
636 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
637 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
638 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
639 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
640};
641
642enum {
643 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
644 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
645 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
646 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
647 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
648 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
649 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
650 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
651 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
652};
653
654struct mlx5_ifc_atomic_caps_bits {
b4ff3a36 655 u8 reserved_at_0[0x40];
e281682b 656
f91e6d89 657 u8 atomic_req_8B_endianess_mode[0x2];
b4ff3a36 658 u8 reserved_at_42[0x4];
f91e6d89 659 u8 supported_atomic_req_8B_endianess_mode_1[0x1];
e281682b 660
b4ff3a36 661 u8 reserved_at_47[0x19];
e281682b 662
b4ff3a36 663 u8 reserved_at_60[0x20];
e281682b 664
b4ff3a36 665 u8 reserved_at_80[0x10];
f91e6d89 666 u8 atomic_operations[0x10];
e281682b 667
b4ff3a36 668 u8 reserved_at_a0[0x10];
f91e6d89
EBE		 669 u8 atomic_size_qp[0x10];
670
b4ff3a36 671 u8 reserved_at_c0[0x10];
e281682b
SM		 672 u8 atomic_size_dc[0x10];
673
b4ff3a36 674 u8 reserved_at_e0[0x720];
e281682b
SM		 675};
676
677struct mlx5_ifc_odp_cap_bits {
b4ff3a36 678 u8 reserved_at_0[0x40];
e281682b
SM		 679
680 u8 sig[0x1];
b4ff3a36 681 u8 reserved_at_41[0x1f];
e281682b 682
b4ff3a36 683 u8 reserved_at_60[0x20];
e281682b
SM		 684
685 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
686
687 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
688
689 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
690
b4ff3a36 691 u8 reserved_at_e0[0x720];
e281682b
SM		 692};
693
3f0393a5
SG		 694struct mlx5_ifc_calc_op {
695 u8 reserved_at_0[0x10];
696 u8 reserved_at_10[0x9];
697 u8 op_swap_endianness[0x1];
698 u8 op_min[0x1];
699 u8 op_xor[0x1];
700 u8 op_or[0x1];
701 u8 op_and[0x1];
702 u8 op_max[0x1];
703 u8 op_add[0x1];
704};
705
706struct mlx5_ifc_vector_calc_cap_bits {
707 u8 calc_matrix[0x1];
708 u8 reserved_at_1[0x1f];
709 u8 reserved_at_20[0x8];
710 u8 max_vec_count[0x8];
711 u8 reserved_at_30[0xd];
712 u8 max_chunk_size[0x3];
713 struct mlx5_ifc_calc_op calc0;
714 struct mlx5_ifc_calc_op calc1;
715 struct mlx5_ifc_calc_op calc2;
716 struct mlx5_ifc_calc_op calc3;
717
718 u8 reserved_at_e0[0x720];
719};
720
e281682b
SM		 721enum {
722 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
723 MLX5_WQ_TYPE_CYCLIC = 0x1,
7d5e1423 724 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
e281682b
SM		 725};
726
727enum {
728 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
729 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
730};
731
732enum {
733 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
734 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
735 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
736 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
737 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
738};
739
740enum {
741 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
742 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
743 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
744 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
745 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
746 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
747};
748
749enum {
750 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
751 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
752};
753
754enum {
755 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
756 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
757 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
758};
759
760enum {
761 MLX5_CAP_PORT_TYPE_IB = 0x0,
762 MLX5_CAP_PORT_TYPE_ETH = 0x1,
d29b796a
EC		 763};
764
b775516b 765struct mlx5_ifc_cmd_hca_cap_bits {
b4ff3a36 766 u8 reserved_at_0[0x80];
b775516b
EC		 767
768 u8 log_max_srq_sz[0x8];
769 u8 log_max_qp_sz[0x8];
b4ff3a36 770 u8 reserved_at_90[0xb];
b775516b
EC		 771 u8 log_max_qp[0x5];
772
b4ff3a36 773 u8 reserved_at_a0[0xb];
e281682b 774 u8 log_max_srq[0x5];
b4ff3a36 775 u8 reserved_at_b0[0x10];
b775516b 776
b4ff3a36 777 u8 reserved_at_c0[0x8];
b775516b 778 u8 log_max_cq_sz[0x8];
b4ff3a36 779 u8 reserved_at_d0[0xb];
b775516b
EC		 780 u8 log_max_cq[0x5];
781
782 u8 log_max_eq_sz[0x8];
b4ff3a36 783 u8 reserved_at_e8[0x2];
b775516b 784 u8 log_max_mkey[0x6];
b4ff3a36 785 u8 reserved_at_f0[0xc];
b775516b
EC		 786 u8 log_max_eq[0x4];
787
788 u8 max_indirection[0x8];
bcda1aca 789 u8 fixed_buffer_size[0x1];
b775516b 790 u8 log_max_mrw_sz[0x7];
b4ff3a36 791 u8 reserved_at_110[0x2];
b775516b 792 u8 log_max_bsf_list_size[0x6];
bcda1aca
AK		 793 u8 umr_extended_translation_offset[0x1];
794 u8 null_mkey[0x1];
b775516b
EC		 795 u8 log_max_klm_list_size[0x6];
796
b4ff3a36 797 u8 reserved_at_120[0xa];
b775516b 798 u8 log_max_ra_req_dc[0x6];
b4ff3a36 799 u8 reserved_at_130[0xa];
b775516b
EC		 800 u8 log_max_ra_res_dc[0x6];
801
b4ff3a36 802 u8 reserved_at_140[0xa];
b775516b 803 u8 log_max_ra_req_qp[0x6];
b4ff3a36 804 u8 reserved_at_150[0xa];
b775516b
EC		 805 u8 log_max_ra_res_qp[0x6];
806
807 u8 pad_cap[0x1];
808 u8 cc_query_allowed[0x1];
809 u8 cc_modify_allowed[0x1];
b4ff3a36 810 u8 reserved_at_163[0xd];
e281682b 811 u8 gid_table_size[0x10];
b775516b 812
e281682b
SM		 813 u8 out_of_seq_cnt[0x1];
814 u8 vport_counters[0x1];
7486216b 815 u8 retransmission_q_counters[0x1];
83b502a1
AV		 816 u8 reserved_at_183[0x1];
817 u8 modify_rq_counter_set_id[0x1];
818 u8 reserved_at_185[0x1];
b775516b
EC		 819 u8 max_qp_cnt[0xa];
820 u8 pkey_table_size[0x10];
821
e281682b
SM		 822 u8 vport_group_manager[0x1];
823 u8 vhca_group_manager[0x1];
824 u8 ib_virt[0x1];
825 u8 eth_virt[0x1];
b4ff3a36 826 u8 reserved_at_1a4[0x1];
e281682b
SM		 827 u8 ets[0x1];
828 u8 nic_flow_table[0x1];
54f0a411 829 u8 eswitch_flow_table[0x1];
e1c9c62b 830 u8 early_vf_enable[0x1];
cfdcbcea
GP		 831 u8 mcam_reg[0x1];
832 u8 pcam_reg[0x1];
b775516b 833 u8 local_ca_ack_delay[0x5];
4ce3bf2f 834 u8 port_module_event[0x1];
7b13558f 835 u8 reserved_at_1b1[0x1];
7d5e1423 836 u8 ports_check[0x1];
7b13558f 837 u8 reserved_at_1b3[0x1];
7d5e1423
SM		 838 u8 disable_link_up[0x1];
839 u8 beacon_led[0x1];
e281682b 840 u8 port_type[0x2];
b775516b
EC		 841 u8 num_ports[0x8];
842
f9a1ef72
EE		 843 u8 reserved_at_1c0[0x1];
844 u8 pps[0x1];
845 u8 pps_modify[0x1];
b775516b 846 u8 log_max_msg[0x5];
e1c9c62b 847 u8 reserved_at_1c8[0x4];
4f3961ee 848 u8 max_tc[0x4];
7486216b
SM		 849 u8 reserved_at_1d0[0x1];
850 u8 dcbx[0x1];
851 u8 reserved_at_1d2[0x4];
928cfe87
TT		 852 u8 rol_s[0x1];
853 u8 rol_g[0x1];
e1c9c62b 854 u8 reserved_at_1d8[0x1];
928cfe87
TT		 855 u8 wol_s[0x1];
856 u8 wol_g[0x1];
857 u8 wol_a[0x1];
858 u8 wol_b[0x1];
859 u8 wol_m[0x1];
860 u8 wol_u[0x1];
861 u8 wol_p[0x1];
b775516b
EC		 862
863 u8 stat_rate_support[0x10];
e1c9c62b 864 u8 reserved_at_1f0[0xc];
e281682b 865 u8 cqe_version[0x4];
b775516b 866
e281682b 867 u8 compact_address_vector[0x1];
7d5e1423 868 u8 striding_rq[0x1];
7b13558f 869 u8 reserved_at_202[0x2];
1015c2e8 870 u8 ipoib_basic_offloads[0x1];
e1c9c62b 871 u8 reserved_at_205[0xa];
e281682b 872 u8 drain_sigerr[0x1];
b775516b
EC		 873 u8 cmdif_checksum[0x2];
874 u8 sigerr_cqe[0x1];
e1c9c62b 875 u8 reserved_at_213[0x1];
b775516b
EC		 876 u8 wq_signature[0x1];
877 u8 sctr_data_cqe[0x1];
e1c9c62b 878 u8 reserved_at_216[0x1];
b775516b
EC		 879 u8 sho[0x1];
880 u8 tph[0x1];
881 u8 rf[0x1];
e281682b 882 u8 dct[0x1];
7486216b 883 u8 qos[0x1];
e281682b 884 u8 eth_net_offloads[0x1];
b775516b
EC		 885 u8 roce[0x1];
886 u8 atomic[0x1];
e1c9c62b 887 u8 reserved_at_21f[0x1];
b775516b
EC		 888
889 u8 cq_oi[0x1];
890 u8 cq_resize[0x1];
891 u8 cq_moderation[0x1];
e1c9c62b 892 u8 reserved_at_223[0x3];
e281682b 893 u8 cq_eq_remap[0x1];
b775516b
EC		 894 u8 pg[0x1];
895 u8 block_lb_mc[0x1];
e1c9c62b 896 u8 reserved_at_229[0x1];
e281682b 897 u8 scqe_break_moderation[0x1];
7d5e1423 898 u8 cq_period_start_from_cqe[0x1];
b775516b 899 u8 cd[0x1];
e1c9c62b 900 u8 reserved_at_22d[0x1];
b775516b 901 u8 apm[0x1];
3f0393a5 902 u8 vector_calc[0x1];
7d5e1423 903 u8 umr_ptr_rlky[0x1];
d2370e0a 904 u8 imaicl[0x1];
e1c9c62b 905 u8 reserved_at_232[0x4];
b775516b
EC		 906 u8 qkv[0x1];
907 u8 pkv[0x1];
b11a4f9c
HE		 908 u8 set_deth_sqpn[0x1];
909 u8 reserved_at_239[0x3];
b775516b
EC		 910 u8 xrc[0x1];
911 u8 ud[0x1];
912 u8 uc[0x1];
913 u8 rc[0x1];
914
a6d51b68
EC		 915 u8 uar_4k[0x1];
916 u8 reserved_at_241[0x9];
b775516b 917 u8 uar_sz[0x6];
e1c9c62b 918 u8 reserved_at_250[0x8];
b775516b
EC		 919 u8 log_pg_sz[0x8];
920
921 u8 bf[0x1];
0dbc6fe0 922 u8 driver_version[0x1];
e281682b 923 u8 pad_tx_eth_packet[0x1];
e1c9c62b 924 u8 reserved_at_263[0x8];
b775516b 925 u8 log_bf_reg_size[0x5];
84df61eb
AH		 926
927 u8 reserved_at_270[0xb];
928 u8 lag_master[0x1];
929 u8 num_lag_ports[0x4];
b775516b 930
e1c9c62b 931 u8 reserved_at_280[0x10];
b775516b
EC		 932 u8 max_wqe_sz_sq[0x10];
933
e1c9c62b 934 u8 reserved_at_2a0[0x10];
b775516b
EC		 935 u8 max_wqe_sz_rq[0x10];
936
e1c9c62b 937 u8 reserved_at_2c0[0x10];
b775516b
EC		 938 u8 max_wqe_sz_sq_dc[0x10];
939
e1c9c62b 940 u8 reserved_at_2e0[0x7];
b775516b
EC		 941 u8 max_qp_mcg[0x19];
942
e1c9c62b 943 u8 reserved_at_300[0x18];
b775516b
EC		 944 u8 log_max_mcg[0x8];
945
e1c9c62b 946 u8 reserved_at_320[0x3];
e281682b 947 u8 log_max_transport_domain[0x5];
e1c9c62b 948 u8 reserved_at_328[0x3];
b775516b 949 u8 log_max_pd[0x5];
e1c9c62b 950 u8 reserved_at_330[0xb];
b775516b
EC		 951 u8 log_max_xrcd[0x5];
952
a351a1b0
AV		 953 u8 reserved_at_340[0x8];
954 u8 log_max_flow_counter_bulk[0x8];
955 u8 max_flow_counter[0x10];
956
b775516b 957
e1c9c62b 958 u8 reserved_at_360[0x3];
b775516b 959 u8 log_max_rq[0x5];
e1c9c62b 960 u8 reserved_at_368[0x3];
b775516b 961 u8 log_max_sq[0x5];
e1c9c62b 962 u8 reserved_at_370[0x3];
b775516b 963 u8 log_max_tir[0x5];
e1c9c62b 964 u8 reserved_at_378[0x3];
b775516b
EC		 965 u8 log_max_tis[0x5];
966
e281682b 967 u8 basic_cyclic_rcv_wqe[0x1];
e1c9c62b 968 u8 reserved_at_381[0x2];
e281682b 969 u8 log_max_rmp[0x5];
e1c9c62b 970 u8 reserved_at_388[0x3];
e281682b 971 u8 log_max_rqt[0x5];
e1c9c62b 972 u8 reserved_at_390[0x3];
e281682b 973 u8 log_max_rqt_size[0x5];
e1c9c62b 974 u8 reserved_at_398[0x3];
b775516b
EC		 975 u8 log_max_tis_per_sq[0x5];
976
e1c9c62b 977 u8 reserved_at_3a0[0x3];
e281682b 978 u8 log_max_stride_sz_rq[0x5];
e1c9c62b 979 u8 reserved_at_3a8[0x3];
e281682b 980 u8 log_min_stride_sz_rq[0x5];
e1c9c62b 981 u8 reserved_at_3b0[0x3];
e281682b 982 u8 log_max_stride_sz_sq[0x5];
e1c9c62b 983 u8 reserved_at_3b8[0x3];
e281682b
SM		 984 u8 log_min_stride_sz_sq[0x5];
985
e1c9c62b 986 u8 reserved_at_3c0[0x1b];
e281682b
SM		 987 u8 log_max_wq_sz[0x5];
988
54f0a411 989 u8 nic_vport_change_event[0x1];
e1c9c62b 990 u8 reserved_at_3e1[0xa];
54f0a411 991 u8 log_max_vlan_list[0x5];
e1c9c62b 992 u8 reserved_at_3f0[0x3];
54f0a411 993 u8 log_max_current_mc_list[0x5];
e1c9c62b 994 u8 reserved_at_3f8[0x3];
54f0a411
SM		 995 u8 log_max_current_uc_list[0x5];
996
e1c9c62b 997 u8 reserved_at_400[0x80];
54f0a411 998
e1c9c62b 999 u8 reserved_at_480[0x3];
e281682b 1000 u8 log_max_l2_table[0x5];
e1c9c62b 1001 u8 reserved_at_488[0x8];
b775516b
EC		 1002 u8 log_uar_page_sz[0x10];
1003
e1c9c62b 1004 u8 reserved_at_4a0[0x20];
048ccca8 1005 u8 device_frequency_mhz[0x20];
b0844444 1006 u8 device_frequency_khz[0x20];
e1c9c62b 1007
a6d51b68
EC		 1008 u8 reserved_at_500[0x20];
1009 u8 num_of_uars_per_page[0x20];
1010 u8 reserved_at_540[0x40];
e1c9c62b
TT		 1011
1012 u8 reserved_at_580[0x3f];
7d5e1423 1013 u8 cqe_compression[0x1];
b775516b 1014
7d5e1423
SM		 1015 u8 cqe_compression_timeout[0x10];
1016 u8 cqe_compression_max_num[0x10];
b775516b 1017
7486216b
SM		 1018 u8 reserved_at_5e0[0x10];
1019 u8 tag_matching[0x1];
1020 u8 rndv_offload_rc[0x1];
1021 u8 rndv_offload_dc[0x1];
1022 u8 log_tag_matching_list_sz[0x5];
7b13558f 1023 u8 reserved_at_5f8[0x3];
7486216b
SM		 1024 u8 log_max_xrq[0x5];
1025
7b13558f 1026 u8 reserved_at_600[0x200];
b775516b
EC		 1027};
1028
81848731
SM		 1029enum mlx5_flow_destination_type {
1030 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
1031 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
1032 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
bd5251db
AV		 1033
1034 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
e281682b 1035};
b775516b 1036
e281682b
SM		 1037struct mlx5_ifc_dest_format_struct_bits {
1038 u8 destination_type[0x8];
1039 u8 destination_id[0x18];
b775516b 1040
b4ff3a36 1041 u8 reserved_at_20[0x20];
e281682b
SM		 1042};
1043
9dc0b289 1044struct mlx5_ifc_flow_counter_list_bits {
a351a1b0
AV		 1045 u8 clear[0x1];
1046 u8 num_of_counters[0xf];
9dc0b289
AV		 1047 u8 flow_counter_id[0x10];
1048
1049 u8 reserved_at_20[0x20];
1050};
1051
1052union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1053 struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1054 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1055 u8 reserved_at_0[0x40];
1056};
1057
e281682b
SM		 1058struct mlx5_ifc_fte_match_param_bits {
1059 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1060
1061 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1062
1063 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
b775516b 1064
b4ff3a36 1065 u8 reserved_at_600[0xa00];
b775516b
EC		 1066};
1067
e281682b
SM		 1068enum {
1069 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1070 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1071 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1072 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1073 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1074};
b775516b 1075
e281682b
SM		 1076struct mlx5_ifc_rx_hash_field_select_bits {
1077 u8 l3_prot_type[0x1];
1078 u8 l4_prot_type[0x1];
1079 u8 selected_fields[0x1e];
1080};
b775516b 1081
e281682b
SM		 1082enum {
1083 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
1084 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
b775516b
EC		 1085};
1086
e281682b
SM		 1087enum {
1088 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
1089 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
1090};
1091
1092struct mlx5_ifc_wq_bits {
1093 u8 wq_type[0x4];
1094 u8 wq_signature[0x1];
1095 u8 end_padding_mode[0x2];
1096 u8 cd_slave[0x1];
b4ff3a36 1097 u8 reserved_at_8[0x18];
b775516b 1098
e281682b
SM		 1099 u8 hds_skip_first_sge[0x1];
1100 u8 log2_hds_buf_size[0x3];
b4ff3a36 1101 u8 reserved_at_24[0x7];
e281682b
SM		 1102 u8 page_offset[0x5];
1103 u8 lwm[0x10];
b775516b 1104
b4ff3a36 1105 u8 reserved_at_40[0x8];
e281682b
SM		 1106 u8 pd[0x18];
1107
b4ff3a36 1108 u8 reserved_at_60[0x8];
e281682b
SM		 1109 u8 uar_page[0x18];
1110
1111 u8 dbr_addr[0x40];
1112
1113 u8 hw_counter[0x20];
1114
1115 u8 sw_counter[0x20];
1116
b4ff3a36 1117 u8 reserved_at_100[0xc];
e281682b 1118 u8 log_wq_stride[0x4];
b4ff3a36 1119 u8 reserved_at_110[0x3];
e281682b 1120 u8 log_wq_pg_sz[0x5];
b4ff3a36 1121 u8 reserved_at_118[0x3];
e281682b
SM		 1122 u8 log_wq_sz[0x5];
1123
7d5e1423
SM		 1124 u8 reserved_at_120[0x15];
1125 u8 log_wqe_num_of_strides[0x3];
1126 u8 two_byte_shift_en[0x1];
1127 u8 reserved_at_139[0x4];
1128 u8 log_wqe_stride_size[0x3];
1129
1130 u8 reserved_at_140[0x4c0];
b775516b 1131
e281682b 1132 struct mlx5_ifc_cmd_pas_bits pas[0];
b775516b
EC		 1133};
1134
e281682b 1135struct mlx5_ifc_rq_num_bits {
b4ff3a36 1136 u8 reserved_at_0[0x8];
e281682b
SM		 1137 u8 rq_num[0x18];
1138};
b775516b 1139
e281682b 1140struct mlx5_ifc_mac_address_layout_bits {
b4ff3a36 1141 u8 reserved_at_0[0x10];
e281682b 1142 u8 mac_addr_47_32[0x10];
b775516b 1143
e281682b
SM		 1144 u8 mac_addr_31_0[0x20];
1145};
1146
c0046cf7 1147struct mlx5_ifc_vlan_layout_bits {
b4ff3a36 1148 u8 reserved_at_0[0x14];
c0046cf7
SM		 1149 u8 vlan[0x0c];
1150
b4ff3a36 1151 u8 reserved_at_20[0x20];
c0046cf7
SM		 1152};
1153
e281682b 1154struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
b4ff3a36 1155 u8 reserved_at_0[0xa0];
e281682b
SM		 1156
1157 u8 min_time_between_cnps[0x20];
1158
b4ff3a36 1159 u8 reserved_at_c0[0x12];
e281682b 1160 u8 cnp_dscp[0x6];
b4ff3a36 1161 u8 reserved_at_d8[0x5];
e281682b
SM		 1162 u8 cnp_802p_prio[0x3];
1163
b4ff3a36 1164 u8 reserved_at_e0[0x720];
e281682b
SM		 1165};
1166
1167struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
b4ff3a36 1168 u8 reserved_at_0[0x60];
e281682b 1169
b4ff3a36 1170 u8 reserved_at_60[0x4];
e281682b 1171 u8 clamp_tgt_rate[0x1];
b4ff3a36 1172 u8 reserved_at_65[0x3];
e281682b 1173 u8 clamp_tgt_rate_after_time_inc[0x1];
b4ff3a36 1174 u8 reserved_at_69[0x17];
e281682b 1175
b4ff3a36 1176 u8 reserved_at_80[0x20];
e281682b
SM		 1177
1178 u8 rpg_time_reset[0x20];
1179
1180 u8 rpg_byte_reset[0x20];
1181
1182 u8 rpg_threshold[0x20];
1183
1184 u8 rpg_max_rate[0x20];
1185
1186 u8 rpg_ai_rate[0x20];
1187
1188 u8 rpg_hai_rate[0x20];
1189
1190 u8 rpg_gd[0x20];
1191
1192 u8 rpg_min_dec_fac[0x20];
1193
1194 u8 rpg_min_rate[0x20];
1195
b4ff3a36 1196 u8 reserved_at_1c0[0xe0];
e281682b
SM		 1197
1198 u8 rate_to_set_on_first_cnp[0x20];
1199
1200 u8 dce_tcp_g[0x20];
1201
1202 u8 dce_tcp_rtt[0x20];
1203
1204 u8 rate_reduce_monitor_period[0x20];
1205
b4ff3a36 1206 u8 reserved_at_320[0x20];
e281682b
SM		 1207
1208 u8 initial_alpha_value[0x20];
1209
b4ff3a36 1210 u8 reserved_at_360[0x4a0];
e281682b
SM		 1211};
1212
1213struct mlx5_ifc_cong_control_802_1qau_rp_bits {
b4ff3a36 1214 u8 reserved_at_0[0x80];
e281682b
SM		 1215
1216 u8 rppp_max_rps[0x20];
1217
1218 u8 rpg_time_reset[0x20];
1219
1220 u8 rpg_byte_reset[0x20];
1221
1222 u8 rpg_threshold[0x20];
1223
1224 u8 rpg_max_rate[0x20];
1225
1226 u8 rpg_ai_rate[0x20];
1227
1228 u8 rpg_hai_rate[0x20];
1229
1230 u8 rpg_gd[0x20];
1231
1232 u8 rpg_min_dec_fac[0x20];
1233
1234 u8 rpg_min_rate[0x20];
1235
b4ff3a36 1236 u8 reserved_at_1c0[0x640];
e281682b
SM		 1237};
1238
1239enum {
1240 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1241 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1242 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1243};
1244
1245struct mlx5_ifc_resize_field_select_bits {
1246 u8 resize_field_select[0x20];
1247};
1248
1249enum {
1250 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1251 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1252 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1253 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1254};
1255
1256struct mlx5_ifc_modify_field_select_bits {
1257 u8 modify_field_select[0x20];
1258};
1259
1260struct mlx5_ifc_field_select_r_roce_np_bits {
1261 u8 field_select_r_roce_np[0x20];
1262};
1263
1264struct mlx5_ifc_field_select_r_roce_rp_bits {
1265 u8 field_select_r_roce_rp[0x20];
1266};
1267
1268enum {
1269 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1270 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1271 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1272 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1273 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1274 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1275 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1276 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1277 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1278 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1279};
1280
1281struct mlx5_ifc_field_select_802_1qau_rp_bits {
1282 u8 field_select_8021qaurp[0x20];
1283};
1284
1285struct mlx5_ifc_phys_layer_cntrs_bits {
1286 u8 time_since_last_clear_high[0x20];
1287
1288 u8 time_since_last_clear_low[0x20];
1289
1290 u8 symbol_errors_high[0x20];
1291
1292 u8 symbol_errors_low[0x20];
1293
1294 u8 sync_headers_errors_high[0x20];
1295
1296 u8 sync_headers_errors_low[0x20];
1297
1298 u8 edpl_bip_errors_lane0_high[0x20];
1299
1300 u8 edpl_bip_errors_lane0_low[0x20];
1301
1302 u8 edpl_bip_errors_lane1_high[0x20];
1303
1304 u8 edpl_bip_errors_lane1_low[0x20];
1305
1306 u8 edpl_bip_errors_lane2_high[0x20];
1307
1308 u8 edpl_bip_errors_lane2_low[0x20];
1309
1310 u8 edpl_bip_errors_lane3_high[0x20];
1311
1312 u8 edpl_bip_errors_lane3_low[0x20];
1313
1314 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1315
1316 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1317
1318 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1319
1320 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1321
1322 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1323
1324 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1325
1326 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1327
1328 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1329
1330 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1331
1332 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1333
1334 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1335
1336 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1337
1338 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1339
1340 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1341
1342 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1343
1344 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1345
1346 u8 rs_fec_corrected_blocks_high[0x20];
1347
1348 u8 rs_fec_corrected_blocks_low[0x20];
1349
1350 u8 rs_fec_uncorrectable_blocks_high[0x20];
1351
1352 u8 rs_fec_uncorrectable_blocks_low[0x20];
1353
1354 u8 rs_fec_no_errors_blocks_high[0x20];
1355
1356 u8 rs_fec_no_errors_blocks_low[0x20];
1357
1358 u8 rs_fec_single_error_blocks_high[0x20];
1359
1360 u8 rs_fec_single_error_blocks_low[0x20];
1361
1362 u8 rs_fec_corrected_symbols_total_high[0x20];
1363
1364 u8 rs_fec_corrected_symbols_total_low[0x20];
1365
1366 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1367
1368 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1369
1370 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1371
1372 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1373
1374 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1375
1376 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1377
1378 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1379
1380 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1381
1382 u8 link_down_events[0x20];
1383
1384 u8 successful_recovery_events[0x20];
1385
b4ff3a36 1386 u8 reserved_at_640[0x180];
e281682b
SM		 1387};
1388
d8dc0508
GP		 1389struct mlx5_ifc_phys_layer_statistical_cntrs_bits {
1390 u8 time_since_last_clear_high[0x20];
1391
1392 u8 time_since_last_clear_low[0x20];
1393
1394 u8 phy_received_bits_high[0x20];
1395
1396 u8 phy_received_bits_low[0x20];
1397
1398 u8 phy_symbol_errors_high[0x20];
1399
1400 u8 phy_symbol_errors_low[0x20];
1401
1402 u8 phy_corrected_bits_high[0x20];
1403
1404 u8 phy_corrected_bits_low[0x20];
1405
1406 u8 phy_corrected_bits_lane0_high[0x20];
1407
1408 u8 phy_corrected_bits_lane0_low[0x20];
1409
1410 u8 phy_corrected_bits_lane1_high[0x20];
1411
1412 u8 phy_corrected_bits_lane1_low[0x20];
1413
1414 u8 phy_corrected_bits_lane2_high[0x20];
1415
1416 u8 phy_corrected_bits_lane2_low[0x20];
1417
1418 u8 phy_corrected_bits_lane3_high[0x20];
1419
1420 u8 phy_corrected_bits_lane3_low[0x20];
1421
1422 u8 reserved_at_200[0x5c0];
1423};
1424
1c64bf6f
MY		 1425struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1426 u8 symbol_error_counter[0x10];
1427
1428 u8 link_error_recovery_counter[0x8];
1429
1430 u8 link_downed_counter[0x8];
1431
1432 u8 port_rcv_errors[0x10];
1433
1434 u8 port_rcv_remote_physical_errors[0x10];
1435
1436 u8 port_rcv_switch_relay_errors[0x10];
1437
1438 u8 port_xmit_discards[0x10];
1439
1440 u8 port_xmit_constraint_errors[0x8];
1441
1442 u8 port_rcv_constraint_errors[0x8];
1443
1444 u8 reserved_at_70[0x8];
1445
1446 u8 link_overrun_errors[0x8];
1447
1448 u8 reserved_at_80[0x10];
1449
1450 u8 vl_15_dropped[0x10];
1451
1452 u8 reserved_at_a0[0xa0];
1453};
1454
e281682b
SM		 1455struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1456 u8 transmit_queue_high[0x20];
1457
1458 u8 transmit_queue_low[0x20];
1459
b4ff3a36 1460 u8 reserved_at_40[0x780];
e281682b
SM		 1461};
1462
1463struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1464 u8 rx_octets_high[0x20];
1465
1466 u8 rx_octets_low[0x20];
1467
b4ff3a36 1468 u8 reserved_at_40[0xc0];
e281682b
SM		 1469
1470 u8 rx_frames_high[0x20];
1471
1472 u8 rx_frames_low[0x20];
1473
1474 u8 tx_octets_high[0x20];
1475
1476 u8 tx_octets_low[0x20];
1477
b4ff3a36 1478 u8 reserved_at_180[0xc0];
e281682b
SM		 1479
1480 u8 tx_frames_high[0x20];
1481
1482 u8 tx_frames_low[0x20];
1483
1484 u8 rx_pause_high[0x20];
1485
1486 u8 rx_pause_low[0x20];
1487
1488 u8 rx_pause_duration_high[0x20];
1489
1490 u8 rx_pause_duration_low[0x20];
1491
1492 u8 tx_pause_high[0x20];
1493
1494 u8 tx_pause_low[0x20];
1495
1496 u8 tx_pause_duration_high[0x20];
1497
1498 u8 tx_pause_duration_low[0x20];
1499
1500 u8 rx_pause_transition_high[0x20];
1501
1502 u8 rx_pause_transition_low[0x20];
1503
b4ff3a36 1504 u8 reserved_at_3c0[0x400];
e281682b
SM		 1505};
1506
1507struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1508 u8 port_transmit_wait_high[0x20];
1509
1510 u8 port_transmit_wait_low[0x20];
1511
b4ff3a36 1512 u8 reserved_at_40[0x780];
e281682b
SM		 1513};
1514
1515struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1516 u8 dot3stats_alignment_errors_high[0x20];
1517
1518 u8 dot3stats_alignment_errors_low[0x20];
1519
1520 u8 dot3stats_fcs_errors_high[0x20];
1521
1522 u8 dot3stats_fcs_errors_low[0x20];
1523
1524 u8 dot3stats_single_collision_frames_high[0x20];
1525
1526 u8 dot3stats_single_collision_frames_low[0x20];
1527
1528 u8 dot3stats_multiple_collision_frames_high[0x20];
1529
1530 u8 dot3stats_multiple_collision_frames_low[0x20];
1531
1532 u8 dot3stats_sqe_test_errors_high[0x20];
1533
1534 u8 dot3stats_sqe_test_errors_low[0x20];
1535
1536 u8 dot3stats_deferred_transmissions_high[0x20];
1537
1538 u8 dot3stats_deferred_transmissions_low[0x20];
1539
1540 u8 dot3stats_late_collisions_high[0x20];
1541
1542 u8 dot3stats_late_collisions_low[0x20];
1543
1544 u8 dot3stats_excessive_collisions_high[0x20];
1545
1546 u8 dot3stats_excessive_collisions_low[0x20];
1547
1548 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1549
1550 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1551
1552 u8 dot3stats_carrier_sense_errors_high[0x20];
1553
1554 u8 dot3stats_carrier_sense_errors_low[0x20];
1555
1556 u8 dot3stats_frame_too_longs_high[0x20];
1557
1558 u8 dot3stats_frame_too_longs_low[0x20];
1559
1560 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1561
1562 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1563
1564 u8 dot3stats_symbol_errors_high[0x20];
1565
1566 u8 dot3stats_symbol_errors_low[0x20];
1567
1568 u8 dot3control_in_unknown_opcodes_high[0x20];
1569
1570 u8 dot3control_in_unknown_opcodes_low[0x20];
1571
1572 u8 dot3in_pause_frames_high[0x20];
1573
1574 u8 dot3in_pause_frames_low[0x20];
1575
1576 u8 dot3out_pause_frames_high[0x20];
1577
1578 u8 dot3out_pause_frames_low[0x20];
1579
b4ff3a36 1580 u8 reserved_at_400[0x3c0];
e281682b
SM		 1581};
1582
1583struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1584 u8 ether_stats_drop_events_high[0x20];
1585
1586 u8 ether_stats_drop_events_low[0x20];
1587
1588 u8 ether_stats_octets_high[0x20];
1589
1590 u8 ether_stats_octets_low[0x20];
1591
1592 u8 ether_stats_pkts_high[0x20];
1593
1594 u8 ether_stats_pkts_low[0x20];
1595
1596 u8 ether_stats_broadcast_pkts_high[0x20];
1597
1598 u8 ether_stats_broadcast_pkts_low[0x20];
1599
1600 u8 ether_stats_multicast_pkts_high[0x20];
1601
1602 u8 ether_stats_multicast_pkts_low[0x20];
1603
1604 u8 ether_stats_crc_align_errors_high[0x20];
1605
1606 u8 ether_stats_crc_align_errors_low[0x20];
1607
1608 u8 ether_stats_undersize_pkts_high[0x20];
1609
1610 u8 ether_stats_undersize_pkts_low[0x20];
1611
1612 u8 ether_stats_oversize_pkts_high[0x20];
1613
1614 u8 ether_stats_oversize_pkts_low[0x20];
1615
1616 u8 ether_stats_fragments_high[0x20];
1617
1618 u8 ether_stats_fragments_low[0x20];
1619
1620 u8 ether_stats_jabbers_high[0x20];
1621
1622 u8 ether_stats_jabbers_low[0x20];
1623
1624 u8 ether_stats_collisions_high[0x20];
1625
1626 u8 ether_stats_collisions_low[0x20];
1627
1628 u8 ether_stats_pkts64octets_high[0x20];
1629
1630 u8 ether_stats_pkts64octets_low[0x20];
1631
1632 u8 ether_stats_pkts65to127octets_high[0x20];
1633
1634 u8 ether_stats_pkts65to127octets_low[0x20];
1635
1636 u8 ether_stats_pkts128to255octets_high[0x20];
1637
1638 u8 ether_stats_pkts128to255octets_low[0x20];
1639
1640 u8 ether_stats_pkts256to511octets_high[0x20];
1641
1642 u8 ether_stats_pkts256to511octets_low[0x20];
1643
1644 u8 ether_stats_pkts512to1023octets_high[0x20];
1645
1646 u8 ether_stats_pkts512to1023octets_low[0x20];
1647
1648 u8 ether_stats_pkts1024to1518octets_high[0x20];
1649
1650 u8 ether_stats_pkts1024to1518octets_low[0x20];
1651
1652 u8 ether_stats_pkts1519to2047octets_high[0x20];
1653
1654 u8 ether_stats_pkts1519to2047octets_low[0x20];
1655
1656 u8 ether_stats_pkts2048to4095octets_high[0x20];
1657
1658 u8 ether_stats_pkts2048to4095octets_low[0x20];
1659
1660 u8 ether_stats_pkts4096to8191octets_high[0x20];
1661
1662 u8 ether_stats_pkts4096to8191octets_low[0x20];
1663
1664 u8 ether_stats_pkts8192to10239octets_high[0x20];
1665
1666 u8 ether_stats_pkts8192to10239octets_low[0x20];
1667
b4ff3a36 1668 u8 reserved_at_540[0x280];
e281682b
SM		 1669};
1670
1671struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1672 u8 if_in_octets_high[0x20];
1673
1674 u8 if_in_octets_low[0x20];
1675
1676 u8 if_in_ucast_pkts_high[0x20];
1677
1678 u8 if_in_ucast_pkts_low[0x20];
1679
1680 u8 if_in_discards_high[0x20];
1681
1682 u8 if_in_discards_low[0x20];
1683
1684 u8 if_in_errors_high[0x20];
1685
1686 u8 if_in_errors_low[0x20];
1687
1688 u8 if_in_unknown_protos_high[0x20];
1689
1690 u8 if_in_unknown_protos_low[0x20];
1691
1692 u8 if_out_octets_high[0x20];
1693
1694 u8 if_out_octets_low[0x20];
1695
1696 u8 if_out_ucast_pkts_high[0x20];
1697
1698 u8 if_out_ucast_pkts_low[0x20];
1699
1700 u8 if_out_discards_high[0x20];
1701
1702 u8 if_out_discards_low[0x20];
1703
1704 u8 if_out_errors_high[0x20];
1705
1706 u8 if_out_errors_low[0x20];
1707
1708 u8 if_in_multicast_pkts_high[0x20];
1709
1710 u8 if_in_multicast_pkts_low[0x20];
1711
1712 u8 if_in_broadcast_pkts_high[0x20];
1713
1714 u8 if_in_broadcast_pkts_low[0x20];
1715
1716 u8 if_out_multicast_pkts_high[0x20];
1717
1718 u8 if_out_multicast_pkts_low[0x20];
1719
1720 u8 if_out_broadcast_pkts_high[0x20];
1721
1722 u8 if_out_broadcast_pkts_low[0x20];
1723
b4ff3a36 1724 u8 reserved_at_340[0x480];
e281682b
SM		 1725};
1726
1727struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1728 u8 a_frames_transmitted_ok_high[0x20];
1729
1730 u8 a_frames_transmitted_ok_low[0x20];
1731
1732 u8 a_frames_received_ok_high[0x20];
1733
1734 u8 a_frames_received_ok_low[0x20];
1735
1736 u8 a_frame_check_sequence_errors_high[0x20];
1737
1738 u8 a_frame_check_sequence_errors_low[0x20];
1739
1740 u8 a_alignment_errors_high[0x20];
1741
1742 u8 a_alignment_errors_low[0x20];
1743
1744 u8 a_octets_transmitted_ok_high[0x20];
1745
1746 u8 a_octets_transmitted_ok_low[0x20];
1747
1748 u8 a_octets_received_ok_high[0x20];
1749
1750 u8 a_octets_received_ok_low[0x20];
1751
1752 u8 a_multicast_frames_xmitted_ok_high[0x20];
1753
1754 u8 a_multicast_frames_xmitted_ok_low[0x20];
1755
1756 u8 a_broadcast_frames_xmitted_ok_high[0x20];
1757
1758 u8 a_broadcast_frames_xmitted_ok_low[0x20];
1759
1760 u8 a_multicast_frames_received_ok_high[0x20];
1761
1762 u8 a_multicast_frames_received_ok_low[0x20];
1763
1764 u8 a_broadcast_frames_received_ok_high[0x20];
1765
1766 u8 a_broadcast_frames_received_ok_low[0x20];
1767
1768 u8 a_in_range_length_errors_high[0x20];
1769
1770 u8 a_in_range_length_errors_low[0x20];
1771
1772 u8 a_out_of_range_length_field_high[0x20];
1773
1774 u8 a_out_of_range_length_field_low[0x20];
1775
1776 u8 a_frame_too_long_errors_high[0x20];
1777
1778 u8 a_frame_too_long_errors_low[0x20];
1779
1780 u8 a_symbol_error_during_carrier_high[0x20];
1781
1782 u8 a_symbol_error_during_carrier_low[0x20];
1783
1784 u8 a_mac_control_frames_transmitted_high[0x20];
1785
1786 u8 a_mac_control_frames_transmitted_low[0x20];
1787
1788 u8 a_mac_control_frames_received_high[0x20];
1789
1790 u8 a_mac_control_frames_received_low[0x20];
1791
1792 u8 a_unsupported_opcodes_received_high[0x20];
1793
1794 u8 a_unsupported_opcodes_received_low[0x20];
1795
1796 u8 a_pause_mac_ctrl_frames_received_high[0x20];
1797
1798 u8 a_pause_mac_ctrl_frames_received_low[0x20];
1799
1800 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
1801
1802 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
1803
b4ff3a36 1804 u8 reserved_at_4c0[0x300];
e281682b
SM		 1805};
1806
8ed1a630
GP		 1807struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits {
1808 u8 life_time_counter_high[0x20];
1809
1810 u8 life_time_counter_low[0x20];
1811
1812 u8 rx_errors[0x20];
1813
1814 u8 tx_errors[0x20];
1815
1816 u8 l0_to_recovery_eieos[0x20];
1817
1818 u8 l0_to_recovery_ts[0x20];
1819
1820 u8 l0_to_recovery_framing[0x20];
1821
1822 u8 l0_to_recovery_retrain[0x20];
1823
1824 u8 crc_error_dllp[0x20];
1825
1826 u8 crc_error_tlp[0x20];
1827
1828 u8 reserved_at_140[0x680];
1829};
1830
e281682b
SM		 1831struct mlx5_ifc_cmd_inter_comp_event_bits {
1832 u8 command_completion_vector[0x20];
1833
b4ff3a36 1834 u8 reserved_at_20[0xc0];
e281682b
SM		 1835};
1836
1837struct mlx5_ifc_stall_vl_event_bits {
b4ff3a36 1838 u8 reserved_at_0[0x18];
e281682b 1839 u8 port_num[0x1];
b4ff3a36 1840 u8 reserved_at_19[0x3];
e281682b
SM		 1841 u8 vl[0x4];
1842
b4ff3a36 1843 u8 reserved_at_20[0xa0];
e281682b
SM		 1844};
1845
1846struct mlx5_ifc_db_bf_congestion_event_bits {
1847 u8 event_subtype[0x8];
b4ff3a36 1848 u8 reserved_at_8[0x8];
e281682b 1849 u8 congestion_level[0x8];
b4ff3a36 1850 u8 reserved_at_18[0x8];
e281682b 1851
b4ff3a36 1852 u8 reserved_at_20[0xa0];
e281682b
SM		 1853};
1854
1855struct mlx5_ifc_gpio_event_bits {
b4ff3a36 1856 u8 reserved_at_0[0x60];
e281682b
SM		 1857
1858 u8 gpio_event_hi[0x20];
1859
1860 u8 gpio_event_lo[0x20];
1861
b4ff3a36 1862 u8 reserved_at_a0[0x40];
e281682b
SM		 1863};
1864
1865struct mlx5_ifc_port_state_change_event_bits {
b4ff3a36 1866 u8 reserved_at_0[0x40];
e281682b
SM		 1867
1868 u8 port_num[0x4];
b4ff3a36 1869 u8 reserved_at_44[0x1c];
e281682b 1870
b4ff3a36 1871 u8 reserved_at_60[0x80];
e281682b
SM		 1872};
1873
1874struct mlx5_ifc_dropped_packet_logged_bits {
b4ff3a36 1875 u8 reserved_at_0[0xe0];
e281682b
SM		 1876};
1877
1878enum {
1879 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
1880 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
1881};
1882
1883struct mlx5_ifc_cq_error_bits {
b4ff3a36 1884 u8 reserved_at_0[0x8];
e281682b
SM		 1885 u8 cqn[0x18];
1886
b4ff3a36 1887 u8 reserved_at_20[0x20];
e281682b 1888
b4ff3a36 1889 u8 reserved_at_40[0x18];
e281682b
SM		 1890 u8 syndrome[0x8];
1891
b4ff3a36 1892 u8 reserved_at_60[0x80];
e281682b
SM		 1893};
1894
1895struct mlx5_ifc_rdma_page_fault_event_bits {
1896 u8 bytes_committed[0x20];
1897
1898 u8 r_key[0x20];
1899
b4ff3a36 1900 u8 reserved_at_40[0x10];
e281682b
SM		 1901 u8 packet_len[0x10];
1902
1903 u8 rdma_op_len[0x20];
1904
1905 u8 rdma_va[0x40];
1906
b4ff3a36 1907 u8 reserved_at_c0[0x5];
e281682b
SM		 1908 u8 rdma[0x1];
1909 u8 write[0x1];
1910 u8 requestor[0x1];
1911 u8 qp_number[0x18];
1912};
1913
1914struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1915 u8 bytes_committed[0x20];
1916
b4ff3a36 1917 u8 reserved_at_20[0x10];
e281682b
SM		 1918 u8 wqe_index[0x10];
1919
b4ff3a36 1920 u8 reserved_at_40[0x10];
e281682b
SM		 1921 u8 len[0x10];
1922
b4ff3a36 1923 u8 reserved_at_60[0x60];
e281682b 1924
b4ff3a36 1925 u8 reserved_at_c0[0x5];
e281682b
SM		 1926 u8 rdma[0x1];
1927 u8 write_read[0x1];
1928 u8 requestor[0x1];
1929 u8 qpn[0x18];
1930};
1931
1932struct mlx5_ifc_qp_events_bits {
b4ff3a36 1933 u8 reserved_at_0[0xa0];
e281682b
SM		 1934
1935 u8 type[0x8];
b4ff3a36 1936 u8 reserved_at_a8[0x18];
e281682b 1937
b4ff3a36 1938 u8 reserved_at_c0[0x8];
e281682b
SM		 1939 u8 qpn_rqn_sqn[0x18];
1940};
1941
1942struct mlx5_ifc_dct_events_bits {
b4ff3a36 1943 u8 reserved_at_0[0xc0];
e281682b 1944
b4ff3a36 1945 u8 reserved_at_c0[0x8];
e281682b
SM		 1946 u8 dct_number[0x18];
1947};
1948
1949struct mlx5_ifc_comp_event_bits {
b4ff3a36 1950 u8 reserved_at_0[0xc0];
e281682b 1951
b4ff3a36 1952 u8 reserved_at_c0[0x8];
e281682b
SM		 1953 u8 cq_number[0x18];
1954};
1955
1956enum {
1957 MLX5_QPC_STATE_RST = 0x0,
1958 MLX5_QPC_STATE_INIT = 0x1,
1959 MLX5_QPC_STATE_RTR = 0x2,
1960 MLX5_QPC_STATE_RTS = 0x3,
1961 MLX5_QPC_STATE_SQER = 0x4,
1962 MLX5_QPC_STATE_ERR = 0x6,
1963 MLX5_QPC_STATE_SQD = 0x7,
1964 MLX5_QPC_STATE_SUSPENDED = 0x9,
1965};
1966
1967enum {
1968 MLX5_QPC_ST_RC = 0x0,
1969 MLX5_QPC_ST_UC = 0x1,
1970 MLX5_QPC_ST_UD = 0x2,
1971 MLX5_QPC_ST_XRC = 0x3,
1972 MLX5_QPC_ST_DCI = 0x5,
1973 MLX5_QPC_ST_QP0 = 0x7,
1974 MLX5_QPC_ST_QP1 = 0x8,
1975 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
1976 MLX5_QPC_ST_REG_UMR = 0xc,
1977};
1978
1979enum {
1980 MLX5_QPC_PM_STATE_ARMED = 0x0,
1981 MLX5_QPC_PM_STATE_REARM = 0x1,
1982 MLX5_QPC_PM_STATE_RESERVED = 0x2,
1983 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
1984};
1985
1986enum {
1987 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
1988 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
1989};
1990
1991enum {
1992 MLX5_QPC_MTU_256_BYTES = 0x1,
1993 MLX5_QPC_MTU_512_BYTES = 0x2,
1994 MLX5_QPC_MTU_1K_BYTES = 0x3,
1995 MLX5_QPC_MTU_2K_BYTES = 0x4,
1996 MLX5_QPC_MTU_4K_BYTES = 0x5,
1997 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
1998};
1999
2000enum {
2001 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
2002 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
2003 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
2004 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
2005 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
2006 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
2007 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
2008 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
2009};
2010
2011enum {
2012 MLX5_QPC_CS_REQ_DISABLE = 0x0,
2013 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
2014 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
2015};
2016
2017enum {
2018 MLX5_QPC_CS_RES_DISABLE = 0x0,
2019 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
2020 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
2021};
2022
2023struct mlx5_ifc_qpc_bits {
2024 u8 state[0x4];
84df61eb 2025 u8 lag_tx_port_affinity[0x4];
e281682b 2026 u8 st[0x8];
b4ff3a36 2027 u8 reserved_at_10[0x3];
e281682b 2028 u8 pm_state[0x2];
b4ff3a36 2029 u8 reserved_at_15[0x7];
e281682b 2030 u8 end_padding_mode[0x2];
b4ff3a36 2031 u8 reserved_at_1e[0x2];
e281682b
SM		 2032
2033 u8 wq_signature[0x1];
2034 u8 block_lb_mc[0x1];
2035 u8 atomic_like_write_en[0x1];
2036 u8 latency_sensitive[0x1];
b4ff3a36 2037 u8 reserved_at_24[0x1];
e281682b 2038 u8 drain_sigerr[0x1];
b4ff3a36 2039 u8 reserved_at_26[0x2];
e281682b
SM		 2040 u8 pd[0x18];
2041
2042 u8 mtu[0x3];
2043 u8 log_msg_max[0x5];
b4ff3a36 2044 u8 reserved_at_48[0x1];
e281682b
SM		 2045 u8 log_rq_size[0x4];
2046 u8 log_rq_stride[0x3];
2047 u8 no_sq[0x1];
2048 u8 log_sq_size[0x4];
b4ff3a36 2049 u8 reserved_at_55[0x6];
e281682b 2050 u8 rlky[0x1];
1015c2e8 2051 u8 ulp_stateless_offload_mode[0x4];
e281682b
SM		 2052
2053 u8 counter_set_id[0x8];
2054 u8 uar_page[0x18];
2055
b4ff3a36 2056 u8 reserved_at_80[0x8];
e281682b
SM		 2057 u8 user_index[0x18];
2058
b4ff3a36 2059 u8 reserved_at_a0[0x3];
e281682b
SM		 2060 u8 log_page_size[0x5];
2061 u8 remote_qpn[0x18];
2062
2063 struct mlx5_ifc_ads_bits primary_address_path;
2064
2065 struct mlx5_ifc_ads_bits secondary_address_path;
2066
2067 u8 log_ack_req_freq[0x4];
b4ff3a36 2068 u8 reserved_at_384[0x4];
e281682b 2069 u8 log_sra_max[0x3];
b4ff3a36 2070 u8 reserved_at_38b[0x2];
e281682b
SM		 2071 u8 retry_count[0x3];
2072 u8 rnr_retry[0x3];
b4ff3a36 2073 u8 reserved_at_393[0x1];
e281682b
SM		 2074 u8 fre[0x1];
2075 u8 cur_rnr_retry[0x3];
2076 u8 cur_retry_count[0x3];
b4ff3a36 2077 u8 reserved_at_39b[0x5];
e281682b 2078
b4ff3a36 2079 u8 reserved_at_3a0[0x20];
e281682b 2080
b4ff3a36 2081 u8 reserved_at_3c0[0x8];
e281682b
SM		 2082 u8 next_send_psn[0x18];
2083
b4ff3a36 2084 u8 reserved_at_3e0[0x8];
e281682b
SM		 2085 u8 cqn_snd[0x18];
2086
09a7d9ec
SM		 2087 u8 reserved_at_400[0x8];
2088 u8 deth_sqpn[0x18];
2089
2090 u8 reserved_at_420[0x20];
e281682b 2091
b4ff3a36 2092 u8 reserved_at_440[0x8];
e281682b
SM		 2093 u8 last_acked_psn[0x18];
2094
b4ff3a36 2095 u8 reserved_at_460[0x8];
e281682b
SM		 2096 u8 ssn[0x18];
2097
b4ff3a36 2098 u8 reserved_at_480[0x8];
e281682b 2099 u8 log_rra_max[0x3];
b4ff3a36 2100 u8 reserved_at_48b[0x1];
e281682b
SM		 2101 u8 atomic_mode[0x4];
2102 u8 rre[0x1];
2103 u8 rwe[0x1];
2104 u8 rae[0x1];
b4ff3a36 2105 u8 reserved_at_493[0x1];
e281682b 2106 u8 page_offset[0x6];
b4ff3a36 2107 u8 reserved_at_49a[0x3];
e281682b
SM		 2108 u8 cd_slave_receive[0x1];
2109 u8 cd_slave_send[0x1];
2110 u8 cd_master[0x1];
2111
b4ff3a36 2112 u8 reserved_at_4a0[0x3];
e281682b
SM		 2113 u8 min_rnr_nak[0x5];
2114 u8 next_rcv_psn[0x18];
2115
b4ff3a36 2116 u8 reserved_at_4c0[0x8];
e281682b
SM		 2117 u8 xrcd[0x18];
2118
b4ff3a36 2119 u8 reserved_at_4e0[0x8];
e281682b
SM		 2120 u8 cqn_rcv[0x18];
2121
2122 u8 dbr_addr[0x40];
2123
2124 u8 q_key[0x20];
2125
b4ff3a36 2126 u8 reserved_at_560[0x5];
e281682b 2127 u8 rq_type[0x3];
7486216b 2128 u8 srqn_rmpn_xrqn[0x18];
e281682b 2129
b4ff3a36 2130 u8 reserved_at_580[0x8];
e281682b
SM		 2131 u8 rmsn[0x18];
2132
2133 u8 hw_sq_wqebb_counter[0x10];
2134 u8 sw_sq_wqebb_counter[0x10];
2135
2136 u8 hw_rq_counter[0x20];
2137
2138 u8 sw_rq_counter[0x20];
2139
b4ff3a36 2140 u8 reserved_at_600[0x20];
e281682b 2141
b4ff3a36 2142 u8 reserved_at_620[0xf];
e281682b
SM		 2143 u8 cgs[0x1];
2144 u8 cs_req[0x8];
2145 u8 cs_res[0x8];
2146
2147 u8 dc_access_key[0x40];
2148
b4ff3a36 2149 u8 reserved_at_680[0xc0];
e281682b
SM		 2150};
2151
2152struct mlx5_ifc_roce_addr_layout_bits {
2153 u8 source_l3_address[16][0x8];
2154
b4ff3a36 2155 u8 reserved_at_80[0x3];
e281682b
SM		 2156 u8 vlan_valid[0x1];
2157 u8 vlan_id[0xc];
2158 u8 source_mac_47_32[0x10];
2159
2160 u8 source_mac_31_0[0x20];
2161
b4ff3a36 2162 u8 reserved_at_c0[0x14];
e281682b
SM		 2163 u8 roce_l3_type[0x4];
2164 u8 roce_version[0x8];
2165
b4ff3a36 2166 u8 reserved_at_e0[0x20];
e281682b
SM		 2167};
2168
2169union mlx5_ifc_hca_cap_union_bits {
2170 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2171 struct mlx5_ifc_odp_cap_bits odp_cap;
2172 struct mlx5_ifc_atomic_caps_bits atomic_caps;
2173 struct mlx5_ifc_roce_cap_bits roce_cap;
2174 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2175 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
495716b1 2176 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
d6666753 2177 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
3f0393a5 2178 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
7486216b 2179 struct mlx5_ifc_qos_cap_bits qos_cap;
b4ff3a36 2180 u8 reserved_at_0[0x8000];
e281682b
SM		 2181};
2182
2183enum {
2184 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
2185 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
2186 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
9dc0b289 2187 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
7adbde20
HHZ		 2188 MLX5_FLOW_CONTEXT_ACTION_ENCAP = 0x10,
2189 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
e281682b
SM		 2190};
2191
2192struct mlx5_ifc_flow_context_bits {
b4ff3a36 2193 u8 reserved_at_0[0x20];
e281682b
SM		 2194
2195 u8 group_id[0x20];
2196
b4ff3a36 2197 u8 reserved_at_40[0x8];
e281682b
SM		 2198 u8 flow_tag[0x18];
2199
b4ff3a36 2200 u8 reserved_at_60[0x10];
e281682b
SM		 2201 u8 action[0x10];
2202
b4ff3a36 2203 u8 reserved_at_80[0x8];
e281682b
SM		 2204 u8 destination_list_size[0x18];
2205
9dc0b289
AV		 2206 u8 reserved_at_a0[0x8];
2207 u8 flow_counter_list_size[0x18];
2208
7adbde20
HHZ		 2209 u8 encap_id[0x20];
2210
2211 u8 reserved_at_e0[0x120];
e281682b
SM		 2212
2213 struct mlx5_ifc_fte_match_param_bits match_value;
2214
b4ff3a36 2215 u8 reserved_at_1200[0x600];
e281682b 2216
9dc0b289 2217 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
e281682b
SM		 2218};
2219
2220enum {
2221 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
2222 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
2223};
2224
2225struct mlx5_ifc_xrc_srqc_bits {
2226 u8 state[0x4];
2227 u8 log_xrc_srq_size[0x4];
b4ff3a36 2228 u8 reserved_at_8[0x18];
e281682b
SM		 2229
2230 u8 wq_signature[0x1];
2231 u8 cont_srq[0x1];
b4ff3a36 2232 u8 reserved_at_22[0x1];
e281682b
SM		 2233 u8 rlky[0x1];
2234 u8 basic_cyclic_rcv_wqe[0x1];
2235 u8 log_rq_stride[0x3];
2236 u8 xrcd[0x18];
2237
2238 u8 page_offset[0x6];
b4ff3a36 2239 u8 reserved_at_46[0x2];
e281682b
SM		 2240 u8 cqn[0x18];
2241
b4ff3a36 2242 u8 reserved_at_60[0x20];
e281682b
SM		 2243
2244 u8 user_index_equal_xrc_srqn[0x1];
b4ff3a36 2245 u8 reserved_at_81[0x1];
e281682b
SM		 2246 u8 log_page_size[0x6];
2247 u8 user_index[0x18];
2248
b4ff3a36 2249 u8 reserved_at_a0[0x20];
e281682b 2250
b4ff3a36 2251 u8 reserved_at_c0[0x8];
e281682b
SM		 2252 u8 pd[0x18];
2253
2254 u8 lwm[0x10];
2255 u8 wqe_cnt[0x10];
2256
b4ff3a36 2257 u8 reserved_at_100[0x40];
e281682b
SM		 2258
2259 u8 db_record_addr_h[0x20];
2260
2261 u8 db_record_addr_l[0x1e];
b4ff3a36 2262 u8 reserved_at_17e[0x2];
e281682b 2263
b4ff3a36 2264 u8 reserved_at_180[0x80];
e281682b
SM		 2265};
2266
2267struct mlx5_ifc_traffic_counter_bits {
2268 u8 packets[0x40];
2269
2270 u8 octets[0x40];
2271};
2272
2273struct mlx5_ifc_tisc_bits {
84df61eb
AH		 2274 u8 strict_lag_tx_port_affinity[0x1];
2275 u8 reserved_at_1[0x3];
2276 u8 lag_tx_port_affinity[0x04];
2277
2278 u8 reserved_at_8[0x4];
e281682b 2279 u8 prio[0x4];
b4ff3a36 2280 u8 reserved_at_10[0x10];
e281682b 2281
b4ff3a36 2282 u8 reserved_at_20[0x100];
e281682b 2283
b4ff3a36 2284 u8 reserved_at_120[0x8];
e281682b
SM		 2285 u8 transport_domain[0x18];
2286
b4ff3a36 2287 u8 reserved_at_140[0x3c0];
e281682b
SM		 2288};
2289
2290enum {
2291 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2292 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2293};
2294
2295enum {
2296 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2297 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2298};
2299
2300enum {
2be6967c
SM		 2301 MLX5_RX_HASH_FN_NONE = 0x0,
2302 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
2303 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
e281682b
SM		 2304};
2305
2306enum {
2307 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1,
2308 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2,
2309};
2310
2311struct mlx5_ifc_tirc_bits {
b4ff3a36 2312 u8 reserved_at_0[0x20];
e281682b
SM		 2313
2314 u8 disp_type[0x4];
b4ff3a36 2315 u8 reserved_at_24[0x1c];
e281682b 2316
b4ff3a36 2317 u8 reserved_at_40[0x40];
e281682b 2318
b4ff3a36 2319 u8 reserved_at_80[0x4];
e281682b
SM		 2320 u8 lro_timeout_period_usecs[0x10];
2321 u8 lro_enable_mask[0x4];
2322 u8 lro_max_ip_payload_size[0x8];
2323
b4ff3a36 2324 u8 reserved_at_a0[0x40];
e281682b 2325
b4ff3a36 2326 u8 reserved_at_e0[0x8];
e281682b
SM		 2327 u8 inline_rqn[0x18];
2328
2329 u8 rx_hash_symmetric[0x1];
b4ff3a36 2330 u8 reserved_at_101[0x1];
e281682b 2331 u8 tunneled_offload_en[0x1];
b4ff3a36 2332 u8 reserved_at_103[0x5];
e281682b
SM		 2333 u8 indirect_table[0x18];
2334
2335 u8 rx_hash_fn[0x4];
b4ff3a36 2336 u8 reserved_at_124[0x2];
e281682b
SM		 2337 u8 self_lb_block[0x2];
2338 u8 transport_domain[0x18];
2339
2340 u8 rx_hash_toeplitz_key[10][0x20];
2341
2342 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2343
2344 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2345
b4ff3a36 2346 u8 reserved_at_2c0[0x4c0];
e281682b
SM		 2347};
2348
2349enum {
2350 MLX5_SRQC_STATE_GOOD = 0x0,
2351 MLX5_SRQC_STATE_ERROR = 0x1,
2352};
2353
2354struct mlx5_ifc_srqc_bits {
2355 u8 state[0x4];
2356 u8 log_srq_size[0x4];
b4ff3a36 2357 u8 reserved_at_8[0x18];
e281682b
SM		 2358
2359 u8 wq_signature[0x1];
2360 u8 cont_srq[0x1];
b4ff3a36 2361 u8 reserved_at_22[0x1];
e281682b 2362 u8 rlky[0x1];
b4ff3a36 2363 u8 reserved_at_24[0x1];
e281682b
SM		 2364 u8 log_rq_stride[0x3];
2365 u8 xrcd[0x18];
2366
2367 u8 page_offset[0x6];
b4ff3a36 2368 u8 reserved_at_46[0x2];
e281682b
SM		 2369 u8 cqn[0x18];
2370
b4ff3a36 2371 u8 reserved_at_60[0x20];
e281682b 2372
b4ff3a36 2373 u8 reserved_at_80[0x2];
e281682b 2374 u8 log_page_size[0x6];
b4ff3a36 2375 u8 reserved_at_88[0x18];
e281682b 2376
b4ff3a36 2377 u8 reserved_at_a0[0x20];
e281682b 2378
b4ff3a36 2379 u8 reserved_at_c0[0x8];
e281682b
SM		 2380 u8 pd[0x18];
2381
2382 u8 lwm[0x10];
2383 u8 wqe_cnt[0x10];
2384
b4ff3a36 2385 u8 reserved_at_100[0x40];
e281682b 2386
01949d01 2387 u8 dbr_addr[0x40];
e281682b 2388
b4ff3a36 2389 u8 reserved_at_180[0x80];
e281682b
SM		 2390};
2391
2392enum {
2393 MLX5_SQC_STATE_RST = 0x0,
2394 MLX5_SQC_STATE_RDY = 0x1,
2395 MLX5_SQC_STATE_ERR = 0x3,
2396};
2397
2398struct mlx5_ifc_sqc_bits {
2399 u8 rlky[0x1];
2400 u8 cd_master[0x1];
2401 u8 fre[0x1];
2402 u8 flush_in_error_en[0x1];
cff92d7c
HHZ		 2403 u8 reserved_at_4[0x1];
2404 u8 min_wqe_inline_mode[0x3];
e281682b 2405 u8 state[0x4];
7d5e1423
SM		 2406 u8 reg_umr[0x1];
2407 u8 reserved_at_d[0x13];
e281682b 2408
b4ff3a36 2409 u8 reserved_at_20[0x8];
e281682b
SM		 2410 u8 user_index[0x18];
2411
b4ff3a36 2412 u8 reserved_at_40[0x8];
e281682b
SM		 2413 u8 cqn[0x18];
2414
7486216b 2415 u8 reserved_at_60[0x90];
e281682b 2416
7486216b 2417 u8 packet_pacing_rate_limit_index[0x10];
e281682b 2418 u8 tis_lst_sz[0x10];
b4ff3a36 2419 u8 reserved_at_110[0x10];
e281682b 2420
b4ff3a36 2421 u8 reserved_at_120[0x40];
e281682b 2422
b4ff3a36 2423 u8 reserved_at_160[0x8];
e281682b
SM		 2424 u8 tis_num_0[0x18];
2425
2426 struct mlx5_ifc_wq_bits wq;
2427};
2428
813f8540
MHY		 2429enum {
2430 SCHEDULING_CONTEXT_ELEMENT_TYPE_TSAR = 0x0,
2431 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT = 0x1,
2432 SCHEDULING_CONTEXT_ELEMENT_TYPE_VPORT_TC = 0x2,
2433 SCHEDULING_CONTEXT_ELEMENT_TYPE_PARA_VPORT_TC = 0x3,
2434};
2435
2436struct mlx5_ifc_scheduling_context_bits {
2437 u8 element_type[0x8];
2438 u8 reserved_at_8[0x18];
2439
2440 u8 element_attributes[0x20];
2441
2442 u8 parent_element_id[0x20];
2443
2444 u8 reserved_at_60[0x40];
2445
2446 u8 bw_share[0x20];
2447
2448 u8 max_average_bw[0x20];
2449
2450 u8 reserved_at_e0[0x120];
2451};
2452
e281682b 2453struct mlx5_ifc_rqtc_bits {
b4ff3a36 2454 u8 reserved_at_0[0xa0];
e281682b 2455
b4ff3a36 2456 u8 reserved_at_a0[0x10];
e281682b
SM		 2457 u8 rqt_max_size[0x10];
2458
b4ff3a36 2459 u8 reserved_at_c0[0x10];
e281682b
SM		 2460 u8 rqt_actual_size[0x10];
2461
b4ff3a36 2462 u8 reserved_at_e0[0x6a0];
e281682b
SM		 2463
2464 struct mlx5_ifc_rq_num_bits rq_num[0];
2465};
2466
2467enum {
2468 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2469 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2470};
2471
2472enum {
2473 MLX5_RQC_STATE_RST = 0x0,
2474 MLX5_RQC_STATE_RDY = 0x1,
2475 MLX5_RQC_STATE_ERR = 0x3,
2476};
2477
2478struct mlx5_ifc_rqc_bits {
2479 u8 rlky[0x1];
7d5e1423
SM		 2480 u8 reserved_at_1[0x1];
2481 u8 scatter_fcs[0x1];
e281682b
SM		 2482 u8 vsd[0x1];
2483 u8 mem_rq_type[0x4];
2484 u8 state[0x4];
b4ff3a36 2485 u8 reserved_at_c[0x1];
e281682b 2486 u8 flush_in_error_en[0x1];
b4ff3a36 2487 u8 reserved_at_e[0x12];
e281682b 2488
b4ff3a36 2489 u8 reserved_at_20[0x8];
e281682b
SM		 2490 u8 user_index[0x18];
2491
b4ff3a36 2492 u8 reserved_at_40[0x8];
e281682b
SM		 2493 u8 cqn[0x18];
2494
2495 u8 counter_set_id[0x8];
b4ff3a36 2496 u8 reserved_at_68[0x18];
e281682b 2497
b4ff3a36 2498 u8 reserved_at_80[0x8];
e281682b
SM		 2499 u8 rmpn[0x18];
2500
b4ff3a36 2501 u8 reserved_at_a0[0xe0];
e281682b
SM		 2502
2503 struct mlx5_ifc_wq_bits wq;
2504};
2505
2506enum {
2507 MLX5_RMPC_STATE_RDY = 0x1,
2508 MLX5_RMPC_STATE_ERR = 0x3,
2509};
2510
2511struct mlx5_ifc_rmpc_bits {
b4ff3a36 2512 u8 reserved_at_0[0x8];
e281682b 2513 u8 state[0x4];
b4ff3a36 2514 u8 reserved_at_c[0x14];
e281682b
SM		 2515
2516 u8 basic_cyclic_rcv_wqe[0x1];
b4ff3a36 2517 u8 reserved_at_21[0x1f];
e281682b 2518
b4ff3a36 2519 u8 reserved_at_40[0x140];
e281682b
SM		 2520
2521 struct mlx5_ifc_wq_bits wq;
2522};
2523
e281682b 2524struct mlx5_ifc_nic_vport_context_bits {
cff92d7c
HHZ		 2525 u8 reserved_at_0[0x5];
2526 u8 min_wqe_inline_mode[0x3];
2527 u8 reserved_at_8[0x17];
e281682b
SM		 2528 u8 roce_en[0x1];
2529
d82b7318 2530 u8 arm_change_event[0x1];
b4ff3a36 2531 u8 reserved_at_21[0x1a];
d82b7318
SM		 2532 u8 event_on_mtu[0x1];
2533 u8 event_on_promisc_change[0x1];
2534 u8 event_on_vlan_change[0x1];
2535 u8 event_on_mc_address_change[0x1];
2536 u8 event_on_uc_address_change[0x1];
e281682b 2537
b4ff3a36 2538 u8 reserved_at_40[0xf0];
d82b7318
SM		 2539
2540 u8 mtu[0x10];
2541
9efa7525
AS		 2542 u8 system_image_guid[0x40];
2543 u8 port_guid[0x40];
2544 u8 node_guid[0x40];
2545
b4ff3a36 2546 u8 reserved_at_200[0x140];
9efa7525 2547 u8 qkey_violation_counter[0x10];
b4ff3a36 2548 u8 reserved_at_350[0x430];
d82b7318
SM		 2549
2550 u8 promisc_uc[0x1];
2551 u8 promisc_mc[0x1];
2552 u8 promisc_all[0x1];
b4ff3a36 2553 u8 reserved_at_783[0x2];
e281682b 2554 u8 allowed_list_type[0x3];
b4ff3a36 2555 u8 reserved_at_788[0xc];
e281682b
SM		 2556 u8 allowed_list_size[0xc];
2557
2558 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2559
b4ff3a36 2560 u8 reserved_at_7e0[0x20];
e281682b
SM		 2561
2562 u8 current_uc_mac_address[0][0x40];
2563};
2564
2565enum {
2566 MLX5_MKC_ACCESS_MODE_PA = 0x0,
2567 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
2568 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
bcda1aca 2569 MLX5_MKC_ACCESS_MODE_KSM = 0x3,
e281682b
SM		 2570};
2571
2572struct mlx5_ifc_mkc_bits {
b4ff3a36 2573 u8 reserved_at_0[0x1];
e281682b 2574 u8 free[0x1];
b4ff3a36 2575 u8 reserved_at_2[0xd];
e281682b
SM		 2576 u8 small_fence_on_rdma_read_response[0x1];
2577 u8 umr_en[0x1];
2578 u8 a[0x1];
2579 u8 rw[0x1];
2580 u8 rr[0x1];
2581 u8 lw[0x1];
2582 u8 lr[0x1];
2583 u8 access_mode[0x2];
b4ff3a36 2584 u8 reserved_at_18[0x8];
e281682b
SM		 2585
2586 u8 qpn[0x18];
2587 u8 mkey_7_0[0x8];
2588
b4ff3a36 2589 u8 reserved_at_40[0x20];
e281682b
SM		 2590
2591 u8 length64[0x1];
2592 u8 bsf_en[0x1];
2593 u8 sync_umr[0x1];
b4ff3a36 2594 u8 reserved_at_63[0x2];
e281682b 2595 u8 expected_sigerr_count[0x1];
b4ff3a36 2596 u8 reserved_at_66[0x1];
e281682b
SM		 2597 u8 en_rinval[0x1];
2598 u8 pd[0x18];
2599
2600 u8 start_addr[0x40];
2601
2602 u8 len[0x40];
2603
2604 u8 bsf_octword_size[0x20];
2605
b4ff3a36 2606 u8 reserved_at_120[0x80];
e281682b
SM		 2607
2608 u8 translations_octword_size[0x20];
2609
b4ff3a36 2610 u8 reserved_at_1c0[0x1b];
e281682b
SM		 2611 u8 log_page_size[0x5];
2612
b4ff3a36 2613 u8 reserved_at_1e0[0x20];
e281682b
SM		 2614};
2615
2616struct mlx5_ifc_pkey_bits {
b4ff3a36 2617 u8 reserved_at_0[0x10];
e281682b
SM		 2618 u8 pkey[0x10];
2619};
2620
2621struct mlx5_ifc_array128_auto_bits {
2622 u8 array128_auto[16][0x8];
2623};
2624
2625struct mlx5_ifc_hca_vport_context_bits {
2626 u8 field_select[0x20];
2627
b4ff3a36 2628 u8 reserved_at_20[0xe0];
e281682b
SM		 2629
2630 u8 sm_virt_aware[0x1];
2631 u8 has_smi[0x1];
2632 u8 has_raw[0x1];
2633 u8 grh_required[0x1];
b4ff3a36 2634 u8 reserved_at_104[0xc];
707c4602
MD		 2635 u8 port_physical_state[0x4];
2636 u8 vport_state_policy[0x4];
2637 u8 port_state[0x4];
e281682b
SM		 2638 u8 vport_state[0x4];
2639
b4ff3a36 2640 u8 reserved_at_120[0x20];
707c4602
MD		 2641
2642 u8 system_image_guid[0x40];
e281682b
SM		 2643
2644 u8 port_guid[0x40];
2645
2646 u8 node_guid[0x40];
2647
2648 u8 cap_mask1[0x20];
2649
2650 u8 cap_mask1_field_select[0x20];
2651
2652 u8 cap_mask2[0x20];
2653
2654 u8 cap_mask2_field_select[0x20];
2655
b4ff3a36 2656 u8 reserved_at_280[0x80];
e281682b
SM		 2657
2658 u8 lid[0x10];
b4ff3a36 2659 u8 reserved_at_310[0x4];
e281682b
SM		 2660 u8 init_type_reply[0x4];
2661 u8 lmc[0x3];
2662 u8 subnet_timeout[0x5];
2663
2664 u8 sm_lid[0x10];
2665 u8 sm_sl[0x4];
b4ff3a36 2666 u8 reserved_at_334[0xc];
e281682b
SM		 2667
2668 u8 qkey_violation_counter[0x10];
2669 u8 pkey_violation_counter[0x10];
2670
b4ff3a36 2671 u8 reserved_at_360[0xca0];
e281682b
SM		 2672};
2673
d6666753 2674struct mlx5_ifc_esw_vport_context_bits {
b4ff3a36 2675 u8 reserved_at_0[0x3];
d6666753
SM		 2676 u8 vport_svlan_strip[0x1];
2677 u8 vport_cvlan_strip[0x1];
2678 u8 vport_svlan_insert[0x1];
2679 u8 vport_cvlan_insert[0x2];
b4ff3a36 2680 u8 reserved_at_8[0x18];
d6666753 2681
b4ff3a36 2682 u8 reserved_at_20[0x20];
d6666753
SM		 2683
2684 u8 svlan_cfi[0x1];
2685 u8 svlan_pcp[0x3];
2686 u8 svlan_id[0xc];
2687 u8 cvlan_cfi[0x1];
2688 u8 cvlan_pcp[0x3];
2689 u8 cvlan_id[0xc];
2690
b4ff3a36 2691 u8 reserved_at_60[0x7a0];
d6666753
SM		 2692};
2693
e281682b
SM		 2694enum {
2695 MLX5_EQC_STATUS_OK = 0x0,
2696 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
2697};
2698
2699enum {
2700 MLX5_EQC_ST_ARMED = 0x9,
2701 MLX5_EQC_ST_FIRED = 0xa,
2702};
2703
2704struct mlx5_ifc_eqc_bits {
2705 u8 status[0x4];
b4ff3a36 2706 u8 reserved_at_4[0x9];
e281682b
SM		 2707 u8 ec[0x1];
2708 u8 oi[0x1];
b4ff3a36 2709 u8 reserved_at_f[0x5];
e281682b 2710 u8 st[0x4];
b4ff3a36 2711 u8 reserved_at_18[0x8];
e281682b 2712
b4ff3a36 2713 u8 reserved_at_20[0x20];
e281682b 2714
b4ff3a36 2715 u8 reserved_at_40[0x14];
e281682b 2716 u8 page_offset[0x6];
b4ff3a36 2717 u8 reserved_at_5a[0x6];
e281682b 2718
b4ff3a36 2719 u8 reserved_at_60[0x3];
e281682b
SM		 2720 u8 log_eq_size[0x5];
2721 u8 uar_page[0x18];
2722
b4ff3a36 2723 u8 reserved_at_80[0x20];
e281682b 2724
b4ff3a36 2725 u8 reserved_at_a0[0x18];
e281682b
SM		 2726 u8 intr[0x8];
2727
b4ff3a36 2728 u8 reserved_at_c0[0x3];
e281682b 2729 u8 log_page_size[0x5];
b4ff3a36 2730 u8 reserved_at_c8[0x18];
e281682b 2731
b4ff3a36 2732 u8 reserved_at_e0[0x60];
e281682b 2733
b4ff3a36 2734 u8 reserved_at_140[0x8];
e281682b
SM		 2735 u8 consumer_counter[0x18];
2736
b4ff3a36 2737 u8 reserved_at_160[0x8];
e281682b
SM		 2738 u8 producer_counter[0x18];
2739
b4ff3a36 2740 u8 reserved_at_180[0x80];
e281682b
SM		 2741};
2742
2743enum {
2744 MLX5_DCTC_STATE_ACTIVE = 0x0,
2745 MLX5_DCTC_STATE_DRAINING = 0x1,
2746 MLX5_DCTC_STATE_DRAINED = 0x2,
2747};
2748
2749enum {
2750 MLX5_DCTC_CS_RES_DISABLE = 0x0,
2751 MLX5_DCTC_CS_RES_NA = 0x1,
2752 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
2753};
2754
2755enum {
2756 MLX5_DCTC_MTU_256_BYTES = 0x1,
2757 MLX5_DCTC_MTU_512_BYTES = 0x2,
2758 MLX5_DCTC_MTU_1K_BYTES = 0x3,
2759 MLX5_DCTC_MTU_2K_BYTES = 0x4,
2760 MLX5_DCTC_MTU_4K_BYTES = 0x5,
2761};
2762
2763struct mlx5_ifc_dctc_bits {
b4ff3a36 2764 u8 reserved_at_0[0x4];
e281682b 2765 u8 state[0x4];
b4ff3a36 2766 u8 reserved_at_8[0x18];
e281682b 2767
b4ff3a36 2768 u8 reserved_at_20[0x8];
e281682b
SM		 2769 u8 user_index[0x18];
2770
b4ff3a36 2771 u8 reserved_at_40[0x8];
e281682b
SM		 2772 u8 cqn[0x18];
2773
2774 u8 counter_set_id[0x8];
2775 u8 atomic_mode[0x4];
2776 u8 rre[0x1];
2777 u8 rwe[0x1];
2778 u8 rae[0x1];
2779 u8 atomic_like_write_en[0x1];
2780 u8 latency_sensitive[0x1];
2781 u8 rlky[0x1];
2782 u8 free_ar[0x1];
b4ff3a36 2783 u8 reserved_at_73[0xd];
e281682b 2784
b4ff3a36 2785 u8 reserved_at_80[0x8];
e281682b 2786 u8 cs_res[0x8];
b4ff3a36 2787 u8 reserved_at_90[0x3];
e281682b 2788 u8 min_rnr_nak[0x5];
b4ff3a36 2789 u8 reserved_at_98[0x8];
e281682b 2790
b4ff3a36 2791 u8 reserved_at_a0[0x8];
7486216b 2792 u8 srqn_xrqn[0x18];
e281682b 2793
b4ff3a36 2794 u8 reserved_at_c0[0x8];
e281682b
SM		 2795 u8 pd[0x18];
2796
2797 u8 tclass[0x8];
b4ff3a36 2798 u8 reserved_at_e8[0x4];
e281682b
SM		 2799 u8 flow_label[0x14];
2800
2801 u8 dc_access_key[0x40];
2802
b4ff3a36 2803 u8 reserved_at_140[0x5];
e281682b
SM		 2804 u8 mtu[0x3];
2805 u8 port[0x8];
2806 u8 pkey_index[0x10];
2807
b4ff3a36 2808 u8 reserved_at_160[0x8];
e281682b 2809 u8 my_addr_index[0x8];
b4ff3a36 2810 u8 reserved_at_170[0x8];
e281682b
SM		 2811 u8 hop_limit[0x8];
2812
2813 u8 dc_access_key_violation_count[0x20];
2814
b4ff3a36 2815 u8 reserved_at_1a0[0x14];
e281682b
SM		 2816 u8 dei_cfi[0x1];
2817 u8 eth_prio[0x3];
2818 u8 ecn[0x2];
2819 u8 dscp[0x6];
2820
b4ff3a36 2821 u8 reserved_at_1c0[0x40];
e281682b
SM		 2822};
2823
2824enum {
2825 MLX5_CQC_STATUS_OK = 0x0,
2826 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
2827 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
2828};
2829
2830enum {
2831 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
2832 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
2833};
2834
2835enum {
2836 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
2837 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
2838 MLX5_CQC_ST_FIRED = 0xa,
2839};
2840
7d5e1423
SM		 2841enum {
2842 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
2843 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
7486216b 2844 MLX5_CQ_PERIOD_NUM_MODES
7d5e1423
SM		 2845};
2846
e281682b
SM		 2847struct mlx5_ifc_cqc_bits {
2848 u8 status[0x4];
b4ff3a36 2849 u8 reserved_at_4[0x4];
e281682b
SM		 2850 u8 cqe_sz[0x3];
2851 u8 cc[0x1];
b4ff3a36 2852 u8 reserved_at_c[0x1];
e281682b
SM		 2853 u8 scqe_break_moderation_en[0x1];
2854 u8 oi[0x1];
7d5e1423
SM		 2855 u8 cq_period_mode[0x2];
2856 u8 cqe_comp_en[0x1];
e281682b
SM		 2857 u8 mini_cqe_res_format[0x2];
2858 u8 st[0x4];
b4ff3a36 2859 u8 reserved_at_18[0x8];
e281682b 2860
b4ff3a36 2861 u8 reserved_at_20[0x20];
e281682b 2862
b4ff3a36 2863 u8 reserved_at_40[0x14];
e281682b 2864 u8 page_offset[0x6];
b4ff3a36 2865 u8 reserved_at_5a[0x6];
e281682b 2866
b4ff3a36 2867 u8 reserved_at_60[0x3];
e281682b
SM		 2868 u8 log_cq_size[0x5];
2869 u8 uar_page[0x18];
2870
b4ff3a36 2871 u8 reserved_at_80[0x4];
e281682b
SM		 2872 u8 cq_period[0xc];
2873 u8 cq_max_count[0x10];
2874
b4ff3a36 2875 u8 reserved_at_a0[0x18];
e281682b
SM		 2876 u8 c_eqn[0x8];
2877
b4ff3a36 2878 u8 reserved_at_c0[0x3];
e281682b 2879 u8 log_page_size[0x5];
b4ff3a36 2880 u8 reserved_at_c8[0x18];
e281682b 2881
b4ff3a36 2882 u8 reserved_at_e0[0x20];
e281682b 2883
b4ff3a36 2884 u8 reserved_at_100[0x8];
e281682b
SM		 2885 u8 last_notified_index[0x18];
2886
b4ff3a36 2887 u8 reserved_at_120[0x8];
e281682b
SM		 2888 u8 last_solicit_index[0x18];
2889
b4ff3a36 2890 u8 reserved_at_140[0x8];
e281682b
SM		 2891 u8 consumer_counter[0x18];
2892
b4ff3a36 2893 u8 reserved_at_160[0x8];
e281682b
SM		 2894 u8 producer_counter[0x18];
2895
b4ff3a36 2896 u8 reserved_at_180[0x40];
e281682b
SM		 2897
2898 u8 dbr_addr[0x40];
2899};
2900
2901union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2902 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2903 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2904 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
b4ff3a36 2905 u8 reserved_at_0[0x800];
e281682b
SM		 2906};
2907
2908struct mlx5_ifc_query_adapter_param_block_bits {
b4ff3a36 2909 u8 reserved_at_0[0xc0];
e281682b 2910
b4ff3a36 2911 u8 reserved_at_c0[0x8];
211e6c80
MD		 2912 u8 ieee_vendor_id[0x18];
2913
b4ff3a36 2914 u8 reserved_at_e0[0x10];
e281682b
SM		 2915 u8 vsd_vendor_id[0x10];
2916
2917 u8 vsd[208][0x8];
2918
2919 u8 vsd_contd_psid[16][0x8];
2920};
2921
7486216b
SM		 2922enum {
2923 MLX5_XRQC_STATE_GOOD = 0x0,
2924 MLX5_XRQC_STATE_ERROR = 0x1,
2925};
2926
2927enum {
2928 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
2929 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
2930};
2931
2932enum {
2933 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
2934};
2935
2936struct mlx5_ifc_tag_matching_topology_context_bits {
2937 u8 log_matching_list_sz[0x4];
2938 u8 reserved_at_4[0xc];
2939 u8 append_next_index[0x10];
2940
2941 u8 sw_phase_cnt[0x10];
2942 u8 hw_phase_cnt[0x10];
2943
2944 u8 reserved_at_40[0x40];
2945};
2946
2947struct mlx5_ifc_xrqc_bits {
2948 u8 state[0x4];
2949 u8 rlkey[0x1];
2950 u8 reserved_at_5[0xf];
2951 u8 topology[0x4];
2952 u8 reserved_at_18[0x4];
2953 u8 offload[0x4];
2954
2955 u8 reserved_at_20[0x8];
2956 u8 user_index[0x18];
2957
2958 u8 reserved_at_40[0x8];
2959 u8 cqn[0x18];
2960
2961 u8 reserved_at_60[0xa0];
2962
2963 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
2964
5579e151 2965 u8 reserved_at_180[0x880];
7486216b
SM		 2966
2967 struct mlx5_ifc_wq_bits wq;
2968};
2969
e281682b
SM		 2970union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2971 struct mlx5_ifc_modify_field_select_bits modify_field_select;
2972 struct mlx5_ifc_resize_field_select_bits resize_field_select;
b4ff3a36 2973 u8 reserved_at_0[0x20];
e281682b
SM		 2974};
2975
2976union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2977 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2978 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2979 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
b4ff3a36 2980 u8 reserved_at_0[0x20];
e281682b
SM		 2981};
2982
2983union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
2984 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
2985 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
2986 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
2987 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
2988 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
2989 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
2990 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
1c64bf6f 2991 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b 2992 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
d8dc0508 2993 struct mlx5_ifc_phys_layer_statistical_cntrs_bits phys_layer_statistical_cntrs;
b4ff3a36 2994 u8 reserved_at_0[0x7c0];
e281682b
SM		 2995};
2996
8ed1a630
GP		 2997union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits {
2998 struct mlx5_ifc_pcie_perf_cntrs_grp_data_layout_bits pcie_perf_cntrs_grp_data_layout;
2999 u8 reserved_at_0[0x7c0];
3000};
3001
e281682b
SM		 3002union mlx5_ifc_event_auto_bits {
3003 struct mlx5_ifc_comp_event_bits comp_event;
3004 struct mlx5_ifc_dct_events_bits dct_events;
3005 struct mlx5_ifc_qp_events_bits qp_events;
3006 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
3007 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
3008 struct mlx5_ifc_cq_error_bits cq_error;
3009 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
3010 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
3011 struct mlx5_ifc_gpio_event_bits gpio_event;
3012 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
3013 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
3014 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
b4ff3a36 3015 u8 reserved_at_0[0xe0];
e281682b
SM		 3016};
3017
3018struct mlx5_ifc_health_buffer_bits {
b4ff3a36 3019 u8 reserved_at_0[0x100];
e281682b
SM		 3020
3021 u8 assert_existptr[0x20];
3022
3023 u8 assert_callra[0x20];
3024
b4ff3a36 3025 u8 reserved_at_140[0x40];
e281682b
SM		 3026
3027 u8 fw_version[0x20];
3028
3029 u8 hw_id[0x20];
3030
b4ff3a36 3031 u8 reserved_at_1c0[0x20];
e281682b
SM		 3032
3033 u8 irisc_index[0x8];
3034 u8 synd[0x8];
3035 u8 ext_synd[0x10];
3036};
3037
3038struct mlx5_ifc_register_loopback_control_bits {
3039 u8 no_lb[0x1];
b4ff3a36 3040 u8 reserved_at_1[0x7];
e281682b 3041 u8 port[0x8];
b4ff3a36 3042 u8 reserved_at_10[0x10];
e281682b 3043
b4ff3a36 3044 u8 reserved_at_20[0x60];
e281682b
SM		 3045};
3046
813f8540
MHY		 3047struct mlx5_ifc_vport_tc_element_bits {
3048 u8 traffic_class[0x4];
3049 u8 reserved_at_4[0xc];
3050 u8 vport_number[0x10];
3051};
3052
3053struct mlx5_ifc_vport_element_bits {
3054 u8 reserved_at_0[0x10];
3055 u8 vport_number[0x10];
3056};
3057
3058enum {
3059 TSAR_ELEMENT_TSAR_TYPE_DWRR = 0x0,
3060 TSAR_ELEMENT_TSAR_TYPE_ROUND_ROBIN = 0x1,
3061 TSAR_ELEMENT_TSAR_TYPE_ETS = 0x2,
3062};
3063
3064struct mlx5_ifc_tsar_element_bits {
3065 u8 reserved_at_0[0x8];
3066 u8 tsar_type[0x8];
3067 u8 reserved_at_10[0x10];
3068};
3069
e281682b
SM		 3070struct mlx5_ifc_teardown_hca_out_bits {
3071 u8 status[0x8];
b4ff3a36 3072 u8 reserved_at_8[0x18];
e281682b
SM		 3073
3074 u8 syndrome[0x20];
3075
b4ff3a36 3076 u8 reserved_at_40[0x40];
e281682b
SM		 3077};
3078
3079enum {
3080 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
3081 MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE = 0x1,
3082};
3083
3084struct mlx5_ifc_teardown_hca_in_bits {
3085 u8 opcode[0x10];
b4ff3a36 3086 u8 reserved_at_10[0x10];
e281682b 3087
b4ff3a36 3088 u8 reserved_at_20[0x10];
e281682b
SM		 3089 u8 op_mod[0x10];
3090
b4ff3a36 3091 u8 reserved_at_40[0x10];
e281682b
SM		 3092 u8 profile[0x10];
3093
b4ff3a36 3094 u8 reserved_at_60[0x20];
e281682b
SM		 3095};
3096
3097struct mlx5_ifc_sqerr2rts_qp_out_bits {
3098 u8 status[0x8];
b4ff3a36 3099 u8 reserved_at_8[0x18];
e281682b
SM		 3100
3101 u8 syndrome[0x20];
3102
b4ff3a36 3103 u8 reserved_at_40[0x40];
e281682b
SM		 3104};
3105
3106struct mlx5_ifc_sqerr2rts_qp_in_bits {
3107 u8 opcode[0x10];
b4ff3a36 3108 u8 reserved_at_10[0x10];
e281682b 3109
b4ff3a36 3110 u8 reserved_at_20[0x10];
e281682b
SM		 3111 u8 op_mod[0x10];
3112
b4ff3a36 3113 u8 reserved_at_40[0x8];
e281682b
SM		 3114 u8 qpn[0x18];
3115
b4ff3a36 3116 u8 reserved_at_60[0x20];
e281682b
SM		 3117
3118 u8 opt_param_mask[0x20];
3119
b4ff3a36 3120 u8 reserved_at_a0[0x20];
e281682b
SM		 3121
3122 struct mlx5_ifc_qpc_bits qpc;
3123
b4ff3a36 3124 u8 reserved_at_800[0x80];
e281682b
SM		 3125};
3126
3127struct mlx5_ifc_sqd2rts_qp_out_bits {
3128 u8 status[0x8];
b4ff3a36 3129 u8 reserved_at_8[0x18];
e281682b
SM		 3130
3131 u8 syndrome[0x20];
3132
b4ff3a36 3133 u8 reserved_at_40[0x40];
e281682b
SM		 3134};
3135
3136struct mlx5_ifc_sqd2rts_qp_in_bits {
3137 u8 opcode[0x10];
b4ff3a36 3138 u8 reserved_at_10[0x10];
e281682b 3139
b4ff3a36 3140 u8 reserved_at_20[0x10];
e281682b
SM		 3141 u8 op_mod[0x10];
3142
b4ff3a36 3143 u8 reserved_at_40[0x8];
e281682b
SM		 3144 u8 qpn[0x18];
3145
b4ff3a36 3146 u8 reserved_at_60[0x20];
e281682b
SM		 3147
3148 u8 opt_param_mask[0x20];
3149
b4ff3a36 3150 u8 reserved_at_a0[0x20];
e281682b
SM		 3151
3152 struct mlx5_ifc_qpc_bits qpc;
3153
b4ff3a36 3154 u8 reserved_at_800[0x80];
e281682b
SM		 3155};
3156
3157struct mlx5_ifc_set_roce_address_out_bits {
3158 u8 status[0x8];
b4ff3a36 3159 u8 reserved_at_8[0x18];
e281682b
SM		 3160
3161 u8 syndrome[0x20];
3162
b4ff3a36 3163 u8 reserved_at_40[0x40];
e281682b
SM		 3164};
3165
3166struct mlx5_ifc_set_roce_address_in_bits {
3167 u8 opcode[0x10];
b4ff3a36 3168 u8 reserved_at_10[0x10];
e281682b 3169
b4ff3a36 3170 u8 reserved_at_20[0x10];
e281682b
SM		 3171 u8 op_mod[0x10];
3172
3173 u8 roce_address_index[0x10];
b4ff3a36 3174 u8 reserved_at_50[0x10];
e281682b 3175
b4ff3a36 3176 u8 reserved_at_60[0x20];
e281682b
SM		 3177
3178 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3179};
3180
3181struct mlx5_ifc_set_mad_demux_out_bits {
3182 u8 status[0x8];
b4ff3a36 3183 u8 reserved_at_8[0x18];
e281682b
SM		 3184
3185 u8 syndrome[0x20];
3186
b4ff3a36 3187 u8 reserved_at_40[0x40];
e281682b
SM		 3188};
3189
3190enum {
3191 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
3192 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
3193};
3194
3195struct mlx5_ifc_set_mad_demux_in_bits {
3196 u8 opcode[0x10];
b4ff3a36 3197 u8 reserved_at_10[0x10];
e281682b 3198
b4ff3a36 3199 u8 reserved_at_20[0x10];
e281682b
SM		 3200 u8 op_mod[0x10];
3201
b4ff3a36 3202 u8 reserved_at_40[0x20];
e281682b 3203
b4ff3a36 3204 u8 reserved_at_60[0x6];
e281682b 3205 u8 demux_mode[0x2];
b4ff3a36 3206 u8 reserved_at_68[0x18];
e281682b
SM		 3207};
3208
3209struct mlx5_ifc_set_l2_table_entry_out_bits {
3210 u8 status[0x8];
b4ff3a36 3211 u8 reserved_at_8[0x18];
e281682b
SM		 3212
3213 u8 syndrome[0x20];
3214
b4ff3a36 3215 u8 reserved_at_40[0x40];
e281682b
SM		 3216};
3217
3218struct mlx5_ifc_set_l2_table_entry_in_bits {
3219 u8 opcode[0x10];
b4ff3a36 3220 u8 reserved_at_10[0x10];
e281682b 3221
b4ff3a36 3222 u8 reserved_at_20[0x10];
e281682b
SM		 3223 u8 op_mod[0x10];
3224
b4ff3a36 3225 u8 reserved_at_40[0x60];
e281682b 3226
b4ff3a36 3227 u8 reserved_at_a0[0x8];
e281682b
SM		 3228 u8 table_index[0x18];
3229
b4ff3a36 3230 u8 reserved_at_c0[0x20];
e281682b 3231
b4ff3a36 3232 u8 reserved_at_e0[0x13];
e281682b
SM		 3233 u8 vlan_valid[0x1];
3234 u8 vlan[0xc];
3235
3236 struct mlx5_ifc_mac_address_layout_bits mac_address;
3237
b4ff3a36 3238 u8 reserved_at_140[0xc0];
e281682b
SM		 3239};
3240
3241struct mlx5_ifc_set_issi_out_bits {
3242 u8 status[0x8];
b4ff3a36 3243 u8 reserved_at_8[0x18];
e281682b
SM		 3244
3245 u8 syndrome[0x20];
3246
b4ff3a36 3247 u8 reserved_at_40[0x40];
e281682b
SM		 3248};
3249
3250struct mlx5_ifc_set_issi_in_bits {
3251 u8 opcode[0x10];
b4ff3a36 3252 u8 reserved_at_10[0x10];
e281682b 3253
b4ff3a36 3254 u8 reserved_at_20[0x10];
e281682b
SM		 3255 u8 op_mod[0x10];
3256
b4ff3a36 3257 u8 reserved_at_40[0x10];
e281682b
SM		 3258 u8 current_issi[0x10];
3259
b4ff3a36 3260 u8 reserved_at_60[0x20];
e281682b
SM		 3261};
3262
3263struct mlx5_ifc_set_hca_cap_out_bits {
3264 u8 status[0x8];
b4ff3a36 3265 u8 reserved_at_8[0x18];
e281682b
SM		 3266
3267 u8 syndrome[0x20];
3268
b4ff3a36 3269 u8 reserved_at_40[0x40];
e281682b
SM		 3270};
3271
3272struct mlx5_ifc_set_hca_cap_in_bits {
3273 u8 opcode[0x10];
b4ff3a36 3274 u8 reserved_at_10[0x10];
e281682b 3275
b4ff3a36 3276 u8 reserved_at_20[0x10];
e281682b
SM		 3277 u8 op_mod[0x10];
3278
b4ff3a36 3279 u8 reserved_at_40[0x40];
e281682b
SM		 3280
3281 union mlx5_ifc_hca_cap_union_bits capability;
3282};
3283
26a81453
MG		 3284enum {
3285 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
3286 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
3287 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
3288 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
3289};
3290
e281682b
SM		 3291struct mlx5_ifc_set_fte_out_bits {
3292 u8 status[0x8];
b4ff3a36 3293 u8 reserved_at_8[0x18];
e281682b
SM		 3294
3295 u8 syndrome[0x20];
3296
b4ff3a36 3297 u8 reserved_at_40[0x40];
e281682b
SM		 3298};
3299
3300struct mlx5_ifc_set_fte_in_bits {
3301 u8 opcode[0x10];
b4ff3a36 3302 u8 reserved_at_10[0x10];
e281682b 3303
b4ff3a36 3304 u8 reserved_at_20[0x10];
e281682b
SM		 3305 u8 op_mod[0x10];
3306
7d5e1423
SM		 3307 u8 other_vport[0x1];
3308 u8 reserved_at_41[0xf];
3309 u8 vport_number[0x10];
3310
3311 u8 reserved_at_60[0x20];
e281682b
SM		 3312
3313 u8 table_type[0x8];
b4ff3a36 3314 u8 reserved_at_88[0x18];
e281682b 3315
b4ff3a36 3316 u8 reserved_at_a0[0x8];
e281682b
SM		 3317 u8 table_id[0x18];
3318
b4ff3a36 3319 u8 reserved_at_c0[0x18];
26a81453
MG		 3320 u8 modify_enable_mask[0x8];
3321
b4ff3a36 3322 u8 reserved_at_e0[0x20];
e281682b
SM		 3323
3324 u8 flow_index[0x20];
3325
b4ff3a36 3326 u8 reserved_at_120[0xe0];
e281682b
SM		 3327
3328 struct mlx5_ifc_flow_context_bits flow_context;
3329};
3330
3331struct mlx5_ifc_rts2rts_qp_out_bits {
3332 u8 status[0x8];
b4ff3a36 3333 u8 reserved_at_8[0x18];
e281682b
SM		 3334
3335 u8 syndrome[0x20];
3336
b4ff3a36 3337 u8 reserved_at_40[0x40];
e281682b
SM		 3338};
3339
3340struct mlx5_ifc_rts2rts_qp_in_bits {
3341 u8 opcode[0x10];
b4ff3a36 3342 u8 reserved_at_10[0x10];
e281682b 3343
b4ff3a36 3344 u8 reserved_at_20[0x10];
e281682b
SM		 3345 u8 op_mod[0x10];
3346
b4ff3a36 3347 u8 reserved_at_40[0x8];
e281682b
SM		 3348 u8 qpn[0x18];
3349
b4ff3a36 3350 u8 reserved_at_60[0x20];
e281682b
SM		 3351
3352 u8 opt_param_mask[0x20];
3353
b4ff3a36 3354 u8 reserved_at_a0[0x20];
e281682b
SM		 3355
3356 struct mlx5_ifc_qpc_bits qpc;
3357
b4ff3a36 3358 u8 reserved_at_800[0x80];
e281682b
SM		 3359};
3360
3361struct mlx5_ifc_rtr2rts_qp_out_bits {
3362 u8 status[0x8];
b4ff3a36 3363 u8 reserved_at_8[0x18];
e281682b
SM		 3364
3365 u8 syndrome[0x20];
3366
b4ff3a36 3367 u8 reserved_at_40[0x40];
e281682b
SM		 3368};
3369
3370struct mlx5_ifc_rtr2rts_qp_in_bits {
3371 u8 opcode[0x10];
b4ff3a36 3372 u8 reserved_at_10[0x10];
e281682b 3373
b4ff3a36 3374 u8 reserved_at_20[0x10];
e281682b
SM		 3375 u8 op_mod[0x10];
3376
b4ff3a36 3377 u8 reserved_at_40[0x8];
e281682b
SM		 3378 u8 qpn[0x18];
3379
b4ff3a36 3380 u8 reserved_at_60[0x20];
e281682b
SM		 3381
3382 u8 opt_param_mask[0x20];
3383
b4ff3a36 3384 u8 reserved_at_a0[0x20];
e281682b
SM		 3385
3386 struct mlx5_ifc_qpc_bits qpc;
3387
b4ff3a36 3388 u8 reserved_at_800[0x80];
e281682b
SM		 3389};
3390
3391struct mlx5_ifc_rst2init_qp_out_bits {
3392 u8 status[0x8];
b4ff3a36 3393 u8 reserved_at_8[0x18];
e281682b
SM		 3394
3395 u8 syndrome[0x20];
3396
b4ff3a36 3397 u8 reserved_at_40[0x40];
e281682b
SM		 3398};
3399
3400struct mlx5_ifc_rst2init_qp_in_bits {
3401 u8 opcode[0x10];
b4ff3a36 3402 u8 reserved_at_10[0x10];
e281682b 3403
b4ff3a36 3404 u8 reserved_at_20[0x10];
e281682b
SM		 3405 u8 op_mod[0x10];
3406
b4ff3a36 3407 u8 reserved_at_40[0x8];
e281682b
SM		 3408 u8 qpn[0x18];
3409
b4ff3a36 3410 u8 reserved_at_60[0x20];
e281682b
SM		 3411
3412 u8 opt_param_mask[0x20];
3413
b4ff3a36 3414 u8 reserved_at_a0[0x20];
e281682b
SM		 3415
3416 struct mlx5_ifc_qpc_bits qpc;
3417
b4ff3a36 3418 u8 reserved_at_800[0x80];
e281682b
SM		 3419};
3420
7486216b
SM		 3421struct mlx5_ifc_query_xrq_out_bits {
3422 u8 status[0x8];
3423 u8 reserved_at_8[0x18];
3424
3425 u8 syndrome[0x20];
3426
3427 u8 reserved_at_40[0x40];
3428
3429 struct mlx5_ifc_xrqc_bits xrq_context;
3430};
3431
3432struct mlx5_ifc_query_xrq_in_bits {
3433 u8 opcode[0x10];
3434 u8 reserved_at_10[0x10];
3435
3436 u8 reserved_at_20[0x10];
3437 u8 op_mod[0x10];
3438
3439 u8 reserved_at_40[0x8];
3440 u8 xrqn[0x18];
3441
3442 u8 reserved_at_60[0x20];
3443};
3444
e281682b
SM		 3445struct mlx5_ifc_query_xrc_srq_out_bits {
3446 u8 status[0x8];
b4ff3a36 3447 u8 reserved_at_8[0x18];
e281682b
SM		 3448
3449 u8 syndrome[0x20];
3450
b4ff3a36 3451 u8 reserved_at_40[0x40];
e281682b
SM		 3452
3453 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3454
b4ff3a36 3455 u8 reserved_at_280[0x600];
e281682b
SM		 3456
3457 u8 pas[0][0x40];
3458};
3459
3460struct mlx5_ifc_query_xrc_srq_in_bits {
3461 u8 opcode[0x10];
b4ff3a36 3462 u8 reserved_at_10[0x10];
e281682b 3463
b4ff3a36 3464 u8 reserved_at_20[0x10];
e281682b
SM		 3465 u8 op_mod[0x10];
3466
b4ff3a36 3467 u8 reserved_at_40[0x8];
e281682b
SM		 3468 u8 xrc_srqn[0x18];
3469
b4ff3a36 3470 u8 reserved_at_60[0x20];
e281682b
SM		 3471};
3472
3473enum {
3474 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
3475 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
3476};
3477
3478struct mlx5_ifc_query_vport_state_out_bits {
3479 u8 status[0x8];
b4ff3a36 3480 u8 reserved_at_8[0x18];
e281682b
SM		 3481
3482 u8 syndrome[0x20];
3483
b4ff3a36 3484 u8 reserved_at_40[0x20];
e281682b 3485
b4ff3a36 3486 u8 reserved_at_60[0x18];
e281682b
SM		 3487 u8 admin_state[0x4];
3488 u8 state[0x4];
3489};
3490
3491enum {
3492 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0,
e7546514 3493 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1,
e281682b
SM		 3494};
3495
3496struct mlx5_ifc_query_vport_state_in_bits {
3497 u8 opcode[0x10];
b4ff3a36 3498 u8 reserved_at_10[0x10];
e281682b 3499
b4ff3a36 3500 u8 reserved_at_20[0x10];
e281682b
SM		 3501 u8 op_mod[0x10];
3502
3503 u8 other_vport[0x1];
b4ff3a36 3504 u8 reserved_at_41[0xf];
e281682b
SM		 3505 u8 vport_number[0x10];
3506
b4ff3a36 3507 u8 reserved_at_60[0x20];
e281682b
SM		 3508};
3509
3510struct mlx5_ifc_query_vport_counter_out_bits {
3511 u8 status[0x8];
b4ff3a36 3512 u8 reserved_at_8[0x18];
e281682b
SM		 3513
3514 u8 syndrome[0x20];
3515
b4ff3a36 3516 u8 reserved_at_40[0x40];
e281682b
SM		 3517
3518 struct mlx5_ifc_traffic_counter_bits received_errors;
3519
3520 struct mlx5_ifc_traffic_counter_bits transmit_errors;
3521
3522 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3523
3524 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3525
3526 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3527
3528 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3529
3530 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3531
3532 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3533
3534 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3535
3536 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3537
3538 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3539
3540 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3541
b4ff3a36 3542 u8 reserved_at_680[0xa00];
e281682b
SM		 3543};
3544
3545enum {
3546 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
3547};
3548
3549struct mlx5_ifc_query_vport_counter_in_bits {
3550 u8 opcode[0x10];
b4ff3a36 3551 u8 reserved_at_10[0x10];
e281682b 3552
b4ff3a36 3553 u8 reserved_at_20[0x10];
e281682b
SM		 3554 u8 op_mod[0x10];
3555
3556 u8 other_vport[0x1];
b54ba277
MY		 3557 u8 reserved_at_41[0xb];
3558 u8 port_num[0x4];
e281682b
SM		 3559 u8 vport_number[0x10];
3560
b4ff3a36 3561 u8 reserved_at_60[0x60];
e281682b
SM		 3562
3563 u8 clear[0x1];
b4ff3a36 3564 u8 reserved_at_c1[0x1f];
e281682b 3565
b4ff3a36 3566 u8 reserved_at_e0[0x20];
e281682b
SM		 3567};
3568
3569struct mlx5_ifc_query_tis_out_bits {
3570 u8 status[0x8];
b4ff3a36 3571 u8 reserved_at_8[0x18];
e281682b
SM		 3572
3573 u8 syndrome[0x20];
3574
b4ff3a36 3575 u8 reserved_at_40[0x40];
e281682b
SM		 3576
3577 struct mlx5_ifc_tisc_bits tis_context;
3578};
3579
3580struct mlx5_ifc_query_tis_in_bits {
3581 u8 opcode[0x10];
b4ff3a36 3582 u8 reserved_at_10[0x10];
e281682b 3583
b4ff3a36 3584 u8 reserved_at_20[0x10];
e281682b
SM		 3585 u8 op_mod[0x10];
3586
b4ff3a36 3587 u8 reserved_at_40[0x8];
e281682b
SM		 3588 u8 tisn[0x18];
3589
b4ff3a36 3590 u8 reserved_at_60[0x20];
e281682b
SM		 3591};
3592
3593struct mlx5_ifc_query_tir_out_bits {
3594 u8 status[0x8];
b4ff3a36 3595 u8 reserved_at_8[0x18];
e281682b
SM		 3596
3597 u8 syndrome[0x20];
3598
b4ff3a36 3599 u8 reserved_at_40[0xc0];
e281682b
SM		 3600
3601 struct mlx5_ifc_tirc_bits tir_context;
3602};
3603
3604struct mlx5_ifc_query_tir_in_bits {
3605 u8 opcode[0x10];
b4ff3a36 3606 u8 reserved_at_10[0x10];
e281682b 3607
b4ff3a36 3608 u8 reserved_at_20[0x10];
e281682b
SM		 3609 u8 op_mod[0x10];
3610
b4ff3a36 3611 u8 reserved_at_40[0x8];
e281682b
SM		 3612 u8 tirn[0x18];
3613
b4ff3a36 3614 u8 reserved_at_60[0x20];
e281682b
SM		 3615};
3616
3617struct mlx5_ifc_query_srq_out_bits {
3618 u8 status[0x8];
b4ff3a36 3619 u8 reserved_at_8[0x18];
e281682b
SM		 3620
3621 u8 syndrome[0x20];
3622
b4ff3a36 3623 u8 reserved_at_40[0x40];
e281682b
SM		 3624
3625 struct mlx5_ifc_srqc_bits srq_context_entry;
3626
b4ff3a36 3627 u8 reserved_at_280[0x600];
e281682b
SM		 3628
3629 u8 pas[0][0x40];
3630};
3631
3632struct mlx5_ifc_query_srq_in_bits {
3633 u8 opcode[0x10];
b4ff3a36 3634 u8 reserved_at_10[0x10];
e281682b 3635
b4ff3a36 3636 u8 reserved_at_20[0x10];
e281682b
SM		 3637 u8 op_mod[0x10];
3638
b4ff3a36 3639 u8 reserved_at_40[0x8];
e281682b
SM		 3640 u8 srqn[0x18];
3641
b4ff3a36 3642 u8 reserved_at_60[0x20];
e281682b
SM		 3643};
3644
3645struct mlx5_ifc_query_sq_out_bits {
3646 u8 status[0x8];
b4ff3a36 3647 u8 reserved_at_8[0x18];
e281682b
SM		 3648
3649 u8 syndrome[0x20];
3650
b4ff3a36 3651 u8 reserved_at_40[0xc0];
e281682b
SM		 3652
3653 struct mlx5_ifc_sqc_bits sq_context;
3654};
3655
3656struct mlx5_ifc_query_sq_in_bits {
3657 u8 opcode[0x10];
b4ff3a36 3658 u8 reserved_at_10[0x10];
e281682b 3659
b4ff3a36 3660 u8 reserved_at_20[0x10];
e281682b
SM		 3661 u8 op_mod[0x10];
3662
b4ff3a36 3663 u8 reserved_at_40[0x8];
e281682b
SM		 3664 u8 sqn[0x18];
3665
b4ff3a36 3666 u8 reserved_at_60[0x20];
e281682b
SM		 3667};
3668
3669struct mlx5_ifc_query_special_contexts_out_bits {
3670 u8 status[0x8];
b4ff3a36 3671 u8 reserved_at_8[0x18];
e281682b
SM		 3672
3673 u8 syndrome[0x20];
3674
ec22eb53 3675 u8 dump_fill_mkey[0x20];
e281682b
SM		 3676
3677 u8 resd_lkey[0x20];
bcda1aca
AK		 3678
3679 u8 null_mkey[0x20];
3680
3681 u8 reserved_at_a0[0x60];
e281682b
SM		 3682};
3683
3684struct mlx5_ifc_query_special_contexts_in_bits {
3685 u8 opcode[0x10];
b4ff3a36 3686 u8 reserved_at_10[0x10];
e281682b 3687
b4ff3a36 3688 u8 reserved_at_20[0x10];
e281682b
SM		 3689 u8 op_mod[0x10];
3690
b4ff3a36 3691 u8 reserved_at_40[0x40];
e281682b
SM		 3692};
3693
813f8540
MHY		 3694struct mlx5_ifc_query_scheduling_element_out_bits {
3695 u8 opcode[0x10];
3696 u8 reserved_at_10[0x10];
3697
3698 u8 reserved_at_20[0x10];
3699 u8 op_mod[0x10];
3700
3701 u8 reserved_at_40[0xc0];
3702
3703 struct mlx5_ifc_scheduling_context_bits scheduling_context;
3704
3705 u8 reserved_at_300[0x100];
3706};
3707
3708enum {
3709 SCHEDULING_HIERARCHY_E_SWITCH = 0x2,
3710};
3711
3712struct mlx5_ifc_query_scheduling_element_in_bits {
3713 u8 opcode[0x10];
3714 u8 reserved_at_10[0x10];
3715
3716 u8 reserved_at_20[0x10];
3717 u8 op_mod[0x10];
3718
3719 u8 scheduling_hierarchy[0x8];
3720 u8 reserved_at_48[0x18];
3721
3722 u8 scheduling_element_id[0x20];
3723
3724 u8 reserved_at_80[0x180];
3725};
3726
e281682b
SM		 3727struct mlx5_ifc_query_rqt_out_bits {
3728 u8 status[0x8];
b4ff3a36 3729 u8 reserved_at_8[0x18];
e281682b
SM		 3730
3731 u8 syndrome[0x20];
3732
b4ff3a36 3733 u8 reserved_at_40[0xc0];
e281682b
SM		 3734
3735 struct mlx5_ifc_rqtc_bits rqt_context;
3736};
3737
3738struct mlx5_ifc_query_rqt_in_bits {
3739 u8 opcode[0x10];
b4ff3a36 3740 u8 reserved_at_10[0x10];
e281682b 3741
b4ff3a36 3742 u8 reserved_at_20[0x10];
e281682b
SM		 3743 u8 op_mod[0x10];
3744
b4ff3a36 3745 u8 reserved_at_40[0x8];
e281682b
SM		 3746 u8 rqtn[0x18];
3747
b4ff3a36 3748 u8 reserved_at_60[0x20];
e281682b
SM		 3749};
3750
3751struct mlx5_ifc_query_rq_out_bits {
3752 u8 status[0x8];
b4ff3a36 3753 u8 reserved_at_8[0x18];
e281682b
SM		 3754
3755 u8 syndrome[0x20];
3756
b4ff3a36 3757 u8 reserved_at_40[0xc0];
e281682b
SM		 3758
3759 struct mlx5_ifc_rqc_bits rq_context;
3760};
3761
3762struct mlx5_ifc_query_rq_in_bits {
3763 u8 opcode[0x10];
b4ff3a36 3764 u8 reserved_at_10[0x10];
e281682b 3765
b4ff3a36 3766 u8 reserved_at_20[0x10];
e281682b
SM		 3767 u8 op_mod[0x10];
3768
b4ff3a36 3769 u8 reserved_at_40[0x8];
e281682b
SM		 3770 u8 rqn[0x18];
3771
b4ff3a36 3772 u8 reserved_at_60[0x20];
e281682b
SM		 3773};
3774
3775struct mlx5_ifc_query_roce_address_out_bits {
3776 u8 status[0x8];
b4ff3a36 3777 u8 reserved_at_8[0x18];
e281682b
SM		 3778
3779 u8 syndrome[0x20];
3780
b4ff3a36 3781 u8 reserved_at_40[0x40];
e281682b
SM		 3782
3783 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3784};
3785
3786struct mlx5_ifc_query_roce_address_in_bits {
3787 u8 opcode[0x10];
b4ff3a36 3788 u8 reserved_at_10[0x10];
e281682b 3789
b4ff3a36 3790 u8 reserved_at_20[0x10];
e281682b
SM		 3791 u8 op_mod[0x10];
3792
3793 u8 roce_address_index[0x10];
b4ff3a36 3794 u8 reserved_at_50[0x10];
e281682b 3795
b4ff3a36 3796 u8 reserved_at_60[0x20];
e281682b
SM		 3797};
3798
3799struct mlx5_ifc_query_rmp_out_bits {
3800 u8 status[0x8];
b4ff3a36 3801 u8 reserved_at_8[0x18];
e281682b
SM		 3802
3803 u8 syndrome[0x20];
3804
b4ff3a36 3805 u8 reserved_at_40[0xc0];
e281682b
SM		 3806
3807 struct mlx5_ifc_rmpc_bits rmp_context;
3808};
3809
3810struct mlx5_ifc_query_rmp_in_bits {
3811 u8 opcode[0x10];
b4ff3a36 3812 u8 reserved_at_10[0x10];
e281682b 3813
b4ff3a36 3814 u8 reserved_at_20[0x10];
e281682b
SM		 3815 u8 op_mod[0x10];
3816
b4ff3a36 3817 u8 reserved_at_40[0x8];
e281682b
SM		 3818 u8 rmpn[0x18];
3819
b4ff3a36 3820 u8 reserved_at_60[0x20];
e281682b
SM		 3821};
3822
3823struct mlx5_ifc_query_qp_out_bits {
3824 u8 status[0x8];
b4ff3a36 3825 u8 reserved_at_8[0x18];
e281682b
SM		 3826
3827 u8 syndrome[0x20];
3828
b4ff3a36 3829 u8 reserved_at_40[0x40];
e281682b
SM		 3830
3831 u8 opt_param_mask[0x20];
3832
b4ff3a36 3833 u8 reserved_at_a0[0x20];
e281682b
SM		 3834
3835 struct mlx5_ifc_qpc_bits qpc;
3836
b4ff3a36 3837 u8 reserved_at_800[0x80];
e281682b
SM		 3838
3839 u8 pas[0][0x40];
3840};
3841
3842struct mlx5_ifc_query_qp_in_bits {
3843 u8 opcode[0x10];
b4ff3a36 3844 u8 reserved_at_10[0x10];
e281682b 3845
b4ff3a36 3846 u8 reserved_at_20[0x10];
e281682b
SM		 3847 u8 op_mod[0x10];
3848
b4ff3a36 3849 u8 reserved_at_40[0x8];
e281682b
SM		 3850 u8 qpn[0x18];
3851
b4ff3a36 3852 u8 reserved_at_60[0x20];
e281682b
SM		 3853};
3854
3855struct mlx5_ifc_query_q_counter_out_bits {
3856 u8 status[0x8];
b4ff3a36 3857 u8 reserved_at_8[0x18];
e281682b
SM		 3858
3859 u8 syndrome[0x20];
3860
b4ff3a36 3861 u8 reserved_at_40[0x40];
e281682b
SM		 3862
3863 u8 rx_write_requests[0x20];
3864
b4ff3a36 3865 u8 reserved_at_a0[0x20];
e281682b
SM		 3866
3867 u8 rx_read_requests[0x20];
3868
b4ff3a36 3869 u8 reserved_at_e0[0x20];
e281682b
SM		 3870
3871 u8 rx_atomic_requests[0x20];
3872
b4ff3a36 3873 u8 reserved_at_120[0x20];
e281682b
SM		 3874
3875 u8 rx_dct_connect[0x20];
3876
b4ff3a36 3877 u8 reserved_at_160[0x20];
e281682b
SM		 3878
3879 u8 out_of_buffer[0x20];
3880
b4ff3a36 3881 u8 reserved_at_1a0[0x20];
e281682b
SM		 3882
3883 u8 out_of_sequence[0x20];
3884
7486216b
SM		 3885 u8 reserved_at_1e0[0x20];
3886
3887 u8 duplicate_request[0x20];
3888
3889 u8 reserved_at_220[0x20];
3890
3891 u8 rnr_nak_retry_err[0x20];
3892
3893 u8 reserved_at_260[0x20];
3894
3895 u8 packet_seq_err[0x20];
3896
3897 u8 reserved_at_2a0[0x20];
3898
3899 u8 implied_nak_seq_err[0x20];
3900
3901 u8 reserved_at_2e0[0x20];
3902
3903 u8 local_ack_timeout_err[0x20];
3904
3905 u8 reserved_at_320[0x4e0];
e281682b
SM		 3906};
3907
3908struct mlx5_ifc_query_q_counter_in_bits {
3909 u8 opcode[0x10];
b4ff3a36 3910 u8 reserved_at_10[0x10];
e281682b 3911
b4ff3a36 3912 u8 reserved_at_20[0x10];
e281682b
SM		 3913 u8 op_mod[0x10];
3914
b4ff3a36 3915 u8 reserved_at_40[0x80];
e281682b
SM		 3916
3917 u8 clear[0x1];
b4ff3a36 3918 u8 reserved_at_c1[0x1f];
e281682b 3919
b4ff3a36 3920 u8 reserved_at_e0[0x18];
e281682b
SM		 3921 u8 counter_set_id[0x8];
3922};
3923
3924struct mlx5_ifc_query_pages_out_bits {
3925 u8 status[0x8];
b4ff3a36 3926 u8 reserved_at_8[0x18];
e281682b
SM		 3927
3928 u8 syndrome[0x20];
3929
b4ff3a36 3930 u8 reserved_at_40[0x10];
e281682b
SM		 3931 u8 function_id[0x10];
3932
3933 u8 num_pages[0x20];
3934};
3935
3936enum {
3937 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
3938 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
3939 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
3940};
3941
3942struct mlx5_ifc_query_pages_in_bits {
3943 u8 opcode[0x10];
b4ff3a36 3944 u8 reserved_at_10[0x10];
e281682b 3945
b4ff3a36 3946 u8 reserved_at_20[0x10];
e281682b
SM		 3947 u8 op_mod[0x10];
3948
b4ff3a36 3949 u8 reserved_at_40[0x10];
e281682b
SM		 3950 u8 function_id[0x10];
3951
b4ff3a36 3952 u8 reserved_at_60[0x20];
e281682b
SM		 3953};
3954
3955struct mlx5_ifc_query_nic_vport_context_out_bits {
3956 u8 status[0x8];
b4ff3a36 3957 u8 reserved_at_8[0x18];
e281682b
SM		 3958
3959 u8 syndrome[0x20];
3960
b4ff3a36 3961 u8 reserved_at_40[0x40];
e281682b
SM		 3962
3963 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
3964};
3965
3966struct mlx5_ifc_query_nic_vport_context_in_bits {
3967 u8 opcode[0x10];
b4ff3a36 3968 u8 reserved_at_10[0x10];
e281682b 3969
b4ff3a36 3970 u8 reserved_at_20[0x10];
e281682b
SM		 3971 u8 op_mod[0x10];
3972
3973 u8 other_vport[0x1];
b4ff3a36 3974 u8 reserved_at_41[0xf];
e281682b
SM		 3975 u8 vport_number[0x10];
3976
b4ff3a36 3977 u8 reserved_at_60[0x5];
e281682b 3978 u8 allowed_list_type[0x3];
b4ff3a36 3979 u8 reserved_at_68[0x18];
e281682b
SM		 3980};
3981
3982struct mlx5_ifc_query_mkey_out_bits {
3983 u8 status[0x8];
b4ff3a36 3984 u8 reserved_at_8[0x18];
e281682b
SM		 3985
3986 u8 syndrome[0x20];
3987
b4ff3a36 3988 u8 reserved_at_40[0x40];
e281682b
SM		 3989
3990 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
3991
b4ff3a36 3992 u8 reserved_at_280[0x600];
e281682b
SM		 3993
3994 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
3995
3996 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
3997};
3998
3999struct mlx5_ifc_query_mkey_in_bits {
4000 u8 opcode[0x10];
b4ff3a36 4001 u8 reserved_at_10[0x10];
e281682b 4002
b4ff3a36 4003 u8 reserved_at_20[0x10];
e281682b
SM		 4004 u8 op_mod[0x10];
4005
b4ff3a36 4006 u8 reserved_at_40[0x8];
e281682b
SM		 4007 u8 mkey_index[0x18];
4008
4009 u8 pg_access[0x1];
b4ff3a36 4010 u8 reserved_at_61[0x1f];
e281682b
SM		 4011};
4012
4013struct mlx5_ifc_query_mad_demux_out_bits {
4014 u8 status[0x8];
b4ff3a36 4015 u8 reserved_at_8[0x18];
e281682b
SM		 4016
4017 u8 syndrome[0x20];
4018
b4ff3a36 4019 u8 reserved_at_40[0x40];
e281682b
SM		 4020
4021 u8 mad_dumux_parameters_block[0x20];
4022};
4023
4024struct mlx5_ifc_query_mad_demux_in_bits {
4025 u8 opcode[0x10];
b4ff3a36 4026 u8 reserved_at_10[0x10];
e281682b 4027
b4ff3a36 4028 u8 reserved_at_20[0x10];
e281682b
SM		 4029 u8 op_mod[0x10];
4030
b4ff3a36 4031 u8 reserved_at_40[0x40];
e281682b
SM		 4032};
4033
4034struct mlx5_ifc_query_l2_table_entry_out_bits {
4035 u8 status[0x8];
b4ff3a36 4036 u8 reserved_at_8[0x18];
e281682b
SM		 4037
4038 u8 syndrome[0x20];
4039
b4ff3a36 4040 u8 reserved_at_40[0xa0];
e281682b 4041
b4ff3a36 4042 u8 reserved_at_e0[0x13];
e281682b
SM		 4043 u8 vlan_valid[0x1];
4044 u8 vlan[0xc];
4045
4046 struct mlx5_ifc_mac_address_layout_bits mac_address;
4047
b4ff3a36 4048 u8 reserved_at_140[0xc0];
e281682b
SM		 4049};
4050
4051struct mlx5_ifc_query_l2_table_entry_in_bits {
4052 u8 opcode[0x10];
b4ff3a36 4053 u8 reserved_at_10[0x10];
e281682b 4054
b4ff3a36 4055 u8 reserved_at_20[0x10];
e281682b
SM		 4056 u8 op_mod[0x10];
4057
b4ff3a36 4058 u8 reserved_at_40[0x60];
e281682b 4059
b4ff3a36 4060 u8 reserved_at_a0[0x8];
e281682b
SM		 4061 u8 table_index[0x18];
4062
b4ff3a36 4063 u8 reserved_at_c0[0x140];
e281682b
SM		 4064};
4065
4066struct mlx5_ifc_query_issi_out_bits {
4067 u8 status[0x8];
b4ff3a36 4068 u8 reserved_at_8[0x18];
e281682b
SM		 4069
4070 u8 syndrome[0x20];
4071
b4ff3a36 4072 u8 reserved_at_40[0x10];
e281682b
SM		 4073 u8 current_issi[0x10];
4074
b4ff3a36 4075 u8 reserved_at_60[0xa0];
e281682b 4076
b4ff3a36 4077 u8 reserved_at_100[76][0x8];
e281682b
SM		 4078 u8 supported_issi_dw0[0x20];
4079};
4080
4081struct mlx5_ifc_query_issi_in_bits {
4082 u8 opcode[0x10];
b4ff3a36 4083 u8 reserved_at_10[0x10];
e281682b 4084
b4ff3a36 4085 u8 reserved_at_20[0x10];
e281682b
SM		 4086 u8 op_mod[0x10];
4087
b4ff3a36 4088 u8 reserved_at_40[0x40];
e281682b
SM		 4089};
4090
0dbc6fe0
SM		 4091struct mlx5_ifc_set_driver_version_out_bits {
4092 u8 status[0x8];
4093 u8 reserved_0[0x18];
4094
4095 u8 syndrome[0x20];
4096 u8 reserved_1[0x40];
4097};
4098
4099struct mlx5_ifc_set_driver_version_in_bits {
4100 u8 opcode[0x10];
4101 u8 reserved_0[0x10];
4102
4103 u8 reserved_1[0x10];
4104 u8 op_mod[0x10];
4105
4106 u8 reserved_2[0x40];
4107 u8 driver_version[64][0x8];
4108};
4109
e281682b
SM		 4110struct mlx5_ifc_query_hca_vport_pkey_out_bits {
4111 u8 status[0x8];
b4ff3a36 4112 u8 reserved_at_8[0x18];
e281682b
SM		 4113
4114 u8 syndrome[0x20];
4115
b4ff3a36 4116 u8 reserved_at_40[0x40];
e281682b
SM		 4117
4118 struct mlx5_ifc_pkey_bits pkey[0];
4119};
4120
4121struct mlx5_ifc_query_hca_vport_pkey_in_bits {
4122 u8 opcode[0x10];
b4ff3a36 4123 u8 reserved_at_10[0x10];
e281682b 4124
b4ff3a36 4125 u8 reserved_at_20[0x10];
e281682b
SM		 4126 u8 op_mod[0x10];
4127
4128 u8 other_vport[0x1];
b4ff3a36 4129 u8 reserved_at_41[0xb];
707c4602 4130 u8 port_num[0x4];
e281682b
SM		 4131 u8 vport_number[0x10];
4132
b4ff3a36 4133 u8 reserved_at_60[0x10];
e281682b
SM		 4134 u8 pkey_index[0x10];
4135};
4136
eff901d3
EC		 4137enum {
4138 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
4139 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
4140 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
4141};
4142
e281682b
SM		 4143struct mlx5_ifc_query_hca_vport_gid_out_bits {
4144 u8 status[0x8];
b4ff3a36 4145 u8 reserved_at_8[0x18];
e281682b
SM		 4146
4147 u8 syndrome[0x20];
4148
b4ff3a36 4149 u8 reserved_at_40[0x20];
e281682b
SM		 4150
4151 u8 gids_num[0x10];
b4ff3a36 4152 u8 reserved_at_70[0x10];
e281682b
SM		 4153
4154 struct mlx5_ifc_array128_auto_bits gid[0];
4155};
4156
4157struct mlx5_ifc_query_hca_vport_gid_in_bits {
4158 u8 opcode[0x10];
b4ff3a36 4159 u8 reserved_at_10[0x10];
e281682b 4160
b4ff3a36 4161 u8 reserved_at_20[0x10];
e281682b
SM		 4162 u8 op_mod[0x10];
4163
4164 u8 other_vport[0x1];
b4ff3a36 4165 u8 reserved_at_41[0xb];
707c4602 4166 u8 port_num[0x4];
e281682b
SM		 4167 u8 vport_number[0x10];
4168
b4ff3a36 4169 u8 reserved_at_60[0x10];
e281682b
SM		 4170 u8 gid_index[0x10];
4171};
4172
4173struct mlx5_ifc_query_hca_vport_context_out_bits {
4174 u8 status[0x8];
b4ff3a36 4175 u8 reserved_at_8[0x18];
e281682b
SM		 4176
4177 u8 syndrome[0x20];
4178
b4ff3a36 4179 u8 reserved_at_40[0x40];
e281682b
SM		 4180
4181 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4182};
4183
4184struct mlx5_ifc_query_hca_vport_context_in_bits {
4185 u8 opcode[0x10];
b4ff3a36 4186 u8 reserved_at_10[0x10];
e281682b 4187
b4ff3a36 4188 u8 reserved_at_20[0x10];
e281682b
SM		 4189 u8 op_mod[0x10];
4190
4191 u8 other_vport[0x1];
b4ff3a36 4192 u8 reserved_at_41[0xb];
707c4602 4193 u8 port_num[0x4];
e281682b
SM		 4194 u8 vport_number[0x10];
4195
b4ff3a36 4196 u8 reserved_at_60[0x20];
e281682b
SM		 4197};
4198
4199struct mlx5_ifc_query_hca_cap_out_bits {
4200 u8 status[0x8];
b4ff3a36 4201 u8 reserved_at_8[0x18];
e281682b
SM		 4202
4203 u8 syndrome[0x20];
4204
b4ff3a36 4205 u8 reserved_at_40[0x40];
e281682b
SM		 4206
4207 union mlx5_ifc_hca_cap_union_bits capability;
4208};
4209
4210struct mlx5_ifc_query_hca_cap_in_bits {
4211 u8 opcode[0x10];
b4ff3a36 4212 u8 reserved_at_10[0x10];
e281682b 4213
b4ff3a36 4214 u8 reserved_at_20[0x10];
e281682b
SM		 4215 u8 op_mod[0x10];
4216
b4ff3a36 4217 u8 reserved_at_40[0x40];
e281682b
SM		 4218};
4219
4220struct mlx5_ifc_query_flow_table_out_bits {
4221 u8 status[0x8];
b4ff3a36 4222 u8 reserved_at_8[0x18];
e281682b
SM		 4223
4224 u8 syndrome[0x20];
4225
b4ff3a36 4226 u8 reserved_at_40[0x80];
e281682b 4227
b4ff3a36 4228 u8 reserved_at_c0[0x8];
e281682b 4229 u8 level[0x8];
b4ff3a36 4230 u8 reserved_at_d0[0x8];
e281682b
SM		 4231 u8 log_size[0x8];
4232
b4ff3a36 4233 u8 reserved_at_e0[0x120];
e281682b
SM		 4234};
4235
4236struct mlx5_ifc_query_flow_table_in_bits {
4237 u8 opcode[0x10];
b4ff3a36 4238 u8 reserved_at_10[0x10];
e281682b 4239
b4ff3a36 4240 u8 reserved_at_20[0x10];
e281682b
SM		 4241 u8 op_mod[0x10];
4242
b4ff3a36 4243 u8 reserved_at_40[0x40];
e281682b
SM		 4244
4245 u8 table_type[0x8];
b4ff3a36 4246 u8 reserved_at_88[0x18];
e281682b 4247
b4ff3a36 4248 u8 reserved_at_a0[0x8];
e281682b
SM		 4249 u8 table_id[0x18];
4250
b4ff3a36 4251 u8 reserved_at_c0[0x140];
e281682b
SM		 4252};
4253
4254struct mlx5_ifc_query_fte_out_bits {
4255 u8 status[0x8];
b4ff3a36 4256 u8 reserved_at_8[0x18];
e281682b
SM		 4257
4258 u8 syndrome[0x20];
4259
b4ff3a36 4260 u8 reserved_at_40[0x1c0];
e281682b
SM		 4261
4262 struct mlx5_ifc_flow_context_bits flow_context;
4263};
4264
4265struct mlx5_ifc_query_fte_in_bits {
4266 u8 opcode[0x10];
b4ff3a36 4267 u8 reserved_at_10[0x10];
e281682b 4268
b4ff3a36 4269 u8 reserved_at_20[0x10];
e281682b
SM		 4270 u8 op_mod[0x10];
4271
b4ff3a36 4272 u8 reserved_at_40[0x40];
e281682b
SM		 4273
4274 u8 table_type[0x8];
b4ff3a36 4275 u8 reserved_at_88[0x18];
e281682b 4276
b4ff3a36 4277 u8 reserved_at_a0[0x8];
e281682b
SM		 4278 u8 table_id[0x18];
4279
b4ff3a36 4280 u8 reserved_at_c0[0x40];
e281682b
SM		 4281
4282 u8 flow_index[0x20];
4283
b4ff3a36 4284 u8 reserved_at_120[0xe0];
e281682b
SM		 4285};
4286
4287enum {
4288 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
4289 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
4290 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
4291};
4292
4293struct mlx5_ifc_query_flow_group_out_bits {
4294 u8 status[0x8];
b4ff3a36 4295 u8 reserved_at_8[0x18];
e281682b
SM		 4296
4297 u8 syndrome[0x20];
4298
b4ff3a36 4299 u8 reserved_at_40[0xa0];
e281682b
SM		 4300
4301 u8 start_flow_index[0x20];
4302
b4ff3a36 4303 u8 reserved_at_100[0x20];
e281682b
SM		 4304
4305 u8 end_flow_index[0x20];
4306
b4ff3a36 4307 u8 reserved_at_140[0xa0];
e281682b 4308
b4ff3a36 4309 u8 reserved_at_1e0[0x18];
e281682b
SM		 4310 u8 match_criteria_enable[0x8];
4311
4312 struct mlx5_ifc_fte_match_param_bits match_criteria;
4313
b4ff3a36 4314 u8 reserved_at_1200[0xe00];
e281682b
SM		 4315};
4316
4317struct mlx5_ifc_query_flow_group_in_bits {
4318 u8 opcode[0x10];
b4ff3a36 4319 u8 reserved_at_10[0x10];
e281682b 4320
b4ff3a36 4321 u8 reserved_at_20[0x10];
e281682b
SM		 4322 u8 op_mod[0x10];
4323
b4ff3a36 4324 u8 reserved_at_40[0x40];
e281682b
SM		 4325
4326 u8 table_type[0x8];
b4ff3a36 4327 u8 reserved_at_88[0x18];
e281682b 4328
b4ff3a36 4329 u8 reserved_at_a0[0x8];
e281682b
SM		 4330 u8 table_id[0x18];
4331
4332 u8 group_id[0x20];
4333
b4ff3a36 4334 u8 reserved_at_e0[0x120];
e281682b
SM		 4335};
4336
9dc0b289
AV		 4337struct mlx5_ifc_query_flow_counter_out_bits {
4338 u8 status[0x8];
4339 u8 reserved_at_8[0x18];
4340
4341 u8 syndrome[0x20];
4342
4343 u8 reserved_at_40[0x40];
4344
4345 struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4346};
4347
4348struct mlx5_ifc_query_flow_counter_in_bits {
4349 u8 opcode[0x10];
4350 u8 reserved_at_10[0x10];
4351
4352 u8 reserved_at_20[0x10];
4353 u8 op_mod[0x10];
4354
4355 u8 reserved_at_40[0x80];
4356
4357 u8 clear[0x1];
4358 u8 reserved_at_c1[0xf];
4359 u8 num_of_counters[0x10];
4360
4361 u8 reserved_at_e0[0x10];
4362 u8 flow_counter_id[0x10];
4363};
4364
d6666753
SM		 4365struct mlx5_ifc_query_esw_vport_context_out_bits {
4366 u8 status[0x8];
b4ff3a36 4367 u8 reserved_at_8[0x18];
d6666753
SM		 4368
4369 u8 syndrome[0x20];
4370
b4ff3a36 4371 u8 reserved_at_40[0x40];
d6666753
SM		 4372
4373 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4374};
4375
4376struct mlx5_ifc_query_esw_vport_context_in_bits {
4377 u8 opcode[0x10];
b4ff3a36 4378 u8 reserved_at_10[0x10];
d6666753 4379
b4ff3a36 4380 u8 reserved_at_20[0x10];
d6666753
SM		 4381 u8 op_mod[0x10];
4382
4383 u8 other_vport[0x1];
b4ff3a36 4384 u8 reserved_at_41[0xf];
d6666753
SM		 4385 u8 vport_number[0x10];
4386
b4ff3a36 4387 u8 reserved_at_60[0x20];
d6666753
SM		 4388};
4389
4390struct mlx5_ifc_modify_esw_vport_context_out_bits {
4391 u8 status[0x8];
b4ff3a36 4392 u8 reserved_at_8[0x18];
d6666753
SM		 4393
4394 u8 syndrome[0x20];
4395
b4ff3a36 4396 u8 reserved_at_40[0x40];
d6666753
SM		 4397};
4398
4399struct mlx5_ifc_esw_vport_context_fields_select_bits {
b4ff3a36 4400 u8 reserved_at_0[0x1c];
d6666753
SM		 4401 u8 vport_cvlan_insert[0x1];
4402 u8 vport_svlan_insert[0x1];
4403 u8 vport_cvlan_strip[0x1];
4404 u8 vport_svlan_strip[0x1];
4405};
4406
4407struct mlx5_ifc_modify_esw_vport_context_in_bits {
4408 u8 opcode[0x10];
b4ff3a36 4409 u8 reserved_at_10[0x10];
d6666753 4410
b4ff3a36 4411 u8 reserved_at_20[0x10];
d6666753
SM		 4412 u8 op_mod[0x10];
4413
4414 u8 other_vport[0x1];
b4ff3a36 4415 u8 reserved_at_41[0xf];
d6666753
SM		 4416 u8 vport_number[0x10];
4417
4418 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4419
4420 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4421};
4422
e281682b
SM		 4423struct mlx5_ifc_query_eq_out_bits {
4424 u8 status[0x8];
b4ff3a36 4425 u8 reserved_at_8[0x18];
e281682b
SM		 4426
4427 u8 syndrome[0x20];
4428
b4ff3a36 4429 u8 reserved_at_40[0x40];
e281682b
SM		 4430
4431 struct mlx5_ifc_eqc_bits eq_context_entry;
4432
b4ff3a36 4433 u8 reserved_at_280[0x40];
e281682b
SM		 4434
4435 u8 event_bitmask[0x40];
4436
b4ff3a36 4437 u8 reserved_at_300[0x580];
e281682b
SM		 4438
4439 u8 pas[0][0x40];
4440};
4441
4442struct mlx5_ifc_query_eq_in_bits {
4443 u8 opcode[0x10];
b4ff3a36 4444 u8 reserved_at_10[0x10];
e281682b 4445
b4ff3a36 4446 u8 reserved_at_20[0x10];
e281682b
SM		 4447 u8 op_mod[0x10];
4448
b4ff3a36 4449 u8 reserved_at_40[0x18];
e281682b
SM		 4450 u8 eq_number[0x8];
4451
b4ff3a36 4452 u8 reserved_at_60[0x20];
e281682b
SM		 4453};
4454
7adbde20
HHZ		 4455struct mlx5_ifc_encap_header_in_bits {
4456 u8 reserved_at_0[0x5];
4457 u8 header_type[0x3];
4458 u8 reserved_at_8[0xe];
4459 u8 encap_header_size[0xa];
4460
4461 u8 reserved_at_20[0x10];
4462 u8 encap_header[2][0x8];
4463
4464 u8 more_encap_header[0][0x8];
4465};
4466
4467struct mlx5_ifc_query_encap_header_out_bits {
4468 u8 status[0x8];
4469 u8 reserved_at_8[0x18];
4470
4471 u8 syndrome[0x20];
4472
4473 u8 reserved_at_40[0xa0];
4474
4475 struct mlx5_ifc_encap_header_in_bits encap_header[0];
4476};
4477
4478struct mlx5_ifc_query_encap_header_in_bits {
4479 u8 opcode[0x10];
4480 u8 reserved_at_10[0x10];
4481
4482 u8 reserved_at_20[0x10];
4483 u8 op_mod[0x10];
4484
4485 u8 encap_id[0x20];
4486
4487 u8 reserved_at_60[0xa0];
4488};
4489
4490struct mlx5_ifc_alloc_encap_header_out_bits {
4491 u8 status[0x8];
4492 u8 reserved_at_8[0x18];
4493
4494 u8 syndrome[0x20];
4495
4496 u8 encap_id[0x20];
4497
4498 u8 reserved_at_60[0x20];
4499};
4500
4501struct mlx5_ifc_alloc_encap_header_in_bits {
4502 u8 opcode[0x10];
4503 u8 reserved_at_10[0x10];
4504
4505 u8 reserved_at_20[0x10];
4506 u8 op_mod[0x10];
4507
4508 u8 reserved_at_40[0xa0];
4509
4510 struct mlx5_ifc_encap_header_in_bits encap_header;
4511};
4512
4513struct mlx5_ifc_dealloc_encap_header_out_bits {
4514 u8 status[0x8];
4515 u8 reserved_at_8[0x18];
4516
4517 u8 syndrome[0x20];
4518
4519 u8 reserved_at_40[0x40];
4520};
4521
4522struct mlx5_ifc_dealloc_encap_header_in_bits {
4523 u8 opcode[0x10];
4524 u8 reserved_at_10[0x10];
4525
4526 u8 reserved_20[0x10];
4527 u8 op_mod[0x10];
4528
4529 u8 encap_id[0x20];
4530
4531 u8 reserved_60[0x20];
4532};
4533
e281682b
SM		 4534struct mlx5_ifc_query_dct_out_bits {
4535 u8 status[0x8];
b4ff3a36 4536 u8 reserved_at_8[0x18];
e281682b
SM		 4537
4538 u8 syndrome[0x20];
4539
b4ff3a36 4540 u8 reserved_at_40[0x40];
e281682b
SM		 4541
4542 struct mlx5_ifc_dctc_bits dct_context_entry;
4543
b4ff3a36 4544 u8 reserved_at_280[0x180];
e281682b
SM		 4545};
4546
4547struct mlx5_ifc_query_dct_in_bits {
4548 u8 opcode[0x10];
b4ff3a36 4549 u8 reserved_at_10[0x10];
e281682b 4550
b4ff3a36 4551 u8 reserved_at_20[0x10];
e281682b
SM		 4552 u8 op_mod[0x10];
4553
b4ff3a36 4554 u8 reserved_at_40[0x8];
e281682b
SM		 4555 u8 dctn[0x18];
4556
b4ff3a36 4557 u8 reserved_at_60[0x20];
e281682b
SM		 4558};
4559
4560struct mlx5_ifc_query_cq_out_bits {
4561 u8 status[0x8];
b4ff3a36 4562 u8 reserved_at_8[0x18];
e281682b
SM		 4563
4564 u8 syndrome[0x20];
4565
b4ff3a36 4566 u8 reserved_at_40[0x40];
e281682b
SM		 4567
4568 struct mlx5_ifc_cqc_bits cq_context;
4569
b4ff3a36 4570 u8 reserved_at_280[0x600];
e281682b
SM		 4571
4572 u8 pas[0][0x40];
4573};
4574
4575struct mlx5_ifc_query_cq_in_bits {
4576 u8 opcode[0x10];
b4ff3a36 4577 u8 reserved_at_10[0x10];
e281682b 4578
b4ff3a36 4579 u8 reserved_at_20[0x10];
e281682b
SM		 4580 u8 op_mod[0x10];
4581
b4ff3a36 4582 u8 reserved_at_40[0x8];
e281682b
SM		 4583 u8 cqn[0x18];
4584
b4ff3a36 4585 u8 reserved_at_60[0x20];
e281682b
SM		 4586};
4587
4588struct mlx5_ifc_query_cong_status_out_bits {
4589 u8 status[0x8];
b4ff3a36 4590 u8 reserved_at_8[0x18];
e281682b
SM		 4591
4592 u8 syndrome[0x20];
4593
b4ff3a36 4594 u8 reserved_at_40[0x20];
e281682b
SM		 4595
4596 u8 enable[0x1];
4597 u8 tag_enable[0x1];
b4ff3a36 4598 u8 reserved_at_62[0x1e];
e281682b
SM		 4599};
4600
4601struct mlx5_ifc_query_cong_status_in_bits {
4602 u8 opcode[0x10];
b4ff3a36 4603 u8 reserved_at_10[0x10];
e281682b 4604
b4ff3a36 4605 u8 reserved_at_20[0x10];
e281682b
SM		 4606 u8 op_mod[0x10];
4607
b4ff3a36 4608 u8 reserved_at_40[0x18];
e281682b
SM		 4609 u8 priority[0x4];
4610 u8 cong_protocol[0x4];
4611
b4ff3a36 4612 u8 reserved_at_60[0x20];
e281682b
SM		 4613};
4614
4615struct mlx5_ifc_query_cong_statistics_out_bits {
4616 u8 status[0x8];
b4ff3a36 4617 u8 reserved_at_8[0x18];
e281682b
SM		 4618
4619 u8 syndrome[0x20];
4620
b4ff3a36 4621 u8 reserved_at_40[0x40];
e281682b
SM		 4622
4623 u8 cur_flows[0x20];
4624
4625 u8 sum_flows[0x20];
4626
4627 u8 cnp_ignored_high[0x20];
4628
4629 u8 cnp_ignored_low[0x20];
4630
4631 u8 cnp_handled_high[0x20];
4632
4633 u8 cnp_handled_low[0x20];
4634
b4ff3a36 4635 u8 reserved_at_140[0x100];
e281682b
SM		 4636
4637 u8 time_stamp_high[0x20];
4638
4639 u8 time_stamp_low[0x20];
4640
4641 u8 accumulators_period[0x20];
4642
4643 u8 ecn_marked_roce_packets_high[0x20];
4644
4645 u8 ecn_marked_roce_packets_low[0x20];
4646
4647 u8 cnps_sent_high[0x20];
4648
4649 u8 cnps_sent_low[0x20];
4650
b4ff3a36 4651 u8 reserved_at_320[0x560];
e281682b
SM		 4652};
4653
4654struct mlx5_ifc_query_cong_statistics_in_bits {
4655 u8 opcode[0x10];
b4ff3a36 4656 u8 reserved_at_10[0x10];
e281682b 4657
b4ff3a36 4658 u8 reserved_at_20[0x10];
e281682b
SM		 4659 u8 op_mod[0x10];
4660
4661 u8 clear[0x1];
b4ff3a36 4662 u8 reserved_at_41[0x1f];
e281682b 4663
b4ff3a36 4664 u8 reserved_at_60[0x20];
e281682b
SM		 4665};
4666
4667struct mlx5_ifc_query_cong_params_out_bits {
4668 u8 status[0x8];
b4ff3a36 4669 u8 reserved_at_8[0x18];
e281682b
SM		 4670
4671 u8 syndrome[0x20];
4672
b4ff3a36 4673 u8 reserved_at_40[0x40];
e281682b
SM		 4674
4675 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4676};
4677
4678struct mlx5_ifc_query_cong_params_in_bits {
4679 u8 opcode[0x10];
b4ff3a36 4680 u8 reserved_at_10[0x10];
e281682b 4681
b4ff3a36 4682 u8 reserved_at_20[0x10];
e281682b
SM		 4683 u8 op_mod[0x10];
4684
b4ff3a36 4685 u8 reserved_at_40[0x1c];
e281682b
SM		 4686 u8 cong_protocol[0x4];
4687
b4ff3a36 4688 u8 reserved_at_60[0x20];
e281682b
SM		 4689};
4690
4691struct mlx5_ifc_query_adapter_out_bits {
4692 u8 status[0x8];
b4ff3a36 4693 u8 reserved_at_8[0x18];
e281682b
SM		 4694
4695 u8 syndrome[0x20];
4696
b4ff3a36 4697 u8 reserved_at_40[0x40];
e281682b
SM		 4698
4699 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4700};
4701
4702struct mlx5_ifc_query_adapter_in_bits {
4703 u8 opcode[0x10];
b4ff3a36 4704 u8 reserved_at_10[0x10];
e281682b 4705
b4ff3a36 4706 u8 reserved_at_20[0x10];
e281682b
SM		 4707 u8 op_mod[0x10];
4708
b4ff3a36 4709 u8 reserved_at_40[0x40];
e281682b
SM		 4710};
4711
4712struct mlx5_ifc_qp_2rst_out_bits {
4713 u8 status[0x8];
b4ff3a36 4714 u8 reserved_at_8[0x18];
e281682b
SM		 4715
4716 u8 syndrome[0x20];
4717
b4ff3a36 4718 u8 reserved_at_40[0x40];
e281682b
SM		 4719};
4720
4721struct mlx5_ifc_qp_2rst_in_bits {
4722 u8 opcode[0x10];
b4ff3a36 4723 u8 reserved_at_10[0x10];
e281682b 4724
b4ff3a36 4725 u8 reserved_at_20[0x10];
e281682b
SM		 4726 u8 op_mod[0x10];
4727
b4ff3a36 4728 u8 reserved_at_40[0x8];
e281682b
SM		 4729 u8 qpn[0x18];
4730
b4ff3a36 4731 u8 reserved_at_60[0x20];
e281682b
SM		 4732};
4733
4734struct mlx5_ifc_qp_2err_out_bits {
4735 u8 status[0x8];
b4ff3a36 4736 u8 reserved_at_8[0x18];
e281682b
SM		 4737
4738 u8 syndrome[0x20];
4739
b4ff3a36 4740 u8 reserved_at_40[0x40];
e281682b
SM		 4741};
4742
4743struct mlx5_ifc_qp_2err_in_bits {
4744 u8 opcode[0x10];
b4ff3a36 4745 u8 reserved_at_10[0x10];
e281682b 4746
b4ff3a36 4747 u8 reserved_at_20[0x10];
e281682b
SM		 4748 u8 op_mod[0x10];
4749
b4ff3a36 4750 u8 reserved_at_40[0x8];
e281682b
SM		 4751 u8 qpn[0x18];
4752
b4ff3a36 4753 u8 reserved_at_60[0x20];
e281682b
SM		 4754};
4755
4756struct mlx5_ifc_page_fault_resume_out_bits {
4757 u8 status[0x8];
b4ff3a36 4758 u8 reserved_at_8[0x18];
e281682b
SM		 4759
4760 u8 syndrome[0x20];
4761
b4ff3a36 4762 u8 reserved_at_40[0x40];
e281682b
SM		 4763};
4764
4765struct mlx5_ifc_page_fault_resume_in_bits {
4766 u8 opcode[0x10];
b4ff3a36 4767 u8 reserved_at_10[0x10];
e281682b 4768
b4ff3a36 4769 u8 reserved_at_20[0x10];
e281682b
SM		 4770 u8 op_mod[0x10];
4771
4772 u8 error[0x1];
b4ff3a36 4773 u8 reserved_at_41[0x4];
223cdc72
AK		 4774 u8 page_fault_type[0x3];
4775 u8 wq_number[0x18];
e281682b 4776
223cdc72
AK		 4777 u8 reserved_at_60[0x8];
4778 u8 token[0x18];
e281682b
SM		 4779};
4780
4781struct mlx5_ifc_nop_out_bits {
4782 u8 status[0x8];
b4ff3a36 4783 u8 reserved_at_8[0x18];
e281682b
SM		 4784
4785 u8 syndrome[0x20];
4786
b4ff3a36 4787 u8 reserved_at_40[0x40];
e281682b
SM		 4788};
4789
4790struct mlx5_ifc_nop_in_bits {
4791 u8 opcode[0x10];
b4ff3a36 4792 u8 reserved_at_10[0x10];
e281682b 4793
b4ff3a36 4794 u8 reserved_at_20[0x10];
e281682b
SM		 4795 u8 op_mod[0x10];
4796
b4ff3a36 4797 u8 reserved_at_40[0x40];
e281682b
SM		 4798};
4799
4800struct mlx5_ifc_modify_vport_state_out_bits {
4801 u8 status[0x8];
b4ff3a36 4802 u8 reserved_at_8[0x18];
e281682b
SM		 4803
4804 u8 syndrome[0x20];
4805
b4ff3a36 4806 u8 reserved_at_40[0x40];
e281682b
SM		 4807};
4808
4809struct mlx5_ifc_modify_vport_state_in_bits {
4810 u8 opcode[0x10];
b4ff3a36 4811 u8 reserved_at_10[0x10];
e281682b 4812
b4ff3a36 4813 u8 reserved_at_20[0x10];
e281682b
SM		 4814 u8 op_mod[0x10];
4815
4816 u8 other_vport[0x1];
b4ff3a36 4817 u8 reserved_at_41[0xf];
e281682b
SM		 4818 u8 vport_number[0x10];
4819
b4ff3a36 4820 u8 reserved_at_60[0x18];
e281682b 4821 u8 admin_state[0x4];
b4ff3a36 4822 u8 reserved_at_7c[0x4];
e281682b
SM		 4823};
4824
4825struct mlx5_ifc_modify_tis_out_bits {
4826 u8 status[0x8];
b4ff3a36 4827 u8 reserved_at_8[0x18];
e281682b
SM		 4828
4829 u8 syndrome[0x20];
4830
b4ff3a36 4831 u8 reserved_at_40[0x40];
e281682b
SM		 4832};
4833
75850d0b 4834struct mlx5_ifc_modify_tis_bitmask_bits {
b4ff3a36 4835 u8 reserved_at_0[0x20];
75850d0b 4836
84df61eb
AH		 4837 u8 reserved_at_20[0x1d];
4838 u8 lag_tx_port_affinity[0x1];
4839 u8 strict_lag_tx_port_affinity[0x1];
75850d0b 4840 u8 prio[0x1];
4841};
4842
e281682b
SM		 4843struct mlx5_ifc_modify_tis_in_bits {
4844 u8 opcode[0x10];
b4ff3a36 4845 u8 reserved_at_10[0x10];
e281682b 4846
b4ff3a36 4847 u8 reserved_at_20[0x10];
e281682b
SM		 4848 u8 op_mod[0x10];
4849
b4ff3a36 4850 u8 reserved_at_40[0x8];
e281682b
SM		 4851 u8 tisn[0x18];
4852
b4ff3a36 4853 u8 reserved_at_60[0x20];
e281682b 4854
75850d0b 4855 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
e281682b 4856
b4ff3a36 4857 u8 reserved_at_c0[0x40];
e281682b
SM		 4858
4859 struct mlx5_ifc_tisc_bits ctx;
4860};
4861
d9eea403 4862struct mlx5_ifc_modify_tir_bitmask_bits {
b4ff3a36 4863 u8 reserved_at_0[0x20];
d9eea403 4864
b4ff3a36 4865 u8 reserved_at_20[0x1b];
66189961 4866 u8 self_lb_en[0x1];
bdfc028d
TT		 4867 u8 reserved_at_3c[0x1];
4868 u8 hash[0x1];
4869 u8 reserved_at_3e[0x1];
d9eea403
AS		 4870 u8 lro[0x1];
4871};
4872
e281682b
SM		 4873struct mlx5_ifc_modify_tir_out_bits {
4874 u8 status[0x8];
b4ff3a36 4875 u8 reserved_at_8[0x18];
e281682b
SM		 4876
4877 u8 syndrome[0x20];
4878
b4ff3a36 4879 u8 reserved_at_40[0x40];
e281682b
SM		 4880};
4881
4882struct mlx5_ifc_modify_tir_in_bits {
4883 u8 opcode[0x10];
b4ff3a36 4884 u8 reserved_at_10[0x10];
e281682b 4885
b4ff3a36 4886 u8 reserved_at_20[0x10];
e281682b
SM		 4887 u8 op_mod[0x10];
4888
b4ff3a36 4889 u8 reserved_at_40[0x8];
e281682b
SM		 4890 u8 tirn[0x18];
4891
b4ff3a36 4892 u8 reserved_at_60[0x20];
e281682b 4893
d9eea403 4894 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
e281682b 4895
b4ff3a36 4896 u8 reserved_at_c0[0x40];
e281682b
SM		 4897
4898 struct mlx5_ifc_tirc_bits ctx;
4899};
4900
4901struct mlx5_ifc_modify_sq_out_bits {
4902 u8 status[0x8];
b4ff3a36 4903 u8 reserved_at_8[0x18];
e281682b
SM		 4904
4905 u8 syndrome[0x20];
4906
b4ff3a36 4907 u8 reserved_at_40[0x40];
e281682b
SM		 4908};
4909
4910struct mlx5_ifc_modify_sq_in_bits {
4911 u8 opcode[0x10];
b4ff3a36 4912 u8 reserved_at_10[0x10];
e281682b 4913
b4ff3a36 4914 u8 reserved_at_20[0x10];
e281682b
SM		 4915 u8 op_mod[0x10];
4916
4917 u8 sq_state[0x4];
b4ff3a36 4918 u8 reserved_at_44[0x4];
e281682b
SM		 4919 u8 sqn[0x18];
4920
b4ff3a36 4921 u8 reserved_at_60[0x20];
e281682b
SM		 4922
4923 u8 modify_bitmask[0x40];
4924
b4ff3a36 4925 u8 reserved_at_c0[0x40];
e281682b
SM		 4926
4927 struct mlx5_ifc_sqc_bits ctx;
4928};
4929
813f8540
MHY		 4930struct mlx5_ifc_modify_scheduling_element_out_bits {
4931 u8 status[0x8];
4932 u8 reserved_at_8[0x18];
4933
4934 u8 syndrome[0x20];
4935
4936 u8 reserved_at_40[0x1c0];
4937};
4938
4939enum {
4940 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_BW_SHARE = 0x1,
4941 MODIFY_SCHEDULING_ELEMENT_IN_MODIFY_BITMASK_MAX_AVERAGE_BW = 0x2,
4942};
4943
4944struct mlx5_ifc_modify_scheduling_element_in_bits {
4945 u8 opcode[0x10];
4946 u8 reserved_at_10[0x10];
4947
4948 u8 reserved_at_20[0x10];
4949 u8 op_mod[0x10];
4950
4951 u8 scheduling_hierarchy[0x8];
4952 u8 reserved_at_48[0x18];
4953
4954 u8 scheduling_element_id[0x20];
4955
4956 u8 reserved_at_80[0x20];
4957
4958 u8 modify_bitmask[0x20];
4959
4960 u8 reserved_at_c0[0x40];
4961
4962 struct mlx5_ifc_scheduling_context_bits scheduling_context;
4963
4964 u8 reserved_at_300[0x100];
4965};
4966
e281682b
SM		 4967struct mlx5_ifc_modify_rqt_out_bits {
4968 u8 status[0x8];
b4ff3a36 4969 u8 reserved_at_8[0x18];
e281682b
SM		 4970
4971 u8 syndrome[0x20];
4972
b4ff3a36 4973 u8 reserved_at_40[0x40];
e281682b
SM		 4974};
4975
5c50368f 4976struct mlx5_ifc_rqt_bitmask_bits {
b4ff3a36 4977 u8 reserved_at_0[0x20];
5c50368f 4978
b4ff3a36 4979 u8 reserved_at_20[0x1f];
5c50368f
AS		 4980 u8 rqn_list[0x1];
4981};
4982
e281682b
SM		 4983struct mlx5_ifc_modify_rqt_in_bits {
4984 u8 opcode[0x10];
b4ff3a36 4985 u8 reserved_at_10[0x10];
e281682b 4986
b4ff3a36 4987 u8 reserved_at_20[0x10];
e281682b
SM		 4988 u8 op_mod[0x10];
4989
b4ff3a36 4990 u8 reserved_at_40[0x8];
e281682b
SM		 4991 u8 rqtn[0x18];
4992
b4ff3a36 4993 u8 reserved_at_60[0x20];
e281682b 4994
5c50368f 4995 struct mlx5_ifc_rqt_bitmask_bits bitmask;
e281682b 4996
b4ff3a36 4997 u8 reserved_at_c0[0x40];
e281682b
SM		 4998
4999 struct mlx5_ifc_rqtc_bits ctx;
5000};
5001
5002struct mlx5_ifc_modify_rq_out_bits {
5003 u8 status[0x8];
b4ff3a36 5004 u8 reserved_at_8[0x18];
e281682b
SM		 5005
5006 u8 syndrome[0x20];
5007
b4ff3a36 5008 u8 reserved_at_40[0x40];
e281682b
SM		 5009};
5010
83b502a1
AV		 5011enum {
5012 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
5013 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID = 1ULL << 3,
5014};
5015
e281682b
SM		 5016struct mlx5_ifc_modify_rq_in_bits {
5017 u8 opcode[0x10];
b4ff3a36 5018 u8 reserved_at_10[0x10];
e281682b 5019
b4ff3a36 5020 u8 reserved_at_20[0x10];
e281682b
SM		 5021 u8 op_mod[0x10];
5022
5023 u8 rq_state[0x4];
b4ff3a36 5024 u8 reserved_at_44[0x4];
e281682b
SM		 5025 u8 rqn[0x18];
5026
b4ff3a36 5027 u8 reserved_at_60[0x20];
e281682b
SM		 5028
5029 u8 modify_bitmask[0x40];
5030
b4ff3a36 5031 u8 reserved_at_c0[0x40];
e281682b
SM		 5032
5033 struct mlx5_ifc_rqc_bits ctx;
5034};
5035
5036struct mlx5_ifc_modify_rmp_out_bits {
5037 u8 status[0x8];
b4ff3a36 5038 u8 reserved_at_8[0x18];
e281682b
SM		 5039
5040 u8 syndrome[0x20];
5041
b4ff3a36 5042 u8 reserved_at_40[0x40];
e281682b
SM		 5043};
5044
01949d01 5045struct mlx5_ifc_rmp_bitmask_bits {
b4ff3a36 5046 u8 reserved_at_0[0x20];
01949d01 5047
b4ff3a36 5048 u8 reserved_at_20[0x1f];
01949d01
HA		 5049 u8 lwm[0x1];
5050};
5051
e281682b
SM		 5052struct mlx5_ifc_modify_rmp_in_bits {
5053 u8 opcode[0x10];
b4ff3a36 5054 u8 reserved_at_10[0x10];
e281682b 5055
b4ff3a36 5056 u8 reserved_at_20[0x10];
e281682b
SM		 5057 u8 op_mod[0x10];
5058
5059 u8 rmp_state[0x4];
b4ff3a36 5060 u8 reserved_at_44[0x4];
e281682b
SM		 5061 u8 rmpn[0x18];
5062
b4ff3a36 5063 u8 reserved_at_60[0x20];
e281682b 5064
01949d01 5065 struct mlx5_ifc_rmp_bitmask_bits bitmask;
e281682b 5066
b4ff3a36 5067 u8 reserved_at_c0[0x40];
e281682b
SM		 5068
5069 struct mlx5_ifc_rmpc_bits ctx;
5070};
5071
5072struct mlx5_ifc_modify_nic_vport_context_out_bits {
5073 u8 status[0x8];
b4ff3a36 5074 u8 reserved_at_8[0x18];
e281682b
SM		 5075
5076 u8 syndrome[0x20];
5077
b4ff3a36 5078 u8 reserved_at_40[0x40];
e281682b
SM		 5079};
5080
5081struct mlx5_ifc_modify_nic_vport_field_select_bits {
23898c76
NO		 5082 u8 reserved_at_0[0x16];
5083 u8 node_guid[0x1];
5084 u8 port_guid[0x1];
9def7121 5085 u8 min_inline[0x1];
d82b7318
SM		 5086 u8 mtu[0x1];
5087 u8 change_event[0x1];
5088 u8 promisc[0x1];
e281682b
SM		 5089 u8 permanent_address[0x1];
5090 u8 addresses_list[0x1];
5091 u8 roce_en[0x1];
b4ff3a36 5092 u8 reserved_at_1f[0x1];
e281682b
SM		 5093};
5094
5095struct mlx5_ifc_modify_nic_vport_context_in_bits {
5096 u8 opcode[0x10];
b4ff3a36 5097 u8 reserved_at_10[0x10];
e281682b 5098
b4ff3a36 5099 u8 reserved_at_20[0x10];
e281682b
SM		 5100 u8 op_mod[0x10];
5101
5102 u8 other_vport[0x1];
b4ff3a36 5103 u8 reserved_at_41[0xf];
e281682b
SM		 5104 u8 vport_number[0x10];
5105
5106 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
5107
b4ff3a36 5108 u8 reserved_at_80[0x780];
e281682b
SM		 5109
5110 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
5111};
5112
5113struct mlx5_ifc_modify_hca_vport_context_out_bits {
5114 u8 status[0x8];
b4ff3a36 5115 u8 reserved_at_8[0x18];
e281682b
SM		 5116
5117 u8 syndrome[0x20];
5118
b4ff3a36 5119 u8 reserved_at_40[0x40];
e281682b
SM		 5120};
5121
5122struct mlx5_ifc_modify_hca_vport_context_in_bits {
5123 u8 opcode[0x10];
b4ff3a36 5124 u8 reserved_at_10[0x10];
e281682b 5125
b4ff3a36 5126 u8 reserved_at_20[0x10];
e281682b
SM		 5127 u8 op_mod[0x10];
5128
5129 u8 other_vport[0x1];
b4ff3a36 5130 u8 reserved_at_41[0xb];
707c4602 5131 u8 port_num[0x4];
e281682b
SM		 5132 u8 vport_number[0x10];
5133
b4ff3a36 5134 u8 reserved_at_60[0x20];
e281682b
SM		 5135
5136 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
5137};
5138
5139struct mlx5_ifc_modify_cq_out_bits {
5140 u8 status[0x8];
b4ff3a36 5141 u8 reserved_at_8[0x18];
e281682b
SM		 5142
5143 u8 syndrome[0x20];
5144
b4ff3a36 5145 u8 reserved_at_40[0x40];
e281682b
SM		 5146};
5147
5148enum {
5149 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
5150 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
5151};
5152
5153struct mlx5_ifc_modify_cq_in_bits {
5154 u8 opcode[0x10];
b4ff3a36 5155 u8 reserved_at_10[0x10];
e281682b 5156
b4ff3a36 5157 u8 reserved_at_20[0x10];
e281682b
SM		 5158 u8 op_mod[0x10];
5159
b4ff3a36 5160 u8 reserved_at_40[0x8];
e281682b
SM		 5161 u8 cqn[0x18];
5162
5163 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
5164
5165 struct mlx5_ifc_cqc_bits cq_context;
5166
b4ff3a36 5167 u8 reserved_at_280[0x600];
e281682b
SM		 5168
5169 u8 pas[0][0x40];
5170};
5171
5172struct mlx5_ifc_modify_cong_status_out_bits {
5173 u8 status[0x8];
b4ff3a36 5174 u8 reserved_at_8[0x18];
e281682b
SM		 5175
5176 u8 syndrome[0x20];
5177
b4ff3a36 5178 u8 reserved_at_40[0x40];
e281682b
SM		 5179};
5180
5181struct mlx5_ifc_modify_cong_status_in_bits {
5182 u8 opcode[0x10];
b4ff3a36 5183 u8 reserved_at_10[0x10];
e281682b 5184
b4ff3a36 5185 u8 reserved_at_20[0x10];
e281682b
SM		 5186 u8 op_mod[0x10];
5187
b4ff3a36 5188 u8 reserved_at_40[0x18];
e281682b
SM		 5189 u8 priority[0x4];
5190 u8 cong_protocol[0x4];
5191
5192 u8 enable[0x1];
5193 u8 tag_enable[0x1];
b4ff3a36 5194 u8 reserved_at_62[0x1e];
e281682b
SM		 5195};
5196
5197struct mlx5_ifc_modify_cong_params_out_bits {
5198 u8 status[0x8];
b4ff3a36 5199 u8 reserved_at_8[0x18];
e281682b
SM		 5200
5201 u8 syndrome[0x20];
5202
b4ff3a36 5203 u8 reserved_at_40[0x40];
e281682b
SM		 5204};
5205
5206struct mlx5_ifc_modify_cong_params_in_bits {
5207 u8 opcode[0x10];
b4ff3a36 5208 u8 reserved_at_10[0x10];
e281682b 5209
b4ff3a36 5210 u8 reserved_at_20[0x10];
e281682b
SM		 5211 u8 op_mod[0x10];
5212
b4ff3a36 5213 u8 reserved_at_40[0x1c];
e281682b
SM		 5214 u8 cong_protocol[0x4];
5215
5216 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
5217
b4ff3a36 5218 u8 reserved_at_80[0x80];
e281682b
SM		 5219
5220 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
5221};
5222
5223struct mlx5_ifc_manage_pages_out_bits {
5224 u8 status[0x8];
b4ff3a36 5225 u8 reserved_at_8[0x18];
e281682b
SM		 5226
5227 u8 syndrome[0x20];
5228
5229 u8 output_num_entries[0x20];
5230
b4ff3a36 5231 u8 reserved_at_60[0x20];
e281682b
SM		 5232
5233 u8 pas[0][0x40];
5234};
5235
5236enum {
5237 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
5238 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
5239 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
5240};
5241
5242struct mlx5_ifc_manage_pages_in_bits {
5243 u8 opcode[0x10];
b4ff3a36 5244 u8 reserved_at_10[0x10];
e281682b 5245
b4ff3a36 5246 u8 reserved_at_20[0x10];
e281682b
SM		 5247 u8 op_mod[0x10];
5248
b4ff3a36 5249 u8 reserved_at_40[0x10];
e281682b
SM		 5250 u8 function_id[0x10];
5251
5252 u8 input_num_entries[0x20];
5253
5254 u8 pas[0][0x40];
5255};
5256
5257struct mlx5_ifc_mad_ifc_out_bits {
5258 u8 status[0x8];
b4ff3a36 5259 u8 reserved_at_8[0x18];
e281682b
SM		 5260
5261 u8 syndrome[0x20];
5262
b4ff3a36 5263 u8 reserved_at_40[0x40];
e281682b
SM		 5264
5265 u8 response_mad_packet[256][0x8];
5266};
5267
5268struct mlx5_ifc_mad_ifc_in_bits {
5269 u8 opcode[0x10];
b4ff3a36 5270 u8 reserved_at_10[0x10];
e281682b 5271
b4ff3a36 5272 u8 reserved_at_20[0x10];
e281682b
SM		 5273 u8 op_mod[0x10];
5274
5275 u8 remote_lid[0x10];
b4ff3a36 5276 u8 reserved_at_50[0x8];
e281682b
SM		 5277 u8 port[0x8];
5278
b4ff3a36 5279 u8 reserved_at_60[0x20];
e281682b
SM		 5280
5281 u8 mad[256][0x8];
5282};
5283
5284struct mlx5_ifc_init_hca_out_bits {
5285 u8 status[0x8];
b4ff3a36 5286 u8 reserved_at_8[0x18];
e281682b
SM		 5287
5288 u8 syndrome[0x20];
5289
b4ff3a36 5290 u8 reserved_at_40[0x40];
e281682b
SM		 5291};
5292
5293struct mlx5_ifc_init_hca_in_bits {
5294 u8 opcode[0x10];
b4ff3a36 5295 u8 reserved_at_10[0x10];
e281682b 5296
b4ff3a36 5297 u8 reserved_at_20[0x10];
e281682b
SM		 5298 u8 op_mod[0x10];
5299
b4ff3a36 5300 u8 reserved_at_40[0x40];
e281682b
SM		 5301};
5302
5303struct mlx5_ifc_init2rtr_qp_out_bits {
5304 u8 status[0x8];
b4ff3a36 5305 u8 reserved_at_8[0x18];
e281682b
SM		 5306
5307 u8 syndrome[0x20];
5308
b4ff3a36 5309 u8 reserved_at_40[0x40];
e281682b
SM		 5310};
5311
5312struct mlx5_ifc_init2rtr_qp_in_bits {
5313 u8 opcode[0x10];
b4ff3a36 5314 u8 reserved_at_10[0x10];
e281682b 5315
b4ff3a36 5316 u8 reserved_at_20[0x10];
e281682b
SM		 5317 u8 op_mod[0x10];
5318
b4ff3a36 5319 u8 reserved_at_40[0x8];
e281682b
SM		 5320 u8 qpn[0x18];
5321
b4ff3a36 5322 u8 reserved_at_60[0x20];
e281682b
SM		 5323
5324 u8 opt_param_mask[0x20];
5325
b4ff3a36 5326 u8 reserved_at_a0[0x20];
e281682b
SM		 5327
5328 struct mlx5_ifc_qpc_bits qpc;
5329
b4ff3a36 5330 u8 reserved_at_800[0x80];
e281682b
SM		 5331};
5332
5333struct mlx5_ifc_init2init_qp_out_bits {
5334 u8 status[0x8];
b4ff3a36 5335 u8 reserved_at_8[0x18];
e281682b
SM		 5336
5337 u8 syndrome[0x20];
5338
b4ff3a36 5339 u8 reserved_at_40[0x40];
e281682b
SM		 5340};
5341
5342struct mlx5_ifc_init2init_qp_in_bits {
5343 u8 opcode[0x10];
b4ff3a36 5344 u8 reserved_at_10[0x10];
e281682b 5345
b4ff3a36 5346 u8 reserved_at_20[0x10];
e281682b
SM		 5347 u8 op_mod[0x10];
5348
b4ff3a36 5349 u8 reserved_at_40[0x8];
e281682b
SM		 5350 u8 qpn[0x18];
5351
b4ff3a36 5352 u8 reserved_at_60[0x20];
e281682b
SM		 5353
5354 u8 opt_param_mask[0x20];
5355
b4ff3a36 5356 u8 reserved_at_a0[0x20];
e281682b
SM		 5357
5358 struct mlx5_ifc_qpc_bits qpc;
5359
b4ff3a36 5360 u8 reserved_at_800[0x80];
e281682b
SM		 5361};
5362
5363struct mlx5_ifc_get_dropped_packet_log_out_bits {
5364 u8 status[0x8];
b4ff3a36 5365 u8 reserved_at_8[0x18];
e281682b
SM		 5366
5367 u8 syndrome[0x20];
5368
b4ff3a36 5369 u8 reserved_at_40[0x40];
e281682b
SM		 5370
5371 u8 packet_headers_log[128][0x8];
5372
5373 u8 packet_syndrome[64][0x8];
5374};
5375
5376struct mlx5_ifc_get_dropped_packet_log_in_bits {
5377 u8 opcode[0x10];
b4ff3a36 5378 u8 reserved_at_10[0x10];
e281682b 5379
b4ff3a36 5380 u8 reserved_at_20[0x10];
e281682b
SM		 5381 u8 op_mod[0x10];
5382
b4ff3a36 5383 u8 reserved_at_40[0x40];
e281682b
SM		 5384};
5385
5386struct mlx5_ifc_gen_eqe_in_bits {
5387 u8 opcode[0x10];
b4ff3a36 5388 u8 reserved_at_10[0x10];
e281682b 5389
b4ff3a36 5390 u8 reserved_at_20[0x10];
e281682b
SM		 5391 u8 op_mod[0x10];
5392
b4ff3a36 5393 u8 reserved_at_40[0x18];
e281682b
SM		 5394 u8 eq_number[0x8];
5395
b4ff3a36 5396 u8 reserved_at_60[0x20];
e281682b
SM		 5397
5398 u8 eqe[64][0x8];
5399};
5400
5401struct mlx5_ifc_gen_eq_out_bits {
5402 u8 status[0x8];
b4ff3a36 5403 u8 reserved_at_8[0x18];
e281682b
SM		 5404
5405 u8 syndrome[0x20];
5406
b4ff3a36 5407 u8 reserved_at_40[0x40];
e281682b
SM		 5408};
5409
5410struct mlx5_ifc_enable_hca_out_bits {
5411 u8 status[0x8];
b4ff3a36 5412 u8 reserved_at_8[0x18];
e281682b
SM		 5413
5414 u8 syndrome[0x20];
5415
b4ff3a36 5416 u8 reserved_at_40[0x20];
e281682b
SM		 5417};
5418
5419struct mlx5_ifc_enable_hca_in_bits {
5420 u8 opcode[0x10];
b4ff3a36 5421 u8 reserved_at_10[0x10];
e281682b 5422
b4ff3a36 5423 u8 reserved_at_20[0x10];
e281682b
SM		 5424 u8 op_mod[0x10];
5425
b4ff3a36 5426 u8 reserved_at_40[0x10];
e281682b
SM		 5427 u8 function_id[0x10];
5428
b4ff3a36 5429 u8 reserved_at_60[0x20];
e281682b
SM		 5430};
5431
5432struct mlx5_ifc_drain_dct_out_bits {
5433 u8 status[0x8];
b4ff3a36 5434 u8 reserved_at_8[0x18];
e281682b
SM		 5435
5436 u8 syndrome[0x20];
5437
b4ff3a36 5438 u8 reserved_at_40[0x40];
e281682b
SM		 5439};
5440
5441struct mlx5_ifc_drain_dct_in_bits {
5442 u8 opcode[0x10];
b4ff3a36 5443 u8 reserved_at_10[0x10];
e281682b 5444
b4ff3a36 5445 u8 reserved_at_20[0x10];
e281682b
SM		 5446 u8 op_mod[0x10];
5447
b4ff3a36 5448 u8 reserved_at_40[0x8];
e281682b
SM		 5449 u8 dctn[0x18];
5450
b4ff3a36 5451 u8 reserved_at_60[0x20];
e281682b
SM		 5452};
5453
5454struct mlx5_ifc_disable_hca_out_bits {
5455 u8 status[0x8];
b4ff3a36 5456 u8 reserved_at_8[0x18];
e281682b
SM		 5457
5458 u8 syndrome[0x20];
5459
b4ff3a36 5460 u8 reserved_at_40[0x20];
e281682b
SM		 5461};
5462
5463struct mlx5_ifc_disable_hca_in_bits {
5464 u8 opcode[0x10];
b4ff3a36 5465 u8 reserved_at_10[0x10];
e281682b 5466
b4ff3a36 5467 u8 reserved_at_20[0x10];
e281682b
SM		 5468 u8 op_mod[0x10];
5469
b4ff3a36 5470 u8 reserved_at_40[0x10];
e281682b
SM		 5471 u8 function_id[0x10];
5472
b4ff3a36 5473 u8 reserved_at_60[0x20];
e281682b
SM		 5474};
5475
5476struct mlx5_ifc_detach_from_mcg_out_bits {
5477 u8 status[0x8];
b4ff3a36 5478 u8 reserved_at_8[0x18];
e281682b
SM		 5479
5480 u8 syndrome[0x20];
5481
b4ff3a36 5482 u8 reserved_at_40[0x40];
e281682b
SM		 5483};
5484
5485struct mlx5_ifc_detach_from_mcg_in_bits {
5486 u8 opcode[0x10];
b4ff3a36 5487 u8 reserved_at_10[0x10];
e281682b 5488
b4ff3a36 5489 u8 reserved_at_20[0x10];
e281682b
SM		 5490 u8 op_mod[0x10];
5491
b4ff3a36 5492 u8 reserved_at_40[0x8];
e281682b
SM		 5493 u8 qpn[0x18];
5494
b4ff3a36 5495 u8 reserved_at_60[0x20];
e281682b
SM		 5496
5497 u8 multicast_gid[16][0x8];
5498};
5499
7486216b
SM		 5500struct mlx5_ifc_destroy_xrq_out_bits {
5501 u8 status[0x8];
5502 u8 reserved_at_8[0x18];
5503
5504 u8 syndrome[0x20];
5505
5506 u8 reserved_at_40[0x40];
5507};
5508
5509struct mlx5_ifc_destroy_xrq_in_bits {
5510 u8 opcode[0x10];
5511 u8 reserved_at_10[0x10];
5512
5513 u8 reserved_at_20[0x10];
5514 u8 op_mod[0x10];
5515
5516 u8 reserved_at_40[0x8];
5517 u8 xrqn[0x18];
5518
5519 u8 reserved_at_60[0x20];
5520};
5521
e281682b
SM		 5522struct mlx5_ifc_destroy_xrc_srq_out_bits {
5523 u8 status[0x8];
b4ff3a36 5524 u8 reserved_at_8[0x18];
e281682b
SM		 5525
5526 u8 syndrome[0x20];
5527
b4ff3a36 5528 u8 reserved_at_40[0x40];
e281682b
SM		 5529};
5530
5531struct mlx5_ifc_destroy_xrc_srq_in_bits {
5532 u8 opcode[0x10];
b4ff3a36 5533 u8 reserved_at_10[0x10];
e281682b 5534
b4ff3a36 5535 u8 reserved_at_20[0x10];
e281682b
SM		 5536 u8 op_mod[0x10];
5537
b4ff3a36 5538 u8 reserved_at_40[0x8];
e281682b
SM		 5539 u8 xrc_srqn[0x18];
5540
b4ff3a36 5541 u8 reserved_at_60[0x20];
e281682b
SM		 5542};
5543
5544struct mlx5_ifc_destroy_tis_out_bits {
5545 u8 status[0x8];
b4ff3a36 5546 u8 reserved_at_8[0x18];
e281682b
SM		 5547
5548 u8 syndrome[0x20];
5549
b4ff3a36 5550 u8 reserved_at_40[0x40];
e281682b
SM		 5551};
5552
5553struct mlx5_ifc_destroy_tis_in_bits {
5554 u8 opcode[0x10];
b4ff3a36 5555 u8 reserved_at_10[0x10];
e281682b 5556
b4ff3a36 5557 u8 reserved_at_20[0x10];
e281682b
SM		 5558 u8 op_mod[0x10];
5559
b4ff3a36 5560 u8 reserved_at_40[0x8];
e281682b
SM		 5561 u8 tisn[0x18];
5562
b4ff3a36 5563 u8 reserved_at_60[0x20];
e281682b
SM		 5564};
5565
5566struct mlx5_ifc_destroy_tir_out_bits {
5567 u8 status[0x8];
b4ff3a36 5568 u8 reserved_at_8[0x18];
e281682b
SM		 5569
5570 u8 syndrome[0x20];
5571
b4ff3a36 5572 u8 reserved_at_40[0x40];
e281682b
SM		 5573};
5574
5575struct mlx5_ifc_destroy_tir_in_bits {
5576 u8 opcode[0x10];
b4ff3a36 5577 u8 reserved_at_10[0x10];
e281682b 5578
b4ff3a36 5579 u8 reserved_at_20[0x10];
e281682b
SM		 5580 u8 op_mod[0x10];
5581
b4ff3a36 5582 u8 reserved_at_40[0x8];
e281682b
SM		 5583 u8 tirn[0x18];
5584
b4ff3a36 5585 u8 reserved_at_60[0x20];
e281682b
SM		 5586};
5587
5588struct mlx5_ifc_destroy_srq_out_bits {
5589 u8 status[0x8];
b4ff3a36 5590 u8 reserved_at_8[0x18];
e281682b
SM		 5591
5592 u8 syndrome[0x20];
5593
b4ff3a36 5594 u8 reserved_at_40[0x40];
e281682b
SM		 5595};
5596
5597struct mlx5_ifc_destroy_srq_in_bits {
5598 u8 opcode[0x10];
b4ff3a36 5599 u8 reserved_at_10[0x10];
e281682b 5600
b4ff3a36 5601 u8 reserved_at_20[0x10];
e281682b
SM		 5602 u8 op_mod[0x10];
5603
b4ff3a36 5604 u8 reserved_at_40[0x8];
e281682b
SM		 5605 u8 srqn[0x18];
5606
b4ff3a36 5607 u8 reserved_at_60[0x20];
e281682b
SM		 5608};
5609
5610struct mlx5_ifc_destroy_sq_out_bits {
5611 u8 status[0x8];
b4ff3a36 5612 u8 reserved_at_8[0x18];
e281682b
SM		 5613
5614 u8 syndrome[0x20];
5615
b4ff3a36 5616 u8 reserved_at_40[0x40];
e281682b
SM		 5617};
5618
5619struct mlx5_ifc_destroy_sq_in_bits {
5620 u8 opcode[0x10];
b4ff3a36 5621 u8 reserved_at_10[0x10];
e281682b 5622
b4ff3a36 5623 u8 reserved_at_20[0x10];
e281682b
SM		 5624 u8 op_mod[0x10];
5625
b4ff3a36 5626 u8 reserved_at_40[0x8];
e281682b
SM		 5627 u8 sqn[0x18];
5628
b4ff3a36 5629 u8 reserved_at_60[0x20];
e281682b
SM		 5630};
5631
813f8540
MHY		 5632struct mlx5_ifc_destroy_scheduling_element_out_bits {
5633 u8 status[0x8];
5634 u8 reserved_at_8[0x18];
5635
5636 u8 syndrome[0x20];
5637
5638 u8 reserved_at_40[0x1c0];
5639};
5640
5641struct mlx5_ifc_destroy_scheduling_element_in_bits {
5642 u8 opcode[0x10];
5643 u8 reserved_at_10[0x10];
5644
5645 u8 reserved_at_20[0x10];
5646 u8 op_mod[0x10];
5647
5648 u8 scheduling_hierarchy[0x8];
5649 u8 reserved_at_48[0x18];
5650
5651 u8 scheduling_element_id[0x20];
5652
5653 u8 reserved_at_80[0x180];
5654};
5655
e281682b
SM		 5656struct mlx5_ifc_destroy_rqt_out_bits {
5657 u8 status[0x8];
b4ff3a36 5658 u8 reserved_at_8[0x18];
e281682b
SM		 5659
5660 u8 syndrome[0x20];
5661
b4ff3a36 5662 u8 reserved_at_40[0x40];
e281682b
SM		 5663};
5664
5665struct mlx5_ifc_destroy_rqt_in_bits {
5666 u8 opcode[0x10];
b4ff3a36 5667 u8 reserved_at_10[0x10];
e281682b 5668
b4ff3a36 5669 u8 reserved_at_20[0x10];
e281682b
SM		 5670 u8 op_mod[0x10];
5671
b4ff3a36 5672 u8 reserved_at_40[0x8];
e281682b
SM		 5673 u8 rqtn[0x18];
5674
b4ff3a36 5675 u8 reserved_at_60[0x20];
e281682b
SM		 5676};
5677
5678struct mlx5_ifc_destroy_rq_out_bits {
5679 u8 status[0x8];
b4ff3a36 5680 u8 reserved_at_8[0x18];
e281682b
SM		 5681
5682 u8 syndrome[0x20];
5683
b4ff3a36 5684 u8 reserved_at_40[0x40];
e281682b
SM		 5685};
5686
5687struct mlx5_ifc_destroy_rq_in_bits {
5688 u8 opcode[0x10];
b4ff3a36 5689 u8 reserved_at_10[0x10];
e281682b 5690
b4ff3a36 5691 u8 reserved_at_20[0x10];
e281682b
SM		 5692 u8 op_mod[0x10];
5693
b4ff3a36 5694 u8 reserved_at_40[0x8];
e281682b
SM		 5695 u8 rqn[0x18];
5696
b4ff3a36 5697 u8 reserved_at_60[0x20];
e281682b
SM		 5698};
5699
5700struct mlx5_ifc_destroy_rmp_out_bits {
5701 u8 status[0x8];
b4ff3a36 5702 u8 reserved_at_8[0x18];
e281682b
SM		 5703
5704 u8 syndrome[0x20];
5705
b4ff3a36 5706 u8 reserved_at_40[0x40];
e281682b
SM		 5707};
5708
5709struct mlx5_ifc_destroy_rmp_in_bits {
5710 u8 opcode[0x10];
b4ff3a36 5711 u8 reserved_at_10[0x10];
e281682b 5712
b4ff3a36 5713 u8 reserved_at_20[0x10];
e281682b
SM		 5714 u8 op_mod[0x10];
5715
b4ff3a36 5716 u8 reserved_at_40[0x8];
e281682b
SM		 5717 u8 rmpn[0x18];
5718
b4ff3a36 5719 u8 reserved_at_60[0x20];
e281682b
SM		 5720};
5721
5722struct mlx5_ifc_destroy_qp_out_bits {
5723 u8 status[0x8];
b4ff3a36 5724 u8 reserved_at_8[0x18];
e281682b
SM		 5725
5726 u8 syndrome[0x20];
5727
b4ff3a36 5728 u8 reserved_at_40[0x40];
e281682b
SM		 5729};
5730
5731struct mlx5_ifc_destroy_qp_in_bits {
5732 u8 opcode[0x10];
b4ff3a36 5733 u8 reserved_at_10[0x10];
e281682b 5734
b4ff3a36 5735 u8 reserved_at_20[0x10];
e281682b
SM		 5736 u8 op_mod[0x10];
5737
b4ff3a36 5738 u8 reserved_at_40[0x8];
e281682b
SM		 5739 u8 qpn[0x18];
5740
b4ff3a36 5741 u8 reserved_at_60[0x20];
e281682b
SM		 5742};
5743
5744struct mlx5_ifc_destroy_psv_out_bits {
5745 u8 status[0x8];
b4ff3a36 5746 u8 reserved_at_8[0x18];
e281682b
SM		 5747
5748 u8 syndrome[0x20];
5749
b4ff3a36 5750 u8 reserved_at_40[0x40];
e281682b
SM		 5751};
5752
5753struct mlx5_ifc_destroy_psv_in_bits {
5754 u8 opcode[0x10];
b4ff3a36 5755 u8 reserved_at_10[0x10];
e281682b 5756
b4ff3a36 5757 u8 reserved_at_20[0x10];
e281682b
SM		 5758 u8 op_mod[0x10];
5759
b4ff3a36 5760 u8 reserved_at_40[0x8];
e281682b
SM		 5761 u8 psvn[0x18];
5762
b4ff3a36 5763 u8 reserved_at_60[0x20];
e281682b
SM		 5764};
5765
5766struct mlx5_ifc_destroy_mkey_out_bits {
5767 u8 status[0x8];
b4ff3a36 5768 u8 reserved_at_8[0x18];
e281682b
SM		 5769
5770 u8 syndrome[0x20];
5771
b4ff3a36 5772 u8 reserved_at_40[0x40];
e281682b
SM		 5773};
5774
5775struct mlx5_ifc_destroy_mkey_in_bits {
5776 u8 opcode[0x10];
b4ff3a36 5777 u8 reserved_at_10[0x10];
e281682b 5778
b4ff3a36 5779 u8 reserved_at_20[0x10];
e281682b
SM		 5780 u8 op_mod[0x10];
5781
b4ff3a36 5782 u8 reserved_at_40[0x8];
e281682b
SM		 5783 u8 mkey_index[0x18];
5784
b4ff3a36 5785 u8 reserved_at_60[0x20];
e281682b
SM		 5786};
5787
5788struct mlx5_ifc_destroy_flow_table_out_bits {
5789 u8 status[0x8];
b4ff3a36 5790 u8 reserved_at_8[0x18];
e281682b
SM		 5791
5792 u8 syndrome[0x20];
5793
b4ff3a36 5794 u8 reserved_at_40[0x40];
e281682b
SM		 5795};
5796
5797struct mlx5_ifc_destroy_flow_table_in_bits {
5798 u8 opcode[0x10];
b4ff3a36 5799 u8 reserved_at_10[0x10];
e281682b 5800
b4ff3a36 5801 u8 reserved_at_20[0x10];
e281682b
SM		 5802 u8 op_mod[0x10];
5803
7d5e1423
SM		 5804 u8 other_vport[0x1];
5805 u8 reserved_at_41[0xf];
5806 u8 vport_number[0x10];
5807
5808 u8 reserved_at_60[0x20];
e281682b
SM		 5809
5810 u8 table_type[0x8];
b4ff3a36 5811 u8 reserved_at_88[0x18];
e281682b 5812
b4ff3a36 5813 u8 reserved_at_a0[0x8];
e281682b
SM		 5814 u8 table_id[0x18];
5815
b4ff3a36 5816 u8 reserved_at_c0[0x140];
e281682b
SM		 5817};
5818
5819struct mlx5_ifc_destroy_flow_group_out_bits {
5820 u8 status[0x8];
b4ff3a36 5821 u8 reserved_at_8[0x18];
e281682b
SM		 5822
5823 u8 syndrome[0x20];
5824
b4ff3a36 5825 u8 reserved_at_40[0x40];
e281682b
SM		 5826};
5827
5828struct mlx5_ifc_destroy_flow_group_in_bits {
5829 u8 opcode[0x10];
b4ff3a36 5830 u8 reserved_at_10[0x10];
e281682b 5831
b4ff3a36 5832 u8 reserved_at_20[0x10];
e281682b
SM		 5833 u8 op_mod[0x10];
5834
7d5e1423
SM		 5835 u8 other_vport[0x1];
5836 u8 reserved_at_41[0xf];
5837 u8 vport_number[0x10];
5838
5839 u8 reserved_at_60[0x20];
e281682b
SM		 5840
5841 u8 table_type[0x8];
b4ff3a36 5842 u8 reserved_at_88[0x18];
e281682b 5843
b4ff3a36 5844 u8 reserved_at_a0[0x8];
e281682b
SM		 5845 u8 table_id[0x18];
5846
5847 u8 group_id[0x20];
5848
b4ff3a36 5849 u8 reserved_at_e0[0x120];
e281682b
SM		 5850};
5851
5852struct mlx5_ifc_destroy_eq_out_bits {
5853 u8 status[0x8];
b4ff3a36 5854 u8 reserved_at_8[0x18];
e281682b
SM		 5855
5856 u8 syndrome[0x20];
5857
b4ff3a36 5858 u8 reserved_at_40[0x40];
e281682b
SM		 5859};
5860
5861struct mlx5_ifc_destroy_eq_in_bits {
5862 u8 opcode[0x10];
b4ff3a36 5863 u8 reserved_at_10[0x10];
e281682b 5864
b4ff3a36 5865 u8 reserved_at_20[0x10];
e281682b
SM		 5866 u8 op_mod[0x10];
5867
b4ff3a36 5868 u8 reserved_at_40[0x18];
e281682b
SM		 5869 u8 eq_number[0x8];
5870
b4ff3a36 5871 u8 reserved_at_60[0x20];
e281682b
SM		 5872};
5873
5874struct mlx5_ifc_destroy_dct_out_bits {
5875 u8 status[0x8];
b4ff3a36 5876 u8 reserved_at_8[0x18];
e281682b
SM		 5877
5878 u8 syndrome[0x20];
5879
b4ff3a36 5880 u8 reserved_at_40[0x40];
e281682b
SM		 5881};
5882
5883struct mlx5_ifc_destroy_dct_in_bits {
5884 u8 opcode[0x10];
b4ff3a36 5885 u8 reserved_at_10[0x10];
e281682b 5886
b4ff3a36 5887 u8 reserved_at_20[0x10];
e281682b
SM		 5888 u8 op_mod[0x10];
5889
b4ff3a36 5890 u8 reserved_at_40[0x8];
e281682b
SM		 5891 u8 dctn[0x18];
5892
b4ff3a36 5893 u8 reserved_at_60[0x20];
e281682b
SM		 5894};
5895
5896struct mlx5_ifc_destroy_cq_out_bits {
5897 u8 status[0x8];
b4ff3a36 5898 u8 reserved_at_8[0x18];
e281682b
SM		 5899
5900 u8 syndrome[0x20];
5901
b4ff3a36 5902 u8 reserved_at_40[0x40];
e281682b
SM		 5903};
5904
5905struct mlx5_ifc_destroy_cq_in_bits {
5906 u8 opcode[0x10];
b4ff3a36 5907 u8 reserved_at_10[0x10];
e281682b 5908
b4ff3a36 5909 u8 reserved_at_20[0x10];
e281682b
SM		 5910 u8 op_mod[0x10];
5911
b4ff3a36 5912 u8 reserved_at_40[0x8];
e281682b
SM		 5913 u8 cqn[0x18];
5914
b4ff3a36 5915 u8 reserved_at_60[0x20];
e281682b
SM		 5916};
5917
5918struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
5919 u8 status[0x8];
b4ff3a36 5920 u8 reserved_at_8[0x18];
e281682b
SM		 5921
5922 u8 syndrome[0x20];
5923
b4ff3a36 5924 u8 reserved_at_40[0x40];
e281682b
SM		 5925};
5926
5927struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
5928 u8 opcode[0x10];
b4ff3a36 5929 u8 reserved_at_10[0x10];
e281682b 5930
b4ff3a36 5931 u8 reserved_at_20[0x10];
e281682b
SM		 5932 u8 op_mod[0x10];
5933
b4ff3a36 5934 u8 reserved_at_40[0x20];
e281682b 5935
b4ff3a36 5936 u8 reserved_at_60[0x10];
e281682b
SM		 5937 u8 vxlan_udp_port[0x10];
5938};
5939
5940struct mlx5_ifc_delete_l2_table_entry_out_bits {
5941 u8 status[0x8];
b4ff3a36 5942 u8 reserved_at_8[0x18];
e281682b
SM		 5943
5944 u8 syndrome[0x20];
5945
b4ff3a36 5946 u8 reserved_at_40[0x40];
e281682b
SM		 5947};
5948
5949struct mlx5_ifc_delete_l2_table_entry_in_bits {
5950 u8 opcode[0x10];
b4ff3a36 5951 u8 reserved_at_10[0x10];
e281682b 5952
b4ff3a36 5953 u8 reserved_at_20[0x10];
e281682b
SM		 5954 u8 op_mod[0x10];
5955
b4ff3a36 5956 u8 reserved_at_40[0x60];
e281682b 5957
b4ff3a36 5958 u8 reserved_at_a0[0x8];
e281682b
SM		 5959 u8 table_index[0x18];
5960
b4ff3a36 5961 u8 reserved_at_c0[0x140];
e281682b
SM		 5962};
5963
5964struct mlx5_ifc_delete_fte_out_bits {
5965 u8 status[0x8];
b4ff3a36 5966 u8 reserved_at_8[0x18];
e281682b
SM		 5967
5968 u8 syndrome[0x20];
5969
b4ff3a36 5970 u8 reserved_at_40[0x40];
e281682b
SM		 5971};
5972
5973struct mlx5_ifc_delete_fte_in_bits {
5974 u8 opcode[0x10];
b4ff3a36 5975 u8 reserved_at_10[0x10];
e281682b 5976
b4ff3a36 5977 u8 reserved_at_20[0x10];
e281682b
SM		 5978 u8 op_mod[0x10];
5979
7d5e1423
SM		 5980 u8 other_vport[0x1];
5981 u8 reserved_at_41[0xf];
5982 u8 vport_number[0x10];
5983
5984 u8 reserved_at_60[0x20];
e281682b
SM		 5985
5986 u8 table_type[0x8];
b4ff3a36 5987 u8 reserved_at_88[0x18];
e281682b 5988
b4ff3a36 5989 u8 reserved_at_a0[0x8];
e281682b
SM		 5990 u8 table_id[0x18];
5991
b4ff3a36 5992 u8 reserved_at_c0[0x40];
e281682b
SM		 5993
5994 u8 flow_index[0x20];
5995
b4ff3a36 5996 u8 reserved_at_120[0xe0];
e281682b
SM		 5997};
5998
5999struct mlx5_ifc_dealloc_xrcd_out_bits {
6000 u8 status[0x8];
b4ff3a36 6001 u8 reserved_at_8[0x18];
e281682b
SM		 6002
6003 u8 syndrome[0x20];
6004
b4ff3a36 6005 u8 reserved_at_40[0x40];
e281682b
SM		 6006};
6007
6008struct mlx5_ifc_dealloc_xrcd_in_bits {
6009 u8 opcode[0x10];
b4ff3a36 6010 u8 reserved_at_10[0x10];
e281682b 6011
b4ff3a36 6012 u8 reserved_at_20[0x10];
e281682b
SM		 6013 u8 op_mod[0x10];
6014
b4ff3a36 6015 u8 reserved_at_40[0x8];
e281682b
SM		 6016 u8 xrcd[0x18];
6017
b4ff3a36 6018 u8 reserved_at_60[0x20];
e281682b
SM		 6019};
6020
6021struct mlx5_ifc_dealloc_uar_out_bits {
6022 u8 status[0x8];
b4ff3a36 6023 u8 reserved_at_8[0x18];
e281682b
SM		 6024
6025 u8 syndrome[0x20];
6026
b4ff3a36 6027 u8 reserved_at_40[0x40];
e281682b
SM		 6028};
6029
6030struct mlx5_ifc_dealloc_uar_in_bits {
6031 u8 opcode[0x10];
b4ff3a36 6032 u8 reserved_at_10[0x10];
e281682b 6033
b4ff3a36 6034 u8 reserved_at_20[0x10];
e281682b
SM		 6035 u8 op_mod[0x10];
6036
b4ff3a36 6037 u8 reserved_at_40[0x8];
e281682b
SM		 6038 u8 uar[0x18];
6039
b4ff3a36 6040 u8 reserved_at_60[0x20];
e281682b
SM		 6041};
6042
6043struct mlx5_ifc_dealloc_transport_domain_out_bits {
6044 u8 status[0x8];
b4ff3a36 6045 u8 reserved_at_8[0x18];
e281682b
SM		 6046
6047 u8 syndrome[0x20];
6048
b4ff3a36 6049 u8 reserved_at_40[0x40];
e281682b
SM		 6050};
6051
6052struct mlx5_ifc_dealloc_transport_domain_in_bits {
6053 u8 opcode[0x10];
b4ff3a36 6054 u8 reserved_at_10[0x10];
e281682b 6055
b4ff3a36 6056 u8 reserved_at_20[0x10];
e281682b
SM		 6057 u8 op_mod[0x10];
6058
b4ff3a36 6059 u8 reserved_at_40[0x8];
e281682b
SM		 6060 u8 transport_domain[0x18];
6061
b4ff3a36 6062 u8 reserved_at_60[0x20];
e281682b
SM		 6063};
6064
6065struct mlx5_ifc_dealloc_q_counter_out_bits {
6066 u8 status[0x8];
b4ff3a36 6067 u8 reserved_at_8[0x18];
e281682b
SM		 6068
6069 u8 syndrome[0x20];
6070
b4ff3a36 6071 u8 reserved_at_40[0x40];
e281682b
SM		 6072};
6073
6074struct mlx5_ifc_dealloc_q_counter_in_bits {
6075 u8 opcode[0x10];
b4ff3a36 6076 u8 reserved_at_10[0x10];
e281682b 6077
b4ff3a36 6078 u8 reserved_at_20[0x10];
e281682b
SM		 6079 u8 op_mod[0x10];
6080
b4ff3a36 6081 u8 reserved_at_40[0x18];
e281682b
SM		 6082 u8 counter_set_id[0x8];
6083
b4ff3a36 6084 u8 reserved_at_60[0x20];
e281682b
SM		 6085};
6086
6087struct mlx5_ifc_dealloc_pd_out_bits {
6088 u8 status[0x8];
b4ff3a36 6089 u8 reserved_at_8[0x18];
e281682b
SM		 6090
6091 u8 syndrome[0x20];
6092
b4ff3a36 6093 u8 reserved_at_40[0x40];
e281682b
SM		 6094};
6095
6096struct mlx5_ifc_dealloc_pd_in_bits {
6097 u8 opcode[0x10];
b4ff3a36 6098 u8 reserved_at_10[0x10];
e281682b 6099
b4ff3a36 6100 u8 reserved_at_20[0x10];
e281682b
SM		 6101 u8 op_mod[0x10];
6102
b4ff3a36 6103 u8 reserved_at_40[0x8];
e281682b
SM		 6104 u8 pd[0x18];
6105
b4ff3a36 6106 u8 reserved_at_60[0x20];
e281682b
SM		 6107};
6108
9dc0b289
AV		 6109struct mlx5_ifc_dealloc_flow_counter_out_bits {
6110 u8 status[0x8];
6111 u8 reserved_at_8[0x18];
6112
6113 u8 syndrome[0x20];
6114
6115 u8 reserved_at_40[0x40];
6116};
6117
6118struct mlx5_ifc_dealloc_flow_counter_in_bits {
6119 u8 opcode[0x10];
6120 u8 reserved_at_10[0x10];
6121
6122 u8 reserved_at_20[0x10];
6123 u8 op_mod[0x10];
6124
6125 u8 reserved_at_40[0x10];
6126 u8 flow_counter_id[0x10];
6127
6128 u8 reserved_at_60[0x20];
6129};
6130
7486216b
SM		 6131struct mlx5_ifc_create_xrq_out_bits {
6132 u8 status[0x8];
6133 u8 reserved_at_8[0x18];
6134
6135 u8 syndrome[0x20];
6136
6137 u8 reserved_at_40[0x8];
6138 u8 xrqn[0x18];
6139
6140 u8 reserved_at_60[0x20];
6141};
6142
6143struct mlx5_ifc_create_xrq_in_bits {
6144 u8 opcode[0x10];
6145 u8 reserved_at_10[0x10];
6146
6147 u8 reserved_at_20[0x10];
6148 u8 op_mod[0x10];
6149
6150 u8 reserved_at_40[0x40];
6151
6152 struct mlx5_ifc_xrqc_bits xrq_context;
6153};
6154
e281682b
SM		 6155struct mlx5_ifc_create_xrc_srq_out_bits {
6156 u8 status[0x8];
b4ff3a36 6157 u8 reserved_at_8[0x18];
e281682b
SM		 6158
6159 u8 syndrome[0x20];
6160
b4ff3a36 6161 u8 reserved_at_40[0x8];
e281682b
SM		 6162 u8 xrc_srqn[0x18];
6163
b4ff3a36 6164 u8 reserved_at_60[0x20];
e281682b
SM		 6165};
6166
6167struct mlx5_ifc_create_xrc_srq_in_bits {
6168 u8 opcode[0x10];
b4ff3a36 6169 u8 reserved_at_10[0x10];
e281682b 6170
b4ff3a36 6171 u8 reserved_at_20[0x10];
e281682b
SM		 6172 u8 op_mod[0x10];
6173
b4ff3a36 6174 u8 reserved_at_40[0x40];
e281682b
SM		 6175
6176 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
6177
b4ff3a36 6178 u8 reserved_at_280[0x600];
e281682b
SM		 6179
6180 u8 pas[0][0x40];
6181};
6182
6183struct mlx5_ifc_create_tis_out_bits {
6184 u8 status[0x8];
b4ff3a36 6185 u8 reserved_at_8[0x18];
e281682b
SM		 6186
6187 u8 syndrome[0x20];
6188
b4ff3a36 6189 u8 reserved_at_40[0x8];
e281682b
SM		 6190 u8 tisn[0x18];
6191
b4ff3a36 6192 u8 reserved_at_60[0x20];
e281682b
SM		 6193};
6194
6195struct mlx5_ifc_create_tis_in_bits {
6196 u8 opcode[0x10];
b4ff3a36 6197 u8 reserved_at_10[0x10];
e281682b 6198
b4ff3a36 6199 u8 reserved_at_20[0x10];
e281682b
SM		 6200 u8 op_mod[0x10];
6201
b4ff3a36 6202 u8 reserved_at_40[0xc0];
e281682b
SM		 6203
6204 struct mlx5_ifc_tisc_bits ctx;
6205};
6206
6207struct mlx5_ifc_create_tir_out_bits {
6208 u8 status[0x8];
b4ff3a36 6209 u8 reserved_at_8[0x18];
e281682b
SM		 6210
6211 u8 syndrome[0x20];
6212
b4ff3a36 6213 u8 reserved_at_40[0x8];
e281682b
SM		 6214 u8 tirn[0x18];
6215
b4ff3a36 6216 u8 reserved_at_60[0x20];
e281682b
SM		 6217};
6218
6219struct mlx5_ifc_create_tir_in_bits {
6220 u8 opcode[0x10];
b4ff3a36 6221 u8 reserved_at_10[0x10];
e281682b 6222
b4ff3a36 6223 u8 reserved_at_20[0x10];
e281682b
SM		 6224 u8 op_mod[0x10];
6225
b4ff3a36 6226 u8 reserved_at_40[0xc0];
e281682b
SM		 6227
6228 struct mlx5_ifc_tirc_bits ctx;
6229};
6230
6231struct mlx5_ifc_create_srq_out_bits {
6232 u8 status[0x8];
b4ff3a36 6233 u8 reserved_at_8[0x18];
e281682b
SM		 6234
6235 u8 syndrome[0x20];
6236
b4ff3a36 6237 u8 reserved_at_40[0x8];
e281682b
SM		 6238 u8 srqn[0x18];
6239
b4ff3a36 6240 u8 reserved_at_60[0x20];
e281682b
SM		 6241};
6242
6243struct mlx5_ifc_create_srq_in_bits {
6244 u8 opcode[0x10];
b4ff3a36 6245 u8 reserved_at_10[0x10];
e281682b 6246
b4ff3a36 6247 u8 reserved_at_20[0x10];
e281682b
SM		 6248 u8 op_mod[0x10];
6249
b4ff3a36 6250 u8 reserved_at_40[0x40];
e281682b
SM		 6251
6252 struct mlx5_ifc_srqc_bits srq_context_entry;
6253
b4ff3a36 6254 u8 reserved_at_280[0x600];
e281682b
SM		 6255
6256 u8 pas[0][0x40];
6257};
6258
6259struct mlx5_ifc_create_sq_out_bits {
6260 u8 status[0x8];
b4ff3a36 6261 u8 reserved_at_8[0x18];
e281682b
SM		 6262
6263 u8 syndrome[0x20];
6264
b4ff3a36 6265 u8 reserved_at_40[0x8];
e281682b
SM		 6266 u8 sqn[0x18];
6267
b4ff3a36 6268 u8 reserved_at_60[0x20];
e281682b
SM		 6269};
6270
6271struct mlx5_ifc_create_sq_in_bits {
6272 u8 opcode[0x10];
b4ff3a36 6273 u8 reserved_at_10[0x10];
e281682b 6274
b4ff3a36 6275 u8 reserved_at_20[0x10];
e281682b
SM		 6276 u8 op_mod[0x10];
6277
b4ff3a36 6278 u8 reserved_at_40[0xc0];
e281682b
SM		 6279
6280 struct mlx5_ifc_sqc_bits ctx;
6281};
6282
813f8540
MHY		 6283struct mlx5_ifc_create_scheduling_element_out_bits {
6284 u8 status[0x8];
6285 u8 reserved_at_8[0x18];
6286
6287 u8 syndrome[0x20];
6288
6289 u8 reserved_at_40[0x40];
6290
6291 u8 scheduling_element_id[0x20];
6292
6293 u8 reserved_at_a0[0x160];
6294};
6295
6296struct mlx5_ifc_create_scheduling_element_in_bits {
6297 u8 opcode[0x10];
6298 u8 reserved_at_10[0x10];
6299
6300 u8 reserved_at_20[0x10];
6301 u8 op_mod[0x10];
6302
6303 u8 scheduling_hierarchy[0x8];
6304 u8 reserved_at_48[0x18];
6305
6306 u8 reserved_at_60[0xa0];
6307
6308 struct mlx5_ifc_scheduling_context_bits scheduling_context;
6309
6310 u8 reserved_at_300[0x100];
6311};
6312
e281682b
SM		 6313struct mlx5_ifc_create_rqt_out_bits {
6314 u8 status[0x8];
b4ff3a36 6315 u8 reserved_at_8[0x18];
e281682b
SM		 6316
6317 u8 syndrome[0x20];
6318
b4ff3a36 6319 u8 reserved_at_40[0x8];
e281682b
SM		 6320 u8 rqtn[0x18];
6321
b4ff3a36 6322 u8 reserved_at_60[0x20];
e281682b
SM		 6323};
6324
6325struct mlx5_ifc_create_rqt_in_bits {
6326 u8 opcode[0x10];
b4ff3a36 6327 u8 reserved_at_10[0x10];
e281682b 6328
b4ff3a36 6329 u8 reserved_at_20[0x10];
e281682b
SM		 6330 u8 op_mod[0x10];
6331
b4ff3a36 6332 u8 reserved_at_40[0xc0];
e281682b
SM		 6333
6334 struct mlx5_ifc_rqtc_bits rqt_context;
6335};
6336
6337struct mlx5_ifc_create_rq_out_bits {
6338 u8 status[0x8];
b4ff3a36 6339 u8 reserved_at_8[0x18];
e281682b
SM		 6340
6341 u8 syndrome[0x20];
6342
b4ff3a36 6343 u8 reserved_at_40[0x8];
e281682b
SM		 6344 u8 rqn[0x18];
6345
b4ff3a36 6346 u8 reserved_at_60[0x20];
e281682b
SM		 6347};
6348
6349struct mlx5_ifc_create_rq_in_bits {
6350 u8 opcode[0x10];
b4ff3a36 6351 u8 reserved_at_10[0x10];
e281682b 6352
b4ff3a36 6353 u8 reserved_at_20[0x10];
e281682b
SM		 6354 u8 op_mod[0x10];
6355
b4ff3a36 6356 u8 reserved_at_40[0xc0];
e281682b
SM		 6357
6358 struct mlx5_ifc_rqc_bits ctx;
6359};
6360
6361struct mlx5_ifc_create_rmp_out_bits {
6362 u8 status[0x8];
b4ff3a36 6363 u8 reserved_at_8[0x18];
e281682b
SM		 6364
6365 u8 syndrome[0x20];
6366
b4ff3a36 6367 u8 reserved_at_40[0x8];
e281682b
SM		 6368 u8 rmpn[0x18];
6369
b4ff3a36 6370 u8 reserved_at_60[0x20];
e281682b
SM		 6371};
6372
6373struct mlx5_ifc_create_rmp_in_bits {
6374 u8 opcode[0x10];
b4ff3a36 6375 u8 reserved_at_10[0x10];
e281682b 6376
b4ff3a36 6377 u8 reserved_at_20[0x10];
e281682b
SM		 6378 u8 op_mod[0x10];
6379
b4ff3a36 6380 u8 reserved_at_40[0xc0];
e281682b
SM		 6381
6382 struct mlx5_ifc_rmpc_bits ctx;
6383};
6384
6385struct mlx5_ifc_create_qp_out_bits {
6386 u8 status[0x8];
b4ff3a36 6387 u8 reserved_at_8[0x18];
e281682b
SM		 6388
6389 u8 syndrome[0x20];
6390
b4ff3a36 6391 u8 reserved_at_40[0x8];
e281682b
SM		 6392 u8 qpn[0x18];
6393
b4ff3a36 6394 u8 reserved_at_60[0x20];
e281682b
SM		 6395};
6396
6397struct mlx5_ifc_create_qp_in_bits {
6398 u8 opcode[0x10];
b4ff3a36 6399 u8 reserved_at_10[0x10];
e281682b 6400
b4ff3a36 6401 u8 reserved_at_20[0x10];
e281682b
SM		 6402 u8 op_mod[0x10];
6403
b4ff3a36 6404 u8 reserved_at_40[0x40];
e281682b
SM		 6405
6406 u8 opt_param_mask[0x20];
6407
b4ff3a36 6408 u8 reserved_at_a0[0x20];
e281682b
SM		 6409
6410 struct mlx5_ifc_qpc_bits qpc;
6411
b4ff3a36 6412 u8 reserved_at_800[0x80];
e281682b
SM		 6413
6414 u8 pas[0][0x40];
6415};
6416
6417struct mlx5_ifc_create_psv_out_bits {
6418 u8 status[0x8];
b4ff3a36 6419 u8 reserved_at_8[0x18];
e281682b
SM		 6420
6421 u8 syndrome[0x20];
6422
b4ff3a36 6423 u8 reserved_at_40[0x40];
e281682b 6424
b4ff3a36 6425 u8 reserved_at_80[0x8];
e281682b
SM		 6426 u8 psv0_index[0x18];
6427
b4ff3a36 6428 u8 reserved_at_a0[0x8];
e281682b
SM		 6429 u8 psv1_index[0x18];
6430
b4ff3a36 6431 u8 reserved_at_c0[0x8];
e281682b
SM		 6432 u8 psv2_index[0x18];
6433
b4ff3a36 6434 u8 reserved_at_e0[0x8];
e281682b
SM		 6435 u8 psv3_index[0x18];
6436};
6437
6438struct mlx5_ifc_create_psv_in_bits {
6439 u8 opcode[0x10];
b4ff3a36 6440 u8 reserved_at_10[0x10];
e281682b 6441
b4ff3a36 6442 u8 reserved_at_20[0x10];
e281682b
SM		 6443 u8 op_mod[0x10];
6444
6445 u8 num_psv[0x4];
b4ff3a36 6446 u8 reserved_at_44[0x4];
e281682b
SM		 6447 u8 pd[0x18];
6448
b4ff3a36 6449 u8 reserved_at_60[0x20];
e281682b
SM		 6450};
6451
6452struct mlx5_ifc_create_mkey_out_bits {
6453 u8 status[0x8];
b4ff3a36 6454 u8 reserved_at_8[0x18];
e281682b
SM		 6455
6456 u8 syndrome[0x20];
6457
b4ff3a36 6458 u8 reserved_at_40[0x8];
e281682b
SM		 6459 u8 mkey_index[0x18];
6460
b4ff3a36 6461 u8 reserved_at_60[0x20];
e281682b
SM		 6462};
6463
6464struct mlx5_ifc_create_mkey_in_bits {
6465 u8 opcode[0x10];
b4ff3a36 6466 u8 reserved_at_10[0x10];
e281682b 6467
b4ff3a36 6468 u8 reserved_at_20[0x10];
e281682b
SM		 6469 u8 op_mod[0x10];
6470
b4ff3a36 6471 u8 reserved_at_40[0x20];
e281682b
SM		 6472
6473 u8 pg_access[0x1];
b4ff3a36 6474 u8 reserved_at_61[0x1f];
e281682b
SM		 6475
6476 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6477
b4ff3a36 6478 u8 reserved_at_280[0x80];
e281682b
SM		 6479
6480 u8 translations_octword_actual_size[0x20];
6481
b4ff3a36 6482 u8 reserved_at_320[0x560];
e281682b
SM		 6483
6484 u8 klm_pas_mtt[0][0x20];
6485};
6486
6487struct mlx5_ifc_create_flow_table_out_bits {
6488 u8 status[0x8];
b4ff3a36 6489 u8 reserved_at_8[0x18];
e281682b
SM		 6490
6491 u8 syndrome[0x20];
6492
b4ff3a36 6493 u8 reserved_at_40[0x8];
e281682b
SM		 6494 u8 table_id[0x18];
6495
b4ff3a36 6496 u8 reserved_at_60[0x20];
e281682b
SM		 6497};
6498
6499struct mlx5_ifc_create_flow_table_in_bits {
6500 u8 opcode[0x10];
b4ff3a36 6501 u8 reserved_at_10[0x10];
e281682b 6502
b4ff3a36 6503 u8 reserved_at_20[0x10];
e281682b
SM		 6504 u8 op_mod[0x10];
6505
7d5e1423
SM		 6506 u8 other_vport[0x1];
6507 u8 reserved_at_41[0xf];
6508 u8 vport_number[0x10];
6509
6510 u8 reserved_at_60[0x20];
e281682b
SM		 6511
6512 u8 table_type[0x8];
b4ff3a36 6513 u8 reserved_at_88[0x18];
e281682b 6514
b4ff3a36 6515 u8 reserved_at_a0[0x20];
e281682b 6516
7adbde20
HHZ		 6517 u8 encap_en[0x1];
6518 u8 decap_en[0x1];
6519 u8 reserved_at_c2[0x2];
34a40e68 6520 u8 table_miss_mode[0x4];
e281682b 6521 u8 level[0x8];
b4ff3a36 6522 u8 reserved_at_d0[0x8];
e281682b
SM		 6523 u8 log_size[0x8];
6524
b4ff3a36 6525 u8 reserved_at_e0[0x8];
34a40e68
MG		 6526 u8 table_miss_id[0x18];
6527
84df61eb
AH		 6528 u8 reserved_at_100[0x8];
6529 u8 lag_master_next_table_id[0x18];
6530
6531 u8 reserved_at_120[0x80];
e281682b
SM		 6532};
6533
6534struct mlx5_ifc_create_flow_group_out_bits {
6535 u8 status[0x8];
b4ff3a36 6536 u8 reserved_at_8[0x18];
e281682b
SM		 6537
6538 u8 syndrome[0x20];
6539
b4ff3a36 6540 u8 reserved_at_40[0x8];
e281682b
SM		 6541 u8 group_id[0x18];
6542
b4ff3a36 6543 u8 reserved_at_60[0x20];
e281682b
SM		 6544};
6545
6546enum {
6547 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
6548 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
6549 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
6550};
6551
6552struct mlx5_ifc_create_flow_group_in_bits {
6553 u8 opcode[0x10];
b4ff3a36 6554 u8 reserved_at_10[0x10];
e281682b 6555
b4ff3a36 6556 u8 reserved_at_20[0x10];
e281682b
SM		 6557 u8 op_mod[0x10];
6558
7d5e1423
SM		 6559 u8 other_vport[0x1];
6560 u8 reserved_at_41[0xf];
6561 u8 vport_number[0x10];
6562
6563 u8 reserved_at_60[0x20];
e281682b
SM		 6564
6565 u8 table_type[0x8];
b4ff3a36 6566 u8 reserved_at_88[0x18];
e281682b 6567
b4ff3a36 6568 u8 reserved_at_a0[0x8];
e281682b
SM		 6569 u8 table_id[0x18];
6570
b4ff3a36 6571 u8 reserved_at_c0[0x20];
e281682b
SM		 6572
6573 u8 start_flow_index[0x20];
6574
b4ff3a36 6575 u8 reserved_at_100[0x20];
e281682b
SM		 6576
6577 u8 end_flow_index[0x20];
6578
b4ff3a36 6579 u8 reserved_at_140[0xa0];
e281682b 6580
b4ff3a36 6581 u8 reserved_at_1e0[0x18];
e281682b
SM		 6582 u8 match_criteria_enable[0x8];
6583
6584 struct mlx5_ifc_fte_match_param_bits match_criteria;
6585
b4ff3a36 6586 u8 reserved_at_1200[0xe00];
e281682b
SM		 6587};
6588
6589struct mlx5_ifc_create_eq_out_bits {
6590 u8 status[0x8];
b4ff3a36 6591 u8 reserved_at_8[0x18];
e281682b
SM		 6592
6593 u8 syndrome[0x20];
6594
b4ff3a36 6595 u8 reserved_at_40[0x18];
e281682b
SM		 6596 u8 eq_number[0x8];
6597
b4ff3a36 6598 u8 reserved_at_60[0x20];
e281682b
SM		 6599};
6600
6601struct mlx5_ifc_create_eq_in_bits {
6602 u8 opcode[0x10];
b4ff3a36 6603 u8 reserved_at_10[0x10];
e281682b 6604
b4ff3a36 6605 u8 reserved_at_20[0x10];
e281682b
SM		 6606 u8 op_mod[0x10];
6607
b4ff3a36 6608 u8 reserved_at_40[0x40];
e281682b
SM		 6609
6610 struct mlx5_ifc_eqc_bits eq_context_entry;
6611
b4ff3a36 6612 u8 reserved_at_280[0x40];
e281682b
SM		 6613
6614 u8 event_bitmask[0x40];
6615
b4ff3a36 6616 u8 reserved_at_300[0x580];
e281682b
SM		 6617
6618 u8 pas[0][0x40];
6619};
6620
6621struct mlx5_ifc_create_dct_out_bits {
6622 u8 status[0x8];
b4ff3a36 6623 u8 reserved_at_8[0x18];
e281682b
SM		 6624
6625 u8 syndrome[0x20];
6626
b4ff3a36 6627 u8 reserved_at_40[0x8];
e281682b
SM		 6628 u8 dctn[0x18];
6629
b4ff3a36 6630 u8 reserved_at_60[0x20];
e281682b
SM		 6631};
6632
6633struct mlx5_ifc_create_dct_in_bits {
6634 u8 opcode[0x10];
b4ff3a36 6635 u8 reserved_at_10[0x10];
e281682b 6636
b4ff3a36 6637 u8 reserved_at_20[0x10];
e281682b
SM		 6638 u8 op_mod[0x10];
6639
b4ff3a36 6640 u8 reserved_at_40[0x40];
e281682b
SM		 6641
6642 struct mlx5_ifc_dctc_bits dct_context_entry;
6643
b4ff3a36 6644 u8 reserved_at_280[0x180];
e281682b
SM		 6645};
6646
6647struct mlx5_ifc_create_cq_out_bits {
6648 u8 status[0x8];
b4ff3a36 6649 u8 reserved_at_8[0x18];
e281682b
SM		 6650
6651 u8 syndrome[0x20];
6652
b4ff3a36 6653 u8 reserved_at_40[0x8];
e281682b
SM		 6654 u8 cqn[0x18];
6655
b4ff3a36 6656 u8 reserved_at_60[0x20];
e281682b
SM		 6657};
6658
6659struct mlx5_ifc_create_cq_in_bits {
6660 u8 opcode[0x10];
b4ff3a36 6661 u8 reserved_at_10[0x10];
e281682b 6662
b4ff3a36 6663 u8 reserved_at_20[0x10];
e281682b
SM		 6664 u8 op_mod[0x10];
6665
b4ff3a36 6666 u8 reserved_at_40[0x40];
e281682b
SM		 6667
6668 struct mlx5_ifc_cqc_bits cq_context;
6669
b4ff3a36 6670 u8 reserved_at_280[0x600];
e281682b
SM		 6671
6672 u8 pas[0][0x40];
6673};
6674
6675struct mlx5_ifc_config_int_moderation_out_bits {
6676 u8 status[0x8];
b4ff3a36 6677 u8 reserved_at_8[0x18];
e281682b
SM		 6678
6679 u8 syndrome[0x20];
6680
b4ff3a36 6681 u8 reserved_at_40[0x4];
e281682b
SM		 6682 u8 min_delay[0xc];
6683 u8 int_vector[0x10];
6684
b4ff3a36 6685 u8 reserved_at_60[0x20];
e281682b
SM		 6686};
6687
6688enum {
6689 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
6690 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
6691};
6692
6693struct mlx5_ifc_config_int_moderation_in_bits {
6694 u8 opcode[0x10];
b4ff3a36 6695 u8 reserved_at_10[0x10];
e281682b 6696
b4ff3a36 6697 u8 reserved_at_20[0x10];
e281682b
SM		 6698 u8 op_mod[0x10];
6699
b4ff3a36 6700 u8 reserved_at_40[0x4];
e281682b
SM		 6701 u8 min_delay[0xc];
6702 u8 int_vector[0x10];
6703
b4ff3a36 6704 u8 reserved_at_60[0x20];
e281682b
SM		 6705};
6706
6707struct mlx5_ifc_attach_to_mcg_out_bits {
6708 u8 status[0x8];
b4ff3a36 6709 u8 reserved_at_8[0x18];
e281682b
SM		 6710
6711 u8 syndrome[0x20];
6712
b4ff3a36 6713 u8 reserved_at_40[0x40];
e281682b
SM		 6714};
6715
6716struct mlx5_ifc_attach_to_mcg_in_bits {
6717 u8 opcode[0x10];
b4ff3a36 6718 u8 reserved_at_10[0x10];
e281682b 6719
b4ff3a36 6720 u8 reserved_at_20[0x10];
e281682b
SM		 6721 u8 op_mod[0x10];
6722
b4ff3a36 6723 u8 reserved_at_40[0x8];
e281682b
SM		 6724 u8 qpn[0x18];
6725
b4ff3a36 6726 u8 reserved_at_60[0x20];
e281682b
SM		 6727
6728 u8 multicast_gid[16][0x8];
6729};
6730
7486216b
SM		 6731struct mlx5_ifc_arm_xrq_out_bits {
6732 u8 status[0x8];
6733 u8 reserved_at_8[0x18];
6734
6735 u8 syndrome[0x20];
6736
6737 u8 reserved_at_40[0x40];
6738};
6739
6740struct mlx5_ifc_arm_xrq_in_bits {
6741 u8 opcode[0x10];
6742 u8 reserved_at_10[0x10];
6743
6744 u8 reserved_at_20[0x10];
6745 u8 op_mod[0x10];
6746
6747 u8 reserved_at_40[0x8];
6748 u8 xrqn[0x18];
6749
6750 u8 reserved_at_60[0x10];
6751 u8 lwm[0x10];
6752};
6753
e281682b
SM		 6754struct mlx5_ifc_arm_xrc_srq_out_bits {
6755 u8 status[0x8];
b4ff3a36 6756 u8 reserved_at_8[0x18];
e281682b
SM		 6757
6758 u8 syndrome[0x20];
6759
b4ff3a36 6760 u8 reserved_at_40[0x40];
e281682b
SM		 6761};
6762
6763enum {
6764 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
6765};
6766
6767struct mlx5_ifc_arm_xrc_srq_in_bits {
6768 u8 opcode[0x10];
b4ff3a36 6769 u8 reserved_at_10[0x10];
e281682b 6770
b4ff3a36 6771 u8 reserved_at_20[0x10];
e281682b
SM		 6772 u8 op_mod[0x10];
6773
b4ff3a36 6774 u8 reserved_at_40[0x8];
e281682b
SM		 6775 u8 xrc_srqn[0x18];
6776
b4ff3a36 6777 u8 reserved_at_60[0x10];
e281682b
SM		 6778 u8 lwm[0x10];
6779};
6780
6781struct mlx5_ifc_arm_rq_out_bits {
6782 u8 status[0x8];
b4ff3a36 6783 u8 reserved_at_8[0x18];
e281682b
SM		 6784
6785 u8 syndrome[0x20];
6786
b4ff3a36 6787 u8 reserved_at_40[0x40];
e281682b
SM		 6788};
6789
6790enum {
7486216b
SM		 6791 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
6792 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
e281682b
SM		 6793};
6794
6795struct mlx5_ifc_arm_rq_in_bits {
6796 u8 opcode[0x10];
b4ff3a36 6797 u8 reserved_at_10[0x10];
e281682b 6798
b4ff3a36 6799 u8 reserved_at_20[0x10];
e281682b
SM		 6800 u8 op_mod[0x10];
6801
b4ff3a36 6802 u8 reserved_at_40[0x8];
e281682b
SM		 6803 u8 srq_number[0x18];
6804
b4ff3a36 6805 u8 reserved_at_60[0x10];
e281682b
SM		 6806 u8 lwm[0x10];
6807};
6808
6809struct mlx5_ifc_arm_dct_out_bits {
6810 u8 status[0x8];
b4ff3a36 6811 u8 reserved_at_8[0x18];
e281682b
SM		 6812
6813 u8 syndrome[0x20];
6814
b4ff3a36 6815 u8 reserved_at_40[0x40];
e281682b
SM		 6816};
6817
6818struct mlx5_ifc_arm_dct_in_bits {
6819 u8 opcode[0x10];
b4ff3a36 6820 u8 reserved_at_10[0x10];
e281682b 6821
b4ff3a36 6822 u8 reserved_at_20[0x10];
e281682b
SM		 6823 u8 op_mod[0x10];
6824
b4ff3a36 6825 u8 reserved_at_40[0x8];
e281682b
SM		 6826 u8 dct_number[0x18];
6827
b4ff3a36 6828 u8 reserved_at_60[0x20];
e281682b
SM		 6829};
6830
6831struct mlx5_ifc_alloc_xrcd_out_bits {
6832 u8 status[0x8];
b4ff3a36 6833 u8 reserved_at_8[0x18];
e281682b
SM		 6834
6835 u8 syndrome[0x20];
6836
b4ff3a36 6837 u8 reserved_at_40[0x8];
e281682b
SM		 6838 u8 xrcd[0x18];
6839
b4ff3a36 6840 u8 reserved_at_60[0x20];
e281682b
SM		 6841};
6842
6843struct mlx5_ifc_alloc_xrcd_in_bits {
6844 u8 opcode[0x10];
b4ff3a36 6845 u8 reserved_at_10[0x10];
e281682b 6846
b4ff3a36 6847 u8 reserved_at_20[0x10];
e281682b
SM		 6848 u8 op_mod[0x10];
6849
b4ff3a36 6850 u8 reserved_at_40[0x40];
e281682b
SM		 6851};
6852
6853struct mlx5_ifc_alloc_uar_out_bits {
6854 u8 status[0x8];
b4ff3a36 6855 u8 reserved_at_8[0x18];
e281682b
SM		 6856
6857 u8 syndrome[0x20];
6858
b4ff3a36 6859 u8 reserved_at_40[0x8];
e281682b
SM		 6860 u8 uar[0x18];
6861
b4ff3a36 6862 u8 reserved_at_60[0x20];
e281682b
SM		 6863};
6864
6865struct mlx5_ifc_alloc_uar_in_bits {
6866 u8 opcode[0x10];
b4ff3a36 6867 u8 reserved_at_10[0x10];
e281682b 6868
b4ff3a36 6869 u8 reserved_at_20[0x10];
e281682b
SM		 6870 u8 op_mod[0x10];
6871
b4ff3a36 6872 u8 reserved_at_40[0x40];
e281682b
SM		 6873};
6874
6875struct mlx5_ifc_alloc_transport_domain_out_bits {
6876 u8 status[0x8];
b4ff3a36 6877 u8 reserved_at_8[0x18];
e281682b
SM		 6878
6879 u8 syndrome[0x20];
6880
b4ff3a36 6881 u8 reserved_at_40[0x8];
e281682b
SM		 6882 u8 transport_domain[0x18];
6883
b4ff3a36 6884 u8 reserved_at_60[0x20];
e281682b
SM		 6885};
6886
6887struct mlx5_ifc_alloc_transport_domain_in_bits {
6888 u8 opcode[0x10];
b4ff3a36 6889 u8 reserved_at_10[0x10];
e281682b 6890
b4ff3a36 6891 u8 reserved_at_20[0x10];
e281682b
SM		 6892 u8 op_mod[0x10];
6893
b4ff3a36 6894 u8 reserved_at_40[0x40];
e281682b
SM		 6895};
6896
6897struct mlx5_ifc_alloc_q_counter_out_bits {
6898 u8 status[0x8];
b4ff3a36 6899 u8 reserved_at_8[0x18];
e281682b
SM		 6900
6901 u8 syndrome[0x20];
6902
b4ff3a36 6903 u8 reserved_at_40[0x18];
e281682b
SM		 6904 u8 counter_set_id[0x8];
6905
b4ff3a36 6906 u8 reserved_at_60[0x20];
e281682b
SM		 6907};
6908
6909struct mlx5_ifc_alloc_q_counter_in_bits {
6910 u8 opcode[0x10];
b4ff3a36 6911 u8 reserved_at_10[0x10];
e281682b 6912
b4ff3a36 6913 u8 reserved_at_20[0x10];
e281682b
SM		 6914 u8 op_mod[0x10];
6915
b4ff3a36 6916 u8 reserved_at_40[0x40];
e281682b
SM		 6917};
6918
6919struct mlx5_ifc_alloc_pd_out_bits {
6920 u8 status[0x8];
b4ff3a36 6921 u8 reserved_at_8[0x18];
e281682b
SM		 6922
6923 u8 syndrome[0x20];
6924
b4ff3a36 6925 u8 reserved_at_40[0x8];
e281682b
SM		 6926 u8 pd[0x18];
6927
b4ff3a36 6928 u8 reserved_at_60[0x20];
e281682b
SM		 6929};
6930
6931struct mlx5_ifc_alloc_pd_in_bits {
9dc0b289
AV		 6932 u8 opcode[0x10];
6933 u8 reserved_at_10[0x10];
6934
6935 u8 reserved_at_20[0x10];
6936 u8 op_mod[0x10];
6937
6938 u8 reserved_at_40[0x40];
6939};
6940
6941struct mlx5_ifc_alloc_flow_counter_out_bits {
6942 u8 status[0x8];
6943 u8 reserved_at_8[0x18];
6944
6945 u8 syndrome[0x20];
6946
6947 u8 reserved_at_40[0x10];
6948 u8 flow_counter_id[0x10];
6949
6950 u8 reserved_at_60[0x20];
6951};
6952
6953struct mlx5_ifc_alloc_flow_counter_in_bits {
e281682b 6954 u8 opcode[0x10];
b4ff3a36 6955 u8 reserved_at_10[0x10];
e281682b 6956
b4ff3a36 6957 u8 reserved_at_20[0x10];
e281682b
SM		 6958 u8 op_mod[0x10];
6959
b4ff3a36 6960 u8 reserved_at_40[0x40];
e281682b
SM		 6961};
6962
6963struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
6964 u8 status[0x8];
b4ff3a36 6965 u8 reserved_at_8[0x18];
e281682b
SM		 6966
6967 u8 syndrome[0x20];
6968
b4ff3a36 6969 u8 reserved_at_40[0x40];
e281682b
SM		 6970};
6971
6972struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
6973 u8 opcode[0x10];
b4ff3a36 6974 u8 reserved_at_10[0x10];
e281682b 6975
b4ff3a36 6976 u8 reserved_at_20[0x10];
e281682b
SM		 6977 u8 op_mod[0x10];
6978
b4ff3a36 6979 u8 reserved_at_40[0x20];
e281682b 6980
b4ff3a36 6981 u8 reserved_at_60[0x10];
e281682b
SM		 6982 u8 vxlan_udp_port[0x10];
6983};
6984
7486216b
SM		 6985struct mlx5_ifc_set_rate_limit_out_bits {
6986 u8 status[0x8];
6987 u8 reserved_at_8[0x18];
6988
6989 u8 syndrome[0x20];
6990
6991 u8 reserved_at_40[0x40];
6992};
6993
6994struct mlx5_ifc_set_rate_limit_in_bits {
6995 u8 opcode[0x10];
6996 u8 reserved_at_10[0x10];
6997
6998 u8 reserved_at_20[0x10];
6999 u8 op_mod[0x10];
7000
7001 u8 reserved_at_40[0x10];
7002 u8 rate_limit_index[0x10];
7003
7004 u8 reserved_at_60[0x20];
7005
7006 u8 rate_limit[0x20];
7007};
7008
e281682b
SM		 7009struct mlx5_ifc_access_register_out_bits {
7010 u8 status[0x8];
b4ff3a36 7011 u8 reserved_at_8[0x18];
e281682b
SM		 7012
7013 u8 syndrome[0x20];
7014
b4ff3a36 7015 u8 reserved_at_40[0x40];
e281682b
SM		 7016
7017 u8 register_data[0][0x20];
7018};
7019
7020enum {
7021 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
7022 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
7023};
7024
7025struct mlx5_ifc_access_register_in_bits {
7026 u8 opcode[0x10];
b4ff3a36 7027 u8 reserved_at_10[0x10];
e281682b 7028
b4ff3a36 7029 u8 reserved_at_20[0x10];
e281682b
SM		 7030 u8 op_mod[0x10];
7031
b4ff3a36 7032 u8 reserved_at_40[0x10];
e281682b
SM		 7033 u8 register_id[0x10];
7034
7035 u8 argument[0x20];
7036
7037 u8 register_data[0][0x20];
7038};
7039
7040struct mlx5_ifc_sltp_reg_bits {
7041 u8 status[0x4];
7042 u8 version[0x4];
7043 u8 local_port[0x8];
7044 u8 pnat[0x2];
b4ff3a36 7045 u8 reserved_at_12[0x2];
e281682b 7046 u8 lane[0x4];
b4ff3a36 7047 u8 reserved_at_18[0x8];
e281682b 7048
b4ff3a36 7049 u8 reserved_at_20[0x20];
e281682b 7050
b4ff3a36 7051 u8 reserved_at_40[0x7];
e281682b
SM		 7052 u8 polarity[0x1];
7053 u8 ob_tap0[0x8];
7054 u8 ob_tap1[0x8];
7055 u8 ob_tap2[0x8];
7056
b4ff3a36 7057 u8 reserved_at_60[0xc];
e281682b
SM		 7058 u8 ob_preemp_mode[0x4];
7059 u8 ob_reg[0x8];
7060 u8 ob_bias[0x8];
7061
b4ff3a36 7062 u8 reserved_at_80[0x20];
e281682b
SM		 7063};
7064
7065struct mlx5_ifc_slrg_reg_bits {
7066 u8 status[0x4];
7067 u8 version[0x4];
7068 u8 local_port[0x8];
7069 u8 pnat[0x2];
b4ff3a36 7070 u8 reserved_at_12[0x2];
e281682b 7071 u8 lane[0x4];
b4ff3a36 7072 u8 reserved_at_18[0x8];
e281682b
SM		 7073
7074 u8 time_to_link_up[0x10];
b4ff3a36 7075 u8 reserved_at_30[0xc];
e281682b
SM		 7076 u8 grade_lane_speed[0x4];
7077
7078 u8 grade_version[0x8];
7079 u8 grade[0x18];
7080
b4ff3a36 7081 u8 reserved_at_60[0x4];
e281682b
SM		 7082 u8 height_grade_type[0x4];
7083 u8 height_grade[0x18];
7084
7085 u8 height_dz[0x10];
7086 u8 height_dv[0x10];
7087
b4ff3a36 7088 u8 reserved_at_a0[0x10];
e281682b
SM		 7089 u8 height_sigma[0x10];
7090
b4ff3a36 7091 u8 reserved_at_c0[0x20];
e281682b 7092
b4ff3a36 7093 u8 reserved_at_e0[0x4];
e281682b
SM		 7094 u8 phase_grade_type[0x4];
7095 u8 phase_grade[0x18];
7096
b4ff3a36 7097 u8 reserved_at_100[0x8];
e281682b 7098 u8 phase_eo_pos[0x8];
b4ff3a36 7099 u8 reserved_at_110[0x8];
e281682b
SM		 7100 u8 phase_eo_neg[0x8];
7101
7102 u8 ffe_set_tested[0x10];
7103 u8 test_errors_per_lane[0x10];
7104};
7105
7106struct mlx5_ifc_pvlc_reg_bits {
b4ff3a36 7107 u8 reserved_at_0[0x8];
e281682b 7108 u8 local_port[0x8];
b4ff3a36 7109 u8 reserved_at_10[0x10];
e281682b 7110
b4ff3a36 7111 u8 reserved_at_20[0x1c];
e281682b
SM		 7112 u8 vl_hw_cap[0x4];
7113
b4ff3a36 7114 u8 reserved_at_40[0x1c];
e281682b
SM		 7115 u8 vl_admin[0x4];
7116
b4ff3a36 7117 u8 reserved_at_60[0x1c];
e281682b
SM		 7118 u8 vl_operational[0x4];
7119};
7120
7121struct mlx5_ifc_pude_reg_bits {
7122 u8 swid[0x8];
7123 u8 local_port[0x8];
b4ff3a36 7124 u8 reserved_at_10[0x4];
e281682b 7125 u8 admin_status[0x4];
b4ff3a36 7126 u8 reserved_at_18[0x4];
e281682b
SM		 7127 u8 oper_status[0x4];
7128
b4ff3a36 7129 u8 reserved_at_20[0x60];
e281682b
SM		 7130};
7131
7132struct mlx5_ifc_ptys_reg_bits {
e7e31ca4 7133 u8 reserved_at_0[0x1];
7486216b 7134 u8 an_disable_admin[0x1];
e7e31ca4
BW		 7135 u8 an_disable_cap[0x1];
7136 u8 reserved_at_3[0x5];
e281682b 7137 u8 local_port[0x8];
b4ff3a36 7138 u8 reserved_at_10[0xd];
e281682b
SM		 7139 u8 proto_mask[0x3];
7140
7486216b
SM		 7141 u8 an_status[0x4];
7142 u8 reserved_at_24[0x3c];
e281682b
SM		 7143
7144 u8 eth_proto_capability[0x20];
7145
7146 u8 ib_link_width_capability[0x10];
7147 u8 ib_proto_capability[0x10];
7148
b4ff3a36 7149 u8 reserved_at_a0[0x20];
e281682b
SM		 7150
7151 u8 eth_proto_admin[0x20];
7152
7153 u8 ib_link_width_admin[0x10];
7154 u8 ib_proto_admin[0x10];
7155
b4ff3a36 7156 u8 reserved_at_100[0x20];
e281682b
SM		 7157
7158 u8 eth_proto_oper[0x20];
7159
7160 u8 ib_link_width_oper[0x10];
7161 u8 ib_proto_oper[0x10];
7162
b4ff3a36 7163 u8 reserved_at_160[0x20];
e281682b
SM		 7164
7165 u8 eth_proto_lp_advertise[0x20];
7166
b4ff3a36 7167 u8 reserved_at_1a0[0x60];
e281682b
SM		 7168};
7169
7d5e1423
SM		 7170struct mlx5_ifc_mlcr_reg_bits {
7171 u8 reserved_at_0[0x8];
7172 u8 local_port[0x8];
7173 u8 reserved_at_10[0x20];
7174
7175 u8 beacon_duration[0x10];
7176 u8 reserved_at_40[0x10];
7177
7178 u8 beacon_remain[0x10];
7179};
7180
e281682b 7181struct mlx5_ifc_ptas_reg_bits {
b4ff3a36 7182 u8 reserved_at_0[0x20];
e281682b
SM		 7183
7184 u8 algorithm_options[0x10];
b4ff3a36 7185 u8 reserved_at_30[0x4];
e281682b
SM		 7186 u8 repetitions_mode[0x4];
7187 u8 num_of_repetitions[0x8];
7188
7189 u8 grade_version[0x8];
7190 u8 height_grade_type[0x4];
7191 u8 phase_grade_type[0x4];
7192 u8 height_grade_weight[0x8];
7193 u8 phase_grade_weight[0x8];
7194
7195 u8 gisim_measure_bits[0x10];
7196 u8 adaptive_tap_measure_bits[0x10];
7197
7198 u8 ber_bath_high_error_threshold[0x10];
7199 u8 ber_bath_mid_error_threshold[0x10];
7200
7201 u8 ber_bath_low_error_threshold[0x10];
7202 u8 one_ratio_high_threshold[0x10];
7203
7204 u8 one_ratio_high_mid_threshold[0x10];
7205 u8 one_ratio_low_mid_threshold[0x10];
7206
7207 u8 one_ratio_low_threshold[0x10];
7208 u8 ndeo_error_threshold[0x10];
7209
7210 u8 mixer_offset_step_size[0x10];
b4ff3a36 7211 u8 reserved_at_110[0x8];
e281682b
SM		 7212 u8 mix90_phase_for_voltage_bath[0x8];
7213
7214 u8 mixer_offset_start[0x10];
7215 u8 mixer_offset_end[0x10];
7216
b4ff3a36 7217 u8 reserved_at_140[0x15];
e281682b
SM		 7218 u8 ber_test_time[0xb];
7219};
7220
7221struct mlx5_ifc_pspa_reg_bits {
7222 u8 swid[0x8];
7223 u8 local_port[0x8];
7224 u8 sub_port[0x8];
b4ff3a36 7225 u8 reserved_at_18[0x8];
e281682b 7226
b4ff3a36 7227 u8 reserved_at_20[0x20];
e281682b
SM		 7228};
7229
7230struct mlx5_ifc_pqdr_reg_bits {
b4ff3a36 7231 u8 reserved_at_0[0x8];
e281682b 7232 u8 local_port[0x8];
b4ff3a36 7233 u8 reserved_at_10[0x5];
e281682b 7234 u8 prio[0x3];
b4ff3a36 7235 u8 reserved_at_18[0x6];
e281682b
SM		 7236 u8 mode[0x2];
7237
b4ff3a36 7238 u8 reserved_at_20[0x20];
e281682b 7239
b4ff3a36 7240 u8 reserved_at_40[0x10];
e281682b
SM		 7241 u8 min_threshold[0x10];
7242
b4ff3a36 7243 u8 reserved_at_60[0x10];
e281682b
SM		 7244 u8 max_threshold[0x10];
7245
b4ff3a36 7246 u8 reserved_at_80[0x10];
e281682b
SM		 7247 u8 mark_probability_denominator[0x10];
7248
b4ff3a36 7249 u8 reserved_at_a0[0x60];
e281682b
SM		 7250};
7251
7252struct mlx5_ifc_ppsc_reg_bits {
b4ff3a36 7253 u8 reserved_at_0[0x8];
e281682b 7254 u8 local_port[0x8];
b4ff3a36 7255 u8 reserved_at_10[0x10];
e281682b 7256
b4ff3a36 7257 u8 reserved_at_20[0x60];
e281682b 7258
b4ff3a36 7259 u8 reserved_at_80[0x1c];
e281682b
SM		 7260 u8 wrps_admin[0x4];
7261
b4ff3a36 7262 u8 reserved_at_a0[0x1c];
e281682b
SM		 7263 u8 wrps_status[0x4];
7264
b4ff3a36 7265 u8 reserved_at_c0[0x8];
e281682b 7266 u8 up_threshold[0x8];
b4ff3a36 7267 u8 reserved_at_d0[0x8];
e281682b
SM		 7268 u8 down_threshold[0x8];
7269
b4ff3a36 7270 u8 reserved_at_e0[0x20];
e281682b 7271
b4ff3a36 7272 u8 reserved_at_100[0x1c];
e281682b
SM		 7273 u8 srps_admin[0x4];
7274
b4ff3a36 7275 u8 reserved_at_120[0x1c];
e281682b
SM		 7276 u8 srps_status[0x4];
7277
b4ff3a36 7278 u8 reserved_at_140[0x40];
e281682b
SM		 7279};
7280
7281struct mlx5_ifc_pplr_reg_bits {
b4ff3a36 7282 u8 reserved_at_0[0x8];
e281682b 7283 u8 local_port[0x8];
b4ff3a36 7284 u8 reserved_at_10[0x10];
e281682b 7285
b4ff3a36 7286 u8 reserved_at_20[0x8];
e281682b 7287 u8 lb_cap[0x8];
b4ff3a36 7288 u8 reserved_at_30[0x8];
e281682b
SM		 7289 u8 lb_en[0x8];
7290};
7291
7292struct mlx5_ifc_pplm_reg_bits {
b4ff3a36 7293 u8 reserved_at_0[0x8];
e281682b 7294 u8 local_port[0x8];
b4ff3a36 7295 u8 reserved_at_10[0x10];
e281682b 7296
b4ff3a36 7297 u8 reserved_at_20[0x20];
e281682b
SM		 7298
7299 u8 port_profile_mode[0x8];
7300 u8 static_port_profile[0x8];
7301 u8 active_port_profile[0x8];
b4ff3a36 7302 u8 reserved_at_58[0x8];
e281682b
SM		 7303
7304 u8 retransmission_active[0x8];
7305 u8 fec_mode_active[0x18];
7306
b4ff3a36 7307 u8 reserved_at_80[0x20];
e281682b
SM		 7308};
7309
7310struct mlx5_ifc_ppcnt_reg_bits {
7311 u8 swid[0x8];
7312 u8 local_port[0x8];
7313 u8 pnat[0x2];
b4ff3a36 7314 u8 reserved_at_12[0x8];
e281682b
SM		 7315 u8 grp[0x6];
7316
7317 u8 clr[0x1];
b4ff3a36 7318 u8 reserved_at_21[0x1c];
e281682b
SM		 7319 u8 prio_tc[0x3];
7320
7321 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
7322};
7323
8ed1a630
GP		 7324struct mlx5_ifc_mpcnt_reg_bits {
7325 u8 reserved_at_0[0x8];
7326 u8 pcie_index[0x8];
7327 u8 reserved_at_10[0xa];
7328 u8 grp[0x6];
7329
7330 u8 clr[0x1];
7331 u8 reserved_at_21[0x1f];
7332
7333 union mlx5_ifc_pcie_cntrs_grp_data_layout_auto_bits counter_set;
7334};
7335
e281682b 7336struct mlx5_ifc_ppad_reg_bits {
b4ff3a36 7337 u8 reserved_at_0[0x3];
e281682b 7338 u8 single_mac[0x1];
b4ff3a36 7339 u8 reserved_at_4[0x4];
e281682b
SM		 7340 u8 local_port[0x8];
7341 u8 mac_47_32[0x10];
7342
7343 u8 mac_31_0[0x20];
7344
b4ff3a36 7345 u8 reserved_at_40[0x40];
e281682b
SM		 7346};
7347
7348struct mlx5_ifc_pmtu_reg_bits {
b4ff3a36 7349 u8 reserved_at_0[0x8];
e281682b 7350 u8 local_port[0x8];
b4ff3a36 7351 u8 reserved_at_10[0x10];
e281682b
SM		 7352
7353 u8 max_mtu[0x10];
b4ff3a36 7354 u8 reserved_at_30[0x10];
e281682b
SM		 7355
7356 u8 admin_mtu[0x10];
b4ff3a36 7357 u8 reserved_at_50[0x10];
e281682b
SM		 7358
7359 u8 oper_mtu[0x10];
b4ff3a36 7360 u8 reserved_at_70[0x10];
e281682b
SM		 7361};
7362
7363struct mlx5_ifc_pmpr_reg_bits {
b4ff3a36 7364 u8 reserved_at_0[0x8];
e281682b 7365 u8 module[0x8];
b4ff3a36 7366 u8 reserved_at_10[0x10];
e281682b 7367
b4ff3a36 7368 u8 reserved_at_20[0x18];
e281682b
SM		 7369 u8 attenuation_5g[0x8];
7370
b4ff3a36 7371 u8 reserved_at_40[0x18];
e281682b
SM		 7372 u8 attenuation_7g[0x8];
7373
b4ff3a36 7374 u8 reserved_at_60[0x18];
e281682b
SM		 7375 u8 attenuation_12g[0x8];
7376};
7377
7378struct mlx5_ifc_pmpe_reg_bits {
b4ff3a36 7379 u8 reserved_at_0[0x8];
e281682b 7380 u8 module[0x8];
b4ff3a36 7381 u8 reserved_at_10[0xc];
e281682b
SM		 7382 u8 module_status[0x4];
7383
b4ff3a36 7384 u8 reserved_at_20[0x60];
e281682b
SM		 7385};
7386
7387struct mlx5_ifc_pmpc_reg_bits {
7388 u8 module_state_updated[32][0x8];
7389};
7390
7391struct mlx5_ifc_pmlpn_reg_bits {
b4ff3a36 7392 u8 reserved_at_0[0x4];
e281682b
SM		 7393 u8 mlpn_status[0x4];
7394 u8 local_port[0x8];
b4ff3a36 7395 u8 reserved_at_10[0x10];
e281682b
SM		 7396
7397 u8 e[0x1];
b4ff3a36 7398 u8 reserved_at_21[0x1f];
e281682b
SM		 7399};
7400
7401struct mlx5_ifc_pmlp_reg_bits {
7402 u8 rxtx[0x1];
b4ff3a36 7403 u8 reserved_at_1[0x7];
e281682b 7404 u8 local_port[0x8];
b4ff3a36 7405 u8 reserved_at_10[0x8];
e281682b
SM		 7406 u8 width[0x8];
7407
7408 u8 lane0_module_mapping[0x20];
7409
7410 u8 lane1_module_mapping[0x20];
7411
7412 u8 lane2_module_mapping[0x20];
7413
7414 u8 lane3_module_mapping[0x20];
7415
b4ff3a36 7416 u8 reserved_at_a0[0x160];
e281682b
SM		 7417};
7418
7419struct mlx5_ifc_pmaos_reg_bits {
b4ff3a36 7420 u8 reserved_at_0[0x8];
e281682b 7421 u8 module[0x8];
b4ff3a36 7422 u8 reserved_at_10[0x4];
e281682b 7423 u8 admin_status[0x4];
b4ff3a36 7424 u8 reserved_at_18[0x4];
e281682b
SM		 7425 u8 oper_status[0x4];
7426
7427 u8 ase[0x1];
7428 u8 ee[0x1];
b4ff3a36 7429 u8 reserved_at_22[0x1c];
e281682b
SM		 7430 u8 e[0x2];
7431
b4ff3a36 7432 u8 reserved_at_40[0x40];
e281682b
SM		 7433};
7434
7435struct mlx5_ifc_plpc_reg_bits {
b4ff3a36 7436 u8 reserved_at_0[0x4];
e281682b 7437 u8 profile_id[0xc];
b4ff3a36 7438 u8 reserved_at_10[0x4];
e281682b 7439 u8 proto_mask[0x4];
b4ff3a36 7440 u8 reserved_at_18[0x8];
e281682b 7441
b4ff3a36 7442 u8 reserved_at_20[0x10];
e281682b
SM		 7443 u8 lane_speed[0x10];
7444
b4ff3a36 7445 u8 reserved_at_40[0x17];
e281682b
SM		 7446 u8 lpbf[0x1];
7447 u8 fec_mode_policy[0x8];
7448
7449 u8 retransmission_capability[0x8];
7450 u8 fec_mode_capability[0x18];
7451
7452 u8 retransmission_support_admin[0x8];
7453 u8 fec_mode_support_admin[0x18];
7454
7455 u8 retransmission_request_admin[0x8];
7456 u8 fec_mode_request_admin[0x18];
7457
b4ff3a36 7458 u8 reserved_at_c0[0x80];
e281682b
SM		 7459};
7460
7461struct mlx5_ifc_plib_reg_bits {
b4ff3a36 7462 u8 reserved_at_0[0x8];
e281682b 7463 u8 local_port[0x8];
b4ff3a36 7464 u8 reserved_at_10[0x8];
e281682b
SM		 7465 u8 ib_port[0x8];
7466
b4ff3a36 7467 u8 reserved_at_20[0x60];
e281682b
SM		 7468};
7469
7470struct mlx5_ifc_plbf_reg_bits {
b4ff3a36 7471 u8 reserved_at_0[0x8];
e281682b 7472 u8 local_port[0x8];
b4ff3a36 7473 u8 reserved_at_10[0xd];
e281682b
SM		 7474 u8 lbf_mode[0x3];
7475
b4ff3a36 7476 u8 reserved_at_20[0x20];
e281682b
SM		 7477};
7478
7479struct mlx5_ifc_pipg_reg_bits {
b4ff3a36 7480 u8 reserved_at_0[0x8];
e281682b 7481 u8 local_port[0x8];
b4ff3a36 7482 u8 reserved_at_10[0x10];
e281682b
SM		 7483
7484 u8 dic[0x1];
b4ff3a36 7485 u8 reserved_at_21[0x19];
e281682b 7486 u8 ipg[0x4];
b4ff3a36 7487 u8 reserved_at_3e[0x2];
e281682b
SM		 7488};
7489
7490struct mlx5_ifc_pifr_reg_bits {
b4ff3a36 7491 u8 reserved_at_0[0x8];
e281682b 7492 u8 local_port[0x8];
b4ff3a36 7493 u8 reserved_at_10[0x10];
e281682b 7494
b4ff3a36 7495 u8 reserved_at_20[0xe0];
e281682b
SM		 7496
7497 u8 port_filter[8][0x20];
7498
7499 u8 port_filter_update_en[8][0x20];
7500};
7501
7502struct mlx5_ifc_pfcc_reg_bits {
b4ff3a36 7503 u8 reserved_at_0[0x8];
e281682b 7504 u8 local_port[0x8];
b4ff3a36 7505 u8 reserved_at_10[0x10];
e281682b
SM		 7506
7507 u8 ppan[0x4];
b4ff3a36 7508 u8 reserved_at_24[0x4];
e281682b 7509 u8 prio_mask_tx[0x8];
b4ff3a36 7510 u8 reserved_at_30[0x8];
e281682b
SM		 7511 u8 prio_mask_rx[0x8];
7512
7513 u8 pptx[0x1];
7514 u8 aptx[0x1];
b4ff3a36 7515 u8 reserved_at_42[0x6];
e281682b 7516 u8 pfctx[0x8];
b4ff3a36 7517 u8 reserved_at_50[0x10];
e281682b
SM		 7518
7519 u8 pprx[0x1];
7520 u8 aprx[0x1];
b4ff3a36 7521 u8 reserved_at_62[0x6];
e281682b 7522 u8 pfcrx[0x8];
b4ff3a36 7523 u8 reserved_at_70[0x10];
e281682b 7524
b4ff3a36 7525 u8 reserved_at_80[0x80];
e281682b
SM		 7526};
7527
7528struct mlx5_ifc_pelc_reg_bits {
7529 u8 op[0x4];
b4ff3a36 7530 u8 reserved_at_4[0x4];
e281682b 7531 u8 local_port[0x8];
b4ff3a36 7532 u8 reserved_at_10[0x10];
e281682b
SM		 7533
7534 u8 op_admin[0x8];
7535 u8 op_capability[0x8];
7536 u8 op_request[0x8];
7537 u8 op_active[0x8];
7538
7539 u8 admin[0x40];
7540
7541 u8 capability[0x40];
7542
7543 u8 request[0x40];
7544
7545 u8 active[0x40];
7546
b4ff3a36 7547 u8 reserved_at_140[0x80];
e281682b
SM		 7548};
7549
7550struct mlx5_ifc_peir_reg_bits {
b4ff3a36 7551 u8 reserved_at_0[0x8];
e281682b 7552 u8 local_port[0x8];
b4ff3a36 7553 u8 reserved_at_10[0x10];
e281682b 7554
b4ff3a36 7555 u8 reserved_at_20[0xc];
e281682b 7556 u8 error_count[0x4];
b4ff3a36 7557 u8 reserved_at_30[0x10];
e281682b 7558
b4ff3a36 7559 u8 reserved_at_40[0xc];
e281682b 7560 u8 lane[0x4];
b4ff3a36 7561 u8 reserved_at_50[0x8];
e281682b
SM		 7562 u8 error_type[0x8];
7563};
7564
cfdcbcea
GP		 7565struct mlx5_ifc_pcam_enhanced_features_bits {
7566 u8 reserved_at_0[0x7e];
7567
7568 u8 ppcnt_discard_group[0x1];
7569 u8 ppcnt_statistical_group[0x1];
7570};
7571
7572struct mlx5_ifc_pcam_reg_bits {
7573 u8 reserved_at_0[0x8];
7574 u8 feature_group[0x8];
7575 u8 reserved_at_10[0x8];
7576 u8 access_reg_group[0x8];
7577
7578 u8 reserved_at_20[0x20];
7579
7580 union {
7581 u8 reserved_at_0[0x80];
7582 } port_access_reg_cap_mask;
7583
7584 u8 reserved_at_c0[0x80];
7585
7586 union {
7587 struct mlx5_ifc_pcam_enhanced_features_bits enhanced_features;
7588 u8 reserved_at_0[0x80];
7589 } feature_cap_mask;
7590
7591 u8 reserved_at_1c0[0xc0];
7592};
7593
7594struct mlx5_ifc_mcam_enhanced_features_bits {
7595 u8 reserved_at_0[0x7f];
7596
7597 u8 pcie_performance_group[0x1];
7598};
7599
7600struct mlx5_ifc_mcam_reg_bits {
7601 u8 reserved_at_0[0x8];
7602 u8 feature_group[0x8];
7603 u8 reserved_at_10[0x8];
7604 u8 access_reg_group[0x8];
7605
7606 u8 reserved_at_20[0x20];
7607
7608 union {
7609 u8 reserved_at_0[0x80];
7610 } mng_access_reg_cap_mask;
7611
7612 u8 reserved_at_c0[0x80];
7613
7614 union {
7615 struct mlx5_ifc_mcam_enhanced_features_bits enhanced_features;
7616 u8 reserved_at_0[0x80];
7617 } mng_feature_cap_mask;
7618
7619 u8 reserved_at_1c0[0x80];
7620};
7621
e281682b 7622struct mlx5_ifc_pcap_reg_bits {
b4ff3a36 7623 u8 reserved_at_0[0x8];
e281682b 7624 u8 local_port[0x8];
b4ff3a36 7625 u8 reserved_at_10[0x10];
e281682b
SM		 7626
7627 u8 port_capability_mask[4][0x20];
7628};
7629
7630struct mlx5_ifc_paos_reg_bits {
7631 u8 swid[0x8];
7632 u8 local_port[0x8];
b4ff3a36 7633 u8 reserved_at_10[0x4];
e281682b 7634 u8 admin_status[0x4];
b4ff3a36 7635 u8 reserved_at_18[0x4];
e281682b
SM		 7636 u8 oper_status[0x4];
7637
7638 u8 ase[0x1];
7639 u8 ee[0x1];
b4ff3a36 7640 u8 reserved_at_22[0x1c];
e281682b
SM		 7641 u8 e[0x2];
7642
b4ff3a36 7643 u8 reserved_at_40[0x40];
e281682b
SM		 7644};
7645
7646struct mlx5_ifc_pamp_reg_bits {
b4ff3a36 7647 u8 reserved_at_0[0x8];
e281682b 7648 u8 opamp_group[0x8];
b4ff3a36 7649 u8 reserved_at_10[0xc];
e281682b
SM		 7650 u8 opamp_group_type[0x4];
7651
7652 u8 start_index[0x10];
b4ff3a36 7653 u8 reserved_at_30[0x4];
e281682b
SM		 7654 u8 num_of_indices[0xc];
7655
7656 u8 index_data[18][0x10];
7657};
7658
7d5e1423
SM		 7659struct mlx5_ifc_pcmr_reg_bits {
7660 u8 reserved_at_0[0x8];
7661 u8 local_port[0x8];
7662 u8 reserved_at_10[0x2e];
7663 u8 fcs_cap[0x1];
7664 u8 reserved_at_3f[0x1f];
7665 u8 fcs_chk[0x1];
7666 u8 reserved_at_5f[0x1];
7667};
7668
e281682b 7669struct mlx5_ifc_lane_2_module_mapping_bits {
b4ff3a36 7670 u8 reserved_at_0[0x6];
e281682b 7671 u8 rx_lane[0x2];
b4ff3a36 7672 u8 reserved_at_8[0x6];
e281682b 7673 u8 tx_lane[0x2];
b4ff3a36 7674 u8 reserved_at_10[0x8];
e281682b
SM		 7675 u8 module[0x8];
7676};
7677
7678struct mlx5_ifc_bufferx_reg_bits {
b4ff3a36 7679 u8 reserved_at_0[0x6];
e281682b
SM		 7680 u8 lossy[0x1];
7681 u8 epsb[0x1];
b4ff3a36 7682 u8 reserved_at_8[0xc];
e281682b
SM		 7683 u8 size[0xc];
7684
7685 u8 xoff_threshold[0x10];
7686 u8 xon_threshold[0x10];
7687};
7688
7689struct mlx5_ifc_set_node_in_bits {
7690 u8 node_description[64][0x8];
7691};
7692
7693struct mlx5_ifc_register_power_settings_bits {
b4ff3a36 7694 u8 reserved_at_0[0x18];
e281682b
SM		 7695 u8 power_settings_level[0x8];
7696
b4ff3a36 7697 u8 reserved_at_20[0x60];
e281682b
SM		 7698};
7699
7700struct mlx5_ifc_register_host_endianness_bits {
7701 u8 he[0x1];
b4ff3a36 7702 u8 reserved_at_1[0x1f];
e281682b 7703
b4ff3a36 7704 u8 reserved_at_20[0x60];
e281682b
SM		 7705};
7706
7707struct mlx5_ifc_umr_pointer_desc_argument_bits {
b4ff3a36 7708 u8 reserved_at_0[0x20];
e281682b
SM		 7709
7710 u8 mkey[0x20];
7711
7712 u8 addressh_63_32[0x20];
7713
7714 u8 addressl_31_0[0x20];
7715};
7716
7717struct mlx5_ifc_ud_adrs_vector_bits {
7718 u8 dc_key[0x40];
7719
7720 u8 ext[0x1];
b4ff3a36 7721 u8 reserved_at_41[0x7];
e281682b
SM		 7722 u8 destination_qp_dct[0x18];
7723
7724 u8 static_rate[0x4];
7725 u8 sl_eth_prio[0x4];
7726 u8 fl[0x1];
7727 u8 mlid[0x7];
7728 u8 rlid_udp_sport[0x10];
7729
b4ff3a36 7730 u8 reserved_at_80[0x20];
e281682b
SM		 7731
7732 u8 rmac_47_16[0x20];
7733
7734 u8 rmac_15_0[0x10];
7735 u8 tclass[0x8];
7736 u8 hop_limit[0x8];
7737
b4ff3a36 7738 u8 reserved_at_e0[0x1];
e281682b 7739 u8 grh[0x1];
b4ff3a36 7740 u8 reserved_at_e2[0x2];
e281682b
SM		 7741 u8 src_addr_index[0x8];
7742 u8 flow_label[0x14];
7743
7744 u8 rgid_rip[16][0x8];
7745};
7746
7747struct mlx5_ifc_pages_req_event_bits {
b4ff3a36 7748 u8 reserved_at_0[0x10];
e281682b
SM		 7749 u8 function_id[0x10];
7750
7751 u8 num_pages[0x20];
7752
b4ff3a36 7753 u8 reserved_at_40[0xa0];
e281682b
SM		 7754};
7755
7756struct mlx5_ifc_eqe_bits {
b4ff3a36 7757 u8 reserved_at_0[0x8];
e281682b 7758 u8 event_type[0x8];
b4ff3a36 7759 u8 reserved_at_10[0x8];
e281682b
SM		 7760 u8 event_sub_type[0x8];
7761
b4ff3a36 7762 u8 reserved_at_20[0xe0];
e281682b
SM		 7763
7764 union mlx5_ifc_event_auto_bits event_data;
7765
b4ff3a36 7766 u8 reserved_at_1e0[0x10];
e281682b 7767 u8 signature[0x8];
b4ff3a36 7768 u8 reserved_at_1f8[0x7];
e281682b
SM		 7769 u8 owner[0x1];
7770};
7771
7772enum {
7773 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
7774};
7775
7776struct mlx5_ifc_cmd_queue_entry_bits {
7777 u8 type[0x8];
b4ff3a36 7778 u8 reserved_at_8[0x18];
e281682b
SM		 7779
7780 u8 input_length[0x20];
7781
7782 u8 input_mailbox_pointer_63_32[0x20];
7783
7784 u8 input_mailbox_pointer_31_9[0x17];
b4ff3a36 7785 u8 reserved_at_77[0x9];
e281682b
SM		 7786
7787 u8 command_input_inline_data[16][0x8];
7788
7789 u8 command_output_inline_data[16][0x8];
7790
7791 u8 output_mailbox_pointer_63_32[0x20];
7792
7793 u8 output_mailbox_pointer_31_9[0x17];
b4ff3a36 7794 u8 reserved_at_1b7[0x9];
e281682b
SM		 7795
7796 u8 output_length[0x20];
7797
7798 u8 token[0x8];
7799 u8 signature[0x8];
b4ff3a36 7800 u8 reserved_at_1f0[0x8];
e281682b
SM		 7801 u8 status[0x7];
7802 u8 ownership[0x1];
7803};
7804
7805struct mlx5_ifc_cmd_out_bits {
7806 u8 status[0x8];
b4ff3a36 7807 u8 reserved_at_8[0x18];
e281682b
SM		 7808
7809 u8 syndrome[0x20];
7810
7811 u8 command_output[0x20];
7812};
7813
7814struct mlx5_ifc_cmd_in_bits {
7815 u8 opcode[0x10];
b4ff3a36 7816 u8 reserved_at_10[0x10];
e281682b 7817
b4ff3a36 7818 u8 reserved_at_20[0x10];
e281682b
SM		 7819 u8 op_mod[0x10];
7820
7821 u8 command[0][0x20];
7822};
7823
7824struct mlx5_ifc_cmd_if_box_bits {
7825 u8 mailbox_data[512][0x8];
7826
b4ff3a36 7827 u8 reserved_at_1000[0x180];
e281682b
SM		 7828
7829 u8 next_pointer_63_32[0x20];
7830
7831 u8 next_pointer_31_10[0x16];
b4ff3a36 7832 u8 reserved_at_11b6[0xa];
e281682b
SM		 7833
7834 u8 block_number[0x20];
7835
b4ff3a36 7836 u8 reserved_at_11e0[0x8];
e281682b
SM		 7837 u8 token[0x8];
7838 u8 ctrl_signature[0x8];
7839 u8 signature[0x8];
7840};
7841
7842struct mlx5_ifc_mtt_bits {
7843 u8 ptag_63_32[0x20];
7844
7845 u8 ptag_31_8[0x18];
b4ff3a36 7846 u8 reserved_at_38[0x6];
e281682b
SM		 7847 u8 wr_en[0x1];
7848 u8 rd_en[0x1];
7849};
7850
928cfe87
TT		 7851struct mlx5_ifc_query_wol_rol_out_bits {
7852 u8 status[0x8];
7853 u8 reserved_at_8[0x18];
7854
7855 u8 syndrome[0x20];
7856
7857 u8 reserved_at_40[0x10];
7858 u8 rol_mode[0x8];
7859 u8 wol_mode[0x8];
7860
7861 u8 reserved_at_60[0x20];
7862};
7863
7864struct mlx5_ifc_query_wol_rol_in_bits {
7865 u8 opcode[0x10];
7866 u8 reserved_at_10[0x10];
7867
7868 u8 reserved_at_20[0x10];
7869 u8 op_mod[0x10];
7870
7871 u8 reserved_at_40[0x40];
7872};
7873
7874struct mlx5_ifc_set_wol_rol_out_bits {
7875 u8 status[0x8];
7876 u8 reserved_at_8[0x18];
7877
7878 u8 syndrome[0x20];
7879
7880 u8 reserved_at_40[0x40];
7881};
7882
7883struct mlx5_ifc_set_wol_rol_in_bits {
7884 u8 opcode[0x10];
7885 u8 reserved_at_10[0x10];
7886
7887 u8 reserved_at_20[0x10];
7888 u8 op_mod[0x10];
7889
7890 u8 rol_mode_valid[0x1];
7891 u8 wol_mode_valid[0x1];
7892 u8 reserved_at_42[0xe];
7893 u8 rol_mode[0x8];
7894 u8 wol_mode[0x8];
7895
7896 u8 reserved_at_60[0x20];
7897};
7898
e281682b
SM		 7899enum {
7900 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
7901 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
7902 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
7903};
7904
7905enum {
7906 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
7907 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
7908 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
7909};
7910
7911enum {
7912 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
7913 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
7914 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
7915 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
7916 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
7917 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
7918 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
7919 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
7920 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
7921 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
7922 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
7923};
7924
7925struct mlx5_ifc_initial_seg_bits {
7926 u8 fw_rev_minor[0x10];
7927 u8 fw_rev_major[0x10];
7928
7929 u8 cmd_interface_rev[0x10];
7930 u8 fw_rev_subminor[0x10];
7931
b4ff3a36 7932 u8 reserved_at_40[0x40];
e281682b
SM		 7933
7934 u8 cmdq_phy_addr_63_32[0x20];
7935
7936 u8 cmdq_phy_addr_31_12[0x14];
b4ff3a36 7937 u8 reserved_at_b4[0x2];
e281682b
SM		 7938 u8 nic_interface[0x2];
7939 u8 log_cmdq_size[0x4];
7940 u8 log_cmdq_stride[0x4];
7941
7942 u8 command_doorbell_vector[0x20];
7943
b4ff3a36 7944 u8 reserved_at_e0[0xf00];
e281682b
SM		 7945
7946 u8 initializing[0x1];
b4ff3a36 7947 u8 reserved_at_fe1[0x4];
e281682b 7948 u8 nic_interface_supported[0x3];
b4ff3a36 7949 u8 reserved_at_fe8[0x18];
e281682b
SM		 7950
7951 struct mlx5_ifc_health_buffer_bits health_buffer;
7952
7953 u8 no_dram_nic_offset[0x20];
7954
b4ff3a36 7955 u8 reserved_at_1220[0x6e40];
e281682b 7956
b4ff3a36 7957 u8 reserved_at_8060[0x1f];
e281682b
SM		 7958 u8 clear_int[0x1];
7959
7960 u8 health_syndrome[0x8];
7961 u8 health_counter[0x18];
7962
b4ff3a36 7963 u8 reserved_at_80a0[0x17fc0];
e281682b
SM		 7964};
7965
f9a1ef72
EE		 7966struct mlx5_ifc_mtpps_reg_bits {
7967 u8 reserved_at_0[0xc];
7968 u8 cap_number_of_pps_pins[0x4];
7969 u8 reserved_at_10[0x4];
7970 u8 cap_max_num_of_pps_in_pins[0x4];
7971 u8 reserved_at_18[0x4];
7972 u8 cap_max_num_of_pps_out_pins[0x4];
7973
7974 u8 reserved_at_20[0x24];
7975 u8 cap_pin_3_mode[0x4];
7976 u8 reserved_at_48[0x4];
7977 u8 cap_pin_2_mode[0x4];
7978 u8 reserved_at_50[0x4];
7979 u8 cap_pin_1_mode[0x4];
7980 u8 reserved_at_58[0x4];
7981 u8 cap_pin_0_mode[0x4];
7982
7983 u8 reserved_at_60[0x4];
7984 u8 cap_pin_7_mode[0x4];
7985 u8 reserved_at_68[0x4];
7986 u8 cap_pin_6_mode[0x4];
7987 u8 reserved_at_70[0x4];
7988 u8 cap_pin_5_mode[0x4];
7989 u8 reserved_at_78[0x4];
7990 u8 cap_pin_4_mode[0x4];
7991
7992 u8 reserved_at_80[0x80];
7993
7994 u8 enable[0x1];
7995 u8 reserved_at_101[0xb];
7996 u8 pattern[0x4];
7997 u8 reserved_at_110[0x4];
7998 u8 pin_mode[0x4];
7999 u8 pin[0x8];
8000
8001 u8 reserved_at_120[0x20];
8002
8003 u8 time_stamp[0x40];
8004
8005 u8 out_pulse_duration[0x10];
8006 u8 out_periodic_adjustment[0x10];
8007
8008 u8 reserved_at_1a0[0x60];
8009};
8010
8011struct mlx5_ifc_mtppse_reg_bits {
8012 u8 reserved_at_0[0x18];
8013 u8 pin[0x8];
8014 u8 event_arm[0x1];
8015 u8 reserved_at_21[0x1b];
8016 u8 event_generation_mode[0x4];
8017 u8 reserved_at_40[0x40];
8018};
8019
e281682b
SM		 8020union mlx5_ifc_ports_control_registers_document_bits {
8021 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
8022 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
8023 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
8024 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
8025 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
8026 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
8027 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
8028 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
8029 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
8030 struct mlx5_ifc_pamp_reg_bits pamp_reg;
8031 struct mlx5_ifc_paos_reg_bits paos_reg;
8032 struct mlx5_ifc_pcap_reg_bits pcap_reg;
8033 struct mlx5_ifc_peir_reg_bits peir_reg;
8034 struct mlx5_ifc_pelc_reg_bits pelc_reg;
8035 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
1c64bf6f 8036 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b
SM		 8037 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
8038 struct mlx5_ifc_pifr_reg_bits pifr_reg;
8039 struct mlx5_ifc_pipg_reg_bits pipg_reg;
8040 struct mlx5_ifc_plbf_reg_bits plbf_reg;
8041 struct mlx5_ifc_plib_reg_bits plib_reg;
8042 struct mlx5_ifc_plpc_reg_bits plpc_reg;
8043 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
8044 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
8045 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
8046 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
8047 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
8048 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
8049 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
8050 struct mlx5_ifc_ppad_reg_bits ppad_reg;
8051 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
8ed1a630 8052 struct mlx5_ifc_mpcnt_reg_bits mpcnt_reg;
e281682b
SM		 8053 struct mlx5_ifc_pplm_reg_bits pplm_reg;
8054 struct mlx5_ifc_pplr_reg_bits pplr_reg;
8055 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
8056 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
8057 struct mlx5_ifc_pspa_reg_bits pspa_reg;
8058 struct mlx5_ifc_ptas_reg_bits ptas_reg;
8059 struct mlx5_ifc_ptys_reg_bits ptys_reg;
7d5e1423 8060 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
e281682b
SM		 8061 struct mlx5_ifc_pude_reg_bits pude_reg;
8062 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
8063 struct mlx5_ifc_slrg_reg_bits slrg_reg;
8064 struct mlx5_ifc_sltp_reg_bits sltp_reg;
f9a1ef72
EE		 8065 struct mlx5_ifc_mtpps_reg_bits mtpps_reg;
8066 struct mlx5_ifc_mtppse_reg_bits mtppse_reg;
b4ff3a36 8067 u8 reserved_at_0[0x60e0];
e281682b
SM		 8068};
8069
8070union mlx5_ifc_debug_enhancements_document_bits {
8071 struct mlx5_ifc_health_buffer_bits health_buffer;
b4ff3a36 8072 u8 reserved_at_0[0x200];
e281682b
SM		 8073};
8074
8075union mlx5_ifc_uplink_pci_interface_document_bits {
8076 struct mlx5_ifc_initial_seg_bits initial_seg;
b4ff3a36 8077 u8 reserved_at_0[0x20060];
b775516b
EC		 8078};
8079
2cc43b49
MG		 8080struct mlx5_ifc_set_flow_table_root_out_bits {
8081 u8 status[0x8];
b4ff3a36 8082 u8 reserved_at_8[0x18];
2cc43b49
MG		 8083
8084 u8 syndrome[0x20];
8085
b4ff3a36 8086 u8 reserved_at_40[0x40];
2cc43b49
MG		 8087};
8088
8089struct mlx5_ifc_set_flow_table_root_in_bits {
8090 u8 opcode[0x10];
b4ff3a36 8091 u8 reserved_at_10[0x10];
2cc43b49 8092
b4ff3a36 8093 u8 reserved_at_20[0x10];
2cc43b49
MG		 8094 u8 op_mod[0x10];
8095
7d5e1423
SM		 8096 u8 other_vport[0x1];
8097 u8 reserved_at_41[0xf];
8098 u8 vport_number[0x10];
8099
8100 u8 reserved_at_60[0x20];
2cc43b49
MG		 8101
8102 u8 table_type[0x8];
b4ff3a36 8103 u8 reserved_at_88[0x18];
2cc43b49 8104
b4ff3a36 8105 u8 reserved_at_a0[0x8];
2cc43b49
MG		 8106 u8 table_id[0x18];
8107
b4ff3a36 8108 u8 reserved_at_c0[0x140];
2cc43b49
MG		 8109};
8110
34a40e68 8111enum {
84df61eb
AH		 8112 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = (1UL << 0),
8113 MLX5_MODIFY_FLOW_TABLE_LAG_NEXT_TABLE_ID = (1UL << 15),
34a40e68
MG		 8114};
8115
8116struct mlx5_ifc_modify_flow_table_out_bits {
8117 u8 status[0x8];
b4ff3a36 8118 u8 reserved_at_8[0x18];
34a40e68
MG		 8119
8120 u8 syndrome[0x20];
8121
b4ff3a36 8122 u8 reserved_at_40[0x40];
34a40e68
MG		 8123};
8124
8125struct mlx5_ifc_modify_flow_table_in_bits {
8126 u8 opcode[0x10];
b4ff3a36 8127 u8 reserved_at_10[0x10];
34a40e68 8128
b4ff3a36 8129 u8 reserved_at_20[0x10];
34a40e68
MG		 8130 u8 op_mod[0x10];
8131
7d5e1423
SM		 8132 u8 other_vport[0x1];
8133 u8 reserved_at_41[0xf];
8134 u8 vport_number[0x10];
34a40e68 8135
b4ff3a36 8136 u8 reserved_at_60[0x10];
34a40e68
MG		 8137 u8 modify_field_select[0x10];
8138
8139 u8 table_type[0x8];
b4ff3a36 8140 u8 reserved_at_88[0x18];
34a40e68 8141
b4ff3a36 8142 u8 reserved_at_a0[0x8];
34a40e68
MG		 8143 u8 table_id[0x18];
8144
b4ff3a36 8145 u8 reserved_at_c0[0x4];
34a40e68 8146 u8 table_miss_mode[0x4];
b4ff3a36 8147 u8 reserved_at_c8[0x18];
34a40e68 8148
b4ff3a36 8149 u8 reserved_at_e0[0x8];
34a40e68
MG		 8150 u8 table_miss_id[0x18];
8151
84df61eb
AH		 8152 u8 reserved_at_100[0x8];
8153 u8 lag_master_next_table_id[0x18];
8154
8155 u8 reserved_at_120[0x80];
34a40e68
MG		 8156};
8157
4f3961ee
SM		 8158struct mlx5_ifc_ets_tcn_config_reg_bits {
8159 u8 g[0x1];
8160 u8 b[0x1];
8161 u8 r[0x1];
8162 u8 reserved_at_3[0x9];
8163 u8 group[0x4];
8164 u8 reserved_at_10[0x9];
8165 u8 bw_allocation[0x7];
8166
8167 u8 reserved_at_20[0xc];
8168 u8 max_bw_units[0x4];
8169 u8 reserved_at_30[0x8];
8170 u8 max_bw_value[0x8];
8171};
8172
8173struct mlx5_ifc_ets_global_config_reg_bits {
8174 u8 reserved_at_0[0x2];
8175 u8 r[0x1];
8176 u8 reserved_at_3[0x1d];
8177
8178 u8 reserved_at_20[0xc];
8179 u8 max_bw_units[0x4];
8180 u8 reserved_at_30[0x8];
8181 u8 max_bw_value[0x8];
8182};
8183
8184struct mlx5_ifc_qetc_reg_bits {
8185 u8 reserved_at_0[0x8];
8186 u8 port_number[0x8];
8187 u8 reserved_at_10[0x30];
8188
8189 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
8190 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
8191};
8192
8193struct mlx5_ifc_qtct_reg_bits {
8194 u8 reserved_at_0[0x8];
8195 u8 port_number[0x8];
8196 u8 reserved_at_10[0xd];
8197 u8 prio[0x3];
8198
8199 u8 reserved_at_20[0x1d];
8200 u8 tclass[0x3];
8201};
8202
7d5e1423
SM		 8203struct mlx5_ifc_mcia_reg_bits {
8204 u8 l[0x1];
8205 u8 reserved_at_1[0x7];
8206 u8 module[0x8];
8207 u8 reserved_at_10[0x8];
8208 u8 status[0x8];
8209
8210 u8 i2c_device_address[0x8];
8211 u8 page_number[0x8];
8212 u8 device_address[0x10];
8213
8214 u8 reserved_at_40[0x10];
8215 u8 size[0x10];
8216
8217 u8 reserved_at_60[0x20];
8218
8219 u8 dword_0[0x20];
8220 u8 dword_1[0x20];
8221 u8 dword_2[0x20];
8222 u8 dword_3[0x20];
8223 u8 dword_4[0x20];
8224 u8 dword_5[0x20];
8225 u8 dword_6[0x20];
8226 u8 dword_7[0x20];
8227 u8 dword_8[0x20];
8228 u8 dword_9[0x20];
8229 u8 dword_10[0x20];
8230 u8 dword_11[0x20];
8231};
8232
7486216b
SM		 8233struct mlx5_ifc_dcbx_param_bits {
8234 u8 dcbx_cee_cap[0x1];
8235 u8 dcbx_ieee_cap[0x1];
8236 u8 dcbx_standby_cap[0x1];
8237 u8 reserved_at_0[0x5];
8238 u8 port_number[0x8];
8239 u8 reserved_at_10[0xa];
8240 u8 max_application_table_size[6];
8241 u8 reserved_at_20[0x15];
8242 u8 version_oper[0x3];
8243 u8 reserved_at_38[5];
8244 u8 version_admin[0x3];
8245 u8 willing_admin[0x1];
8246 u8 reserved_at_41[0x3];
8247 u8 pfc_cap_oper[0x4];
8248 u8 reserved_at_48[0x4];
8249 u8 pfc_cap_admin[0x4];
8250 u8 reserved_at_50[0x4];
8251 u8 num_of_tc_oper[0x4];
8252 u8 reserved_at_58[0x4];
8253 u8 num_of_tc_admin[0x4];
8254 u8 remote_willing[0x1];
8255 u8 reserved_at_61[3];
8256 u8 remote_pfc_cap[4];
8257 u8 reserved_at_68[0x14];
8258 u8 remote_num_of_tc[0x4];
8259 u8 reserved_at_80[0x18];
8260 u8 error[0x8];
8261 u8 reserved_at_a0[0x160];
8262};
84df61eb
AH		 8263
8264struct mlx5_ifc_lagc_bits {
8265 u8 reserved_at_0[0x1d];
8266 u8 lag_state[0x3];
8267
8268 u8 reserved_at_20[0x14];
8269 u8 tx_remap_affinity_2[0x4];
8270 u8 reserved_at_38[0x4];
8271 u8 tx_remap_affinity_1[0x4];
8272};
8273
8274struct mlx5_ifc_create_lag_out_bits {
8275 u8 status[0x8];
8276 u8 reserved_at_8[0x18];
8277
8278 u8 syndrome[0x20];
8279
8280 u8 reserved_at_40[0x40];
8281};
8282
8283struct mlx5_ifc_create_lag_in_bits {
8284 u8 opcode[0x10];
8285 u8 reserved_at_10[0x10];
8286
8287 u8 reserved_at_20[0x10];
8288 u8 op_mod[0x10];
8289
8290 struct mlx5_ifc_lagc_bits ctx;
8291};
8292
8293struct mlx5_ifc_modify_lag_out_bits {
8294 u8 status[0x8];
8295 u8 reserved_at_8[0x18];
8296
8297 u8 syndrome[0x20];
8298
8299 u8 reserved_at_40[0x40];
8300};
8301
8302struct mlx5_ifc_modify_lag_in_bits {
8303 u8 opcode[0x10];
8304 u8 reserved_at_10[0x10];
8305
8306 u8 reserved_at_20[0x10];
8307 u8 op_mod[0x10];
8308
8309 u8 reserved_at_40[0x20];
8310 u8 field_select[0x20];
8311
8312 struct mlx5_ifc_lagc_bits ctx;
8313};
8314
8315struct mlx5_ifc_query_lag_out_bits {
8316 u8 status[0x8];
8317 u8 reserved_at_8[0x18];
8318
8319 u8 syndrome[0x20];
8320
8321 u8 reserved_at_40[0x40];
8322
8323 struct mlx5_ifc_lagc_bits ctx;
8324};
8325
8326struct mlx5_ifc_query_lag_in_bits {
8327 u8 opcode[0x10];
8328 u8 reserved_at_10[0x10];
8329
8330 u8 reserved_at_20[0x10];
8331 u8 op_mod[0x10];
8332
8333 u8 reserved_at_40[0x40];
8334};
8335
8336struct mlx5_ifc_destroy_lag_out_bits {
8337 u8 status[0x8];
8338 u8 reserved_at_8[0x18];
8339
8340 u8 syndrome[0x20];
8341
8342 u8 reserved_at_40[0x40];
8343};
8344
8345struct mlx5_ifc_destroy_lag_in_bits {
8346 u8 opcode[0x10];
8347 u8 reserved_at_10[0x10];
8348
8349 u8 reserved_at_20[0x10];
8350 u8 op_mod[0x10];
8351
8352 u8 reserved_at_40[0x40];
8353};
8354
8355struct mlx5_ifc_create_vport_lag_out_bits {
8356 u8 status[0x8];
8357 u8 reserved_at_8[0x18];
8358
8359 u8 syndrome[0x20];
8360
8361 u8 reserved_at_40[0x40];
8362};
8363
8364struct mlx5_ifc_create_vport_lag_in_bits {
8365 u8 opcode[0x10];
8366 u8 reserved_at_10[0x10];
8367
8368 u8 reserved_at_20[0x10];
8369 u8 op_mod[0x10];
8370
8371 u8 reserved_at_40[0x40];
8372};
8373
8374struct mlx5_ifc_destroy_vport_lag_out_bits {
8375 u8 status[0x8];
8376 u8 reserved_at_8[0x18];
8377
8378 u8 syndrome[0x20];
8379
8380 u8 reserved_at_40[0x40];
8381};
8382
8383struct mlx5_ifc_destroy_vport_lag_in_bits {
8384 u8 opcode[0x10];
8385 u8 reserved_at_10[0x10];
8386
8387 u8 reserved_at_20[0x10];
8388 u8 op_mod[0x10];
8389
8390 u8 reserved_at_40[0x40];
8391};
8392
d29b796a 8393#endif /* MLX5_IFC_H */
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