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net/mlx5e: Check the minimum inline header mode before xmit
[mirror_ubuntu-bionic-kernel.git] / include / linux / mlx5 / mlx5_ifc.h
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d29b796a 1/*
e281682b 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
d29b796a
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
e281682b 31*/
d29b796a
EC		 32#ifndef MLX5_IFC_H
33#define MLX5_IFC_H
34
e281682b
SM		 35enum {
36 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
37 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
38 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
39 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
40 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
41 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
42 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
43 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
44 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
45 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
46 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
47 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
48 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
49 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
50 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
51 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
52 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
53 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
54 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
55 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
56 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
57 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
58 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
59 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb
60};
61
62enum {
63 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
64 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
65 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
66 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
67};
68
f91e6d89
EBE		 69enum {
70 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
71 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
72};
73
d29b796a
EC		 74enum {
75 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
76 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
77 MLX5_CMD_OP_INIT_HCA = 0x102,
78 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
79 MLX5_CMD_OP_ENABLE_HCA = 0x104,
80 MLX5_CMD_OP_DISABLE_HCA = 0x105,
81 MLX5_CMD_OP_QUERY_PAGES = 0x107,
82 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
83 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
e281682b
SM		 84 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
85 MLX5_CMD_OP_SET_ISSI = 0x10b,
d29b796a
EC		 86 MLX5_CMD_OP_CREATE_MKEY = 0x200,
87 MLX5_CMD_OP_QUERY_MKEY = 0x201,
88 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
89 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
90 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
91 MLX5_CMD_OP_CREATE_EQ = 0x301,
92 MLX5_CMD_OP_DESTROY_EQ = 0x302,
93 MLX5_CMD_OP_QUERY_EQ = 0x303,
94 MLX5_CMD_OP_GEN_EQE = 0x304,
95 MLX5_CMD_OP_CREATE_CQ = 0x400,
96 MLX5_CMD_OP_DESTROY_CQ = 0x401,
97 MLX5_CMD_OP_QUERY_CQ = 0x402,
98 MLX5_CMD_OP_MODIFY_CQ = 0x403,
99 MLX5_CMD_OP_CREATE_QP = 0x500,
100 MLX5_CMD_OP_DESTROY_QP = 0x501,
101 MLX5_CMD_OP_RST2INIT_QP = 0x502,
102 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
103 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
104 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
105 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
106 MLX5_CMD_OP_2ERR_QP = 0x507,
107 MLX5_CMD_OP_2RST_QP = 0x50a,
108 MLX5_CMD_OP_QUERY_QP = 0x50b,
e281682b 109 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
d29b796a
EC		 110 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
111 MLX5_CMD_OP_CREATE_PSV = 0x600,
112 MLX5_CMD_OP_DESTROY_PSV = 0x601,
113 MLX5_CMD_OP_CREATE_SRQ = 0x700,
114 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
115 MLX5_CMD_OP_QUERY_SRQ = 0x702,
116 MLX5_CMD_OP_ARM_RQ = 0x703,
e281682b
SM		 117 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
118 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
119 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
120 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
d29b796a
EC		 121 MLX5_CMD_OP_CREATE_DCT = 0x710,
122 MLX5_CMD_OP_DESTROY_DCT = 0x711,
123 MLX5_CMD_OP_DRAIN_DCT = 0x712,
124 MLX5_CMD_OP_QUERY_DCT = 0x713,
125 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
7486216b
SM		 126 MLX5_CMD_OP_CREATE_XRQ = 0x717,
127 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
128 MLX5_CMD_OP_QUERY_XRQ = 0x719,
129 MLX5_CMD_OP_ARM_XRQ = 0x71a,
d29b796a
EC		 130 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
131 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
132 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
133 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
134 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
135 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
e281682b 136 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
d29b796a 137 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
e281682b
SM		 138 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
139 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
140 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
141 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
d29b796a
EC		 142 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
143 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
144 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
145 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
7486216b
SM		 146 MLX5_CMD_OP_SET_RATE_LIMIT = 0x780,
147 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
d29b796a
EC		 148 MLX5_CMD_OP_ALLOC_PD = 0x800,
149 MLX5_CMD_OP_DEALLOC_PD = 0x801,
150 MLX5_CMD_OP_ALLOC_UAR = 0x802,
151 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
152 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
153 MLX5_CMD_OP_ACCESS_REG = 0x805,
154 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
e281682b 155 MLX5_CMD_OP_DETTACH_FROM_MCG = 0x807,
d29b796a
EC		 156 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
157 MLX5_CMD_OP_MAD_IFC = 0x50d,
158 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
159 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
160 MLX5_CMD_OP_NOP = 0x80d,
161 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
162 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
e281682b
SM		 163 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
164 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
165 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
166 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
167 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
168 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
169 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
170 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
171 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
172 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
173 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
174 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
928cfe87
TT		 175 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
176 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
d29b796a
EC		 177 MLX5_CMD_OP_CREATE_TIR = 0x900,
178 MLX5_CMD_OP_MODIFY_TIR = 0x901,
179 MLX5_CMD_OP_DESTROY_TIR = 0x902,
180 MLX5_CMD_OP_QUERY_TIR = 0x903,
d29b796a
EC		 181 MLX5_CMD_OP_CREATE_SQ = 0x904,
182 MLX5_CMD_OP_MODIFY_SQ = 0x905,
183 MLX5_CMD_OP_DESTROY_SQ = 0x906,
184 MLX5_CMD_OP_QUERY_SQ = 0x907,
185 MLX5_CMD_OP_CREATE_RQ = 0x908,
186 MLX5_CMD_OP_MODIFY_RQ = 0x909,
187 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
188 MLX5_CMD_OP_QUERY_RQ = 0x90b,
189 MLX5_CMD_OP_CREATE_RMP = 0x90c,
190 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
191 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
192 MLX5_CMD_OP_QUERY_RMP = 0x90f,
e281682b
SM		 193 MLX5_CMD_OP_CREATE_TIS = 0x912,
194 MLX5_CMD_OP_MODIFY_TIS = 0x913,
195 MLX5_CMD_OP_DESTROY_TIS = 0x914,
196 MLX5_CMD_OP_QUERY_TIS = 0x915,
197 MLX5_CMD_OP_CREATE_RQT = 0x916,
198 MLX5_CMD_OP_MODIFY_RQT = 0x917,
199 MLX5_CMD_OP_DESTROY_RQT = 0x918,
200 MLX5_CMD_OP_QUERY_RQT = 0x919,
2cc43b49 201 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
e281682b
SM		 202 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
203 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
204 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
205 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
206 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
207 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
208 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
209 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
34a40e68 210 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
9dc0b289
AV		 211 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
212 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
213 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
86d56a1a
SK		 214 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
215 MLX5_CMD_OP_MAX
e281682b
SM		 216};
217
218struct mlx5_ifc_flow_table_fields_supported_bits {
219 u8 outer_dmac[0x1];
220 u8 outer_smac[0x1];
221 u8 outer_ether_type[0x1];
b4ff3a36 222 u8 reserved_at_3[0x1];
e281682b
SM		 223 u8 outer_first_prio[0x1];
224 u8 outer_first_cfi[0x1];
225 u8 outer_first_vid[0x1];
b4ff3a36 226 u8 reserved_at_7[0x1];
e281682b
SM		 227 u8 outer_second_prio[0x1];
228 u8 outer_second_cfi[0x1];
229 u8 outer_second_vid[0x1];
b4ff3a36 230 u8 reserved_at_b[0x1];
e281682b
SM		 231 u8 outer_sip[0x1];
232 u8 outer_dip[0x1];
233 u8 outer_frag[0x1];
234 u8 outer_ip_protocol[0x1];
235 u8 outer_ip_ecn[0x1];
236 u8 outer_ip_dscp[0x1];
237 u8 outer_udp_sport[0x1];
238 u8 outer_udp_dport[0x1];
239 u8 outer_tcp_sport[0x1];
240 u8 outer_tcp_dport[0x1];
241 u8 outer_tcp_flags[0x1];
242 u8 outer_gre_protocol[0x1];
243 u8 outer_gre_key[0x1];
244 u8 outer_vxlan_vni[0x1];
b4ff3a36 245 u8 reserved_at_1a[0x5];
e281682b
SM		 246 u8 source_eswitch_port[0x1];
247
248 u8 inner_dmac[0x1];
249 u8 inner_smac[0x1];
250 u8 inner_ether_type[0x1];
b4ff3a36 251 u8 reserved_at_23[0x1];
e281682b
SM		 252 u8 inner_first_prio[0x1];
253 u8 inner_first_cfi[0x1];
254 u8 inner_first_vid[0x1];
b4ff3a36 255 u8 reserved_at_27[0x1];
e281682b
SM		 256 u8 inner_second_prio[0x1];
257 u8 inner_second_cfi[0x1];
258 u8 inner_second_vid[0x1];
b4ff3a36 259 u8 reserved_at_2b[0x1];
e281682b
SM		 260 u8 inner_sip[0x1];
261 u8 inner_dip[0x1];
262 u8 inner_frag[0x1];
263 u8 inner_ip_protocol[0x1];
264 u8 inner_ip_ecn[0x1];
265 u8 inner_ip_dscp[0x1];
266 u8 inner_udp_sport[0x1];
267 u8 inner_udp_dport[0x1];
268 u8 inner_tcp_sport[0x1];
269 u8 inner_tcp_dport[0x1];
270 u8 inner_tcp_flags[0x1];
b4ff3a36 271 u8 reserved_at_37[0x9];
e281682b 272
b4ff3a36 273 u8 reserved_at_40[0x40];
e281682b
SM		 274};
275
276struct mlx5_ifc_flow_table_prop_layout_bits {
277 u8 ft_support[0x1];
9dc0b289
AV		 278 u8 reserved_at_1[0x1];
279 u8 flow_counter[0x1];
26a81453 280 u8 flow_modify_en[0x1];
2cc43b49 281 u8 modify_root[0x1];
34a40e68
MG		 282 u8 identified_miss_table_mode[0x1];
283 u8 flow_table_modify[0x1];
b4ff3a36 284 u8 reserved_at_7[0x19];
e281682b 285
b4ff3a36 286 u8 reserved_at_20[0x2];
e281682b 287 u8 log_max_ft_size[0x6];
b4ff3a36 288 u8 reserved_at_28[0x10];
e281682b
SM		 289 u8 max_ft_level[0x8];
290
b4ff3a36 291 u8 reserved_at_40[0x20];
e281682b 292
b4ff3a36 293 u8 reserved_at_60[0x18];
e281682b
SM		 294 u8 log_max_ft_num[0x8];
295
b4ff3a36 296 u8 reserved_at_80[0x18];
e281682b
SM		 297 u8 log_max_destination[0x8];
298
b4ff3a36 299 u8 reserved_at_a0[0x18];
e281682b
SM		 300 u8 log_max_flow[0x8];
301
b4ff3a36 302 u8 reserved_at_c0[0x40];
e281682b
SM		 303
304 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
305
306 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
307};
308
309struct mlx5_ifc_odp_per_transport_service_cap_bits {
310 u8 send[0x1];
311 u8 receive[0x1];
312 u8 write[0x1];
313 u8 read[0x1];
b4ff3a36 314 u8 reserved_at_4[0x1];
e281682b 315 u8 srq_receive[0x1];
b4ff3a36 316 u8 reserved_at_6[0x1a];
e281682b
SM		 317};
318
b4d1f032 319struct mlx5_ifc_ipv4_layout_bits {
b4ff3a36 320 u8 reserved_at_0[0x60];
b4d1f032
MG		 321
322 u8 ipv4[0x20];
323};
324
325struct mlx5_ifc_ipv6_layout_bits {
326 u8 ipv6[16][0x8];
327};
328
329union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
330 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
331 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
b4ff3a36 332 u8 reserved_at_0[0x80];
b4d1f032
MG		 333};
334
e281682b
SM		 335struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
336 u8 smac_47_16[0x20];
337
338 u8 smac_15_0[0x10];
339 u8 ethertype[0x10];
340
341 u8 dmac_47_16[0x20];
342
343 u8 dmac_15_0[0x10];
344 u8 first_prio[0x3];
345 u8 first_cfi[0x1];
346 u8 first_vid[0xc];
347
348 u8 ip_protocol[0x8];
349 u8 ip_dscp[0x6];
350 u8 ip_ecn[0x2];
351 u8 vlan_tag[0x1];
b4ff3a36 352 u8 reserved_at_91[0x1];
e281682b 353 u8 frag[0x1];
b4ff3a36 354 u8 reserved_at_93[0x4];
e281682b
SM		 355 u8 tcp_flags[0x9];
356
357 u8 tcp_sport[0x10];
358 u8 tcp_dport[0x10];
359
b4ff3a36 360 u8 reserved_at_c0[0x20];
e281682b
SM		 361
362 u8 udp_sport[0x10];
363 u8 udp_dport[0x10];
364
b4d1f032 365 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
e281682b 366
b4d1f032 367 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
e281682b
SM		 368};
369
370struct mlx5_ifc_fte_match_set_misc_bits {
7486216b
SM		 371 u8 reserved_at_0[0x8];
372 u8 source_sqn[0x18];
e281682b 373
b4ff3a36 374 u8 reserved_at_20[0x10];
e281682b
SM		 375 u8 source_port[0x10];
376
377 u8 outer_second_prio[0x3];
378 u8 outer_second_cfi[0x1];
379 u8 outer_second_vid[0xc];
380 u8 inner_second_prio[0x3];
381 u8 inner_second_cfi[0x1];
382 u8 inner_second_vid[0xc];
383
384 u8 outer_second_vlan_tag[0x1];
385 u8 inner_second_vlan_tag[0x1];
b4ff3a36 386 u8 reserved_at_62[0xe];
e281682b
SM		 387 u8 gre_protocol[0x10];
388
389 u8 gre_key_h[0x18];
390 u8 gre_key_l[0x8];
391
392 u8 vxlan_vni[0x18];
b4ff3a36 393 u8 reserved_at_b8[0x8];
e281682b 394
b4ff3a36 395 u8 reserved_at_c0[0x20];
e281682b 396
b4ff3a36 397 u8 reserved_at_e0[0xc];
e281682b
SM		 398 u8 outer_ipv6_flow_label[0x14];
399
b4ff3a36 400 u8 reserved_at_100[0xc];
e281682b
SM		 401 u8 inner_ipv6_flow_label[0x14];
402
b4ff3a36 403 u8 reserved_at_120[0xe0];
e281682b
SM		 404};
405
406struct mlx5_ifc_cmd_pas_bits {
407 u8 pa_h[0x20];
408
409 u8 pa_l[0x14];
b4ff3a36 410 u8 reserved_at_34[0xc];
e281682b
SM		 411};
412
413struct mlx5_ifc_uint64_bits {
414 u8 hi[0x20];
415
416 u8 lo[0x20];
417};
418
419enum {
420 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
421 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
422 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
423 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
424 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
425 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
426 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
427 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
428 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
429 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
430};
431
432struct mlx5_ifc_ads_bits {
433 u8 fl[0x1];
434 u8 free_ar[0x1];
b4ff3a36 435 u8 reserved_at_2[0xe];
e281682b
SM		 436 u8 pkey_index[0x10];
437
b4ff3a36 438 u8 reserved_at_20[0x8];
e281682b
SM		 439 u8 grh[0x1];
440 u8 mlid[0x7];
441 u8 rlid[0x10];
442
443 u8 ack_timeout[0x5];
b4ff3a36 444 u8 reserved_at_45[0x3];
e281682b 445 u8 src_addr_index[0x8];
b4ff3a36 446 u8 reserved_at_50[0x4];
e281682b
SM		 447 u8 stat_rate[0x4];
448 u8 hop_limit[0x8];
449
b4ff3a36 450 u8 reserved_at_60[0x4];
e281682b
SM		 451 u8 tclass[0x8];
452 u8 flow_label[0x14];
453
454 u8 rgid_rip[16][0x8];
455
b4ff3a36 456 u8 reserved_at_100[0x4];
e281682b
SM		 457 u8 f_dscp[0x1];
458 u8 f_ecn[0x1];
b4ff3a36 459 u8 reserved_at_106[0x1];
e281682b
SM		 460 u8 f_eth_prio[0x1];
461 u8 ecn[0x2];
462 u8 dscp[0x6];
463 u8 udp_sport[0x10];
464
465 u8 dei_cfi[0x1];
466 u8 eth_prio[0x3];
467 u8 sl[0x4];
468 u8 port[0x8];
469 u8 rmac_47_32[0x10];
470
471 u8 rmac_31_0[0x20];
472};
473
474struct mlx5_ifc_flow_table_nic_cap_bits {
b3638e1a
MG		 475 u8 nic_rx_multi_path_tirs[0x1];
476 u8 reserved_at_1[0x1ff];
e281682b
SM		 477
478 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
479
b4ff3a36 480 u8 reserved_at_400[0x200];
e281682b
SM		 481
482 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
483
484 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
485
b4ff3a36 486 u8 reserved_at_a00[0x200];
e281682b
SM		 487
488 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
489
b4ff3a36 490 u8 reserved_at_e00[0x7200];
e281682b
SM		 491};
492
495716b1 493struct mlx5_ifc_flow_table_eswitch_cap_bits {
b4ff3a36 494 u8 reserved_at_0[0x200];
495716b1
SM		 495
496 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
497
498 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
499
500 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
501
b4ff3a36 502 u8 reserved_at_800[0x7800];
495716b1
SM		 503};
504
d6666753
SM		 505struct mlx5_ifc_e_switch_cap_bits {
506 u8 vport_svlan_strip[0x1];
507 u8 vport_cvlan_strip[0x1];
508 u8 vport_svlan_insert[0x1];
509 u8 vport_cvlan_insert_if_not_exist[0x1];
510 u8 vport_cvlan_insert_overwrite[0x1];
23898c76
NO		 511 u8 reserved_at_5[0x19];
512 u8 nic_vport_node_guid_modify[0x1];
513 u8 nic_vport_port_guid_modify[0x1];
d6666753 514
b4ff3a36 515 u8 reserved_at_20[0x7e0];
d6666753
SM		 516};
517
7486216b
SM		 518struct mlx5_ifc_qos_cap_bits {
519 u8 packet_pacing[0x1];
520 u8 reserved_0[0x1f];
521 u8 reserved_1[0x20];
522 u8 packet_pacing_max_rate[0x20];
523 u8 packet_pacing_min_rate[0x20];
524 u8 reserved_2[0x10];
525 u8 packet_pacing_rate_table_size[0x10];
526 u8 reserved_3[0x760];
527};
528
e281682b
SM		 529struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
530 u8 csum_cap[0x1];
531 u8 vlan_cap[0x1];
532 u8 lro_cap[0x1];
533 u8 lro_psh_flag[0x1];
534 u8 lro_time_stamp[0x1];
b4ff3a36 535 u8 reserved_at_5[0x3];
66189961 536 u8 self_lb_en_modifiable[0x1];
b4ff3a36 537 u8 reserved_at_9[0x2];
e281682b 538 u8 max_lso_cap[0x5];
b4ff3a36 539 u8 reserved_at_10[0x4];
e281682b 540 u8 rss_ind_tbl_cap[0x4];
7d5e1423
SM		 541 u8 reg_umr_sq[0x1];
542 u8 scatter_fcs[0x1];
543 u8 reserved_at_1a[0x1];
e281682b 544 u8 tunnel_lso_const_out_ip_id[0x1];
b4ff3a36 545 u8 reserved_at_1c[0x2];
e281682b
SM		 546 u8 tunnel_statless_gre[0x1];
547 u8 tunnel_stateless_vxlan[0x1];
548
b4ff3a36 549 u8 reserved_at_20[0x20];
e281682b 550
b4ff3a36 551 u8 reserved_at_40[0x10];
e281682b
SM		 552 u8 lro_min_mss_size[0x10];
553
b4ff3a36 554 u8 reserved_at_60[0x120];
e281682b
SM		 555
556 u8 lro_timer_supported_periods[4][0x20];
557
b4ff3a36 558 u8 reserved_at_200[0x600];
e281682b
SM		 559};
560
561struct mlx5_ifc_roce_cap_bits {
562 u8 roce_apm[0x1];
b4ff3a36 563 u8 reserved_at_1[0x1f];
e281682b 564
b4ff3a36 565 u8 reserved_at_20[0x60];
e281682b 566
b4ff3a36 567 u8 reserved_at_80[0xc];
e281682b 568 u8 l3_type[0x4];
b4ff3a36 569 u8 reserved_at_90[0x8];
e281682b
SM		 570 u8 roce_version[0x8];
571
b4ff3a36 572 u8 reserved_at_a0[0x10];
e281682b
SM		 573 u8 r_roce_dest_udp_port[0x10];
574
575 u8 r_roce_max_src_udp_port[0x10];
576 u8 r_roce_min_src_udp_port[0x10];
577
b4ff3a36 578 u8 reserved_at_e0[0x10];
e281682b
SM		 579 u8 roce_address_table_size[0x10];
580
b4ff3a36 581 u8 reserved_at_100[0x700];
e281682b
SM		 582};
583
584enum {
585 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
586 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
587 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
588 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
589 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
590 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
591 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
592 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
593 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
594};
595
596enum {
597 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
598 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
599 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
600 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
601 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
602 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
603 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
604 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
605 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
606};
607
608struct mlx5_ifc_atomic_caps_bits {
b4ff3a36 609 u8 reserved_at_0[0x40];
e281682b 610
f91e6d89 611 u8 atomic_req_8B_endianess_mode[0x2];
b4ff3a36 612 u8 reserved_at_42[0x4];
f91e6d89 613 u8 supported_atomic_req_8B_endianess_mode_1[0x1];
e281682b 614
b4ff3a36 615 u8 reserved_at_47[0x19];
e281682b 616
b4ff3a36 617 u8 reserved_at_60[0x20];
e281682b 618
b4ff3a36 619 u8 reserved_at_80[0x10];
f91e6d89 620 u8 atomic_operations[0x10];
e281682b 621
b4ff3a36 622 u8 reserved_at_a0[0x10];
f91e6d89
EBE		 623 u8 atomic_size_qp[0x10];
624
b4ff3a36 625 u8 reserved_at_c0[0x10];
e281682b
SM		 626 u8 atomic_size_dc[0x10];
627
b4ff3a36 628 u8 reserved_at_e0[0x720];
e281682b
SM		 629};
630
631struct mlx5_ifc_odp_cap_bits {
b4ff3a36 632 u8 reserved_at_0[0x40];
e281682b
SM		 633
634 u8 sig[0x1];
b4ff3a36 635 u8 reserved_at_41[0x1f];
e281682b 636
b4ff3a36 637 u8 reserved_at_60[0x20];
e281682b
SM		 638
639 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
640
641 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
642
643 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
644
b4ff3a36 645 u8 reserved_at_e0[0x720];
e281682b
SM		 646};
647
3f0393a5
SG		 648struct mlx5_ifc_calc_op {
649 u8 reserved_at_0[0x10];
650 u8 reserved_at_10[0x9];
651 u8 op_swap_endianness[0x1];
652 u8 op_min[0x1];
653 u8 op_xor[0x1];
654 u8 op_or[0x1];
655 u8 op_and[0x1];
656 u8 op_max[0x1];
657 u8 op_add[0x1];
658};
659
660struct mlx5_ifc_vector_calc_cap_bits {
661 u8 calc_matrix[0x1];
662 u8 reserved_at_1[0x1f];
663 u8 reserved_at_20[0x8];
664 u8 max_vec_count[0x8];
665 u8 reserved_at_30[0xd];
666 u8 max_chunk_size[0x3];
667 struct mlx5_ifc_calc_op calc0;
668 struct mlx5_ifc_calc_op calc1;
669 struct mlx5_ifc_calc_op calc2;
670 struct mlx5_ifc_calc_op calc3;
671
672 u8 reserved_at_e0[0x720];
673};
674
e281682b
SM		 675enum {
676 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
677 MLX5_WQ_TYPE_CYCLIC = 0x1,
7d5e1423 678 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
e281682b
SM		 679};
680
681enum {
682 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
683 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
684};
685
686enum {
687 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
688 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
689 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
690 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
691 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
692};
693
694enum {
695 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
696 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
697 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
698 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
699 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
700 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
701};
702
703enum {
704 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
705 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
706};
707
708enum {
709 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
710 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
711 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
712};
713
714enum {
715 MLX5_CAP_PORT_TYPE_IB = 0x0,
716 MLX5_CAP_PORT_TYPE_ETH = 0x1,
d29b796a
EC		 717};
718
b775516b 719struct mlx5_ifc_cmd_hca_cap_bits {
b4ff3a36 720 u8 reserved_at_0[0x80];
b775516b
EC		 721
722 u8 log_max_srq_sz[0x8];
723 u8 log_max_qp_sz[0x8];
b4ff3a36 724 u8 reserved_at_90[0xb];
b775516b
EC		 725 u8 log_max_qp[0x5];
726
b4ff3a36 727 u8 reserved_at_a0[0xb];
e281682b 728 u8 log_max_srq[0x5];
b4ff3a36 729 u8 reserved_at_b0[0x10];
b775516b 730
b4ff3a36 731 u8 reserved_at_c0[0x8];
b775516b 732 u8 log_max_cq_sz[0x8];
b4ff3a36 733 u8 reserved_at_d0[0xb];
b775516b
EC		 734 u8 log_max_cq[0x5];
735
736 u8 log_max_eq_sz[0x8];
b4ff3a36 737 u8 reserved_at_e8[0x2];
b775516b 738 u8 log_max_mkey[0x6];
b4ff3a36 739 u8 reserved_at_f0[0xc];
b775516b
EC		 740 u8 log_max_eq[0x4];
741
742 u8 max_indirection[0x8];
b4ff3a36 743 u8 reserved_at_108[0x1];
b775516b 744 u8 log_max_mrw_sz[0x7];
b4ff3a36 745 u8 reserved_at_110[0x2];
b775516b 746 u8 log_max_bsf_list_size[0x6];
b4ff3a36 747 u8 reserved_at_118[0x2];
b775516b
EC		 748 u8 log_max_klm_list_size[0x6];
749
b4ff3a36 750 u8 reserved_at_120[0xa];
b775516b 751 u8 log_max_ra_req_dc[0x6];
b4ff3a36 752 u8 reserved_at_130[0xa];
b775516b
EC		 753 u8 log_max_ra_res_dc[0x6];
754
b4ff3a36 755 u8 reserved_at_140[0xa];
b775516b 756 u8 log_max_ra_req_qp[0x6];
b4ff3a36 757 u8 reserved_at_150[0xa];
b775516b
EC		 758 u8 log_max_ra_res_qp[0x6];
759
760 u8 pad_cap[0x1];
761 u8 cc_query_allowed[0x1];
762 u8 cc_modify_allowed[0x1];
b4ff3a36 763 u8 reserved_at_163[0xd];
e281682b 764 u8 gid_table_size[0x10];
b775516b 765
e281682b
SM		 766 u8 out_of_seq_cnt[0x1];
767 u8 vport_counters[0x1];
7486216b
SM		 768 u8 retransmission_q_counters[0x1];
769 u8 reserved_at_183[0x3];
b775516b
EC		 770 u8 max_qp_cnt[0xa];
771 u8 pkey_table_size[0x10];
772
e281682b
SM		 773 u8 vport_group_manager[0x1];
774 u8 vhca_group_manager[0x1];
775 u8 ib_virt[0x1];
776 u8 eth_virt[0x1];
b4ff3a36 777 u8 reserved_at_1a4[0x1];
e281682b
SM		 778 u8 ets[0x1];
779 u8 nic_flow_table[0x1];
54f0a411 780 u8 eswitch_flow_table[0x1];
e1c9c62b
TT		 781 u8 early_vf_enable[0x1];
782 u8 reserved_at_1a9[0x2];
b775516b 783 u8 local_ca_ack_delay[0x5];
7d5e1423
SM		 784 u8 reserved_at_1af[0x2];
785 u8 ports_check[0x1];
786 u8 reserved_at_1b2[0x1];
787 u8 disable_link_up[0x1];
788 u8 beacon_led[0x1];
e281682b 789 u8 port_type[0x2];
b775516b
EC		 790 u8 num_ports[0x8];
791
e1c9c62b 792 u8 reserved_at_1c0[0x3];
b775516b 793 u8 log_max_msg[0x5];
e1c9c62b 794 u8 reserved_at_1c8[0x4];
4f3961ee 795 u8 max_tc[0x4];
7486216b
SM		 796 u8 reserved_at_1d0[0x1];
797 u8 dcbx[0x1];
798 u8 reserved_at_1d2[0x4];
928cfe87
TT		 799 u8 rol_s[0x1];
800 u8 rol_g[0x1];
e1c9c62b 801 u8 reserved_at_1d8[0x1];
928cfe87
TT		 802 u8 wol_s[0x1];
803 u8 wol_g[0x1];
804 u8 wol_a[0x1];
805 u8 wol_b[0x1];
806 u8 wol_m[0x1];
807 u8 wol_u[0x1];
808 u8 wol_p[0x1];
b775516b
EC		 809
810 u8 stat_rate_support[0x10];
e1c9c62b 811 u8 reserved_at_1f0[0xc];
e281682b 812 u8 cqe_version[0x4];
b775516b 813
e281682b 814 u8 compact_address_vector[0x1];
7d5e1423
SM		 815 u8 striding_rq[0x1];
816 u8 reserved_at_201[0x2];
1015c2e8 817 u8 ipoib_basic_offloads[0x1];
e1c9c62b 818 u8 reserved_at_205[0xa];
e281682b 819 u8 drain_sigerr[0x1];
b775516b
EC		 820 u8 cmdif_checksum[0x2];
821 u8 sigerr_cqe[0x1];
e1c9c62b 822 u8 reserved_at_213[0x1];
b775516b
EC		 823 u8 wq_signature[0x1];
824 u8 sctr_data_cqe[0x1];
e1c9c62b 825 u8 reserved_at_216[0x1];
b775516b
EC		 826 u8 sho[0x1];
827 u8 tph[0x1];
828 u8 rf[0x1];
e281682b 829 u8 dct[0x1];
7486216b 830 u8 qos[0x1];
e281682b 831 u8 eth_net_offloads[0x1];
b775516b
EC		 832 u8 roce[0x1];
833 u8 atomic[0x1];
e1c9c62b 834 u8 reserved_at_21f[0x1];
b775516b
EC		 835
836 u8 cq_oi[0x1];
837 u8 cq_resize[0x1];
838 u8 cq_moderation[0x1];
e1c9c62b 839 u8 reserved_at_223[0x3];
e281682b 840 u8 cq_eq_remap[0x1];
b775516b
EC		 841 u8 pg[0x1];
842 u8 block_lb_mc[0x1];
e1c9c62b 843 u8 reserved_at_229[0x1];
e281682b 844 u8 scqe_break_moderation[0x1];
7d5e1423 845 u8 cq_period_start_from_cqe[0x1];
b775516b 846 u8 cd[0x1];
e1c9c62b 847 u8 reserved_at_22d[0x1];
b775516b 848 u8 apm[0x1];
3f0393a5 849 u8 vector_calc[0x1];
7d5e1423 850 u8 umr_ptr_rlky[0x1];
d2370e0a 851 u8 imaicl[0x1];
e1c9c62b 852 u8 reserved_at_232[0x4];
b775516b
EC		 853 u8 qkv[0x1];
854 u8 pkv[0x1];
b11a4f9c
HE		 855 u8 set_deth_sqpn[0x1];
856 u8 reserved_at_239[0x3];
b775516b
EC		 857 u8 xrc[0x1];
858 u8 ud[0x1];
859 u8 uc[0x1];
860 u8 rc[0x1];
861
e1c9c62b 862 u8 reserved_at_240[0xa];
b775516b 863 u8 uar_sz[0x6];
e1c9c62b 864 u8 reserved_at_250[0x8];
b775516b
EC		 865 u8 log_pg_sz[0x8];
866
867 u8 bf[0x1];
e1c9c62b 868 u8 reserved_at_261[0x1];
e281682b 869 u8 pad_tx_eth_packet[0x1];
e1c9c62b 870 u8 reserved_at_263[0x8];
b775516b 871 u8 log_bf_reg_size[0x5];
e1c9c62b 872 u8 reserved_at_270[0x10];
b775516b 873
e1c9c62b 874 u8 reserved_at_280[0x10];
b775516b
EC		 875 u8 max_wqe_sz_sq[0x10];
876
e1c9c62b 877 u8 reserved_at_2a0[0x10];
b775516b
EC		 878 u8 max_wqe_sz_rq[0x10];
879
e1c9c62b 880 u8 reserved_at_2c0[0x10];
b775516b
EC		 881 u8 max_wqe_sz_sq_dc[0x10];
882
e1c9c62b 883 u8 reserved_at_2e0[0x7];
b775516b
EC		 884 u8 max_qp_mcg[0x19];
885
e1c9c62b 886 u8 reserved_at_300[0x18];
b775516b
EC		 887 u8 log_max_mcg[0x8];
888
e1c9c62b 889 u8 reserved_at_320[0x3];
e281682b 890 u8 log_max_transport_domain[0x5];
e1c9c62b 891 u8 reserved_at_328[0x3];
b775516b 892 u8 log_max_pd[0x5];
e1c9c62b 893 u8 reserved_at_330[0xb];
b775516b
EC		 894 u8 log_max_xrcd[0x5];
895
a351a1b0
AV		 896 u8 reserved_at_340[0x8];
897 u8 log_max_flow_counter_bulk[0x8];
898 u8 max_flow_counter[0x10];
899
b775516b 900
e1c9c62b 901 u8 reserved_at_360[0x3];
b775516b 902 u8 log_max_rq[0x5];
e1c9c62b 903 u8 reserved_at_368[0x3];
b775516b 904 u8 log_max_sq[0x5];
e1c9c62b 905 u8 reserved_at_370[0x3];
b775516b 906 u8 log_max_tir[0x5];
e1c9c62b 907 u8 reserved_at_378[0x3];
b775516b
EC		 908 u8 log_max_tis[0x5];
909
e281682b 910 u8 basic_cyclic_rcv_wqe[0x1];
e1c9c62b 911 u8 reserved_at_381[0x2];
e281682b 912 u8 log_max_rmp[0x5];
e1c9c62b 913 u8 reserved_at_388[0x3];
e281682b 914 u8 log_max_rqt[0x5];
e1c9c62b 915 u8 reserved_at_390[0x3];
e281682b 916 u8 log_max_rqt_size[0x5];
e1c9c62b 917 u8 reserved_at_398[0x3];
b775516b
EC		 918 u8 log_max_tis_per_sq[0x5];
919
e1c9c62b 920 u8 reserved_at_3a0[0x3];
e281682b 921 u8 log_max_stride_sz_rq[0x5];
e1c9c62b 922 u8 reserved_at_3a8[0x3];
e281682b 923 u8 log_min_stride_sz_rq[0x5];
e1c9c62b 924 u8 reserved_at_3b0[0x3];
e281682b 925 u8 log_max_stride_sz_sq[0x5];
e1c9c62b 926 u8 reserved_at_3b8[0x3];
e281682b
SM		 927 u8 log_min_stride_sz_sq[0x5];
928
e1c9c62b 929 u8 reserved_at_3c0[0x1b];
e281682b
SM		 930 u8 log_max_wq_sz[0x5];
931
54f0a411 932 u8 nic_vport_change_event[0x1];
e1c9c62b 933 u8 reserved_at_3e1[0xa];
54f0a411 934 u8 log_max_vlan_list[0x5];
e1c9c62b 935 u8 reserved_at_3f0[0x3];
54f0a411 936 u8 log_max_current_mc_list[0x5];
e1c9c62b 937 u8 reserved_at_3f8[0x3];
54f0a411
SM		 938 u8 log_max_current_uc_list[0x5];
939
e1c9c62b 940 u8 reserved_at_400[0x80];
54f0a411 941
e1c9c62b 942 u8 reserved_at_480[0x3];
e281682b 943 u8 log_max_l2_table[0x5];
e1c9c62b 944 u8 reserved_at_488[0x8];
b775516b
EC		 945 u8 log_uar_page_sz[0x10];
946
e1c9c62b 947 u8 reserved_at_4a0[0x20];
048ccca8 948 u8 device_frequency_mhz[0x20];
b0844444 949 u8 device_frequency_khz[0x20];
e1c9c62b
TT		 950
951 u8 reserved_at_500[0x80];
952
953 u8 reserved_at_580[0x3f];
7d5e1423 954 u8 cqe_compression[0x1];
b775516b 955
7d5e1423
SM		 956 u8 cqe_compression_timeout[0x10];
957 u8 cqe_compression_max_num[0x10];
b775516b 958
7486216b
SM		 959 u8 reserved_at_5e0[0x10];
960 u8 tag_matching[0x1];
961 u8 rndv_offload_rc[0x1];
962 u8 rndv_offload_dc[0x1];
963 u8 log_tag_matching_list_sz[0x5];
964 u8 reserved_at_5e8[0x3];
965 u8 log_max_xrq[0x5];
966
967 u8 reserved_at_5f0[0x200];
b775516b
EC		 968};
969
81848731
SM		 970enum mlx5_flow_destination_type {
971 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
972 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
973 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
bd5251db
AV		 974
975 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
e281682b 976};
b775516b 977
e281682b
SM		 978struct mlx5_ifc_dest_format_struct_bits {
979 u8 destination_type[0x8];
980 u8 destination_id[0x18];
b775516b 981
b4ff3a36 982 u8 reserved_at_20[0x20];
e281682b
SM		 983};
984
9dc0b289 985struct mlx5_ifc_flow_counter_list_bits {
a351a1b0
AV		 986 u8 clear[0x1];
987 u8 num_of_counters[0xf];
9dc0b289
AV		 988 u8 flow_counter_id[0x10];
989
990 u8 reserved_at_20[0x20];
991};
992
993union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
994 struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
995 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
996 u8 reserved_at_0[0x40];
997};
998
e281682b
SM		 999struct mlx5_ifc_fte_match_param_bits {
1000 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1001
1002 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1003
1004 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
b775516b 1005
b4ff3a36 1006 u8 reserved_at_600[0xa00];
b775516b
EC		 1007};
1008
e281682b
SM		 1009enum {
1010 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1011 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1012 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1013 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1014 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1015};
b775516b 1016
e281682b
SM		 1017struct mlx5_ifc_rx_hash_field_select_bits {
1018 u8 l3_prot_type[0x1];
1019 u8 l4_prot_type[0x1];
1020 u8 selected_fields[0x1e];
1021};
b775516b 1022
e281682b
SM		 1023enum {
1024 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
1025 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
b775516b
EC		 1026};
1027
e281682b
SM		 1028enum {
1029 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
1030 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
1031};
1032
1033struct mlx5_ifc_wq_bits {
1034 u8 wq_type[0x4];
1035 u8 wq_signature[0x1];
1036 u8 end_padding_mode[0x2];
1037 u8 cd_slave[0x1];
b4ff3a36 1038 u8 reserved_at_8[0x18];
b775516b 1039
e281682b
SM		 1040 u8 hds_skip_first_sge[0x1];
1041 u8 log2_hds_buf_size[0x3];
b4ff3a36 1042 u8 reserved_at_24[0x7];
e281682b
SM		 1043 u8 page_offset[0x5];
1044 u8 lwm[0x10];
b775516b 1045
b4ff3a36 1046 u8 reserved_at_40[0x8];
e281682b
SM		 1047 u8 pd[0x18];
1048
b4ff3a36 1049 u8 reserved_at_60[0x8];
e281682b
SM		 1050 u8 uar_page[0x18];
1051
1052 u8 dbr_addr[0x40];
1053
1054 u8 hw_counter[0x20];
1055
1056 u8 sw_counter[0x20];
1057
b4ff3a36 1058 u8 reserved_at_100[0xc];
e281682b 1059 u8 log_wq_stride[0x4];
b4ff3a36 1060 u8 reserved_at_110[0x3];
e281682b 1061 u8 log_wq_pg_sz[0x5];
b4ff3a36 1062 u8 reserved_at_118[0x3];
e281682b
SM		 1063 u8 log_wq_sz[0x5];
1064
7d5e1423
SM		 1065 u8 reserved_at_120[0x15];
1066 u8 log_wqe_num_of_strides[0x3];
1067 u8 two_byte_shift_en[0x1];
1068 u8 reserved_at_139[0x4];
1069 u8 log_wqe_stride_size[0x3];
1070
1071 u8 reserved_at_140[0x4c0];
b775516b 1072
e281682b 1073 struct mlx5_ifc_cmd_pas_bits pas[0];
b775516b
EC		 1074};
1075
e281682b 1076struct mlx5_ifc_rq_num_bits {
b4ff3a36 1077 u8 reserved_at_0[0x8];
e281682b
SM		 1078 u8 rq_num[0x18];
1079};
b775516b 1080
e281682b 1081struct mlx5_ifc_mac_address_layout_bits {
b4ff3a36 1082 u8 reserved_at_0[0x10];
e281682b 1083 u8 mac_addr_47_32[0x10];
b775516b 1084
e281682b
SM		 1085 u8 mac_addr_31_0[0x20];
1086};
1087
c0046cf7 1088struct mlx5_ifc_vlan_layout_bits {
b4ff3a36 1089 u8 reserved_at_0[0x14];
c0046cf7
SM		 1090 u8 vlan[0x0c];
1091
b4ff3a36 1092 u8 reserved_at_20[0x20];
c0046cf7
SM		 1093};
1094
e281682b 1095struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
b4ff3a36 1096 u8 reserved_at_0[0xa0];
e281682b
SM		 1097
1098 u8 min_time_between_cnps[0x20];
1099
b4ff3a36 1100 u8 reserved_at_c0[0x12];
e281682b 1101 u8 cnp_dscp[0x6];
b4ff3a36 1102 u8 reserved_at_d8[0x5];
e281682b
SM		 1103 u8 cnp_802p_prio[0x3];
1104
b4ff3a36 1105 u8 reserved_at_e0[0x720];
e281682b
SM		 1106};
1107
1108struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
b4ff3a36 1109 u8 reserved_at_0[0x60];
e281682b 1110
b4ff3a36 1111 u8 reserved_at_60[0x4];
e281682b 1112 u8 clamp_tgt_rate[0x1];
b4ff3a36 1113 u8 reserved_at_65[0x3];
e281682b 1114 u8 clamp_tgt_rate_after_time_inc[0x1];
b4ff3a36 1115 u8 reserved_at_69[0x17];
e281682b 1116
b4ff3a36 1117 u8 reserved_at_80[0x20];
e281682b
SM		 1118
1119 u8 rpg_time_reset[0x20];
1120
1121 u8 rpg_byte_reset[0x20];
1122
1123 u8 rpg_threshold[0x20];
1124
1125 u8 rpg_max_rate[0x20];
1126
1127 u8 rpg_ai_rate[0x20];
1128
1129 u8 rpg_hai_rate[0x20];
1130
1131 u8 rpg_gd[0x20];
1132
1133 u8 rpg_min_dec_fac[0x20];
1134
1135 u8 rpg_min_rate[0x20];
1136
b4ff3a36 1137 u8 reserved_at_1c0[0xe0];
e281682b
SM		 1138
1139 u8 rate_to_set_on_first_cnp[0x20];
1140
1141 u8 dce_tcp_g[0x20];
1142
1143 u8 dce_tcp_rtt[0x20];
1144
1145 u8 rate_reduce_monitor_period[0x20];
1146
b4ff3a36 1147 u8 reserved_at_320[0x20];
e281682b
SM		 1148
1149 u8 initial_alpha_value[0x20];
1150
b4ff3a36 1151 u8 reserved_at_360[0x4a0];
e281682b
SM		 1152};
1153
1154struct mlx5_ifc_cong_control_802_1qau_rp_bits {
b4ff3a36 1155 u8 reserved_at_0[0x80];
e281682b
SM		 1156
1157 u8 rppp_max_rps[0x20];
1158
1159 u8 rpg_time_reset[0x20];
1160
1161 u8 rpg_byte_reset[0x20];
1162
1163 u8 rpg_threshold[0x20];
1164
1165 u8 rpg_max_rate[0x20];
1166
1167 u8 rpg_ai_rate[0x20];
1168
1169 u8 rpg_hai_rate[0x20];
1170
1171 u8 rpg_gd[0x20];
1172
1173 u8 rpg_min_dec_fac[0x20];
1174
1175 u8 rpg_min_rate[0x20];
1176
b4ff3a36 1177 u8 reserved_at_1c0[0x640];
e281682b
SM		 1178};
1179
1180enum {
1181 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1182 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1183 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1184};
1185
1186struct mlx5_ifc_resize_field_select_bits {
1187 u8 resize_field_select[0x20];
1188};
1189
1190enum {
1191 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1192 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1193 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1194 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1195};
1196
1197struct mlx5_ifc_modify_field_select_bits {
1198 u8 modify_field_select[0x20];
1199};
1200
1201struct mlx5_ifc_field_select_r_roce_np_bits {
1202 u8 field_select_r_roce_np[0x20];
1203};
1204
1205struct mlx5_ifc_field_select_r_roce_rp_bits {
1206 u8 field_select_r_roce_rp[0x20];
1207};
1208
1209enum {
1210 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1211 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1212 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1213 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1214 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1215 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1216 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1217 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1218 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1219 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1220};
1221
1222struct mlx5_ifc_field_select_802_1qau_rp_bits {
1223 u8 field_select_8021qaurp[0x20];
1224};
1225
1226struct mlx5_ifc_phys_layer_cntrs_bits {
1227 u8 time_since_last_clear_high[0x20];
1228
1229 u8 time_since_last_clear_low[0x20];
1230
1231 u8 symbol_errors_high[0x20];
1232
1233 u8 symbol_errors_low[0x20];
1234
1235 u8 sync_headers_errors_high[0x20];
1236
1237 u8 sync_headers_errors_low[0x20];
1238
1239 u8 edpl_bip_errors_lane0_high[0x20];
1240
1241 u8 edpl_bip_errors_lane0_low[0x20];
1242
1243 u8 edpl_bip_errors_lane1_high[0x20];
1244
1245 u8 edpl_bip_errors_lane1_low[0x20];
1246
1247 u8 edpl_bip_errors_lane2_high[0x20];
1248
1249 u8 edpl_bip_errors_lane2_low[0x20];
1250
1251 u8 edpl_bip_errors_lane3_high[0x20];
1252
1253 u8 edpl_bip_errors_lane3_low[0x20];
1254
1255 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1256
1257 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1258
1259 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1260
1261 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1262
1263 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1264
1265 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1266
1267 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1268
1269 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1270
1271 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1272
1273 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1274
1275 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1276
1277 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1278
1279 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1280
1281 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1282
1283 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1284
1285 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1286
1287 u8 rs_fec_corrected_blocks_high[0x20];
1288
1289 u8 rs_fec_corrected_blocks_low[0x20];
1290
1291 u8 rs_fec_uncorrectable_blocks_high[0x20];
1292
1293 u8 rs_fec_uncorrectable_blocks_low[0x20];
1294
1295 u8 rs_fec_no_errors_blocks_high[0x20];
1296
1297 u8 rs_fec_no_errors_blocks_low[0x20];
1298
1299 u8 rs_fec_single_error_blocks_high[0x20];
1300
1301 u8 rs_fec_single_error_blocks_low[0x20];
1302
1303 u8 rs_fec_corrected_symbols_total_high[0x20];
1304
1305 u8 rs_fec_corrected_symbols_total_low[0x20];
1306
1307 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1308
1309 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1310
1311 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1312
1313 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1314
1315 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1316
1317 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1318
1319 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1320
1321 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1322
1323 u8 link_down_events[0x20];
1324
1325 u8 successful_recovery_events[0x20];
1326
b4ff3a36 1327 u8 reserved_at_640[0x180];
e281682b
SM		 1328};
1329
1c64bf6f
MY		 1330struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1331 u8 symbol_error_counter[0x10];
1332
1333 u8 link_error_recovery_counter[0x8];
1334
1335 u8 link_downed_counter[0x8];
1336
1337 u8 port_rcv_errors[0x10];
1338
1339 u8 port_rcv_remote_physical_errors[0x10];
1340
1341 u8 port_rcv_switch_relay_errors[0x10];
1342
1343 u8 port_xmit_discards[0x10];
1344
1345 u8 port_xmit_constraint_errors[0x8];
1346
1347 u8 port_rcv_constraint_errors[0x8];
1348
1349 u8 reserved_at_70[0x8];
1350
1351 u8 link_overrun_errors[0x8];
1352
1353 u8 reserved_at_80[0x10];
1354
1355 u8 vl_15_dropped[0x10];
1356
1357 u8 reserved_at_a0[0xa0];
1358};
1359
e281682b
SM		 1360struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1361 u8 transmit_queue_high[0x20];
1362
1363 u8 transmit_queue_low[0x20];
1364
b4ff3a36 1365 u8 reserved_at_40[0x780];
e281682b
SM		 1366};
1367
1368struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1369 u8 rx_octets_high[0x20];
1370
1371 u8 rx_octets_low[0x20];
1372
b4ff3a36 1373 u8 reserved_at_40[0xc0];
e281682b
SM		 1374
1375 u8 rx_frames_high[0x20];
1376
1377 u8 rx_frames_low[0x20];
1378
1379 u8 tx_octets_high[0x20];
1380
1381 u8 tx_octets_low[0x20];
1382
b4ff3a36 1383 u8 reserved_at_180[0xc0];
e281682b
SM		 1384
1385 u8 tx_frames_high[0x20];
1386
1387 u8 tx_frames_low[0x20];
1388
1389 u8 rx_pause_high[0x20];
1390
1391 u8 rx_pause_low[0x20];
1392
1393 u8 rx_pause_duration_high[0x20];
1394
1395 u8 rx_pause_duration_low[0x20];
1396
1397 u8 tx_pause_high[0x20];
1398
1399 u8 tx_pause_low[0x20];
1400
1401 u8 tx_pause_duration_high[0x20];
1402
1403 u8 tx_pause_duration_low[0x20];
1404
1405 u8 rx_pause_transition_high[0x20];
1406
1407 u8 rx_pause_transition_low[0x20];
1408
b4ff3a36 1409 u8 reserved_at_3c0[0x400];
e281682b
SM		 1410};
1411
1412struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1413 u8 port_transmit_wait_high[0x20];
1414
1415 u8 port_transmit_wait_low[0x20];
1416
b4ff3a36 1417 u8 reserved_at_40[0x780];
e281682b
SM		 1418};
1419
1420struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1421 u8 dot3stats_alignment_errors_high[0x20];
1422
1423 u8 dot3stats_alignment_errors_low[0x20];
1424
1425 u8 dot3stats_fcs_errors_high[0x20];
1426
1427 u8 dot3stats_fcs_errors_low[0x20];
1428
1429 u8 dot3stats_single_collision_frames_high[0x20];
1430
1431 u8 dot3stats_single_collision_frames_low[0x20];
1432
1433 u8 dot3stats_multiple_collision_frames_high[0x20];
1434
1435 u8 dot3stats_multiple_collision_frames_low[0x20];
1436
1437 u8 dot3stats_sqe_test_errors_high[0x20];
1438
1439 u8 dot3stats_sqe_test_errors_low[0x20];
1440
1441 u8 dot3stats_deferred_transmissions_high[0x20];
1442
1443 u8 dot3stats_deferred_transmissions_low[0x20];
1444
1445 u8 dot3stats_late_collisions_high[0x20];
1446
1447 u8 dot3stats_late_collisions_low[0x20];
1448
1449 u8 dot3stats_excessive_collisions_high[0x20];
1450
1451 u8 dot3stats_excessive_collisions_low[0x20];
1452
1453 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1454
1455 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1456
1457 u8 dot3stats_carrier_sense_errors_high[0x20];
1458
1459 u8 dot3stats_carrier_sense_errors_low[0x20];
1460
1461 u8 dot3stats_frame_too_longs_high[0x20];
1462
1463 u8 dot3stats_frame_too_longs_low[0x20];
1464
1465 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1466
1467 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1468
1469 u8 dot3stats_symbol_errors_high[0x20];
1470
1471 u8 dot3stats_symbol_errors_low[0x20];
1472
1473 u8 dot3control_in_unknown_opcodes_high[0x20];
1474
1475 u8 dot3control_in_unknown_opcodes_low[0x20];
1476
1477 u8 dot3in_pause_frames_high[0x20];
1478
1479 u8 dot3in_pause_frames_low[0x20];
1480
1481 u8 dot3out_pause_frames_high[0x20];
1482
1483 u8 dot3out_pause_frames_low[0x20];
1484
b4ff3a36 1485 u8 reserved_at_400[0x3c0];
e281682b
SM		 1486};
1487
1488struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1489 u8 ether_stats_drop_events_high[0x20];
1490
1491 u8 ether_stats_drop_events_low[0x20];
1492
1493 u8 ether_stats_octets_high[0x20];
1494
1495 u8 ether_stats_octets_low[0x20];
1496
1497 u8 ether_stats_pkts_high[0x20];
1498
1499 u8 ether_stats_pkts_low[0x20];
1500
1501 u8 ether_stats_broadcast_pkts_high[0x20];
1502
1503 u8 ether_stats_broadcast_pkts_low[0x20];
1504
1505 u8 ether_stats_multicast_pkts_high[0x20];
1506
1507 u8 ether_stats_multicast_pkts_low[0x20];
1508
1509 u8 ether_stats_crc_align_errors_high[0x20];
1510
1511 u8 ether_stats_crc_align_errors_low[0x20];
1512
1513 u8 ether_stats_undersize_pkts_high[0x20];
1514
1515 u8 ether_stats_undersize_pkts_low[0x20];
1516
1517 u8 ether_stats_oversize_pkts_high[0x20];
1518
1519 u8 ether_stats_oversize_pkts_low[0x20];
1520
1521 u8 ether_stats_fragments_high[0x20];
1522
1523 u8 ether_stats_fragments_low[0x20];
1524
1525 u8 ether_stats_jabbers_high[0x20];
1526
1527 u8 ether_stats_jabbers_low[0x20];
1528
1529 u8 ether_stats_collisions_high[0x20];
1530
1531 u8 ether_stats_collisions_low[0x20];
1532
1533 u8 ether_stats_pkts64octets_high[0x20];
1534
1535 u8 ether_stats_pkts64octets_low[0x20];
1536
1537 u8 ether_stats_pkts65to127octets_high[0x20];
1538
1539 u8 ether_stats_pkts65to127octets_low[0x20];
1540
1541 u8 ether_stats_pkts128to255octets_high[0x20];
1542
1543 u8 ether_stats_pkts128to255octets_low[0x20];
1544
1545 u8 ether_stats_pkts256to511octets_high[0x20];
1546
1547 u8 ether_stats_pkts256to511octets_low[0x20];
1548
1549 u8 ether_stats_pkts512to1023octets_high[0x20];
1550
1551 u8 ether_stats_pkts512to1023octets_low[0x20];
1552
1553 u8 ether_stats_pkts1024to1518octets_high[0x20];
1554
1555 u8 ether_stats_pkts1024to1518octets_low[0x20];
1556
1557 u8 ether_stats_pkts1519to2047octets_high[0x20];
1558
1559 u8 ether_stats_pkts1519to2047octets_low[0x20];
1560
1561 u8 ether_stats_pkts2048to4095octets_high[0x20];
1562
1563 u8 ether_stats_pkts2048to4095octets_low[0x20];
1564
1565 u8 ether_stats_pkts4096to8191octets_high[0x20];
1566
1567 u8 ether_stats_pkts4096to8191octets_low[0x20];
1568
1569 u8 ether_stats_pkts8192to10239octets_high[0x20];
1570
1571 u8 ether_stats_pkts8192to10239octets_low[0x20];
1572
b4ff3a36 1573 u8 reserved_at_540[0x280];
e281682b
SM		 1574};
1575
1576struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1577 u8 if_in_octets_high[0x20];
1578
1579 u8 if_in_octets_low[0x20];
1580
1581 u8 if_in_ucast_pkts_high[0x20];
1582
1583 u8 if_in_ucast_pkts_low[0x20];
1584
1585 u8 if_in_discards_high[0x20];
1586
1587 u8 if_in_discards_low[0x20];
1588
1589 u8 if_in_errors_high[0x20];
1590
1591 u8 if_in_errors_low[0x20];
1592
1593 u8 if_in_unknown_protos_high[0x20];
1594
1595 u8 if_in_unknown_protos_low[0x20];
1596
1597 u8 if_out_octets_high[0x20];
1598
1599 u8 if_out_octets_low[0x20];
1600
1601 u8 if_out_ucast_pkts_high[0x20];
1602
1603 u8 if_out_ucast_pkts_low[0x20];
1604
1605 u8 if_out_discards_high[0x20];
1606
1607 u8 if_out_discards_low[0x20];
1608
1609 u8 if_out_errors_high[0x20];
1610
1611 u8 if_out_errors_low[0x20];
1612
1613 u8 if_in_multicast_pkts_high[0x20];
1614
1615 u8 if_in_multicast_pkts_low[0x20];
1616
1617 u8 if_in_broadcast_pkts_high[0x20];
1618
1619 u8 if_in_broadcast_pkts_low[0x20];
1620
1621 u8 if_out_multicast_pkts_high[0x20];
1622
1623 u8 if_out_multicast_pkts_low[0x20];
1624
1625 u8 if_out_broadcast_pkts_high[0x20];
1626
1627 u8 if_out_broadcast_pkts_low[0x20];
1628
b4ff3a36 1629 u8 reserved_at_340[0x480];
e281682b
SM		 1630};
1631
1632struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1633 u8 a_frames_transmitted_ok_high[0x20];
1634
1635 u8 a_frames_transmitted_ok_low[0x20];
1636
1637 u8 a_frames_received_ok_high[0x20];
1638
1639 u8 a_frames_received_ok_low[0x20];
1640
1641 u8 a_frame_check_sequence_errors_high[0x20];
1642
1643 u8 a_frame_check_sequence_errors_low[0x20];
1644
1645 u8 a_alignment_errors_high[0x20];
1646
1647 u8 a_alignment_errors_low[0x20];
1648
1649 u8 a_octets_transmitted_ok_high[0x20];
1650
1651 u8 a_octets_transmitted_ok_low[0x20];
1652
1653 u8 a_octets_received_ok_high[0x20];
1654
1655 u8 a_octets_received_ok_low[0x20];
1656
1657 u8 a_multicast_frames_xmitted_ok_high[0x20];
1658
1659 u8 a_multicast_frames_xmitted_ok_low[0x20];
1660
1661 u8 a_broadcast_frames_xmitted_ok_high[0x20];
1662
1663 u8 a_broadcast_frames_xmitted_ok_low[0x20];
1664
1665 u8 a_multicast_frames_received_ok_high[0x20];
1666
1667 u8 a_multicast_frames_received_ok_low[0x20];
1668
1669 u8 a_broadcast_frames_received_ok_high[0x20];
1670
1671 u8 a_broadcast_frames_received_ok_low[0x20];
1672
1673 u8 a_in_range_length_errors_high[0x20];
1674
1675 u8 a_in_range_length_errors_low[0x20];
1676
1677 u8 a_out_of_range_length_field_high[0x20];
1678
1679 u8 a_out_of_range_length_field_low[0x20];
1680
1681 u8 a_frame_too_long_errors_high[0x20];
1682
1683 u8 a_frame_too_long_errors_low[0x20];
1684
1685 u8 a_symbol_error_during_carrier_high[0x20];
1686
1687 u8 a_symbol_error_during_carrier_low[0x20];
1688
1689 u8 a_mac_control_frames_transmitted_high[0x20];
1690
1691 u8 a_mac_control_frames_transmitted_low[0x20];
1692
1693 u8 a_mac_control_frames_received_high[0x20];
1694
1695 u8 a_mac_control_frames_received_low[0x20];
1696
1697 u8 a_unsupported_opcodes_received_high[0x20];
1698
1699 u8 a_unsupported_opcodes_received_low[0x20];
1700
1701 u8 a_pause_mac_ctrl_frames_received_high[0x20];
1702
1703 u8 a_pause_mac_ctrl_frames_received_low[0x20];
1704
1705 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
1706
1707 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
1708
b4ff3a36 1709 u8 reserved_at_4c0[0x300];
e281682b
SM		 1710};
1711
1712struct mlx5_ifc_cmd_inter_comp_event_bits {
1713 u8 command_completion_vector[0x20];
1714
b4ff3a36 1715 u8 reserved_at_20[0xc0];
e281682b
SM		 1716};
1717
1718struct mlx5_ifc_stall_vl_event_bits {
b4ff3a36 1719 u8 reserved_at_0[0x18];
e281682b 1720 u8 port_num[0x1];
b4ff3a36 1721 u8 reserved_at_19[0x3];
e281682b
SM		 1722 u8 vl[0x4];
1723
b4ff3a36 1724 u8 reserved_at_20[0xa0];
e281682b
SM		 1725};
1726
1727struct mlx5_ifc_db_bf_congestion_event_bits {
1728 u8 event_subtype[0x8];
b4ff3a36 1729 u8 reserved_at_8[0x8];
e281682b 1730 u8 congestion_level[0x8];
b4ff3a36 1731 u8 reserved_at_18[0x8];
e281682b 1732
b4ff3a36 1733 u8 reserved_at_20[0xa0];
e281682b
SM		 1734};
1735
1736struct mlx5_ifc_gpio_event_bits {
b4ff3a36 1737 u8 reserved_at_0[0x60];
e281682b
SM		 1738
1739 u8 gpio_event_hi[0x20];
1740
1741 u8 gpio_event_lo[0x20];
1742
b4ff3a36 1743 u8 reserved_at_a0[0x40];
e281682b
SM		 1744};
1745
1746struct mlx5_ifc_port_state_change_event_bits {
b4ff3a36 1747 u8 reserved_at_0[0x40];
e281682b
SM		 1748
1749 u8 port_num[0x4];
b4ff3a36 1750 u8 reserved_at_44[0x1c];
e281682b 1751
b4ff3a36 1752 u8 reserved_at_60[0x80];
e281682b
SM		 1753};
1754
1755struct mlx5_ifc_dropped_packet_logged_bits {
b4ff3a36 1756 u8 reserved_at_0[0xe0];
e281682b
SM		 1757};
1758
1759enum {
1760 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
1761 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
1762};
1763
1764struct mlx5_ifc_cq_error_bits {
b4ff3a36 1765 u8 reserved_at_0[0x8];
e281682b
SM		 1766 u8 cqn[0x18];
1767
b4ff3a36 1768 u8 reserved_at_20[0x20];
e281682b 1769
b4ff3a36 1770 u8 reserved_at_40[0x18];
e281682b
SM		 1771 u8 syndrome[0x8];
1772
b4ff3a36 1773 u8 reserved_at_60[0x80];
e281682b
SM		 1774};
1775
1776struct mlx5_ifc_rdma_page_fault_event_bits {
1777 u8 bytes_committed[0x20];
1778
1779 u8 r_key[0x20];
1780
b4ff3a36 1781 u8 reserved_at_40[0x10];
e281682b
SM		 1782 u8 packet_len[0x10];
1783
1784 u8 rdma_op_len[0x20];
1785
1786 u8 rdma_va[0x40];
1787
b4ff3a36 1788 u8 reserved_at_c0[0x5];
e281682b
SM		 1789 u8 rdma[0x1];
1790 u8 write[0x1];
1791 u8 requestor[0x1];
1792 u8 qp_number[0x18];
1793};
1794
1795struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1796 u8 bytes_committed[0x20];
1797
b4ff3a36 1798 u8 reserved_at_20[0x10];
e281682b
SM		 1799 u8 wqe_index[0x10];
1800
b4ff3a36 1801 u8 reserved_at_40[0x10];
e281682b
SM		 1802 u8 len[0x10];
1803
b4ff3a36 1804 u8 reserved_at_60[0x60];
e281682b 1805
b4ff3a36 1806 u8 reserved_at_c0[0x5];
e281682b
SM		 1807 u8 rdma[0x1];
1808 u8 write_read[0x1];
1809 u8 requestor[0x1];
1810 u8 qpn[0x18];
1811};
1812
1813struct mlx5_ifc_qp_events_bits {
b4ff3a36 1814 u8 reserved_at_0[0xa0];
e281682b
SM		 1815
1816 u8 type[0x8];
b4ff3a36 1817 u8 reserved_at_a8[0x18];
e281682b 1818
b4ff3a36 1819 u8 reserved_at_c0[0x8];
e281682b
SM		 1820 u8 qpn_rqn_sqn[0x18];
1821};
1822
1823struct mlx5_ifc_dct_events_bits {
b4ff3a36 1824 u8 reserved_at_0[0xc0];
e281682b 1825
b4ff3a36 1826 u8 reserved_at_c0[0x8];
e281682b
SM		 1827 u8 dct_number[0x18];
1828};
1829
1830struct mlx5_ifc_comp_event_bits {
b4ff3a36 1831 u8 reserved_at_0[0xc0];
e281682b 1832
b4ff3a36 1833 u8 reserved_at_c0[0x8];
e281682b
SM		 1834 u8 cq_number[0x18];
1835};
1836
1837enum {
1838 MLX5_QPC_STATE_RST = 0x0,
1839 MLX5_QPC_STATE_INIT = 0x1,
1840 MLX5_QPC_STATE_RTR = 0x2,
1841 MLX5_QPC_STATE_RTS = 0x3,
1842 MLX5_QPC_STATE_SQER = 0x4,
1843 MLX5_QPC_STATE_ERR = 0x6,
1844 MLX5_QPC_STATE_SQD = 0x7,
1845 MLX5_QPC_STATE_SUSPENDED = 0x9,
1846};
1847
1848enum {
1849 MLX5_QPC_ST_RC = 0x0,
1850 MLX5_QPC_ST_UC = 0x1,
1851 MLX5_QPC_ST_UD = 0x2,
1852 MLX5_QPC_ST_XRC = 0x3,
1853 MLX5_QPC_ST_DCI = 0x5,
1854 MLX5_QPC_ST_QP0 = 0x7,
1855 MLX5_QPC_ST_QP1 = 0x8,
1856 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
1857 MLX5_QPC_ST_REG_UMR = 0xc,
1858};
1859
1860enum {
1861 MLX5_QPC_PM_STATE_ARMED = 0x0,
1862 MLX5_QPC_PM_STATE_REARM = 0x1,
1863 MLX5_QPC_PM_STATE_RESERVED = 0x2,
1864 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
1865};
1866
1867enum {
1868 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
1869 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
1870};
1871
1872enum {
1873 MLX5_QPC_MTU_256_BYTES = 0x1,
1874 MLX5_QPC_MTU_512_BYTES = 0x2,
1875 MLX5_QPC_MTU_1K_BYTES = 0x3,
1876 MLX5_QPC_MTU_2K_BYTES = 0x4,
1877 MLX5_QPC_MTU_4K_BYTES = 0x5,
1878 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
1879};
1880
1881enum {
1882 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
1883 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
1884 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
1885 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
1886 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
1887 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
1888 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
1889 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
1890};
1891
1892enum {
1893 MLX5_QPC_CS_REQ_DISABLE = 0x0,
1894 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
1895 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
1896};
1897
1898enum {
1899 MLX5_QPC_CS_RES_DISABLE = 0x0,
1900 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
1901 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
1902};
1903
1904struct mlx5_ifc_qpc_bits {
1905 u8 state[0x4];
b4ff3a36 1906 u8 reserved_at_4[0x4];
e281682b 1907 u8 st[0x8];
b4ff3a36 1908 u8 reserved_at_10[0x3];
e281682b 1909 u8 pm_state[0x2];
b4ff3a36 1910 u8 reserved_at_15[0x7];
e281682b 1911 u8 end_padding_mode[0x2];
b4ff3a36 1912 u8 reserved_at_1e[0x2];
e281682b
SM		 1913
1914 u8 wq_signature[0x1];
1915 u8 block_lb_mc[0x1];
1916 u8 atomic_like_write_en[0x1];
1917 u8 latency_sensitive[0x1];
b4ff3a36 1918 u8 reserved_at_24[0x1];
e281682b 1919 u8 drain_sigerr[0x1];
b4ff3a36 1920 u8 reserved_at_26[0x2];
e281682b
SM		 1921 u8 pd[0x18];
1922
1923 u8 mtu[0x3];
1924 u8 log_msg_max[0x5];
b4ff3a36 1925 u8 reserved_at_48[0x1];
e281682b
SM		 1926 u8 log_rq_size[0x4];
1927 u8 log_rq_stride[0x3];
1928 u8 no_sq[0x1];
1929 u8 log_sq_size[0x4];
b4ff3a36 1930 u8 reserved_at_55[0x6];
e281682b 1931 u8 rlky[0x1];
1015c2e8 1932 u8 ulp_stateless_offload_mode[0x4];
e281682b
SM		 1933
1934 u8 counter_set_id[0x8];
1935 u8 uar_page[0x18];
1936
b4ff3a36 1937 u8 reserved_at_80[0x8];
e281682b
SM		 1938 u8 user_index[0x18];
1939
b4ff3a36 1940 u8 reserved_at_a0[0x3];
e281682b
SM		 1941 u8 log_page_size[0x5];
1942 u8 remote_qpn[0x18];
1943
1944 struct mlx5_ifc_ads_bits primary_address_path;
1945
1946 struct mlx5_ifc_ads_bits secondary_address_path;
1947
1948 u8 log_ack_req_freq[0x4];
b4ff3a36 1949 u8 reserved_at_384[0x4];
e281682b 1950 u8 log_sra_max[0x3];
b4ff3a36 1951 u8 reserved_at_38b[0x2];
e281682b
SM		 1952 u8 retry_count[0x3];
1953 u8 rnr_retry[0x3];
b4ff3a36 1954 u8 reserved_at_393[0x1];
e281682b
SM		 1955 u8 fre[0x1];
1956 u8 cur_rnr_retry[0x3];
1957 u8 cur_retry_count[0x3];
b4ff3a36 1958 u8 reserved_at_39b[0x5];
e281682b 1959
b4ff3a36 1960 u8 reserved_at_3a0[0x20];
e281682b 1961
b4ff3a36 1962 u8 reserved_at_3c0[0x8];
e281682b
SM		 1963 u8 next_send_psn[0x18];
1964
b4ff3a36 1965 u8 reserved_at_3e0[0x8];
e281682b
SM		 1966 u8 cqn_snd[0x18];
1967
b4ff3a36 1968 u8 reserved_at_400[0x40];
e281682b 1969
b4ff3a36 1970 u8 reserved_at_440[0x8];
e281682b
SM		 1971 u8 last_acked_psn[0x18];
1972
b4ff3a36 1973 u8 reserved_at_460[0x8];
e281682b
SM		 1974 u8 ssn[0x18];
1975
b4ff3a36 1976 u8 reserved_at_480[0x8];
e281682b 1977 u8 log_rra_max[0x3];
b4ff3a36 1978 u8 reserved_at_48b[0x1];
e281682b
SM		 1979 u8 atomic_mode[0x4];
1980 u8 rre[0x1];
1981 u8 rwe[0x1];
1982 u8 rae[0x1];
b4ff3a36 1983 u8 reserved_at_493[0x1];
e281682b 1984 u8 page_offset[0x6];
b4ff3a36 1985 u8 reserved_at_49a[0x3];
e281682b
SM		 1986 u8 cd_slave_receive[0x1];
1987 u8 cd_slave_send[0x1];
1988 u8 cd_master[0x1];
1989
b4ff3a36 1990 u8 reserved_at_4a0[0x3];
e281682b
SM		 1991 u8 min_rnr_nak[0x5];
1992 u8 next_rcv_psn[0x18];
1993
b4ff3a36 1994 u8 reserved_at_4c0[0x8];
e281682b
SM		 1995 u8 xrcd[0x18];
1996
b4ff3a36 1997 u8 reserved_at_4e0[0x8];
e281682b
SM		 1998 u8 cqn_rcv[0x18];
1999
2000 u8 dbr_addr[0x40];
2001
2002 u8 q_key[0x20];
2003
b4ff3a36 2004 u8 reserved_at_560[0x5];
e281682b 2005 u8 rq_type[0x3];
7486216b 2006 u8 srqn_rmpn_xrqn[0x18];
e281682b 2007
b4ff3a36 2008 u8 reserved_at_580[0x8];
e281682b
SM		 2009 u8 rmsn[0x18];
2010
2011 u8 hw_sq_wqebb_counter[0x10];
2012 u8 sw_sq_wqebb_counter[0x10];
2013
2014 u8 hw_rq_counter[0x20];
2015
2016 u8 sw_rq_counter[0x20];
2017
b4ff3a36 2018 u8 reserved_at_600[0x20];
e281682b 2019
b4ff3a36 2020 u8 reserved_at_620[0xf];
e281682b
SM		 2021 u8 cgs[0x1];
2022 u8 cs_req[0x8];
2023 u8 cs_res[0x8];
2024
2025 u8 dc_access_key[0x40];
2026
b4ff3a36 2027 u8 reserved_at_680[0xc0];
e281682b
SM		 2028};
2029
2030struct mlx5_ifc_roce_addr_layout_bits {
2031 u8 source_l3_address[16][0x8];
2032
b4ff3a36 2033 u8 reserved_at_80[0x3];
e281682b
SM		 2034 u8 vlan_valid[0x1];
2035 u8 vlan_id[0xc];
2036 u8 source_mac_47_32[0x10];
2037
2038 u8 source_mac_31_0[0x20];
2039
b4ff3a36 2040 u8 reserved_at_c0[0x14];
e281682b
SM		 2041 u8 roce_l3_type[0x4];
2042 u8 roce_version[0x8];
2043
b4ff3a36 2044 u8 reserved_at_e0[0x20];
e281682b
SM		 2045};
2046
2047union mlx5_ifc_hca_cap_union_bits {
2048 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2049 struct mlx5_ifc_odp_cap_bits odp_cap;
2050 struct mlx5_ifc_atomic_caps_bits atomic_caps;
2051 struct mlx5_ifc_roce_cap_bits roce_cap;
2052 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2053 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
495716b1 2054 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
d6666753 2055 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
3f0393a5 2056 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
7486216b 2057 struct mlx5_ifc_qos_cap_bits qos_cap;
b4ff3a36 2058 u8 reserved_at_0[0x8000];
e281682b
SM		 2059};
2060
2061enum {
2062 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
2063 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
2064 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
9dc0b289 2065 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
e281682b
SM		 2066};
2067
2068struct mlx5_ifc_flow_context_bits {
b4ff3a36 2069 u8 reserved_at_0[0x20];
e281682b
SM		 2070
2071 u8 group_id[0x20];
2072
b4ff3a36 2073 u8 reserved_at_40[0x8];
e281682b
SM		 2074 u8 flow_tag[0x18];
2075
b4ff3a36 2076 u8 reserved_at_60[0x10];
e281682b
SM		 2077 u8 action[0x10];
2078
b4ff3a36 2079 u8 reserved_at_80[0x8];
e281682b
SM		 2080 u8 destination_list_size[0x18];
2081
9dc0b289
AV		 2082 u8 reserved_at_a0[0x8];
2083 u8 flow_counter_list_size[0x18];
2084
2085 u8 reserved_at_c0[0x140];
e281682b
SM		 2086
2087 struct mlx5_ifc_fte_match_param_bits match_value;
2088
b4ff3a36 2089 u8 reserved_at_1200[0x600];
e281682b 2090
9dc0b289 2091 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
e281682b
SM		 2092};
2093
2094enum {
2095 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
2096 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
2097};
2098
2099struct mlx5_ifc_xrc_srqc_bits {
2100 u8 state[0x4];
2101 u8 log_xrc_srq_size[0x4];
b4ff3a36 2102 u8 reserved_at_8[0x18];
e281682b
SM		 2103
2104 u8 wq_signature[0x1];
2105 u8 cont_srq[0x1];
b4ff3a36 2106 u8 reserved_at_22[0x1];
e281682b
SM		 2107 u8 rlky[0x1];
2108 u8 basic_cyclic_rcv_wqe[0x1];
2109 u8 log_rq_stride[0x3];
2110 u8 xrcd[0x18];
2111
2112 u8 page_offset[0x6];
b4ff3a36 2113 u8 reserved_at_46[0x2];
e281682b
SM		 2114 u8 cqn[0x18];
2115
b4ff3a36 2116 u8 reserved_at_60[0x20];
e281682b
SM		 2117
2118 u8 user_index_equal_xrc_srqn[0x1];
b4ff3a36 2119 u8 reserved_at_81[0x1];
e281682b
SM		 2120 u8 log_page_size[0x6];
2121 u8 user_index[0x18];
2122
b4ff3a36 2123 u8 reserved_at_a0[0x20];
e281682b 2124
b4ff3a36 2125 u8 reserved_at_c0[0x8];
e281682b
SM		 2126 u8 pd[0x18];
2127
2128 u8 lwm[0x10];
2129 u8 wqe_cnt[0x10];
2130
b4ff3a36 2131 u8 reserved_at_100[0x40];
e281682b
SM		 2132
2133 u8 db_record_addr_h[0x20];
2134
2135 u8 db_record_addr_l[0x1e];
b4ff3a36 2136 u8 reserved_at_17e[0x2];
e281682b 2137
b4ff3a36 2138 u8 reserved_at_180[0x80];
e281682b
SM		 2139};
2140
2141struct mlx5_ifc_traffic_counter_bits {
2142 u8 packets[0x40];
2143
2144 u8 octets[0x40];
2145};
2146
2147struct mlx5_ifc_tisc_bits {
b4ff3a36 2148 u8 reserved_at_0[0xc];
e281682b 2149 u8 prio[0x4];
b4ff3a36 2150 u8 reserved_at_10[0x10];
e281682b 2151
b4ff3a36 2152 u8 reserved_at_20[0x100];
e281682b 2153
b4ff3a36 2154 u8 reserved_at_120[0x8];
e281682b
SM		 2155 u8 transport_domain[0x18];
2156
b4ff3a36 2157 u8 reserved_at_140[0x3c0];
e281682b
SM		 2158};
2159
2160enum {
2161 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2162 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2163};
2164
2165enum {
2166 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2167 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2168};
2169
2170enum {
2be6967c
SM		 2171 MLX5_RX_HASH_FN_NONE = 0x0,
2172 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
2173 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
e281682b
SM		 2174};
2175
2176enum {
2177 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1,
2178 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2,
2179};
2180
2181struct mlx5_ifc_tirc_bits {
b4ff3a36 2182 u8 reserved_at_0[0x20];
e281682b
SM		 2183
2184 u8 disp_type[0x4];
b4ff3a36 2185 u8 reserved_at_24[0x1c];
e281682b 2186
b4ff3a36 2187 u8 reserved_at_40[0x40];
e281682b 2188
b4ff3a36 2189 u8 reserved_at_80[0x4];
e281682b
SM		 2190 u8 lro_timeout_period_usecs[0x10];
2191 u8 lro_enable_mask[0x4];
2192 u8 lro_max_ip_payload_size[0x8];
2193
b4ff3a36 2194 u8 reserved_at_a0[0x40];
e281682b 2195
b4ff3a36 2196 u8 reserved_at_e0[0x8];
e281682b
SM		 2197 u8 inline_rqn[0x18];
2198
2199 u8 rx_hash_symmetric[0x1];
b4ff3a36 2200 u8 reserved_at_101[0x1];
e281682b 2201 u8 tunneled_offload_en[0x1];
b4ff3a36 2202 u8 reserved_at_103[0x5];
e281682b
SM		 2203 u8 indirect_table[0x18];
2204
2205 u8 rx_hash_fn[0x4];
b4ff3a36 2206 u8 reserved_at_124[0x2];
e281682b
SM		 2207 u8 self_lb_block[0x2];
2208 u8 transport_domain[0x18];
2209
2210 u8 rx_hash_toeplitz_key[10][0x20];
2211
2212 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2213
2214 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2215
b4ff3a36 2216 u8 reserved_at_2c0[0x4c0];
e281682b
SM		 2217};
2218
2219enum {
2220 MLX5_SRQC_STATE_GOOD = 0x0,
2221 MLX5_SRQC_STATE_ERROR = 0x1,
2222};
2223
2224struct mlx5_ifc_srqc_bits {
2225 u8 state[0x4];
2226 u8 log_srq_size[0x4];
b4ff3a36 2227 u8 reserved_at_8[0x18];
e281682b
SM		 2228
2229 u8 wq_signature[0x1];
2230 u8 cont_srq[0x1];
b4ff3a36 2231 u8 reserved_at_22[0x1];
e281682b 2232 u8 rlky[0x1];
b4ff3a36 2233 u8 reserved_at_24[0x1];
e281682b
SM		 2234 u8 log_rq_stride[0x3];
2235 u8 xrcd[0x18];
2236
2237 u8 page_offset[0x6];
b4ff3a36 2238 u8 reserved_at_46[0x2];
e281682b
SM		 2239 u8 cqn[0x18];
2240
b4ff3a36 2241 u8 reserved_at_60[0x20];
e281682b 2242
b4ff3a36 2243 u8 reserved_at_80[0x2];
e281682b 2244 u8 log_page_size[0x6];
b4ff3a36 2245 u8 reserved_at_88[0x18];
e281682b 2246
b4ff3a36 2247 u8 reserved_at_a0[0x20];
e281682b 2248
b4ff3a36 2249 u8 reserved_at_c0[0x8];
e281682b
SM		 2250 u8 pd[0x18];
2251
2252 u8 lwm[0x10];
2253 u8 wqe_cnt[0x10];
2254
b4ff3a36 2255 u8 reserved_at_100[0x40];
e281682b 2256
01949d01 2257 u8 dbr_addr[0x40];
e281682b 2258
b4ff3a36 2259 u8 reserved_at_180[0x80];
e281682b
SM		 2260};
2261
2262enum {
2263 MLX5_SQC_STATE_RST = 0x0,
2264 MLX5_SQC_STATE_RDY = 0x1,
2265 MLX5_SQC_STATE_ERR = 0x3,
2266};
2267
2268struct mlx5_ifc_sqc_bits {
2269 u8 rlky[0x1];
2270 u8 cd_master[0x1];
2271 u8 fre[0x1];
2272 u8 flush_in_error_en[0x1];
b4ff3a36 2273 u8 reserved_at_4[0x4];
e281682b 2274 u8 state[0x4];
7d5e1423
SM		 2275 u8 reg_umr[0x1];
2276 u8 reserved_at_d[0x13];
e281682b 2277
b4ff3a36 2278 u8 reserved_at_20[0x8];
e281682b
SM		 2279 u8 user_index[0x18];
2280
b4ff3a36 2281 u8 reserved_at_40[0x8];
e281682b
SM		 2282 u8 cqn[0x18];
2283
7486216b 2284 u8 reserved_at_60[0x90];
e281682b 2285
7486216b 2286 u8 packet_pacing_rate_limit_index[0x10];
e281682b 2287 u8 tis_lst_sz[0x10];
b4ff3a36 2288 u8 reserved_at_110[0x10];
e281682b 2289
b4ff3a36 2290 u8 reserved_at_120[0x40];
e281682b 2291
b4ff3a36 2292 u8 reserved_at_160[0x8];
e281682b
SM		 2293 u8 tis_num_0[0x18];
2294
2295 struct mlx5_ifc_wq_bits wq;
2296};
2297
2298struct mlx5_ifc_rqtc_bits {
b4ff3a36 2299 u8 reserved_at_0[0xa0];
e281682b 2300
b4ff3a36 2301 u8 reserved_at_a0[0x10];
e281682b
SM		 2302 u8 rqt_max_size[0x10];
2303
b4ff3a36 2304 u8 reserved_at_c0[0x10];
e281682b
SM		 2305 u8 rqt_actual_size[0x10];
2306
b4ff3a36 2307 u8 reserved_at_e0[0x6a0];
e281682b
SM		 2308
2309 struct mlx5_ifc_rq_num_bits rq_num[0];
2310};
2311
2312enum {
2313 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2314 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2315};
2316
2317enum {
2318 MLX5_RQC_STATE_RST = 0x0,
2319 MLX5_RQC_STATE_RDY = 0x1,
2320 MLX5_RQC_STATE_ERR = 0x3,
2321};
2322
2323struct mlx5_ifc_rqc_bits {
2324 u8 rlky[0x1];
7d5e1423
SM		 2325 u8 reserved_at_1[0x1];
2326 u8 scatter_fcs[0x1];
e281682b
SM		 2327 u8 vsd[0x1];
2328 u8 mem_rq_type[0x4];
2329 u8 state[0x4];
b4ff3a36 2330 u8 reserved_at_c[0x1];
e281682b 2331 u8 flush_in_error_en[0x1];
b4ff3a36 2332 u8 reserved_at_e[0x12];
e281682b 2333
b4ff3a36 2334 u8 reserved_at_20[0x8];
e281682b
SM		 2335 u8 user_index[0x18];
2336
b4ff3a36 2337 u8 reserved_at_40[0x8];
e281682b
SM		 2338 u8 cqn[0x18];
2339
2340 u8 counter_set_id[0x8];
b4ff3a36 2341 u8 reserved_at_68[0x18];
e281682b 2342
b4ff3a36 2343 u8 reserved_at_80[0x8];
e281682b
SM		 2344 u8 rmpn[0x18];
2345
b4ff3a36 2346 u8 reserved_at_a0[0xe0];
e281682b
SM		 2347
2348 struct mlx5_ifc_wq_bits wq;
2349};
2350
2351enum {
2352 MLX5_RMPC_STATE_RDY = 0x1,
2353 MLX5_RMPC_STATE_ERR = 0x3,
2354};
2355
2356struct mlx5_ifc_rmpc_bits {
b4ff3a36 2357 u8 reserved_at_0[0x8];
e281682b 2358 u8 state[0x4];
b4ff3a36 2359 u8 reserved_at_c[0x14];
e281682b
SM		 2360
2361 u8 basic_cyclic_rcv_wqe[0x1];
b4ff3a36 2362 u8 reserved_at_21[0x1f];
e281682b 2363
b4ff3a36 2364 u8 reserved_at_40[0x140];
e281682b
SM		 2365
2366 struct mlx5_ifc_wq_bits wq;
2367};
2368
e281682b 2369struct mlx5_ifc_nic_vport_context_bits {
b4ff3a36 2370 u8 reserved_at_0[0x1f];
e281682b
SM		 2371 u8 roce_en[0x1];
2372
d82b7318 2373 u8 arm_change_event[0x1];
b4ff3a36 2374 u8 reserved_at_21[0x1a];
d82b7318
SM		 2375 u8 event_on_mtu[0x1];
2376 u8 event_on_promisc_change[0x1];
2377 u8 event_on_vlan_change[0x1];
2378 u8 event_on_mc_address_change[0x1];
2379 u8 event_on_uc_address_change[0x1];
e281682b 2380
b4ff3a36 2381 u8 reserved_at_40[0xf0];
d82b7318
SM		 2382
2383 u8 mtu[0x10];
2384
9efa7525
AS		 2385 u8 system_image_guid[0x40];
2386 u8 port_guid[0x40];
2387 u8 node_guid[0x40];
2388
b4ff3a36 2389 u8 reserved_at_200[0x140];
9efa7525 2390 u8 qkey_violation_counter[0x10];
b4ff3a36 2391 u8 reserved_at_350[0x430];
d82b7318
SM		 2392
2393 u8 promisc_uc[0x1];
2394 u8 promisc_mc[0x1];
2395 u8 promisc_all[0x1];
b4ff3a36 2396 u8 reserved_at_783[0x2];
e281682b 2397 u8 allowed_list_type[0x3];
b4ff3a36 2398 u8 reserved_at_788[0xc];
e281682b
SM		 2399 u8 allowed_list_size[0xc];
2400
2401 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2402
b4ff3a36 2403 u8 reserved_at_7e0[0x20];
e281682b
SM		 2404
2405 u8 current_uc_mac_address[0][0x40];
2406};
2407
2408enum {
2409 MLX5_MKC_ACCESS_MODE_PA = 0x0,
2410 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
2411 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
2412};
2413
2414struct mlx5_ifc_mkc_bits {
b4ff3a36 2415 u8 reserved_at_0[0x1];
e281682b 2416 u8 free[0x1];
b4ff3a36 2417 u8 reserved_at_2[0xd];
e281682b
SM		 2418 u8 small_fence_on_rdma_read_response[0x1];
2419 u8 umr_en[0x1];
2420 u8 a[0x1];
2421 u8 rw[0x1];
2422 u8 rr[0x1];
2423 u8 lw[0x1];
2424 u8 lr[0x1];
2425 u8 access_mode[0x2];
b4ff3a36 2426 u8 reserved_at_18[0x8];
e281682b
SM		 2427
2428 u8 qpn[0x18];
2429 u8 mkey_7_0[0x8];
2430
b4ff3a36 2431 u8 reserved_at_40[0x20];
e281682b
SM		 2432
2433 u8 length64[0x1];
2434 u8 bsf_en[0x1];
2435 u8 sync_umr[0x1];
b4ff3a36 2436 u8 reserved_at_63[0x2];
e281682b 2437 u8 expected_sigerr_count[0x1];
b4ff3a36 2438 u8 reserved_at_66[0x1];
e281682b
SM		 2439 u8 en_rinval[0x1];
2440 u8 pd[0x18];
2441
2442 u8 start_addr[0x40];
2443
2444 u8 len[0x40];
2445
2446 u8 bsf_octword_size[0x20];
2447
b4ff3a36 2448 u8 reserved_at_120[0x80];
e281682b
SM		 2449
2450 u8 translations_octword_size[0x20];
2451
b4ff3a36 2452 u8 reserved_at_1c0[0x1b];
e281682b
SM		 2453 u8 log_page_size[0x5];
2454
b4ff3a36 2455 u8 reserved_at_1e0[0x20];
e281682b
SM		 2456};
2457
2458struct mlx5_ifc_pkey_bits {
b4ff3a36 2459 u8 reserved_at_0[0x10];
e281682b
SM		 2460 u8 pkey[0x10];
2461};
2462
2463struct mlx5_ifc_array128_auto_bits {
2464 u8 array128_auto[16][0x8];
2465};
2466
2467struct mlx5_ifc_hca_vport_context_bits {
2468 u8 field_select[0x20];
2469
b4ff3a36 2470 u8 reserved_at_20[0xe0];
e281682b
SM		 2471
2472 u8 sm_virt_aware[0x1];
2473 u8 has_smi[0x1];
2474 u8 has_raw[0x1];
2475 u8 grh_required[0x1];
b4ff3a36 2476 u8 reserved_at_104[0xc];
707c4602
MD		 2477 u8 port_physical_state[0x4];
2478 u8 vport_state_policy[0x4];
2479 u8 port_state[0x4];
e281682b
SM		 2480 u8 vport_state[0x4];
2481
b4ff3a36 2482 u8 reserved_at_120[0x20];
707c4602
MD		 2483
2484 u8 system_image_guid[0x40];
e281682b
SM		 2485
2486 u8 port_guid[0x40];
2487
2488 u8 node_guid[0x40];
2489
2490 u8 cap_mask1[0x20];
2491
2492 u8 cap_mask1_field_select[0x20];
2493
2494 u8 cap_mask2[0x20];
2495
2496 u8 cap_mask2_field_select[0x20];
2497
b4ff3a36 2498 u8 reserved_at_280[0x80];
e281682b
SM		 2499
2500 u8 lid[0x10];
b4ff3a36 2501 u8 reserved_at_310[0x4];
e281682b
SM		 2502 u8 init_type_reply[0x4];
2503 u8 lmc[0x3];
2504 u8 subnet_timeout[0x5];
2505
2506 u8 sm_lid[0x10];
2507 u8 sm_sl[0x4];
b4ff3a36 2508 u8 reserved_at_334[0xc];
e281682b
SM		 2509
2510 u8 qkey_violation_counter[0x10];
2511 u8 pkey_violation_counter[0x10];
2512
b4ff3a36 2513 u8 reserved_at_360[0xca0];
e281682b
SM		 2514};
2515
d6666753 2516struct mlx5_ifc_esw_vport_context_bits {
b4ff3a36 2517 u8 reserved_at_0[0x3];
d6666753
SM		 2518 u8 vport_svlan_strip[0x1];
2519 u8 vport_cvlan_strip[0x1];
2520 u8 vport_svlan_insert[0x1];
2521 u8 vport_cvlan_insert[0x2];
b4ff3a36 2522 u8 reserved_at_8[0x18];
d6666753 2523
b4ff3a36 2524 u8 reserved_at_20[0x20];
d6666753
SM		 2525
2526 u8 svlan_cfi[0x1];
2527 u8 svlan_pcp[0x3];
2528 u8 svlan_id[0xc];
2529 u8 cvlan_cfi[0x1];
2530 u8 cvlan_pcp[0x3];
2531 u8 cvlan_id[0xc];
2532
b4ff3a36 2533 u8 reserved_at_60[0x7a0];
d6666753
SM		 2534};
2535
e281682b
SM		 2536enum {
2537 MLX5_EQC_STATUS_OK = 0x0,
2538 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
2539};
2540
2541enum {
2542 MLX5_EQC_ST_ARMED = 0x9,
2543 MLX5_EQC_ST_FIRED = 0xa,
2544};
2545
2546struct mlx5_ifc_eqc_bits {
2547 u8 status[0x4];
b4ff3a36 2548 u8 reserved_at_4[0x9];
e281682b
SM		 2549 u8 ec[0x1];
2550 u8 oi[0x1];
b4ff3a36 2551 u8 reserved_at_f[0x5];
e281682b 2552 u8 st[0x4];
b4ff3a36 2553 u8 reserved_at_18[0x8];
e281682b 2554
b4ff3a36 2555 u8 reserved_at_20[0x20];
e281682b 2556
b4ff3a36 2557 u8 reserved_at_40[0x14];
e281682b 2558 u8 page_offset[0x6];
b4ff3a36 2559 u8 reserved_at_5a[0x6];
e281682b 2560
b4ff3a36 2561 u8 reserved_at_60[0x3];
e281682b
SM		 2562 u8 log_eq_size[0x5];
2563 u8 uar_page[0x18];
2564
b4ff3a36 2565 u8 reserved_at_80[0x20];
e281682b 2566
b4ff3a36 2567 u8 reserved_at_a0[0x18];
e281682b
SM		 2568 u8 intr[0x8];
2569
b4ff3a36 2570 u8 reserved_at_c0[0x3];
e281682b 2571 u8 log_page_size[0x5];
b4ff3a36 2572 u8 reserved_at_c8[0x18];
e281682b 2573
b4ff3a36 2574 u8 reserved_at_e0[0x60];
e281682b 2575
b4ff3a36 2576 u8 reserved_at_140[0x8];
e281682b
SM		 2577 u8 consumer_counter[0x18];
2578
b4ff3a36 2579 u8 reserved_at_160[0x8];
e281682b
SM		 2580 u8 producer_counter[0x18];
2581
b4ff3a36 2582 u8 reserved_at_180[0x80];
e281682b
SM		 2583};
2584
2585enum {
2586 MLX5_DCTC_STATE_ACTIVE = 0x0,
2587 MLX5_DCTC_STATE_DRAINING = 0x1,
2588 MLX5_DCTC_STATE_DRAINED = 0x2,
2589};
2590
2591enum {
2592 MLX5_DCTC_CS_RES_DISABLE = 0x0,
2593 MLX5_DCTC_CS_RES_NA = 0x1,
2594 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
2595};
2596
2597enum {
2598 MLX5_DCTC_MTU_256_BYTES = 0x1,
2599 MLX5_DCTC_MTU_512_BYTES = 0x2,
2600 MLX5_DCTC_MTU_1K_BYTES = 0x3,
2601 MLX5_DCTC_MTU_2K_BYTES = 0x4,
2602 MLX5_DCTC_MTU_4K_BYTES = 0x5,
2603};
2604
2605struct mlx5_ifc_dctc_bits {
b4ff3a36 2606 u8 reserved_at_0[0x4];
e281682b 2607 u8 state[0x4];
b4ff3a36 2608 u8 reserved_at_8[0x18];
e281682b 2609
b4ff3a36 2610 u8 reserved_at_20[0x8];
e281682b
SM		 2611 u8 user_index[0x18];
2612
b4ff3a36 2613 u8 reserved_at_40[0x8];
e281682b
SM		 2614 u8 cqn[0x18];
2615
2616 u8 counter_set_id[0x8];
2617 u8 atomic_mode[0x4];
2618 u8 rre[0x1];
2619 u8 rwe[0x1];
2620 u8 rae[0x1];
2621 u8 atomic_like_write_en[0x1];
2622 u8 latency_sensitive[0x1];
2623 u8 rlky[0x1];
2624 u8 free_ar[0x1];
b4ff3a36 2625 u8 reserved_at_73[0xd];
e281682b 2626
b4ff3a36 2627 u8 reserved_at_80[0x8];
e281682b 2628 u8 cs_res[0x8];
b4ff3a36 2629 u8 reserved_at_90[0x3];
e281682b 2630 u8 min_rnr_nak[0x5];
b4ff3a36 2631 u8 reserved_at_98[0x8];
e281682b 2632
b4ff3a36 2633 u8 reserved_at_a0[0x8];
7486216b 2634 u8 srqn_xrqn[0x18];
e281682b 2635
b4ff3a36 2636 u8 reserved_at_c0[0x8];
e281682b
SM		 2637 u8 pd[0x18];
2638
2639 u8 tclass[0x8];
b4ff3a36 2640 u8 reserved_at_e8[0x4];
e281682b
SM		 2641 u8 flow_label[0x14];
2642
2643 u8 dc_access_key[0x40];
2644
b4ff3a36 2645 u8 reserved_at_140[0x5];
e281682b
SM		 2646 u8 mtu[0x3];
2647 u8 port[0x8];
2648 u8 pkey_index[0x10];
2649
b4ff3a36 2650 u8 reserved_at_160[0x8];
e281682b 2651 u8 my_addr_index[0x8];
b4ff3a36 2652 u8 reserved_at_170[0x8];
e281682b
SM		 2653 u8 hop_limit[0x8];
2654
2655 u8 dc_access_key_violation_count[0x20];
2656
b4ff3a36 2657 u8 reserved_at_1a0[0x14];
e281682b
SM		 2658 u8 dei_cfi[0x1];
2659 u8 eth_prio[0x3];
2660 u8 ecn[0x2];
2661 u8 dscp[0x6];
2662
b4ff3a36 2663 u8 reserved_at_1c0[0x40];
e281682b
SM		 2664};
2665
2666enum {
2667 MLX5_CQC_STATUS_OK = 0x0,
2668 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
2669 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
2670};
2671
2672enum {
2673 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
2674 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
2675};
2676
2677enum {
2678 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
2679 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
2680 MLX5_CQC_ST_FIRED = 0xa,
2681};
2682
7d5e1423
SM		 2683enum {
2684 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
2685 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
7486216b 2686 MLX5_CQ_PERIOD_NUM_MODES
7d5e1423
SM		 2687};
2688
e281682b
SM		 2689struct mlx5_ifc_cqc_bits {
2690 u8 status[0x4];
b4ff3a36 2691 u8 reserved_at_4[0x4];
e281682b
SM		 2692 u8 cqe_sz[0x3];
2693 u8 cc[0x1];
b4ff3a36 2694 u8 reserved_at_c[0x1];
e281682b
SM		 2695 u8 scqe_break_moderation_en[0x1];
2696 u8 oi[0x1];
7d5e1423
SM		 2697 u8 cq_period_mode[0x2];
2698 u8 cqe_comp_en[0x1];
e281682b
SM		 2699 u8 mini_cqe_res_format[0x2];
2700 u8 st[0x4];
b4ff3a36 2701 u8 reserved_at_18[0x8];
e281682b 2702
b4ff3a36 2703 u8 reserved_at_20[0x20];
e281682b 2704
b4ff3a36 2705 u8 reserved_at_40[0x14];
e281682b 2706 u8 page_offset[0x6];
b4ff3a36 2707 u8 reserved_at_5a[0x6];
e281682b 2708
b4ff3a36 2709 u8 reserved_at_60[0x3];
e281682b
SM		 2710 u8 log_cq_size[0x5];
2711 u8 uar_page[0x18];
2712
b4ff3a36 2713 u8 reserved_at_80[0x4];
e281682b
SM		 2714 u8 cq_period[0xc];
2715 u8 cq_max_count[0x10];
2716
b4ff3a36 2717 u8 reserved_at_a0[0x18];
e281682b
SM		 2718 u8 c_eqn[0x8];
2719
b4ff3a36 2720 u8 reserved_at_c0[0x3];
e281682b 2721 u8 log_page_size[0x5];
b4ff3a36 2722 u8 reserved_at_c8[0x18];
e281682b 2723
b4ff3a36 2724 u8 reserved_at_e0[0x20];
e281682b 2725
b4ff3a36 2726 u8 reserved_at_100[0x8];
e281682b
SM		 2727 u8 last_notified_index[0x18];
2728
b4ff3a36 2729 u8 reserved_at_120[0x8];
e281682b
SM		 2730 u8 last_solicit_index[0x18];
2731
b4ff3a36 2732 u8 reserved_at_140[0x8];
e281682b
SM		 2733 u8 consumer_counter[0x18];
2734
b4ff3a36 2735 u8 reserved_at_160[0x8];
e281682b
SM		 2736 u8 producer_counter[0x18];
2737
b4ff3a36 2738 u8 reserved_at_180[0x40];
e281682b
SM		 2739
2740 u8 dbr_addr[0x40];
2741};
2742
2743union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2744 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2745 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2746 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
b4ff3a36 2747 u8 reserved_at_0[0x800];
e281682b
SM		 2748};
2749
2750struct mlx5_ifc_query_adapter_param_block_bits {
b4ff3a36 2751 u8 reserved_at_0[0xc0];
e281682b 2752
b4ff3a36 2753 u8 reserved_at_c0[0x8];
211e6c80
MD		 2754 u8 ieee_vendor_id[0x18];
2755
b4ff3a36 2756 u8 reserved_at_e0[0x10];
e281682b
SM		 2757 u8 vsd_vendor_id[0x10];
2758
2759 u8 vsd[208][0x8];
2760
2761 u8 vsd_contd_psid[16][0x8];
2762};
2763
7486216b
SM		 2764enum {
2765 MLX5_XRQC_STATE_GOOD = 0x0,
2766 MLX5_XRQC_STATE_ERROR = 0x1,
2767};
2768
2769enum {
2770 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
2771 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
2772};
2773
2774enum {
2775 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
2776};
2777
2778struct mlx5_ifc_tag_matching_topology_context_bits {
2779 u8 log_matching_list_sz[0x4];
2780 u8 reserved_at_4[0xc];
2781 u8 append_next_index[0x10];
2782
2783 u8 sw_phase_cnt[0x10];
2784 u8 hw_phase_cnt[0x10];
2785
2786 u8 reserved_at_40[0x40];
2787};
2788
2789struct mlx5_ifc_xrqc_bits {
2790 u8 state[0x4];
2791 u8 rlkey[0x1];
2792 u8 reserved_at_5[0xf];
2793 u8 topology[0x4];
2794 u8 reserved_at_18[0x4];
2795 u8 offload[0x4];
2796
2797 u8 reserved_at_20[0x8];
2798 u8 user_index[0x18];
2799
2800 u8 reserved_at_40[0x8];
2801 u8 cqn[0x18];
2802
2803 u8 reserved_at_60[0xa0];
2804
2805 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
2806
2807 u8 reserved_at_180[0x180];
2808
2809 struct mlx5_ifc_wq_bits wq;
2810};
2811
e281682b
SM		 2812union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2813 struct mlx5_ifc_modify_field_select_bits modify_field_select;
2814 struct mlx5_ifc_resize_field_select_bits resize_field_select;
b4ff3a36 2815 u8 reserved_at_0[0x20];
e281682b
SM		 2816};
2817
2818union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2819 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2820 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2821 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
b4ff3a36 2822 u8 reserved_at_0[0x20];
e281682b
SM		 2823};
2824
2825union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
2826 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
2827 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
2828 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
2829 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
2830 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
2831 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
2832 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
1c64bf6f 2833 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b 2834 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
b4ff3a36 2835 u8 reserved_at_0[0x7c0];
e281682b
SM		 2836};
2837
2838union mlx5_ifc_event_auto_bits {
2839 struct mlx5_ifc_comp_event_bits comp_event;
2840 struct mlx5_ifc_dct_events_bits dct_events;
2841 struct mlx5_ifc_qp_events_bits qp_events;
2842 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
2843 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
2844 struct mlx5_ifc_cq_error_bits cq_error;
2845 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
2846 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
2847 struct mlx5_ifc_gpio_event_bits gpio_event;
2848 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
2849 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
2850 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
b4ff3a36 2851 u8 reserved_at_0[0xe0];
e281682b
SM		 2852};
2853
2854struct mlx5_ifc_health_buffer_bits {
b4ff3a36 2855 u8 reserved_at_0[0x100];
e281682b
SM		 2856
2857 u8 assert_existptr[0x20];
2858
2859 u8 assert_callra[0x20];
2860
b4ff3a36 2861 u8 reserved_at_140[0x40];
e281682b
SM		 2862
2863 u8 fw_version[0x20];
2864
2865 u8 hw_id[0x20];
2866
b4ff3a36 2867 u8 reserved_at_1c0[0x20];
e281682b
SM		 2868
2869 u8 irisc_index[0x8];
2870 u8 synd[0x8];
2871 u8 ext_synd[0x10];
2872};
2873
2874struct mlx5_ifc_register_loopback_control_bits {
2875 u8 no_lb[0x1];
b4ff3a36 2876 u8 reserved_at_1[0x7];
e281682b 2877 u8 port[0x8];
b4ff3a36 2878 u8 reserved_at_10[0x10];
e281682b 2879
b4ff3a36 2880 u8 reserved_at_20[0x60];
e281682b
SM		 2881};
2882
2883struct mlx5_ifc_teardown_hca_out_bits {
2884 u8 status[0x8];
b4ff3a36 2885 u8 reserved_at_8[0x18];
e281682b
SM		 2886
2887 u8 syndrome[0x20];
2888
b4ff3a36 2889 u8 reserved_at_40[0x40];
e281682b
SM		 2890};
2891
2892enum {
2893 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
2894 MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE = 0x1,
2895};
2896
2897struct mlx5_ifc_teardown_hca_in_bits {
2898 u8 opcode[0x10];
b4ff3a36 2899 u8 reserved_at_10[0x10];
e281682b 2900
b4ff3a36 2901 u8 reserved_at_20[0x10];
e281682b
SM		 2902 u8 op_mod[0x10];
2903
b4ff3a36 2904 u8 reserved_at_40[0x10];
e281682b
SM		 2905 u8 profile[0x10];
2906
b4ff3a36 2907 u8 reserved_at_60[0x20];
e281682b
SM		 2908};
2909
2910struct mlx5_ifc_sqerr2rts_qp_out_bits {
2911 u8 status[0x8];
b4ff3a36 2912 u8 reserved_at_8[0x18];
e281682b
SM		 2913
2914 u8 syndrome[0x20];
2915
b4ff3a36 2916 u8 reserved_at_40[0x40];
e281682b
SM		 2917};
2918
2919struct mlx5_ifc_sqerr2rts_qp_in_bits {
2920 u8 opcode[0x10];
b4ff3a36 2921 u8 reserved_at_10[0x10];
e281682b 2922
b4ff3a36 2923 u8 reserved_at_20[0x10];
e281682b
SM		 2924 u8 op_mod[0x10];
2925
b4ff3a36 2926 u8 reserved_at_40[0x8];
e281682b
SM		 2927 u8 qpn[0x18];
2928
b4ff3a36 2929 u8 reserved_at_60[0x20];
e281682b
SM		 2930
2931 u8 opt_param_mask[0x20];
2932
b4ff3a36 2933 u8 reserved_at_a0[0x20];
e281682b
SM		 2934
2935 struct mlx5_ifc_qpc_bits qpc;
2936
b4ff3a36 2937 u8 reserved_at_800[0x80];
e281682b
SM		 2938};
2939
2940struct mlx5_ifc_sqd2rts_qp_out_bits {
2941 u8 status[0x8];
b4ff3a36 2942 u8 reserved_at_8[0x18];
e281682b
SM		 2943
2944 u8 syndrome[0x20];
2945
b4ff3a36 2946 u8 reserved_at_40[0x40];
e281682b
SM		 2947};
2948
2949struct mlx5_ifc_sqd2rts_qp_in_bits {
2950 u8 opcode[0x10];
b4ff3a36 2951 u8 reserved_at_10[0x10];
e281682b 2952
b4ff3a36 2953 u8 reserved_at_20[0x10];
e281682b
SM		 2954 u8 op_mod[0x10];
2955
b4ff3a36 2956 u8 reserved_at_40[0x8];
e281682b
SM		 2957 u8 qpn[0x18];
2958
b4ff3a36 2959 u8 reserved_at_60[0x20];
e281682b
SM		 2960
2961 u8 opt_param_mask[0x20];
2962
b4ff3a36 2963 u8 reserved_at_a0[0x20];
e281682b
SM		 2964
2965 struct mlx5_ifc_qpc_bits qpc;
2966
b4ff3a36 2967 u8 reserved_at_800[0x80];
e281682b
SM		 2968};
2969
2970struct mlx5_ifc_set_roce_address_out_bits {
2971 u8 status[0x8];
b4ff3a36 2972 u8 reserved_at_8[0x18];
e281682b
SM		 2973
2974 u8 syndrome[0x20];
2975
b4ff3a36 2976 u8 reserved_at_40[0x40];
e281682b
SM		 2977};
2978
2979struct mlx5_ifc_set_roce_address_in_bits {
2980 u8 opcode[0x10];
b4ff3a36 2981 u8 reserved_at_10[0x10];
e281682b 2982
b4ff3a36 2983 u8 reserved_at_20[0x10];
e281682b
SM		 2984 u8 op_mod[0x10];
2985
2986 u8 roce_address_index[0x10];
b4ff3a36 2987 u8 reserved_at_50[0x10];
e281682b 2988
b4ff3a36 2989 u8 reserved_at_60[0x20];
e281682b
SM		 2990
2991 struct mlx5_ifc_roce_addr_layout_bits roce_address;
2992};
2993
2994struct mlx5_ifc_set_mad_demux_out_bits {
2995 u8 status[0x8];
b4ff3a36 2996 u8 reserved_at_8[0x18];
e281682b
SM		 2997
2998 u8 syndrome[0x20];
2999
b4ff3a36 3000 u8 reserved_at_40[0x40];
e281682b
SM		 3001};
3002
3003enum {
3004 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
3005 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
3006};
3007
3008struct mlx5_ifc_set_mad_demux_in_bits {
3009 u8 opcode[0x10];
b4ff3a36 3010 u8 reserved_at_10[0x10];
e281682b 3011
b4ff3a36 3012 u8 reserved_at_20[0x10];
e281682b
SM		 3013 u8 op_mod[0x10];
3014
b4ff3a36 3015 u8 reserved_at_40[0x20];
e281682b 3016
b4ff3a36 3017 u8 reserved_at_60[0x6];
e281682b 3018 u8 demux_mode[0x2];
b4ff3a36 3019 u8 reserved_at_68[0x18];
e281682b
SM		 3020};
3021
3022struct mlx5_ifc_set_l2_table_entry_out_bits {
3023 u8 status[0x8];
b4ff3a36 3024 u8 reserved_at_8[0x18];
e281682b
SM		 3025
3026 u8 syndrome[0x20];
3027
b4ff3a36 3028 u8 reserved_at_40[0x40];
e281682b
SM		 3029};
3030
3031struct mlx5_ifc_set_l2_table_entry_in_bits {
3032 u8 opcode[0x10];
b4ff3a36 3033 u8 reserved_at_10[0x10];
e281682b 3034
b4ff3a36 3035 u8 reserved_at_20[0x10];
e281682b
SM		 3036 u8 op_mod[0x10];
3037
b4ff3a36 3038 u8 reserved_at_40[0x60];
e281682b 3039
b4ff3a36 3040 u8 reserved_at_a0[0x8];
e281682b
SM		 3041 u8 table_index[0x18];
3042
b4ff3a36 3043 u8 reserved_at_c0[0x20];
e281682b 3044
b4ff3a36 3045 u8 reserved_at_e0[0x13];
e281682b
SM		 3046 u8 vlan_valid[0x1];
3047 u8 vlan[0xc];
3048
3049 struct mlx5_ifc_mac_address_layout_bits mac_address;
3050
b4ff3a36 3051 u8 reserved_at_140[0xc0];
e281682b
SM		 3052};
3053
3054struct mlx5_ifc_set_issi_out_bits {
3055 u8 status[0x8];
b4ff3a36 3056 u8 reserved_at_8[0x18];
e281682b
SM		 3057
3058 u8 syndrome[0x20];
3059
b4ff3a36 3060 u8 reserved_at_40[0x40];
e281682b
SM		 3061};
3062
3063struct mlx5_ifc_set_issi_in_bits {
3064 u8 opcode[0x10];
b4ff3a36 3065 u8 reserved_at_10[0x10];
e281682b 3066
b4ff3a36 3067 u8 reserved_at_20[0x10];
e281682b
SM		 3068 u8 op_mod[0x10];
3069
b4ff3a36 3070 u8 reserved_at_40[0x10];
e281682b
SM		 3071 u8 current_issi[0x10];
3072
b4ff3a36 3073 u8 reserved_at_60[0x20];
e281682b
SM		 3074};
3075
3076struct mlx5_ifc_set_hca_cap_out_bits {
3077 u8 status[0x8];
b4ff3a36 3078 u8 reserved_at_8[0x18];
e281682b
SM		 3079
3080 u8 syndrome[0x20];
3081
b4ff3a36 3082 u8 reserved_at_40[0x40];
e281682b
SM		 3083};
3084
3085struct mlx5_ifc_set_hca_cap_in_bits {
3086 u8 opcode[0x10];
b4ff3a36 3087 u8 reserved_at_10[0x10];
e281682b 3088
b4ff3a36 3089 u8 reserved_at_20[0x10];
e281682b
SM		 3090 u8 op_mod[0x10];
3091
b4ff3a36 3092 u8 reserved_at_40[0x40];
e281682b
SM		 3093
3094 union mlx5_ifc_hca_cap_union_bits capability;
3095};
3096
26a81453
MG		 3097enum {
3098 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
3099 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
3100 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
3101 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
3102};
3103
e281682b
SM		 3104struct mlx5_ifc_set_fte_out_bits {
3105 u8 status[0x8];
b4ff3a36 3106 u8 reserved_at_8[0x18];
e281682b
SM		 3107
3108 u8 syndrome[0x20];
3109
b4ff3a36 3110 u8 reserved_at_40[0x40];
e281682b
SM		 3111};
3112
3113struct mlx5_ifc_set_fte_in_bits {
3114 u8 opcode[0x10];
b4ff3a36 3115 u8 reserved_at_10[0x10];
e281682b 3116
b4ff3a36 3117 u8 reserved_at_20[0x10];
e281682b
SM		 3118 u8 op_mod[0x10];
3119
7d5e1423
SM		 3120 u8 other_vport[0x1];
3121 u8 reserved_at_41[0xf];
3122 u8 vport_number[0x10];
3123
3124 u8 reserved_at_60[0x20];
e281682b
SM		 3125
3126 u8 table_type[0x8];
b4ff3a36 3127 u8 reserved_at_88[0x18];
e281682b 3128
b4ff3a36 3129 u8 reserved_at_a0[0x8];
e281682b
SM		 3130 u8 table_id[0x18];
3131
b4ff3a36 3132 u8 reserved_at_c0[0x18];
26a81453
MG		 3133 u8 modify_enable_mask[0x8];
3134
b4ff3a36 3135 u8 reserved_at_e0[0x20];
e281682b
SM		 3136
3137 u8 flow_index[0x20];
3138
b4ff3a36 3139 u8 reserved_at_120[0xe0];
e281682b
SM		 3140
3141 struct mlx5_ifc_flow_context_bits flow_context;
3142};
3143
3144struct mlx5_ifc_rts2rts_qp_out_bits {
3145 u8 status[0x8];
b4ff3a36 3146 u8 reserved_at_8[0x18];
e281682b
SM		 3147
3148 u8 syndrome[0x20];
3149
b4ff3a36 3150 u8 reserved_at_40[0x40];
e281682b
SM		 3151};
3152
3153struct mlx5_ifc_rts2rts_qp_in_bits {
3154 u8 opcode[0x10];
b4ff3a36 3155 u8 reserved_at_10[0x10];
e281682b 3156
b4ff3a36 3157 u8 reserved_at_20[0x10];
e281682b
SM		 3158 u8 op_mod[0x10];
3159
b4ff3a36 3160 u8 reserved_at_40[0x8];
e281682b
SM		 3161 u8 qpn[0x18];
3162
b4ff3a36 3163 u8 reserved_at_60[0x20];
e281682b
SM		 3164
3165 u8 opt_param_mask[0x20];
3166
b4ff3a36 3167 u8 reserved_at_a0[0x20];
e281682b
SM		 3168
3169 struct mlx5_ifc_qpc_bits qpc;
3170
b4ff3a36 3171 u8 reserved_at_800[0x80];
e281682b
SM		 3172};
3173
3174struct mlx5_ifc_rtr2rts_qp_out_bits {
3175 u8 status[0x8];
b4ff3a36 3176 u8 reserved_at_8[0x18];
e281682b
SM		 3177
3178 u8 syndrome[0x20];
3179
b4ff3a36 3180 u8 reserved_at_40[0x40];
e281682b
SM		 3181};
3182
3183struct mlx5_ifc_rtr2rts_qp_in_bits {
3184 u8 opcode[0x10];
b4ff3a36 3185 u8 reserved_at_10[0x10];
e281682b 3186
b4ff3a36 3187 u8 reserved_at_20[0x10];
e281682b
SM		 3188 u8 op_mod[0x10];
3189
b4ff3a36 3190 u8 reserved_at_40[0x8];
e281682b
SM		 3191 u8 qpn[0x18];
3192
b4ff3a36 3193 u8 reserved_at_60[0x20];
e281682b
SM		 3194
3195 u8 opt_param_mask[0x20];
3196
b4ff3a36 3197 u8 reserved_at_a0[0x20];
e281682b
SM		 3198
3199 struct mlx5_ifc_qpc_bits qpc;
3200
b4ff3a36 3201 u8 reserved_at_800[0x80];
e281682b
SM		 3202};
3203
3204struct mlx5_ifc_rst2init_qp_out_bits {
3205 u8 status[0x8];
b4ff3a36 3206 u8 reserved_at_8[0x18];
e281682b
SM		 3207
3208 u8 syndrome[0x20];
3209
b4ff3a36 3210 u8 reserved_at_40[0x40];
e281682b
SM		 3211};
3212
3213struct mlx5_ifc_rst2init_qp_in_bits {
3214 u8 opcode[0x10];
b4ff3a36 3215 u8 reserved_at_10[0x10];
e281682b 3216
b4ff3a36 3217 u8 reserved_at_20[0x10];
e281682b
SM		 3218 u8 op_mod[0x10];
3219
b4ff3a36 3220 u8 reserved_at_40[0x8];
e281682b
SM		 3221 u8 qpn[0x18];
3222
b4ff3a36 3223 u8 reserved_at_60[0x20];
e281682b
SM		 3224
3225 u8 opt_param_mask[0x20];
3226
b4ff3a36 3227 u8 reserved_at_a0[0x20];
e281682b
SM		 3228
3229 struct mlx5_ifc_qpc_bits qpc;
3230
b4ff3a36 3231 u8 reserved_at_800[0x80];
e281682b
SM		 3232};
3233
7486216b
SM		 3234struct mlx5_ifc_query_xrq_out_bits {
3235 u8 status[0x8];
3236 u8 reserved_at_8[0x18];
3237
3238 u8 syndrome[0x20];
3239
3240 u8 reserved_at_40[0x40];
3241
3242 struct mlx5_ifc_xrqc_bits xrq_context;
3243};
3244
3245struct mlx5_ifc_query_xrq_in_bits {
3246 u8 opcode[0x10];
3247 u8 reserved_at_10[0x10];
3248
3249 u8 reserved_at_20[0x10];
3250 u8 op_mod[0x10];
3251
3252 u8 reserved_at_40[0x8];
3253 u8 xrqn[0x18];
3254
3255 u8 reserved_at_60[0x20];
3256};
3257
e281682b
SM		 3258struct mlx5_ifc_query_xrc_srq_out_bits {
3259 u8 status[0x8];
b4ff3a36 3260 u8 reserved_at_8[0x18];
e281682b
SM		 3261
3262 u8 syndrome[0x20];
3263
b4ff3a36 3264 u8 reserved_at_40[0x40];
e281682b
SM		 3265
3266 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3267
b4ff3a36 3268 u8 reserved_at_280[0x600];
e281682b
SM		 3269
3270 u8 pas[0][0x40];
3271};
3272
3273struct mlx5_ifc_query_xrc_srq_in_bits {
3274 u8 opcode[0x10];
b4ff3a36 3275 u8 reserved_at_10[0x10];
e281682b 3276
b4ff3a36 3277 u8 reserved_at_20[0x10];
e281682b
SM		 3278 u8 op_mod[0x10];
3279
b4ff3a36 3280 u8 reserved_at_40[0x8];
e281682b
SM		 3281 u8 xrc_srqn[0x18];
3282
b4ff3a36 3283 u8 reserved_at_60[0x20];
e281682b
SM		 3284};
3285
3286enum {
3287 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
3288 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
3289};
3290
3291struct mlx5_ifc_query_vport_state_out_bits {
3292 u8 status[0x8];
b4ff3a36 3293 u8 reserved_at_8[0x18];
e281682b
SM		 3294
3295 u8 syndrome[0x20];
3296
b4ff3a36 3297 u8 reserved_at_40[0x20];
e281682b 3298
b4ff3a36 3299 u8 reserved_at_60[0x18];
e281682b
SM		 3300 u8 admin_state[0x4];
3301 u8 state[0x4];
3302};
3303
3304enum {
3305 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0,
e7546514 3306 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1,
e281682b
SM		 3307};
3308
3309struct mlx5_ifc_query_vport_state_in_bits {
3310 u8 opcode[0x10];
b4ff3a36 3311 u8 reserved_at_10[0x10];
e281682b 3312
b4ff3a36 3313 u8 reserved_at_20[0x10];
e281682b
SM		 3314 u8 op_mod[0x10];
3315
3316 u8 other_vport[0x1];
b4ff3a36 3317 u8 reserved_at_41[0xf];
e281682b
SM		 3318 u8 vport_number[0x10];
3319
b4ff3a36 3320 u8 reserved_at_60[0x20];
e281682b
SM		 3321};
3322
3323struct mlx5_ifc_query_vport_counter_out_bits {
3324 u8 status[0x8];
b4ff3a36 3325 u8 reserved_at_8[0x18];
e281682b
SM		 3326
3327 u8 syndrome[0x20];
3328
b4ff3a36 3329 u8 reserved_at_40[0x40];
e281682b
SM		 3330
3331 struct mlx5_ifc_traffic_counter_bits received_errors;
3332
3333 struct mlx5_ifc_traffic_counter_bits transmit_errors;
3334
3335 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3336
3337 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3338
3339 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3340
3341 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3342
3343 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3344
3345 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3346
3347 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3348
3349 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3350
3351 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3352
3353 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3354
b4ff3a36 3355 u8 reserved_at_680[0xa00];
e281682b
SM		 3356};
3357
3358enum {
3359 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
3360};
3361
3362struct mlx5_ifc_query_vport_counter_in_bits {
3363 u8 opcode[0x10];
b4ff3a36 3364 u8 reserved_at_10[0x10];
e281682b 3365
b4ff3a36 3366 u8 reserved_at_20[0x10];
e281682b
SM		 3367 u8 op_mod[0x10];
3368
3369 u8 other_vport[0x1];
b54ba277
MY		 3370 u8 reserved_at_41[0xb];
3371 u8 port_num[0x4];
e281682b
SM		 3372 u8 vport_number[0x10];
3373
b4ff3a36 3374 u8 reserved_at_60[0x60];
e281682b
SM		 3375
3376 u8 clear[0x1];
b4ff3a36 3377 u8 reserved_at_c1[0x1f];
e281682b 3378
b4ff3a36 3379 u8 reserved_at_e0[0x20];
e281682b
SM		 3380};
3381
3382struct mlx5_ifc_query_tis_out_bits {
3383 u8 status[0x8];
b4ff3a36 3384 u8 reserved_at_8[0x18];
e281682b
SM		 3385
3386 u8 syndrome[0x20];
3387
b4ff3a36 3388 u8 reserved_at_40[0x40];
e281682b
SM		 3389
3390 struct mlx5_ifc_tisc_bits tis_context;
3391};
3392
3393struct mlx5_ifc_query_tis_in_bits {
3394 u8 opcode[0x10];
b4ff3a36 3395 u8 reserved_at_10[0x10];
e281682b 3396
b4ff3a36 3397 u8 reserved_at_20[0x10];
e281682b
SM		 3398 u8 op_mod[0x10];
3399
b4ff3a36 3400 u8 reserved_at_40[0x8];
e281682b
SM		 3401 u8 tisn[0x18];
3402
b4ff3a36 3403 u8 reserved_at_60[0x20];
e281682b
SM		 3404};
3405
3406struct mlx5_ifc_query_tir_out_bits {
3407 u8 status[0x8];
b4ff3a36 3408 u8 reserved_at_8[0x18];
e281682b
SM		 3409
3410 u8 syndrome[0x20];
3411
b4ff3a36 3412 u8 reserved_at_40[0xc0];
e281682b
SM		 3413
3414 struct mlx5_ifc_tirc_bits tir_context;
3415};
3416
3417struct mlx5_ifc_query_tir_in_bits {
3418 u8 opcode[0x10];
b4ff3a36 3419 u8 reserved_at_10[0x10];
e281682b 3420
b4ff3a36 3421 u8 reserved_at_20[0x10];
e281682b
SM		 3422 u8 op_mod[0x10];
3423
b4ff3a36 3424 u8 reserved_at_40[0x8];
e281682b
SM		 3425 u8 tirn[0x18];
3426
b4ff3a36 3427 u8 reserved_at_60[0x20];
e281682b
SM		 3428};
3429
3430struct mlx5_ifc_query_srq_out_bits {
3431 u8 status[0x8];
b4ff3a36 3432 u8 reserved_at_8[0x18];
e281682b
SM		 3433
3434 u8 syndrome[0x20];
3435
b4ff3a36 3436 u8 reserved_at_40[0x40];
e281682b
SM		 3437
3438 struct mlx5_ifc_srqc_bits srq_context_entry;
3439
b4ff3a36 3440 u8 reserved_at_280[0x600];
e281682b
SM		 3441
3442 u8 pas[0][0x40];
3443};
3444
3445struct mlx5_ifc_query_srq_in_bits {
3446 u8 opcode[0x10];
b4ff3a36 3447 u8 reserved_at_10[0x10];
e281682b 3448
b4ff3a36 3449 u8 reserved_at_20[0x10];
e281682b
SM		 3450 u8 op_mod[0x10];
3451
b4ff3a36 3452 u8 reserved_at_40[0x8];
e281682b
SM		 3453 u8 srqn[0x18];
3454
b4ff3a36 3455 u8 reserved_at_60[0x20];
e281682b
SM		 3456};
3457
3458struct mlx5_ifc_query_sq_out_bits {
3459 u8 status[0x8];
b4ff3a36 3460 u8 reserved_at_8[0x18];
e281682b
SM		 3461
3462 u8 syndrome[0x20];
3463
b4ff3a36 3464 u8 reserved_at_40[0xc0];
e281682b
SM		 3465
3466 struct mlx5_ifc_sqc_bits sq_context;
3467};
3468
3469struct mlx5_ifc_query_sq_in_bits {
3470 u8 opcode[0x10];
b4ff3a36 3471 u8 reserved_at_10[0x10];
e281682b 3472
b4ff3a36 3473 u8 reserved_at_20[0x10];
e281682b
SM		 3474 u8 op_mod[0x10];
3475
b4ff3a36 3476 u8 reserved_at_40[0x8];
e281682b
SM		 3477 u8 sqn[0x18];
3478
b4ff3a36 3479 u8 reserved_at_60[0x20];
e281682b
SM		 3480};
3481
3482struct mlx5_ifc_query_special_contexts_out_bits {
3483 u8 status[0x8];
b4ff3a36 3484 u8 reserved_at_8[0x18];
e281682b
SM		 3485
3486 u8 syndrome[0x20];
3487
b4ff3a36 3488 u8 reserved_at_40[0x20];
e281682b
SM		 3489
3490 u8 resd_lkey[0x20];
3491};
3492
3493struct mlx5_ifc_query_special_contexts_in_bits {
3494 u8 opcode[0x10];
b4ff3a36 3495 u8 reserved_at_10[0x10];
e281682b 3496
b4ff3a36 3497 u8 reserved_at_20[0x10];
e281682b
SM		 3498 u8 op_mod[0x10];
3499
b4ff3a36 3500 u8 reserved_at_40[0x40];
e281682b
SM		 3501};
3502
3503struct mlx5_ifc_query_rqt_out_bits {
3504 u8 status[0x8];
b4ff3a36 3505 u8 reserved_at_8[0x18];
e281682b
SM		 3506
3507 u8 syndrome[0x20];
3508
b4ff3a36 3509 u8 reserved_at_40[0xc0];
e281682b
SM		 3510
3511 struct mlx5_ifc_rqtc_bits rqt_context;
3512};
3513
3514struct mlx5_ifc_query_rqt_in_bits {
3515 u8 opcode[0x10];
b4ff3a36 3516 u8 reserved_at_10[0x10];
e281682b 3517
b4ff3a36 3518 u8 reserved_at_20[0x10];
e281682b
SM		 3519 u8 op_mod[0x10];
3520
b4ff3a36 3521 u8 reserved_at_40[0x8];
e281682b
SM		 3522 u8 rqtn[0x18];
3523
b4ff3a36 3524 u8 reserved_at_60[0x20];
e281682b
SM		 3525};
3526
3527struct mlx5_ifc_query_rq_out_bits {
3528 u8 status[0x8];
b4ff3a36 3529 u8 reserved_at_8[0x18];
e281682b
SM		 3530
3531 u8 syndrome[0x20];
3532
b4ff3a36 3533 u8 reserved_at_40[0xc0];
e281682b
SM		 3534
3535 struct mlx5_ifc_rqc_bits rq_context;
3536};
3537
3538struct mlx5_ifc_query_rq_in_bits {
3539 u8 opcode[0x10];
b4ff3a36 3540 u8 reserved_at_10[0x10];
e281682b 3541
b4ff3a36 3542 u8 reserved_at_20[0x10];
e281682b
SM		 3543 u8 op_mod[0x10];
3544
b4ff3a36 3545 u8 reserved_at_40[0x8];
e281682b
SM		 3546 u8 rqn[0x18];
3547
b4ff3a36 3548 u8 reserved_at_60[0x20];
e281682b
SM		 3549};
3550
3551struct mlx5_ifc_query_roce_address_out_bits {
3552 u8 status[0x8];
b4ff3a36 3553 u8 reserved_at_8[0x18];
e281682b
SM		 3554
3555 u8 syndrome[0x20];
3556
b4ff3a36 3557 u8 reserved_at_40[0x40];
e281682b
SM		 3558
3559 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3560};
3561
3562struct mlx5_ifc_query_roce_address_in_bits {
3563 u8 opcode[0x10];
b4ff3a36 3564 u8 reserved_at_10[0x10];
e281682b 3565
b4ff3a36 3566 u8 reserved_at_20[0x10];
e281682b
SM		 3567 u8 op_mod[0x10];
3568
3569 u8 roce_address_index[0x10];
b4ff3a36 3570 u8 reserved_at_50[0x10];
e281682b 3571
b4ff3a36 3572 u8 reserved_at_60[0x20];
e281682b
SM		 3573};
3574
3575struct mlx5_ifc_query_rmp_out_bits {
3576 u8 status[0x8];
b4ff3a36 3577 u8 reserved_at_8[0x18];
e281682b
SM		 3578
3579 u8 syndrome[0x20];
3580
b4ff3a36 3581 u8 reserved_at_40[0xc0];
e281682b
SM		 3582
3583 struct mlx5_ifc_rmpc_bits rmp_context;
3584};
3585
3586struct mlx5_ifc_query_rmp_in_bits {
3587 u8 opcode[0x10];
b4ff3a36 3588 u8 reserved_at_10[0x10];
e281682b 3589
b4ff3a36 3590 u8 reserved_at_20[0x10];
e281682b
SM		 3591 u8 op_mod[0x10];
3592
b4ff3a36 3593 u8 reserved_at_40[0x8];
e281682b
SM		 3594 u8 rmpn[0x18];
3595
b4ff3a36 3596 u8 reserved_at_60[0x20];
e281682b
SM		 3597};
3598
3599struct mlx5_ifc_query_qp_out_bits {
3600 u8 status[0x8];
b4ff3a36 3601 u8 reserved_at_8[0x18];
e281682b
SM		 3602
3603 u8 syndrome[0x20];
3604
b4ff3a36 3605 u8 reserved_at_40[0x40];
e281682b
SM		 3606
3607 u8 opt_param_mask[0x20];
3608
b4ff3a36 3609 u8 reserved_at_a0[0x20];
e281682b
SM		 3610
3611 struct mlx5_ifc_qpc_bits qpc;
3612
b4ff3a36 3613 u8 reserved_at_800[0x80];
e281682b
SM		 3614
3615 u8 pas[0][0x40];
3616};
3617
3618struct mlx5_ifc_query_qp_in_bits {
3619 u8 opcode[0x10];
b4ff3a36 3620 u8 reserved_at_10[0x10];
e281682b 3621
b4ff3a36 3622 u8 reserved_at_20[0x10];
e281682b
SM		 3623 u8 op_mod[0x10];
3624
b4ff3a36 3625 u8 reserved_at_40[0x8];
e281682b
SM		 3626 u8 qpn[0x18];
3627
b4ff3a36 3628 u8 reserved_at_60[0x20];
e281682b
SM		 3629};
3630
3631struct mlx5_ifc_query_q_counter_out_bits {
3632 u8 status[0x8];
b4ff3a36 3633 u8 reserved_at_8[0x18];
e281682b
SM		 3634
3635 u8 syndrome[0x20];
3636
b4ff3a36 3637 u8 reserved_at_40[0x40];
e281682b
SM		 3638
3639 u8 rx_write_requests[0x20];
3640
b4ff3a36 3641 u8 reserved_at_a0[0x20];
e281682b
SM		 3642
3643 u8 rx_read_requests[0x20];
3644
b4ff3a36 3645 u8 reserved_at_e0[0x20];
e281682b
SM		 3646
3647 u8 rx_atomic_requests[0x20];
3648
b4ff3a36 3649 u8 reserved_at_120[0x20];
e281682b
SM		 3650
3651 u8 rx_dct_connect[0x20];
3652
b4ff3a36 3653 u8 reserved_at_160[0x20];
e281682b
SM		 3654
3655 u8 out_of_buffer[0x20];
3656
b4ff3a36 3657 u8 reserved_at_1a0[0x20];
e281682b
SM		 3658
3659 u8 out_of_sequence[0x20];
3660
7486216b
SM		 3661 u8 reserved_at_1e0[0x20];
3662
3663 u8 duplicate_request[0x20];
3664
3665 u8 reserved_at_220[0x20];
3666
3667 u8 rnr_nak_retry_err[0x20];
3668
3669 u8 reserved_at_260[0x20];
3670
3671 u8 packet_seq_err[0x20];
3672
3673 u8 reserved_at_2a0[0x20];
3674
3675 u8 implied_nak_seq_err[0x20];
3676
3677 u8 reserved_at_2e0[0x20];
3678
3679 u8 local_ack_timeout_err[0x20];
3680
3681 u8 reserved_at_320[0x4e0];
e281682b
SM		 3682};
3683
3684struct mlx5_ifc_query_q_counter_in_bits {
3685 u8 opcode[0x10];
b4ff3a36 3686 u8 reserved_at_10[0x10];
e281682b 3687
b4ff3a36 3688 u8 reserved_at_20[0x10];
e281682b
SM		 3689 u8 op_mod[0x10];
3690
b4ff3a36 3691 u8 reserved_at_40[0x80];
e281682b
SM		 3692
3693 u8 clear[0x1];
b4ff3a36 3694 u8 reserved_at_c1[0x1f];
e281682b 3695
b4ff3a36 3696 u8 reserved_at_e0[0x18];
e281682b
SM		 3697 u8 counter_set_id[0x8];
3698};
3699
3700struct mlx5_ifc_query_pages_out_bits {
3701 u8 status[0x8];
b4ff3a36 3702 u8 reserved_at_8[0x18];
e281682b
SM		 3703
3704 u8 syndrome[0x20];
3705
b4ff3a36 3706 u8 reserved_at_40[0x10];
e281682b
SM		 3707 u8 function_id[0x10];
3708
3709 u8 num_pages[0x20];
3710};
3711
3712enum {
3713 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
3714 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
3715 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
3716};
3717
3718struct mlx5_ifc_query_pages_in_bits {
3719 u8 opcode[0x10];
b4ff3a36 3720 u8 reserved_at_10[0x10];
e281682b 3721
b4ff3a36 3722 u8 reserved_at_20[0x10];
e281682b
SM		 3723 u8 op_mod[0x10];
3724
b4ff3a36 3725 u8 reserved_at_40[0x10];
e281682b
SM		 3726 u8 function_id[0x10];
3727
b4ff3a36 3728 u8 reserved_at_60[0x20];
e281682b
SM		 3729};
3730
3731struct mlx5_ifc_query_nic_vport_context_out_bits {
3732 u8 status[0x8];
b4ff3a36 3733 u8 reserved_at_8[0x18];
e281682b
SM		 3734
3735 u8 syndrome[0x20];
3736
b4ff3a36 3737 u8 reserved_at_40[0x40];
e281682b
SM		 3738
3739 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
3740};
3741
3742struct mlx5_ifc_query_nic_vport_context_in_bits {
3743 u8 opcode[0x10];
b4ff3a36 3744 u8 reserved_at_10[0x10];
e281682b 3745
b4ff3a36 3746 u8 reserved_at_20[0x10];
e281682b
SM		 3747 u8 op_mod[0x10];
3748
3749 u8 other_vport[0x1];
b4ff3a36 3750 u8 reserved_at_41[0xf];
e281682b
SM		 3751 u8 vport_number[0x10];
3752
b4ff3a36 3753 u8 reserved_at_60[0x5];
e281682b 3754 u8 allowed_list_type[0x3];
b4ff3a36 3755 u8 reserved_at_68[0x18];
e281682b
SM		 3756};
3757
3758struct mlx5_ifc_query_mkey_out_bits {
3759 u8 status[0x8];
b4ff3a36 3760 u8 reserved_at_8[0x18];
e281682b
SM		 3761
3762 u8 syndrome[0x20];
3763
b4ff3a36 3764 u8 reserved_at_40[0x40];
e281682b
SM		 3765
3766 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
3767
b4ff3a36 3768 u8 reserved_at_280[0x600];
e281682b
SM		 3769
3770 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
3771
3772 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
3773};
3774
3775struct mlx5_ifc_query_mkey_in_bits {
3776 u8 opcode[0x10];
b4ff3a36 3777 u8 reserved_at_10[0x10];
e281682b 3778
b4ff3a36 3779 u8 reserved_at_20[0x10];
e281682b
SM		 3780 u8 op_mod[0x10];
3781
b4ff3a36 3782 u8 reserved_at_40[0x8];
e281682b
SM		 3783 u8 mkey_index[0x18];
3784
3785 u8 pg_access[0x1];
b4ff3a36 3786 u8 reserved_at_61[0x1f];
e281682b
SM		 3787};
3788
3789struct mlx5_ifc_query_mad_demux_out_bits {
3790 u8 status[0x8];
b4ff3a36 3791 u8 reserved_at_8[0x18];
e281682b
SM		 3792
3793 u8 syndrome[0x20];
3794
b4ff3a36 3795 u8 reserved_at_40[0x40];
e281682b
SM		 3796
3797 u8 mad_dumux_parameters_block[0x20];
3798};
3799
3800struct mlx5_ifc_query_mad_demux_in_bits {
3801 u8 opcode[0x10];
b4ff3a36 3802 u8 reserved_at_10[0x10];
e281682b 3803
b4ff3a36 3804 u8 reserved_at_20[0x10];
e281682b
SM		 3805 u8 op_mod[0x10];
3806
b4ff3a36 3807 u8 reserved_at_40[0x40];
e281682b
SM		 3808};
3809
3810struct mlx5_ifc_query_l2_table_entry_out_bits {
3811 u8 status[0x8];
b4ff3a36 3812 u8 reserved_at_8[0x18];
e281682b
SM		 3813
3814 u8 syndrome[0x20];
3815
b4ff3a36 3816 u8 reserved_at_40[0xa0];
e281682b 3817
b4ff3a36 3818 u8 reserved_at_e0[0x13];
e281682b
SM		 3819 u8 vlan_valid[0x1];
3820 u8 vlan[0xc];
3821
3822 struct mlx5_ifc_mac_address_layout_bits mac_address;
3823
b4ff3a36 3824 u8 reserved_at_140[0xc0];
e281682b
SM		 3825};
3826
3827struct mlx5_ifc_query_l2_table_entry_in_bits {
3828 u8 opcode[0x10];
b4ff3a36 3829 u8 reserved_at_10[0x10];
e281682b 3830
b4ff3a36 3831 u8 reserved_at_20[0x10];
e281682b
SM		 3832 u8 op_mod[0x10];
3833
b4ff3a36 3834 u8 reserved_at_40[0x60];
e281682b 3835
b4ff3a36 3836 u8 reserved_at_a0[0x8];
e281682b
SM		 3837 u8 table_index[0x18];
3838
b4ff3a36 3839 u8 reserved_at_c0[0x140];
e281682b
SM		 3840};
3841
3842struct mlx5_ifc_query_issi_out_bits {
3843 u8 status[0x8];
b4ff3a36 3844 u8 reserved_at_8[0x18];
e281682b
SM		 3845
3846 u8 syndrome[0x20];
3847
b4ff3a36 3848 u8 reserved_at_40[0x10];
e281682b
SM		 3849 u8 current_issi[0x10];
3850
b4ff3a36 3851 u8 reserved_at_60[0xa0];
e281682b 3852
b4ff3a36 3853 u8 reserved_at_100[76][0x8];
e281682b
SM		 3854 u8 supported_issi_dw0[0x20];
3855};
3856
3857struct mlx5_ifc_query_issi_in_bits {
3858 u8 opcode[0x10];
b4ff3a36 3859 u8 reserved_at_10[0x10];
e281682b 3860
b4ff3a36 3861 u8 reserved_at_20[0x10];
e281682b
SM		 3862 u8 op_mod[0x10];
3863
b4ff3a36 3864 u8 reserved_at_40[0x40];
e281682b
SM		 3865};
3866
3867struct mlx5_ifc_query_hca_vport_pkey_out_bits {
3868 u8 status[0x8];
b4ff3a36 3869 u8 reserved_at_8[0x18];
e281682b
SM		 3870
3871 u8 syndrome[0x20];
3872
b4ff3a36 3873 u8 reserved_at_40[0x40];
e281682b
SM		 3874
3875 struct mlx5_ifc_pkey_bits pkey[0];
3876};
3877
3878struct mlx5_ifc_query_hca_vport_pkey_in_bits {
3879 u8 opcode[0x10];
b4ff3a36 3880 u8 reserved_at_10[0x10];
e281682b 3881
b4ff3a36 3882 u8 reserved_at_20[0x10];
e281682b
SM		 3883 u8 op_mod[0x10];
3884
3885 u8 other_vport[0x1];
b4ff3a36 3886 u8 reserved_at_41[0xb];
707c4602 3887 u8 port_num[0x4];
e281682b
SM		 3888 u8 vport_number[0x10];
3889
b4ff3a36 3890 u8 reserved_at_60[0x10];
e281682b
SM		 3891 u8 pkey_index[0x10];
3892};
3893
eff901d3
EC		 3894enum {
3895 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
3896 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
3897 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
3898};
3899
e281682b
SM		 3900struct mlx5_ifc_query_hca_vport_gid_out_bits {
3901 u8 status[0x8];
b4ff3a36 3902 u8 reserved_at_8[0x18];
e281682b
SM		 3903
3904 u8 syndrome[0x20];
3905
b4ff3a36 3906 u8 reserved_at_40[0x20];
e281682b
SM		 3907
3908 u8 gids_num[0x10];
b4ff3a36 3909 u8 reserved_at_70[0x10];
e281682b
SM		 3910
3911 struct mlx5_ifc_array128_auto_bits gid[0];
3912};
3913
3914struct mlx5_ifc_query_hca_vport_gid_in_bits {
3915 u8 opcode[0x10];
b4ff3a36 3916 u8 reserved_at_10[0x10];
e281682b 3917
b4ff3a36 3918 u8 reserved_at_20[0x10];
e281682b
SM		 3919 u8 op_mod[0x10];
3920
3921 u8 other_vport[0x1];
b4ff3a36 3922 u8 reserved_at_41[0xb];
707c4602 3923 u8 port_num[0x4];
e281682b
SM		 3924 u8 vport_number[0x10];
3925
b4ff3a36 3926 u8 reserved_at_60[0x10];
e281682b
SM		 3927 u8 gid_index[0x10];
3928};
3929
3930struct mlx5_ifc_query_hca_vport_context_out_bits {
3931 u8 status[0x8];
b4ff3a36 3932 u8 reserved_at_8[0x18];
e281682b
SM		 3933
3934 u8 syndrome[0x20];
3935
b4ff3a36 3936 u8 reserved_at_40[0x40];
e281682b
SM		 3937
3938 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
3939};
3940
3941struct mlx5_ifc_query_hca_vport_context_in_bits {
3942 u8 opcode[0x10];
b4ff3a36 3943 u8 reserved_at_10[0x10];
e281682b 3944
b4ff3a36 3945 u8 reserved_at_20[0x10];
e281682b
SM		 3946 u8 op_mod[0x10];
3947
3948 u8 other_vport[0x1];
b4ff3a36 3949 u8 reserved_at_41[0xb];
707c4602 3950 u8 port_num[0x4];
e281682b
SM		 3951 u8 vport_number[0x10];
3952
b4ff3a36 3953 u8 reserved_at_60[0x20];
e281682b
SM		 3954};
3955
3956struct mlx5_ifc_query_hca_cap_out_bits {
3957 u8 status[0x8];
b4ff3a36 3958 u8 reserved_at_8[0x18];
e281682b
SM		 3959
3960 u8 syndrome[0x20];
3961
b4ff3a36 3962 u8 reserved_at_40[0x40];
e281682b
SM		 3963
3964 union mlx5_ifc_hca_cap_union_bits capability;
3965};
3966
3967struct mlx5_ifc_query_hca_cap_in_bits {
3968 u8 opcode[0x10];
b4ff3a36 3969 u8 reserved_at_10[0x10];
e281682b 3970
b4ff3a36 3971 u8 reserved_at_20[0x10];
e281682b
SM		 3972 u8 op_mod[0x10];
3973
b4ff3a36 3974 u8 reserved_at_40[0x40];
e281682b
SM		 3975};
3976
3977struct mlx5_ifc_query_flow_table_out_bits {
3978 u8 status[0x8];
b4ff3a36 3979 u8 reserved_at_8[0x18];
e281682b
SM		 3980
3981 u8 syndrome[0x20];
3982
b4ff3a36 3983 u8 reserved_at_40[0x80];
e281682b 3984
b4ff3a36 3985 u8 reserved_at_c0[0x8];
e281682b 3986 u8 level[0x8];
b4ff3a36 3987 u8 reserved_at_d0[0x8];
e281682b
SM		 3988 u8 log_size[0x8];
3989
b4ff3a36 3990 u8 reserved_at_e0[0x120];
e281682b
SM		 3991};
3992
3993struct mlx5_ifc_query_flow_table_in_bits {
3994 u8 opcode[0x10];
b4ff3a36 3995 u8 reserved_at_10[0x10];
e281682b 3996
b4ff3a36 3997 u8 reserved_at_20[0x10];
e281682b
SM		 3998 u8 op_mod[0x10];
3999
b4ff3a36 4000 u8 reserved_at_40[0x40];
e281682b
SM		 4001
4002 u8 table_type[0x8];
b4ff3a36 4003 u8 reserved_at_88[0x18];
e281682b 4004
b4ff3a36 4005 u8 reserved_at_a0[0x8];
e281682b
SM		 4006 u8 table_id[0x18];
4007
b4ff3a36 4008 u8 reserved_at_c0[0x140];
e281682b
SM		 4009};
4010
4011struct mlx5_ifc_query_fte_out_bits {
4012 u8 status[0x8];
b4ff3a36 4013 u8 reserved_at_8[0x18];
e281682b
SM		 4014
4015 u8 syndrome[0x20];
4016
b4ff3a36 4017 u8 reserved_at_40[0x1c0];
e281682b
SM		 4018
4019 struct mlx5_ifc_flow_context_bits flow_context;
4020};
4021
4022struct mlx5_ifc_query_fte_in_bits {
4023 u8 opcode[0x10];
b4ff3a36 4024 u8 reserved_at_10[0x10];
e281682b 4025
b4ff3a36 4026 u8 reserved_at_20[0x10];
e281682b
SM		 4027 u8 op_mod[0x10];
4028
b4ff3a36 4029 u8 reserved_at_40[0x40];
e281682b
SM		 4030
4031 u8 table_type[0x8];
b4ff3a36 4032 u8 reserved_at_88[0x18];
e281682b 4033
b4ff3a36 4034 u8 reserved_at_a0[0x8];
e281682b
SM		 4035 u8 table_id[0x18];
4036
b4ff3a36 4037 u8 reserved_at_c0[0x40];
e281682b
SM		 4038
4039 u8 flow_index[0x20];
4040
b4ff3a36 4041 u8 reserved_at_120[0xe0];
e281682b
SM		 4042};
4043
4044enum {
4045 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
4046 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
4047 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
4048};
4049
4050struct mlx5_ifc_query_flow_group_out_bits {
4051 u8 status[0x8];
b4ff3a36 4052 u8 reserved_at_8[0x18];
e281682b
SM		 4053
4054 u8 syndrome[0x20];
4055
b4ff3a36 4056 u8 reserved_at_40[0xa0];
e281682b
SM		 4057
4058 u8 start_flow_index[0x20];
4059
b4ff3a36 4060 u8 reserved_at_100[0x20];
e281682b
SM		 4061
4062 u8 end_flow_index[0x20];
4063
b4ff3a36 4064 u8 reserved_at_140[0xa0];
e281682b 4065
b4ff3a36 4066 u8 reserved_at_1e0[0x18];
e281682b
SM		 4067 u8 match_criteria_enable[0x8];
4068
4069 struct mlx5_ifc_fte_match_param_bits match_criteria;
4070
b4ff3a36 4071 u8 reserved_at_1200[0xe00];
e281682b
SM		 4072};
4073
4074struct mlx5_ifc_query_flow_group_in_bits {
4075 u8 opcode[0x10];
b4ff3a36 4076 u8 reserved_at_10[0x10];
e281682b 4077
b4ff3a36 4078 u8 reserved_at_20[0x10];
e281682b
SM		 4079 u8 op_mod[0x10];
4080
b4ff3a36 4081 u8 reserved_at_40[0x40];
e281682b
SM		 4082
4083 u8 table_type[0x8];
b4ff3a36 4084 u8 reserved_at_88[0x18];
e281682b 4085
b4ff3a36 4086 u8 reserved_at_a0[0x8];
e281682b
SM		 4087 u8 table_id[0x18];
4088
4089 u8 group_id[0x20];
4090
b4ff3a36 4091 u8 reserved_at_e0[0x120];
e281682b
SM		 4092};
4093
9dc0b289
AV		 4094struct mlx5_ifc_query_flow_counter_out_bits {
4095 u8 status[0x8];
4096 u8 reserved_at_8[0x18];
4097
4098 u8 syndrome[0x20];
4099
4100 u8 reserved_at_40[0x40];
4101
4102 struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4103};
4104
4105struct mlx5_ifc_query_flow_counter_in_bits {
4106 u8 opcode[0x10];
4107 u8 reserved_at_10[0x10];
4108
4109 u8 reserved_at_20[0x10];
4110 u8 op_mod[0x10];
4111
4112 u8 reserved_at_40[0x80];
4113
4114 u8 clear[0x1];
4115 u8 reserved_at_c1[0xf];
4116 u8 num_of_counters[0x10];
4117
4118 u8 reserved_at_e0[0x10];
4119 u8 flow_counter_id[0x10];
4120};
4121
d6666753
SM		 4122struct mlx5_ifc_query_esw_vport_context_out_bits {
4123 u8 status[0x8];
b4ff3a36 4124 u8 reserved_at_8[0x18];
d6666753
SM		 4125
4126 u8 syndrome[0x20];
4127
b4ff3a36 4128 u8 reserved_at_40[0x40];
d6666753
SM		 4129
4130 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4131};
4132
4133struct mlx5_ifc_query_esw_vport_context_in_bits {
4134 u8 opcode[0x10];
b4ff3a36 4135 u8 reserved_at_10[0x10];
d6666753 4136
b4ff3a36 4137 u8 reserved_at_20[0x10];
d6666753
SM		 4138 u8 op_mod[0x10];
4139
4140 u8 other_vport[0x1];
b4ff3a36 4141 u8 reserved_at_41[0xf];
d6666753
SM		 4142 u8 vport_number[0x10];
4143
b4ff3a36 4144 u8 reserved_at_60[0x20];
d6666753
SM		 4145};
4146
4147struct mlx5_ifc_modify_esw_vport_context_out_bits {
4148 u8 status[0x8];
b4ff3a36 4149 u8 reserved_at_8[0x18];
d6666753
SM		 4150
4151 u8 syndrome[0x20];
4152
b4ff3a36 4153 u8 reserved_at_40[0x40];
d6666753
SM		 4154};
4155
4156struct mlx5_ifc_esw_vport_context_fields_select_bits {
b4ff3a36 4157 u8 reserved_at_0[0x1c];
d6666753
SM		 4158 u8 vport_cvlan_insert[0x1];
4159 u8 vport_svlan_insert[0x1];
4160 u8 vport_cvlan_strip[0x1];
4161 u8 vport_svlan_strip[0x1];
4162};
4163
4164struct mlx5_ifc_modify_esw_vport_context_in_bits {
4165 u8 opcode[0x10];
b4ff3a36 4166 u8 reserved_at_10[0x10];
d6666753 4167
b4ff3a36 4168 u8 reserved_at_20[0x10];
d6666753
SM		 4169 u8 op_mod[0x10];
4170
4171 u8 other_vport[0x1];
b4ff3a36 4172 u8 reserved_at_41[0xf];
d6666753
SM		 4173 u8 vport_number[0x10];
4174
4175 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4176
4177 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4178};
4179
e281682b
SM		 4180struct mlx5_ifc_query_eq_out_bits {
4181 u8 status[0x8];
b4ff3a36 4182 u8 reserved_at_8[0x18];
e281682b
SM		 4183
4184 u8 syndrome[0x20];
4185
b4ff3a36 4186 u8 reserved_at_40[0x40];
e281682b
SM		 4187
4188 struct mlx5_ifc_eqc_bits eq_context_entry;
4189
b4ff3a36 4190 u8 reserved_at_280[0x40];
e281682b
SM		 4191
4192 u8 event_bitmask[0x40];
4193
b4ff3a36 4194 u8 reserved_at_300[0x580];
e281682b
SM		 4195
4196 u8 pas[0][0x40];
4197};
4198
4199struct mlx5_ifc_query_eq_in_bits {
4200 u8 opcode[0x10];
b4ff3a36 4201 u8 reserved_at_10[0x10];
e281682b 4202
b4ff3a36 4203 u8 reserved_at_20[0x10];
e281682b
SM		 4204 u8 op_mod[0x10];
4205
b4ff3a36 4206 u8 reserved_at_40[0x18];
e281682b
SM		 4207 u8 eq_number[0x8];
4208
b4ff3a36 4209 u8 reserved_at_60[0x20];
e281682b
SM		 4210};
4211
4212struct mlx5_ifc_query_dct_out_bits {
4213 u8 status[0x8];
b4ff3a36 4214 u8 reserved_at_8[0x18];
e281682b
SM		 4215
4216 u8 syndrome[0x20];
4217
b4ff3a36 4218 u8 reserved_at_40[0x40];
e281682b
SM		 4219
4220 struct mlx5_ifc_dctc_bits dct_context_entry;
4221
b4ff3a36 4222 u8 reserved_at_280[0x180];
e281682b
SM		 4223};
4224
4225struct mlx5_ifc_query_dct_in_bits {
4226 u8 opcode[0x10];
b4ff3a36 4227 u8 reserved_at_10[0x10];
e281682b 4228
b4ff3a36 4229 u8 reserved_at_20[0x10];
e281682b
SM		 4230 u8 op_mod[0x10];
4231
b4ff3a36 4232 u8 reserved_at_40[0x8];
e281682b
SM		 4233 u8 dctn[0x18];
4234
b4ff3a36 4235 u8 reserved_at_60[0x20];
e281682b
SM		 4236};
4237
4238struct mlx5_ifc_query_cq_out_bits {
4239 u8 status[0x8];
b4ff3a36 4240 u8 reserved_at_8[0x18];
e281682b
SM		 4241
4242 u8 syndrome[0x20];
4243
b4ff3a36 4244 u8 reserved_at_40[0x40];
e281682b
SM		 4245
4246 struct mlx5_ifc_cqc_bits cq_context;
4247
b4ff3a36 4248 u8 reserved_at_280[0x600];
e281682b
SM		 4249
4250 u8 pas[0][0x40];
4251};
4252
4253struct mlx5_ifc_query_cq_in_bits {
4254 u8 opcode[0x10];
b4ff3a36 4255 u8 reserved_at_10[0x10];
e281682b 4256
b4ff3a36 4257 u8 reserved_at_20[0x10];
e281682b
SM		 4258 u8 op_mod[0x10];
4259
b4ff3a36 4260 u8 reserved_at_40[0x8];
e281682b
SM		 4261 u8 cqn[0x18];
4262
b4ff3a36 4263 u8 reserved_at_60[0x20];
e281682b
SM		 4264};
4265
4266struct mlx5_ifc_query_cong_status_out_bits {
4267 u8 status[0x8];
b4ff3a36 4268 u8 reserved_at_8[0x18];
e281682b
SM		 4269
4270 u8 syndrome[0x20];
4271
b4ff3a36 4272 u8 reserved_at_40[0x20];
e281682b
SM		 4273
4274 u8 enable[0x1];
4275 u8 tag_enable[0x1];
b4ff3a36 4276 u8 reserved_at_62[0x1e];
e281682b
SM		 4277};
4278
4279struct mlx5_ifc_query_cong_status_in_bits {
4280 u8 opcode[0x10];
b4ff3a36 4281 u8 reserved_at_10[0x10];
e281682b 4282
b4ff3a36 4283 u8 reserved_at_20[0x10];
e281682b
SM		 4284 u8 op_mod[0x10];
4285
b4ff3a36 4286 u8 reserved_at_40[0x18];
e281682b
SM		 4287 u8 priority[0x4];
4288 u8 cong_protocol[0x4];
4289
b4ff3a36 4290 u8 reserved_at_60[0x20];
e281682b
SM		 4291};
4292
4293struct mlx5_ifc_query_cong_statistics_out_bits {
4294 u8 status[0x8];
b4ff3a36 4295 u8 reserved_at_8[0x18];
e281682b
SM		 4296
4297 u8 syndrome[0x20];
4298
b4ff3a36 4299 u8 reserved_at_40[0x40];
e281682b
SM		 4300
4301 u8 cur_flows[0x20];
4302
4303 u8 sum_flows[0x20];
4304
4305 u8 cnp_ignored_high[0x20];
4306
4307 u8 cnp_ignored_low[0x20];
4308
4309 u8 cnp_handled_high[0x20];
4310
4311 u8 cnp_handled_low[0x20];
4312
b4ff3a36 4313 u8 reserved_at_140[0x100];
e281682b
SM		 4314
4315 u8 time_stamp_high[0x20];
4316
4317 u8 time_stamp_low[0x20];
4318
4319 u8 accumulators_period[0x20];
4320
4321 u8 ecn_marked_roce_packets_high[0x20];
4322
4323 u8 ecn_marked_roce_packets_low[0x20];
4324
4325 u8 cnps_sent_high[0x20];
4326
4327 u8 cnps_sent_low[0x20];
4328
b4ff3a36 4329 u8 reserved_at_320[0x560];
e281682b
SM		 4330};
4331
4332struct mlx5_ifc_query_cong_statistics_in_bits {
4333 u8 opcode[0x10];
b4ff3a36 4334 u8 reserved_at_10[0x10];
e281682b 4335
b4ff3a36 4336 u8 reserved_at_20[0x10];
e281682b
SM		 4337 u8 op_mod[0x10];
4338
4339 u8 clear[0x1];
b4ff3a36 4340 u8 reserved_at_41[0x1f];
e281682b 4341
b4ff3a36 4342 u8 reserved_at_60[0x20];
e281682b
SM		 4343};
4344
4345struct mlx5_ifc_query_cong_params_out_bits {
4346 u8 status[0x8];
b4ff3a36 4347 u8 reserved_at_8[0x18];
e281682b
SM		 4348
4349 u8 syndrome[0x20];
4350
b4ff3a36 4351 u8 reserved_at_40[0x40];
e281682b
SM		 4352
4353 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4354};
4355
4356struct mlx5_ifc_query_cong_params_in_bits {
4357 u8 opcode[0x10];
b4ff3a36 4358 u8 reserved_at_10[0x10];
e281682b 4359
b4ff3a36 4360 u8 reserved_at_20[0x10];
e281682b
SM		 4361 u8 op_mod[0x10];
4362
b4ff3a36 4363 u8 reserved_at_40[0x1c];
e281682b
SM		 4364 u8 cong_protocol[0x4];
4365
b4ff3a36 4366 u8 reserved_at_60[0x20];
e281682b
SM		 4367};
4368
4369struct mlx5_ifc_query_adapter_out_bits {
4370 u8 status[0x8];
b4ff3a36 4371 u8 reserved_at_8[0x18];
e281682b
SM		 4372
4373 u8 syndrome[0x20];
4374
b4ff3a36 4375 u8 reserved_at_40[0x40];
e281682b
SM		 4376
4377 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4378};
4379
4380struct mlx5_ifc_query_adapter_in_bits {
4381 u8 opcode[0x10];
b4ff3a36 4382 u8 reserved_at_10[0x10];
e281682b 4383
b4ff3a36 4384 u8 reserved_at_20[0x10];
e281682b
SM		 4385 u8 op_mod[0x10];
4386
b4ff3a36 4387 u8 reserved_at_40[0x40];
e281682b
SM		 4388};
4389
4390struct mlx5_ifc_qp_2rst_out_bits {
4391 u8 status[0x8];
b4ff3a36 4392 u8 reserved_at_8[0x18];
e281682b
SM		 4393
4394 u8 syndrome[0x20];
4395
b4ff3a36 4396 u8 reserved_at_40[0x40];
e281682b
SM		 4397};
4398
4399struct mlx5_ifc_qp_2rst_in_bits {
4400 u8 opcode[0x10];
b4ff3a36 4401 u8 reserved_at_10[0x10];
e281682b 4402
b4ff3a36 4403 u8 reserved_at_20[0x10];
e281682b
SM		 4404 u8 op_mod[0x10];
4405
b4ff3a36 4406 u8 reserved_at_40[0x8];
e281682b
SM		 4407 u8 qpn[0x18];
4408
b4ff3a36 4409 u8 reserved_at_60[0x20];
e281682b
SM		 4410};
4411
4412struct mlx5_ifc_qp_2err_out_bits {
4413 u8 status[0x8];
b4ff3a36 4414 u8 reserved_at_8[0x18];
e281682b
SM		 4415
4416 u8 syndrome[0x20];
4417
b4ff3a36 4418 u8 reserved_at_40[0x40];
e281682b
SM		 4419};
4420
4421struct mlx5_ifc_qp_2err_in_bits {
4422 u8 opcode[0x10];
b4ff3a36 4423 u8 reserved_at_10[0x10];
e281682b 4424
b4ff3a36 4425 u8 reserved_at_20[0x10];
e281682b
SM		 4426 u8 op_mod[0x10];
4427
b4ff3a36 4428 u8 reserved_at_40[0x8];
e281682b
SM		 4429 u8 qpn[0x18];
4430
b4ff3a36 4431 u8 reserved_at_60[0x20];
e281682b
SM		 4432};
4433
4434struct mlx5_ifc_page_fault_resume_out_bits {
4435 u8 status[0x8];
b4ff3a36 4436 u8 reserved_at_8[0x18];
e281682b
SM		 4437
4438 u8 syndrome[0x20];
4439
b4ff3a36 4440 u8 reserved_at_40[0x40];
e281682b
SM		 4441};
4442
4443struct mlx5_ifc_page_fault_resume_in_bits {
4444 u8 opcode[0x10];
b4ff3a36 4445 u8 reserved_at_10[0x10];
e281682b 4446
b4ff3a36 4447 u8 reserved_at_20[0x10];
e281682b
SM		 4448 u8 op_mod[0x10];
4449
4450 u8 error[0x1];
b4ff3a36 4451 u8 reserved_at_41[0x4];
e281682b
SM		 4452 u8 rdma[0x1];
4453 u8 read_write[0x1];
4454 u8 req_res[0x1];
4455 u8 qpn[0x18];
4456
b4ff3a36 4457 u8 reserved_at_60[0x20];
e281682b
SM		 4458};
4459
4460struct mlx5_ifc_nop_out_bits {
4461 u8 status[0x8];
b4ff3a36 4462 u8 reserved_at_8[0x18];
e281682b
SM		 4463
4464 u8 syndrome[0x20];
4465
b4ff3a36 4466 u8 reserved_at_40[0x40];
e281682b
SM		 4467};
4468
4469struct mlx5_ifc_nop_in_bits {
4470 u8 opcode[0x10];
b4ff3a36 4471 u8 reserved_at_10[0x10];
e281682b 4472
b4ff3a36 4473 u8 reserved_at_20[0x10];
e281682b
SM		 4474 u8 op_mod[0x10];
4475
b4ff3a36 4476 u8 reserved_at_40[0x40];
e281682b
SM		 4477};
4478
4479struct mlx5_ifc_modify_vport_state_out_bits {
4480 u8 status[0x8];
b4ff3a36 4481 u8 reserved_at_8[0x18];
e281682b
SM		 4482
4483 u8 syndrome[0x20];
4484
b4ff3a36 4485 u8 reserved_at_40[0x40];
e281682b
SM		 4486};
4487
4488struct mlx5_ifc_modify_vport_state_in_bits {
4489 u8 opcode[0x10];
b4ff3a36 4490 u8 reserved_at_10[0x10];
e281682b 4491
b4ff3a36 4492 u8 reserved_at_20[0x10];
e281682b
SM		 4493 u8 op_mod[0x10];
4494
4495 u8 other_vport[0x1];
b4ff3a36 4496 u8 reserved_at_41[0xf];
e281682b
SM		 4497 u8 vport_number[0x10];
4498
b4ff3a36 4499 u8 reserved_at_60[0x18];
e281682b 4500 u8 admin_state[0x4];
b4ff3a36 4501 u8 reserved_at_7c[0x4];
e281682b
SM		 4502};
4503
4504struct mlx5_ifc_modify_tis_out_bits {
4505 u8 status[0x8];
b4ff3a36 4506 u8 reserved_at_8[0x18];
e281682b
SM		 4507
4508 u8 syndrome[0x20];
4509
b4ff3a36 4510 u8 reserved_at_40[0x40];
e281682b
SM		 4511};
4512
75850d0b 4513struct mlx5_ifc_modify_tis_bitmask_bits {
b4ff3a36 4514 u8 reserved_at_0[0x20];
75850d0b 4515
b4ff3a36 4516 u8 reserved_at_20[0x1f];
75850d0b 4517 u8 prio[0x1];
4518};
4519
e281682b
SM		 4520struct mlx5_ifc_modify_tis_in_bits {
4521 u8 opcode[0x10];
b4ff3a36 4522 u8 reserved_at_10[0x10];
e281682b 4523
b4ff3a36 4524 u8 reserved_at_20[0x10];
e281682b
SM		 4525 u8 op_mod[0x10];
4526
b4ff3a36 4527 u8 reserved_at_40[0x8];
e281682b
SM		 4528 u8 tisn[0x18];
4529
b4ff3a36 4530 u8 reserved_at_60[0x20];
e281682b 4531
75850d0b 4532 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
e281682b 4533
b4ff3a36 4534 u8 reserved_at_c0[0x40];
e281682b
SM		 4535
4536 struct mlx5_ifc_tisc_bits ctx;
4537};
4538
d9eea403 4539struct mlx5_ifc_modify_tir_bitmask_bits {
b4ff3a36 4540 u8 reserved_at_0[0x20];
d9eea403 4541
b4ff3a36 4542 u8 reserved_at_20[0x1b];
66189961 4543 u8 self_lb_en[0x1];
bdfc028d
TT		 4544 u8 reserved_at_3c[0x1];
4545 u8 hash[0x1];
4546 u8 reserved_at_3e[0x1];
d9eea403
AS		 4547 u8 lro[0x1];
4548};
4549
e281682b
SM		 4550struct mlx5_ifc_modify_tir_out_bits {
4551 u8 status[0x8];
b4ff3a36 4552 u8 reserved_at_8[0x18];
e281682b
SM		 4553
4554 u8 syndrome[0x20];
4555
b4ff3a36 4556 u8 reserved_at_40[0x40];
e281682b
SM		 4557};
4558
4559struct mlx5_ifc_modify_tir_in_bits {
4560 u8 opcode[0x10];
b4ff3a36 4561 u8 reserved_at_10[0x10];
e281682b 4562
b4ff3a36 4563 u8 reserved_at_20[0x10];
e281682b
SM		 4564 u8 op_mod[0x10];
4565
b4ff3a36 4566 u8 reserved_at_40[0x8];
e281682b
SM		 4567 u8 tirn[0x18];
4568
b4ff3a36 4569 u8 reserved_at_60[0x20];
e281682b 4570
d9eea403 4571 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
e281682b 4572
b4ff3a36 4573 u8 reserved_at_c0[0x40];
e281682b
SM		 4574
4575 struct mlx5_ifc_tirc_bits ctx;
4576};
4577
4578struct mlx5_ifc_modify_sq_out_bits {
4579 u8 status[0x8];
b4ff3a36 4580 u8 reserved_at_8[0x18];
e281682b
SM		 4581
4582 u8 syndrome[0x20];
4583
b4ff3a36 4584 u8 reserved_at_40[0x40];
e281682b
SM		 4585};
4586
4587struct mlx5_ifc_modify_sq_in_bits {
4588 u8 opcode[0x10];
b4ff3a36 4589 u8 reserved_at_10[0x10];
e281682b 4590
b4ff3a36 4591 u8 reserved_at_20[0x10];
e281682b
SM		 4592 u8 op_mod[0x10];
4593
4594 u8 sq_state[0x4];
b4ff3a36 4595 u8 reserved_at_44[0x4];
e281682b
SM		 4596 u8 sqn[0x18];
4597
b4ff3a36 4598 u8 reserved_at_60[0x20];
e281682b
SM		 4599
4600 u8 modify_bitmask[0x40];
4601
b4ff3a36 4602 u8 reserved_at_c0[0x40];
e281682b
SM		 4603
4604 struct mlx5_ifc_sqc_bits ctx;
4605};
4606
4607struct mlx5_ifc_modify_rqt_out_bits {
4608 u8 status[0x8];
b4ff3a36 4609 u8 reserved_at_8[0x18];
e281682b
SM		 4610
4611 u8 syndrome[0x20];
4612
b4ff3a36 4613 u8 reserved_at_40[0x40];
e281682b
SM		 4614};
4615
5c50368f 4616struct mlx5_ifc_rqt_bitmask_bits {
b4ff3a36 4617 u8 reserved_at_0[0x20];
5c50368f 4618
b4ff3a36 4619 u8 reserved_at_20[0x1f];
5c50368f
AS		 4620 u8 rqn_list[0x1];
4621};
4622
e281682b
SM		 4623struct mlx5_ifc_modify_rqt_in_bits {
4624 u8 opcode[0x10];
b4ff3a36 4625 u8 reserved_at_10[0x10];
e281682b 4626
b4ff3a36 4627 u8 reserved_at_20[0x10];
e281682b
SM		 4628 u8 op_mod[0x10];
4629
b4ff3a36 4630 u8 reserved_at_40[0x8];
e281682b
SM		 4631 u8 rqtn[0x18];
4632
b4ff3a36 4633 u8 reserved_at_60[0x20];
e281682b 4634
5c50368f 4635 struct mlx5_ifc_rqt_bitmask_bits bitmask;
e281682b 4636
b4ff3a36 4637 u8 reserved_at_c0[0x40];
e281682b
SM		 4638
4639 struct mlx5_ifc_rqtc_bits ctx;
4640};
4641
4642struct mlx5_ifc_modify_rq_out_bits {
4643 u8 status[0x8];
b4ff3a36 4644 u8 reserved_at_8[0x18];
e281682b
SM		 4645
4646 u8 syndrome[0x20];
4647
b4ff3a36 4648 u8 reserved_at_40[0x40];
e281682b
SM		 4649};
4650
4651struct mlx5_ifc_modify_rq_in_bits {
4652 u8 opcode[0x10];
b4ff3a36 4653 u8 reserved_at_10[0x10];
e281682b 4654
b4ff3a36 4655 u8 reserved_at_20[0x10];
e281682b
SM		 4656 u8 op_mod[0x10];
4657
4658 u8 rq_state[0x4];
b4ff3a36 4659 u8 reserved_at_44[0x4];
e281682b
SM		 4660 u8 rqn[0x18];
4661
b4ff3a36 4662 u8 reserved_at_60[0x20];
e281682b
SM		 4663
4664 u8 modify_bitmask[0x40];
4665
b4ff3a36 4666 u8 reserved_at_c0[0x40];
e281682b
SM		 4667
4668 struct mlx5_ifc_rqc_bits ctx;
4669};
4670
4671struct mlx5_ifc_modify_rmp_out_bits {
4672 u8 status[0x8];
b4ff3a36 4673 u8 reserved_at_8[0x18];
e281682b
SM		 4674
4675 u8 syndrome[0x20];
4676
b4ff3a36 4677 u8 reserved_at_40[0x40];
e281682b
SM		 4678};
4679
01949d01 4680struct mlx5_ifc_rmp_bitmask_bits {
b4ff3a36 4681 u8 reserved_at_0[0x20];
01949d01 4682
b4ff3a36 4683 u8 reserved_at_20[0x1f];
01949d01
HA		 4684 u8 lwm[0x1];
4685};
4686
e281682b
SM		 4687struct mlx5_ifc_modify_rmp_in_bits {
4688 u8 opcode[0x10];
b4ff3a36 4689 u8 reserved_at_10[0x10];
e281682b 4690
b4ff3a36 4691 u8 reserved_at_20[0x10];
e281682b
SM		 4692 u8 op_mod[0x10];
4693
4694 u8 rmp_state[0x4];
b4ff3a36 4695 u8 reserved_at_44[0x4];
e281682b
SM		 4696 u8 rmpn[0x18];
4697
b4ff3a36 4698 u8 reserved_at_60[0x20];
e281682b 4699
01949d01 4700 struct mlx5_ifc_rmp_bitmask_bits bitmask;
e281682b 4701
b4ff3a36 4702 u8 reserved_at_c0[0x40];
e281682b
SM		 4703
4704 struct mlx5_ifc_rmpc_bits ctx;
4705};
4706
4707struct mlx5_ifc_modify_nic_vport_context_out_bits {
4708 u8 status[0x8];
b4ff3a36 4709 u8 reserved_at_8[0x18];
e281682b
SM		 4710
4711 u8 syndrome[0x20];
4712
b4ff3a36 4713 u8 reserved_at_40[0x40];
e281682b
SM		 4714};
4715
4716struct mlx5_ifc_modify_nic_vport_field_select_bits {
23898c76
NO		 4717 u8 reserved_at_0[0x16];
4718 u8 node_guid[0x1];
4719 u8 port_guid[0x1];
4720 u8 reserved_at_18[0x1];
d82b7318
SM		 4721 u8 mtu[0x1];
4722 u8 change_event[0x1];
4723 u8 promisc[0x1];
e281682b
SM		 4724 u8 permanent_address[0x1];
4725 u8 addresses_list[0x1];
4726 u8 roce_en[0x1];
b4ff3a36 4727 u8 reserved_at_1f[0x1];
e281682b
SM		 4728};
4729
4730struct mlx5_ifc_modify_nic_vport_context_in_bits {
4731 u8 opcode[0x10];
b4ff3a36 4732 u8 reserved_at_10[0x10];
e281682b 4733
b4ff3a36 4734 u8 reserved_at_20[0x10];
e281682b
SM		 4735 u8 op_mod[0x10];
4736
4737 u8 other_vport[0x1];
b4ff3a36 4738 u8 reserved_at_41[0xf];
e281682b
SM		 4739 u8 vport_number[0x10];
4740
4741 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
4742
b4ff3a36 4743 u8 reserved_at_80[0x780];
e281682b
SM		 4744
4745 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4746};
4747
4748struct mlx5_ifc_modify_hca_vport_context_out_bits {
4749 u8 status[0x8];
b4ff3a36 4750 u8 reserved_at_8[0x18];
e281682b
SM		 4751
4752 u8 syndrome[0x20];
4753
b4ff3a36 4754 u8 reserved_at_40[0x40];
e281682b
SM		 4755};
4756
4757struct mlx5_ifc_modify_hca_vport_context_in_bits {
4758 u8 opcode[0x10];
b4ff3a36 4759 u8 reserved_at_10[0x10];
e281682b 4760
b4ff3a36 4761 u8 reserved_at_20[0x10];
e281682b
SM		 4762 u8 op_mod[0x10];
4763
4764 u8 other_vport[0x1];
b4ff3a36 4765 u8 reserved_at_41[0xb];
707c4602 4766 u8 port_num[0x4];
e281682b
SM		 4767 u8 vport_number[0x10];
4768
b4ff3a36 4769 u8 reserved_at_60[0x20];
e281682b
SM		 4770
4771 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4772};
4773
4774struct mlx5_ifc_modify_cq_out_bits {
4775 u8 status[0x8];
b4ff3a36 4776 u8 reserved_at_8[0x18];
e281682b
SM		 4777
4778 u8 syndrome[0x20];
4779
b4ff3a36 4780 u8 reserved_at_40[0x40];
e281682b
SM		 4781};
4782
4783enum {
4784 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
4785 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
4786};
4787
4788struct mlx5_ifc_modify_cq_in_bits {
4789 u8 opcode[0x10];
b4ff3a36 4790 u8 reserved_at_10[0x10];
e281682b 4791
b4ff3a36 4792 u8 reserved_at_20[0x10];
e281682b
SM		 4793 u8 op_mod[0x10];
4794
b4ff3a36 4795 u8 reserved_at_40[0x8];
e281682b
SM		 4796 u8 cqn[0x18];
4797
4798 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
4799
4800 struct mlx5_ifc_cqc_bits cq_context;
4801
b4ff3a36 4802 u8 reserved_at_280[0x600];
e281682b
SM		 4803
4804 u8 pas[0][0x40];
4805};
4806
4807struct mlx5_ifc_modify_cong_status_out_bits {
4808 u8 status[0x8];
b4ff3a36 4809 u8 reserved_at_8[0x18];
e281682b
SM		 4810
4811 u8 syndrome[0x20];
4812
b4ff3a36 4813 u8 reserved_at_40[0x40];
e281682b
SM		 4814};
4815
4816struct mlx5_ifc_modify_cong_status_in_bits {
4817 u8 opcode[0x10];
b4ff3a36 4818 u8 reserved_at_10[0x10];
e281682b 4819
b4ff3a36 4820 u8 reserved_at_20[0x10];
e281682b
SM		 4821 u8 op_mod[0x10];
4822
b4ff3a36 4823 u8 reserved_at_40[0x18];
e281682b
SM		 4824 u8 priority[0x4];
4825 u8 cong_protocol[0x4];
4826
4827 u8 enable[0x1];
4828 u8 tag_enable[0x1];
b4ff3a36 4829 u8 reserved_at_62[0x1e];
e281682b
SM		 4830};
4831
4832struct mlx5_ifc_modify_cong_params_out_bits {
4833 u8 status[0x8];
b4ff3a36 4834 u8 reserved_at_8[0x18];
e281682b
SM		 4835
4836 u8 syndrome[0x20];
4837
b4ff3a36 4838 u8 reserved_at_40[0x40];
e281682b
SM		 4839};
4840
4841struct mlx5_ifc_modify_cong_params_in_bits {
4842 u8 opcode[0x10];
b4ff3a36 4843 u8 reserved_at_10[0x10];
e281682b 4844
b4ff3a36 4845 u8 reserved_at_20[0x10];
e281682b
SM		 4846 u8 op_mod[0x10];
4847
b4ff3a36 4848 u8 reserved_at_40[0x1c];
e281682b
SM		 4849 u8 cong_protocol[0x4];
4850
4851 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
4852
b4ff3a36 4853 u8 reserved_at_80[0x80];
e281682b
SM		 4854
4855 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4856};
4857
4858struct mlx5_ifc_manage_pages_out_bits {
4859 u8 status[0x8];
b4ff3a36 4860 u8 reserved_at_8[0x18];
e281682b
SM		 4861
4862 u8 syndrome[0x20];
4863
4864 u8 output_num_entries[0x20];
4865
b4ff3a36 4866 u8 reserved_at_60[0x20];
e281682b
SM		 4867
4868 u8 pas[0][0x40];
4869};
4870
4871enum {
4872 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
4873 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
4874 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
4875};
4876
4877struct mlx5_ifc_manage_pages_in_bits {
4878 u8 opcode[0x10];
b4ff3a36 4879 u8 reserved_at_10[0x10];
e281682b 4880
b4ff3a36 4881 u8 reserved_at_20[0x10];
e281682b
SM		 4882 u8 op_mod[0x10];
4883
b4ff3a36 4884 u8 reserved_at_40[0x10];
e281682b
SM		 4885 u8 function_id[0x10];
4886
4887 u8 input_num_entries[0x20];
4888
4889 u8 pas[0][0x40];
4890};
4891
4892struct mlx5_ifc_mad_ifc_out_bits {
4893 u8 status[0x8];
b4ff3a36 4894 u8 reserved_at_8[0x18];
e281682b
SM		 4895
4896 u8 syndrome[0x20];
4897
b4ff3a36 4898 u8 reserved_at_40[0x40];
e281682b
SM		 4899
4900 u8 response_mad_packet[256][0x8];
4901};
4902
4903struct mlx5_ifc_mad_ifc_in_bits {
4904 u8 opcode[0x10];
b4ff3a36 4905 u8 reserved_at_10[0x10];
e281682b 4906
b4ff3a36 4907 u8 reserved_at_20[0x10];
e281682b
SM		 4908 u8 op_mod[0x10];
4909
4910 u8 remote_lid[0x10];
b4ff3a36 4911 u8 reserved_at_50[0x8];
e281682b
SM		 4912 u8 port[0x8];
4913
b4ff3a36 4914 u8 reserved_at_60[0x20];
e281682b
SM		 4915
4916 u8 mad[256][0x8];
4917};
4918
4919struct mlx5_ifc_init_hca_out_bits {
4920 u8 status[0x8];
b4ff3a36 4921 u8 reserved_at_8[0x18];
e281682b
SM		 4922
4923 u8 syndrome[0x20];
4924
b4ff3a36 4925 u8 reserved_at_40[0x40];
e281682b
SM		 4926};
4927
4928struct mlx5_ifc_init_hca_in_bits {
4929 u8 opcode[0x10];
b4ff3a36 4930 u8 reserved_at_10[0x10];
e281682b 4931
b4ff3a36 4932 u8 reserved_at_20[0x10];
e281682b
SM		 4933 u8 op_mod[0x10];
4934
b4ff3a36 4935 u8 reserved_at_40[0x40];
e281682b
SM		 4936};
4937
4938struct mlx5_ifc_init2rtr_qp_out_bits {
4939 u8 status[0x8];
b4ff3a36 4940 u8 reserved_at_8[0x18];
e281682b
SM		 4941
4942 u8 syndrome[0x20];
4943
b4ff3a36 4944 u8 reserved_at_40[0x40];
e281682b
SM		 4945};
4946
4947struct mlx5_ifc_init2rtr_qp_in_bits {
4948 u8 opcode[0x10];
b4ff3a36 4949 u8 reserved_at_10[0x10];
e281682b 4950
b4ff3a36 4951 u8 reserved_at_20[0x10];
e281682b
SM		 4952 u8 op_mod[0x10];
4953
b4ff3a36 4954 u8 reserved_at_40[0x8];
e281682b
SM		 4955 u8 qpn[0x18];
4956
b4ff3a36 4957 u8 reserved_at_60[0x20];
e281682b
SM		 4958
4959 u8 opt_param_mask[0x20];
4960
b4ff3a36 4961 u8 reserved_at_a0[0x20];
e281682b
SM		 4962
4963 struct mlx5_ifc_qpc_bits qpc;
4964
b4ff3a36 4965 u8 reserved_at_800[0x80];
e281682b
SM		 4966};
4967
4968struct mlx5_ifc_init2init_qp_out_bits {
4969 u8 status[0x8];
b4ff3a36 4970 u8 reserved_at_8[0x18];
e281682b
SM		 4971
4972 u8 syndrome[0x20];
4973
b4ff3a36 4974 u8 reserved_at_40[0x40];
e281682b
SM		 4975};
4976
4977struct mlx5_ifc_init2init_qp_in_bits {
4978 u8 opcode[0x10];
b4ff3a36 4979 u8 reserved_at_10[0x10];
e281682b 4980
b4ff3a36 4981 u8 reserved_at_20[0x10];
e281682b
SM		 4982 u8 op_mod[0x10];
4983
b4ff3a36 4984 u8 reserved_at_40[0x8];
e281682b
SM		 4985 u8 qpn[0x18];
4986
b4ff3a36 4987 u8 reserved_at_60[0x20];
e281682b
SM		 4988
4989 u8 opt_param_mask[0x20];
4990
b4ff3a36 4991 u8 reserved_at_a0[0x20];
e281682b
SM		 4992
4993 struct mlx5_ifc_qpc_bits qpc;
4994
b4ff3a36 4995 u8 reserved_at_800[0x80];
e281682b
SM		 4996};
4997
4998struct mlx5_ifc_get_dropped_packet_log_out_bits {
4999 u8 status[0x8];
b4ff3a36 5000 u8 reserved_at_8[0x18];
e281682b
SM		 5001
5002 u8 syndrome[0x20];
5003
b4ff3a36 5004 u8 reserved_at_40[0x40];
e281682b
SM		 5005
5006 u8 packet_headers_log[128][0x8];
5007
5008 u8 packet_syndrome[64][0x8];
5009};
5010
5011struct mlx5_ifc_get_dropped_packet_log_in_bits {
5012 u8 opcode[0x10];
b4ff3a36 5013 u8 reserved_at_10[0x10];
e281682b 5014
b4ff3a36 5015 u8 reserved_at_20[0x10];
e281682b
SM		 5016 u8 op_mod[0x10];
5017
b4ff3a36 5018 u8 reserved_at_40[0x40];
e281682b
SM		 5019};
5020
5021struct mlx5_ifc_gen_eqe_in_bits {
5022 u8 opcode[0x10];
b4ff3a36 5023 u8 reserved_at_10[0x10];
e281682b 5024
b4ff3a36 5025 u8 reserved_at_20[0x10];
e281682b
SM		 5026 u8 op_mod[0x10];
5027
b4ff3a36 5028 u8 reserved_at_40[0x18];
e281682b
SM		 5029 u8 eq_number[0x8];
5030
b4ff3a36 5031 u8 reserved_at_60[0x20];
e281682b
SM		 5032
5033 u8 eqe[64][0x8];
5034};
5035
5036struct mlx5_ifc_gen_eq_out_bits {
5037 u8 status[0x8];
b4ff3a36 5038 u8 reserved_at_8[0x18];
e281682b
SM		 5039
5040 u8 syndrome[0x20];
5041
b4ff3a36 5042 u8 reserved_at_40[0x40];
e281682b
SM		 5043};
5044
5045struct mlx5_ifc_enable_hca_out_bits {
5046 u8 status[0x8];
b4ff3a36 5047 u8 reserved_at_8[0x18];
e281682b
SM		 5048
5049 u8 syndrome[0x20];
5050
b4ff3a36 5051 u8 reserved_at_40[0x20];
e281682b
SM		 5052};
5053
5054struct mlx5_ifc_enable_hca_in_bits {
5055 u8 opcode[0x10];
b4ff3a36 5056 u8 reserved_at_10[0x10];
e281682b 5057
b4ff3a36 5058 u8 reserved_at_20[0x10];
e281682b
SM		 5059 u8 op_mod[0x10];
5060
b4ff3a36 5061 u8 reserved_at_40[0x10];
e281682b
SM		 5062 u8 function_id[0x10];
5063
b4ff3a36 5064 u8 reserved_at_60[0x20];
e281682b
SM		 5065};
5066
5067struct mlx5_ifc_drain_dct_out_bits {
5068 u8 status[0x8];
b4ff3a36 5069 u8 reserved_at_8[0x18];
e281682b
SM		 5070
5071 u8 syndrome[0x20];
5072
b4ff3a36 5073 u8 reserved_at_40[0x40];
e281682b
SM		 5074};
5075
5076struct mlx5_ifc_drain_dct_in_bits {
5077 u8 opcode[0x10];
b4ff3a36 5078 u8 reserved_at_10[0x10];
e281682b 5079
b4ff3a36 5080 u8 reserved_at_20[0x10];
e281682b
SM		 5081 u8 op_mod[0x10];
5082
b4ff3a36 5083 u8 reserved_at_40[0x8];
e281682b
SM		 5084 u8 dctn[0x18];
5085
b4ff3a36 5086 u8 reserved_at_60[0x20];
e281682b
SM		 5087};
5088
5089struct mlx5_ifc_disable_hca_out_bits {
5090 u8 status[0x8];
b4ff3a36 5091 u8 reserved_at_8[0x18];
e281682b
SM		 5092
5093 u8 syndrome[0x20];
5094
b4ff3a36 5095 u8 reserved_at_40[0x20];
e281682b
SM		 5096};
5097
5098struct mlx5_ifc_disable_hca_in_bits {
5099 u8 opcode[0x10];
b4ff3a36 5100 u8 reserved_at_10[0x10];
e281682b 5101
b4ff3a36 5102 u8 reserved_at_20[0x10];
e281682b
SM		 5103 u8 op_mod[0x10];
5104
b4ff3a36 5105 u8 reserved_at_40[0x10];
e281682b
SM		 5106 u8 function_id[0x10];
5107
b4ff3a36 5108 u8 reserved_at_60[0x20];
e281682b
SM		 5109};
5110
5111struct mlx5_ifc_detach_from_mcg_out_bits {
5112 u8 status[0x8];
b4ff3a36 5113 u8 reserved_at_8[0x18];
e281682b
SM		 5114
5115 u8 syndrome[0x20];
5116
b4ff3a36 5117 u8 reserved_at_40[0x40];
e281682b
SM		 5118};
5119
5120struct mlx5_ifc_detach_from_mcg_in_bits {
5121 u8 opcode[0x10];
b4ff3a36 5122 u8 reserved_at_10[0x10];
e281682b 5123
b4ff3a36 5124 u8 reserved_at_20[0x10];
e281682b
SM		 5125 u8 op_mod[0x10];
5126
b4ff3a36 5127 u8 reserved_at_40[0x8];
e281682b
SM		 5128 u8 qpn[0x18];
5129
b4ff3a36 5130 u8 reserved_at_60[0x20];
e281682b
SM		 5131
5132 u8 multicast_gid[16][0x8];
5133};
5134
7486216b
SM		 5135struct mlx5_ifc_destroy_xrq_out_bits {
5136 u8 status[0x8];
5137 u8 reserved_at_8[0x18];
5138
5139 u8 syndrome[0x20];
5140
5141 u8 reserved_at_40[0x40];
5142};
5143
5144struct mlx5_ifc_destroy_xrq_in_bits {
5145 u8 opcode[0x10];
5146 u8 reserved_at_10[0x10];
5147
5148 u8 reserved_at_20[0x10];
5149 u8 op_mod[0x10];
5150
5151 u8 reserved_at_40[0x8];
5152 u8 xrqn[0x18];
5153
5154 u8 reserved_at_60[0x20];
5155};
5156
e281682b
SM		 5157struct mlx5_ifc_destroy_xrc_srq_out_bits {
5158 u8 status[0x8];
b4ff3a36 5159 u8 reserved_at_8[0x18];
e281682b
SM		 5160
5161 u8 syndrome[0x20];
5162
b4ff3a36 5163 u8 reserved_at_40[0x40];
e281682b
SM		 5164};
5165
5166struct mlx5_ifc_destroy_xrc_srq_in_bits {
5167 u8 opcode[0x10];
b4ff3a36 5168 u8 reserved_at_10[0x10];
e281682b 5169
b4ff3a36 5170 u8 reserved_at_20[0x10];
e281682b
SM		 5171 u8 op_mod[0x10];
5172
b4ff3a36 5173 u8 reserved_at_40[0x8];
e281682b
SM		 5174 u8 xrc_srqn[0x18];
5175
b4ff3a36 5176 u8 reserved_at_60[0x20];
e281682b
SM		 5177};
5178
5179struct mlx5_ifc_destroy_tis_out_bits {
5180 u8 status[0x8];
b4ff3a36 5181 u8 reserved_at_8[0x18];
e281682b
SM		 5182
5183 u8 syndrome[0x20];
5184
b4ff3a36 5185 u8 reserved_at_40[0x40];
e281682b
SM		 5186};
5187
5188struct mlx5_ifc_destroy_tis_in_bits {
5189 u8 opcode[0x10];
b4ff3a36 5190 u8 reserved_at_10[0x10];
e281682b 5191
b4ff3a36 5192 u8 reserved_at_20[0x10];
e281682b
SM		 5193 u8 op_mod[0x10];
5194
b4ff3a36 5195 u8 reserved_at_40[0x8];
e281682b
SM		 5196 u8 tisn[0x18];
5197
b4ff3a36 5198 u8 reserved_at_60[0x20];
e281682b
SM		 5199};
5200
5201struct mlx5_ifc_destroy_tir_out_bits {
5202 u8 status[0x8];
b4ff3a36 5203 u8 reserved_at_8[0x18];
e281682b
SM		 5204
5205 u8 syndrome[0x20];
5206
b4ff3a36 5207 u8 reserved_at_40[0x40];
e281682b
SM		 5208};
5209
5210struct mlx5_ifc_destroy_tir_in_bits {
5211 u8 opcode[0x10];
b4ff3a36 5212 u8 reserved_at_10[0x10];
e281682b 5213
b4ff3a36 5214 u8 reserved_at_20[0x10];
e281682b
SM		 5215 u8 op_mod[0x10];
5216
b4ff3a36 5217 u8 reserved_at_40[0x8];
e281682b
SM		 5218 u8 tirn[0x18];
5219
b4ff3a36 5220 u8 reserved_at_60[0x20];
e281682b
SM		 5221};
5222
5223struct mlx5_ifc_destroy_srq_out_bits {
5224 u8 status[0x8];
b4ff3a36 5225 u8 reserved_at_8[0x18];
e281682b
SM		 5226
5227 u8 syndrome[0x20];
5228
b4ff3a36 5229 u8 reserved_at_40[0x40];
e281682b
SM		 5230};
5231
5232struct mlx5_ifc_destroy_srq_in_bits {
5233 u8 opcode[0x10];
b4ff3a36 5234 u8 reserved_at_10[0x10];
e281682b 5235
b4ff3a36 5236 u8 reserved_at_20[0x10];
e281682b
SM		 5237 u8 op_mod[0x10];
5238
b4ff3a36 5239 u8 reserved_at_40[0x8];
e281682b
SM		 5240 u8 srqn[0x18];
5241
b4ff3a36 5242 u8 reserved_at_60[0x20];
e281682b
SM		 5243};
5244
5245struct mlx5_ifc_destroy_sq_out_bits {
5246 u8 status[0x8];
b4ff3a36 5247 u8 reserved_at_8[0x18];
e281682b
SM		 5248
5249 u8 syndrome[0x20];
5250
b4ff3a36 5251 u8 reserved_at_40[0x40];
e281682b
SM		 5252};
5253
5254struct mlx5_ifc_destroy_sq_in_bits {
5255 u8 opcode[0x10];
b4ff3a36 5256 u8 reserved_at_10[0x10];
e281682b 5257
b4ff3a36 5258 u8 reserved_at_20[0x10];
e281682b
SM		 5259 u8 op_mod[0x10];
5260
b4ff3a36 5261 u8 reserved_at_40[0x8];
e281682b
SM		 5262 u8 sqn[0x18];
5263
b4ff3a36 5264 u8 reserved_at_60[0x20];
e281682b
SM		 5265};
5266
5267struct mlx5_ifc_destroy_rqt_out_bits {
5268 u8 status[0x8];
b4ff3a36 5269 u8 reserved_at_8[0x18];
e281682b
SM		 5270
5271 u8 syndrome[0x20];
5272
b4ff3a36 5273 u8 reserved_at_40[0x40];
e281682b
SM		 5274};
5275
5276struct mlx5_ifc_destroy_rqt_in_bits {
5277 u8 opcode[0x10];
b4ff3a36 5278 u8 reserved_at_10[0x10];
e281682b 5279
b4ff3a36 5280 u8 reserved_at_20[0x10];
e281682b
SM		 5281 u8 op_mod[0x10];
5282
b4ff3a36 5283 u8 reserved_at_40[0x8];
e281682b
SM		 5284 u8 rqtn[0x18];
5285
b4ff3a36 5286 u8 reserved_at_60[0x20];
e281682b
SM		 5287};
5288
5289struct mlx5_ifc_destroy_rq_out_bits {
5290 u8 status[0x8];
b4ff3a36 5291 u8 reserved_at_8[0x18];
e281682b
SM		 5292
5293 u8 syndrome[0x20];
5294
b4ff3a36 5295 u8 reserved_at_40[0x40];
e281682b
SM		 5296};
5297
5298struct mlx5_ifc_destroy_rq_in_bits {
5299 u8 opcode[0x10];
b4ff3a36 5300 u8 reserved_at_10[0x10];
e281682b 5301
b4ff3a36 5302 u8 reserved_at_20[0x10];
e281682b
SM		 5303 u8 op_mod[0x10];
5304
b4ff3a36 5305 u8 reserved_at_40[0x8];
e281682b
SM		 5306 u8 rqn[0x18];
5307
b4ff3a36 5308 u8 reserved_at_60[0x20];
e281682b
SM		 5309};
5310
5311struct mlx5_ifc_destroy_rmp_out_bits {
5312 u8 status[0x8];
b4ff3a36 5313 u8 reserved_at_8[0x18];
e281682b
SM		 5314
5315 u8 syndrome[0x20];
5316
b4ff3a36 5317 u8 reserved_at_40[0x40];
e281682b
SM		 5318};
5319
5320struct mlx5_ifc_destroy_rmp_in_bits {
5321 u8 opcode[0x10];
b4ff3a36 5322 u8 reserved_at_10[0x10];
e281682b 5323
b4ff3a36 5324 u8 reserved_at_20[0x10];
e281682b
SM		 5325 u8 op_mod[0x10];
5326
b4ff3a36 5327 u8 reserved_at_40[0x8];
e281682b
SM		 5328 u8 rmpn[0x18];
5329
b4ff3a36 5330 u8 reserved_at_60[0x20];
e281682b
SM		 5331};
5332
5333struct mlx5_ifc_destroy_qp_out_bits {
5334 u8 status[0x8];
b4ff3a36 5335 u8 reserved_at_8[0x18];
e281682b
SM		 5336
5337 u8 syndrome[0x20];
5338
b4ff3a36 5339 u8 reserved_at_40[0x40];
e281682b
SM		 5340};
5341
5342struct mlx5_ifc_destroy_qp_in_bits {
5343 u8 opcode[0x10];
b4ff3a36 5344 u8 reserved_at_10[0x10];
e281682b 5345
b4ff3a36 5346 u8 reserved_at_20[0x10];
e281682b
SM		 5347 u8 op_mod[0x10];
5348
b4ff3a36 5349 u8 reserved_at_40[0x8];
e281682b
SM		 5350 u8 qpn[0x18];
5351
b4ff3a36 5352 u8 reserved_at_60[0x20];
e281682b
SM		 5353};
5354
5355struct mlx5_ifc_destroy_psv_out_bits {
5356 u8 status[0x8];
b4ff3a36 5357 u8 reserved_at_8[0x18];
e281682b
SM		 5358
5359 u8 syndrome[0x20];
5360
b4ff3a36 5361 u8 reserved_at_40[0x40];
e281682b
SM		 5362};
5363
5364struct mlx5_ifc_destroy_psv_in_bits {
5365 u8 opcode[0x10];
b4ff3a36 5366 u8 reserved_at_10[0x10];
e281682b 5367
b4ff3a36 5368 u8 reserved_at_20[0x10];
e281682b
SM		 5369 u8 op_mod[0x10];
5370
b4ff3a36 5371 u8 reserved_at_40[0x8];
e281682b
SM		 5372 u8 psvn[0x18];
5373
b4ff3a36 5374 u8 reserved_at_60[0x20];
e281682b
SM		 5375};
5376
5377struct mlx5_ifc_destroy_mkey_out_bits {
5378 u8 status[0x8];
b4ff3a36 5379 u8 reserved_at_8[0x18];
e281682b
SM		 5380
5381 u8 syndrome[0x20];
5382
b4ff3a36 5383 u8 reserved_at_40[0x40];
e281682b
SM		 5384};
5385
5386struct mlx5_ifc_destroy_mkey_in_bits {
5387 u8 opcode[0x10];
b4ff3a36 5388 u8 reserved_at_10[0x10];
e281682b 5389
b4ff3a36 5390 u8 reserved_at_20[0x10];
e281682b
SM		 5391 u8 op_mod[0x10];
5392
b4ff3a36 5393 u8 reserved_at_40[0x8];
e281682b
SM		 5394 u8 mkey_index[0x18];
5395
b4ff3a36 5396 u8 reserved_at_60[0x20];
e281682b
SM		 5397};
5398
5399struct mlx5_ifc_destroy_flow_table_out_bits {
5400 u8 status[0x8];
b4ff3a36 5401 u8 reserved_at_8[0x18];
e281682b
SM		 5402
5403 u8 syndrome[0x20];
5404
b4ff3a36 5405 u8 reserved_at_40[0x40];
e281682b
SM		 5406};
5407
5408struct mlx5_ifc_destroy_flow_table_in_bits {
5409 u8 opcode[0x10];
b4ff3a36 5410 u8 reserved_at_10[0x10];
e281682b 5411
b4ff3a36 5412 u8 reserved_at_20[0x10];
e281682b
SM		 5413 u8 op_mod[0x10];
5414
7d5e1423
SM		 5415 u8 other_vport[0x1];
5416 u8 reserved_at_41[0xf];
5417 u8 vport_number[0x10];
5418
5419 u8 reserved_at_60[0x20];
e281682b
SM		 5420
5421 u8 table_type[0x8];
b4ff3a36 5422 u8 reserved_at_88[0x18];
e281682b 5423
b4ff3a36 5424 u8 reserved_at_a0[0x8];
e281682b
SM		 5425 u8 table_id[0x18];
5426
b4ff3a36 5427 u8 reserved_at_c0[0x140];
e281682b
SM		 5428};
5429
5430struct mlx5_ifc_destroy_flow_group_out_bits {
5431 u8 status[0x8];
b4ff3a36 5432 u8 reserved_at_8[0x18];
e281682b
SM		 5433
5434 u8 syndrome[0x20];
5435
b4ff3a36 5436 u8 reserved_at_40[0x40];
e281682b
SM		 5437};
5438
5439struct mlx5_ifc_destroy_flow_group_in_bits {
5440 u8 opcode[0x10];
b4ff3a36 5441 u8 reserved_at_10[0x10];
e281682b 5442
b4ff3a36 5443 u8 reserved_at_20[0x10];
e281682b
SM		 5444 u8 op_mod[0x10];
5445
7d5e1423
SM		 5446 u8 other_vport[0x1];
5447 u8 reserved_at_41[0xf];
5448 u8 vport_number[0x10];
5449
5450 u8 reserved_at_60[0x20];
e281682b
SM		 5451
5452 u8 table_type[0x8];
b4ff3a36 5453 u8 reserved_at_88[0x18];
e281682b 5454
b4ff3a36 5455 u8 reserved_at_a0[0x8];
e281682b
SM		 5456 u8 table_id[0x18];
5457
5458 u8 group_id[0x20];
5459
b4ff3a36 5460 u8 reserved_at_e0[0x120];
e281682b
SM		 5461};
5462
5463struct mlx5_ifc_destroy_eq_out_bits {
5464 u8 status[0x8];
b4ff3a36 5465 u8 reserved_at_8[0x18];
e281682b
SM		 5466
5467 u8 syndrome[0x20];
5468
b4ff3a36 5469 u8 reserved_at_40[0x40];
e281682b
SM		 5470};
5471
5472struct mlx5_ifc_destroy_eq_in_bits {
5473 u8 opcode[0x10];
b4ff3a36 5474 u8 reserved_at_10[0x10];
e281682b 5475
b4ff3a36 5476 u8 reserved_at_20[0x10];
e281682b
SM		 5477 u8 op_mod[0x10];
5478
b4ff3a36 5479 u8 reserved_at_40[0x18];
e281682b
SM		 5480 u8 eq_number[0x8];
5481
b4ff3a36 5482 u8 reserved_at_60[0x20];
e281682b
SM		 5483};
5484
5485struct mlx5_ifc_destroy_dct_out_bits {
5486 u8 status[0x8];
b4ff3a36 5487 u8 reserved_at_8[0x18];
e281682b
SM		 5488
5489 u8 syndrome[0x20];
5490
b4ff3a36 5491 u8 reserved_at_40[0x40];
e281682b
SM		 5492};
5493
5494struct mlx5_ifc_destroy_dct_in_bits {
5495 u8 opcode[0x10];
b4ff3a36 5496 u8 reserved_at_10[0x10];
e281682b 5497
b4ff3a36 5498 u8 reserved_at_20[0x10];
e281682b
SM		 5499 u8 op_mod[0x10];
5500
b4ff3a36 5501 u8 reserved_at_40[0x8];
e281682b
SM		 5502 u8 dctn[0x18];
5503
b4ff3a36 5504 u8 reserved_at_60[0x20];
e281682b
SM		 5505};
5506
5507struct mlx5_ifc_destroy_cq_out_bits {
5508 u8 status[0x8];
b4ff3a36 5509 u8 reserved_at_8[0x18];
e281682b
SM		 5510
5511 u8 syndrome[0x20];
5512
b4ff3a36 5513 u8 reserved_at_40[0x40];
e281682b
SM		 5514};
5515
5516struct mlx5_ifc_destroy_cq_in_bits {
5517 u8 opcode[0x10];
b4ff3a36 5518 u8 reserved_at_10[0x10];
e281682b 5519
b4ff3a36 5520 u8 reserved_at_20[0x10];
e281682b
SM		 5521 u8 op_mod[0x10];
5522
b4ff3a36 5523 u8 reserved_at_40[0x8];
e281682b
SM		 5524 u8 cqn[0x18];
5525
b4ff3a36 5526 u8 reserved_at_60[0x20];
e281682b
SM		 5527};
5528
5529struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
5530 u8 status[0x8];
b4ff3a36 5531 u8 reserved_at_8[0x18];
e281682b
SM		 5532
5533 u8 syndrome[0x20];
5534
b4ff3a36 5535 u8 reserved_at_40[0x40];
e281682b
SM		 5536};
5537
5538struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
5539 u8 opcode[0x10];
b4ff3a36 5540 u8 reserved_at_10[0x10];
e281682b 5541
b4ff3a36 5542 u8 reserved_at_20[0x10];
e281682b
SM		 5543 u8 op_mod[0x10];
5544
b4ff3a36 5545 u8 reserved_at_40[0x20];
e281682b 5546
b4ff3a36 5547 u8 reserved_at_60[0x10];
e281682b
SM		 5548 u8 vxlan_udp_port[0x10];
5549};
5550
5551struct mlx5_ifc_delete_l2_table_entry_out_bits {
5552 u8 status[0x8];
b4ff3a36 5553 u8 reserved_at_8[0x18];
e281682b
SM		 5554
5555 u8 syndrome[0x20];
5556
b4ff3a36 5557 u8 reserved_at_40[0x40];
e281682b
SM		 5558};
5559
5560struct mlx5_ifc_delete_l2_table_entry_in_bits {
5561 u8 opcode[0x10];
b4ff3a36 5562 u8 reserved_at_10[0x10];
e281682b 5563
b4ff3a36 5564 u8 reserved_at_20[0x10];
e281682b
SM		 5565 u8 op_mod[0x10];
5566
b4ff3a36 5567 u8 reserved_at_40[0x60];
e281682b 5568
b4ff3a36 5569 u8 reserved_at_a0[0x8];
e281682b
SM		 5570 u8 table_index[0x18];
5571
b4ff3a36 5572 u8 reserved_at_c0[0x140];
e281682b
SM		 5573};
5574
5575struct mlx5_ifc_delete_fte_out_bits {
5576 u8 status[0x8];
b4ff3a36 5577 u8 reserved_at_8[0x18];
e281682b
SM		 5578
5579 u8 syndrome[0x20];
5580
b4ff3a36 5581 u8 reserved_at_40[0x40];
e281682b
SM		 5582};
5583
5584struct mlx5_ifc_delete_fte_in_bits {
5585 u8 opcode[0x10];
b4ff3a36 5586 u8 reserved_at_10[0x10];
e281682b 5587
b4ff3a36 5588 u8 reserved_at_20[0x10];
e281682b
SM		 5589 u8 op_mod[0x10];
5590
7d5e1423
SM		 5591 u8 other_vport[0x1];
5592 u8 reserved_at_41[0xf];
5593 u8 vport_number[0x10];
5594
5595 u8 reserved_at_60[0x20];
e281682b
SM		 5596
5597 u8 table_type[0x8];
b4ff3a36 5598 u8 reserved_at_88[0x18];
e281682b 5599
b4ff3a36 5600 u8 reserved_at_a0[0x8];
e281682b
SM		 5601 u8 table_id[0x18];
5602
b4ff3a36 5603 u8 reserved_at_c0[0x40];
e281682b
SM		 5604
5605 u8 flow_index[0x20];
5606
b4ff3a36 5607 u8 reserved_at_120[0xe0];
e281682b
SM		 5608};
5609
5610struct mlx5_ifc_dealloc_xrcd_out_bits {
5611 u8 status[0x8];
b4ff3a36 5612 u8 reserved_at_8[0x18];
e281682b
SM		 5613
5614 u8 syndrome[0x20];
5615
b4ff3a36 5616 u8 reserved_at_40[0x40];
e281682b
SM		 5617};
5618
5619struct mlx5_ifc_dealloc_xrcd_in_bits {
5620 u8 opcode[0x10];
b4ff3a36 5621 u8 reserved_at_10[0x10];
e281682b 5622
b4ff3a36 5623 u8 reserved_at_20[0x10];
e281682b
SM		 5624 u8 op_mod[0x10];
5625
b4ff3a36 5626 u8 reserved_at_40[0x8];
e281682b
SM		 5627 u8 xrcd[0x18];
5628
b4ff3a36 5629 u8 reserved_at_60[0x20];
e281682b
SM		 5630};
5631
5632struct mlx5_ifc_dealloc_uar_out_bits {
5633 u8 status[0x8];
b4ff3a36 5634 u8 reserved_at_8[0x18];
e281682b
SM		 5635
5636 u8 syndrome[0x20];
5637
b4ff3a36 5638 u8 reserved_at_40[0x40];
e281682b
SM		 5639};
5640
5641struct mlx5_ifc_dealloc_uar_in_bits {
5642 u8 opcode[0x10];
b4ff3a36 5643 u8 reserved_at_10[0x10];
e281682b 5644
b4ff3a36 5645 u8 reserved_at_20[0x10];
e281682b
SM		 5646 u8 op_mod[0x10];
5647
b4ff3a36 5648 u8 reserved_at_40[0x8];
e281682b
SM		 5649 u8 uar[0x18];
5650
b4ff3a36 5651 u8 reserved_at_60[0x20];
e281682b
SM		 5652};
5653
5654struct mlx5_ifc_dealloc_transport_domain_out_bits {
5655 u8 status[0x8];
b4ff3a36 5656 u8 reserved_at_8[0x18];
e281682b
SM		 5657
5658 u8 syndrome[0x20];
5659
b4ff3a36 5660 u8 reserved_at_40[0x40];
e281682b
SM		 5661};
5662
5663struct mlx5_ifc_dealloc_transport_domain_in_bits {
5664 u8 opcode[0x10];
b4ff3a36 5665 u8 reserved_at_10[0x10];
e281682b 5666
b4ff3a36 5667 u8 reserved_at_20[0x10];
e281682b
SM		 5668 u8 op_mod[0x10];
5669
b4ff3a36 5670 u8 reserved_at_40[0x8];
e281682b
SM		 5671 u8 transport_domain[0x18];
5672
b4ff3a36 5673 u8 reserved_at_60[0x20];
e281682b
SM		 5674};
5675
5676struct mlx5_ifc_dealloc_q_counter_out_bits {
5677 u8 status[0x8];
b4ff3a36 5678 u8 reserved_at_8[0x18];
e281682b
SM		 5679
5680 u8 syndrome[0x20];
5681
b4ff3a36 5682 u8 reserved_at_40[0x40];
e281682b
SM		 5683};
5684
5685struct mlx5_ifc_dealloc_q_counter_in_bits {
5686 u8 opcode[0x10];
b4ff3a36 5687 u8 reserved_at_10[0x10];
e281682b 5688
b4ff3a36 5689 u8 reserved_at_20[0x10];
e281682b
SM		 5690 u8 op_mod[0x10];
5691
b4ff3a36 5692 u8 reserved_at_40[0x18];
e281682b
SM		 5693 u8 counter_set_id[0x8];
5694
b4ff3a36 5695 u8 reserved_at_60[0x20];
e281682b
SM		 5696};
5697
5698struct mlx5_ifc_dealloc_pd_out_bits {
5699 u8 status[0x8];
b4ff3a36 5700 u8 reserved_at_8[0x18];
e281682b
SM		 5701
5702 u8 syndrome[0x20];
5703
b4ff3a36 5704 u8 reserved_at_40[0x40];
e281682b
SM		 5705};
5706
5707struct mlx5_ifc_dealloc_pd_in_bits {
5708 u8 opcode[0x10];
b4ff3a36 5709 u8 reserved_at_10[0x10];
e281682b 5710
b4ff3a36 5711 u8 reserved_at_20[0x10];
e281682b
SM		 5712 u8 op_mod[0x10];
5713
b4ff3a36 5714 u8 reserved_at_40[0x8];
e281682b
SM		 5715 u8 pd[0x18];
5716
b4ff3a36 5717 u8 reserved_at_60[0x20];
e281682b
SM		 5718};
5719
9dc0b289
AV		 5720struct mlx5_ifc_dealloc_flow_counter_out_bits {
5721 u8 status[0x8];
5722 u8 reserved_at_8[0x18];
5723
5724 u8 syndrome[0x20];
5725
5726 u8 reserved_at_40[0x40];
5727};
5728
5729struct mlx5_ifc_dealloc_flow_counter_in_bits {
5730 u8 opcode[0x10];
5731 u8 reserved_at_10[0x10];
5732
5733 u8 reserved_at_20[0x10];
5734 u8 op_mod[0x10];
5735
5736 u8 reserved_at_40[0x10];
5737 u8 flow_counter_id[0x10];
5738
5739 u8 reserved_at_60[0x20];
5740};
5741
7486216b
SM		 5742struct mlx5_ifc_create_xrq_out_bits {
5743 u8 status[0x8];
5744 u8 reserved_at_8[0x18];
5745
5746 u8 syndrome[0x20];
5747
5748 u8 reserved_at_40[0x8];
5749 u8 xrqn[0x18];
5750
5751 u8 reserved_at_60[0x20];
5752};
5753
5754struct mlx5_ifc_create_xrq_in_bits {
5755 u8 opcode[0x10];
5756 u8 reserved_at_10[0x10];
5757
5758 u8 reserved_at_20[0x10];
5759 u8 op_mod[0x10];
5760
5761 u8 reserved_at_40[0x40];
5762
5763 struct mlx5_ifc_xrqc_bits xrq_context;
5764};
5765
e281682b
SM		 5766struct mlx5_ifc_create_xrc_srq_out_bits {
5767 u8 status[0x8];
b4ff3a36 5768 u8 reserved_at_8[0x18];
e281682b
SM		 5769
5770 u8 syndrome[0x20];
5771
b4ff3a36 5772 u8 reserved_at_40[0x8];
e281682b
SM		 5773 u8 xrc_srqn[0x18];
5774
b4ff3a36 5775 u8 reserved_at_60[0x20];
e281682b
SM		 5776};
5777
5778struct mlx5_ifc_create_xrc_srq_in_bits {
5779 u8 opcode[0x10];
b4ff3a36 5780 u8 reserved_at_10[0x10];
e281682b 5781
b4ff3a36 5782 u8 reserved_at_20[0x10];
e281682b
SM		 5783 u8 op_mod[0x10];
5784
b4ff3a36 5785 u8 reserved_at_40[0x40];
e281682b
SM		 5786
5787 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
5788
b4ff3a36 5789 u8 reserved_at_280[0x600];
e281682b
SM		 5790
5791 u8 pas[0][0x40];
5792};
5793
5794struct mlx5_ifc_create_tis_out_bits {
5795 u8 status[0x8];
b4ff3a36 5796 u8 reserved_at_8[0x18];
e281682b
SM		 5797
5798 u8 syndrome[0x20];
5799
b4ff3a36 5800 u8 reserved_at_40[0x8];
e281682b
SM		 5801 u8 tisn[0x18];
5802
b4ff3a36 5803 u8 reserved_at_60[0x20];
e281682b
SM		 5804};
5805
5806struct mlx5_ifc_create_tis_in_bits {
5807 u8 opcode[0x10];
b4ff3a36 5808 u8 reserved_at_10[0x10];
e281682b 5809
b4ff3a36 5810 u8 reserved_at_20[0x10];
e281682b
SM		 5811 u8 op_mod[0x10];
5812
b4ff3a36 5813 u8 reserved_at_40[0xc0];
e281682b
SM		 5814
5815 struct mlx5_ifc_tisc_bits ctx;
5816};
5817
5818struct mlx5_ifc_create_tir_out_bits {
5819 u8 status[0x8];
b4ff3a36 5820 u8 reserved_at_8[0x18];
e281682b
SM		 5821
5822 u8 syndrome[0x20];
5823
b4ff3a36 5824 u8 reserved_at_40[0x8];
e281682b
SM		 5825 u8 tirn[0x18];
5826
b4ff3a36 5827 u8 reserved_at_60[0x20];
e281682b
SM		 5828};
5829
5830struct mlx5_ifc_create_tir_in_bits {
5831 u8 opcode[0x10];
b4ff3a36 5832 u8 reserved_at_10[0x10];
e281682b 5833
b4ff3a36 5834 u8 reserved_at_20[0x10];
e281682b
SM		 5835 u8 op_mod[0x10];
5836
b4ff3a36 5837 u8 reserved_at_40[0xc0];
e281682b
SM		 5838
5839 struct mlx5_ifc_tirc_bits ctx;
5840};
5841
5842struct mlx5_ifc_create_srq_out_bits {
5843 u8 status[0x8];
b4ff3a36 5844 u8 reserved_at_8[0x18];
e281682b
SM		 5845
5846 u8 syndrome[0x20];
5847
b4ff3a36 5848 u8 reserved_at_40[0x8];
e281682b
SM		 5849 u8 srqn[0x18];
5850
b4ff3a36 5851 u8 reserved_at_60[0x20];
e281682b
SM		 5852};
5853
5854struct mlx5_ifc_create_srq_in_bits {
5855 u8 opcode[0x10];
b4ff3a36 5856 u8 reserved_at_10[0x10];
e281682b 5857
b4ff3a36 5858 u8 reserved_at_20[0x10];
e281682b
SM		 5859 u8 op_mod[0x10];
5860
b4ff3a36 5861 u8 reserved_at_40[0x40];
e281682b
SM		 5862
5863 struct mlx5_ifc_srqc_bits srq_context_entry;
5864
b4ff3a36 5865 u8 reserved_at_280[0x600];
e281682b
SM		 5866
5867 u8 pas[0][0x40];
5868};
5869
5870struct mlx5_ifc_create_sq_out_bits {
5871 u8 status[0x8];
b4ff3a36 5872 u8 reserved_at_8[0x18];
e281682b
SM		 5873
5874 u8 syndrome[0x20];
5875
b4ff3a36 5876 u8 reserved_at_40[0x8];
e281682b
SM		 5877 u8 sqn[0x18];
5878
b4ff3a36 5879 u8 reserved_at_60[0x20];
e281682b
SM		 5880};
5881
5882struct mlx5_ifc_create_sq_in_bits {
5883 u8 opcode[0x10];
b4ff3a36 5884 u8 reserved_at_10[0x10];
e281682b 5885
b4ff3a36 5886 u8 reserved_at_20[0x10];
e281682b
SM		 5887 u8 op_mod[0x10];
5888
b4ff3a36 5889 u8 reserved_at_40[0xc0];
e281682b
SM		 5890
5891 struct mlx5_ifc_sqc_bits ctx;
5892};
5893
5894struct mlx5_ifc_create_rqt_out_bits {
5895 u8 status[0x8];
b4ff3a36 5896 u8 reserved_at_8[0x18];
e281682b
SM		 5897
5898 u8 syndrome[0x20];
5899
b4ff3a36 5900 u8 reserved_at_40[0x8];
e281682b
SM		 5901 u8 rqtn[0x18];
5902
b4ff3a36 5903 u8 reserved_at_60[0x20];
e281682b
SM		 5904};
5905
5906struct mlx5_ifc_create_rqt_in_bits {
5907 u8 opcode[0x10];
b4ff3a36 5908 u8 reserved_at_10[0x10];
e281682b 5909
b4ff3a36 5910 u8 reserved_at_20[0x10];
e281682b
SM		 5911 u8 op_mod[0x10];
5912
b4ff3a36 5913 u8 reserved_at_40[0xc0];
e281682b
SM		 5914
5915 struct mlx5_ifc_rqtc_bits rqt_context;
5916};
5917
5918struct mlx5_ifc_create_rq_out_bits {
5919 u8 status[0x8];
b4ff3a36 5920 u8 reserved_at_8[0x18];
e281682b
SM		 5921
5922 u8 syndrome[0x20];
5923
b4ff3a36 5924 u8 reserved_at_40[0x8];
e281682b
SM		 5925 u8 rqn[0x18];
5926
b4ff3a36 5927 u8 reserved_at_60[0x20];
e281682b
SM		 5928};
5929
5930struct mlx5_ifc_create_rq_in_bits {
5931 u8 opcode[0x10];
b4ff3a36 5932 u8 reserved_at_10[0x10];
e281682b 5933
b4ff3a36 5934 u8 reserved_at_20[0x10];
e281682b
SM		 5935 u8 op_mod[0x10];
5936
b4ff3a36 5937 u8 reserved_at_40[0xc0];
e281682b
SM		 5938
5939 struct mlx5_ifc_rqc_bits ctx;
5940};
5941
5942struct mlx5_ifc_create_rmp_out_bits {
5943 u8 status[0x8];
b4ff3a36 5944 u8 reserved_at_8[0x18];
e281682b
SM		 5945
5946 u8 syndrome[0x20];
5947
b4ff3a36 5948 u8 reserved_at_40[0x8];
e281682b
SM		 5949 u8 rmpn[0x18];
5950
b4ff3a36 5951 u8 reserved_at_60[0x20];
e281682b
SM		 5952};
5953
5954struct mlx5_ifc_create_rmp_in_bits {
5955 u8 opcode[0x10];
b4ff3a36 5956 u8 reserved_at_10[0x10];
e281682b 5957
b4ff3a36 5958 u8 reserved_at_20[0x10];
e281682b
SM		 5959 u8 op_mod[0x10];
5960
b4ff3a36 5961 u8 reserved_at_40[0xc0];
e281682b
SM		 5962
5963 struct mlx5_ifc_rmpc_bits ctx;
5964};
5965
5966struct mlx5_ifc_create_qp_out_bits {
5967 u8 status[0x8];
b4ff3a36 5968 u8 reserved_at_8[0x18];
e281682b
SM		 5969
5970 u8 syndrome[0x20];
5971
b4ff3a36 5972 u8 reserved_at_40[0x8];
e281682b
SM		 5973 u8 qpn[0x18];
5974
b4ff3a36 5975 u8 reserved_at_60[0x20];
e281682b
SM		 5976};
5977
5978struct mlx5_ifc_create_qp_in_bits {
5979 u8 opcode[0x10];
b4ff3a36 5980 u8 reserved_at_10[0x10];
e281682b 5981
b4ff3a36 5982 u8 reserved_at_20[0x10];
e281682b
SM		 5983 u8 op_mod[0x10];
5984
b4ff3a36 5985 u8 reserved_at_40[0x40];
e281682b
SM		 5986
5987 u8 opt_param_mask[0x20];
5988
b4ff3a36 5989 u8 reserved_at_a0[0x20];
e281682b
SM		 5990
5991 struct mlx5_ifc_qpc_bits qpc;
5992
b4ff3a36 5993 u8 reserved_at_800[0x80];
e281682b
SM		 5994
5995 u8 pas[0][0x40];
5996};
5997
5998struct mlx5_ifc_create_psv_out_bits {
5999 u8 status[0x8];
b4ff3a36 6000 u8 reserved_at_8[0x18];
e281682b
SM		 6001
6002 u8 syndrome[0x20];
6003
b4ff3a36 6004 u8 reserved_at_40[0x40];
e281682b 6005
b4ff3a36 6006 u8 reserved_at_80[0x8];
e281682b
SM		 6007 u8 psv0_index[0x18];
6008
b4ff3a36 6009 u8 reserved_at_a0[0x8];
e281682b
SM		 6010 u8 psv1_index[0x18];
6011
b4ff3a36 6012 u8 reserved_at_c0[0x8];
e281682b
SM		 6013 u8 psv2_index[0x18];
6014
b4ff3a36 6015 u8 reserved_at_e0[0x8];
e281682b
SM		 6016 u8 psv3_index[0x18];
6017};
6018
6019struct mlx5_ifc_create_psv_in_bits {
6020 u8 opcode[0x10];
b4ff3a36 6021 u8 reserved_at_10[0x10];
e281682b 6022
b4ff3a36 6023 u8 reserved_at_20[0x10];
e281682b
SM		 6024 u8 op_mod[0x10];
6025
6026 u8 num_psv[0x4];
b4ff3a36 6027 u8 reserved_at_44[0x4];
e281682b
SM		 6028 u8 pd[0x18];
6029
b4ff3a36 6030 u8 reserved_at_60[0x20];
e281682b
SM		 6031};
6032
6033struct mlx5_ifc_create_mkey_out_bits {
6034 u8 status[0x8];
b4ff3a36 6035 u8 reserved_at_8[0x18];
e281682b
SM		 6036
6037 u8 syndrome[0x20];
6038
b4ff3a36 6039 u8 reserved_at_40[0x8];
e281682b
SM		 6040 u8 mkey_index[0x18];
6041
b4ff3a36 6042 u8 reserved_at_60[0x20];
e281682b
SM		 6043};
6044
6045struct mlx5_ifc_create_mkey_in_bits {
6046 u8 opcode[0x10];
b4ff3a36 6047 u8 reserved_at_10[0x10];
e281682b 6048
b4ff3a36 6049 u8 reserved_at_20[0x10];
e281682b
SM		 6050 u8 op_mod[0x10];
6051
b4ff3a36 6052 u8 reserved_at_40[0x20];
e281682b
SM		 6053
6054 u8 pg_access[0x1];
b4ff3a36 6055 u8 reserved_at_61[0x1f];
e281682b
SM		 6056
6057 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6058
b4ff3a36 6059 u8 reserved_at_280[0x80];
e281682b
SM		 6060
6061 u8 translations_octword_actual_size[0x20];
6062
b4ff3a36 6063 u8 reserved_at_320[0x560];
e281682b
SM		 6064
6065 u8 klm_pas_mtt[0][0x20];
6066};
6067
6068struct mlx5_ifc_create_flow_table_out_bits {
6069 u8 status[0x8];
b4ff3a36 6070 u8 reserved_at_8[0x18];
e281682b
SM		 6071
6072 u8 syndrome[0x20];
6073
b4ff3a36 6074 u8 reserved_at_40[0x8];
e281682b
SM		 6075 u8 table_id[0x18];
6076
b4ff3a36 6077 u8 reserved_at_60[0x20];
e281682b
SM		 6078};
6079
6080struct mlx5_ifc_create_flow_table_in_bits {
6081 u8 opcode[0x10];
b4ff3a36 6082 u8 reserved_at_10[0x10];
e281682b 6083
b4ff3a36 6084 u8 reserved_at_20[0x10];
e281682b
SM		 6085 u8 op_mod[0x10];
6086
7d5e1423
SM		 6087 u8 other_vport[0x1];
6088 u8 reserved_at_41[0xf];
6089 u8 vport_number[0x10];
6090
6091 u8 reserved_at_60[0x20];
e281682b
SM		 6092
6093 u8 table_type[0x8];
b4ff3a36 6094 u8 reserved_at_88[0x18];
e281682b 6095
b4ff3a36 6096 u8 reserved_at_a0[0x20];
e281682b 6097
b4ff3a36 6098 u8 reserved_at_c0[0x4];
34a40e68 6099 u8 table_miss_mode[0x4];
e281682b 6100 u8 level[0x8];
b4ff3a36 6101 u8 reserved_at_d0[0x8];
e281682b
SM		 6102 u8 log_size[0x8];
6103
b4ff3a36 6104 u8 reserved_at_e0[0x8];
34a40e68
MG		 6105 u8 table_miss_id[0x18];
6106
b4ff3a36 6107 u8 reserved_at_100[0x100];
e281682b
SM		 6108};
6109
6110struct mlx5_ifc_create_flow_group_out_bits {
6111 u8 status[0x8];
b4ff3a36 6112 u8 reserved_at_8[0x18];
e281682b
SM		 6113
6114 u8 syndrome[0x20];
6115
b4ff3a36 6116 u8 reserved_at_40[0x8];
e281682b
SM		 6117 u8 group_id[0x18];
6118
b4ff3a36 6119 u8 reserved_at_60[0x20];
e281682b
SM		 6120};
6121
6122enum {
6123 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
6124 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
6125 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
6126};
6127
6128struct mlx5_ifc_create_flow_group_in_bits {
6129 u8 opcode[0x10];
b4ff3a36 6130 u8 reserved_at_10[0x10];
e281682b 6131
b4ff3a36 6132 u8 reserved_at_20[0x10];
e281682b
SM		 6133 u8 op_mod[0x10];
6134
7d5e1423
SM		 6135 u8 other_vport[0x1];
6136 u8 reserved_at_41[0xf];
6137 u8 vport_number[0x10];
6138
6139 u8 reserved_at_60[0x20];
e281682b
SM		 6140
6141 u8 table_type[0x8];
b4ff3a36 6142 u8 reserved_at_88[0x18];
e281682b 6143
b4ff3a36 6144 u8 reserved_at_a0[0x8];
e281682b
SM		 6145 u8 table_id[0x18];
6146
b4ff3a36 6147 u8 reserved_at_c0[0x20];
e281682b
SM		 6148
6149 u8 start_flow_index[0x20];
6150
b4ff3a36 6151 u8 reserved_at_100[0x20];
e281682b
SM		 6152
6153 u8 end_flow_index[0x20];
6154
b4ff3a36 6155 u8 reserved_at_140[0xa0];
e281682b 6156
b4ff3a36 6157 u8 reserved_at_1e0[0x18];
e281682b
SM		 6158 u8 match_criteria_enable[0x8];
6159
6160 struct mlx5_ifc_fte_match_param_bits match_criteria;
6161
b4ff3a36 6162 u8 reserved_at_1200[0xe00];
e281682b
SM		 6163};
6164
6165struct mlx5_ifc_create_eq_out_bits {
6166 u8 status[0x8];
b4ff3a36 6167 u8 reserved_at_8[0x18];
e281682b
SM		 6168
6169 u8 syndrome[0x20];
6170
b4ff3a36 6171 u8 reserved_at_40[0x18];
e281682b
SM		 6172 u8 eq_number[0x8];
6173
b4ff3a36 6174 u8 reserved_at_60[0x20];
e281682b
SM		 6175};
6176
6177struct mlx5_ifc_create_eq_in_bits {
6178 u8 opcode[0x10];
b4ff3a36 6179 u8 reserved_at_10[0x10];
e281682b 6180
b4ff3a36 6181 u8 reserved_at_20[0x10];
e281682b
SM		 6182 u8 op_mod[0x10];
6183
b4ff3a36 6184 u8 reserved_at_40[0x40];
e281682b
SM		 6185
6186 struct mlx5_ifc_eqc_bits eq_context_entry;
6187
b4ff3a36 6188 u8 reserved_at_280[0x40];
e281682b
SM		 6189
6190 u8 event_bitmask[0x40];
6191
b4ff3a36 6192 u8 reserved_at_300[0x580];
e281682b
SM		 6193
6194 u8 pas[0][0x40];
6195};
6196
6197struct mlx5_ifc_create_dct_out_bits {
6198 u8 status[0x8];
b4ff3a36 6199 u8 reserved_at_8[0x18];
e281682b
SM		 6200
6201 u8 syndrome[0x20];
6202
b4ff3a36 6203 u8 reserved_at_40[0x8];
e281682b
SM		 6204 u8 dctn[0x18];
6205
b4ff3a36 6206 u8 reserved_at_60[0x20];
e281682b
SM		 6207};
6208
6209struct mlx5_ifc_create_dct_in_bits {
6210 u8 opcode[0x10];
b4ff3a36 6211 u8 reserved_at_10[0x10];
e281682b 6212
b4ff3a36 6213 u8 reserved_at_20[0x10];
e281682b
SM		 6214 u8 op_mod[0x10];
6215
b4ff3a36 6216 u8 reserved_at_40[0x40];
e281682b
SM		 6217
6218 struct mlx5_ifc_dctc_bits dct_context_entry;
6219
b4ff3a36 6220 u8 reserved_at_280[0x180];
e281682b
SM		 6221};
6222
6223struct mlx5_ifc_create_cq_out_bits {
6224 u8 status[0x8];
b4ff3a36 6225 u8 reserved_at_8[0x18];
e281682b
SM		 6226
6227 u8 syndrome[0x20];
6228
b4ff3a36 6229 u8 reserved_at_40[0x8];
e281682b
SM		 6230 u8 cqn[0x18];
6231
b4ff3a36 6232 u8 reserved_at_60[0x20];
e281682b
SM		 6233};
6234
6235struct mlx5_ifc_create_cq_in_bits {
6236 u8 opcode[0x10];
b4ff3a36 6237 u8 reserved_at_10[0x10];
e281682b 6238
b4ff3a36 6239 u8 reserved_at_20[0x10];
e281682b
SM		 6240 u8 op_mod[0x10];
6241
b4ff3a36 6242 u8 reserved_at_40[0x40];
e281682b
SM		 6243
6244 struct mlx5_ifc_cqc_bits cq_context;
6245
b4ff3a36 6246 u8 reserved_at_280[0x600];
e281682b
SM		 6247
6248 u8 pas[0][0x40];
6249};
6250
6251struct mlx5_ifc_config_int_moderation_out_bits {
6252 u8 status[0x8];
b4ff3a36 6253 u8 reserved_at_8[0x18];
e281682b
SM		 6254
6255 u8 syndrome[0x20];
6256
b4ff3a36 6257 u8 reserved_at_40[0x4];
e281682b
SM		 6258 u8 min_delay[0xc];
6259 u8 int_vector[0x10];
6260
b4ff3a36 6261 u8 reserved_at_60[0x20];
e281682b
SM		 6262};
6263
6264enum {
6265 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
6266 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
6267};
6268
6269struct mlx5_ifc_config_int_moderation_in_bits {
6270 u8 opcode[0x10];
b4ff3a36 6271 u8 reserved_at_10[0x10];
e281682b 6272
b4ff3a36 6273 u8 reserved_at_20[0x10];
e281682b
SM		 6274 u8 op_mod[0x10];
6275
b4ff3a36 6276 u8 reserved_at_40[0x4];
e281682b
SM		 6277 u8 min_delay[0xc];
6278 u8 int_vector[0x10];
6279
b4ff3a36 6280 u8 reserved_at_60[0x20];
e281682b
SM		 6281};
6282
6283struct mlx5_ifc_attach_to_mcg_out_bits {
6284 u8 status[0x8];
b4ff3a36 6285 u8 reserved_at_8[0x18];
e281682b
SM		 6286
6287 u8 syndrome[0x20];
6288
b4ff3a36 6289 u8 reserved_at_40[0x40];
e281682b
SM		 6290};
6291
6292struct mlx5_ifc_attach_to_mcg_in_bits {
6293 u8 opcode[0x10];
b4ff3a36 6294 u8 reserved_at_10[0x10];
e281682b 6295
b4ff3a36 6296 u8 reserved_at_20[0x10];
e281682b
SM		 6297 u8 op_mod[0x10];
6298
b4ff3a36 6299 u8 reserved_at_40[0x8];
e281682b
SM		 6300 u8 qpn[0x18];
6301
b4ff3a36 6302 u8 reserved_at_60[0x20];
e281682b
SM		 6303
6304 u8 multicast_gid[16][0x8];
6305};
6306
7486216b
SM		 6307struct mlx5_ifc_arm_xrq_out_bits {
6308 u8 status[0x8];
6309 u8 reserved_at_8[0x18];
6310
6311 u8 syndrome[0x20];
6312
6313 u8 reserved_at_40[0x40];
6314};
6315
6316struct mlx5_ifc_arm_xrq_in_bits {
6317 u8 opcode[0x10];
6318 u8 reserved_at_10[0x10];
6319
6320 u8 reserved_at_20[0x10];
6321 u8 op_mod[0x10];
6322
6323 u8 reserved_at_40[0x8];
6324 u8 xrqn[0x18];
6325
6326 u8 reserved_at_60[0x10];
6327 u8 lwm[0x10];
6328};
6329
e281682b
SM		 6330struct mlx5_ifc_arm_xrc_srq_out_bits {
6331 u8 status[0x8];
b4ff3a36 6332 u8 reserved_at_8[0x18];
e281682b
SM		 6333
6334 u8 syndrome[0x20];
6335
b4ff3a36 6336 u8 reserved_at_40[0x40];
e281682b
SM		 6337};
6338
6339enum {
6340 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
6341};
6342
6343struct mlx5_ifc_arm_xrc_srq_in_bits {
6344 u8 opcode[0x10];
b4ff3a36 6345 u8 reserved_at_10[0x10];
e281682b 6346
b4ff3a36 6347 u8 reserved_at_20[0x10];
e281682b
SM		 6348 u8 op_mod[0x10];
6349
b4ff3a36 6350 u8 reserved_at_40[0x8];
e281682b
SM		 6351 u8 xrc_srqn[0x18];
6352
b4ff3a36 6353 u8 reserved_at_60[0x10];
e281682b
SM		 6354 u8 lwm[0x10];
6355};
6356
6357struct mlx5_ifc_arm_rq_out_bits {
6358 u8 status[0x8];
b4ff3a36 6359 u8 reserved_at_8[0x18];
e281682b
SM		 6360
6361 u8 syndrome[0x20];
6362
b4ff3a36 6363 u8 reserved_at_40[0x40];
e281682b
SM		 6364};
6365
6366enum {
7486216b
SM		 6367 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
6368 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
e281682b
SM		 6369};
6370
6371struct mlx5_ifc_arm_rq_in_bits {
6372 u8 opcode[0x10];
b4ff3a36 6373 u8 reserved_at_10[0x10];
e281682b 6374
b4ff3a36 6375 u8 reserved_at_20[0x10];
e281682b
SM		 6376 u8 op_mod[0x10];
6377
b4ff3a36 6378 u8 reserved_at_40[0x8];
e281682b
SM		 6379 u8 srq_number[0x18];
6380
b4ff3a36 6381 u8 reserved_at_60[0x10];
e281682b
SM		 6382 u8 lwm[0x10];
6383};
6384
6385struct mlx5_ifc_arm_dct_out_bits {
6386 u8 status[0x8];
b4ff3a36 6387 u8 reserved_at_8[0x18];
e281682b
SM		 6388
6389 u8 syndrome[0x20];
6390
b4ff3a36 6391 u8 reserved_at_40[0x40];
e281682b
SM		 6392};
6393
6394struct mlx5_ifc_arm_dct_in_bits {
6395 u8 opcode[0x10];
b4ff3a36 6396 u8 reserved_at_10[0x10];
e281682b 6397
b4ff3a36 6398 u8 reserved_at_20[0x10];
e281682b
SM		 6399 u8 op_mod[0x10];
6400
b4ff3a36 6401 u8 reserved_at_40[0x8];
e281682b
SM		 6402 u8 dct_number[0x18];
6403
b4ff3a36 6404 u8 reserved_at_60[0x20];
e281682b
SM		 6405};
6406
6407struct mlx5_ifc_alloc_xrcd_out_bits {
6408 u8 status[0x8];
b4ff3a36 6409 u8 reserved_at_8[0x18];
e281682b
SM		 6410
6411 u8 syndrome[0x20];
6412
b4ff3a36 6413 u8 reserved_at_40[0x8];
e281682b
SM		 6414 u8 xrcd[0x18];
6415
b4ff3a36 6416 u8 reserved_at_60[0x20];
e281682b
SM		 6417};
6418
6419struct mlx5_ifc_alloc_xrcd_in_bits {
6420 u8 opcode[0x10];
b4ff3a36 6421 u8 reserved_at_10[0x10];
e281682b 6422
b4ff3a36 6423 u8 reserved_at_20[0x10];
e281682b
SM		 6424 u8 op_mod[0x10];
6425
b4ff3a36 6426 u8 reserved_at_40[0x40];
e281682b
SM		 6427};
6428
6429struct mlx5_ifc_alloc_uar_out_bits {
6430 u8 status[0x8];
b4ff3a36 6431 u8 reserved_at_8[0x18];
e281682b
SM		 6432
6433 u8 syndrome[0x20];
6434
b4ff3a36 6435 u8 reserved_at_40[0x8];
e281682b
SM		 6436 u8 uar[0x18];
6437
b4ff3a36 6438 u8 reserved_at_60[0x20];
e281682b
SM		 6439};
6440
6441struct mlx5_ifc_alloc_uar_in_bits {
6442 u8 opcode[0x10];
b4ff3a36 6443 u8 reserved_at_10[0x10];
e281682b 6444
b4ff3a36 6445 u8 reserved_at_20[0x10];
e281682b
SM		 6446 u8 op_mod[0x10];
6447
b4ff3a36 6448 u8 reserved_at_40[0x40];
e281682b
SM		 6449};
6450
6451struct mlx5_ifc_alloc_transport_domain_out_bits {
6452 u8 status[0x8];
b4ff3a36 6453 u8 reserved_at_8[0x18];
e281682b
SM		 6454
6455 u8 syndrome[0x20];
6456
b4ff3a36 6457 u8 reserved_at_40[0x8];
e281682b
SM		 6458 u8 transport_domain[0x18];
6459
b4ff3a36 6460 u8 reserved_at_60[0x20];
e281682b
SM		 6461};
6462
6463struct mlx5_ifc_alloc_transport_domain_in_bits {
6464 u8 opcode[0x10];
b4ff3a36 6465 u8 reserved_at_10[0x10];
e281682b 6466
b4ff3a36 6467 u8 reserved_at_20[0x10];
e281682b
SM		 6468 u8 op_mod[0x10];
6469
b4ff3a36 6470 u8 reserved_at_40[0x40];
e281682b
SM		 6471};
6472
6473struct mlx5_ifc_alloc_q_counter_out_bits {
6474 u8 status[0x8];
b4ff3a36 6475 u8 reserved_at_8[0x18];
e281682b
SM		 6476
6477 u8 syndrome[0x20];
6478
b4ff3a36 6479 u8 reserved_at_40[0x18];
e281682b
SM		 6480 u8 counter_set_id[0x8];
6481
b4ff3a36 6482 u8 reserved_at_60[0x20];
e281682b
SM		 6483};
6484
6485struct mlx5_ifc_alloc_q_counter_in_bits {
6486 u8 opcode[0x10];
b4ff3a36 6487 u8 reserved_at_10[0x10];
e281682b 6488
b4ff3a36 6489 u8 reserved_at_20[0x10];
e281682b
SM		 6490 u8 op_mod[0x10];
6491
b4ff3a36 6492 u8 reserved_at_40[0x40];
e281682b
SM		 6493};
6494
6495struct mlx5_ifc_alloc_pd_out_bits {
6496 u8 status[0x8];
b4ff3a36 6497 u8 reserved_at_8[0x18];
e281682b
SM		 6498
6499 u8 syndrome[0x20];
6500
b4ff3a36 6501 u8 reserved_at_40[0x8];
e281682b
SM		 6502 u8 pd[0x18];
6503
b4ff3a36 6504 u8 reserved_at_60[0x20];
e281682b
SM		 6505};
6506
6507struct mlx5_ifc_alloc_pd_in_bits {
9dc0b289
AV		 6508 u8 opcode[0x10];
6509 u8 reserved_at_10[0x10];
6510
6511 u8 reserved_at_20[0x10];
6512 u8 op_mod[0x10];
6513
6514 u8 reserved_at_40[0x40];
6515};
6516
6517struct mlx5_ifc_alloc_flow_counter_out_bits {
6518 u8 status[0x8];
6519 u8 reserved_at_8[0x18];
6520
6521 u8 syndrome[0x20];
6522
6523 u8 reserved_at_40[0x10];
6524 u8 flow_counter_id[0x10];
6525
6526 u8 reserved_at_60[0x20];
6527};
6528
6529struct mlx5_ifc_alloc_flow_counter_in_bits {
e281682b 6530 u8 opcode[0x10];
b4ff3a36 6531 u8 reserved_at_10[0x10];
e281682b 6532
b4ff3a36 6533 u8 reserved_at_20[0x10];
e281682b
SM		 6534 u8 op_mod[0x10];
6535
b4ff3a36 6536 u8 reserved_at_40[0x40];
e281682b
SM		 6537};
6538
6539struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
6540 u8 status[0x8];
b4ff3a36 6541 u8 reserved_at_8[0x18];
e281682b
SM		 6542
6543 u8 syndrome[0x20];
6544
b4ff3a36 6545 u8 reserved_at_40[0x40];
e281682b
SM		 6546};
6547
6548struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
6549 u8 opcode[0x10];
b4ff3a36 6550 u8 reserved_at_10[0x10];
e281682b 6551
b4ff3a36 6552 u8 reserved_at_20[0x10];
e281682b
SM		 6553 u8 op_mod[0x10];
6554
b4ff3a36 6555 u8 reserved_at_40[0x20];
e281682b 6556
b4ff3a36 6557 u8 reserved_at_60[0x10];
e281682b
SM		 6558 u8 vxlan_udp_port[0x10];
6559};
6560
7486216b
SM		 6561struct mlx5_ifc_set_rate_limit_out_bits {
6562 u8 status[0x8];
6563 u8 reserved_at_8[0x18];
6564
6565 u8 syndrome[0x20];
6566
6567 u8 reserved_at_40[0x40];
6568};
6569
6570struct mlx5_ifc_set_rate_limit_in_bits {
6571 u8 opcode[0x10];
6572 u8 reserved_at_10[0x10];
6573
6574 u8 reserved_at_20[0x10];
6575 u8 op_mod[0x10];
6576
6577 u8 reserved_at_40[0x10];
6578 u8 rate_limit_index[0x10];
6579
6580 u8 reserved_at_60[0x20];
6581
6582 u8 rate_limit[0x20];
6583};
6584
e281682b
SM		 6585struct mlx5_ifc_access_register_out_bits {
6586 u8 status[0x8];
b4ff3a36 6587 u8 reserved_at_8[0x18];
e281682b
SM		 6588
6589 u8 syndrome[0x20];
6590
b4ff3a36 6591 u8 reserved_at_40[0x40];
e281682b
SM		 6592
6593 u8 register_data[0][0x20];
6594};
6595
6596enum {
6597 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
6598 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
6599};
6600
6601struct mlx5_ifc_access_register_in_bits {
6602 u8 opcode[0x10];
b4ff3a36 6603 u8 reserved_at_10[0x10];
e281682b 6604
b4ff3a36 6605 u8 reserved_at_20[0x10];
e281682b
SM		 6606 u8 op_mod[0x10];
6607
b4ff3a36 6608 u8 reserved_at_40[0x10];
e281682b
SM		 6609 u8 register_id[0x10];
6610
6611 u8 argument[0x20];
6612
6613 u8 register_data[0][0x20];
6614};
6615
6616struct mlx5_ifc_sltp_reg_bits {
6617 u8 status[0x4];
6618 u8 version[0x4];
6619 u8 local_port[0x8];
6620 u8 pnat[0x2];
b4ff3a36 6621 u8 reserved_at_12[0x2];
e281682b 6622 u8 lane[0x4];
b4ff3a36 6623 u8 reserved_at_18[0x8];
e281682b 6624
b4ff3a36 6625 u8 reserved_at_20[0x20];
e281682b 6626
b4ff3a36 6627 u8 reserved_at_40[0x7];
e281682b
SM		 6628 u8 polarity[0x1];
6629 u8 ob_tap0[0x8];
6630 u8 ob_tap1[0x8];
6631 u8 ob_tap2[0x8];
6632
b4ff3a36 6633 u8 reserved_at_60[0xc];
e281682b
SM		 6634 u8 ob_preemp_mode[0x4];
6635 u8 ob_reg[0x8];
6636 u8 ob_bias[0x8];
6637
b4ff3a36 6638 u8 reserved_at_80[0x20];
e281682b
SM		 6639};
6640
6641struct mlx5_ifc_slrg_reg_bits {
6642 u8 status[0x4];
6643 u8 version[0x4];
6644 u8 local_port[0x8];
6645 u8 pnat[0x2];
b4ff3a36 6646 u8 reserved_at_12[0x2];
e281682b 6647 u8 lane[0x4];
b4ff3a36 6648 u8 reserved_at_18[0x8];
e281682b
SM		 6649
6650 u8 time_to_link_up[0x10];
b4ff3a36 6651 u8 reserved_at_30[0xc];
e281682b
SM		 6652 u8 grade_lane_speed[0x4];
6653
6654 u8 grade_version[0x8];
6655 u8 grade[0x18];
6656
b4ff3a36 6657 u8 reserved_at_60[0x4];
e281682b
SM		 6658 u8 height_grade_type[0x4];
6659 u8 height_grade[0x18];
6660
6661 u8 height_dz[0x10];
6662 u8 height_dv[0x10];
6663
b4ff3a36 6664 u8 reserved_at_a0[0x10];
e281682b
SM		 6665 u8 height_sigma[0x10];
6666
b4ff3a36 6667 u8 reserved_at_c0[0x20];
e281682b 6668
b4ff3a36 6669 u8 reserved_at_e0[0x4];
e281682b
SM		 6670 u8 phase_grade_type[0x4];
6671 u8 phase_grade[0x18];
6672
b4ff3a36 6673 u8 reserved_at_100[0x8];
e281682b 6674 u8 phase_eo_pos[0x8];
b4ff3a36 6675 u8 reserved_at_110[0x8];
e281682b
SM		 6676 u8 phase_eo_neg[0x8];
6677
6678 u8 ffe_set_tested[0x10];
6679 u8 test_errors_per_lane[0x10];
6680};
6681
6682struct mlx5_ifc_pvlc_reg_bits {
b4ff3a36 6683 u8 reserved_at_0[0x8];
e281682b 6684 u8 local_port[0x8];
b4ff3a36 6685 u8 reserved_at_10[0x10];
e281682b 6686
b4ff3a36 6687 u8 reserved_at_20[0x1c];
e281682b
SM		 6688 u8 vl_hw_cap[0x4];
6689
b4ff3a36 6690 u8 reserved_at_40[0x1c];
e281682b
SM		 6691 u8 vl_admin[0x4];
6692
b4ff3a36 6693 u8 reserved_at_60[0x1c];
e281682b
SM		 6694 u8 vl_operational[0x4];
6695};
6696
6697struct mlx5_ifc_pude_reg_bits {
6698 u8 swid[0x8];
6699 u8 local_port[0x8];
b4ff3a36 6700 u8 reserved_at_10[0x4];
e281682b 6701 u8 admin_status[0x4];
b4ff3a36 6702 u8 reserved_at_18[0x4];
e281682b
SM		 6703 u8 oper_status[0x4];
6704
b4ff3a36 6705 u8 reserved_at_20[0x60];
e281682b
SM		 6706};
6707
6708struct mlx5_ifc_ptys_reg_bits {
7486216b
SM		 6709 u8 an_disable_cap[0x1];
6710 u8 an_disable_admin[0x1];
6711 u8 reserved_at_2[0x6];
e281682b 6712 u8 local_port[0x8];
b4ff3a36 6713 u8 reserved_at_10[0xd];
e281682b
SM		 6714 u8 proto_mask[0x3];
6715
7486216b
SM		 6716 u8 an_status[0x4];
6717 u8 reserved_at_24[0x3c];
e281682b
SM		 6718
6719 u8 eth_proto_capability[0x20];
6720
6721 u8 ib_link_width_capability[0x10];
6722 u8 ib_proto_capability[0x10];
6723
b4ff3a36 6724 u8 reserved_at_a0[0x20];
e281682b
SM		 6725
6726 u8 eth_proto_admin[0x20];
6727
6728 u8 ib_link_width_admin[0x10];
6729 u8 ib_proto_admin[0x10];
6730
b4ff3a36 6731 u8 reserved_at_100[0x20];
e281682b
SM		 6732
6733 u8 eth_proto_oper[0x20];
6734
6735 u8 ib_link_width_oper[0x10];
6736 u8 ib_proto_oper[0x10];
6737
b4ff3a36 6738 u8 reserved_at_160[0x20];
e281682b
SM		 6739
6740 u8 eth_proto_lp_advertise[0x20];
6741
b4ff3a36 6742 u8 reserved_at_1a0[0x60];
e281682b
SM		 6743};
6744
7d5e1423
SM		 6745struct mlx5_ifc_mlcr_reg_bits {
6746 u8 reserved_at_0[0x8];
6747 u8 local_port[0x8];
6748 u8 reserved_at_10[0x20];
6749
6750 u8 beacon_duration[0x10];
6751 u8 reserved_at_40[0x10];
6752
6753 u8 beacon_remain[0x10];
6754};
6755
e281682b 6756struct mlx5_ifc_ptas_reg_bits {
b4ff3a36 6757 u8 reserved_at_0[0x20];
e281682b
SM		 6758
6759 u8 algorithm_options[0x10];
b4ff3a36 6760 u8 reserved_at_30[0x4];
e281682b
SM		 6761 u8 repetitions_mode[0x4];
6762 u8 num_of_repetitions[0x8];
6763
6764 u8 grade_version[0x8];
6765 u8 height_grade_type[0x4];
6766 u8 phase_grade_type[0x4];
6767 u8 height_grade_weight[0x8];
6768 u8 phase_grade_weight[0x8];
6769
6770 u8 gisim_measure_bits[0x10];
6771 u8 adaptive_tap_measure_bits[0x10];
6772
6773 u8 ber_bath_high_error_threshold[0x10];
6774 u8 ber_bath_mid_error_threshold[0x10];
6775
6776 u8 ber_bath_low_error_threshold[0x10];
6777 u8 one_ratio_high_threshold[0x10];
6778
6779 u8 one_ratio_high_mid_threshold[0x10];
6780 u8 one_ratio_low_mid_threshold[0x10];
6781
6782 u8 one_ratio_low_threshold[0x10];
6783 u8 ndeo_error_threshold[0x10];
6784
6785 u8 mixer_offset_step_size[0x10];
b4ff3a36 6786 u8 reserved_at_110[0x8];
e281682b
SM		 6787 u8 mix90_phase_for_voltage_bath[0x8];
6788
6789 u8 mixer_offset_start[0x10];
6790 u8 mixer_offset_end[0x10];
6791
b4ff3a36 6792 u8 reserved_at_140[0x15];
e281682b
SM		 6793 u8 ber_test_time[0xb];
6794};
6795
6796struct mlx5_ifc_pspa_reg_bits {
6797 u8 swid[0x8];
6798 u8 local_port[0x8];
6799 u8 sub_port[0x8];
b4ff3a36 6800 u8 reserved_at_18[0x8];
e281682b 6801
b4ff3a36 6802 u8 reserved_at_20[0x20];
e281682b
SM		 6803};
6804
6805struct mlx5_ifc_pqdr_reg_bits {
b4ff3a36 6806 u8 reserved_at_0[0x8];
e281682b 6807 u8 local_port[0x8];
b4ff3a36 6808 u8 reserved_at_10[0x5];
e281682b 6809 u8 prio[0x3];
b4ff3a36 6810 u8 reserved_at_18[0x6];
e281682b
SM		 6811 u8 mode[0x2];
6812
b4ff3a36 6813 u8 reserved_at_20[0x20];
e281682b 6814
b4ff3a36 6815 u8 reserved_at_40[0x10];
e281682b
SM		 6816 u8 min_threshold[0x10];
6817
b4ff3a36 6818 u8 reserved_at_60[0x10];
e281682b
SM		 6819 u8 max_threshold[0x10];
6820
b4ff3a36 6821 u8 reserved_at_80[0x10];
e281682b
SM		 6822 u8 mark_probability_denominator[0x10];
6823
b4ff3a36 6824 u8 reserved_at_a0[0x60];
e281682b
SM		 6825};
6826
6827struct mlx5_ifc_ppsc_reg_bits {
b4ff3a36 6828 u8 reserved_at_0[0x8];
e281682b 6829 u8 local_port[0x8];
b4ff3a36 6830 u8 reserved_at_10[0x10];
e281682b 6831
b4ff3a36 6832 u8 reserved_at_20[0x60];
e281682b 6833
b4ff3a36 6834 u8 reserved_at_80[0x1c];
e281682b
SM		 6835 u8 wrps_admin[0x4];
6836
b4ff3a36 6837 u8 reserved_at_a0[0x1c];
e281682b
SM		 6838 u8 wrps_status[0x4];
6839
b4ff3a36 6840 u8 reserved_at_c0[0x8];
e281682b 6841 u8 up_threshold[0x8];
b4ff3a36 6842 u8 reserved_at_d0[0x8];
e281682b
SM		 6843 u8 down_threshold[0x8];
6844
b4ff3a36 6845 u8 reserved_at_e0[0x20];
e281682b 6846
b4ff3a36 6847 u8 reserved_at_100[0x1c];
e281682b
SM		 6848 u8 srps_admin[0x4];
6849
b4ff3a36 6850 u8 reserved_at_120[0x1c];
e281682b
SM		 6851 u8 srps_status[0x4];
6852
b4ff3a36 6853 u8 reserved_at_140[0x40];
e281682b
SM		 6854};
6855
6856struct mlx5_ifc_pplr_reg_bits {
b4ff3a36 6857 u8 reserved_at_0[0x8];
e281682b 6858 u8 local_port[0x8];
b4ff3a36 6859 u8 reserved_at_10[0x10];
e281682b 6860
b4ff3a36 6861 u8 reserved_at_20[0x8];
e281682b 6862 u8 lb_cap[0x8];
b4ff3a36 6863 u8 reserved_at_30[0x8];
e281682b
SM		 6864 u8 lb_en[0x8];
6865};
6866
6867struct mlx5_ifc_pplm_reg_bits {
b4ff3a36 6868 u8 reserved_at_0[0x8];
e281682b 6869 u8 local_port[0x8];
b4ff3a36 6870 u8 reserved_at_10[0x10];
e281682b 6871
b4ff3a36 6872 u8 reserved_at_20[0x20];
e281682b
SM		 6873
6874 u8 port_profile_mode[0x8];
6875 u8 static_port_profile[0x8];
6876 u8 active_port_profile[0x8];
b4ff3a36 6877 u8 reserved_at_58[0x8];
e281682b
SM		 6878
6879 u8 retransmission_active[0x8];
6880 u8 fec_mode_active[0x18];
6881
b4ff3a36 6882 u8 reserved_at_80[0x20];
e281682b
SM		 6883};
6884
6885struct mlx5_ifc_ppcnt_reg_bits {
6886 u8 swid[0x8];
6887 u8 local_port[0x8];
6888 u8 pnat[0x2];
b4ff3a36 6889 u8 reserved_at_12[0x8];
e281682b
SM		 6890 u8 grp[0x6];
6891
6892 u8 clr[0x1];
b4ff3a36 6893 u8 reserved_at_21[0x1c];
e281682b
SM		 6894 u8 prio_tc[0x3];
6895
6896 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
6897};
6898
6899struct mlx5_ifc_ppad_reg_bits {
b4ff3a36 6900 u8 reserved_at_0[0x3];
e281682b 6901 u8 single_mac[0x1];
b4ff3a36 6902 u8 reserved_at_4[0x4];
e281682b
SM		 6903 u8 local_port[0x8];
6904 u8 mac_47_32[0x10];
6905
6906 u8 mac_31_0[0x20];
6907
b4ff3a36 6908 u8 reserved_at_40[0x40];
e281682b
SM		 6909};
6910
6911struct mlx5_ifc_pmtu_reg_bits {
b4ff3a36 6912 u8 reserved_at_0[0x8];
e281682b 6913 u8 local_port[0x8];
b4ff3a36 6914 u8 reserved_at_10[0x10];
e281682b
SM		 6915
6916 u8 max_mtu[0x10];
b4ff3a36 6917 u8 reserved_at_30[0x10];
e281682b
SM		 6918
6919 u8 admin_mtu[0x10];
b4ff3a36 6920 u8 reserved_at_50[0x10];
e281682b
SM		 6921
6922 u8 oper_mtu[0x10];
b4ff3a36 6923 u8 reserved_at_70[0x10];
e281682b
SM		 6924};
6925
6926struct mlx5_ifc_pmpr_reg_bits {
b4ff3a36 6927 u8 reserved_at_0[0x8];
e281682b 6928 u8 module[0x8];
b4ff3a36 6929 u8 reserved_at_10[0x10];
e281682b 6930
b4ff3a36 6931 u8 reserved_at_20[0x18];
e281682b
SM		 6932 u8 attenuation_5g[0x8];
6933
b4ff3a36 6934 u8 reserved_at_40[0x18];
e281682b
SM		 6935 u8 attenuation_7g[0x8];
6936
b4ff3a36 6937 u8 reserved_at_60[0x18];
e281682b
SM		 6938 u8 attenuation_12g[0x8];
6939};
6940
6941struct mlx5_ifc_pmpe_reg_bits {
b4ff3a36 6942 u8 reserved_at_0[0x8];
e281682b 6943 u8 module[0x8];
b4ff3a36 6944 u8 reserved_at_10[0xc];
e281682b
SM		 6945 u8 module_status[0x4];
6946
b4ff3a36 6947 u8 reserved_at_20[0x60];
e281682b
SM		 6948};
6949
6950struct mlx5_ifc_pmpc_reg_bits {
6951 u8 module_state_updated[32][0x8];
6952};
6953
6954struct mlx5_ifc_pmlpn_reg_bits {
b4ff3a36 6955 u8 reserved_at_0[0x4];
e281682b
SM		 6956 u8 mlpn_status[0x4];
6957 u8 local_port[0x8];
b4ff3a36 6958 u8 reserved_at_10[0x10];
e281682b
SM		 6959
6960 u8 e[0x1];
b4ff3a36 6961 u8 reserved_at_21[0x1f];
e281682b
SM		 6962};
6963
6964struct mlx5_ifc_pmlp_reg_bits {
6965 u8 rxtx[0x1];
b4ff3a36 6966 u8 reserved_at_1[0x7];
e281682b 6967 u8 local_port[0x8];
b4ff3a36 6968 u8 reserved_at_10[0x8];
e281682b
SM		 6969 u8 width[0x8];
6970
6971 u8 lane0_module_mapping[0x20];
6972
6973 u8 lane1_module_mapping[0x20];
6974
6975 u8 lane2_module_mapping[0x20];
6976
6977 u8 lane3_module_mapping[0x20];
6978
b4ff3a36 6979 u8 reserved_at_a0[0x160];
e281682b
SM		 6980};
6981
6982struct mlx5_ifc_pmaos_reg_bits {
b4ff3a36 6983 u8 reserved_at_0[0x8];
e281682b 6984 u8 module[0x8];
b4ff3a36 6985 u8 reserved_at_10[0x4];
e281682b 6986 u8 admin_status[0x4];
b4ff3a36 6987 u8 reserved_at_18[0x4];
e281682b
SM		 6988 u8 oper_status[0x4];
6989
6990 u8 ase[0x1];
6991 u8 ee[0x1];
b4ff3a36 6992 u8 reserved_at_22[0x1c];
e281682b
SM		 6993 u8 e[0x2];
6994
b4ff3a36 6995 u8 reserved_at_40[0x40];
e281682b
SM		 6996};
6997
6998struct mlx5_ifc_plpc_reg_bits {
b4ff3a36 6999 u8 reserved_at_0[0x4];
e281682b 7000 u8 profile_id[0xc];
b4ff3a36 7001 u8 reserved_at_10[0x4];
e281682b 7002 u8 proto_mask[0x4];
b4ff3a36 7003 u8 reserved_at_18[0x8];
e281682b 7004
b4ff3a36 7005 u8 reserved_at_20[0x10];
e281682b
SM		 7006 u8 lane_speed[0x10];
7007
b4ff3a36 7008 u8 reserved_at_40[0x17];
e281682b
SM		 7009 u8 lpbf[0x1];
7010 u8 fec_mode_policy[0x8];
7011
7012 u8 retransmission_capability[0x8];
7013 u8 fec_mode_capability[0x18];
7014
7015 u8 retransmission_support_admin[0x8];
7016 u8 fec_mode_support_admin[0x18];
7017
7018 u8 retransmission_request_admin[0x8];
7019 u8 fec_mode_request_admin[0x18];
7020
b4ff3a36 7021 u8 reserved_at_c0[0x80];
e281682b
SM		 7022};
7023
7024struct mlx5_ifc_plib_reg_bits {
b4ff3a36 7025 u8 reserved_at_0[0x8];
e281682b 7026 u8 local_port[0x8];
b4ff3a36 7027 u8 reserved_at_10[0x8];
e281682b
SM		 7028 u8 ib_port[0x8];
7029
b4ff3a36 7030 u8 reserved_at_20[0x60];
e281682b
SM		 7031};
7032
7033struct mlx5_ifc_plbf_reg_bits {
b4ff3a36 7034 u8 reserved_at_0[0x8];
e281682b 7035 u8 local_port[0x8];
b4ff3a36 7036 u8 reserved_at_10[0xd];
e281682b
SM		 7037 u8 lbf_mode[0x3];
7038
b4ff3a36 7039 u8 reserved_at_20[0x20];
e281682b
SM		 7040};
7041
7042struct mlx5_ifc_pipg_reg_bits {
b4ff3a36 7043 u8 reserved_at_0[0x8];
e281682b 7044 u8 local_port[0x8];
b4ff3a36 7045 u8 reserved_at_10[0x10];
e281682b
SM		 7046
7047 u8 dic[0x1];
b4ff3a36 7048 u8 reserved_at_21[0x19];
e281682b 7049 u8 ipg[0x4];
b4ff3a36 7050 u8 reserved_at_3e[0x2];
e281682b
SM		 7051};
7052
7053struct mlx5_ifc_pifr_reg_bits {
b4ff3a36 7054 u8 reserved_at_0[0x8];
e281682b 7055 u8 local_port[0x8];
b4ff3a36 7056 u8 reserved_at_10[0x10];
e281682b 7057
b4ff3a36 7058 u8 reserved_at_20[0xe0];
e281682b
SM		 7059
7060 u8 port_filter[8][0x20];
7061
7062 u8 port_filter_update_en[8][0x20];
7063};
7064
7065struct mlx5_ifc_pfcc_reg_bits {
b4ff3a36 7066 u8 reserved_at_0[0x8];
e281682b 7067 u8 local_port[0x8];
b4ff3a36 7068 u8 reserved_at_10[0x10];
e281682b
SM		 7069
7070 u8 ppan[0x4];
b4ff3a36 7071 u8 reserved_at_24[0x4];
e281682b 7072 u8 prio_mask_tx[0x8];
b4ff3a36 7073 u8 reserved_at_30[0x8];
e281682b
SM		 7074 u8 prio_mask_rx[0x8];
7075
7076 u8 pptx[0x1];
7077 u8 aptx[0x1];
b4ff3a36 7078 u8 reserved_at_42[0x6];
e281682b 7079 u8 pfctx[0x8];
b4ff3a36 7080 u8 reserved_at_50[0x10];
e281682b
SM		 7081
7082 u8 pprx[0x1];
7083 u8 aprx[0x1];
b4ff3a36 7084 u8 reserved_at_62[0x6];
e281682b 7085 u8 pfcrx[0x8];
b4ff3a36 7086 u8 reserved_at_70[0x10];
e281682b 7087
b4ff3a36 7088 u8 reserved_at_80[0x80];
e281682b
SM		 7089};
7090
7091struct mlx5_ifc_pelc_reg_bits {
7092 u8 op[0x4];
b4ff3a36 7093 u8 reserved_at_4[0x4];
e281682b 7094 u8 local_port[0x8];
b4ff3a36 7095 u8 reserved_at_10[0x10];
e281682b
SM		 7096
7097 u8 op_admin[0x8];
7098 u8 op_capability[0x8];
7099 u8 op_request[0x8];
7100 u8 op_active[0x8];
7101
7102 u8 admin[0x40];
7103
7104 u8 capability[0x40];
7105
7106 u8 request[0x40];
7107
7108 u8 active[0x40];
7109
b4ff3a36 7110 u8 reserved_at_140[0x80];
e281682b
SM		 7111};
7112
7113struct mlx5_ifc_peir_reg_bits {
b4ff3a36 7114 u8 reserved_at_0[0x8];
e281682b 7115 u8 local_port[0x8];
b4ff3a36 7116 u8 reserved_at_10[0x10];
e281682b 7117
b4ff3a36 7118 u8 reserved_at_20[0xc];
e281682b 7119 u8 error_count[0x4];
b4ff3a36 7120 u8 reserved_at_30[0x10];
e281682b 7121
b4ff3a36 7122 u8 reserved_at_40[0xc];
e281682b 7123 u8 lane[0x4];
b4ff3a36 7124 u8 reserved_at_50[0x8];
e281682b
SM		 7125 u8 error_type[0x8];
7126};
7127
7128struct mlx5_ifc_pcap_reg_bits {
b4ff3a36 7129 u8 reserved_at_0[0x8];
e281682b 7130 u8 local_port[0x8];
b4ff3a36 7131 u8 reserved_at_10[0x10];
e281682b
SM		 7132
7133 u8 port_capability_mask[4][0x20];
7134};
7135
7136struct mlx5_ifc_paos_reg_bits {
7137 u8 swid[0x8];
7138 u8 local_port[0x8];
b4ff3a36 7139 u8 reserved_at_10[0x4];
e281682b 7140 u8 admin_status[0x4];
b4ff3a36 7141 u8 reserved_at_18[0x4];
e281682b
SM		 7142 u8 oper_status[0x4];
7143
7144 u8 ase[0x1];
7145 u8 ee[0x1];
b4ff3a36 7146 u8 reserved_at_22[0x1c];
e281682b
SM		 7147 u8 e[0x2];
7148
b4ff3a36 7149 u8 reserved_at_40[0x40];
e281682b
SM		 7150};
7151
7152struct mlx5_ifc_pamp_reg_bits {
b4ff3a36 7153 u8 reserved_at_0[0x8];
e281682b 7154 u8 opamp_group[0x8];
b4ff3a36 7155 u8 reserved_at_10[0xc];
e281682b
SM		 7156 u8 opamp_group_type[0x4];
7157
7158 u8 start_index[0x10];
b4ff3a36 7159 u8 reserved_at_30[0x4];
e281682b
SM		 7160 u8 num_of_indices[0xc];
7161
7162 u8 index_data[18][0x10];
7163};
7164
7d5e1423
SM		 7165struct mlx5_ifc_pcmr_reg_bits {
7166 u8 reserved_at_0[0x8];
7167 u8 local_port[0x8];
7168 u8 reserved_at_10[0x2e];
7169 u8 fcs_cap[0x1];
7170 u8 reserved_at_3f[0x1f];
7171 u8 fcs_chk[0x1];
7172 u8 reserved_at_5f[0x1];
7173};
7174
e281682b 7175struct mlx5_ifc_lane_2_module_mapping_bits {
b4ff3a36 7176 u8 reserved_at_0[0x6];
e281682b 7177 u8 rx_lane[0x2];
b4ff3a36 7178 u8 reserved_at_8[0x6];
e281682b 7179 u8 tx_lane[0x2];
b4ff3a36 7180 u8 reserved_at_10[0x8];
e281682b
SM		 7181 u8 module[0x8];
7182};
7183
7184struct mlx5_ifc_bufferx_reg_bits {
b4ff3a36 7185 u8 reserved_at_0[0x6];
e281682b
SM		 7186 u8 lossy[0x1];
7187 u8 epsb[0x1];
b4ff3a36 7188 u8 reserved_at_8[0xc];
e281682b
SM		 7189 u8 size[0xc];
7190
7191 u8 xoff_threshold[0x10];
7192 u8 xon_threshold[0x10];
7193};
7194
7195struct mlx5_ifc_set_node_in_bits {
7196 u8 node_description[64][0x8];
7197};
7198
7199struct mlx5_ifc_register_power_settings_bits {
b4ff3a36 7200 u8 reserved_at_0[0x18];
e281682b
SM		 7201 u8 power_settings_level[0x8];
7202
b4ff3a36 7203 u8 reserved_at_20[0x60];
e281682b
SM		 7204};
7205
7206struct mlx5_ifc_register_host_endianness_bits {
7207 u8 he[0x1];
b4ff3a36 7208 u8 reserved_at_1[0x1f];
e281682b 7209
b4ff3a36 7210 u8 reserved_at_20[0x60];
e281682b
SM		 7211};
7212
7213struct mlx5_ifc_umr_pointer_desc_argument_bits {
b4ff3a36 7214 u8 reserved_at_0[0x20];
e281682b
SM		 7215
7216 u8 mkey[0x20];
7217
7218 u8 addressh_63_32[0x20];
7219
7220 u8 addressl_31_0[0x20];
7221};
7222
7223struct mlx5_ifc_ud_adrs_vector_bits {
7224 u8 dc_key[0x40];
7225
7226 u8 ext[0x1];
b4ff3a36 7227 u8 reserved_at_41[0x7];
e281682b
SM		 7228 u8 destination_qp_dct[0x18];
7229
7230 u8 static_rate[0x4];
7231 u8 sl_eth_prio[0x4];
7232 u8 fl[0x1];
7233 u8 mlid[0x7];
7234 u8 rlid_udp_sport[0x10];
7235
b4ff3a36 7236 u8 reserved_at_80[0x20];
e281682b
SM		 7237
7238 u8 rmac_47_16[0x20];
7239
7240 u8 rmac_15_0[0x10];
7241 u8 tclass[0x8];
7242 u8 hop_limit[0x8];
7243
b4ff3a36 7244 u8 reserved_at_e0[0x1];
e281682b 7245 u8 grh[0x1];
b4ff3a36 7246 u8 reserved_at_e2[0x2];
e281682b
SM		 7247 u8 src_addr_index[0x8];
7248 u8 flow_label[0x14];
7249
7250 u8 rgid_rip[16][0x8];
7251};
7252
7253struct mlx5_ifc_pages_req_event_bits {
b4ff3a36 7254 u8 reserved_at_0[0x10];
e281682b
SM		 7255 u8 function_id[0x10];
7256
7257 u8 num_pages[0x20];
7258
b4ff3a36 7259 u8 reserved_at_40[0xa0];
e281682b
SM		 7260};
7261
7262struct mlx5_ifc_eqe_bits {
b4ff3a36 7263 u8 reserved_at_0[0x8];
e281682b 7264 u8 event_type[0x8];
b4ff3a36 7265 u8 reserved_at_10[0x8];
e281682b
SM		 7266 u8 event_sub_type[0x8];
7267
b4ff3a36 7268 u8 reserved_at_20[0xe0];
e281682b
SM		 7269
7270 union mlx5_ifc_event_auto_bits event_data;
7271
b4ff3a36 7272 u8 reserved_at_1e0[0x10];
e281682b 7273 u8 signature[0x8];
b4ff3a36 7274 u8 reserved_at_1f8[0x7];
e281682b
SM		 7275 u8 owner[0x1];
7276};
7277
7278enum {
7279 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
7280};
7281
7282struct mlx5_ifc_cmd_queue_entry_bits {
7283 u8 type[0x8];
b4ff3a36 7284 u8 reserved_at_8[0x18];
e281682b
SM		 7285
7286 u8 input_length[0x20];
7287
7288 u8 input_mailbox_pointer_63_32[0x20];
7289
7290 u8 input_mailbox_pointer_31_9[0x17];
b4ff3a36 7291 u8 reserved_at_77[0x9];
e281682b
SM		 7292
7293 u8 command_input_inline_data[16][0x8];
7294
7295 u8 command_output_inline_data[16][0x8];
7296
7297 u8 output_mailbox_pointer_63_32[0x20];
7298
7299 u8 output_mailbox_pointer_31_9[0x17];
b4ff3a36 7300 u8 reserved_at_1b7[0x9];
e281682b
SM		 7301
7302 u8 output_length[0x20];
7303
7304 u8 token[0x8];
7305 u8 signature[0x8];
b4ff3a36 7306 u8 reserved_at_1f0[0x8];
e281682b
SM		 7307 u8 status[0x7];
7308 u8 ownership[0x1];
7309};
7310
7311struct mlx5_ifc_cmd_out_bits {
7312 u8 status[0x8];
b4ff3a36 7313 u8 reserved_at_8[0x18];
e281682b
SM		 7314
7315 u8 syndrome[0x20];
7316
7317 u8 command_output[0x20];
7318};
7319
7320struct mlx5_ifc_cmd_in_bits {
7321 u8 opcode[0x10];
b4ff3a36 7322 u8 reserved_at_10[0x10];
e281682b 7323
b4ff3a36 7324 u8 reserved_at_20[0x10];
e281682b
SM		 7325 u8 op_mod[0x10];
7326
7327 u8 command[0][0x20];
7328};
7329
7330struct mlx5_ifc_cmd_if_box_bits {
7331 u8 mailbox_data[512][0x8];
7332
b4ff3a36 7333 u8 reserved_at_1000[0x180];
e281682b
SM		 7334
7335 u8 next_pointer_63_32[0x20];
7336
7337 u8 next_pointer_31_10[0x16];
b4ff3a36 7338 u8 reserved_at_11b6[0xa];
e281682b
SM		 7339
7340 u8 block_number[0x20];
7341
b4ff3a36 7342 u8 reserved_at_11e0[0x8];
e281682b
SM		 7343 u8 token[0x8];
7344 u8 ctrl_signature[0x8];
7345 u8 signature[0x8];
7346};
7347
7348struct mlx5_ifc_mtt_bits {
7349 u8 ptag_63_32[0x20];
7350
7351 u8 ptag_31_8[0x18];
b4ff3a36 7352 u8 reserved_at_38[0x6];
e281682b
SM		 7353 u8 wr_en[0x1];
7354 u8 rd_en[0x1];
7355};
7356
928cfe87
TT		 7357struct mlx5_ifc_query_wol_rol_out_bits {
7358 u8 status[0x8];
7359 u8 reserved_at_8[0x18];
7360
7361 u8 syndrome[0x20];
7362
7363 u8 reserved_at_40[0x10];
7364 u8 rol_mode[0x8];
7365 u8 wol_mode[0x8];
7366
7367 u8 reserved_at_60[0x20];
7368};
7369
7370struct mlx5_ifc_query_wol_rol_in_bits {
7371 u8 opcode[0x10];
7372 u8 reserved_at_10[0x10];
7373
7374 u8 reserved_at_20[0x10];
7375 u8 op_mod[0x10];
7376
7377 u8 reserved_at_40[0x40];
7378};
7379
7380struct mlx5_ifc_set_wol_rol_out_bits {
7381 u8 status[0x8];
7382 u8 reserved_at_8[0x18];
7383
7384 u8 syndrome[0x20];
7385
7386 u8 reserved_at_40[0x40];
7387};
7388
7389struct mlx5_ifc_set_wol_rol_in_bits {
7390 u8 opcode[0x10];
7391 u8 reserved_at_10[0x10];
7392
7393 u8 reserved_at_20[0x10];
7394 u8 op_mod[0x10];
7395
7396 u8 rol_mode_valid[0x1];
7397 u8 wol_mode_valid[0x1];
7398 u8 reserved_at_42[0xe];
7399 u8 rol_mode[0x8];
7400 u8 wol_mode[0x8];
7401
7402 u8 reserved_at_60[0x20];
7403};
7404
e281682b
SM		 7405enum {
7406 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
7407 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
7408 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
7409};
7410
7411enum {
7412 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
7413 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
7414 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
7415};
7416
7417enum {
7418 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
7419 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
7420 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
7421 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
7422 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
7423 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
7424 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
7425 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
7426 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
7427 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
7428 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
7429};
7430
7431struct mlx5_ifc_initial_seg_bits {
7432 u8 fw_rev_minor[0x10];
7433 u8 fw_rev_major[0x10];
7434
7435 u8 cmd_interface_rev[0x10];
7436 u8 fw_rev_subminor[0x10];
7437
b4ff3a36 7438 u8 reserved_at_40[0x40];
e281682b
SM		 7439
7440 u8 cmdq_phy_addr_63_32[0x20];
7441
7442 u8 cmdq_phy_addr_31_12[0x14];
b4ff3a36 7443 u8 reserved_at_b4[0x2];
e281682b
SM		 7444 u8 nic_interface[0x2];
7445 u8 log_cmdq_size[0x4];
7446 u8 log_cmdq_stride[0x4];
7447
7448 u8 command_doorbell_vector[0x20];
7449
b4ff3a36 7450 u8 reserved_at_e0[0xf00];
e281682b
SM		 7451
7452 u8 initializing[0x1];
b4ff3a36 7453 u8 reserved_at_fe1[0x4];
e281682b 7454 u8 nic_interface_supported[0x3];
b4ff3a36 7455 u8 reserved_at_fe8[0x18];
e281682b
SM		 7456
7457 struct mlx5_ifc_health_buffer_bits health_buffer;
7458
7459 u8 no_dram_nic_offset[0x20];
7460
b4ff3a36 7461 u8 reserved_at_1220[0x6e40];
e281682b 7462
b4ff3a36 7463 u8 reserved_at_8060[0x1f];
e281682b
SM		 7464 u8 clear_int[0x1];
7465
7466 u8 health_syndrome[0x8];
7467 u8 health_counter[0x18];
7468
b4ff3a36 7469 u8 reserved_at_80a0[0x17fc0];
e281682b
SM		 7470};
7471
7472union mlx5_ifc_ports_control_registers_document_bits {
7473 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
7474 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
7475 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
7476 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
7477 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
7478 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
7479 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
7480 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
7481 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
7482 struct mlx5_ifc_pamp_reg_bits pamp_reg;
7483 struct mlx5_ifc_paos_reg_bits paos_reg;
7484 struct mlx5_ifc_pcap_reg_bits pcap_reg;
7485 struct mlx5_ifc_peir_reg_bits peir_reg;
7486 struct mlx5_ifc_pelc_reg_bits pelc_reg;
7487 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
1c64bf6f 7488 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b
SM		 7489 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
7490 struct mlx5_ifc_pifr_reg_bits pifr_reg;
7491 struct mlx5_ifc_pipg_reg_bits pipg_reg;
7492 struct mlx5_ifc_plbf_reg_bits plbf_reg;
7493 struct mlx5_ifc_plib_reg_bits plib_reg;
7494 struct mlx5_ifc_plpc_reg_bits plpc_reg;
7495 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
7496 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
7497 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
7498 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
7499 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
7500 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
7501 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
7502 struct mlx5_ifc_ppad_reg_bits ppad_reg;
7503 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
7504 struct mlx5_ifc_pplm_reg_bits pplm_reg;
7505 struct mlx5_ifc_pplr_reg_bits pplr_reg;
7506 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
7507 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
7508 struct mlx5_ifc_pspa_reg_bits pspa_reg;
7509 struct mlx5_ifc_ptas_reg_bits ptas_reg;
7510 struct mlx5_ifc_ptys_reg_bits ptys_reg;
7d5e1423 7511 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
e281682b
SM		 7512 struct mlx5_ifc_pude_reg_bits pude_reg;
7513 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
7514 struct mlx5_ifc_slrg_reg_bits slrg_reg;
7515 struct mlx5_ifc_sltp_reg_bits sltp_reg;
b4ff3a36 7516 u8 reserved_at_0[0x60e0];
e281682b
SM		 7517};
7518
7519union mlx5_ifc_debug_enhancements_document_bits {
7520 struct mlx5_ifc_health_buffer_bits health_buffer;
b4ff3a36 7521 u8 reserved_at_0[0x200];
e281682b
SM		 7522};
7523
7524union mlx5_ifc_uplink_pci_interface_document_bits {
7525 struct mlx5_ifc_initial_seg_bits initial_seg;
b4ff3a36 7526 u8 reserved_at_0[0x20060];
b775516b
EC		 7527};
7528
2cc43b49
MG		 7529struct mlx5_ifc_set_flow_table_root_out_bits {
7530 u8 status[0x8];
b4ff3a36 7531 u8 reserved_at_8[0x18];
2cc43b49
MG		 7532
7533 u8 syndrome[0x20];
7534
b4ff3a36 7535 u8 reserved_at_40[0x40];
2cc43b49
MG		 7536};
7537
7538struct mlx5_ifc_set_flow_table_root_in_bits {
7539 u8 opcode[0x10];
b4ff3a36 7540 u8 reserved_at_10[0x10];
2cc43b49 7541
b4ff3a36 7542 u8 reserved_at_20[0x10];
2cc43b49
MG		 7543 u8 op_mod[0x10];
7544
7d5e1423
SM		 7545 u8 other_vport[0x1];
7546 u8 reserved_at_41[0xf];
7547 u8 vport_number[0x10];
7548
7549 u8 reserved_at_60[0x20];
2cc43b49
MG		 7550
7551 u8 table_type[0x8];
b4ff3a36 7552 u8 reserved_at_88[0x18];
2cc43b49 7553
b4ff3a36 7554 u8 reserved_at_a0[0x8];
2cc43b49
MG		 7555 u8 table_id[0x18];
7556
b4ff3a36 7557 u8 reserved_at_c0[0x140];
2cc43b49
MG		 7558};
7559
34a40e68
MG		 7560enum {
7561 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = 0x1,
7562};
7563
7564struct mlx5_ifc_modify_flow_table_out_bits {
7565 u8 status[0x8];
b4ff3a36 7566 u8 reserved_at_8[0x18];
34a40e68
MG		 7567
7568 u8 syndrome[0x20];
7569
b4ff3a36 7570 u8 reserved_at_40[0x40];
34a40e68
MG		 7571};
7572
7573struct mlx5_ifc_modify_flow_table_in_bits {
7574 u8 opcode[0x10];
b4ff3a36 7575 u8 reserved_at_10[0x10];
34a40e68 7576
b4ff3a36 7577 u8 reserved_at_20[0x10];
34a40e68
MG		 7578 u8 op_mod[0x10];
7579
7d5e1423
SM		 7580 u8 other_vport[0x1];
7581 u8 reserved_at_41[0xf];
7582 u8 vport_number[0x10];
34a40e68 7583
b4ff3a36 7584 u8 reserved_at_60[0x10];
34a40e68
MG		 7585 u8 modify_field_select[0x10];
7586
7587 u8 table_type[0x8];
b4ff3a36 7588 u8 reserved_at_88[0x18];
34a40e68 7589
b4ff3a36 7590 u8 reserved_at_a0[0x8];
34a40e68
MG		 7591 u8 table_id[0x18];
7592
b4ff3a36 7593 u8 reserved_at_c0[0x4];
34a40e68 7594 u8 table_miss_mode[0x4];
b4ff3a36 7595 u8 reserved_at_c8[0x18];
34a40e68 7596
b4ff3a36 7597 u8 reserved_at_e0[0x8];
34a40e68
MG		 7598 u8 table_miss_id[0x18];
7599
b4ff3a36 7600 u8 reserved_at_100[0x100];
34a40e68
MG		 7601};
7602
4f3961ee
SM		 7603struct mlx5_ifc_ets_tcn_config_reg_bits {
7604 u8 g[0x1];
7605 u8 b[0x1];
7606 u8 r[0x1];
7607 u8 reserved_at_3[0x9];
7608 u8 group[0x4];
7609 u8 reserved_at_10[0x9];
7610 u8 bw_allocation[0x7];
7611
7612 u8 reserved_at_20[0xc];
7613 u8 max_bw_units[0x4];
7614 u8 reserved_at_30[0x8];
7615 u8 max_bw_value[0x8];
7616};
7617
7618struct mlx5_ifc_ets_global_config_reg_bits {
7619 u8 reserved_at_0[0x2];
7620 u8 r[0x1];
7621 u8 reserved_at_3[0x1d];
7622
7623 u8 reserved_at_20[0xc];
7624 u8 max_bw_units[0x4];
7625 u8 reserved_at_30[0x8];
7626 u8 max_bw_value[0x8];
7627};
7628
7629struct mlx5_ifc_qetc_reg_bits {
7630 u8 reserved_at_0[0x8];
7631 u8 port_number[0x8];
7632 u8 reserved_at_10[0x30];
7633
7634 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
7635 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
7636};
7637
7638struct mlx5_ifc_qtct_reg_bits {
7639 u8 reserved_at_0[0x8];
7640 u8 port_number[0x8];
7641 u8 reserved_at_10[0xd];
7642 u8 prio[0x3];
7643
7644 u8 reserved_at_20[0x1d];
7645 u8 tclass[0x3];
7646};
7647
7d5e1423
SM		 7648struct mlx5_ifc_mcia_reg_bits {
7649 u8 l[0x1];
7650 u8 reserved_at_1[0x7];
7651 u8 module[0x8];
7652 u8 reserved_at_10[0x8];
7653 u8 status[0x8];
7654
7655 u8 i2c_device_address[0x8];
7656 u8 page_number[0x8];
7657 u8 device_address[0x10];
7658
7659 u8 reserved_at_40[0x10];
7660 u8 size[0x10];
7661
7662 u8 reserved_at_60[0x20];
7663
7664 u8 dword_0[0x20];
7665 u8 dword_1[0x20];
7666 u8 dword_2[0x20];
7667 u8 dword_3[0x20];
7668 u8 dword_4[0x20];
7669 u8 dword_5[0x20];
7670 u8 dword_6[0x20];
7671 u8 dword_7[0x20];
7672 u8 dword_8[0x20];
7673 u8 dword_9[0x20];
7674 u8 dword_10[0x20];
7675 u8 dword_11[0x20];
7676};
7677
7486216b
SM		 7678struct mlx5_ifc_dcbx_param_bits {
7679 u8 dcbx_cee_cap[0x1];
7680 u8 dcbx_ieee_cap[0x1];
7681 u8 dcbx_standby_cap[0x1];
7682 u8 reserved_at_0[0x5];
7683 u8 port_number[0x8];
7684 u8 reserved_at_10[0xa];
7685 u8 max_application_table_size[6];
7686 u8 reserved_at_20[0x15];
7687 u8 version_oper[0x3];
7688 u8 reserved_at_38[5];
7689 u8 version_admin[0x3];
7690 u8 willing_admin[0x1];
7691 u8 reserved_at_41[0x3];
7692 u8 pfc_cap_oper[0x4];
7693 u8 reserved_at_48[0x4];
7694 u8 pfc_cap_admin[0x4];
7695 u8 reserved_at_50[0x4];
7696 u8 num_of_tc_oper[0x4];
7697 u8 reserved_at_58[0x4];
7698 u8 num_of_tc_admin[0x4];
7699 u8 remote_willing[0x1];
7700 u8 reserved_at_61[3];
7701 u8 remote_pfc_cap[4];
7702 u8 reserved_at_68[0x14];
7703 u8 remote_num_of_tc[0x4];
7704 u8 reserved_at_80[0x18];
7705 u8 error[0x8];
7706 u8 reserved_at_a0[0x160];
7707};
d29b796a 7708#endif /* MLX5_IFC_H */
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