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net/mlx5: Separate query_port_proto_oper for IB and EN
[mirror_ubuntu-artful-kernel.git] / include / linux / mlx5 / mlx5_ifc.h
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d29b796a 1/*
e281682b 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
d29b796a
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
e281682b 31*/
d29b796a
EC		 32#ifndef MLX5_IFC_H
33#define MLX5_IFC_H
34
e281682b
SM		 35enum {
36 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
37 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
38 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
39 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
40 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
41 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
42 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
43 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
44 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
45 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
46 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
47 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
48 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
49 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
50 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
51 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
52 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
53 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
54 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
55 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
56 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
57 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
58 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
59 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb
60};
61
62enum {
63 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
64 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
65 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
66 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
67};
68
f91e6d89
EBE		 69enum {
70 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE = 0x0,
71 MLX5_SET_HCA_CAP_OP_MOD_ATOMIC = 0x3,
72};
73
d29b796a
EC		 74enum {
75 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
76 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
77 MLX5_CMD_OP_INIT_HCA = 0x102,
78 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
79 MLX5_CMD_OP_ENABLE_HCA = 0x104,
80 MLX5_CMD_OP_DISABLE_HCA = 0x105,
81 MLX5_CMD_OP_QUERY_PAGES = 0x107,
82 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
83 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
e281682b
SM		 84 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
85 MLX5_CMD_OP_SET_ISSI = 0x10b,
d29b796a
EC		 86 MLX5_CMD_OP_CREATE_MKEY = 0x200,
87 MLX5_CMD_OP_QUERY_MKEY = 0x201,
88 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
89 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
90 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
91 MLX5_CMD_OP_CREATE_EQ = 0x301,
92 MLX5_CMD_OP_DESTROY_EQ = 0x302,
93 MLX5_CMD_OP_QUERY_EQ = 0x303,
94 MLX5_CMD_OP_GEN_EQE = 0x304,
95 MLX5_CMD_OP_CREATE_CQ = 0x400,
96 MLX5_CMD_OP_DESTROY_CQ = 0x401,
97 MLX5_CMD_OP_QUERY_CQ = 0x402,
98 MLX5_CMD_OP_MODIFY_CQ = 0x403,
99 MLX5_CMD_OP_CREATE_QP = 0x500,
100 MLX5_CMD_OP_DESTROY_QP = 0x501,
101 MLX5_CMD_OP_RST2INIT_QP = 0x502,
102 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
103 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
104 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
105 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
106 MLX5_CMD_OP_2ERR_QP = 0x507,
107 MLX5_CMD_OP_2RST_QP = 0x50a,
108 MLX5_CMD_OP_QUERY_QP = 0x50b,
e281682b 109 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
d29b796a
EC		 110 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
111 MLX5_CMD_OP_CREATE_PSV = 0x600,
112 MLX5_CMD_OP_DESTROY_PSV = 0x601,
113 MLX5_CMD_OP_CREATE_SRQ = 0x700,
114 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
115 MLX5_CMD_OP_QUERY_SRQ = 0x702,
116 MLX5_CMD_OP_ARM_RQ = 0x703,
e281682b
SM		 117 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
118 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
119 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
120 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
d29b796a
EC		 121 MLX5_CMD_OP_CREATE_DCT = 0x710,
122 MLX5_CMD_OP_DESTROY_DCT = 0x711,
123 MLX5_CMD_OP_DRAIN_DCT = 0x712,
124 MLX5_CMD_OP_QUERY_DCT = 0x713,
125 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
7486216b
SM		 126 MLX5_CMD_OP_CREATE_XRQ = 0x717,
127 MLX5_CMD_OP_DESTROY_XRQ = 0x718,
128 MLX5_CMD_OP_QUERY_XRQ = 0x719,
129 MLX5_CMD_OP_ARM_XRQ = 0x71a,
d29b796a
EC		 130 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
131 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
132 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
133 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
134 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
135 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
e281682b 136 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
d29b796a 137 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
e281682b
SM		 138 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
139 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
140 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
141 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
d29b796a
EC		 142 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
143 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
144 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
145 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
7486216b
SM		 146 MLX5_CMD_OP_SET_RATE_LIMIT = 0x780,
147 MLX5_CMD_OP_QUERY_RATE_LIMIT = 0x781,
d29b796a
EC		 148 MLX5_CMD_OP_ALLOC_PD = 0x800,
149 MLX5_CMD_OP_DEALLOC_PD = 0x801,
150 MLX5_CMD_OP_ALLOC_UAR = 0x802,
151 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
152 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
153 MLX5_CMD_OP_ACCESS_REG = 0x805,
154 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
20bb566b 155 MLX5_CMD_OP_DETACH_FROM_MCG = 0x807,
d29b796a
EC		 156 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
157 MLX5_CMD_OP_MAD_IFC = 0x50d,
158 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
159 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
160 MLX5_CMD_OP_NOP = 0x80d,
161 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
162 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
e281682b
SM		 163 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
164 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
165 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
166 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
167 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
168 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
169 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
170 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
171 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
172 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
173 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
174 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
928cfe87
TT		 175 MLX5_CMD_OP_SET_WOL_ROL = 0x830,
176 MLX5_CMD_OP_QUERY_WOL_ROL = 0x831,
d29b796a
EC		 177 MLX5_CMD_OP_CREATE_TIR = 0x900,
178 MLX5_CMD_OP_MODIFY_TIR = 0x901,
179 MLX5_CMD_OP_DESTROY_TIR = 0x902,
180 MLX5_CMD_OP_QUERY_TIR = 0x903,
d29b796a
EC		 181 MLX5_CMD_OP_CREATE_SQ = 0x904,
182 MLX5_CMD_OP_MODIFY_SQ = 0x905,
183 MLX5_CMD_OP_DESTROY_SQ = 0x906,
184 MLX5_CMD_OP_QUERY_SQ = 0x907,
185 MLX5_CMD_OP_CREATE_RQ = 0x908,
186 MLX5_CMD_OP_MODIFY_RQ = 0x909,
187 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
188 MLX5_CMD_OP_QUERY_RQ = 0x90b,
189 MLX5_CMD_OP_CREATE_RMP = 0x90c,
190 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
191 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
192 MLX5_CMD_OP_QUERY_RMP = 0x90f,
e281682b
SM		 193 MLX5_CMD_OP_CREATE_TIS = 0x912,
194 MLX5_CMD_OP_MODIFY_TIS = 0x913,
195 MLX5_CMD_OP_DESTROY_TIS = 0x914,
196 MLX5_CMD_OP_QUERY_TIS = 0x915,
197 MLX5_CMD_OP_CREATE_RQT = 0x916,
198 MLX5_CMD_OP_MODIFY_RQT = 0x917,
199 MLX5_CMD_OP_DESTROY_RQT = 0x918,
200 MLX5_CMD_OP_QUERY_RQT = 0x919,
2cc43b49 201 MLX5_CMD_OP_SET_FLOW_TABLE_ROOT = 0x92f,
e281682b
SM		 202 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
203 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
204 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
205 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
206 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
207 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
208 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
209 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
34a40e68 210 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938,
9dc0b289
AV		 211 MLX5_CMD_OP_ALLOC_FLOW_COUNTER = 0x939,
212 MLX5_CMD_OP_DEALLOC_FLOW_COUNTER = 0x93a,
213 MLX5_CMD_OP_QUERY_FLOW_COUNTER = 0x93b,
86d56a1a 214 MLX5_CMD_OP_MODIFY_FLOW_TABLE = 0x93c,
7adbde20
HHZ		 215 MLX5_CMD_OP_ALLOC_ENCAP_HEADER = 0x93d,
216 MLX5_CMD_OP_DEALLOC_ENCAP_HEADER = 0x93e,
86d56a1a 217 MLX5_CMD_OP_MAX
e281682b
SM		 218};
219
220struct mlx5_ifc_flow_table_fields_supported_bits {
221 u8 outer_dmac[0x1];
222 u8 outer_smac[0x1];
223 u8 outer_ether_type[0x1];
b4ff3a36 224 u8 reserved_at_3[0x1];
e281682b
SM		 225 u8 outer_first_prio[0x1];
226 u8 outer_first_cfi[0x1];
227 u8 outer_first_vid[0x1];
b4ff3a36 228 u8 reserved_at_7[0x1];
e281682b
SM		 229 u8 outer_second_prio[0x1];
230 u8 outer_second_cfi[0x1];
231 u8 outer_second_vid[0x1];
b4ff3a36 232 u8 reserved_at_b[0x1];
e281682b
SM		 233 u8 outer_sip[0x1];
234 u8 outer_dip[0x1];
235 u8 outer_frag[0x1];
236 u8 outer_ip_protocol[0x1];
237 u8 outer_ip_ecn[0x1];
238 u8 outer_ip_dscp[0x1];
239 u8 outer_udp_sport[0x1];
240 u8 outer_udp_dport[0x1];
241 u8 outer_tcp_sport[0x1];
242 u8 outer_tcp_dport[0x1];
243 u8 outer_tcp_flags[0x1];
244 u8 outer_gre_protocol[0x1];
245 u8 outer_gre_key[0x1];
246 u8 outer_vxlan_vni[0x1];
b4ff3a36 247 u8 reserved_at_1a[0x5];
e281682b
SM		 248 u8 source_eswitch_port[0x1];
249
250 u8 inner_dmac[0x1];
251 u8 inner_smac[0x1];
252 u8 inner_ether_type[0x1];
b4ff3a36 253 u8 reserved_at_23[0x1];
e281682b
SM		 254 u8 inner_first_prio[0x1];
255 u8 inner_first_cfi[0x1];
256 u8 inner_first_vid[0x1];
b4ff3a36 257 u8 reserved_at_27[0x1];
e281682b
SM		 258 u8 inner_second_prio[0x1];
259 u8 inner_second_cfi[0x1];
260 u8 inner_second_vid[0x1];
b4ff3a36 261 u8 reserved_at_2b[0x1];
e281682b
SM		 262 u8 inner_sip[0x1];
263 u8 inner_dip[0x1];
264 u8 inner_frag[0x1];
265 u8 inner_ip_protocol[0x1];
266 u8 inner_ip_ecn[0x1];
267 u8 inner_ip_dscp[0x1];
268 u8 inner_udp_sport[0x1];
269 u8 inner_udp_dport[0x1];
270 u8 inner_tcp_sport[0x1];
271 u8 inner_tcp_dport[0x1];
272 u8 inner_tcp_flags[0x1];
b4ff3a36 273 u8 reserved_at_37[0x9];
e281682b 274
b4ff3a36 275 u8 reserved_at_40[0x40];
e281682b
SM		 276};
277
278struct mlx5_ifc_flow_table_prop_layout_bits {
279 u8 ft_support[0x1];
9dc0b289
AV		 280 u8 reserved_at_1[0x1];
281 u8 flow_counter[0x1];
26a81453 282 u8 flow_modify_en[0x1];
2cc43b49 283 u8 modify_root[0x1];
34a40e68
MG		 284 u8 identified_miss_table_mode[0x1];
285 u8 flow_table_modify[0x1];
7adbde20
HHZ		 286 u8 encap[0x1];
287 u8 decap[0x1];
288 u8 reserved_at_9[0x17];
e281682b 289
b4ff3a36 290 u8 reserved_at_20[0x2];
e281682b 291 u8 log_max_ft_size[0x6];
b4ff3a36 292 u8 reserved_at_28[0x10];
e281682b
SM		 293 u8 max_ft_level[0x8];
294
b4ff3a36 295 u8 reserved_at_40[0x20];
e281682b 296
b4ff3a36 297 u8 reserved_at_60[0x18];
e281682b
SM		 298 u8 log_max_ft_num[0x8];
299
b4ff3a36 300 u8 reserved_at_80[0x18];
e281682b
SM		 301 u8 log_max_destination[0x8];
302
b4ff3a36 303 u8 reserved_at_a0[0x18];
e281682b
SM		 304 u8 log_max_flow[0x8];
305
b4ff3a36 306 u8 reserved_at_c0[0x40];
e281682b
SM		 307
308 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
309
310 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
311};
312
313struct mlx5_ifc_odp_per_transport_service_cap_bits {
314 u8 send[0x1];
315 u8 receive[0x1];
316 u8 write[0x1];
317 u8 read[0x1];
b4ff3a36 318 u8 reserved_at_4[0x1];
e281682b 319 u8 srq_receive[0x1];
b4ff3a36 320 u8 reserved_at_6[0x1a];
e281682b
SM		 321};
322
b4d1f032 323struct mlx5_ifc_ipv4_layout_bits {
b4ff3a36 324 u8 reserved_at_0[0x60];
b4d1f032
MG		 325
326 u8 ipv4[0x20];
327};
328
329struct mlx5_ifc_ipv6_layout_bits {
330 u8 ipv6[16][0x8];
331};
332
333union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
334 struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
335 struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
b4ff3a36 336 u8 reserved_at_0[0x80];
b4d1f032
MG		 337};
338
e281682b
SM		 339struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
340 u8 smac_47_16[0x20];
341
342 u8 smac_15_0[0x10];
343 u8 ethertype[0x10];
344
345 u8 dmac_47_16[0x20];
346
347 u8 dmac_15_0[0x10];
348 u8 first_prio[0x3];
349 u8 first_cfi[0x1];
350 u8 first_vid[0xc];
351
352 u8 ip_protocol[0x8];
353 u8 ip_dscp[0x6];
354 u8 ip_ecn[0x2];
355 u8 vlan_tag[0x1];
b4ff3a36 356 u8 reserved_at_91[0x1];
e281682b 357 u8 frag[0x1];
b4ff3a36 358 u8 reserved_at_93[0x4];
e281682b
SM		 359 u8 tcp_flags[0x9];
360
361 u8 tcp_sport[0x10];
362 u8 tcp_dport[0x10];
363
b4ff3a36 364 u8 reserved_at_c0[0x20];
e281682b
SM		 365
366 u8 udp_sport[0x10];
367 u8 udp_dport[0x10];
368
b4d1f032 369 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits src_ipv4_src_ipv6;
e281682b 370
b4d1f032 371 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits dst_ipv4_dst_ipv6;
e281682b
SM		 372};
373
374struct mlx5_ifc_fte_match_set_misc_bits {
7486216b
SM		 375 u8 reserved_at_0[0x8];
376 u8 source_sqn[0x18];
e281682b 377
b4ff3a36 378 u8 reserved_at_20[0x10];
e281682b
SM		 379 u8 source_port[0x10];
380
381 u8 outer_second_prio[0x3];
382 u8 outer_second_cfi[0x1];
383 u8 outer_second_vid[0xc];
384 u8 inner_second_prio[0x3];
385 u8 inner_second_cfi[0x1];
386 u8 inner_second_vid[0xc];
387
388 u8 outer_second_vlan_tag[0x1];
389 u8 inner_second_vlan_tag[0x1];
b4ff3a36 390 u8 reserved_at_62[0xe];
e281682b
SM		 391 u8 gre_protocol[0x10];
392
393 u8 gre_key_h[0x18];
394 u8 gre_key_l[0x8];
395
396 u8 vxlan_vni[0x18];
b4ff3a36 397 u8 reserved_at_b8[0x8];
e281682b 398
b4ff3a36 399 u8 reserved_at_c0[0x20];
e281682b 400
b4ff3a36 401 u8 reserved_at_e0[0xc];
e281682b
SM		 402 u8 outer_ipv6_flow_label[0x14];
403
b4ff3a36 404 u8 reserved_at_100[0xc];
e281682b
SM		 405 u8 inner_ipv6_flow_label[0x14];
406
b4ff3a36 407 u8 reserved_at_120[0xe0];
e281682b
SM		 408};
409
410struct mlx5_ifc_cmd_pas_bits {
411 u8 pa_h[0x20];
412
413 u8 pa_l[0x14];
b4ff3a36 414 u8 reserved_at_34[0xc];
e281682b
SM		 415};
416
417struct mlx5_ifc_uint64_bits {
418 u8 hi[0x20];
419
420 u8 lo[0x20];
421};
422
423enum {
424 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
425 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
426 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
427 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
428 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
429 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
430 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
431 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
432 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
433 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
434};
435
436struct mlx5_ifc_ads_bits {
437 u8 fl[0x1];
438 u8 free_ar[0x1];
b4ff3a36 439 u8 reserved_at_2[0xe];
e281682b
SM		 440 u8 pkey_index[0x10];
441
b4ff3a36 442 u8 reserved_at_20[0x8];
e281682b
SM		 443 u8 grh[0x1];
444 u8 mlid[0x7];
445 u8 rlid[0x10];
446
447 u8 ack_timeout[0x5];
b4ff3a36 448 u8 reserved_at_45[0x3];
e281682b 449 u8 src_addr_index[0x8];
b4ff3a36 450 u8 reserved_at_50[0x4];
e281682b
SM		 451 u8 stat_rate[0x4];
452 u8 hop_limit[0x8];
453
b4ff3a36 454 u8 reserved_at_60[0x4];
e281682b
SM		 455 u8 tclass[0x8];
456 u8 flow_label[0x14];
457
458 u8 rgid_rip[16][0x8];
459
b4ff3a36 460 u8 reserved_at_100[0x4];
e281682b
SM		 461 u8 f_dscp[0x1];
462 u8 f_ecn[0x1];
b4ff3a36 463 u8 reserved_at_106[0x1];
e281682b
SM		 464 u8 f_eth_prio[0x1];
465 u8 ecn[0x2];
466 u8 dscp[0x6];
467 u8 udp_sport[0x10];
468
469 u8 dei_cfi[0x1];
470 u8 eth_prio[0x3];
471 u8 sl[0x4];
472 u8 port[0x8];
473 u8 rmac_47_32[0x10];
474
475 u8 rmac_31_0[0x20];
476};
477
478struct mlx5_ifc_flow_table_nic_cap_bits {
b3638e1a
MG		 479 u8 nic_rx_multi_path_tirs[0x1];
480 u8 reserved_at_1[0x1ff];
e281682b
SM		 481
482 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
483
b4ff3a36 484 u8 reserved_at_400[0x200];
e281682b
SM		 485
486 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
487
488 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
489
b4ff3a36 490 u8 reserved_at_a00[0x200];
e281682b
SM		 491
492 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
493
b4ff3a36 494 u8 reserved_at_e00[0x7200];
e281682b
SM		 495};
496
495716b1 497struct mlx5_ifc_flow_table_eswitch_cap_bits {
b4ff3a36 498 u8 reserved_at_0[0x200];
495716b1
SM		 499
500 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_esw_fdb;
501
502 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_ingress;
503
504 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_esw_acl_egress;
505
b4ff3a36 506 u8 reserved_at_800[0x7800];
495716b1
SM		 507};
508
d6666753
SM		 509struct mlx5_ifc_e_switch_cap_bits {
510 u8 vport_svlan_strip[0x1];
511 u8 vport_cvlan_strip[0x1];
512 u8 vport_svlan_insert[0x1];
513 u8 vport_cvlan_insert_if_not_exist[0x1];
514 u8 vport_cvlan_insert_overwrite[0x1];
23898c76
NO		 515 u8 reserved_at_5[0x19];
516 u8 nic_vport_node_guid_modify[0x1];
517 u8 nic_vport_port_guid_modify[0x1];
d6666753 518
7adbde20
HHZ		 519 u8 vxlan_encap_decap[0x1];
520 u8 nvgre_encap_decap[0x1];
521 u8 reserved_at_22[0x9];
522 u8 log_max_encap_headers[0x5];
523 u8 reserved_2b[0x6];
524 u8 max_encap_header_size[0xa];
525
526 u8 reserved_40[0x7c0];
527
d6666753
SM		 528};
529
7486216b
SM		 530struct mlx5_ifc_qos_cap_bits {
531 u8 packet_pacing[0x1];
532 u8 reserved_0[0x1f];
533 u8 reserved_1[0x20];
534 u8 packet_pacing_max_rate[0x20];
535 u8 packet_pacing_min_rate[0x20];
536 u8 reserved_2[0x10];
537 u8 packet_pacing_rate_table_size[0x10];
538 u8 reserved_3[0x760];
539};
540
e281682b
SM		 541struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
542 u8 csum_cap[0x1];
543 u8 vlan_cap[0x1];
544 u8 lro_cap[0x1];
545 u8 lro_psh_flag[0x1];
546 u8 lro_time_stamp[0x1];
b4ff3a36 547 u8 reserved_at_5[0x3];
66189961 548 u8 self_lb_en_modifiable[0x1];
b4ff3a36 549 u8 reserved_at_9[0x2];
e281682b 550 u8 max_lso_cap[0x5];
cff92d7c
HHZ		 551 u8 reserved_at_10[0x2];
552 u8 wqe_inline_mode[0x2];
e281682b 553 u8 rss_ind_tbl_cap[0x4];
7d5e1423
SM		 554 u8 reg_umr_sq[0x1];
555 u8 scatter_fcs[0x1];
556 u8 reserved_at_1a[0x1];
e281682b 557 u8 tunnel_lso_const_out_ip_id[0x1];
b4ff3a36 558 u8 reserved_at_1c[0x2];
e281682b
SM		 559 u8 tunnel_statless_gre[0x1];
560 u8 tunnel_stateless_vxlan[0x1];
561
b4ff3a36 562 u8 reserved_at_20[0x20];
e281682b 563
b4ff3a36 564 u8 reserved_at_40[0x10];
e281682b
SM		 565 u8 lro_min_mss_size[0x10];
566
b4ff3a36 567 u8 reserved_at_60[0x120];
e281682b
SM		 568
569 u8 lro_timer_supported_periods[4][0x20];
570
b4ff3a36 571 u8 reserved_at_200[0x600];
e281682b
SM		 572};
573
574struct mlx5_ifc_roce_cap_bits {
575 u8 roce_apm[0x1];
b4ff3a36 576 u8 reserved_at_1[0x1f];
e281682b 577
b4ff3a36 578 u8 reserved_at_20[0x60];
e281682b 579
b4ff3a36 580 u8 reserved_at_80[0xc];
e281682b 581 u8 l3_type[0x4];
b4ff3a36 582 u8 reserved_at_90[0x8];
e281682b
SM		 583 u8 roce_version[0x8];
584
b4ff3a36 585 u8 reserved_at_a0[0x10];
e281682b
SM		 586 u8 r_roce_dest_udp_port[0x10];
587
588 u8 r_roce_max_src_udp_port[0x10];
589 u8 r_roce_min_src_udp_port[0x10];
590
b4ff3a36 591 u8 reserved_at_e0[0x10];
e281682b
SM		 592 u8 roce_address_table_size[0x10];
593
b4ff3a36 594 u8 reserved_at_100[0x700];
e281682b
SM		 595};
596
597enum {
598 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
599 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
600 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
601 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
602 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
603 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
604 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
605 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
606 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
607};
608
609enum {
610 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
611 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
612 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
613 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
614 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
615 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
616 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
617 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
618 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
619};
620
621struct mlx5_ifc_atomic_caps_bits {
b4ff3a36 622 u8 reserved_at_0[0x40];
e281682b 623
f91e6d89 624 u8 atomic_req_8B_endianess_mode[0x2];
b4ff3a36 625 u8 reserved_at_42[0x4];
f91e6d89 626 u8 supported_atomic_req_8B_endianess_mode_1[0x1];
e281682b 627
b4ff3a36 628 u8 reserved_at_47[0x19];
e281682b 629
b4ff3a36 630 u8 reserved_at_60[0x20];
e281682b 631
b4ff3a36 632 u8 reserved_at_80[0x10];
f91e6d89 633 u8 atomic_operations[0x10];
e281682b 634
b4ff3a36 635 u8 reserved_at_a0[0x10];
f91e6d89
EBE		 636 u8 atomic_size_qp[0x10];
637
b4ff3a36 638 u8 reserved_at_c0[0x10];
e281682b
SM		 639 u8 atomic_size_dc[0x10];
640
b4ff3a36 641 u8 reserved_at_e0[0x720];
e281682b
SM		 642};
643
644struct mlx5_ifc_odp_cap_bits {
b4ff3a36 645 u8 reserved_at_0[0x40];
e281682b
SM		 646
647 u8 sig[0x1];
b4ff3a36 648 u8 reserved_at_41[0x1f];
e281682b 649
b4ff3a36 650 u8 reserved_at_60[0x20];
e281682b
SM		 651
652 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
653
654 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
655
656 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
657
b4ff3a36 658 u8 reserved_at_e0[0x720];
e281682b
SM		 659};
660
3f0393a5
SG		 661struct mlx5_ifc_calc_op {
662 u8 reserved_at_0[0x10];
663 u8 reserved_at_10[0x9];
664 u8 op_swap_endianness[0x1];
665 u8 op_min[0x1];
666 u8 op_xor[0x1];
667 u8 op_or[0x1];
668 u8 op_and[0x1];
669 u8 op_max[0x1];
670 u8 op_add[0x1];
671};
672
673struct mlx5_ifc_vector_calc_cap_bits {
674 u8 calc_matrix[0x1];
675 u8 reserved_at_1[0x1f];
676 u8 reserved_at_20[0x8];
677 u8 max_vec_count[0x8];
678 u8 reserved_at_30[0xd];
679 u8 max_chunk_size[0x3];
680 struct mlx5_ifc_calc_op calc0;
681 struct mlx5_ifc_calc_op calc1;
682 struct mlx5_ifc_calc_op calc2;
683 struct mlx5_ifc_calc_op calc3;
684
685 u8 reserved_at_e0[0x720];
686};
687
e281682b
SM		 688enum {
689 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
690 MLX5_WQ_TYPE_CYCLIC = 0x1,
7d5e1423 691 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ = 0x2,
e281682b
SM		 692};
693
694enum {
695 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
696 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
697};
698
699enum {
700 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
701 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
702 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
703 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
704 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
705};
706
707enum {
708 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
709 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
710 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
711 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
712 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
713 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
714};
715
716enum {
717 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
718 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
719};
720
721enum {
722 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
723 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
724 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
725};
726
727enum {
728 MLX5_CAP_PORT_TYPE_IB = 0x0,
729 MLX5_CAP_PORT_TYPE_ETH = 0x1,
d29b796a
EC		 730};
731
b775516b 732struct mlx5_ifc_cmd_hca_cap_bits {
b4ff3a36 733 u8 reserved_at_0[0x80];
b775516b
EC		 734
735 u8 log_max_srq_sz[0x8];
736 u8 log_max_qp_sz[0x8];
b4ff3a36 737 u8 reserved_at_90[0xb];
b775516b
EC		 738 u8 log_max_qp[0x5];
739
b4ff3a36 740 u8 reserved_at_a0[0xb];
e281682b 741 u8 log_max_srq[0x5];
b4ff3a36 742 u8 reserved_at_b0[0x10];
b775516b 743
b4ff3a36 744 u8 reserved_at_c0[0x8];
b775516b 745 u8 log_max_cq_sz[0x8];
b4ff3a36 746 u8 reserved_at_d0[0xb];
b775516b
EC		 747 u8 log_max_cq[0x5];
748
749 u8 log_max_eq_sz[0x8];
b4ff3a36 750 u8 reserved_at_e8[0x2];
b775516b 751 u8 log_max_mkey[0x6];
b4ff3a36 752 u8 reserved_at_f0[0xc];
b775516b
EC		 753 u8 log_max_eq[0x4];
754
755 u8 max_indirection[0x8];
b4ff3a36 756 u8 reserved_at_108[0x1];
b775516b 757 u8 log_max_mrw_sz[0x7];
b4ff3a36 758 u8 reserved_at_110[0x2];
b775516b 759 u8 log_max_bsf_list_size[0x6];
b4ff3a36 760 u8 reserved_at_118[0x2];
b775516b
EC		 761 u8 log_max_klm_list_size[0x6];
762
b4ff3a36 763 u8 reserved_at_120[0xa];
b775516b 764 u8 log_max_ra_req_dc[0x6];
b4ff3a36 765 u8 reserved_at_130[0xa];
b775516b
EC		 766 u8 log_max_ra_res_dc[0x6];
767
b4ff3a36 768 u8 reserved_at_140[0xa];
b775516b 769 u8 log_max_ra_req_qp[0x6];
b4ff3a36 770 u8 reserved_at_150[0xa];
b775516b
EC		 771 u8 log_max_ra_res_qp[0x6];
772
773 u8 pad_cap[0x1];
774 u8 cc_query_allowed[0x1];
775 u8 cc_modify_allowed[0x1];
b4ff3a36 776 u8 reserved_at_163[0xd];
e281682b 777 u8 gid_table_size[0x10];
b775516b 778
e281682b
SM		 779 u8 out_of_seq_cnt[0x1];
780 u8 vport_counters[0x1];
7486216b 781 u8 retransmission_q_counters[0x1];
83b502a1
AV		 782 u8 reserved_at_183[0x1];
783 u8 modify_rq_counter_set_id[0x1];
784 u8 reserved_at_185[0x1];
b775516b
EC		 785 u8 max_qp_cnt[0xa];
786 u8 pkey_table_size[0x10];
787
e281682b
SM		 788 u8 vport_group_manager[0x1];
789 u8 vhca_group_manager[0x1];
790 u8 ib_virt[0x1];
791 u8 eth_virt[0x1];
b4ff3a36 792 u8 reserved_at_1a4[0x1];
e281682b
SM		 793 u8 ets[0x1];
794 u8 nic_flow_table[0x1];
54f0a411 795 u8 eswitch_flow_table[0x1];
e1c9c62b
TT		 796 u8 early_vf_enable[0x1];
797 u8 reserved_at_1a9[0x2];
b775516b 798 u8 local_ca_ack_delay[0x5];
7d5e1423
SM		 799 u8 reserved_at_1af[0x2];
800 u8 ports_check[0x1];
801 u8 reserved_at_1b2[0x1];
802 u8 disable_link_up[0x1];
803 u8 beacon_led[0x1];
e281682b 804 u8 port_type[0x2];
b775516b
EC		 805 u8 num_ports[0x8];
806
e1c9c62b 807 u8 reserved_at_1c0[0x3];
b775516b 808 u8 log_max_msg[0x5];
e1c9c62b 809 u8 reserved_at_1c8[0x4];
4f3961ee 810 u8 max_tc[0x4];
7486216b
SM		 811 u8 reserved_at_1d0[0x1];
812 u8 dcbx[0x1];
813 u8 reserved_at_1d2[0x4];
928cfe87
TT		 814 u8 rol_s[0x1];
815 u8 rol_g[0x1];
e1c9c62b 816 u8 reserved_at_1d8[0x1];
928cfe87
TT		 817 u8 wol_s[0x1];
818 u8 wol_g[0x1];
819 u8 wol_a[0x1];
820 u8 wol_b[0x1];
821 u8 wol_m[0x1];
822 u8 wol_u[0x1];
823 u8 wol_p[0x1];
b775516b
EC		 824
825 u8 stat_rate_support[0x10];
e1c9c62b 826 u8 reserved_at_1f0[0xc];
e281682b 827 u8 cqe_version[0x4];
b775516b 828
e281682b 829 u8 compact_address_vector[0x1];
7d5e1423
SM		 830 u8 striding_rq[0x1];
831 u8 reserved_at_201[0x2];
1015c2e8 832 u8 ipoib_basic_offloads[0x1];
e1c9c62b 833 u8 reserved_at_205[0xa];
e281682b 834 u8 drain_sigerr[0x1];
b775516b
EC		 835 u8 cmdif_checksum[0x2];
836 u8 sigerr_cqe[0x1];
e1c9c62b 837 u8 reserved_at_213[0x1];
b775516b
EC		 838 u8 wq_signature[0x1];
839 u8 sctr_data_cqe[0x1];
e1c9c62b 840 u8 reserved_at_216[0x1];
b775516b
EC		 841 u8 sho[0x1];
842 u8 tph[0x1];
843 u8 rf[0x1];
e281682b 844 u8 dct[0x1];
7486216b 845 u8 qos[0x1];
e281682b 846 u8 eth_net_offloads[0x1];
b775516b
EC		 847 u8 roce[0x1];
848 u8 atomic[0x1];
e1c9c62b 849 u8 reserved_at_21f[0x1];
b775516b
EC		 850
851 u8 cq_oi[0x1];
852 u8 cq_resize[0x1];
853 u8 cq_moderation[0x1];
e1c9c62b 854 u8 reserved_at_223[0x3];
e281682b 855 u8 cq_eq_remap[0x1];
b775516b
EC		 856 u8 pg[0x1];
857 u8 block_lb_mc[0x1];
e1c9c62b 858 u8 reserved_at_229[0x1];
e281682b 859 u8 scqe_break_moderation[0x1];
7d5e1423 860 u8 cq_period_start_from_cqe[0x1];
b775516b 861 u8 cd[0x1];
e1c9c62b 862 u8 reserved_at_22d[0x1];
b775516b 863 u8 apm[0x1];
3f0393a5 864 u8 vector_calc[0x1];
7d5e1423 865 u8 umr_ptr_rlky[0x1];
d2370e0a 866 u8 imaicl[0x1];
e1c9c62b 867 u8 reserved_at_232[0x4];
b775516b
EC		 868 u8 qkv[0x1];
869 u8 pkv[0x1];
b11a4f9c
HE		 870 u8 set_deth_sqpn[0x1];
871 u8 reserved_at_239[0x3];
b775516b
EC		 872 u8 xrc[0x1];
873 u8 ud[0x1];
874 u8 uc[0x1];
875 u8 rc[0x1];
876
e1c9c62b 877 u8 reserved_at_240[0xa];
b775516b 878 u8 uar_sz[0x6];
e1c9c62b 879 u8 reserved_at_250[0x8];
b775516b
EC		 880 u8 log_pg_sz[0x8];
881
882 u8 bf[0x1];
e1c9c62b 883 u8 reserved_at_261[0x1];
e281682b 884 u8 pad_tx_eth_packet[0x1];
e1c9c62b 885 u8 reserved_at_263[0x8];
b775516b 886 u8 log_bf_reg_size[0x5];
e1c9c62b 887 u8 reserved_at_270[0x10];
b775516b 888
e1c9c62b 889 u8 reserved_at_280[0x10];
b775516b
EC		 890 u8 max_wqe_sz_sq[0x10];
891
e1c9c62b 892 u8 reserved_at_2a0[0x10];
b775516b
EC		 893 u8 max_wqe_sz_rq[0x10];
894
e1c9c62b 895 u8 reserved_at_2c0[0x10];
b775516b
EC		 896 u8 max_wqe_sz_sq_dc[0x10];
897
e1c9c62b 898 u8 reserved_at_2e0[0x7];
b775516b
EC		 899 u8 max_qp_mcg[0x19];
900
e1c9c62b 901 u8 reserved_at_300[0x18];
b775516b
EC		 902 u8 log_max_mcg[0x8];
903
e1c9c62b 904 u8 reserved_at_320[0x3];
e281682b 905 u8 log_max_transport_domain[0x5];
e1c9c62b 906 u8 reserved_at_328[0x3];
b775516b 907 u8 log_max_pd[0x5];
e1c9c62b 908 u8 reserved_at_330[0xb];
b775516b
EC		 909 u8 log_max_xrcd[0x5];
910
a351a1b0
AV		 911 u8 reserved_at_340[0x8];
912 u8 log_max_flow_counter_bulk[0x8];
913 u8 max_flow_counter[0x10];
914
b775516b 915
e1c9c62b 916 u8 reserved_at_360[0x3];
b775516b 917 u8 log_max_rq[0x5];
e1c9c62b 918 u8 reserved_at_368[0x3];
b775516b 919 u8 log_max_sq[0x5];
e1c9c62b 920 u8 reserved_at_370[0x3];
b775516b 921 u8 log_max_tir[0x5];
e1c9c62b 922 u8 reserved_at_378[0x3];
b775516b
EC		 923 u8 log_max_tis[0x5];
924
e281682b 925 u8 basic_cyclic_rcv_wqe[0x1];
e1c9c62b 926 u8 reserved_at_381[0x2];
e281682b 927 u8 log_max_rmp[0x5];
e1c9c62b 928 u8 reserved_at_388[0x3];
e281682b 929 u8 log_max_rqt[0x5];
e1c9c62b 930 u8 reserved_at_390[0x3];
e281682b 931 u8 log_max_rqt_size[0x5];
e1c9c62b 932 u8 reserved_at_398[0x3];
b775516b
EC		 933 u8 log_max_tis_per_sq[0x5];
934
e1c9c62b 935 u8 reserved_at_3a0[0x3];
e281682b 936 u8 log_max_stride_sz_rq[0x5];
e1c9c62b 937 u8 reserved_at_3a8[0x3];
e281682b 938 u8 log_min_stride_sz_rq[0x5];
e1c9c62b 939 u8 reserved_at_3b0[0x3];
e281682b 940 u8 log_max_stride_sz_sq[0x5];
e1c9c62b 941 u8 reserved_at_3b8[0x3];
e281682b
SM		 942 u8 log_min_stride_sz_sq[0x5];
943
e1c9c62b 944 u8 reserved_at_3c0[0x1b];
e281682b
SM		 945 u8 log_max_wq_sz[0x5];
946
54f0a411 947 u8 nic_vport_change_event[0x1];
e1c9c62b 948 u8 reserved_at_3e1[0xa];
54f0a411 949 u8 log_max_vlan_list[0x5];
e1c9c62b 950 u8 reserved_at_3f0[0x3];
54f0a411 951 u8 log_max_current_mc_list[0x5];
e1c9c62b 952 u8 reserved_at_3f8[0x3];
54f0a411
SM		 953 u8 log_max_current_uc_list[0x5];
954
e1c9c62b 955 u8 reserved_at_400[0x80];
54f0a411 956
e1c9c62b 957 u8 reserved_at_480[0x3];
e281682b 958 u8 log_max_l2_table[0x5];
e1c9c62b 959 u8 reserved_at_488[0x8];
b775516b
EC		 960 u8 log_uar_page_sz[0x10];
961
e1c9c62b 962 u8 reserved_at_4a0[0x20];
048ccca8 963 u8 device_frequency_mhz[0x20];
b0844444 964 u8 device_frequency_khz[0x20];
e1c9c62b
TT		 965
966 u8 reserved_at_500[0x80];
967
968 u8 reserved_at_580[0x3f];
7d5e1423 969 u8 cqe_compression[0x1];
b775516b 970
7d5e1423
SM		 971 u8 cqe_compression_timeout[0x10];
972 u8 cqe_compression_max_num[0x10];
b775516b 973
7486216b
SM		 974 u8 reserved_at_5e0[0x10];
975 u8 tag_matching[0x1];
976 u8 rndv_offload_rc[0x1];
977 u8 rndv_offload_dc[0x1];
978 u8 log_tag_matching_list_sz[0x5];
979 u8 reserved_at_5e8[0x3];
980 u8 log_max_xrq[0x5];
981
982 u8 reserved_at_5f0[0x200];
b775516b
EC		 983};
984
81848731
SM		 985enum mlx5_flow_destination_type {
986 MLX5_FLOW_DESTINATION_TYPE_VPORT = 0x0,
987 MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE = 0x1,
988 MLX5_FLOW_DESTINATION_TYPE_TIR = 0x2,
bd5251db
AV		 989
990 MLX5_FLOW_DESTINATION_TYPE_COUNTER = 0x100,
e281682b 991};
b775516b 992
e281682b
SM		 993struct mlx5_ifc_dest_format_struct_bits {
994 u8 destination_type[0x8];
995 u8 destination_id[0x18];
b775516b 996
b4ff3a36 997 u8 reserved_at_20[0x20];
e281682b
SM		 998};
999
9dc0b289 1000struct mlx5_ifc_flow_counter_list_bits {
a351a1b0
AV		 1001 u8 clear[0x1];
1002 u8 num_of_counters[0xf];
9dc0b289
AV		 1003 u8 flow_counter_id[0x10];
1004
1005 u8 reserved_at_20[0x20];
1006};
1007
1008union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits {
1009 struct mlx5_ifc_dest_format_struct_bits dest_format_struct;
1010 struct mlx5_ifc_flow_counter_list_bits flow_counter_list;
1011 u8 reserved_at_0[0x40];
1012};
1013
e281682b
SM		 1014struct mlx5_ifc_fte_match_param_bits {
1015 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
1016
1017 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
1018
1019 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
b775516b 1020
b4ff3a36 1021 u8 reserved_at_600[0xa00];
b775516b
EC		 1022};
1023
e281682b
SM		 1024enum {
1025 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
1026 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
1027 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
1028 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
1029 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
1030};
b775516b 1031
e281682b
SM		 1032struct mlx5_ifc_rx_hash_field_select_bits {
1033 u8 l3_prot_type[0x1];
1034 u8 l4_prot_type[0x1];
1035 u8 selected_fields[0x1e];
1036};
b775516b 1037
e281682b
SM		 1038enum {
1039 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
1040 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
b775516b
EC		 1041};
1042
e281682b
SM		 1043enum {
1044 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
1045 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
1046};
1047
1048struct mlx5_ifc_wq_bits {
1049 u8 wq_type[0x4];
1050 u8 wq_signature[0x1];
1051 u8 end_padding_mode[0x2];
1052 u8 cd_slave[0x1];
b4ff3a36 1053 u8 reserved_at_8[0x18];
b775516b 1054
e281682b
SM		 1055 u8 hds_skip_first_sge[0x1];
1056 u8 log2_hds_buf_size[0x3];
b4ff3a36 1057 u8 reserved_at_24[0x7];
e281682b
SM		 1058 u8 page_offset[0x5];
1059 u8 lwm[0x10];
b775516b 1060
b4ff3a36 1061 u8 reserved_at_40[0x8];
e281682b
SM		 1062 u8 pd[0x18];
1063
b4ff3a36 1064 u8 reserved_at_60[0x8];
e281682b
SM		 1065 u8 uar_page[0x18];
1066
1067 u8 dbr_addr[0x40];
1068
1069 u8 hw_counter[0x20];
1070
1071 u8 sw_counter[0x20];
1072
b4ff3a36 1073 u8 reserved_at_100[0xc];
e281682b 1074 u8 log_wq_stride[0x4];
b4ff3a36 1075 u8 reserved_at_110[0x3];
e281682b 1076 u8 log_wq_pg_sz[0x5];
b4ff3a36 1077 u8 reserved_at_118[0x3];
e281682b
SM		 1078 u8 log_wq_sz[0x5];
1079
7d5e1423
SM		 1080 u8 reserved_at_120[0x15];
1081 u8 log_wqe_num_of_strides[0x3];
1082 u8 two_byte_shift_en[0x1];
1083 u8 reserved_at_139[0x4];
1084 u8 log_wqe_stride_size[0x3];
1085
1086 u8 reserved_at_140[0x4c0];
b775516b 1087
e281682b 1088 struct mlx5_ifc_cmd_pas_bits pas[0];
b775516b
EC		 1089};
1090
e281682b 1091struct mlx5_ifc_rq_num_bits {
b4ff3a36 1092 u8 reserved_at_0[0x8];
e281682b
SM		 1093 u8 rq_num[0x18];
1094};
b775516b 1095
e281682b 1096struct mlx5_ifc_mac_address_layout_bits {
b4ff3a36 1097 u8 reserved_at_0[0x10];
e281682b 1098 u8 mac_addr_47_32[0x10];
b775516b 1099
e281682b
SM		 1100 u8 mac_addr_31_0[0x20];
1101};
1102
c0046cf7 1103struct mlx5_ifc_vlan_layout_bits {
b4ff3a36 1104 u8 reserved_at_0[0x14];
c0046cf7
SM		 1105 u8 vlan[0x0c];
1106
b4ff3a36 1107 u8 reserved_at_20[0x20];
c0046cf7
SM		 1108};
1109
e281682b 1110struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
b4ff3a36 1111 u8 reserved_at_0[0xa0];
e281682b
SM		 1112
1113 u8 min_time_between_cnps[0x20];
1114
b4ff3a36 1115 u8 reserved_at_c0[0x12];
e281682b 1116 u8 cnp_dscp[0x6];
b4ff3a36 1117 u8 reserved_at_d8[0x5];
e281682b
SM		 1118 u8 cnp_802p_prio[0x3];
1119
b4ff3a36 1120 u8 reserved_at_e0[0x720];
e281682b
SM		 1121};
1122
1123struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
b4ff3a36 1124 u8 reserved_at_0[0x60];
e281682b 1125
b4ff3a36 1126 u8 reserved_at_60[0x4];
e281682b 1127 u8 clamp_tgt_rate[0x1];
b4ff3a36 1128 u8 reserved_at_65[0x3];
e281682b 1129 u8 clamp_tgt_rate_after_time_inc[0x1];
b4ff3a36 1130 u8 reserved_at_69[0x17];
e281682b 1131
b4ff3a36 1132 u8 reserved_at_80[0x20];
e281682b
SM		 1133
1134 u8 rpg_time_reset[0x20];
1135
1136 u8 rpg_byte_reset[0x20];
1137
1138 u8 rpg_threshold[0x20];
1139
1140 u8 rpg_max_rate[0x20];
1141
1142 u8 rpg_ai_rate[0x20];
1143
1144 u8 rpg_hai_rate[0x20];
1145
1146 u8 rpg_gd[0x20];
1147
1148 u8 rpg_min_dec_fac[0x20];
1149
1150 u8 rpg_min_rate[0x20];
1151
b4ff3a36 1152 u8 reserved_at_1c0[0xe0];
e281682b
SM		 1153
1154 u8 rate_to_set_on_first_cnp[0x20];
1155
1156 u8 dce_tcp_g[0x20];
1157
1158 u8 dce_tcp_rtt[0x20];
1159
1160 u8 rate_reduce_monitor_period[0x20];
1161
b4ff3a36 1162 u8 reserved_at_320[0x20];
e281682b
SM		 1163
1164 u8 initial_alpha_value[0x20];
1165
b4ff3a36 1166 u8 reserved_at_360[0x4a0];
e281682b
SM		 1167};
1168
1169struct mlx5_ifc_cong_control_802_1qau_rp_bits {
b4ff3a36 1170 u8 reserved_at_0[0x80];
e281682b
SM		 1171
1172 u8 rppp_max_rps[0x20];
1173
1174 u8 rpg_time_reset[0x20];
1175
1176 u8 rpg_byte_reset[0x20];
1177
1178 u8 rpg_threshold[0x20];
1179
1180 u8 rpg_max_rate[0x20];
1181
1182 u8 rpg_ai_rate[0x20];
1183
1184 u8 rpg_hai_rate[0x20];
1185
1186 u8 rpg_gd[0x20];
1187
1188 u8 rpg_min_dec_fac[0x20];
1189
1190 u8 rpg_min_rate[0x20];
1191
b4ff3a36 1192 u8 reserved_at_1c0[0x640];
e281682b
SM		 1193};
1194
1195enum {
1196 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
1197 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
1198 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
1199};
1200
1201struct mlx5_ifc_resize_field_select_bits {
1202 u8 resize_field_select[0x20];
1203};
1204
1205enum {
1206 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
1207 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
1208 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1209 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1210};
1211
1212struct mlx5_ifc_modify_field_select_bits {
1213 u8 modify_field_select[0x20];
1214};
1215
1216struct mlx5_ifc_field_select_r_roce_np_bits {
1217 u8 field_select_r_roce_np[0x20];
1218};
1219
1220struct mlx5_ifc_field_select_r_roce_rp_bits {
1221 u8 field_select_r_roce_rp[0x20];
1222};
1223
1224enum {
1225 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1226 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1227 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1228 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1229 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1230 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1231 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1232 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1233 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1234 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1235};
1236
1237struct mlx5_ifc_field_select_802_1qau_rp_bits {
1238 u8 field_select_8021qaurp[0x20];
1239};
1240
1241struct mlx5_ifc_phys_layer_cntrs_bits {
1242 u8 time_since_last_clear_high[0x20];
1243
1244 u8 time_since_last_clear_low[0x20];
1245
1246 u8 symbol_errors_high[0x20];
1247
1248 u8 symbol_errors_low[0x20];
1249
1250 u8 sync_headers_errors_high[0x20];
1251
1252 u8 sync_headers_errors_low[0x20];
1253
1254 u8 edpl_bip_errors_lane0_high[0x20];
1255
1256 u8 edpl_bip_errors_lane0_low[0x20];
1257
1258 u8 edpl_bip_errors_lane1_high[0x20];
1259
1260 u8 edpl_bip_errors_lane1_low[0x20];
1261
1262 u8 edpl_bip_errors_lane2_high[0x20];
1263
1264 u8 edpl_bip_errors_lane2_low[0x20];
1265
1266 u8 edpl_bip_errors_lane3_high[0x20];
1267
1268 u8 edpl_bip_errors_lane3_low[0x20];
1269
1270 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1271
1272 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1273
1274 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1275
1276 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1277
1278 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1279
1280 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1281
1282 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1283
1284 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1285
1286 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1287
1288 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1289
1290 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1291
1292 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1293
1294 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1295
1296 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1297
1298 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1299
1300 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1301
1302 u8 rs_fec_corrected_blocks_high[0x20];
1303
1304 u8 rs_fec_corrected_blocks_low[0x20];
1305
1306 u8 rs_fec_uncorrectable_blocks_high[0x20];
1307
1308 u8 rs_fec_uncorrectable_blocks_low[0x20];
1309
1310 u8 rs_fec_no_errors_blocks_high[0x20];
1311
1312 u8 rs_fec_no_errors_blocks_low[0x20];
1313
1314 u8 rs_fec_single_error_blocks_high[0x20];
1315
1316 u8 rs_fec_single_error_blocks_low[0x20];
1317
1318 u8 rs_fec_corrected_symbols_total_high[0x20];
1319
1320 u8 rs_fec_corrected_symbols_total_low[0x20];
1321
1322 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1323
1324 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1325
1326 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1327
1328 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1329
1330 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1331
1332 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1333
1334 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1335
1336 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1337
1338 u8 link_down_events[0x20];
1339
1340 u8 successful_recovery_events[0x20];
1341
b4ff3a36 1342 u8 reserved_at_640[0x180];
e281682b
SM		 1343};
1344
1c64bf6f
MY		 1345struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits {
1346 u8 symbol_error_counter[0x10];
1347
1348 u8 link_error_recovery_counter[0x8];
1349
1350 u8 link_downed_counter[0x8];
1351
1352 u8 port_rcv_errors[0x10];
1353
1354 u8 port_rcv_remote_physical_errors[0x10];
1355
1356 u8 port_rcv_switch_relay_errors[0x10];
1357
1358 u8 port_xmit_discards[0x10];
1359
1360 u8 port_xmit_constraint_errors[0x8];
1361
1362 u8 port_rcv_constraint_errors[0x8];
1363
1364 u8 reserved_at_70[0x8];
1365
1366 u8 link_overrun_errors[0x8];
1367
1368 u8 reserved_at_80[0x10];
1369
1370 u8 vl_15_dropped[0x10];
1371
1372 u8 reserved_at_a0[0xa0];
1373};
1374
e281682b
SM		 1375struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1376 u8 transmit_queue_high[0x20];
1377
1378 u8 transmit_queue_low[0x20];
1379
b4ff3a36 1380 u8 reserved_at_40[0x780];
e281682b
SM		 1381};
1382
1383struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1384 u8 rx_octets_high[0x20];
1385
1386 u8 rx_octets_low[0x20];
1387
b4ff3a36 1388 u8 reserved_at_40[0xc0];
e281682b
SM		 1389
1390 u8 rx_frames_high[0x20];
1391
1392 u8 rx_frames_low[0x20];
1393
1394 u8 tx_octets_high[0x20];
1395
1396 u8 tx_octets_low[0x20];
1397
b4ff3a36 1398 u8 reserved_at_180[0xc0];
e281682b
SM		 1399
1400 u8 tx_frames_high[0x20];
1401
1402 u8 tx_frames_low[0x20];
1403
1404 u8 rx_pause_high[0x20];
1405
1406 u8 rx_pause_low[0x20];
1407
1408 u8 rx_pause_duration_high[0x20];
1409
1410 u8 rx_pause_duration_low[0x20];
1411
1412 u8 tx_pause_high[0x20];
1413
1414 u8 tx_pause_low[0x20];
1415
1416 u8 tx_pause_duration_high[0x20];
1417
1418 u8 tx_pause_duration_low[0x20];
1419
1420 u8 rx_pause_transition_high[0x20];
1421
1422 u8 rx_pause_transition_low[0x20];
1423
b4ff3a36 1424 u8 reserved_at_3c0[0x400];
e281682b
SM		 1425};
1426
1427struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1428 u8 port_transmit_wait_high[0x20];
1429
1430 u8 port_transmit_wait_low[0x20];
1431
b4ff3a36 1432 u8 reserved_at_40[0x780];
e281682b
SM		 1433};
1434
1435struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1436 u8 dot3stats_alignment_errors_high[0x20];
1437
1438 u8 dot3stats_alignment_errors_low[0x20];
1439
1440 u8 dot3stats_fcs_errors_high[0x20];
1441
1442 u8 dot3stats_fcs_errors_low[0x20];
1443
1444 u8 dot3stats_single_collision_frames_high[0x20];
1445
1446 u8 dot3stats_single_collision_frames_low[0x20];
1447
1448 u8 dot3stats_multiple_collision_frames_high[0x20];
1449
1450 u8 dot3stats_multiple_collision_frames_low[0x20];
1451
1452 u8 dot3stats_sqe_test_errors_high[0x20];
1453
1454 u8 dot3stats_sqe_test_errors_low[0x20];
1455
1456 u8 dot3stats_deferred_transmissions_high[0x20];
1457
1458 u8 dot3stats_deferred_transmissions_low[0x20];
1459
1460 u8 dot3stats_late_collisions_high[0x20];
1461
1462 u8 dot3stats_late_collisions_low[0x20];
1463
1464 u8 dot3stats_excessive_collisions_high[0x20];
1465
1466 u8 dot3stats_excessive_collisions_low[0x20];
1467
1468 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1469
1470 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1471
1472 u8 dot3stats_carrier_sense_errors_high[0x20];
1473
1474 u8 dot3stats_carrier_sense_errors_low[0x20];
1475
1476 u8 dot3stats_frame_too_longs_high[0x20];
1477
1478 u8 dot3stats_frame_too_longs_low[0x20];
1479
1480 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1481
1482 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1483
1484 u8 dot3stats_symbol_errors_high[0x20];
1485
1486 u8 dot3stats_symbol_errors_low[0x20];
1487
1488 u8 dot3control_in_unknown_opcodes_high[0x20];
1489
1490 u8 dot3control_in_unknown_opcodes_low[0x20];
1491
1492 u8 dot3in_pause_frames_high[0x20];
1493
1494 u8 dot3in_pause_frames_low[0x20];
1495
1496 u8 dot3out_pause_frames_high[0x20];
1497
1498 u8 dot3out_pause_frames_low[0x20];
1499
b4ff3a36 1500 u8 reserved_at_400[0x3c0];
e281682b
SM		 1501};
1502
1503struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1504 u8 ether_stats_drop_events_high[0x20];
1505
1506 u8 ether_stats_drop_events_low[0x20];
1507
1508 u8 ether_stats_octets_high[0x20];
1509
1510 u8 ether_stats_octets_low[0x20];
1511
1512 u8 ether_stats_pkts_high[0x20];
1513
1514 u8 ether_stats_pkts_low[0x20];
1515
1516 u8 ether_stats_broadcast_pkts_high[0x20];
1517
1518 u8 ether_stats_broadcast_pkts_low[0x20];
1519
1520 u8 ether_stats_multicast_pkts_high[0x20];
1521
1522 u8 ether_stats_multicast_pkts_low[0x20];
1523
1524 u8 ether_stats_crc_align_errors_high[0x20];
1525
1526 u8 ether_stats_crc_align_errors_low[0x20];
1527
1528 u8 ether_stats_undersize_pkts_high[0x20];
1529
1530 u8 ether_stats_undersize_pkts_low[0x20];
1531
1532 u8 ether_stats_oversize_pkts_high[0x20];
1533
1534 u8 ether_stats_oversize_pkts_low[0x20];
1535
1536 u8 ether_stats_fragments_high[0x20];
1537
1538 u8 ether_stats_fragments_low[0x20];
1539
1540 u8 ether_stats_jabbers_high[0x20];
1541
1542 u8 ether_stats_jabbers_low[0x20];
1543
1544 u8 ether_stats_collisions_high[0x20];
1545
1546 u8 ether_stats_collisions_low[0x20];
1547
1548 u8 ether_stats_pkts64octets_high[0x20];
1549
1550 u8 ether_stats_pkts64octets_low[0x20];
1551
1552 u8 ether_stats_pkts65to127octets_high[0x20];
1553
1554 u8 ether_stats_pkts65to127octets_low[0x20];
1555
1556 u8 ether_stats_pkts128to255octets_high[0x20];
1557
1558 u8 ether_stats_pkts128to255octets_low[0x20];
1559
1560 u8 ether_stats_pkts256to511octets_high[0x20];
1561
1562 u8 ether_stats_pkts256to511octets_low[0x20];
1563
1564 u8 ether_stats_pkts512to1023octets_high[0x20];
1565
1566 u8 ether_stats_pkts512to1023octets_low[0x20];
1567
1568 u8 ether_stats_pkts1024to1518octets_high[0x20];
1569
1570 u8 ether_stats_pkts1024to1518octets_low[0x20];
1571
1572 u8 ether_stats_pkts1519to2047octets_high[0x20];
1573
1574 u8 ether_stats_pkts1519to2047octets_low[0x20];
1575
1576 u8 ether_stats_pkts2048to4095octets_high[0x20];
1577
1578 u8 ether_stats_pkts2048to4095octets_low[0x20];
1579
1580 u8 ether_stats_pkts4096to8191octets_high[0x20];
1581
1582 u8 ether_stats_pkts4096to8191octets_low[0x20];
1583
1584 u8 ether_stats_pkts8192to10239octets_high[0x20];
1585
1586 u8 ether_stats_pkts8192to10239octets_low[0x20];
1587
b4ff3a36 1588 u8 reserved_at_540[0x280];
e281682b
SM		 1589};
1590
1591struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1592 u8 if_in_octets_high[0x20];
1593
1594 u8 if_in_octets_low[0x20];
1595
1596 u8 if_in_ucast_pkts_high[0x20];
1597
1598 u8 if_in_ucast_pkts_low[0x20];
1599
1600 u8 if_in_discards_high[0x20];
1601
1602 u8 if_in_discards_low[0x20];
1603
1604 u8 if_in_errors_high[0x20];
1605
1606 u8 if_in_errors_low[0x20];
1607
1608 u8 if_in_unknown_protos_high[0x20];
1609
1610 u8 if_in_unknown_protos_low[0x20];
1611
1612 u8 if_out_octets_high[0x20];
1613
1614 u8 if_out_octets_low[0x20];
1615
1616 u8 if_out_ucast_pkts_high[0x20];
1617
1618 u8 if_out_ucast_pkts_low[0x20];
1619
1620 u8 if_out_discards_high[0x20];
1621
1622 u8 if_out_discards_low[0x20];
1623
1624 u8 if_out_errors_high[0x20];
1625
1626 u8 if_out_errors_low[0x20];
1627
1628 u8 if_in_multicast_pkts_high[0x20];
1629
1630 u8 if_in_multicast_pkts_low[0x20];
1631
1632 u8 if_in_broadcast_pkts_high[0x20];
1633
1634 u8 if_in_broadcast_pkts_low[0x20];
1635
1636 u8 if_out_multicast_pkts_high[0x20];
1637
1638 u8 if_out_multicast_pkts_low[0x20];
1639
1640 u8 if_out_broadcast_pkts_high[0x20];
1641
1642 u8 if_out_broadcast_pkts_low[0x20];
1643
b4ff3a36 1644 u8 reserved_at_340[0x480];
e281682b
SM		 1645};
1646
1647struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1648 u8 a_frames_transmitted_ok_high[0x20];
1649
1650 u8 a_frames_transmitted_ok_low[0x20];
1651
1652 u8 a_frames_received_ok_high[0x20];
1653
1654 u8 a_frames_received_ok_low[0x20];
1655
1656 u8 a_frame_check_sequence_errors_high[0x20];
1657
1658 u8 a_frame_check_sequence_errors_low[0x20];
1659
1660 u8 a_alignment_errors_high[0x20];
1661
1662 u8 a_alignment_errors_low[0x20];
1663
1664 u8 a_octets_transmitted_ok_high[0x20];
1665
1666 u8 a_octets_transmitted_ok_low[0x20];
1667
1668 u8 a_octets_received_ok_high[0x20];
1669
1670 u8 a_octets_received_ok_low[0x20];
1671
1672 u8 a_multicast_frames_xmitted_ok_high[0x20];
1673
1674 u8 a_multicast_frames_xmitted_ok_low[0x20];
1675
1676 u8 a_broadcast_frames_xmitted_ok_high[0x20];
1677
1678 u8 a_broadcast_frames_xmitted_ok_low[0x20];
1679
1680 u8 a_multicast_frames_received_ok_high[0x20];
1681
1682 u8 a_multicast_frames_received_ok_low[0x20];
1683
1684 u8 a_broadcast_frames_received_ok_high[0x20];
1685
1686 u8 a_broadcast_frames_received_ok_low[0x20];
1687
1688 u8 a_in_range_length_errors_high[0x20];
1689
1690 u8 a_in_range_length_errors_low[0x20];
1691
1692 u8 a_out_of_range_length_field_high[0x20];
1693
1694 u8 a_out_of_range_length_field_low[0x20];
1695
1696 u8 a_frame_too_long_errors_high[0x20];
1697
1698 u8 a_frame_too_long_errors_low[0x20];
1699
1700 u8 a_symbol_error_during_carrier_high[0x20];
1701
1702 u8 a_symbol_error_during_carrier_low[0x20];
1703
1704 u8 a_mac_control_frames_transmitted_high[0x20];
1705
1706 u8 a_mac_control_frames_transmitted_low[0x20];
1707
1708 u8 a_mac_control_frames_received_high[0x20];
1709
1710 u8 a_mac_control_frames_received_low[0x20];
1711
1712 u8 a_unsupported_opcodes_received_high[0x20];
1713
1714 u8 a_unsupported_opcodes_received_low[0x20];
1715
1716 u8 a_pause_mac_ctrl_frames_received_high[0x20];
1717
1718 u8 a_pause_mac_ctrl_frames_received_low[0x20];
1719
1720 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
1721
1722 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
1723
b4ff3a36 1724 u8 reserved_at_4c0[0x300];
e281682b
SM		 1725};
1726
1727struct mlx5_ifc_cmd_inter_comp_event_bits {
1728 u8 command_completion_vector[0x20];
1729
b4ff3a36 1730 u8 reserved_at_20[0xc0];
e281682b
SM		 1731};
1732
1733struct mlx5_ifc_stall_vl_event_bits {
b4ff3a36 1734 u8 reserved_at_0[0x18];
e281682b 1735 u8 port_num[0x1];
b4ff3a36 1736 u8 reserved_at_19[0x3];
e281682b
SM		 1737 u8 vl[0x4];
1738
b4ff3a36 1739 u8 reserved_at_20[0xa0];
e281682b
SM		 1740};
1741
1742struct mlx5_ifc_db_bf_congestion_event_bits {
1743 u8 event_subtype[0x8];
b4ff3a36 1744 u8 reserved_at_8[0x8];
e281682b 1745 u8 congestion_level[0x8];
b4ff3a36 1746 u8 reserved_at_18[0x8];
e281682b 1747
b4ff3a36 1748 u8 reserved_at_20[0xa0];
e281682b
SM		 1749};
1750
1751struct mlx5_ifc_gpio_event_bits {
b4ff3a36 1752 u8 reserved_at_0[0x60];
e281682b
SM		 1753
1754 u8 gpio_event_hi[0x20];
1755
1756 u8 gpio_event_lo[0x20];
1757
b4ff3a36 1758 u8 reserved_at_a0[0x40];
e281682b
SM		 1759};
1760
1761struct mlx5_ifc_port_state_change_event_bits {
b4ff3a36 1762 u8 reserved_at_0[0x40];
e281682b
SM		 1763
1764 u8 port_num[0x4];
b4ff3a36 1765 u8 reserved_at_44[0x1c];
e281682b 1766
b4ff3a36 1767 u8 reserved_at_60[0x80];
e281682b
SM		 1768};
1769
1770struct mlx5_ifc_dropped_packet_logged_bits {
b4ff3a36 1771 u8 reserved_at_0[0xe0];
e281682b
SM		 1772};
1773
1774enum {
1775 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
1776 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
1777};
1778
1779struct mlx5_ifc_cq_error_bits {
b4ff3a36 1780 u8 reserved_at_0[0x8];
e281682b
SM		 1781 u8 cqn[0x18];
1782
b4ff3a36 1783 u8 reserved_at_20[0x20];
e281682b 1784
b4ff3a36 1785 u8 reserved_at_40[0x18];
e281682b
SM		 1786 u8 syndrome[0x8];
1787
b4ff3a36 1788 u8 reserved_at_60[0x80];
e281682b
SM		 1789};
1790
1791struct mlx5_ifc_rdma_page_fault_event_bits {
1792 u8 bytes_committed[0x20];
1793
1794 u8 r_key[0x20];
1795
b4ff3a36 1796 u8 reserved_at_40[0x10];
e281682b
SM		 1797 u8 packet_len[0x10];
1798
1799 u8 rdma_op_len[0x20];
1800
1801 u8 rdma_va[0x40];
1802
b4ff3a36 1803 u8 reserved_at_c0[0x5];
e281682b
SM		 1804 u8 rdma[0x1];
1805 u8 write[0x1];
1806 u8 requestor[0x1];
1807 u8 qp_number[0x18];
1808};
1809
1810struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1811 u8 bytes_committed[0x20];
1812
b4ff3a36 1813 u8 reserved_at_20[0x10];
e281682b
SM		 1814 u8 wqe_index[0x10];
1815
b4ff3a36 1816 u8 reserved_at_40[0x10];
e281682b
SM		 1817 u8 len[0x10];
1818
b4ff3a36 1819 u8 reserved_at_60[0x60];
e281682b 1820
b4ff3a36 1821 u8 reserved_at_c0[0x5];
e281682b
SM		 1822 u8 rdma[0x1];
1823 u8 write_read[0x1];
1824 u8 requestor[0x1];
1825 u8 qpn[0x18];
1826};
1827
1828struct mlx5_ifc_qp_events_bits {
b4ff3a36 1829 u8 reserved_at_0[0xa0];
e281682b
SM		 1830
1831 u8 type[0x8];
b4ff3a36 1832 u8 reserved_at_a8[0x18];
e281682b 1833
b4ff3a36 1834 u8 reserved_at_c0[0x8];
e281682b
SM		 1835 u8 qpn_rqn_sqn[0x18];
1836};
1837
1838struct mlx5_ifc_dct_events_bits {
b4ff3a36 1839 u8 reserved_at_0[0xc0];
e281682b 1840
b4ff3a36 1841 u8 reserved_at_c0[0x8];
e281682b
SM		 1842 u8 dct_number[0x18];
1843};
1844
1845struct mlx5_ifc_comp_event_bits {
b4ff3a36 1846 u8 reserved_at_0[0xc0];
e281682b 1847
b4ff3a36 1848 u8 reserved_at_c0[0x8];
e281682b
SM		 1849 u8 cq_number[0x18];
1850};
1851
1852enum {
1853 MLX5_QPC_STATE_RST = 0x0,
1854 MLX5_QPC_STATE_INIT = 0x1,
1855 MLX5_QPC_STATE_RTR = 0x2,
1856 MLX5_QPC_STATE_RTS = 0x3,
1857 MLX5_QPC_STATE_SQER = 0x4,
1858 MLX5_QPC_STATE_ERR = 0x6,
1859 MLX5_QPC_STATE_SQD = 0x7,
1860 MLX5_QPC_STATE_SUSPENDED = 0x9,
1861};
1862
1863enum {
1864 MLX5_QPC_ST_RC = 0x0,
1865 MLX5_QPC_ST_UC = 0x1,
1866 MLX5_QPC_ST_UD = 0x2,
1867 MLX5_QPC_ST_XRC = 0x3,
1868 MLX5_QPC_ST_DCI = 0x5,
1869 MLX5_QPC_ST_QP0 = 0x7,
1870 MLX5_QPC_ST_QP1 = 0x8,
1871 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
1872 MLX5_QPC_ST_REG_UMR = 0xc,
1873};
1874
1875enum {
1876 MLX5_QPC_PM_STATE_ARMED = 0x0,
1877 MLX5_QPC_PM_STATE_REARM = 0x1,
1878 MLX5_QPC_PM_STATE_RESERVED = 0x2,
1879 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
1880};
1881
1882enum {
1883 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
1884 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
1885};
1886
1887enum {
1888 MLX5_QPC_MTU_256_BYTES = 0x1,
1889 MLX5_QPC_MTU_512_BYTES = 0x2,
1890 MLX5_QPC_MTU_1K_BYTES = 0x3,
1891 MLX5_QPC_MTU_2K_BYTES = 0x4,
1892 MLX5_QPC_MTU_4K_BYTES = 0x5,
1893 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
1894};
1895
1896enum {
1897 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
1898 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
1899 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
1900 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
1901 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
1902 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
1903 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
1904 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
1905};
1906
1907enum {
1908 MLX5_QPC_CS_REQ_DISABLE = 0x0,
1909 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
1910 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
1911};
1912
1913enum {
1914 MLX5_QPC_CS_RES_DISABLE = 0x0,
1915 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
1916 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
1917};
1918
1919struct mlx5_ifc_qpc_bits {
1920 u8 state[0x4];
b4ff3a36 1921 u8 reserved_at_4[0x4];
e281682b 1922 u8 st[0x8];
b4ff3a36 1923 u8 reserved_at_10[0x3];
e281682b 1924 u8 pm_state[0x2];
b4ff3a36 1925 u8 reserved_at_15[0x7];
e281682b 1926 u8 end_padding_mode[0x2];
b4ff3a36 1927 u8 reserved_at_1e[0x2];
e281682b
SM		 1928
1929 u8 wq_signature[0x1];
1930 u8 block_lb_mc[0x1];
1931 u8 atomic_like_write_en[0x1];
1932 u8 latency_sensitive[0x1];
b4ff3a36 1933 u8 reserved_at_24[0x1];
e281682b 1934 u8 drain_sigerr[0x1];
b4ff3a36 1935 u8 reserved_at_26[0x2];
e281682b
SM		 1936 u8 pd[0x18];
1937
1938 u8 mtu[0x3];
1939 u8 log_msg_max[0x5];
b4ff3a36 1940 u8 reserved_at_48[0x1];
e281682b
SM		 1941 u8 log_rq_size[0x4];
1942 u8 log_rq_stride[0x3];
1943 u8 no_sq[0x1];
1944 u8 log_sq_size[0x4];
b4ff3a36 1945 u8 reserved_at_55[0x6];
e281682b 1946 u8 rlky[0x1];
1015c2e8 1947 u8 ulp_stateless_offload_mode[0x4];
e281682b
SM		 1948
1949 u8 counter_set_id[0x8];
1950 u8 uar_page[0x18];
1951
b4ff3a36 1952 u8 reserved_at_80[0x8];
e281682b
SM		 1953 u8 user_index[0x18];
1954
b4ff3a36 1955 u8 reserved_at_a0[0x3];
e281682b
SM		 1956 u8 log_page_size[0x5];
1957 u8 remote_qpn[0x18];
1958
1959 struct mlx5_ifc_ads_bits primary_address_path;
1960
1961 struct mlx5_ifc_ads_bits secondary_address_path;
1962
1963 u8 log_ack_req_freq[0x4];
b4ff3a36 1964 u8 reserved_at_384[0x4];
e281682b 1965 u8 log_sra_max[0x3];
b4ff3a36 1966 u8 reserved_at_38b[0x2];
e281682b
SM		 1967 u8 retry_count[0x3];
1968 u8 rnr_retry[0x3];
b4ff3a36 1969 u8 reserved_at_393[0x1];
e281682b
SM		 1970 u8 fre[0x1];
1971 u8 cur_rnr_retry[0x3];
1972 u8 cur_retry_count[0x3];
b4ff3a36 1973 u8 reserved_at_39b[0x5];
e281682b 1974
b4ff3a36 1975 u8 reserved_at_3a0[0x20];
e281682b 1976
b4ff3a36 1977 u8 reserved_at_3c0[0x8];
e281682b
SM		 1978 u8 next_send_psn[0x18];
1979
b4ff3a36 1980 u8 reserved_at_3e0[0x8];
e281682b
SM		 1981 u8 cqn_snd[0x18];
1982
09a7d9ec
SM		 1983 u8 reserved_at_400[0x8];
1984 u8 deth_sqpn[0x18];
1985
1986 u8 reserved_at_420[0x20];
e281682b 1987
b4ff3a36 1988 u8 reserved_at_440[0x8];
e281682b
SM		 1989 u8 last_acked_psn[0x18];
1990
b4ff3a36 1991 u8 reserved_at_460[0x8];
e281682b
SM		 1992 u8 ssn[0x18];
1993
b4ff3a36 1994 u8 reserved_at_480[0x8];
e281682b 1995 u8 log_rra_max[0x3];
b4ff3a36 1996 u8 reserved_at_48b[0x1];
e281682b
SM		 1997 u8 atomic_mode[0x4];
1998 u8 rre[0x1];
1999 u8 rwe[0x1];
2000 u8 rae[0x1];
b4ff3a36 2001 u8 reserved_at_493[0x1];
e281682b 2002 u8 page_offset[0x6];
b4ff3a36 2003 u8 reserved_at_49a[0x3];
e281682b
SM		 2004 u8 cd_slave_receive[0x1];
2005 u8 cd_slave_send[0x1];
2006 u8 cd_master[0x1];
2007
b4ff3a36 2008 u8 reserved_at_4a0[0x3];
e281682b
SM		 2009 u8 min_rnr_nak[0x5];
2010 u8 next_rcv_psn[0x18];
2011
b4ff3a36 2012 u8 reserved_at_4c0[0x8];
e281682b
SM		 2013 u8 xrcd[0x18];
2014
b4ff3a36 2015 u8 reserved_at_4e0[0x8];
e281682b
SM		 2016 u8 cqn_rcv[0x18];
2017
2018 u8 dbr_addr[0x40];
2019
2020 u8 q_key[0x20];
2021
b4ff3a36 2022 u8 reserved_at_560[0x5];
e281682b 2023 u8 rq_type[0x3];
7486216b 2024 u8 srqn_rmpn_xrqn[0x18];
e281682b 2025
b4ff3a36 2026 u8 reserved_at_580[0x8];
e281682b
SM		 2027 u8 rmsn[0x18];
2028
2029 u8 hw_sq_wqebb_counter[0x10];
2030 u8 sw_sq_wqebb_counter[0x10];
2031
2032 u8 hw_rq_counter[0x20];
2033
2034 u8 sw_rq_counter[0x20];
2035
b4ff3a36 2036 u8 reserved_at_600[0x20];
e281682b 2037
b4ff3a36 2038 u8 reserved_at_620[0xf];
e281682b
SM		 2039 u8 cgs[0x1];
2040 u8 cs_req[0x8];
2041 u8 cs_res[0x8];
2042
2043 u8 dc_access_key[0x40];
2044
b4ff3a36 2045 u8 reserved_at_680[0xc0];
e281682b
SM		 2046};
2047
2048struct mlx5_ifc_roce_addr_layout_bits {
2049 u8 source_l3_address[16][0x8];
2050
b4ff3a36 2051 u8 reserved_at_80[0x3];
e281682b
SM		 2052 u8 vlan_valid[0x1];
2053 u8 vlan_id[0xc];
2054 u8 source_mac_47_32[0x10];
2055
2056 u8 source_mac_31_0[0x20];
2057
b4ff3a36 2058 u8 reserved_at_c0[0x14];
e281682b
SM		 2059 u8 roce_l3_type[0x4];
2060 u8 roce_version[0x8];
2061
b4ff3a36 2062 u8 reserved_at_e0[0x20];
e281682b
SM		 2063};
2064
2065union mlx5_ifc_hca_cap_union_bits {
2066 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
2067 struct mlx5_ifc_odp_cap_bits odp_cap;
2068 struct mlx5_ifc_atomic_caps_bits atomic_caps;
2069 struct mlx5_ifc_roce_cap_bits roce_cap;
2070 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
2071 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
495716b1 2072 struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;
d6666753 2073 struct mlx5_ifc_e_switch_cap_bits e_switch_cap;
3f0393a5 2074 struct mlx5_ifc_vector_calc_cap_bits vector_calc_cap;
7486216b 2075 struct mlx5_ifc_qos_cap_bits qos_cap;
b4ff3a36 2076 u8 reserved_at_0[0x8000];
e281682b
SM		 2077};
2078
2079enum {
2080 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
2081 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
2082 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
9dc0b289 2083 MLX5_FLOW_CONTEXT_ACTION_COUNT = 0x8,
7adbde20
HHZ		 2084 MLX5_FLOW_CONTEXT_ACTION_ENCAP = 0x10,
2085 MLX5_FLOW_CONTEXT_ACTION_DECAP = 0x20,
e281682b
SM		 2086};
2087
2088struct mlx5_ifc_flow_context_bits {
b4ff3a36 2089 u8 reserved_at_0[0x20];
e281682b
SM		 2090
2091 u8 group_id[0x20];
2092
b4ff3a36 2093 u8 reserved_at_40[0x8];
e281682b
SM		 2094 u8 flow_tag[0x18];
2095
b4ff3a36 2096 u8 reserved_at_60[0x10];
e281682b
SM		 2097 u8 action[0x10];
2098
b4ff3a36 2099 u8 reserved_at_80[0x8];
e281682b
SM		 2100 u8 destination_list_size[0x18];
2101
9dc0b289
AV		 2102 u8 reserved_at_a0[0x8];
2103 u8 flow_counter_list_size[0x18];
2104
7adbde20
HHZ		 2105 u8 encap_id[0x20];
2106
2107 u8 reserved_at_e0[0x120];
e281682b
SM		 2108
2109 struct mlx5_ifc_fte_match_param_bits match_value;
2110
b4ff3a36 2111 u8 reserved_at_1200[0x600];
e281682b 2112
9dc0b289 2113 union mlx5_ifc_dest_format_struct_flow_counter_list_auto_bits destination[0];
e281682b
SM		 2114};
2115
2116enum {
2117 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
2118 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
2119};
2120
2121struct mlx5_ifc_xrc_srqc_bits {
2122 u8 state[0x4];
2123 u8 log_xrc_srq_size[0x4];
b4ff3a36 2124 u8 reserved_at_8[0x18];
e281682b
SM		 2125
2126 u8 wq_signature[0x1];
2127 u8 cont_srq[0x1];
b4ff3a36 2128 u8 reserved_at_22[0x1];
e281682b
SM		 2129 u8 rlky[0x1];
2130 u8 basic_cyclic_rcv_wqe[0x1];
2131 u8 log_rq_stride[0x3];
2132 u8 xrcd[0x18];
2133
2134 u8 page_offset[0x6];
b4ff3a36 2135 u8 reserved_at_46[0x2];
e281682b
SM		 2136 u8 cqn[0x18];
2137
b4ff3a36 2138 u8 reserved_at_60[0x20];
e281682b
SM		 2139
2140 u8 user_index_equal_xrc_srqn[0x1];
b4ff3a36 2141 u8 reserved_at_81[0x1];
e281682b
SM		 2142 u8 log_page_size[0x6];
2143 u8 user_index[0x18];
2144
b4ff3a36 2145 u8 reserved_at_a0[0x20];
e281682b 2146
b4ff3a36 2147 u8 reserved_at_c0[0x8];
e281682b
SM		 2148 u8 pd[0x18];
2149
2150 u8 lwm[0x10];
2151 u8 wqe_cnt[0x10];
2152
b4ff3a36 2153 u8 reserved_at_100[0x40];
e281682b
SM		 2154
2155 u8 db_record_addr_h[0x20];
2156
2157 u8 db_record_addr_l[0x1e];
b4ff3a36 2158 u8 reserved_at_17e[0x2];
e281682b 2159
b4ff3a36 2160 u8 reserved_at_180[0x80];
e281682b
SM		 2161};
2162
2163struct mlx5_ifc_traffic_counter_bits {
2164 u8 packets[0x40];
2165
2166 u8 octets[0x40];
2167};
2168
2169struct mlx5_ifc_tisc_bits {
b4ff3a36 2170 u8 reserved_at_0[0xc];
e281682b 2171 u8 prio[0x4];
b4ff3a36 2172 u8 reserved_at_10[0x10];
e281682b 2173
b4ff3a36 2174 u8 reserved_at_20[0x100];
e281682b 2175
b4ff3a36 2176 u8 reserved_at_120[0x8];
e281682b
SM		 2177 u8 transport_domain[0x18];
2178
b4ff3a36 2179 u8 reserved_at_140[0x3c0];
e281682b
SM		 2180};
2181
2182enum {
2183 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
2184 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
2185};
2186
2187enum {
2188 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
2189 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
2190};
2191
2192enum {
2be6967c
SM		 2193 MLX5_RX_HASH_FN_NONE = 0x0,
2194 MLX5_RX_HASH_FN_INVERTED_XOR8 = 0x1,
2195 MLX5_RX_HASH_FN_TOEPLITZ = 0x2,
e281682b
SM		 2196};
2197
2198enum {
2199 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1,
2200 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2,
2201};
2202
2203struct mlx5_ifc_tirc_bits {
b4ff3a36 2204 u8 reserved_at_0[0x20];
e281682b
SM		 2205
2206 u8 disp_type[0x4];
b4ff3a36 2207 u8 reserved_at_24[0x1c];
e281682b 2208
b4ff3a36 2209 u8 reserved_at_40[0x40];
e281682b 2210
b4ff3a36 2211 u8 reserved_at_80[0x4];
e281682b
SM		 2212 u8 lro_timeout_period_usecs[0x10];
2213 u8 lro_enable_mask[0x4];
2214 u8 lro_max_ip_payload_size[0x8];
2215
b4ff3a36 2216 u8 reserved_at_a0[0x40];
e281682b 2217
b4ff3a36 2218 u8 reserved_at_e0[0x8];
e281682b
SM		 2219 u8 inline_rqn[0x18];
2220
2221 u8 rx_hash_symmetric[0x1];
b4ff3a36 2222 u8 reserved_at_101[0x1];
e281682b 2223 u8 tunneled_offload_en[0x1];
b4ff3a36 2224 u8 reserved_at_103[0x5];
e281682b
SM		 2225 u8 indirect_table[0x18];
2226
2227 u8 rx_hash_fn[0x4];
b4ff3a36 2228 u8 reserved_at_124[0x2];
e281682b
SM		 2229 u8 self_lb_block[0x2];
2230 u8 transport_domain[0x18];
2231
2232 u8 rx_hash_toeplitz_key[10][0x20];
2233
2234 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
2235
2236 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
2237
b4ff3a36 2238 u8 reserved_at_2c0[0x4c0];
e281682b
SM		 2239};
2240
2241enum {
2242 MLX5_SRQC_STATE_GOOD = 0x0,
2243 MLX5_SRQC_STATE_ERROR = 0x1,
2244};
2245
2246struct mlx5_ifc_srqc_bits {
2247 u8 state[0x4];
2248 u8 log_srq_size[0x4];
b4ff3a36 2249 u8 reserved_at_8[0x18];
e281682b
SM		 2250
2251 u8 wq_signature[0x1];
2252 u8 cont_srq[0x1];
b4ff3a36 2253 u8 reserved_at_22[0x1];
e281682b 2254 u8 rlky[0x1];
b4ff3a36 2255 u8 reserved_at_24[0x1];
e281682b
SM		 2256 u8 log_rq_stride[0x3];
2257 u8 xrcd[0x18];
2258
2259 u8 page_offset[0x6];
b4ff3a36 2260 u8 reserved_at_46[0x2];
e281682b
SM		 2261 u8 cqn[0x18];
2262
b4ff3a36 2263 u8 reserved_at_60[0x20];
e281682b 2264
b4ff3a36 2265 u8 reserved_at_80[0x2];
e281682b 2266 u8 log_page_size[0x6];
b4ff3a36 2267 u8 reserved_at_88[0x18];
e281682b 2268
b4ff3a36 2269 u8 reserved_at_a0[0x20];
e281682b 2270
b4ff3a36 2271 u8 reserved_at_c0[0x8];
e281682b
SM		 2272 u8 pd[0x18];
2273
2274 u8 lwm[0x10];
2275 u8 wqe_cnt[0x10];
2276
b4ff3a36 2277 u8 reserved_at_100[0x40];
e281682b 2278
01949d01 2279 u8 dbr_addr[0x40];
e281682b 2280
b4ff3a36 2281 u8 reserved_at_180[0x80];
e281682b
SM		 2282};
2283
2284enum {
2285 MLX5_SQC_STATE_RST = 0x0,
2286 MLX5_SQC_STATE_RDY = 0x1,
2287 MLX5_SQC_STATE_ERR = 0x3,
2288};
2289
2290struct mlx5_ifc_sqc_bits {
2291 u8 rlky[0x1];
2292 u8 cd_master[0x1];
2293 u8 fre[0x1];
2294 u8 flush_in_error_en[0x1];
cff92d7c
HHZ		 2295 u8 reserved_at_4[0x1];
2296 u8 min_wqe_inline_mode[0x3];
e281682b 2297 u8 state[0x4];
7d5e1423
SM		 2298 u8 reg_umr[0x1];
2299 u8 reserved_at_d[0x13];
e281682b 2300
b4ff3a36 2301 u8 reserved_at_20[0x8];
e281682b
SM		 2302 u8 user_index[0x18];
2303
b4ff3a36 2304 u8 reserved_at_40[0x8];
e281682b
SM		 2305 u8 cqn[0x18];
2306
7486216b 2307 u8 reserved_at_60[0x90];
e281682b 2308
7486216b 2309 u8 packet_pacing_rate_limit_index[0x10];
e281682b 2310 u8 tis_lst_sz[0x10];
b4ff3a36 2311 u8 reserved_at_110[0x10];
e281682b 2312
b4ff3a36 2313 u8 reserved_at_120[0x40];
e281682b 2314
b4ff3a36 2315 u8 reserved_at_160[0x8];
e281682b
SM		 2316 u8 tis_num_0[0x18];
2317
2318 struct mlx5_ifc_wq_bits wq;
2319};
2320
2321struct mlx5_ifc_rqtc_bits {
b4ff3a36 2322 u8 reserved_at_0[0xa0];
e281682b 2323
b4ff3a36 2324 u8 reserved_at_a0[0x10];
e281682b
SM		 2325 u8 rqt_max_size[0x10];
2326
b4ff3a36 2327 u8 reserved_at_c0[0x10];
e281682b
SM		 2328 u8 rqt_actual_size[0x10];
2329
b4ff3a36 2330 u8 reserved_at_e0[0x6a0];
e281682b
SM		 2331
2332 struct mlx5_ifc_rq_num_bits rq_num[0];
2333};
2334
2335enum {
2336 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2337 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2338};
2339
2340enum {
2341 MLX5_RQC_STATE_RST = 0x0,
2342 MLX5_RQC_STATE_RDY = 0x1,
2343 MLX5_RQC_STATE_ERR = 0x3,
2344};
2345
2346struct mlx5_ifc_rqc_bits {
2347 u8 rlky[0x1];
7d5e1423
SM		 2348 u8 reserved_at_1[0x1];
2349 u8 scatter_fcs[0x1];
e281682b
SM		 2350 u8 vsd[0x1];
2351 u8 mem_rq_type[0x4];
2352 u8 state[0x4];
b4ff3a36 2353 u8 reserved_at_c[0x1];
e281682b 2354 u8 flush_in_error_en[0x1];
b4ff3a36 2355 u8 reserved_at_e[0x12];
e281682b 2356
b4ff3a36 2357 u8 reserved_at_20[0x8];
e281682b
SM		 2358 u8 user_index[0x18];
2359
b4ff3a36 2360 u8 reserved_at_40[0x8];
e281682b
SM		 2361 u8 cqn[0x18];
2362
2363 u8 counter_set_id[0x8];
b4ff3a36 2364 u8 reserved_at_68[0x18];
e281682b 2365
b4ff3a36 2366 u8 reserved_at_80[0x8];
e281682b
SM		 2367 u8 rmpn[0x18];
2368
b4ff3a36 2369 u8 reserved_at_a0[0xe0];
e281682b
SM		 2370
2371 struct mlx5_ifc_wq_bits wq;
2372};
2373
2374enum {
2375 MLX5_RMPC_STATE_RDY = 0x1,
2376 MLX5_RMPC_STATE_ERR = 0x3,
2377};
2378
2379struct mlx5_ifc_rmpc_bits {
b4ff3a36 2380 u8 reserved_at_0[0x8];
e281682b 2381 u8 state[0x4];
b4ff3a36 2382 u8 reserved_at_c[0x14];
e281682b
SM		 2383
2384 u8 basic_cyclic_rcv_wqe[0x1];
b4ff3a36 2385 u8 reserved_at_21[0x1f];
e281682b 2386
b4ff3a36 2387 u8 reserved_at_40[0x140];
e281682b
SM		 2388
2389 struct mlx5_ifc_wq_bits wq;
2390};
2391
e281682b 2392struct mlx5_ifc_nic_vport_context_bits {
cff92d7c
HHZ		 2393 u8 reserved_at_0[0x5];
2394 u8 min_wqe_inline_mode[0x3];
2395 u8 reserved_at_8[0x17];
e281682b
SM		 2396 u8 roce_en[0x1];
2397
d82b7318 2398 u8 arm_change_event[0x1];
b4ff3a36 2399 u8 reserved_at_21[0x1a];
d82b7318
SM		 2400 u8 event_on_mtu[0x1];
2401 u8 event_on_promisc_change[0x1];
2402 u8 event_on_vlan_change[0x1];
2403 u8 event_on_mc_address_change[0x1];
2404 u8 event_on_uc_address_change[0x1];
e281682b 2405
b4ff3a36 2406 u8 reserved_at_40[0xf0];
d82b7318
SM		 2407
2408 u8 mtu[0x10];
2409
9efa7525
AS		 2410 u8 system_image_guid[0x40];
2411 u8 port_guid[0x40];
2412 u8 node_guid[0x40];
2413
b4ff3a36 2414 u8 reserved_at_200[0x140];
9efa7525 2415 u8 qkey_violation_counter[0x10];
b4ff3a36 2416 u8 reserved_at_350[0x430];
d82b7318
SM		 2417
2418 u8 promisc_uc[0x1];
2419 u8 promisc_mc[0x1];
2420 u8 promisc_all[0x1];
b4ff3a36 2421 u8 reserved_at_783[0x2];
e281682b 2422 u8 allowed_list_type[0x3];
b4ff3a36 2423 u8 reserved_at_788[0xc];
e281682b
SM		 2424 u8 allowed_list_size[0xc];
2425
2426 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2427
b4ff3a36 2428 u8 reserved_at_7e0[0x20];
e281682b
SM		 2429
2430 u8 current_uc_mac_address[0][0x40];
2431};
2432
2433enum {
2434 MLX5_MKC_ACCESS_MODE_PA = 0x0,
2435 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
2436 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
2437};
2438
2439struct mlx5_ifc_mkc_bits {
b4ff3a36 2440 u8 reserved_at_0[0x1];
e281682b 2441 u8 free[0x1];
b4ff3a36 2442 u8 reserved_at_2[0xd];
e281682b
SM		 2443 u8 small_fence_on_rdma_read_response[0x1];
2444 u8 umr_en[0x1];
2445 u8 a[0x1];
2446 u8 rw[0x1];
2447 u8 rr[0x1];
2448 u8 lw[0x1];
2449 u8 lr[0x1];
2450 u8 access_mode[0x2];
b4ff3a36 2451 u8 reserved_at_18[0x8];
e281682b
SM		 2452
2453 u8 qpn[0x18];
2454 u8 mkey_7_0[0x8];
2455
b4ff3a36 2456 u8 reserved_at_40[0x20];
e281682b
SM		 2457
2458 u8 length64[0x1];
2459 u8 bsf_en[0x1];
2460 u8 sync_umr[0x1];
b4ff3a36 2461 u8 reserved_at_63[0x2];
e281682b 2462 u8 expected_sigerr_count[0x1];
b4ff3a36 2463 u8 reserved_at_66[0x1];
e281682b
SM		 2464 u8 en_rinval[0x1];
2465 u8 pd[0x18];
2466
2467 u8 start_addr[0x40];
2468
2469 u8 len[0x40];
2470
2471 u8 bsf_octword_size[0x20];
2472
b4ff3a36 2473 u8 reserved_at_120[0x80];
e281682b
SM		 2474
2475 u8 translations_octword_size[0x20];
2476
b4ff3a36 2477 u8 reserved_at_1c0[0x1b];
e281682b
SM		 2478 u8 log_page_size[0x5];
2479
b4ff3a36 2480 u8 reserved_at_1e0[0x20];
e281682b
SM		 2481};
2482
2483struct mlx5_ifc_pkey_bits {
b4ff3a36 2484 u8 reserved_at_0[0x10];
e281682b
SM		 2485 u8 pkey[0x10];
2486};
2487
2488struct mlx5_ifc_array128_auto_bits {
2489 u8 array128_auto[16][0x8];
2490};
2491
2492struct mlx5_ifc_hca_vport_context_bits {
2493 u8 field_select[0x20];
2494
b4ff3a36 2495 u8 reserved_at_20[0xe0];
e281682b
SM		 2496
2497 u8 sm_virt_aware[0x1];
2498 u8 has_smi[0x1];
2499 u8 has_raw[0x1];
2500 u8 grh_required[0x1];
b4ff3a36 2501 u8 reserved_at_104[0xc];
707c4602
MD		 2502 u8 port_physical_state[0x4];
2503 u8 vport_state_policy[0x4];
2504 u8 port_state[0x4];
e281682b
SM		 2505 u8 vport_state[0x4];
2506
b4ff3a36 2507 u8 reserved_at_120[0x20];
707c4602
MD		 2508
2509 u8 system_image_guid[0x40];
e281682b
SM		 2510
2511 u8 port_guid[0x40];
2512
2513 u8 node_guid[0x40];
2514
2515 u8 cap_mask1[0x20];
2516
2517 u8 cap_mask1_field_select[0x20];
2518
2519 u8 cap_mask2[0x20];
2520
2521 u8 cap_mask2_field_select[0x20];
2522
b4ff3a36 2523 u8 reserved_at_280[0x80];
e281682b
SM		 2524
2525 u8 lid[0x10];
b4ff3a36 2526 u8 reserved_at_310[0x4];
e281682b
SM		 2527 u8 init_type_reply[0x4];
2528 u8 lmc[0x3];
2529 u8 subnet_timeout[0x5];
2530
2531 u8 sm_lid[0x10];
2532 u8 sm_sl[0x4];
b4ff3a36 2533 u8 reserved_at_334[0xc];
e281682b
SM		 2534
2535 u8 qkey_violation_counter[0x10];
2536 u8 pkey_violation_counter[0x10];
2537
b4ff3a36 2538 u8 reserved_at_360[0xca0];
e281682b
SM		 2539};
2540
d6666753 2541struct mlx5_ifc_esw_vport_context_bits {
b4ff3a36 2542 u8 reserved_at_0[0x3];
d6666753
SM		 2543 u8 vport_svlan_strip[0x1];
2544 u8 vport_cvlan_strip[0x1];
2545 u8 vport_svlan_insert[0x1];
2546 u8 vport_cvlan_insert[0x2];
b4ff3a36 2547 u8 reserved_at_8[0x18];
d6666753 2548
b4ff3a36 2549 u8 reserved_at_20[0x20];
d6666753
SM		 2550
2551 u8 svlan_cfi[0x1];
2552 u8 svlan_pcp[0x3];
2553 u8 svlan_id[0xc];
2554 u8 cvlan_cfi[0x1];
2555 u8 cvlan_pcp[0x3];
2556 u8 cvlan_id[0xc];
2557
b4ff3a36 2558 u8 reserved_at_60[0x7a0];
d6666753
SM		 2559};
2560
e281682b
SM		 2561enum {
2562 MLX5_EQC_STATUS_OK = 0x0,
2563 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
2564};
2565
2566enum {
2567 MLX5_EQC_ST_ARMED = 0x9,
2568 MLX5_EQC_ST_FIRED = 0xa,
2569};
2570
2571struct mlx5_ifc_eqc_bits {
2572 u8 status[0x4];
b4ff3a36 2573 u8 reserved_at_4[0x9];
e281682b
SM		 2574 u8 ec[0x1];
2575 u8 oi[0x1];
b4ff3a36 2576 u8 reserved_at_f[0x5];
e281682b 2577 u8 st[0x4];
b4ff3a36 2578 u8 reserved_at_18[0x8];
e281682b 2579
b4ff3a36 2580 u8 reserved_at_20[0x20];
e281682b 2581
b4ff3a36 2582 u8 reserved_at_40[0x14];
e281682b 2583 u8 page_offset[0x6];
b4ff3a36 2584 u8 reserved_at_5a[0x6];
e281682b 2585
b4ff3a36 2586 u8 reserved_at_60[0x3];
e281682b
SM		 2587 u8 log_eq_size[0x5];
2588 u8 uar_page[0x18];
2589
b4ff3a36 2590 u8 reserved_at_80[0x20];
e281682b 2591
b4ff3a36 2592 u8 reserved_at_a0[0x18];
e281682b
SM		 2593 u8 intr[0x8];
2594
b4ff3a36 2595 u8 reserved_at_c0[0x3];
e281682b 2596 u8 log_page_size[0x5];
b4ff3a36 2597 u8 reserved_at_c8[0x18];
e281682b 2598
b4ff3a36 2599 u8 reserved_at_e0[0x60];
e281682b 2600
b4ff3a36 2601 u8 reserved_at_140[0x8];
e281682b
SM		 2602 u8 consumer_counter[0x18];
2603
b4ff3a36 2604 u8 reserved_at_160[0x8];
e281682b
SM		 2605 u8 producer_counter[0x18];
2606
b4ff3a36 2607 u8 reserved_at_180[0x80];
e281682b
SM		 2608};
2609
2610enum {
2611 MLX5_DCTC_STATE_ACTIVE = 0x0,
2612 MLX5_DCTC_STATE_DRAINING = 0x1,
2613 MLX5_DCTC_STATE_DRAINED = 0x2,
2614};
2615
2616enum {
2617 MLX5_DCTC_CS_RES_DISABLE = 0x0,
2618 MLX5_DCTC_CS_RES_NA = 0x1,
2619 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
2620};
2621
2622enum {
2623 MLX5_DCTC_MTU_256_BYTES = 0x1,
2624 MLX5_DCTC_MTU_512_BYTES = 0x2,
2625 MLX5_DCTC_MTU_1K_BYTES = 0x3,
2626 MLX5_DCTC_MTU_2K_BYTES = 0x4,
2627 MLX5_DCTC_MTU_4K_BYTES = 0x5,
2628};
2629
2630struct mlx5_ifc_dctc_bits {
b4ff3a36 2631 u8 reserved_at_0[0x4];
e281682b 2632 u8 state[0x4];
b4ff3a36 2633 u8 reserved_at_8[0x18];
e281682b 2634
b4ff3a36 2635 u8 reserved_at_20[0x8];
e281682b
SM		 2636 u8 user_index[0x18];
2637
b4ff3a36 2638 u8 reserved_at_40[0x8];
e281682b
SM		 2639 u8 cqn[0x18];
2640
2641 u8 counter_set_id[0x8];
2642 u8 atomic_mode[0x4];
2643 u8 rre[0x1];
2644 u8 rwe[0x1];
2645 u8 rae[0x1];
2646 u8 atomic_like_write_en[0x1];
2647 u8 latency_sensitive[0x1];
2648 u8 rlky[0x1];
2649 u8 free_ar[0x1];
b4ff3a36 2650 u8 reserved_at_73[0xd];
e281682b 2651
b4ff3a36 2652 u8 reserved_at_80[0x8];
e281682b 2653 u8 cs_res[0x8];
b4ff3a36 2654 u8 reserved_at_90[0x3];
e281682b 2655 u8 min_rnr_nak[0x5];
b4ff3a36 2656 u8 reserved_at_98[0x8];
e281682b 2657
b4ff3a36 2658 u8 reserved_at_a0[0x8];
7486216b 2659 u8 srqn_xrqn[0x18];
e281682b 2660
b4ff3a36 2661 u8 reserved_at_c0[0x8];
e281682b
SM		 2662 u8 pd[0x18];
2663
2664 u8 tclass[0x8];
b4ff3a36 2665 u8 reserved_at_e8[0x4];
e281682b
SM		 2666 u8 flow_label[0x14];
2667
2668 u8 dc_access_key[0x40];
2669
b4ff3a36 2670 u8 reserved_at_140[0x5];
e281682b
SM		 2671 u8 mtu[0x3];
2672 u8 port[0x8];
2673 u8 pkey_index[0x10];
2674
b4ff3a36 2675 u8 reserved_at_160[0x8];
e281682b 2676 u8 my_addr_index[0x8];
b4ff3a36 2677 u8 reserved_at_170[0x8];
e281682b
SM		 2678 u8 hop_limit[0x8];
2679
2680 u8 dc_access_key_violation_count[0x20];
2681
b4ff3a36 2682 u8 reserved_at_1a0[0x14];
e281682b
SM		 2683 u8 dei_cfi[0x1];
2684 u8 eth_prio[0x3];
2685 u8 ecn[0x2];
2686 u8 dscp[0x6];
2687
b4ff3a36 2688 u8 reserved_at_1c0[0x40];
e281682b
SM		 2689};
2690
2691enum {
2692 MLX5_CQC_STATUS_OK = 0x0,
2693 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
2694 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
2695};
2696
2697enum {
2698 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
2699 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
2700};
2701
2702enum {
2703 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
2704 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
2705 MLX5_CQC_ST_FIRED = 0xa,
2706};
2707
7d5e1423
SM		 2708enum {
2709 MLX5_CQ_PERIOD_MODE_START_FROM_EQE = 0x0,
2710 MLX5_CQ_PERIOD_MODE_START_FROM_CQE = 0x1,
7486216b 2711 MLX5_CQ_PERIOD_NUM_MODES
7d5e1423
SM		 2712};
2713
e281682b
SM		 2714struct mlx5_ifc_cqc_bits {
2715 u8 status[0x4];
b4ff3a36 2716 u8 reserved_at_4[0x4];
e281682b
SM		 2717 u8 cqe_sz[0x3];
2718 u8 cc[0x1];
b4ff3a36 2719 u8 reserved_at_c[0x1];
e281682b
SM		 2720 u8 scqe_break_moderation_en[0x1];
2721 u8 oi[0x1];
7d5e1423
SM		 2722 u8 cq_period_mode[0x2];
2723 u8 cqe_comp_en[0x1];
e281682b
SM		 2724 u8 mini_cqe_res_format[0x2];
2725 u8 st[0x4];
b4ff3a36 2726 u8 reserved_at_18[0x8];
e281682b 2727
b4ff3a36 2728 u8 reserved_at_20[0x20];
e281682b 2729
b4ff3a36 2730 u8 reserved_at_40[0x14];
e281682b 2731 u8 page_offset[0x6];
b4ff3a36 2732 u8 reserved_at_5a[0x6];
e281682b 2733
b4ff3a36 2734 u8 reserved_at_60[0x3];
e281682b
SM		 2735 u8 log_cq_size[0x5];
2736 u8 uar_page[0x18];
2737
b4ff3a36 2738 u8 reserved_at_80[0x4];
e281682b
SM		 2739 u8 cq_period[0xc];
2740 u8 cq_max_count[0x10];
2741
b4ff3a36 2742 u8 reserved_at_a0[0x18];
e281682b
SM		 2743 u8 c_eqn[0x8];
2744
b4ff3a36 2745 u8 reserved_at_c0[0x3];
e281682b 2746 u8 log_page_size[0x5];
b4ff3a36 2747 u8 reserved_at_c8[0x18];
e281682b 2748
b4ff3a36 2749 u8 reserved_at_e0[0x20];
e281682b 2750
b4ff3a36 2751 u8 reserved_at_100[0x8];
e281682b
SM		 2752 u8 last_notified_index[0x18];
2753
b4ff3a36 2754 u8 reserved_at_120[0x8];
e281682b
SM		 2755 u8 last_solicit_index[0x18];
2756
b4ff3a36 2757 u8 reserved_at_140[0x8];
e281682b
SM		 2758 u8 consumer_counter[0x18];
2759
b4ff3a36 2760 u8 reserved_at_160[0x8];
e281682b
SM		 2761 u8 producer_counter[0x18];
2762
b4ff3a36 2763 u8 reserved_at_180[0x40];
e281682b
SM		 2764
2765 u8 dbr_addr[0x40];
2766};
2767
2768union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2769 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2770 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2771 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
b4ff3a36 2772 u8 reserved_at_0[0x800];
e281682b
SM		 2773};
2774
2775struct mlx5_ifc_query_adapter_param_block_bits {
b4ff3a36 2776 u8 reserved_at_0[0xc0];
e281682b 2777
b4ff3a36 2778 u8 reserved_at_c0[0x8];
211e6c80
MD		 2779 u8 ieee_vendor_id[0x18];
2780
b4ff3a36 2781 u8 reserved_at_e0[0x10];
e281682b
SM		 2782 u8 vsd_vendor_id[0x10];
2783
2784 u8 vsd[208][0x8];
2785
2786 u8 vsd_contd_psid[16][0x8];
2787};
2788
7486216b
SM		 2789enum {
2790 MLX5_XRQC_STATE_GOOD = 0x0,
2791 MLX5_XRQC_STATE_ERROR = 0x1,
2792};
2793
2794enum {
2795 MLX5_XRQC_TOPOLOGY_NO_SPECIAL_TOPOLOGY = 0x0,
2796 MLX5_XRQC_TOPOLOGY_TAG_MATCHING = 0x1,
2797};
2798
2799enum {
2800 MLX5_XRQC_OFFLOAD_RNDV = 0x1,
2801};
2802
2803struct mlx5_ifc_tag_matching_topology_context_bits {
2804 u8 log_matching_list_sz[0x4];
2805 u8 reserved_at_4[0xc];
2806 u8 append_next_index[0x10];
2807
2808 u8 sw_phase_cnt[0x10];
2809 u8 hw_phase_cnt[0x10];
2810
2811 u8 reserved_at_40[0x40];
2812};
2813
2814struct mlx5_ifc_xrqc_bits {
2815 u8 state[0x4];
2816 u8 rlkey[0x1];
2817 u8 reserved_at_5[0xf];
2818 u8 topology[0x4];
2819 u8 reserved_at_18[0x4];
2820 u8 offload[0x4];
2821
2822 u8 reserved_at_20[0x8];
2823 u8 user_index[0x18];
2824
2825 u8 reserved_at_40[0x8];
2826 u8 cqn[0x18];
2827
2828 u8 reserved_at_60[0xa0];
2829
2830 struct mlx5_ifc_tag_matching_topology_context_bits tag_matching_topology_context;
2831
2e353b34 2832 u8 reserved_at_180[0x200];
7486216b
SM		 2833
2834 struct mlx5_ifc_wq_bits wq;
2835};
2836
e281682b
SM		 2837union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2838 struct mlx5_ifc_modify_field_select_bits modify_field_select;
2839 struct mlx5_ifc_resize_field_select_bits resize_field_select;
b4ff3a36 2840 u8 reserved_at_0[0x20];
e281682b
SM		 2841};
2842
2843union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2844 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2845 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2846 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
b4ff3a36 2847 u8 reserved_at_0[0x20];
e281682b
SM		 2848};
2849
2850union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
2851 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
2852 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
2853 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
2854 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
2855 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
2856 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
2857 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
1c64bf6f 2858 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b 2859 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
b4ff3a36 2860 u8 reserved_at_0[0x7c0];
e281682b
SM		 2861};
2862
2863union mlx5_ifc_event_auto_bits {
2864 struct mlx5_ifc_comp_event_bits comp_event;
2865 struct mlx5_ifc_dct_events_bits dct_events;
2866 struct mlx5_ifc_qp_events_bits qp_events;
2867 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
2868 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
2869 struct mlx5_ifc_cq_error_bits cq_error;
2870 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
2871 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
2872 struct mlx5_ifc_gpio_event_bits gpio_event;
2873 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
2874 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
2875 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
b4ff3a36 2876 u8 reserved_at_0[0xe0];
e281682b
SM		 2877};
2878
2879struct mlx5_ifc_health_buffer_bits {
b4ff3a36 2880 u8 reserved_at_0[0x100];
e281682b
SM		 2881
2882 u8 assert_existptr[0x20];
2883
2884 u8 assert_callra[0x20];
2885
b4ff3a36 2886 u8 reserved_at_140[0x40];
e281682b
SM		 2887
2888 u8 fw_version[0x20];
2889
2890 u8 hw_id[0x20];
2891
b4ff3a36 2892 u8 reserved_at_1c0[0x20];
e281682b
SM		 2893
2894 u8 irisc_index[0x8];
2895 u8 synd[0x8];
2896 u8 ext_synd[0x10];
2897};
2898
2899struct mlx5_ifc_register_loopback_control_bits {
2900 u8 no_lb[0x1];
b4ff3a36 2901 u8 reserved_at_1[0x7];
e281682b 2902 u8 port[0x8];
b4ff3a36 2903 u8 reserved_at_10[0x10];
e281682b 2904
b4ff3a36 2905 u8 reserved_at_20[0x60];
e281682b
SM		 2906};
2907
2908struct mlx5_ifc_teardown_hca_out_bits {
2909 u8 status[0x8];
b4ff3a36 2910 u8 reserved_at_8[0x18];
e281682b
SM		 2911
2912 u8 syndrome[0x20];
2913
b4ff3a36 2914 u8 reserved_at_40[0x40];
e281682b
SM		 2915};
2916
2917enum {
2918 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
2919 MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE = 0x1,
2920};
2921
2922struct mlx5_ifc_teardown_hca_in_bits {
2923 u8 opcode[0x10];
b4ff3a36 2924 u8 reserved_at_10[0x10];
e281682b 2925
b4ff3a36 2926 u8 reserved_at_20[0x10];
e281682b
SM		 2927 u8 op_mod[0x10];
2928
b4ff3a36 2929 u8 reserved_at_40[0x10];
e281682b
SM		 2930 u8 profile[0x10];
2931
b4ff3a36 2932 u8 reserved_at_60[0x20];
e281682b
SM		 2933};
2934
2935struct mlx5_ifc_sqerr2rts_qp_out_bits {
2936 u8 status[0x8];
b4ff3a36 2937 u8 reserved_at_8[0x18];
e281682b
SM		 2938
2939 u8 syndrome[0x20];
2940
b4ff3a36 2941 u8 reserved_at_40[0x40];
e281682b
SM		 2942};
2943
2944struct mlx5_ifc_sqerr2rts_qp_in_bits {
2945 u8 opcode[0x10];
b4ff3a36 2946 u8 reserved_at_10[0x10];
e281682b 2947
b4ff3a36 2948 u8 reserved_at_20[0x10];
e281682b
SM		 2949 u8 op_mod[0x10];
2950
b4ff3a36 2951 u8 reserved_at_40[0x8];
e281682b
SM		 2952 u8 qpn[0x18];
2953
b4ff3a36 2954 u8 reserved_at_60[0x20];
e281682b
SM		 2955
2956 u8 opt_param_mask[0x20];
2957
b4ff3a36 2958 u8 reserved_at_a0[0x20];
e281682b
SM		 2959
2960 struct mlx5_ifc_qpc_bits qpc;
2961
b4ff3a36 2962 u8 reserved_at_800[0x80];
e281682b
SM		 2963};
2964
2965struct mlx5_ifc_sqd2rts_qp_out_bits {
2966 u8 status[0x8];
b4ff3a36 2967 u8 reserved_at_8[0x18];
e281682b
SM		 2968
2969 u8 syndrome[0x20];
2970
b4ff3a36 2971 u8 reserved_at_40[0x40];
e281682b
SM		 2972};
2973
2974struct mlx5_ifc_sqd2rts_qp_in_bits {
2975 u8 opcode[0x10];
b4ff3a36 2976 u8 reserved_at_10[0x10];
e281682b 2977
b4ff3a36 2978 u8 reserved_at_20[0x10];
e281682b
SM		 2979 u8 op_mod[0x10];
2980
b4ff3a36 2981 u8 reserved_at_40[0x8];
e281682b
SM		 2982 u8 qpn[0x18];
2983
b4ff3a36 2984 u8 reserved_at_60[0x20];
e281682b
SM		 2985
2986 u8 opt_param_mask[0x20];
2987
b4ff3a36 2988 u8 reserved_at_a0[0x20];
e281682b
SM		 2989
2990 struct mlx5_ifc_qpc_bits qpc;
2991
b4ff3a36 2992 u8 reserved_at_800[0x80];
e281682b
SM		 2993};
2994
2995struct mlx5_ifc_set_roce_address_out_bits {
2996 u8 status[0x8];
b4ff3a36 2997 u8 reserved_at_8[0x18];
e281682b
SM		 2998
2999 u8 syndrome[0x20];
3000
b4ff3a36 3001 u8 reserved_at_40[0x40];
e281682b
SM		 3002};
3003
3004struct mlx5_ifc_set_roce_address_in_bits {
3005 u8 opcode[0x10];
b4ff3a36 3006 u8 reserved_at_10[0x10];
e281682b 3007
b4ff3a36 3008 u8 reserved_at_20[0x10];
e281682b
SM		 3009 u8 op_mod[0x10];
3010
3011 u8 roce_address_index[0x10];
b4ff3a36 3012 u8 reserved_at_50[0x10];
e281682b 3013
b4ff3a36 3014 u8 reserved_at_60[0x20];
e281682b
SM		 3015
3016 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3017};
3018
3019struct mlx5_ifc_set_mad_demux_out_bits {
3020 u8 status[0x8];
b4ff3a36 3021 u8 reserved_at_8[0x18];
e281682b
SM		 3022
3023 u8 syndrome[0x20];
3024
b4ff3a36 3025 u8 reserved_at_40[0x40];
e281682b
SM		 3026};
3027
3028enum {
3029 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
3030 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
3031};
3032
3033struct mlx5_ifc_set_mad_demux_in_bits {
3034 u8 opcode[0x10];
b4ff3a36 3035 u8 reserved_at_10[0x10];
e281682b 3036
b4ff3a36 3037 u8 reserved_at_20[0x10];
e281682b
SM		 3038 u8 op_mod[0x10];
3039
b4ff3a36 3040 u8 reserved_at_40[0x20];
e281682b 3041
b4ff3a36 3042 u8 reserved_at_60[0x6];
e281682b 3043 u8 demux_mode[0x2];
b4ff3a36 3044 u8 reserved_at_68[0x18];
e281682b
SM		 3045};
3046
3047struct mlx5_ifc_set_l2_table_entry_out_bits {
3048 u8 status[0x8];
b4ff3a36 3049 u8 reserved_at_8[0x18];
e281682b
SM		 3050
3051 u8 syndrome[0x20];
3052
b4ff3a36 3053 u8 reserved_at_40[0x40];
e281682b
SM		 3054};
3055
3056struct mlx5_ifc_set_l2_table_entry_in_bits {
3057 u8 opcode[0x10];
b4ff3a36 3058 u8 reserved_at_10[0x10];
e281682b 3059
b4ff3a36 3060 u8 reserved_at_20[0x10];
e281682b
SM		 3061 u8 op_mod[0x10];
3062
b4ff3a36 3063 u8 reserved_at_40[0x60];
e281682b 3064
b4ff3a36 3065 u8 reserved_at_a0[0x8];
e281682b
SM		 3066 u8 table_index[0x18];
3067
b4ff3a36 3068 u8 reserved_at_c0[0x20];
e281682b 3069
b4ff3a36 3070 u8 reserved_at_e0[0x13];
e281682b
SM		 3071 u8 vlan_valid[0x1];
3072 u8 vlan[0xc];
3073
3074 struct mlx5_ifc_mac_address_layout_bits mac_address;
3075
b4ff3a36 3076 u8 reserved_at_140[0xc0];
e281682b
SM		 3077};
3078
3079struct mlx5_ifc_set_issi_out_bits {
3080 u8 status[0x8];
b4ff3a36 3081 u8 reserved_at_8[0x18];
e281682b
SM		 3082
3083 u8 syndrome[0x20];
3084
b4ff3a36 3085 u8 reserved_at_40[0x40];
e281682b
SM		 3086};
3087
3088struct mlx5_ifc_set_issi_in_bits {
3089 u8 opcode[0x10];
b4ff3a36 3090 u8 reserved_at_10[0x10];
e281682b 3091
b4ff3a36 3092 u8 reserved_at_20[0x10];
e281682b
SM		 3093 u8 op_mod[0x10];
3094
b4ff3a36 3095 u8 reserved_at_40[0x10];
e281682b
SM		 3096 u8 current_issi[0x10];
3097
b4ff3a36 3098 u8 reserved_at_60[0x20];
e281682b
SM		 3099};
3100
3101struct mlx5_ifc_set_hca_cap_out_bits {
3102 u8 status[0x8];
b4ff3a36 3103 u8 reserved_at_8[0x18];
e281682b
SM		 3104
3105 u8 syndrome[0x20];
3106
b4ff3a36 3107 u8 reserved_at_40[0x40];
e281682b
SM		 3108};
3109
3110struct mlx5_ifc_set_hca_cap_in_bits {
3111 u8 opcode[0x10];
b4ff3a36 3112 u8 reserved_at_10[0x10];
e281682b 3113
b4ff3a36 3114 u8 reserved_at_20[0x10];
e281682b
SM		 3115 u8 op_mod[0x10];
3116
b4ff3a36 3117 u8 reserved_at_40[0x40];
e281682b
SM		 3118
3119 union mlx5_ifc_hca_cap_union_bits capability;
3120};
3121
26a81453
MG		 3122enum {
3123 MLX5_SET_FTE_MODIFY_ENABLE_MASK_ACTION = 0x0,
3124 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_TAG = 0x1,
3125 MLX5_SET_FTE_MODIFY_ENABLE_MASK_DESTINATION_LIST = 0x2,
3126 MLX5_SET_FTE_MODIFY_ENABLE_MASK_FLOW_COUNTERS = 0x3
3127};
3128
e281682b
SM		 3129struct mlx5_ifc_set_fte_out_bits {
3130 u8 status[0x8];
b4ff3a36 3131 u8 reserved_at_8[0x18];
e281682b
SM		 3132
3133 u8 syndrome[0x20];
3134
b4ff3a36 3135 u8 reserved_at_40[0x40];
e281682b
SM		 3136};
3137
3138struct mlx5_ifc_set_fte_in_bits {
3139 u8 opcode[0x10];
b4ff3a36 3140 u8 reserved_at_10[0x10];
e281682b 3141
b4ff3a36 3142 u8 reserved_at_20[0x10];
e281682b
SM		 3143 u8 op_mod[0x10];
3144
7d5e1423
SM		 3145 u8 other_vport[0x1];
3146 u8 reserved_at_41[0xf];
3147 u8 vport_number[0x10];
3148
3149 u8 reserved_at_60[0x20];
e281682b
SM		 3150
3151 u8 table_type[0x8];
b4ff3a36 3152 u8 reserved_at_88[0x18];
e281682b 3153
b4ff3a36 3154 u8 reserved_at_a0[0x8];
e281682b
SM		 3155 u8 table_id[0x18];
3156
b4ff3a36 3157 u8 reserved_at_c0[0x18];
26a81453
MG		 3158 u8 modify_enable_mask[0x8];
3159
b4ff3a36 3160 u8 reserved_at_e0[0x20];
e281682b
SM		 3161
3162 u8 flow_index[0x20];
3163
b4ff3a36 3164 u8 reserved_at_120[0xe0];
e281682b
SM		 3165
3166 struct mlx5_ifc_flow_context_bits flow_context;
3167};
3168
3169struct mlx5_ifc_rts2rts_qp_out_bits {
3170 u8 status[0x8];
b4ff3a36 3171 u8 reserved_at_8[0x18];
e281682b
SM		 3172
3173 u8 syndrome[0x20];
3174
b4ff3a36 3175 u8 reserved_at_40[0x40];
e281682b
SM		 3176};
3177
3178struct mlx5_ifc_rts2rts_qp_in_bits {
3179 u8 opcode[0x10];
b4ff3a36 3180 u8 reserved_at_10[0x10];
e281682b 3181
b4ff3a36 3182 u8 reserved_at_20[0x10];
e281682b
SM		 3183 u8 op_mod[0x10];
3184
b4ff3a36 3185 u8 reserved_at_40[0x8];
e281682b
SM		 3186 u8 qpn[0x18];
3187
b4ff3a36 3188 u8 reserved_at_60[0x20];
e281682b
SM		 3189
3190 u8 opt_param_mask[0x20];
3191
b4ff3a36 3192 u8 reserved_at_a0[0x20];
e281682b
SM		 3193
3194 struct mlx5_ifc_qpc_bits qpc;
3195
b4ff3a36 3196 u8 reserved_at_800[0x80];
e281682b
SM		 3197};
3198
3199struct mlx5_ifc_rtr2rts_qp_out_bits {
3200 u8 status[0x8];
b4ff3a36 3201 u8 reserved_at_8[0x18];
e281682b
SM		 3202
3203 u8 syndrome[0x20];
3204
b4ff3a36 3205 u8 reserved_at_40[0x40];
e281682b
SM		 3206};
3207
3208struct mlx5_ifc_rtr2rts_qp_in_bits {
3209 u8 opcode[0x10];
b4ff3a36 3210 u8 reserved_at_10[0x10];
e281682b 3211
b4ff3a36 3212 u8 reserved_at_20[0x10];
e281682b
SM		 3213 u8 op_mod[0x10];
3214
b4ff3a36 3215 u8 reserved_at_40[0x8];
e281682b
SM		 3216 u8 qpn[0x18];
3217
b4ff3a36 3218 u8 reserved_at_60[0x20];
e281682b
SM		 3219
3220 u8 opt_param_mask[0x20];
3221
b4ff3a36 3222 u8 reserved_at_a0[0x20];
e281682b
SM		 3223
3224 struct mlx5_ifc_qpc_bits qpc;
3225
b4ff3a36 3226 u8 reserved_at_800[0x80];
e281682b
SM		 3227};
3228
3229struct mlx5_ifc_rst2init_qp_out_bits {
3230 u8 status[0x8];
b4ff3a36 3231 u8 reserved_at_8[0x18];
e281682b
SM		 3232
3233 u8 syndrome[0x20];
3234
b4ff3a36 3235 u8 reserved_at_40[0x40];
e281682b
SM		 3236};
3237
3238struct mlx5_ifc_rst2init_qp_in_bits {
3239 u8 opcode[0x10];
b4ff3a36 3240 u8 reserved_at_10[0x10];
e281682b 3241
b4ff3a36 3242 u8 reserved_at_20[0x10];
e281682b
SM		 3243 u8 op_mod[0x10];
3244
b4ff3a36 3245 u8 reserved_at_40[0x8];
e281682b
SM		 3246 u8 qpn[0x18];
3247
b4ff3a36 3248 u8 reserved_at_60[0x20];
e281682b
SM		 3249
3250 u8 opt_param_mask[0x20];
3251
b4ff3a36 3252 u8 reserved_at_a0[0x20];
e281682b
SM		 3253
3254 struct mlx5_ifc_qpc_bits qpc;
3255
b4ff3a36 3256 u8 reserved_at_800[0x80];
e281682b
SM		 3257};
3258
7486216b
SM		 3259struct mlx5_ifc_query_xrq_out_bits {
3260 u8 status[0x8];
3261 u8 reserved_at_8[0x18];
3262
3263 u8 syndrome[0x20];
3264
3265 u8 reserved_at_40[0x40];
3266
3267 struct mlx5_ifc_xrqc_bits xrq_context;
3268};
3269
3270struct mlx5_ifc_query_xrq_in_bits {
3271 u8 opcode[0x10];
3272 u8 reserved_at_10[0x10];
3273
3274 u8 reserved_at_20[0x10];
3275 u8 op_mod[0x10];
3276
3277 u8 reserved_at_40[0x8];
3278 u8 xrqn[0x18];
3279
3280 u8 reserved_at_60[0x20];
3281};
3282
e281682b
SM		 3283struct mlx5_ifc_query_xrc_srq_out_bits {
3284 u8 status[0x8];
b4ff3a36 3285 u8 reserved_at_8[0x18];
e281682b
SM		 3286
3287 u8 syndrome[0x20];
3288
b4ff3a36 3289 u8 reserved_at_40[0x40];
e281682b
SM		 3290
3291 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
3292
b4ff3a36 3293 u8 reserved_at_280[0x600];
e281682b
SM		 3294
3295 u8 pas[0][0x40];
3296};
3297
3298struct mlx5_ifc_query_xrc_srq_in_bits {
3299 u8 opcode[0x10];
b4ff3a36 3300 u8 reserved_at_10[0x10];
e281682b 3301
b4ff3a36 3302 u8 reserved_at_20[0x10];
e281682b
SM		 3303 u8 op_mod[0x10];
3304
b4ff3a36 3305 u8 reserved_at_40[0x8];
e281682b
SM		 3306 u8 xrc_srqn[0x18];
3307
b4ff3a36 3308 u8 reserved_at_60[0x20];
e281682b
SM		 3309};
3310
3311enum {
3312 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
3313 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
3314};
3315
3316struct mlx5_ifc_query_vport_state_out_bits {
3317 u8 status[0x8];
b4ff3a36 3318 u8 reserved_at_8[0x18];
e281682b
SM		 3319
3320 u8 syndrome[0x20];
3321
b4ff3a36 3322 u8 reserved_at_40[0x20];
e281682b 3323
b4ff3a36 3324 u8 reserved_at_60[0x18];
e281682b
SM		 3325 u8 admin_state[0x4];
3326 u8 state[0x4];
3327};
3328
3329enum {
3330 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0,
e7546514 3331 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_ESW_VPORT = 0x1,
e281682b
SM		 3332};
3333
3334struct mlx5_ifc_query_vport_state_in_bits {
3335 u8 opcode[0x10];
b4ff3a36 3336 u8 reserved_at_10[0x10];
e281682b 3337
b4ff3a36 3338 u8 reserved_at_20[0x10];
e281682b
SM		 3339 u8 op_mod[0x10];
3340
3341 u8 other_vport[0x1];
b4ff3a36 3342 u8 reserved_at_41[0xf];
e281682b
SM		 3343 u8 vport_number[0x10];
3344
b4ff3a36 3345 u8 reserved_at_60[0x20];
e281682b
SM		 3346};
3347
3348struct mlx5_ifc_query_vport_counter_out_bits {
3349 u8 status[0x8];
b4ff3a36 3350 u8 reserved_at_8[0x18];
e281682b
SM		 3351
3352 u8 syndrome[0x20];
3353
b4ff3a36 3354 u8 reserved_at_40[0x40];
e281682b
SM		 3355
3356 struct mlx5_ifc_traffic_counter_bits received_errors;
3357
3358 struct mlx5_ifc_traffic_counter_bits transmit_errors;
3359
3360 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
3361
3362 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
3363
3364 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
3365
3366 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
3367
3368 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
3369
3370 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
3371
3372 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
3373
3374 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
3375
3376 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
3377
3378 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
3379
b4ff3a36 3380 u8 reserved_at_680[0xa00];
e281682b
SM		 3381};
3382
3383enum {
3384 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
3385};
3386
3387struct mlx5_ifc_query_vport_counter_in_bits {
3388 u8 opcode[0x10];
b4ff3a36 3389 u8 reserved_at_10[0x10];
e281682b 3390
b4ff3a36 3391 u8 reserved_at_20[0x10];
e281682b
SM		 3392 u8 op_mod[0x10];
3393
3394 u8 other_vport[0x1];
b54ba277
MY		 3395 u8 reserved_at_41[0xb];
3396 u8 port_num[0x4];
e281682b
SM		 3397 u8 vport_number[0x10];
3398
b4ff3a36 3399 u8 reserved_at_60[0x60];
e281682b
SM		 3400
3401 u8 clear[0x1];
b4ff3a36 3402 u8 reserved_at_c1[0x1f];
e281682b 3403
b4ff3a36 3404 u8 reserved_at_e0[0x20];
e281682b
SM		 3405};
3406
3407struct mlx5_ifc_query_tis_out_bits {
3408 u8 status[0x8];
b4ff3a36 3409 u8 reserved_at_8[0x18];
e281682b
SM		 3410
3411 u8 syndrome[0x20];
3412
b4ff3a36 3413 u8 reserved_at_40[0x40];
e281682b
SM		 3414
3415 struct mlx5_ifc_tisc_bits tis_context;
3416};
3417
3418struct mlx5_ifc_query_tis_in_bits {
3419 u8 opcode[0x10];
b4ff3a36 3420 u8 reserved_at_10[0x10];
e281682b 3421
b4ff3a36 3422 u8 reserved_at_20[0x10];
e281682b
SM		 3423 u8 op_mod[0x10];
3424
b4ff3a36 3425 u8 reserved_at_40[0x8];
e281682b
SM		 3426 u8 tisn[0x18];
3427
b4ff3a36 3428 u8 reserved_at_60[0x20];
e281682b
SM		 3429};
3430
3431struct mlx5_ifc_query_tir_out_bits {
3432 u8 status[0x8];
b4ff3a36 3433 u8 reserved_at_8[0x18];
e281682b
SM		 3434
3435 u8 syndrome[0x20];
3436
b4ff3a36 3437 u8 reserved_at_40[0xc0];
e281682b
SM		 3438
3439 struct mlx5_ifc_tirc_bits tir_context;
3440};
3441
3442struct mlx5_ifc_query_tir_in_bits {
3443 u8 opcode[0x10];
b4ff3a36 3444 u8 reserved_at_10[0x10];
e281682b 3445
b4ff3a36 3446 u8 reserved_at_20[0x10];
e281682b
SM		 3447 u8 op_mod[0x10];
3448
b4ff3a36 3449 u8 reserved_at_40[0x8];
e281682b
SM		 3450 u8 tirn[0x18];
3451
b4ff3a36 3452 u8 reserved_at_60[0x20];
e281682b
SM		 3453};
3454
3455struct mlx5_ifc_query_srq_out_bits {
3456 u8 status[0x8];
b4ff3a36 3457 u8 reserved_at_8[0x18];
e281682b
SM		 3458
3459 u8 syndrome[0x20];
3460
b4ff3a36 3461 u8 reserved_at_40[0x40];
e281682b
SM		 3462
3463 struct mlx5_ifc_srqc_bits srq_context_entry;
3464
b4ff3a36 3465 u8 reserved_at_280[0x600];
e281682b
SM		 3466
3467 u8 pas[0][0x40];
3468};
3469
3470struct mlx5_ifc_query_srq_in_bits {
3471 u8 opcode[0x10];
b4ff3a36 3472 u8 reserved_at_10[0x10];
e281682b 3473
b4ff3a36 3474 u8 reserved_at_20[0x10];
e281682b
SM		 3475 u8 op_mod[0x10];
3476
b4ff3a36 3477 u8 reserved_at_40[0x8];
e281682b
SM		 3478 u8 srqn[0x18];
3479
b4ff3a36 3480 u8 reserved_at_60[0x20];
e281682b
SM		 3481};
3482
3483struct mlx5_ifc_query_sq_out_bits {
3484 u8 status[0x8];
b4ff3a36 3485 u8 reserved_at_8[0x18];
e281682b
SM		 3486
3487 u8 syndrome[0x20];
3488
b4ff3a36 3489 u8 reserved_at_40[0xc0];
e281682b
SM		 3490
3491 struct mlx5_ifc_sqc_bits sq_context;
3492};
3493
3494struct mlx5_ifc_query_sq_in_bits {
3495 u8 opcode[0x10];
b4ff3a36 3496 u8 reserved_at_10[0x10];
e281682b 3497
b4ff3a36 3498 u8 reserved_at_20[0x10];
e281682b
SM		 3499 u8 op_mod[0x10];
3500
b4ff3a36 3501 u8 reserved_at_40[0x8];
e281682b
SM		 3502 u8 sqn[0x18];
3503
b4ff3a36 3504 u8 reserved_at_60[0x20];
e281682b
SM		 3505};
3506
3507struct mlx5_ifc_query_special_contexts_out_bits {
3508 u8 status[0x8];
b4ff3a36 3509 u8 reserved_at_8[0x18];
e281682b
SM		 3510
3511 u8 syndrome[0x20];
3512
ec22eb53 3513 u8 dump_fill_mkey[0x20];
e281682b
SM		 3514
3515 u8 resd_lkey[0x20];
3516};
3517
3518struct mlx5_ifc_query_special_contexts_in_bits {
3519 u8 opcode[0x10];
b4ff3a36 3520 u8 reserved_at_10[0x10];
e281682b 3521
b4ff3a36 3522 u8 reserved_at_20[0x10];
e281682b
SM		 3523 u8 op_mod[0x10];
3524
b4ff3a36 3525 u8 reserved_at_40[0x40];
e281682b
SM		 3526};
3527
3528struct mlx5_ifc_query_rqt_out_bits {
3529 u8 status[0x8];
b4ff3a36 3530 u8 reserved_at_8[0x18];
e281682b
SM		 3531
3532 u8 syndrome[0x20];
3533
b4ff3a36 3534 u8 reserved_at_40[0xc0];
e281682b
SM		 3535
3536 struct mlx5_ifc_rqtc_bits rqt_context;
3537};
3538
3539struct mlx5_ifc_query_rqt_in_bits {
3540 u8 opcode[0x10];
b4ff3a36 3541 u8 reserved_at_10[0x10];
e281682b 3542
b4ff3a36 3543 u8 reserved_at_20[0x10];
e281682b
SM		 3544 u8 op_mod[0x10];
3545
b4ff3a36 3546 u8 reserved_at_40[0x8];
e281682b
SM		 3547 u8 rqtn[0x18];
3548
b4ff3a36 3549 u8 reserved_at_60[0x20];
e281682b
SM		 3550};
3551
3552struct mlx5_ifc_query_rq_out_bits {
3553 u8 status[0x8];
b4ff3a36 3554 u8 reserved_at_8[0x18];
e281682b
SM		 3555
3556 u8 syndrome[0x20];
3557
b4ff3a36 3558 u8 reserved_at_40[0xc0];
e281682b
SM		 3559
3560 struct mlx5_ifc_rqc_bits rq_context;
3561};
3562
3563struct mlx5_ifc_query_rq_in_bits {
3564 u8 opcode[0x10];
b4ff3a36 3565 u8 reserved_at_10[0x10];
e281682b 3566
b4ff3a36 3567 u8 reserved_at_20[0x10];
e281682b
SM		 3568 u8 op_mod[0x10];
3569
b4ff3a36 3570 u8 reserved_at_40[0x8];
e281682b
SM		 3571 u8 rqn[0x18];
3572
b4ff3a36 3573 u8 reserved_at_60[0x20];
e281682b
SM		 3574};
3575
3576struct mlx5_ifc_query_roce_address_out_bits {
3577 u8 status[0x8];
b4ff3a36 3578 u8 reserved_at_8[0x18];
e281682b
SM		 3579
3580 u8 syndrome[0x20];
3581
b4ff3a36 3582 u8 reserved_at_40[0x40];
e281682b
SM		 3583
3584 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3585};
3586
3587struct mlx5_ifc_query_roce_address_in_bits {
3588 u8 opcode[0x10];
b4ff3a36 3589 u8 reserved_at_10[0x10];
e281682b 3590
b4ff3a36 3591 u8 reserved_at_20[0x10];
e281682b
SM		 3592 u8 op_mod[0x10];
3593
3594 u8 roce_address_index[0x10];
b4ff3a36 3595 u8 reserved_at_50[0x10];
e281682b 3596
b4ff3a36 3597 u8 reserved_at_60[0x20];
e281682b
SM		 3598};
3599
3600struct mlx5_ifc_query_rmp_out_bits {
3601 u8 status[0x8];
b4ff3a36 3602 u8 reserved_at_8[0x18];
e281682b
SM		 3603
3604 u8 syndrome[0x20];
3605
b4ff3a36 3606 u8 reserved_at_40[0xc0];
e281682b
SM		 3607
3608 struct mlx5_ifc_rmpc_bits rmp_context;
3609};
3610
3611struct mlx5_ifc_query_rmp_in_bits {
3612 u8 opcode[0x10];
b4ff3a36 3613 u8 reserved_at_10[0x10];
e281682b 3614
b4ff3a36 3615 u8 reserved_at_20[0x10];
e281682b
SM		 3616 u8 op_mod[0x10];
3617
b4ff3a36 3618 u8 reserved_at_40[0x8];
e281682b
SM		 3619 u8 rmpn[0x18];
3620
b4ff3a36 3621 u8 reserved_at_60[0x20];
e281682b
SM		 3622};
3623
3624struct mlx5_ifc_query_qp_out_bits {
3625 u8 status[0x8];
b4ff3a36 3626 u8 reserved_at_8[0x18];
e281682b
SM		 3627
3628 u8 syndrome[0x20];
3629
b4ff3a36 3630 u8 reserved_at_40[0x40];
e281682b
SM		 3631
3632 u8 opt_param_mask[0x20];
3633
b4ff3a36 3634 u8 reserved_at_a0[0x20];
e281682b
SM		 3635
3636 struct mlx5_ifc_qpc_bits qpc;
3637
b4ff3a36 3638 u8 reserved_at_800[0x80];
e281682b
SM		 3639
3640 u8 pas[0][0x40];
3641};
3642
3643struct mlx5_ifc_query_qp_in_bits {
3644 u8 opcode[0x10];
b4ff3a36 3645 u8 reserved_at_10[0x10];
e281682b 3646
b4ff3a36 3647 u8 reserved_at_20[0x10];
e281682b
SM		 3648 u8 op_mod[0x10];
3649
b4ff3a36 3650 u8 reserved_at_40[0x8];
e281682b
SM		 3651 u8 qpn[0x18];
3652
b4ff3a36 3653 u8 reserved_at_60[0x20];
e281682b
SM		 3654};
3655
3656struct mlx5_ifc_query_q_counter_out_bits {
3657 u8 status[0x8];
b4ff3a36 3658 u8 reserved_at_8[0x18];
e281682b
SM		 3659
3660 u8 syndrome[0x20];
3661
b4ff3a36 3662 u8 reserved_at_40[0x40];
e281682b
SM		 3663
3664 u8 rx_write_requests[0x20];
3665
b4ff3a36 3666 u8 reserved_at_a0[0x20];
e281682b
SM		 3667
3668 u8 rx_read_requests[0x20];
3669
b4ff3a36 3670 u8 reserved_at_e0[0x20];
e281682b
SM		 3671
3672 u8 rx_atomic_requests[0x20];
3673
b4ff3a36 3674 u8 reserved_at_120[0x20];
e281682b
SM		 3675
3676 u8 rx_dct_connect[0x20];
3677
b4ff3a36 3678 u8 reserved_at_160[0x20];
e281682b
SM		 3679
3680 u8 out_of_buffer[0x20];
3681
b4ff3a36 3682 u8 reserved_at_1a0[0x20];
e281682b
SM		 3683
3684 u8 out_of_sequence[0x20];
3685
7486216b
SM		 3686 u8 reserved_at_1e0[0x20];
3687
3688 u8 duplicate_request[0x20];
3689
3690 u8 reserved_at_220[0x20];
3691
3692 u8 rnr_nak_retry_err[0x20];
3693
3694 u8 reserved_at_260[0x20];
3695
3696 u8 packet_seq_err[0x20];
3697
3698 u8 reserved_at_2a0[0x20];
3699
3700 u8 implied_nak_seq_err[0x20];
3701
3702 u8 reserved_at_2e0[0x20];
3703
3704 u8 local_ack_timeout_err[0x20];
3705
3706 u8 reserved_at_320[0x4e0];
e281682b
SM		 3707};
3708
3709struct mlx5_ifc_query_q_counter_in_bits {
3710 u8 opcode[0x10];
b4ff3a36 3711 u8 reserved_at_10[0x10];
e281682b 3712
b4ff3a36 3713 u8 reserved_at_20[0x10];
e281682b
SM		 3714 u8 op_mod[0x10];
3715
b4ff3a36 3716 u8 reserved_at_40[0x80];
e281682b
SM		 3717
3718 u8 clear[0x1];
b4ff3a36 3719 u8 reserved_at_c1[0x1f];
e281682b 3720
b4ff3a36 3721 u8 reserved_at_e0[0x18];
e281682b
SM		 3722 u8 counter_set_id[0x8];
3723};
3724
3725struct mlx5_ifc_query_pages_out_bits {
3726 u8 status[0x8];
b4ff3a36 3727 u8 reserved_at_8[0x18];
e281682b
SM		 3728
3729 u8 syndrome[0x20];
3730
b4ff3a36 3731 u8 reserved_at_40[0x10];
e281682b
SM		 3732 u8 function_id[0x10];
3733
3734 u8 num_pages[0x20];
3735};
3736
3737enum {
3738 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
3739 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
3740 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
3741};
3742
3743struct mlx5_ifc_query_pages_in_bits {
3744 u8 opcode[0x10];
b4ff3a36 3745 u8 reserved_at_10[0x10];
e281682b 3746
b4ff3a36 3747 u8 reserved_at_20[0x10];
e281682b
SM		 3748 u8 op_mod[0x10];
3749
b4ff3a36 3750 u8 reserved_at_40[0x10];
e281682b
SM		 3751 u8 function_id[0x10];
3752
b4ff3a36 3753 u8 reserved_at_60[0x20];
e281682b
SM		 3754};
3755
3756struct mlx5_ifc_query_nic_vport_context_out_bits {
3757 u8 status[0x8];
b4ff3a36 3758 u8 reserved_at_8[0x18];
e281682b
SM		 3759
3760 u8 syndrome[0x20];
3761
b4ff3a36 3762 u8 reserved_at_40[0x40];
e281682b
SM		 3763
3764 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
3765};
3766
3767struct mlx5_ifc_query_nic_vport_context_in_bits {
3768 u8 opcode[0x10];
b4ff3a36 3769 u8 reserved_at_10[0x10];
e281682b 3770
b4ff3a36 3771 u8 reserved_at_20[0x10];
e281682b
SM		 3772 u8 op_mod[0x10];
3773
3774 u8 other_vport[0x1];
b4ff3a36 3775 u8 reserved_at_41[0xf];
e281682b
SM		 3776 u8 vport_number[0x10];
3777
b4ff3a36 3778 u8 reserved_at_60[0x5];
e281682b 3779 u8 allowed_list_type[0x3];
b4ff3a36 3780 u8 reserved_at_68[0x18];
e281682b
SM		 3781};
3782
3783struct mlx5_ifc_query_mkey_out_bits {
3784 u8 status[0x8];
b4ff3a36 3785 u8 reserved_at_8[0x18];
e281682b
SM		 3786
3787 u8 syndrome[0x20];
3788
b4ff3a36 3789 u8 reserved_at_40[0x40];
e281682b
SM		 3790
3791 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
3792
b4ff3a36 3793 u8 reserved_at_280[0x600];
e281682b
SM		 3794
3795 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
3796
3797 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
3798};
3799
3800struct mlx5_ifc_query_mkey_in_bits {
3801 u8 opcode[0x10];
b4ff3a36 3802 u8 reserved_at_10[0x10];
e281682b 3803
b4ff3a36 3804 u8 reserved_at_20[0x10];
e281682b
SM		 3805 u8 op_mod[0x10];
3806
b4ff3a36 3807 u8 reserved_at_40[0x8];
e281682b
SM		 3808 u8 mkey_index[0x18];
3809
3810 u8 pg_access[0x1];
b4ff3a36 3811 u8 reserved_at_61[0x1f];
e281682b
SM		 3812};
3813
3814struct mlx5_ifc_query_mad_demux_out_bits {
3815 u8 status[0x8];
b4ff3a36 3816 u8 reserved_at_8[0x18];
e281682b
SM		 3817
3818 u8 syndrome[0x20];
3819
b4ff3a36 3820 u8 reserved_at_40[0x40];
e281682b
SM		 3821
3822 u8 mad_dumux_parameters_block[0x20];
3823};
3824
3825struct mlx5_ifc_query_mad_demux_in_bits {
3826 u8 opcode[0x10];
b4ff3a36 3827 u8 reserved_at_10[0x10];
e281682b 3828
b4ff3a36 3829 u8 reserved_at_20[0x10];
e281682b
SM		 3830 u8 op_mod[0x10];
3831
b4ff3a36 3832 u8 reserved_at_40[0x40];
e281682b
SM		 3833};
3834
3835struct mlx5_ifc_query_l2_table_entry_out_bits {
3836 u8 status[0x8];
b4ff3a36 3837 u8 reserved_at_8[0x18];
e281682b
SM		 3838
3839 u8 syndrome[0x20];
3840
b4ff3a36 3841 u8 reserved_at_40[0xa0];
e281682b 3842
b4ff3a36 3843 u8 reserved_at_e0[0x13];
e281682b
SM		 3844 u8 vlan_valid[0x1];
3845 u8 vlan[0xc];
3846
3847 struct mlx5_ifc_mac_address_layout_bits mac_address;
3848
b4ff3a36 3849 u8 reserved_at_140[0xc0];
e281682b
SM		 3850};
3851
3852struct mlx5_ifc_query_l2_table_entry_in_bits {
3853 u8 opcode[0x10];
b4ff3a36 3854 u8 reserved_at_10[0x10];
e281682b 3855
b4ff3a36 3856 u8 reserved_at_20[0x10];
e281682b
SM		 3857 u8 op_mod[0x10];
3858
b4ff3a36 3859 u8 reserved_at_40[0x60];
e281682b 3860
b4ff3a36 3861 u8 reserved_at_a0[0x8];
e281682b
SM		 3862 u8 table_index[0x18];
3863
b4ff3a36 3864 u8 reserved_at_c0[0x140];
e281682b
SM		 3865};
3866
3867struct mlx5_ifc_query_issi_out_bits {
3868 u8 status[0x8];
b4ff3a36 3869 u8 reserved_at_8[0x18];
e281682b
SM		 3870
3871 u8 syndrome[0x20];
3872
b4ff3a36 3873 u8 reserved_at_40[0x10];
e281682b
SM		 3874 u8 current_issi[0x10];
3875
b4ff3a36 3876 u8 reserved_at_60[0xa0];
e281682b 3877
b4ff3a36 3878 u8 reserved_at_100[76][0x8];
e281682b
SM		 3879 u8 supported_issi_dw0[0x20];
3880};
3881
3882struct mlx5_ifc_query_issi_in_bits {
3883 u8 opcode[0x10];
b4ff3a36 3884 u8 reserved_at_10[0x10];
e281682b 3885
b4ff3a36 3886 u8 reserved_at_20[0x10];
e281682b
SM		 3887 u8 op_mod[0x10];
3888
b4ff3a36 3889 u8 reserved_at_40[0x40];
e281682b
SM		 3890};
3891
3892struct mlx5_ifc_query_hca_vport_pkey_out_bits {
3893 u8 status[0x8];
b4ff3a36 3894 u8 reserved_at_8[0x18];
e281682b
SM		 3895
3896 u8 syndrome[0x20];
3897
b4ff3a36 3898 u8 reserved_at_40[0x40];
e281682b
SM		 3899
3900 struct mlx5_ifc_pkey_bits pkey[0];
3901};
3902
3903struct mlx5_ifc_query_hca_vport_pkey_in_bits {
3904 u8 opcode[0x10];
b4ff3a36 3905 u8 reserved_at_10[0x10];
e281682b 3906
b4ff3a36 3907 u8 reserved_at_20[0x10];
e281682b
SM		 3908 u8 op_mod[0x10];
3909
3910 u8 other_vport[0x1];
b4ff3a36 3911 u8 reserved_at_41[0xb];
707c4602 3912 u8 port_num[0x4];
e281682b
SM		 3913 u8 vport_number[0x10];
3914
b4ff3a36 3915 u8 reserved_at_60[0x10];
e281682b
SM		 3916 u8 pkey_index[0x10];
3917};
3918
eff901d3
EC		 3919enum {
3920 MLX5_HCA_VPORT_SEL_PORT_GUID = 1 << 0,
3921 MLX5_HCA_VPORT_SEL_NODE_GUID = 1 << 1,
3922 MLX5_HCA_VPORT_SEL_STATE_POLICY = 1 << 2,
3923};
3924
e281682b
SM		 3925struct mlx5_ifc_query_hca_vport_gid_out_bits {
3926 u8 status[0x8];
b4ff3a36 3927 u8 reserved_at_8[0x18];
e281682b
SM		 3928
3929 u8 syndrome[0x20];
3930
b4ff3a36 3931 u8 reserved_at_40[0x20];
e281682b
SM		 3932
3933 u8 gids_num[0x10];
b4ff3a36 3934 u8 reserved_at_70[0x10];
e281682b
SM		 3935
3936 struct mlx5_ifc_array128_auto_bits gid[0];
3937};
3938
3939struct mlx5_ifc_query_hca_vport_gid_in_bits {
3940 u8 opcode[0x10];
b4ff3a36 3941 u8 reserved_at_10[0x10];
e281682b 3942
b4ff3a36 3943 u8 reserved_at_20[0x10];
e281682b
SM		 3944 u8 op_mod[0x10];
3945
3946 u8 other_vport[0x1];
b4ff3a36 3947 u8 reserved_at_41[0xb];
707c4602 3948 u8 port_num[0x4];
e281682b
SM		 3949 u8 vport_number[0x10];
3950
b4ff3a36 3951 u8 reserved_at_60[0x10];
e281682b
SM		 3952 u8 gid_index[0x10];
3953};
3954
3955struct mlx5_ifc_query_hca_vport_context_out_bits {
3956 u8 status[0x8];
b4ff3a36 3957 u8 reserved_at_8[0x18];
e281682b
SM		 3958
3959 u8 syndrome[0x20];
3960
b4ff3a36 3961 u8 reserved_at_40[0x40];
e281682b
SM		 3962
3963 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
3964};
3965
3966struct mlx5_ifc_query_hca_vport_context_in_bits {
3967 u8 opcode[0x10];
b4ff3a36 3968 u8 reserved_at_10[0x10];
e281682b 3969
b4ff3a36 3970 u8 reserved_at_20[0x10];
e281682b
SM		 3971 u8 op_mod[0x10];
3972
3973 u8 other_vport[0x1];
b4ff3a36 3974 u8 reserved_at_41[0xb];
707c4602 3975 u8 port_num[0x4];
e281682b
SM		 3976 u8 vport_number[0x10];
3977
b4ff3a36 3978 u8 reserved_at_60[0x20];
e281682b
SM		 3979};
3980
3981struct mlx5_ifc_query_hca_cap_out_bits {
3982 u8 status[0x8];
b4ff3a36 3983 u8 reserved_at_8[0x18];
e281682b
SM		 3984
3985 u8 syndrome[0x20];
3986
b4ff3a36 3987 u8 reserved_at_40[0x40];
e281682b
SM		 3988
3989 union mlx5_ifc_hca_cap_union_bits capability;
3990};
3991
3992struct mlx5_ifc_query_hca_cap_in_bits {
3993 u8 opcode[0x10];
b4ff3a36 3994 u8 reserved_at_10[0x10];
e281682b 3995
b4ff3a36 3996 u8 reserved_at_20[0x10];
e281682b
SM		 3997 u8 op_mod[0x10];
3998
b4ff3a36 3999 u8 reserved_at_40[0x40];
e281682b
SM		 4000};
4001
4002struct mlx5_ifc_query_flow_table_out_bits {
4003 u8 status[0x8];
b4ff3a36 4004 u8 reserved_at_8[0x18];
e281682b
SM		 4005
4006 u8 syndrome[0x20];
4007
b4ff3a36 4008 u8 reserved_at_40[0x80];
e281682b 4009
b4ff3a36 4010 u8 reserved_at_c0[0x8];
e281682b 4011 u8 level[0x8];
b4ff3a36 4012 u8 reserved_at_d0[0x8];
e281682b
SM		 4013 u8 log_size[0x8];
4014
b4ff3a36 4015 u8 reserved_at_e0[0x120];
e281682b
SM		 4016};
4017
4018struct mlx5_ifc_query_flow_table_in_bits {
4019 u8 opcode[0x10];
b4ff3a36 4020 u8 reserved_at_10[0x10];
e281682b 4021
b4ff3a36 4022 u8 reserved_at_20[0x10];
e281682b
SM		 4023 u8 op_mod[0x10];
4024
b4ff3a36 4025 u8 reserved_at_40[0x40];
e281682b
SM		 4026
4027 u8 table_type[0x8];
b4ff3a36 4028 u8 reserved_at_88[0x18];
e281682b 4029
b4ff3a36 4030 u8 reserved_at_a0[0x8];
e281682b
SM		 4031 u8 table_id[0x18];
4032
b4ff3a36 4033 u8 reserved_at_c0[0x140];
e281682b
SM		 4034};
4035
4036struct mlx5_ifc_query_fte_out_bits {
4037 u8 status[0x8];
b4ff3a36 4038 u8 reserved_at_8[0x18];
e281682b
SM		 4039
4040 u8 syndrome[0x20];
4041
b4ff3a36 4042 u8 reserved_at_40[0x1c0];
e281682b
SM		 4043
4044 struct mlx5_ifc_flow_context_bits flow_context;
4045};
4046
4047struct mlx5_ifc_query_fte_in_bits {
4048 u8 opcode[0x10];
b4ff3a36 4049 u8 reserved_at_10[0x10];
e281682b 4050
b4ff3a36 4051 u8 reserved_at_20[0x10];
e281682b
SM		 4052 u8 op_mod[0x10];
4053
b4ff3a36 4054 u8 reserved_at_40[0x40];
e281682b
SM		 4055
4056 u8 table_type[0x8];
b4ff3a36 4057 u8 reserved_at_88[0x18];
e281682b 4058
b4ff3a36 4059 u8 reserved_at_a0[0x8];
e281682b
SM		 4060 u8 table_id[0x18];
4061
b4ff3a36 4062 u8 reserved_at_c0[0x40];
e281682b
SM		 4063
4064 u8 flow_index[0x20];
4065
b4ff3a36 4066 u8 reserved_at_120[0xe0];
e281682b
SM		 4067};
4068
4069enum {
4070 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
4071 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
4072 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
4073};
4074
4075struct mlx5_ifc_query_flow_group_out_bits {
4076 u8 status[0x8];
b4ff3a36 4077 u8 reserved_at_8[0x18];
e281682b
SM		 4078
4079 u8 syndrome[0x20];
4080
b4ff3a36 4081 u8 reserved_at_40[0xa0];
e281682b
SM		 4082
4083 u8 start_flow_index[0x20];
4084
b4ff3a36 4085 u8 reserved_at_100[0x20];
e281682b
SM		 4086
4087 u8 end_flow_index[0x20];
4088
b4ff3a36 4089 u8 reserved_at_140[0xa0];
e281682b 4090
b4ff3a36 4091 u8 reserved_at_1e0[0x18];
e281682b
SM		 4092 u8 match_criteria_enable[0x8];
4093
4094 struct mlx5_ifc_fte_match_param_bits match_criteria;
4095
b4ff3a36 4096 u8 reserved_at_1200[0xe00];
e281682b
SM		 4097};
4098
4099struct mlx5_ifc_query_flow_group_in_bits {
4100 u8 opcode[0x10];
b4ff3a36 4101 u8 reserved_at_10[0x10];
e281682b 4102
b4ff3a36 4103 u8 reserved_at_20[0x10];
e281682b
SM		 4104 u8 op_mod[0x10];
4105
b4ff3a36 4106 u8 reserved_at_40[0x40];
e281682b
SM		 4107
4108 u8 table_type[0x8];
b4ff3a36 4109 u8 reserved_at_88[0x18];
e281682b 4110
b4ff3a36 4111 u8 reserved_at_a0[0x8];
e281682b
SM		 4112 u8 table_id[0x18];
4113
4114 u8 group_id[0x20];
4115
b4ff3a36 4116 u8 reserved_at_e0[0x120];
e281682b
SM		 4117};
4118
9dc0b289
AV		 4119struct mlx5_ifc_query_flow_counter_out_bits {
4120 u8 status[0x8];
4121 u8 reserved_at_8[0x18];
4122
4123 u8 syndrome[0x20];
4124
4125 u8 reserved_at_40[0x40];
4126
4127 struct mlx5_ifc_traffic_counter_bits flow_statistics[0];
4128};
4129
4130struct mlx5_ifc_query_flow_counter_in_bits {
4131 u8 opcode[0x10];
4132 u8 reserved_at_10[0x10];
4133
4134 u8 reserved_at_20[0x10];
4135 u8 op_mod[0x10];
4136
4137 u8 reserved_at_40[0x80];
4138
4139 u8 clear[0x1];
4140 u8 reserved_at_c1[0xf];
4141 u8 num_of_counters[0x10];
4142
4143 u8 reserved_at_e0[0x10];
4144 u8 flow_counter_id[0x10];
4145};
4146
d6666753
SM		 4147struct mlx5_ifc_query_esw_vport_context_out_bits {
4148 u8 status[0x8];
b4ff3a36 4149 u8 reserved_at_8[0x18];
d6666753
SM		 4150
4151 u8 syndrome[0x20];
4152
b4ff3a36 4153 u8 reserved_at_40[0x40];
d6666753
SM		 4154
4155 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4156};
4157
4158struct mlx5_ifc_query_esw_vport_context_in_bits {
4159 u8 opcode[0x10];
b4ff3a36 4160 u8 reserved_at_10[0x10];
d6666753 4161
b4ff3a36 4162 u8 reserved_at_20[0x10];
d6666753
SM		 4163 u8 op_mod[0x10];
4164
4165 u8 other_vport[0x1];
b4ff3a36 4166 u8 reserved_at_41[0xf];
d6666753
SM		 4167 u8 vport_number[0x10];
4168
b4ff3a36 4169 u8 reserved_at_60[0x20];
d6666753
SM		 4170};
4171
4172struct mlx5_ifc_modify_esw_vport_context_out_bits {
4173 u8 status[0x8];
b4ff3a36 4174 u8 reserved_at_8[0x18];
d6666753
SM		 4175
4176 u8 syndrome[0x20];
4177
b4ff3a36 4178 u8 reserved_at_40[0x40];
d6666753
SM		 4179};
4180
4181struct mlx5_ifc_esw_vport_context_fields_select_bits {
b4ff3a36 4182 u8 reserved_at_0[0x1c];
d6666753
SM		 4183 u8 vport_cvlan_insert[0x1];
4184 u8 vport_svlan_insert[0x1];
4185 u8 vport_cvlan_strip[0x1];
4186 u8 vport_svlan_strip[0x1];
4187};
4188
4189struct mlx5_ifc_modify_esw_vport_context_in_bits {
4190 u8 opcode[0x10];
b4ff3a36 4191 u8 reserved_at_10[0x10];
d6666753 4192
b4ff3a36 4193 u8 reserved_at_20[0x10];
d6666753
SM		 4194 u8 op_mod[0x10];
4195
4196 u8 other_vport[0x1];
b4ff3a36 4197 u8 reserved_at_41[0xf];
d6666753
SM		 4198 u8 vport_number[0x10];
4199
4200 struct mlx5_ifc_esw_vport_context_fields_select_bits field_select;
4201
4202 struct mlx5_ifc_esw_vport_context_bits esw_vport_context;
4203};
4204
e281682b
SM		 4205struct mlx5_ifc_query_eq_out_bits {
4206 u8 status[0x8];
b4ff3a36 4207 u8 reserved_at_8[0x18];
e281682b
SM		 4208
4209 u8 syndrome[0x20];
4210
b4ff3a36 4211 u8 reserved_at_40[0x40];
e281682b
SM		 4212
4213 struct mlx5_ifc_eqc_bits eq_context_entry;
4214
b4ff3a36 4215 u8 reserved_at_280[0x40];
e281682b
SM		 4216
4217 u8 event_bitmask[0x40];
4218
b4ff3a36 4219 u8 reserved_at_300[0x580];
e281682b
SM		 4220
4221 u8 pas[0][0x40];
4222};
4223
4224struct mlx5_ifc_query_eq_in_bits {
4225 u8 opcode[0x10];
b4ff3a36 4226 u8 reserved_at_10[0x10];
e281682b 4227
b4ff3a36 4228 u8 reserved_at_20[0x10];
e281682b
SM		 4229 u8 op_mod[0x10];
4230
b4ff3a36 4231 u8 reserved_at_40[0x18];
e281682b
SM		 4232 u8 eq_number[0x8];
4233
b4ff3a36 4234 u8 reserved_at_60[0x20];
e281682b
SM		 4235};
4236
7adbde20
HHZ		 4237struct mlx5_ifc_encap_header_in_bits {
4238 u8 reserved_at_0[0x5];
4239 u8 header_type[0x3];
4240 u8 reserved_at_8[0xe];
4241 u8 encap_header_size[0xa];
4242
4243 u8 reserved_at_20[0x10];
4244 u8 encap_header[2][0x8];
4245
4246 u8 more_encap_header[0][0x8];
4247};
4248
4249struct mlx5_ifc_query_encap_header_out_bits {
4250 u8 status[0x8];
4251 u8 reserved_at_8[0x18];
4252
4253 u8 syndrome[0x20];
4254
4255 u8 reserved_at_40[0xa0];
4256
4257 struct mlx5_ifc_encap_header_in_bits encap_header[0];
4258};
4259
4260struct mlx5_ifc_query_encap_header_in_bits {
4261 u8 opcode[0x10];
4262 u8 reserved_at_10[0x10];
4263
4264 u8 reserved_at_20[0x10];
4265 u8 op_mod[0x10];
4266
4267 u8 encap_id[0x20];
4268
4269 u8 reserved_at_60[0xa0];
4270};
4271
4272struct mlx5_ifc_alloc_encap_header_out_bits {
4273 u8 status[0x8];
4274 u8 reserved_at_8[0x18];
4275
4276 u8 syndrome[0x20];
4277
4278 u8 encap_id[0x20];
4279
4280 u8 reserved_at_60[0x20];
4281};
4282
4283struct mlx5_ifc_alloc_encap_header_in_bits {
4284 u8 opcode[0x10];
4285 u8 reserved_at_10[0x10];
4286
4287 u8 reserved_at_20[0x10];
4288 u8 op_mod[0x10];
4289
4290 u8 reserved_at_40[0xa0];
4291
4292 struct mlx5_ifc_encap_header_in_bits encap_header;
4293};
4294
4295struct mlx5_ifc_dealloc_encap_header_out_bits {
4296 u8 status[0x8];
4297 u8 reserved_at_8[0x18];
4298
4299 u8 syndrome[0x20];
4300
4301 u8 reserved_at_40[0x40];
4302};
4303
4304struct mlx5_ifc_dealloc_encap_header_in_bits {
4305 u8 opcode[0x10];
4306 u8 reserved_at_10[0x10];
4307
4308 u8 reserved_20[0x10];
4309 u8 op_mod[0x10];
4310
4311 u8 encap_id[0x20];
4312
4313 u8 reserved_60[0x20];
4314};
4315
e281682b
SM		 4316struct mlx5_ifc_query_dct_out_bits {
4317 u8 status[0x8];
b4ff3a36 4318 u8 reserved_at_8[0x18];
e281682b
SM		 4319
4320 u8 syndrome[0x20];
4321
b4ff3a36 4322 u8 reserved_at_40[0x40];
e281682b
SM		 4323
4324 struct mlx5_ifc_dctc_bits dct_context_entry;
4325
b4ff3a36 4326 u8 reserved_at_280[0x180];
e281682b
SM		 4327};
4328
4329struct mlx5_ifc_query_dct_in_bits {
4330 u8 opcode[0x10];
b4ff3a36 4331 u8 reserved_at_10[0x10];
e281682b 4332
b4ff3a36 4333 u8 reserved_at_20[0x10];
e281682b
SM		 4334 u8 op_mod[0x10];
4335
b4ff3a36 4336 u8 reserved_at_40[0x8];
e281682b
SM		 4337 u8 dctn[0x18];
4338
b4ff3a36 4339 u8 reserved_at_60[0x20];
e281682b
SM		 4340};
4341
4342struct mlx5_ifc_query_cq_out_bits {
4343 u8 status[0x8];
b4ff3a36 4344 u8 reserved_at_8[0x18];
e281682b
SM		 4345
4346 u8 syndrome[0x20];
4347
b4ff3a36 4348 u8 reserved_at_40[0x40];
e281682b
SM		 4349
4350 struct mlx5_ifc_cqc_bits cq_context;
4351
b4ff3a36 4352 u8 reserved_at_280[0x600];
e281682b
SM		 4353
4354 u8 pas[0][0x40];
4355};
4356
4357struct mlx5_ifc_query_cq_in_bits {
4358 u8 opcode[0x10];
b4ff3a36 4359 u8 reserved_at_10[0x10];
e281682b 4360
b4ff3a36 4361 u8 reserved_at_20[0x10];
e281682b
SM		 4362 u8 op_mod[0x10];
4363
b4ff3a36 4364 u8 reserved_at_40[0x8];
e281682b
SM		 4365 u8 cqn[0x18];
4366
b4ff3a36 4367 u8 reserved_at_60[0x20];
e281682b
SM		 4368};
4369
4370struct mlx5_ifc_query_cong_status_out_bits {
4371 u8 status[0x8];
b4ff3a36 4372 u8 reserved_at_8[0x18];
e281682b
SM		 4373
4374 u8 syndrome[0x20];
4375
b4ff3a36 4376 u8 reserved_at_40[0x20];
e281682b
SM		 4377
4378 u8 enable[0x1];
4379 u8 tag_enable[0x1];
b4ff3a36 4380 u8 reserved_at_62[0x1e];
e281682b
SM		 4381};
4382
4383struct mlx5_ifc_query_cong_status_in_bits {
4384 u8 opcode[0x10];
b4ff3a36 4385 u8 reserved_at_10[0x10];
e281682b 4386
b4ff3a36 4387 u8 reserved_at_20[0x10];
e281682b
SM		 4388 u8 op_mod[0x10];
4389
b4ff3a36 4390 u8 reserved_at_40[0x18];
e281682b
SM		 4391 u8 priority[0x4];
4392 u8 cong_protocol[0x4];
4393
b4ff3a36 4394 u8 reserved_at_60[0x20];
e281682b
SM		 4395};
4396
4397struct mlx5_ifc_query_cong_statistics_out_bits {
4398 u8 status[0x8];
b4ff3a36 4399 u8 reserved_at_8[0x18];
e281682b
SM		 4400
4401 u8 syndrome[0x20];
4402
b4ff3a36 4403 u8 reserved_at_40[0x40];
e281682b
SM		 4404
4405 u8 cur_flows[0x20];
4406
4407 u8 sum_flows[0x20];
4408
4409 u8 cnp_ignored_high[0x20];
4410
4411 u8 cnp_ignored_low[0x20];
4412
4413 u8 cnp_handled_high[0x20];
4414
4415 u8 cnp_handled_low[0x20];
4416
b4ff3a36 4417 u8 reserved_at_140[0x100];
e281682b
SM		 4418
4419 u8 time_stamp_high[0x20];
4420
4421 u8 time_stamp_low[0x20];
4422
4423 u8 accumulators_period[0x20];
4424
4425 u8 ecn_marked_roce_packets_high[0x20];
4426
4427 u8 ecn_marked_roce_packets_low[0x20];
4428
4429 u8 cnps_sent_high[0x20];
4430
4431 u8 cnps_sent_low[0x20];
4432
b4ff3a36 4433 u8 reserved_at_320[0x560];
e281682b
SM		 4434};
4435
4436struct mlx5_ifc_query_cong_statistics_in_bits {
4437 u8 opcode[0x10];
b4ff3a36 4438 u8 reserved_at_10[0x10];
e281682b 4439
b4ff3a36 4440 u8 reserved_at_20[0x10];
e281682b
SM		 4441 u8 op_mod[0x10];
4442
4443 u8 clear[0x1];
b4ff3a36 4444 u8 reserved_at_41[0x1f];
e281682b 4445
b4ff3a36 4446 u8 reserved_at_60[0x20];
e281682b
SM		 4447};
4448
4449struct mlx5_ifc_query_cong_params_out_bits {
4450 u8 status[0x8];
b4ff3a36 4451 u8 reserved_at_8[0x18];
e281682b
SM		 4452
4453 u8 syndrome[0x20];
4454
b4ff3a36 4455 u8 reserved_at_40[0x40];
e281682b
SM		 4456
4457 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4458};
4459
4460struct mlx5_ifc_query_cong_params_in_bits {
4461 u8 opcode[0x10];
b4ff3a36 4462 u8 reserved_at_10[0x10];
e281682b 4463
b4ff3a36 4464 u8 reserved_at_20[0x10];
e281682b
SM		 4465 u8 op_mod[0x10];
4466
b4ff3a36 4467 u8 reserved_at_40[0x1c];
e281682b
SM		 4468 u8 cong_protocol[0x4];
4469
b4ff3a36 4470 u8 reserved_at_60[0x20];
e281682b
SM		 4471};
4472
4473struct mlx5_ifc_query_adapter_out_bits {
4474 u8 status[0x8];
b4ff3a36 4475 u8 reserved_at_8[0x18];
e281682b
SM		 4476
4477 u8 syndrome[0x20];
4478
b4ff3a36 4479 u8 reserved_at_40[0x40];
e281682b
SM		 4480
4481 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
4482};
4483
4484struct mlx5_ifc_query_adapter_in_bits {
4485 u8 opcode[0x10];
b4ff3a36 4486 u8 reserved_at_10[0x10];
e281682b 4487
b4ff3a36 4488 u8 reserved_at_20[0x10];
e281682b
SM		 4489 u8 op_mod[0x10];
4490
b4ff3a36 4491 u8 reserved_at_40[0x40];
e281682b
SM		 4492};
4493
4494struct mlx5_ifc_qp_2rst_out_bits {
4495 u8 status[0x8];
b4ff3a36 4496 u8 reserved_at_8[0x18];
e281682b
SM		 4497
4498 u8 syndrome[0x20];
4499
b4ff3a36 4500 u8 reserved_at_40[0x40];
e281682b
SM		 4501};
4502
4503struct mlx5_ifc_qp_2rst_in_bits {
4504 u8 opcode[0x10];
b4ff3a36 4505 u8 reserved_at_10[0x10];
e281682b 4506
b4ff3a36 4507 u8 reserved_at_20[0x10];
e281682b
SM		 4508 u8 op_mod[0x10];
4509
b4ff3a36 4510 u8 reserved_at_40[0x8];
e281682b
SM		 4511 u8 qpn[0x18];
4512
b4ff3a36 4513 u8 reserved_at_60[0x20];
e281682b
SM		 4514};
4515
4516struct mlx5_ifc_qp_2err_out_bits {
4517 u8 status[0x8];
b4ff3a36 4518 u8 reserved_at_8[0x18];
e281682b
SM		 4519
4520 u8 syndrome[0x20];
4521
b4ff3a36 4522 u8 reserved_at_40[0x40];
e281682b
SM		 4523};
4524
4525struct mlx5_ifc_qp_2err_in_bits {
4526 u8 opcode[0x10];
b4ff3a36 4527 u8 reserved_at_10[0x10];
e281682b 4528
b4ff3a36 4529 u8 reserved_at_20[0x10];
e281682b
SM		 4530 u8 op_mod[0x10];
4531
b4ff3a36 4532 u8 reserved_at_40[0x8];
e281682b
SM		 4533 u8 qpn[0x18];
4534
b4ff3a36 4535 u8 reserved_at_60[0x20];
e281682b
SM		 4536};
4537
4538struct mlx5_ifc_page_fault_resume_out_bits {
4539 u8 status[0x8];
b4ff3a36 4540 u8 reserved_at_8[0x18];
e281682b
SM		 4541
4542 u8 syndrome[0x20];
4543
b4ff3a36 4544 u8 reserved_at_40[0x40];
e281682b
SM		 4545};
4546
4547struct mlx5_ifc_page_fault_resume_in_bits {
4548 u8 opcode[0x10];
b4ff3a36 4549 u8 reserved_at_10[0x10];
e281682b 4550
b4ff3a36 4551 u8 reserved_at_20[0x10];
e281682b
SM		 4552 u8 op_mod[0x10];
4553
4554 u8 error[0x1];
b4ff3a36 4555 u8 reserved_at_41[0x4];
e281682b
SM		 4556 u8 rdma[0x1];
4557 u8 read_write[0x1];
4558 u8 req_res[0x1];
4559 u8 qpn[0x18];
4560
b4ff3a36 4561 u8 reserved_at_60[0x20];
e281682b
SM		 4562};
4563
4564struct mlx5_ifc_nop_out_bits {
4565 u8 status[0x8];
b4ff3a36 4566 u8 reserved_at_8[0x18];
e281682b
SM		 4567
4568 u8 syndrome[0x20];
4569
b4ff3a36 4570 u8 reserved_at_40[0x40];
e281682b
SM		 4571};
4572
4573struct mlx5_ifc_nop_in_bits {
4574 u8 opcode[0x10];
b4ff3a36 4575 u8 reserved_at_10[0x10];
e281682b 4576
b4ff3a36 4577 u8 reserved_at_20[0x10];
e281682b
SM		 4578 u8 op_mod[0x10];
4579
b4ff3a36 4580 u8 reserved_at_40[0x40];
e281682b
SM		 4581};
4582
4583struct mlx5_ifc_modify_vport_state_out_bits {
4584 u8 status[0x8];
b4ff3a36 4585 u8 reserved_at_8[0x18];
e281682b
SM		 4586
4587 u8 syndrome[0x20];
4588
b4ff3a36 4589 u8 reserved_at_40[0x40];
e281682b
SM		 4590};
4591
4592struct mlx5_ifc_modify_vport_state_in_bits {
4593 u8 opcode[0x10];
b4ff3a36 4594 u8 reserved_at_10[0x10];
e281682b 4595
b4ff3a36 4596 u8 reserved_at_20[0x10];
e281682b
SM		 4597 u8 op_mod[0x10];
4598
4599 u8 other_vport[0x1];
b4ff3a36 4600 u8 reserved_at_41[0xf];
e281682b
SM		 4601 u8 vport_number[0x10];
4602
b4ff3a36 4603 u8 reserved_at_60[0x18];
e281682b 4604 u8 admin_state[0x4];
b4ff3a36 4605 u8 reserved_at_7c[0x4];
e281682b
SM		 4606};
4607
4608struct mlx5_ifc_modify_tis_out_bits {
4609 u8 status[0x8];
b4ff3a36 4610 u8 reserved_at_8[0x18];
e281682b
SM		 4611
4612 u8 syndrome[0x20];
4613
b4ff3a36 4614 u8 reserved_at_40[0x40];
e281682b
SM		 4615};
4616
75850d0b 4617struct mlx5_ifc_modify_tis_bitmask_bits {
b4ff3a36 4618 u8 reserved_at_0[0x20];
75850d0b 4619
b4ff3a36 4620 u8 reserved_at_20[0x1f];
75850d0b 4621 u8 prio[0x1];
4622};
4623
e281682b
SM		 4624struct mlx5_ifc_modify_tis_in_bits {
4625 u8 opcode[0x10];
b4ff3a36 4626 u8 reserved_at_10[0x10];
e281682b 4627
b4ff3a36 4628 u8 reserved_at_20[0x10];
e281682b
SM		 4629 u8 op_mod[0x10];
4630
b4ff3a36 4631 u8 reserved_at_40[0x8];
e281682b
SM		 4632 u8 tisn[0x18];
4633
b4ff3a36 4634 u8 reserved_at_60[0x20];
e281682b 4635
75850d0b 4636 struct mlx5_ifc_modify_tis_bitmask_bits bitmask;
e281682b 4637
b4ff3a36 4638 u8 reserved_at_c0[0x40];
e281682b
SM		 4639
4640 struct mlx5_ifc_tisc_bits ctx;
4641};
4642
d9eea403 4643struct mlx5_ifc_modify_tir_bitmask_bits {
b4ff3a36 4644 u8 reserved_at_0[0x20];
d9eea403 4645
b4ff3a36 4646 u8 reserved_at_20[0x1b];
66189961 4647 u8 self_lb_en[0x1];
bdfc028d
TT		 4648 u8 reserved_at_3c[0x1];
4649 u8 hash[0x1];
4650 u8 reserved_at_3e[0x1];
d9eea403
AS		 4651 u8 lro[0x1];
4652};
4653
e281682b
SM		 4654struct mlx5_ifc_modify_tir_out_bits {
4655 u8 status[0x8];
b4ff3a36 4656 u8 reserved_at_8[0x18];
e281682b
SM		 4657
4658 u8 syndrome[0x20];
4659
b4ff3a36 4660 u8 reserved_at_40[0x40];
e281682b
SM		 4661};
4662
4663struct mlx5_ifc_modify_tir_in_bits {
4664 u8 opcode[0x10];
b4ff3a36 4665 u8 reserved_at_10[0x10];
e281682b 4666
b4ff3a36 4667 u8 reserved_at_20[0x10];
e281682b
SM		 4668 u8 op_mod[0x10];
4669
b4ff3a36 4670 u8 reserved_at_40[0x8];
e281682b
SM		 4671 u8 tirn[0x18];
4672
b4ff3a36 4673 u8 reserved_at_60[0x20];
e281682b 4674
d9eea403 4675 struct mlx5_ifc_modify_tir_bitmask_bits bitmask;
e281682b 4676
b4ff3a36 4677 u8 reserved_at_c0[0x40];
e281682b
SM		 4678
4679 struct mlx5_ifc_tirc_bits ctx;
4680};
4681
4682struct mlx5_ifc_modify_sq_out_bits {
4683 u8 status[0x8];
b4ff3a36 4684 u8 reserved_at_8[0x18];
e281682b
SM		 4685
4686 u8 syndrome[0x20];
4687
b4ff3a36 4688 u8 reserved_at_40[0x40];
e281682b
SM		 4689};
4690
4691struct mlx5_ifc_modify_sq_in_bits {
4692 u8 opcode[0x10];
b4ff3a36 4693 u8 reserved_at_10[0x10];
e281682b 4694
b4ff3a36 4695 u8 reserved_at_20[0x10];
e281682b
SM		 4696 u8 op_mod[0x10];
4697
4698 u8 sq_state[0x4];
b4ff3a36 4699 u8 reserved_at_44[0x4];
e281682b
SM		 4700 u8 sqn[0x18];
4701
b4ff3a36 4702 u8 reserved_at_60[0x20];
e281682b
SM		 4703
4704 u8 modify_bitmask[0x40];
4705
b4ff3a36 4706 u8 reserved_at_c0[0x40];
e281682b
SM		 4707
4708 struct mlx5_ifc_sqc_bits ctx;
4709};
4710
4711struct mlx5_ifc_modify_rqt_out_bits {
4712 u8 status[0x8];
b4ff3a36 4713 u8 reserved_at_8[0x18];
e281682b
SM		 4714
4715 u8 syndrome[0x20];
4716
b4ff3a36 4717 u8 reserved_at_40[0x40];
e281682b
SM		 4718};
4719
5c50368f 4720struct mlx5_ifc_rqt_bitmask_bits {
b4ff3a36 4721 u8 reserved_at_0[0x20];
5c50368f 4722
b4ff3a36 4723 u8 reserved_at_20[0x1f];
5c50368f
AS		 4724 u8 rqn_list[0x1];
4725};
4726
e281682b
SM		 4727struct mlx5_ifc_modify_rqt_in_bits {
4728 u8 opcode[0x10];
b4ff3a36 4729 u8 reserved_at_10[0x10];
e281682b 4730
b4ff3a36 4731 u8 reserved_at_20[0x10];
e281682b
SM		 4732 u8 op_mod[0x10];
4733
b4ff3a36 4734 u8 reserved_at_40[0x8];
e281682b
SM		 4735 u8 rqtn[0x18];
4736
b4ff3a36 4737 u8 reserved_at_60[0x20];
e281682b 4738
5c50368f 4739 struct mlx5_ifc_rqt_bitmask_bits bitmask;
e281682b 4740
b4ff3a36 4741 u8 reserved_at_c0[0x40];
e281682b
SM		 4742
4743 struct mlx5_ifc_rqtc_bits ctx;
4744};
4745
4746struct mlx5_ifc_modify_rq_out_bits {
4747 u8 status[0x8];
b4ff3a36 4748 u8 reserved_at_8[0x18];
e281682b
SM		 4749
4750 u8 syndrome[0x20];
4751
b4ff3a36 4752 u8 reserved_at_40[0x40];
e281682b
SM		 4753};
4754
83b502a1
AV		 4755enum {
4756 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD = 1ULL << 1,
4757 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID = 1ULL << 3,
4758};
4759
e281682b
SM		 4760struct mlx5_ifc_modify_rq_in_bits {
4761 u8 opcode[0x10];
b4ff3a36 4762 u8 reserved_at_10[0x10];
e281682b 4763
b4ff3a36 4764 u8 reserved_at_20[0x10];
e281682b
SM		 4765 u8 op_mod[0x10];
4766
4767 u8 rq_state[0x4];
b4ff3a36 4768 u8 reserved_at_44[0x4];
e281682b
SM		 4769 u8 rqn[0x18];
4770
b4ff3a36 4771 u8 reserved_at_60[0x20];
e281682b
SM		 4772
4773 u8 modify_bitmask[0x40];
4774
b4ff3a36 4775 u8 reserved_at_c0[0x40];
e281682b
SM		 4776
4777 struct mlx5_ifc_rqc_bits ctx;
4778};
4779
4780struct mlx5_ifc_modify_rmp_out_bits {
4781 u8 status[0x8];
b4ff3a36 4782 u8 reserved_at_8[0x18];
e281682b
SM		 4783
4784 u8 syndrome[0x20];
4785
b4ff3a36 4786 u8 reserved_at_40[0x40];
e281682b
SM		 4787};
4788
01949d01 4789struct mlx5_ifc_rmp_bitmask_bits {
b4ff3a36 4790 u8 reserved_at_0[0x20];
01949d01 4791
b4ff3a36 4792 u8 reserved_at_20[0x1f];
01949d01
HA		 4793 u8 lwm[0x1];
4794};
4795
e281682b
SM		 4796struct mlx5_ifc_modify_rmp_in_bits {
4797 u8 opcode[0x10];
b4ff3a36 4798 u8 reserved_at_10[0x10];
e281682b 4799
b4ff3a36 4800 u8 reserved_at_20[0x10];
e281682b
SM		 4801 u8 op_mod[0x10];
4802
4803 u8 rmp_state[0x4];
b4ff3a36 4804 u8 reserved_at_44[0x4];
e281682b
SM		 4805 u8 rmpn[0x18];
4806
b4ff3a36 4807 u8 reserved_at_60[0x20];
e281682b 4808
01949d01 4809 struct mlx5_ifc_rmp_bitmask_bits bitmask;
e281682b 4810
b4ff3a36 4811 u8 reserved_at_c0[0x40];
e281682b
SM		 4812
4813 struct mlx5_ifc_rmpc_bits ctx;
4814};
4815
4816struct mlx5_ifc_modify_nic_vport_context_out_bits {
4817 u8 status[0x8];
b4ff3a36 4818 u8 reserved_at_8[0x18];
e281682b
SM		 4819
4820 u8 syndrome[0x20];
4821
b4ff3a36 4822 u8 reserved_at_40[0x40];
e281682b
SM		 4823};
4824
4825struct mlx5_ifc_modify_nic_vport_field_select_bits {
23898c76
NO		 4826 u8 reserved_at_0[0x16];
4827 u8 node_guid[0x1];
4828 u8 port_guid[0x1];
9def7121 4829 u8 min_inline[0x1];
d82b7318
SM		 4830 u8 mtu[0x1];
4831 u8 change_event[0x1];
4832 u8 promisc[0x1];
e281682b
SM		 4833 u8 permanent_address[0x1];
4834 u8 addresses_list[0x1];
4835 u8 roce_en[0x1];
b4ff3a36 4836 u8 reserved_at_1f[0x1];
e281682b
SM		 4837};
4838
4839struct mlx5_ifc_modify_nic_vport_context_in_bits {
4840 u8 opcode[0x10];
b4ff3a36 4841 u8 reserved_at_10[0x10];
e281682b 4842
b4ff3a36 4843 u8 reserved_at_20[0x10];
e281682b
SM		 4844 u8 op_mod[0x10];
4845
4846 u8 other_vport[0x1];
b4ff3a36 4847 u8 reserved_at_41[0xf];
e281682b
SM		 4848 u8 vport_number[0x10];
4849
4850 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
4851
b4ff3a36 4852 u8 reserved_at_80[0x780];
e281682b
SM		 4853
4854 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4855};
4856
4857struct mlx5_ifc_modify_hca_vport_context_out_bits {
4858 u8 status[0x8];
b4ff3a36 4859 u8 reserved_at_8[0x18];
e281682b
SM		 4860
4861 u8 syndrome[0x20];
4862
b4ff3a36 4863 u8 reserved_at_40[0x40];
e281682b
SM		 4864};
4865
4866struct mlx5_ifc_modify_hca_vport_context_in_bits {
4867 u8 opcode[0x10];
b4ff3a36 4868 u8 reserved_at_10[0x10];
e281682b 4869
b4ff3a36 4870 u8 reserved_at_20[0x10];
e281682b
SM		 4871 u8 op_mod[0x10];
4872
4873 u8 other_vport[0x1];
b4ff3a36 4874 u8 reserved_at_41[0xb];
707c4602 4875 u8 port_num[0x4];
e281682b
SM		 4876 u8 vport_number[0x10];
4877
b4ff3a36 4878 u8 reserved_at_60[0x20];
e281682b
SM		 4879
4880 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4881};
4882
4883struct mlx5_ifc_modify_cq_out_bits {
4884 u8 status[0x8];
b4ff3a36 4885 u8 reserved_at_8[0x18];
e281682b
SM		 4886
4887 u8 syndrome[0x20];
4888
b4ff3a36 4889 u8 reserved_at_40[0x40];
e281682b
SM		 4890};
4891
4892enum {
4893 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
4894 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
4895};
4896
4897struct mlx5_ifc_modify_cq_in_bits {
4898 u8 opcode[0x10];
b4ff3a36 4899 u8 reserved_at_10[0x10];
e281682b 4900
b4ff3a36 4901 u8 reserved_at_20[0x10];
e281682b
SM		 4902 u8 op_mod[0x10];
4903
b4ff3a36 4904 u8 reserved_at_40[0x8];
e281682b
SM		 4905 u8 cqn[0x18];
4906
4907 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
4908
4909 struct mlx5_ifc_cqc_bits cq_context;
4910
b4ff3a36 4911 u8 reserved_at_280[0x600];
e281682b
SM		 4912
4913 u8 pas[0][0x40];
4914};
4915
4916struct mlx5_ifc_modify_cong_status_out_bits {
4917 u8 status[0x8];
b4ff3a36 4918 u8 reserved_at_8[0x18];
e281682b
SM		 4919
4920 u8 syndrome[0x20];
4921
b4ff3a36 4922 u8 reserved_at_40[0x40];
e281682b
SM		 4923};
4924
4925struct mlx5_ifc_modify_cong_status_in_bits {
4926 u8 opcode[0x10];
b4ff3a36 4927 u8 reserved_at_10[0x10];
e281682b 4928
b4ff3a36 4929 u8 reserved_at_20[0x10];
e281682b
SM		 4930 u8 op_mod[0x10];
4931
b4ff3a36 4932 u8 reserved_at_40[0x18];
e281682b
SM		 4933 u8 priority[0x4];
4934 u8 cong_protocol[0x4];
4935
4936 u8 enable[0x1];
4937 u8 tag_enable[0x1];
b4ff3a36 4938 u8 reserved_at_62[0x1e];
e281682b
SM		 4939};
4940
4941struct mlx5_ifc_modify_cong_params_out_bits {
4942 u8 status[0x8];
b4ff3a36 4943 u8 reserved_at_8[0x18];
e281682b
SM		 4944
4945 u8 syndrome[0x20];
4946
b4ff3a36 4947 u8 reserved_at_40[0x40];
e281682b
SM		 4948};
4949
4950struct mlx5_ifc_modify_cong_params_in_bits {
4951 u8 opcode[0x10];
b4ff3a36 4952 u8 reserved_at_10[0x10];
e281682b 4953
b4ff3a36 4954 u8 reserved_at_20[0x10];
e281682b
SM		 4955 u8 op_mod[0x10];
4956
b4ff3a36 4957 u8 reserved_at_40[0x1c];
e281682b
SM		 4958 u8 cong_protocol[0x4];
4959
4960 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
4961
b4ff3a36 4962 u8 reserved_at_80[0x80];
e281682b
SM		 4963
4964 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4965};
4966
4967struct mlx5_ifc_manage_pages_out_bits {
4968 u8 status[0x8];
b4ff3a36 4969 u8 reserved_at_8[0x18];
e281682b
SM		 4970
4971 u8 syndrome[0x20];
4972
4973 u8 output_num_entries[0x20];
4974
b4ff3a36 4975 u8 reserved_at_60[0x20];
e281682b
SM		 4976
4977 u8 pas[0][0x40];
4978};
4979
4980enum {
4981 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
4982 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
4983 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
4984};
4985
4986struct mlx5_ifc_manage_pages_in_bits {
4987 u8 opcode[0x10];
b4ff3a36 4988 u8 reserved_at_10[0x10];
e281682b 4989
b4ff3a36 4990 u8 reserved_at_20[0x10];
e281682b
SM		 4991 u8 op_mod[0x10];
4992
b4ff3a36 4993 u8 reserved_at_40[0x10];
e281682b
SM		 4994 u8 function_id[0x10];
4995
4996 u8 input_num_entries[0x20];
4997
4998 u8 pas[0][0x40];
4999};
5000
5001struct mlx5_ifc_mad_ifc_out_bits {
5002 u8 status[0x8];
b4ff3a36 5003 u8 reserved_at_8[0x18];
e281682b
SM		 5004
5005 u8 syndrome[0x20];
5006
b4ff3a36 5007 u8 reserved_at_40[0x40];
e281682b
SM		 5008
5009 u8 response_mad_packet[256][0x8];
5010};
5011
5012struct mlx5_ifc_mad_ifc_in_bits {
5013 u8 opcode[0x10];
b4ff3a36 5014 u8 reserved_at_10[0x10];
e281682b 5015
b4ff3a36 5016 u8 reserved_at_20[0x10];
e281682b
SM		 5017 u8 op_mod[0x10];
5018
5019 u8 remote_lid[0x10];
b4ff3a36 5020 u8 reserved_at_50[0x8];
e281682b
SM		 5021 u8 port[0x8];
5022
b4ff3a36 5023 u8 reserved_at_60[0x20];
e281682b
SM		 5024
5025 u8 mad[256][0x8];
5026};
5027
5028struct mlx5_ifc_init_hca_out_bits {
5029 u8 status[0x8];
b4ff3a36 5030 u8 reserved_at_8[0x18];
e281682b
SM		 5031
5032 u8 syndrome[0x20];
5033
b4ff3a36 5034 u8 reserved_at_40[0x40];
e281682b
SM		 5035};
5036
5037struct mlx5_ifc_init_hca_in_bits {
5038 u8 opcode[0x10];
b4ff3a36 5039 u8 reserved_at_10[0x10];
e281682b 5040
b4ff3a36 5041 u8 reserved_at_20[0x10];
e281682b
SM		 5042 u8 op_mod[0x10];
5043
b4ff3a36 5044 u8 reserved_at_40[0x40];
e281682b
SM		 5045};
5046
5047struct mlx5_ifc_init2rtr_qp_out_bits {
5048 u8 status[0x8];
b4ff3a36 5049 u8 reserved_at_8[0x18];
e281682b
SM		 5050
5051 u8 syndrome[0x20];
5052
b4ff3a36 5053 u8 reserved_at_40[0x40];
e281682b
SM		 5054};
5055
5056struct mlx5_ifc_init2rtr_qp_in_bits {
5057 u8 opcode[0x10];
b4ff3a36 5058 u8 reserved_at_10[0x10];
e281682b 5059
b4ff3a36 5060 u8 reserved_at_20[0x10];
e281682b
SM		 5061 u8 op_mod[0x10];
5062
b4ff3a36 5063 u8 reserved_at_40[0x8];
e281682b
SM		 5064 u8 qpn[0x18];
5065
b4ff3a36 5066 u8 reserved_at_60[0x20];
e281682b
SM		 5067
5068 u8 opt_param_mask[0x20];
5069
b4ff3a36 5070 u8 reserved_at_a0[0x20];
e281682b
SM		 5071
5072 struct mlx5_ifc_qpc_bits qpc;
5073
b4ff3a36 5074 u8 reserved_at_800[0x80];
e281682b
SM		 5075};
5076
5077struct mlx5_ifc_init2init_qp_out_bits {
5078 u8 status[0x8];
b4ff3a36 5079 u8 reserved_at_8[0x18];
e281682b
SM		 5080
5081 u8 syndrome[0x20];
5082
b4ff3a36 5083 u8 reserved_at_40[0x40];
e281682b
SM		 5084};
5085
5086struct mlx5_ifc_init2init_qp_in_bits {
5087 u8 opcode[0x10];
b4ff3a36 5088 u8 reserved_at_10[0x10];
e281682b 5089
b4ff3a36 5090 u8 reserved_at_20[0x10];
e281682b
SM		 5091 u8 op_mod[0x10];
5092
b4ff3a36 5093 u8 reserved_at_40[0x8];
e281682b
SM		 5094 u8 qpn[0x18];
5095
b4ff3a36 5096 u8 reserved_at_60[0x20];
e281682b
SM		 5097
5098 u8 opt_param_mask[0x20];
5099
b4ff3a36 5100 u8 reserved_at_a0[0x20];
e281682b
SM		 5101
5102 struct mlx5_ifc_qpc_bits qpc;
5103
b4ff3a36 5104 u8 reserved_at_800[0x80];
e281682b
SM		 5105};
5106
5107struct mlx5_ifc_get_dropped_packet_log_out_bits {
5108 u8 status[0x8];
b4ff3a36 5109 u8 reserved_at_8[0x18];
e281682b
SM		 5110
5111 u8 syndrome[0x20];
5112
b4ff3a36 5113 u8 reserved_at_40[0x40];
e281682b
SM		 5114
5115 u8 packet_headers_log[128][0x8];
5116
5117 u8 packet_syndrome[64][0x8];
5118};
5119
5120struct mlx5_ifc_get_dropped_packet_log_in_bits {
5121 u8 opcode[0x10];
b4ff3a36 5122 u8 reserved_at_10[0x10];
e281682b 5123
b4ff3a36 5124 u8 reserved_at_20[0x10];
e281682b
SM		 5125 u8 op_mod[0x10];
5126
b4ff3a36 5127 u8 reserved_at_40[0x40];
e281682b
SM		 5128};
5129
5130struct mlx5_ifc_gen_eqe_in_bits {
5131 u8 opcode[0x10];
b4ff3a36 5132 u8 reserved_at_10[0x10];
e281682b 5133
b4ff3a36 5134 u8 reserved_at_20[0x10];
e281682b
SM		 5135 u8 op_mod[0x10];
5136
b4ff3a36 5137 u8 reserved_at_40[0x18];
e281682b
SM		 5138 u8 eq_number[0x8];
5139
b4ff3a36 5140 u8 reserved_at_60[0x20];
e281682b
SM		 5141
5142 u8 eqe[64][0x8];
5143};
5144
5145struct mlx5_ifc_gen_eq_out_bits {
5146 u8 status[0x8];
b4ff3a36 5147 u8 reserved_at_8[0x18];
e281682b
SM		 5148
5149 u8 syndrome[0x20];
5150
b4ff3a36 5151 u8 reserved_at_40[0x40];
e281682b
SM		 5152};
5153
5154struct mlx5_ifc_enable_hca_out_bits {
5155 u8 status[0x8];
b4ff3a36 5156 u8 reserved_at_8[0x18];
e281682b
SM		 5157
5158 u8 syndrome[0x20];
5159
b4ff3a36 5160 u8 reserved_at_40[0x20];
e281682b
SM		 5161};
5162
5163struct mlx5_ifc_enable_hca_in_bits {
5164 u8 opcode[0x10];
b4ff3a36 5165 u8 reserved_at_10[0x10];
e281682b 5166
b4ff3a36 5167 u8 reserved_at_20[0x10];
e281682b
SM		 5168 u8 op_mod[0x10];
5169
b4ff3a36 5170 u8 reserved_at_40[0x10];
e281682b
SM		 5171 u8 function_id[0x10];
5172
b4ff3a36 5173 u8 reserved_at_60[0x20];
e281682b
SM		 5174};
5175
5176struct mlx5_ifc_drain_dct_out_bits {
5177 u8 status[0x8];
b4ff3a36 5178 u8 reserved_at_8[0x18];
e281682b
SM		 5179
5180 u8 syndrome[0x20];
5181
b4ff3a36 5182 u8 reserved_at_40[0x40];
e281682b
SM		 5183};
5184
5185struct mlx5_ifc_drain_dct_in_bits {
5186 u8 opcode[0x10];
b4ff3a36 5187 u8 reserved_at_10[0x10];
e281682b 5188
b4ff3a36 5189 u8 reserved_at_20[0x10];
e281682b
SM		 5190 u8 op_mod[0x10];
5191
b4ff3a36 5192 u8 reserved_at_40[0x8];
e281682b
SM		 5193 u8 dctn[0x18];
5194
b4ff3a36 5195 u8 reserved_at_60[0x20];
e281682b
SM		 5196};
5197
5198struct mlx5_ifc_disable_hca_out_bits {
5199 u8 status[0x8];
b4ff3a36 5200 u8 reserved_at_8[0x18];
e281682b
SM		 5201
5202 u8 syndrome[0x20];
5203
b4ff3a36 5204 u8 reserved_at_40[0x20];
e281682b
SM		 5205};
5206
5207struct mlx5_ifc_disable_hca_in_bits {
5208 u8 opcode[0x10];
b4ff3a36 5209 u8 reserved_at_10[0x10];
e281682b 5210
b4ff3a36 5211 u8 reserved_at_20[0x10];
e281682b
SM		 5212 u8 op_mod[0x10];
5213
b4ff3a36 5214 u8 reserved_at_40[0x10];
e281682b
SM		 5215 u8 function_id[0x10];
5216
b4ff3a36 5217 u8 reserved_at_60[0x20];
e281682b
SM		 5218};
5219
5220struct mlx5_ifc_detach_from_mcg_out_bits {
5221 u8 status[0x8];
b4ff3a36 5222 u8 reserved_at_8[0x18];
e281682b
SM		 5223
5224 u8 syndrome[0x20];
5225
b4ff3a36 5226 u8 reserved_at_40[0x40];
e281682b
SM		 5227};
5228
5229struct mlx5_ifc_detach_from_mcg_in_bits {
5230 u8 opcode[0x10];
b4ff3a36 5231 u8 reserved_at_10[0x10];
e281682b 5232
b4ff3a36 5233 u8 reserved_at_20[0x10];
e281682b
SM		 5234 u8 op_mod[0x10];
5235
b4ff3a36 5236 u8 reserved_at_40[0x8];
e281682b
SM		 5237 u8 qpn[0x18];
5238
b4ff3a36 5239 u8 reserved_at_60[0x20];
e281682b
SM		 5240
5241 u8 multicast_gid[16][0x8];
5242};
5243
7486216b
SM		 5244struct mlx5_ifc_destroy_xrq_out_bits {
5245 u8 status[0x8];
5246 u8 reserved_at_8[0x18];
5247
5248 u8 syndrome[0x20];
5249
5250 u8 reserved_at_40[0x40];
5251};
5252
5253struct mlx5_ifc_destroy_xrq_in_bits {
5254 u8 opcode[0x10];
5255 u8 reserved_at_10[0x10];
5256
5257 u8 reserved_at_20[0x10];
5258 u8 op_mod[0x10];
5259
5260 u8 reserved_at_40[0x8];
5261 u8 xrqn[0x18];
5262
5263 u8 reserved_at_60[0x20];
5264};
5265
e281682b
SM		 5266struct mlx5_ifc_destroy_xrc_srq_out_bits {
5267 u8 status[0x8];
b4ff3a36 5268 u8 reserved_at_8[0x18];
e281682b
SM		 5269
5270 u8 syndrome[0x20];
5271
b4ff3a36 5272 u8 reserved_at_40[0x40];
e281682b
SM		 5273};
5274
5275struct mlx5_ifc_destroy_xrc_srq_in_bits {
5276 u8 opcode[0x10];
b4ff3a36 5277 u8 reserved_at_10[0x10];
e281682b 5278
b4ff3a36 5279 u8 reserved_at_20[0x10];
e281682b
SM		 5280 u8 op_mod[0x10];
5281
b4ff3a36 5282 u8 reserved_at_40[0x8];
e281682b
SM		 5283 u8 xrc_srqn[0x18];
5284
b4ff3a36 5285 u8 reserved_at_60[0x20];
e281682b
SM		 5286};
5287
5288struct mlx5_ifc_destroy_tis_out_bits {
5289 u8 status[0x8];
b4ff3a36 5290 u8 reserved_at_8[0x18];
e281682b
SM		 5291
5292 u8 syndrome[0x20];
5293
b4ff3a36 5294 u8 reserved_at_40[0x40];
e281682b
SM		 5295};
5296
5297struct mlx5_ifc_destroy_tis_in_bits {
5298 u8 opcode[0x10];
b4ff3a36 5299 u8 reserved_at_10[0x10];
e281682b 5300
b4ff3a36 5301 u8 reserved_at_20[0x10];
e281682b
SM		 5302 u8 op_mod[0x10];
5303
b4ff3a36 5304 u8 reserved_at_40[0x8];
e281682b
SM		 5305 u8 tisn[0x18];
5306
b4ff3a36 5307 u8 reserved_at_60[0x20];
e281682b
SM		 5308};
5309
5310struct mlx5_ifc_destroy_tir_out_bits {
5311 u8 status[0x8];
b4ff3a36 5312 u8 reserved_at_8[0x18];
e281682b
SM		 5313
5314 u8 syndrome[0x20];
5315
b4ff3a36 5316 u8 reserved_at_40[0x40];
e281682b
SM		 5317};
5318
5319struct mlx5_ifc_destroy_tir_in_bits {
5320 u8 opcode[0x10];
b4ff3a36 5321 u8 reserved_at_10[0x10];
e281682b 5322
b4ff3a36 5323 u8 reserved_at_20[0x10];
e281682b
SM		 5324 u8 op_mod[0x10];
5325
b4ff3a36 5326 u8 reserved_at_40[0x8];
e281682b
SM		 5327 u8 tirn[0x18];
5328
b4ff3a36 5329 u8 reserved_at_60[0x20];
e281682b
SM		 5330};
5331
5332struct mlx5_ifc_destroy_srq_out_bits {
5333 u8 status[0x8];
b4ff3a36 5334 u8 reserved_at_8[0x18];
e281682b
SM		 5335
5336 u8 syndrome[0x20];
5337
b4ff3a36 5338 u8 reserved_at_40[0x40];
e281682b
SM		 5339};
5340
5341struct mlx5_ifc_destroy_srq_in_bits {
5342 u8 opcode[0x10];
b4ff3a36 5343 u8 reserved_at_10[0x10];
e281682b 5344
b4ff3a36 5345 u8 reserved_at_20[0x10];
e281682b
SM		 5346 u8 op_mod[0x10];
5347
b4ff3a36 5348 u8 reserved_at_40[0x8];
e281682b
SM		 5349 u8 srqn[0x18];
5350
b4ff3a36 5351 u8 reserved_at_60[0x20];
e281682b
SM		 5352};
5353
5354struct mlx5_ifc_destroy_sq_out_bits {
5355 u8 status[0x8];
b4ff3a36 5356 u8 reserved_at_8[0x18];
e281682b
SM		 5357
5358 u8 syndrome[0x20];
5359
b4ff3a36 5360 u8 reserved_at_40[0x40];
e281682b
SM		 5361};
5362
5363struct mlx5_ifc_destroy_sq_in_bits {
5364 u8 opcode[0x10];
b4ff3a36 5365 u8 reserved_at_10[0x10];
e281682b 5366
b4ff3a36 5367 u8 reserved_at_20[0x10];
e281682b
SM		 5368 u8 op_mod[0x10];
5369
b4ff3a36 5370 u8 reserved_at_40[0x8];
e281682b
SM		 5371 u8 sqn[0x18];
5372
b4ff3a36 5373 u8 reserved_at_60[0x20];
e281682b
SM		 5374};
5375
5376struct mlx5_ifc_destroy_rqt_out_bits {
5377 u8 status[0x8];
b4ff3a36 5378 u8 reserved_at_8[0x18];
e281682b
SM		 5379
5380 u8 syndrome[0x20];
5381
b4ff3a36 5382 u8 reserved_at_40[0x40];
e281682b
SM		 5383};
5384
5385struct mlx5_ifc_destroy_rqt_in_bits {
5386 u8 opcode[0x10];
b4ff3a36 5387 u8 reserved_at_10[0x10];
e281682b 5388
b4ff3a36 5389 u8 reserved_at_20[0x10];
e281682b
SM		 5390 u8 op_mod[0x10];
5391
b4ff3a36 5392 u8 reserved_at_40[0x8];
e281682b
SM		 5393 u8 rqtn[0x18];
5394
b4ff3a36 5395 u8 reserved_at_60[0x20];
e281682b
SM		 5396};
5397
5398struct mlx5_ifc_destroy_rq_out_bits {
5399 u8 status[0x8];
b4ff3a36 5400 u8 reserved_at_8[0x18];
e281682b
SM		 5401
5402 u8 syndrome[0x20];
5403
b4ff3a36 5404 u8 reserved_at_40[0x40];
e281682b
SM		 5405};
5406
5407struct mlx5_ifc_destroy_rq_in_bits {
5408 u8 opcode[0x10];
b4ff3a36 5409 u8 reserved_at_10[0x10];
e281682b 5410
b4ff3a36 5411 u8 reserved_at_20[0x10];
e281682b
SM		 5412 u8 op_mod[0x10];
5413
b4ff3a36 5414 u8 reserved_at_40[0x8];
e281682b
SM		 5415 u8 rqn[0x18];
5416
b4ff3a36 5417 u8 reserved_at_60[0x20];
e281682b
SM		 5418};
5419
5420struct mlx5_ifc_destroy_rmp_out_bits {
5421 u8 status[0x8];
b4ff3a36 5422 u8 reserved_at_8[0x18];
e281682b
SM		 5423
5424 u8 syndrome[0x20];
5425
b4ff3a36 5426 u8 reserved_at_40[0x40];
e281682b
SM		 5427};
5428
5429struct mlx5_ifc_destroy_rmp_in_bits {
5430 u8 opcode[0x10];
b4ff3a36 5431 u8 reserved_at_10[0x10];
e281682b 5432
b4ff3a36 5433 u8 reserved_at_20[0x10];
e281682b
SM		 5434 u8 op_mod[0x10];
5435
b4ff3a36 5436 u8 reserved_at_40[0x8];
e281682b
SM		 5437 u8 rmpn[0x18];
5438
b4ff3a36 5439 u8 reserved_at_60[0x20];
e281682b
SM		 5440};
5441
5442struct mlx5_ifc_destroy_qp_out_bits {
5443 u8 status[0x8];
b4ff3a36 5444 u8 reserved_at_8[0x18];
e281682b
SM		 5445
5446 u8 syndrome[0x20];
5447
b4ff3a36 5448 u8 reserved_at_40[0x40];
e281682b
SM		 5449};
5450
5451struct mlx5_ifc_destroy_qp_in_bits {
5452 u8 opcode[0x10];
b4ff3a36 5453 u8 reserved_at_10[0x10];
e281682b 5454
b4ff3a36 5455 u8 reserved_at_20[0x10];
e281682b
SM		 5456 u8 op_mod[0x10];
5457
b4ff3a36 5458 u8 reserved_at_40[0x8];
e281682b
SM		 5459 u8 qpn[0x18];
5460
b4ff3a36 5461 u8 reserved_at_60[0x20];
e281682b
SM		 5462};
5463
5464struct mlx5_ifc_destroy_psv_out_bits {
5465 u8 status[0x8];
b4ff3a36 5466 u8 reserved_at_8[0x18];
e281682b
SM		 5467
5468 u8 syndrome[0x20];
5469
b4ff3a36 5470 u8 reserved_at_40[0x40];
e281682b
SM		 5471};
5472
5473struct mlx5_ifc_destroy_psv_in_bits {
5474 u8 opcode[0x10];
b4ff3a36 5475 u8 reserved_at_10[0x10];
e281682b 5476
b4ff3a36 5477 u8 reserved_at_20[0x10];
e281682b
SM		 5478 u8 op_mod[0x10];
5479
b4ff3a36 5480 u8 reserved_at_40[0x8];
e281682b
SM		 5481 u8 psvn[0x18];
5482
b4ff3a36 5483 u8 reserved_at_60[0x20];
e281682b
SM		 5484};
5485
5486struct mlx5_ifc_destroy_mkey_out_bits {
5487 u8 status[0x8];
b4ff3a36 5488 u8 reserved_at_8[0x18];
e281682b
SM		 5489
5490 u8 syndrome[0x20];
5491
b4ff3a36 5492 u8 reserved_at_40[0x40];
e281682b
SM		 5493};
5494
5495struct mlx5_ifc_destroy_mkey_in_bits {
5496 u8 opcode[0x10];
b4ff3a36 5497 u8 reserved_at_10[0x10];
e281682b 5498
b4ff3a36 5499 u8 reserved_at_20[0x10];
e281682b
SM		 5500 u8 op_mod[0x10];
5501
b4ff3a36 5502 u8 reserved_at_40[0x8];
e281682b
SM		 5503 u8 mkey_index[0x18];
5504
b4ff3a36 5505 u8 reserved_at_60[0x20];
e281682b
SM		 5506};
5507
5508struct mlx5_ifc_destroy_flow_table_out_bits {
5509 u8 status[0x8];
b4ff3a36 5510 u8 reserved_at_8[0x18];
e281682b
SM		 5511
5512 u8 syndrome[0x20];
5513
b4ff3a36 5514 u8 reserved_at_40[0x40];
e281682b
SM		 5515};
5516
5517struct mlx5_ifc_destroy_flow_table_in_bits {
5518 u8 opcode[0x10];
b4ff3a36 5519 u8 reserved_at_10[0x10];
e281682b 5520
b4ff3a36 5521 u8 reserved_at_20[0x10];
e281682b
SM		 5522 u8 op_mod[0x10];
5523
7d5e1423
SM		 5524 u8 other_vport[0x1];
5525 u8 reserved_at_41[0xf];
5526 u8 vport_number[0x10];
5527
5528 u8 reserved_at_60[0x20];
e281682b
SM		 5529
5530 u8 table_type[0x8];
b4ff3a36 5531 u8 reserved_at_88[0x18];
e281682b 5532
b4ff3a36 5533 u8 reserved_at_a0[0x8];
e281682b
SM		 5534 u8 table_id[0x18];
5535
b4ff3a36 5536 u8 reserved_at_c0[0x140];
e281682b
SM		 5537};
5538
5539struct mlx5_ifc_destroy_flow_group_out_bits {
5540 u8 status[0x8];
b4ff3a36 5541 u8 reserved_at_8[0x18];
e281682b
SM		 5542
5543 u8 syndrome[0x20];
5544
b4ff3a36 5545 u8 reserved_at_40[0x40];
e281682b
SM		 5546};
5547
5548struct mlx5_ifc_destroy_flow_group_in_bits {
5549 u8 opcode[0x10];
b4ff3a36 5550 u8 reserved_at_10[0x10];
e281682b 5551
b4ff3a36 5552 u8 reserved_at_20[0x10];
e281682b
SM		 5553 u8 op_mod[0x10];
5554
7d5e1423
SM		 5555 u8 other_vport[0x1];
5556 u8 reserved_at_41[0xf];
5557 u8 vport_number[0x10];
5558
5559 u8 reserved_at_60[0x20];
e281682b
SM		 5560
5561 u8 table_type[0x8];
b4ff3a36 5562 u8 reserved_at_88[0x18];
e281682b 5563
b4ff3a36 5564 u8 reserved_at_a0[0x8];
e281682b
SM		 5565 u8 table_id[0x18];
5566
5567 u8 group_id[0x20];
5568
b4ff3a36 5569 u8 reserved_at_e0[0x120];
e281682b
SM		 5570};
5571
5572struct mlx5_ifc_destroy_eq_out_bits {
5573 u8 status[0x8];
b4ff3a36 5574 u8 reserved_at_8[0x18];
e281682b
SM		 5575
5576 u8 syndrome[0x20];
5577
b4ff3a36 5578 u8 reserved_at_40[0x40];
e281682b
SM		 5579};
5580
5581struct mlx5_ifc_destroy_eq_in_bits {
5582 u8 opcode[0x10];
b4ff3a36 5583 u8 reserved_at_10[0x10];
e281682b 5584
b4ff3a36 5585 u8 reserved_at_20[0x10];
e281682b
SM		 5586 u8 op_mod[0x10];
5587
b4ff3a36 5588 u8 reserved_at_40[0x18];
e281682b
SM		 5589 u8 eq_number[0x8];
5590
b4ff3a36 5591 u8 reserved_at_60[0x20];
e281682b
SM		 5592};
5593
5594struct mlx5_ifc_destroy_dct_out_bits {
5595 u8 status[0x8];
b4ff3a36 5596 u8 reserved_at_8[0x18];
e281682b
SM		 5597
5598 u8 syndrome[0x20];
5599
b4ff3a36 5600 u8 reserved_at_40[0x40];
e281682b
SM		 5601};
5602
5603struct mlx5_ifc_destroy_dct_in_bits {
5604 u8 opcode[0x10];
b4ff3a36 5605 u8 reserved_at_10[0x10];
e281682b 5606
b4ff3a36 5607 u8 reserved_at_20[0x10];
e281682b
SM		 5608 u8 op_mod[0x10];
5609
b4ff3a36 5610 u8 reserved_at_40[0x8];
e281682b
SM		 5611 u8 dctn[0x18];
5612
b4ff3a36 5613 u8 reserved_at_60[0x20];
e281682b
SM		 5614};
5615
5616struct mlx5_ifc_destroy_cq_out_bits {
5617 u8 status[0x8];
b4ff3a36 5618 u8 reserved_at_8[0x18];
e281682b
SM		 5619
5620 u8 syndrome[0x20];
5621
b4ff3a36 5622 u8 reserved_at_40[0x40];
e281682b
SM		 5623};
5624
5625struct mlx5_ifc_destroy_cq_in_bits {
5626 u8 opcode[0x10];
b4ff3a36 5627 u8 reserved_at_10[0x10];
e281682b 5628
b4ff3a36 5629 u8 reserved_at_20[0x10];
e281682b
SM		 5630 u8 op_mod[0x10];
5631
b4ff3a36 5632 u8 reserved_at_40[0x8];
e281682b
SM		 5633 u8 cqn[0x18];
5634
b4ff3a36 5635 u8 reserved_at_60[0x20];
e281682b
SM		 5636};
5637
5638struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
5639 u8 status[0x8];
b4ff3a36 5640 u8 reserved_at_8[0x18];
e281682b
SM		 5641
5642 u8 syndrome[0x20];
5643
b4ff3a36 5644 u8 reserved_at_40[0x40];
e281682b
SM		 5645};
5646
5647struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
5648 u8 opcode[0x10];
b4ff3a36 5649 u8 reserved_at_10[0x10];
e281682b 5650
b4ff3a36 5651 u8 reserved_at_20[0x10];
e281682b
SM		 5652 u8 op_mod[0x10];
5653
b4ff3a36 5654 u8 reserved_at_40[0x20];
e281682b 5655
b4ff3a36 5656 u8 reserved_at_60[0x10];
e281682b
SM		 5657 u8 vxlan_udp_port[0x10];
5658};
5659
5660struct mlx5_ifc_delete_l2_table_entry_out_bits {
5661 u8 status[0x8];
b4ff3a36 5662 u8 reserved_at_8[0x18];
e281682b
SM		 5663
5664 u8 syndrome[0x20];
5665
b4ff3a36 5666 u8 reserved_at_40[0x40];
e281682b
SM		 5667};
5668
5669struct mlx5_ifc_delete_l2_table_entry_in_bits {
5670 u8 opcode[0x10];
b4ff3a36 5671 u8 reserved_at_10[0x10];
e281682b 5672
b4ff3a36 5673 u8 reserved_at_20[0x10];
e281682b
SM		 5674 u8 op_mod[0x10];
5675
b4ff3a36 5676 u8 reserved_at_40[0x60];
e281682b 5677
b4ff3a36 5678 u8 reserved_at_a0[0x8];
e281682b
SM		 5679 u8 table_index[0x18];
5680
b4ff3a36 5681 u8 reserved_at_c0[0x140];
e281682b
SM		 5682};
5683
5684struct mlx5_ifc_delete_fte_out_bits {
5685 u8 status[0x8];
b4ff3a36 5686 u8 reserved_at_8[0x18];
e281682b
SM		 5687
5688 u8 syndrome[0x20];
5689
b4ff3a36 5690 u8 reserved_at_40[0x40];
e281682b
SM		 5691};
5692
5693struct mlx5_ifc_delete_fte_in_bits {
5694 u8 opcode[0x10];
b4ff3a36 5695 u8 reserved_at_10[0x10];
e281682b 5696
b4ff3a36 5697 u8 reserved_at_20[0x10];
e281682b
SM		 5698 u8 op_mod[0x10];
5699
7d5e1423
SM		 5700 u8 other_vport[0x1];
5701 u8 reserved_at_41[0xf];
5702 u8 vport_number[0x10];
5703
5704 u8 reserved_at_60[0x20];
e281682b
SM		 5705
5706 u8 table_type[0x8];
b4ff3a36 5707 u8 reserved_at_88[0x18];
e281682b 5708
b4ff3a36 5709 u8 reserved_at_a0[0x8];
e281682b
SM		 5710 u8 table_id[0x18];
5711
b4ff3a36 5712 u8 reserved_at_c0[0x40];
e281682b
SM		 5713
5714 u8 flow_index[0x20];
5715
b4ff3a36 5716 u8 reserved_at_120[0xe0];
e281682b
SM		 5717};
5718
5719struct mlx5_ifc_dealloc_xrcd_out_bits {
5720 u8 status[0x8];
b4ff3a36 5721 u8 reserved_at_8[0x18];
e281682b
SM		 5722
5723 u8 syndrome[0x20];
5724
b4ff3a36 5725 u8 reserved_at_40[0x40];
e281682b
SM		 5726};
5727
5728struct mlx5_ifc_dealloc_xrcd_in_bits {
5729 u8 opcode[0x10];
b4ff3a36 5730 u8 reserved_at_10[0x10];
e281682b 5731
b4ff3a36 5732 u8 reserved_at_20[0x10];
e281682b
SM		 5733 u8 op_mod[0x10];
5734
b4ff3a36 5735 u8 reserved_at_40[0x8];
e281682b
SM		 5736 u8 xrcd[0x18];
5737
b4ff3a36 5738 u8 reserved_at_60[0x20];
e281682b
SM		 5739};
5740
5741struct mlx5_ifc_dealloc_uar_out_bits {
5742 u8 status[0x8];
b4ff3a36 5743 u8 reserved_at_8[0x18];
e281682b
SM		 5744
5745 u8 syndrome[0x20];
5746
b4ff3a36 5747 u8 reserved_at_40[0x40];
e281682b
SM		 5748};
5749
5750struct mlx5_ifc_dealloc_uar_in_bits {
5751 u8 opcode[0x10];
b4ff3a36 5752 u8 reserved_at_10[0x10];
e281682b 5753
b4ff3a36 5754 u8 reserved_at_20[0x10];
e281682b
SM		 5755 u8 op_mod[0x10];
5756
b4ff3a36 5757 u8 reserved_at_40[0x8];
e281682b
SM		 5758 u8 uar[0x18];
5759
b4ff3a36 5760 u8 reserved_at_60[0x20];
e281682b
SM		 5761};
5762
5763struct mlx5_ifc_dealloc_transport_domain_out_bits {
5764 u8 status[0x8];
b4ff3a36 5765 u8 reserved_at_8[0x18];
e281682b
SM		 5766
5767 u8 syndrome[0x20];
5768
b4ff3a36 5769 u8 reserved_at_40[0x40];
e281682b
SM		 5770};
5771
5772struct mlx5_ifc_dealloc_transport_domain_in_bits {
5773 u8 opcode[0x10];
b4ff3a36 5774 u8 reserved_at_10[0x10];
e281682b 5775
b4ff3a36 5776 u8 reserved_at_20[0x10];
e281682b
SM		 5777 u8 op_mod[0x10];
5778
b4ff3a36 5779 u8 reserved_at_40[0x8];
e281682b
SM		 5780 u8 transport_domain[0x18];
5781
b4ff3a36 5782 u8 reserved_at_60[0x20];
e281682b
SM		 5783};
5784
5785struct mlx5_ifc_dealloc_q_counter_out_bits {
5786 u8 status[0x8];
b4ff3a36 5787 u8 reserved_at_8[0x18];
e281682b
SM		 5788
5789 u8 syndrome[0x20];
5790
b4ff3a36 5791 u8 reserved_at_40[0x40];
e281682b
SM		 5792};
5793
5794struct mlx5_ifc_dealloc_q_counter_in_bits {
5795 u8 opcode[0x10];
b4ff3a36 5796 u8 reserved_at_10[0x10];
e281682b 5797
b4ff3a36 5798 u8 reserved_at_20[0x10];
e281682b
SM		 5799 u8 op_mod[0x10];
5800
b4ff3a36 5801 u8 reserved_at_40[0x18];
e281682b
SM		 5802 u8 counter_set_id[0x8];
5803
b4ff3a36 5804 u8 reserved_at_60[0x20];
e281682b
SM		 5805};
5806
5807struct mlx5_ifc_dealloc_pd_out_bits {
5808 u8 status[0x8];
b4ff3a36 5809 u8 reserved_at_8[0x18];
e281682b
SM		 5810
5811 u8 syndrome[0x20];
5812
b4ff3a36 5813 u8 reserved_at_40[0x40];
e281682b
SM		 5814};
5815
5816struct mlx5_ifc_dealloc_pd_in_bits {
5817 u8 opcode[0x10];
b4ff3a36 5818 u8 reserved_at_10[0x10];
e281682b 5819
b4ff3a36 5820 u8 reserved_at_20[0x10];
e281682b
SM		 5821 u8 op_mod[0x10];
5822
b4ff3a36 5823 u8 reserved_at_40[0x8];
e281682b
SM		 5824 u8 pd[0x18];
5825
b4ff3a36 5826 u8 reserved_at_60[0x20];
e281682b
SM		 5827};
5828
9dc0b289
AV		 5829struct mlx5_ifc_dealloc_flow_counter_out_bits {
5830 u8 status[0x8];
5831 u8 reserved_at_8[0x18];
5832
5833 u8 syndrome[0x20];
5834
5835 u8 reserved_at_40[0x40];
5836};
5837
5838struct mlx5_ifc_dealloc_flow_counter_in_bits {
5839 u8 opcode[0x10];
5840 u8 reserved_at_10[0x10];
5841
5842 u8 reserved_at_20[0x10];
5843 u8 op_mod[0x10];
5844
5845 u8 reserved_at_40[0x10];
5846 u8 flow_counter_id[0x10];
5847
5848 u8 reserved_at_60[0x20];
5849};
5850
7486216b
SM		 5851struct mlx5_ifc_create_xrq_out_bits {
5852 u8 status[0x8];
5853 u8 reserved_at_8[0x18];
5854
5855 u8 syndrome[0x20];
5856
5857 u8 reserved_at_40[0x8];
5858 u8 xrqn[0x18];
5859
5860 u8 reserved_at_60[0x20];
5861};
5862
5863struct mlx5_ifc_create_xrq_in_bits {
5864 u8 opcode[0x10];
5865 u8 reserved_at_10[0x10];
5866
5867 u8 reserved_at_20[0x10];
5868 u8 op_mod[0x10];
5869
5870 u8 reserved_at_40[0x40];
5871
5872 struct mlx5_ifc_xrqc_bits xrq_context;
5873};
5874
e281682b
SM		 5875struct mlx5_ifc_create_xrc_srq_out_bits {
5876 u8 status[0x8];
b4ff3a36 5877 u8 reserved_at_8[0x18];
e281682b
SM		 5878
5879 u8 syndrome[0x20];
5880
b4ff3a36 5881 u8 reserved_at_40[0x8];
e281682b
SM		 5882 u8 xrc_srqn[0x18];
5883
b4ff3a36 5884 u8 reserved_at_60[0x20];
e281682b
SM		 5885};
5886
5887struct mlx5_ifc_create_xrc_srq_in_bits {
5888 u8 opcode[0x10];
b4ff3a36 5889 u8 reserved_at_10[0x10];
e281682b 5890
b4ff3a36 5891 u8 reserved_at_20[0x10];
e281682b
SM		 5892 u8 op_mod[0x10];
5893
b4ff3a36 5894 u8 reserved_at_40[0x40];
e281682b
SM		 5895
5896 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
5897
b4ff3a36 5898 u8 reserved_at_280[0x600];
e281682b
SM		 5899
5900 u8 pas[0][0x40];
5901};
5902
5903struct mlx5_ifc_create_tis_out_bits {
5904 u8 status[0x8];
b4ff3a36 5905 u8 reserved_at_8[0x18];
e281682b
SM		 5906
5907 u8 syndrome[0x20];
5908
b4ff3a36 5909 u8 reserved_at_40[0x8];
e281682b
SM		 5910 u8 tisn[0x18];
5911
b4ff3a36 5912 u8 reserved_at_60[0x20];
e281682b
SM		 5913};
5914
5915struct mlx5_ifc_create_tis_in_bits {
5916 u8 opcode[0x10];
b4ff3a36 5917 u8 reserved_at_10[0x10];
e281682b 5918
b4ff3a36 5919 u8 reserved_at_20[0x10];
e281682b
SM		 5920 u8 op_mod[0x10];
5921
b4ff3a36 5922 u8 reserved_at_40[0xc0];
e281682b
SM		 5923
5924 struct mlx5_ifc_tisc_bits ctx;
5925};
5926
5927struct mlx5_ifc_create_tir_out_bits {
5928 u8 status[0x8];
b4ff3a36 5929 u8 reserved_at_8[0x18];
e281682b
SM		 5930
5931 u8 syndrome[0x20];
5932
b4ff3a36 5933 u8 reserved_at_40[0x8];
e281682b
SM		 5934 u8 tirn[0x18];
5935
b4ff3a36 5936 u8 reserved_at_60[0x20];
e281682b
SM		 5937};
5938
5939struct mlx5_ifc_create_tir_in_bits {
5940 u8 opcode[0x10];
b4ff3a36 5941 u8 reserved_at_10[0x10];
e281682b 5942
b4ff3a36 5943 u8 reserved_at_20[0x10];
e281682b
SM		 5944 u8 op_mod[0x10];
5945
b4ff3a36 5946 u8 reserved_at_40[0xc0];
e281682b
SM		 5947
5948 struct mlx5_ifc_tirc_bits ctx;
5949};
5950
5951struct mlx5_ifc_create_srq_out_bits {
5952 u8 status[0x8];
b4ff3a36 5953 u8 reserved_at_8[0x18];
e281682b
SM		 5954
5955 u8 syndrome[0x20];
5956
b4ff3a36 5957 u8 reserved_at_40[0x8];
e281682b
SM		 5958 u8 srqn[0x18];
5959
b4ff3a36 5960 u8 reserved_at_60[0x20];
e281682b
SM		 5961};
5962
5963struct mlx5_ifc_create_srq_in_bits {
5964 u8 opcode[0x10];
b4ff3a36 5965 u8 reserved_at_10[0x10];
e281682b 5966
b4ff3a36 5967 u8 reserved_at_20[0x10];
e281682b
SM		 5968 u8 op_mod[0x10];
5969
b4ff3a36 5970 u8 reserved_at_40[0x40];
e281682b
SM		 5971
5972 struct mlx5_ifc_srqc_bits srq_context_entry;
5973
b4ff3a36 5974 u8 reserved_at_280[0x600];
e281682b
SM		 5975
5976 u8 pas[0][0x40];
5977};
5978
5979struct mlx5_ifc_create_sq_out_bits {
5980 u8 status[0x8];
b4ff3a36 5981 u8 reserved_at_8[0x18];
e281682b
SM		 5982
5983 u8 syndrome[0x20];
5984
b4ff3a36 5985 u8 reserved_at_40[0x8];
e281682b
SM		 5986 u8 sqn[0x18];
5987
b4ff3a36 5988 u8 reserved_at_60[0x20];
e281682b
SM		 5989};
5990
5991struct mlx5_ifc_create_sq_in_bits {
5992 u8 opcode[0x10];
b4ff3a36 5993 u8 reserved_at_10[0x10];
e281682b 5994
b4ff3a36 5995 u8 reserved_at_20[0x10];
e281682b
SM		 5996 u8 op_mod[0x10];
5997
b4ff3a36 5998 u8 reserved_at_40[0xc0];
e281682b
SM		 5999
6000 struct mlx5_ifc_sqc_bits ctx;
6001};
6002
6003struct mlx5_ifc_create_rqt_out_bits {
6004 u8 status[0x8];
b4ff3a36 6005 u8 reserved_at_8[0x18];
e281682b
SM		 6006
6007 u8 syndrome[0x20];
6008
b4ff3a36 6009 u8 reserved_at_40[0x8];
e281682b
SM		 6010 u8 rqtn[0x18];
6011
b4ff3a36 6012 u8 reserved_at_60[0x20];
e281682b
SM		 6013};
6014
6015struct mlx5_ifc_create_rqt_in_bits {
6016 u8 opcode[0x10];
b4ff3a36 6017 u8 reserved_at_10[0x10];
e281682b 6018
b4ff3a36 6019 u8 reserved_at_20[0x10];
e281682b
SM		 6020 u8 op_mod[0x10];
6021
b4ff3a36 6022 u8 reserved_at_40[0xc0];
e281682b
SM		 6023
6024 struct mlx5_ifc_rqtc_bits rqt_context;
6025};
6026
6027struct mlx5_ifc_create_rq_out_bits {
6028 u8 status[0x8];
b4ff3a36 6029 u8 reserved_at_8[0x18];
e281682b
SM		 6030
6031 u8 syndrome[0x20];
6032
b4ff3a36 6033 u8 reserved_at_40[0x8];
e281682b
SM		 6034 u8 rqn[0x18];
6035
b4ff3a36 6036 u8 reserved_at_60[0x20];
e281682b
SM		 6037};
6038
6039struct mlx5_ifc_create_rq_in_bits {
6040 u8 opcode[0x10];
b4ff3a36 6041 u8 reserved_at_10[0x10];
e281682b 6042
b4ff3a36 6043 u8 reserved_at_20[0x10];
e281682b
SM		 6044 u8 op_mod[0x10];
6045
b4ff3a36 6046 u8 reserved_at_40[0xc0];
e281682b
SM		 6047
6048 struct mlx5_ifc_rqc_bits ctx;
6049};
6050
6051struct mlx5_ifc_create_rmp_out_bits {
6052 u8 status[0x8];
b4ff3a36 6053 u8 reserved_at_8[0x18];
e281682b
SM		 6054
6055 u8 syndrome[0x20];
6056
b4ff3a36 6057 u8 reserved_at_40[0x8];
e281682b
SM		 6058 u8 rmpn[0x18];
6059
b4ff3a36 6060 u8 reserved_at_60[0x20];
e281682b
SM		 6061};
6062
6063struct mlx5_ifc_create_rmp_in_bits {
6064 u8 opcode[0x10];
b4ff3a36 6065 u8 reserved_at_10[0x10];
e281682b 6066
b4ff3a36 6067 u8 reserved_at_20[0x10];
e281682b
SM		 6068 u8 op_mod[0x10];
6069
b4ff3a36 6070 u8 reserved_at_40[0xc0];
e281682b
SM		 6071
6072 struct mlx5_ifc_rmpc_bits ctx;
6073};
6074
6075struct mlx5_ifc_create_qp_out_bits {
6076 u8 status[0x8];
b4ff3a36 6077 u8 reserved_at_8[0x18];
e281682b
SM		 6078
6079 u8 syndrome[0x20];
6080
b4ff3a36 6081 u8 reserved_at_40[0x8];
e281682b
SM		 6082 u8 qpn[0x18];
6083
b4ff3a36 6084 u8 reserved_at_60[0x20];
e281682b
SM		 6085};
6086
6087struct mlx5_ifc_create_qp_in_bits {
6088 u8 opcode[0x10];
b4ff3a36 6089 u8 reserved_at_10[0x10];
e281682b 6090
b4ff3a36 6091 u8 reserved_at_20[0x10];
e281682b
SM		 6092 u8 op_mod[0x10];
6093
b4ff3a36 6094 u8 reserved_at_40[0x40];
e281682b
SM		 6095
6096 u8 opt_param_mask[0x20];
6097
b4ff3a36 6098 u8 reserved_at_a0[0x20];
e281682b
SM		 6099
6100 struct mlx5_ifc_qpc_bits qpc;
6101
b4ff3a36 6102 u8 reserved_at_800[0x80];
e281682b
SM		 6103
6104 u8 pas[0][0x40];
6105};
6106
6107struct mlx5_ifc_create_psv_out_bits {
6108 u8 status[0x8];
b4ff3a36 6109 u8 reserved_at_8[0x18];
e281682b
SM		 6110
6111 u8 syndrome[0x20];
6112
b4ff3a36 6113 u8 reserved_at_40[0x40];
e281682b 6114
b4ff3a36 6115 u8 reserved_at_80[0x8];
e281682b
SM		 6116 u8 psv0_index[0x18];
6117
b4ff3a36 6118 u8 reserved_at_a0[0x8];
e281682b
SM		 6119 u8 psv1_index[0x18];
6120
b4ff3a36 6121 u8 reserved_at_c0[0x8];
e281682b
SM		 6122 u8 psv2_index[0x18];
6123
b4ff3a36 6124 u8 reserved_at_e0[0x8];
e281682b
SM		 6125 u8 psv3_index[0x18];
6126};
6127
6128struct mlx5_ifc_create_psv_in_bits {
6129 u8 opcode[0x10];
b4ff3a36 6130 u8 reserved_at_10[0x10];
e281682b 6131
b4ff3a36 6132 u8 reserved_at_20[0x10];
e281682b
SM		 6133 u8 op_mod[0x10];
6134
6135 u8 num_psv[0x4];
b4ff3a36 6136 u8 reserved_at_44[0x4];
e281682b
SM		 6137 u8 pd[0x18];
6138
b4ff3a36 6139 u8 reserved_at_60[0x20];
e281682b
SM		 6140};
6141
6142struct mlx5_ifc_create_mkey_out_bits {
6143 u8 status[0x8];
b4ff3a36 6144 u8 reserved_at_8[0x18];
e281682b
SM		 6145
6146 u8 syndrome[0x20];
6147
b4ff3a36 6148 u8 reserved_at_40[0x8];
e281682b
SM		 6149 u8 mkey_index[0x18];
6150
b4ff3a36 6151 u8 reserved_at_60[0x20];
e281682b
SM		 6152};
6153
6154struct mlx5_ifc_create_mkey_in_bits {
6155 u8 opcode[0x10];
b4ff3a36 6156 u8 reserved_at_10[0x10];
e281682b 6157
b4ff3a36 6158 u8 reserved_at_20[0x10];
e281682b
SM		 6159 u8 op_mod[0x10];
6160
b4ff3a36 6161 u8 reserved_at_40[0x20];
e281682b
SM		 6162
6163 u8 pg_access[0x1];
b4ff3a36 6164 u8 reserved_at_61[0x1f];
e281682b
SM		 6165
6166 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
6167
b4ff3a36 6168 u8 reserved_at_280[0x80];
e281682b
SM		 6169
6170 u8 translations_octword_actual_size[0x20];
6171
b4ff3a36 6172 u8 reserved_at_320[0x560];
e281682b
SM		 6173
6174 u8 klm_pas_mtt[0][0x20];
6175};
6176
6177struct mlx5_ifc_create_flow_table_out_bits {
6178 u8 status[0x8];
b4ff3a36 6179 u8 reserved_at_8[0x18];
e281682b
SM		 6180
6181 u8 syndrome[0x20];
6182
b4ff3a36 6183 u8 reserved_at_40[0x8];
e281682b
SM		 6184 u8 table_id[0x18];
6185
b4ff3a36 6186 u8 reserved_at_60[0x20];
e281682b
SM		 6187};
6188
6189struct mlx5_ifc_create_flow_table_in_bits {
6190 u8 opcode[0x10];
b4ff3a36 6191 u8 reserved_at_10[0x10];
e281682b 6192
b4ff3a36 6193 u8 reserved_at_20[0x10];
e281682b
SM		 6194 u8 op_mod[0x10];
6195
7d5e1423
SM		 6196 u8 other_vport[0x1];
6197 u8 reserved_at_41[0xf];
6198 u8 vport_number[0x10];
6199
6200 u8 reserved_at_60[0x20];
e281682b
SM		 6201
6202 u8 table_type[0x8];
b4ff3a36 6203 u8 reserved_at_88[0x18];
e281682b 6204
b4ff3a36 6205 u8 reserved_at_a0[0x20];
e281682b 6206
7adbde20
HHZ		 6207 u8 encap_en[0x1];
6208 u8 decap_en[0x1];
6209 u8 reserved_at_c2[0x2];
34a40e68 6210 u8 table_miss_mode[0x4];
e281682b 6211 u8 level[0x8];
b4ff3a36 6212 u8 reserved_at_d0[0x8];
e281682b
SM		 6213 u8 log_size[0x8];
6214
b4ff3a36 6215 u8 reserved_at_e0[0x8];
34a40e68
MG		 6216 u8 table_miss_id[0x18];
6217
b4ff3a36 6218 u8 reserved_at_100[0x100];
e281682b
SM		 6219};
6220
6221struct mlx5_ifc_create_flow_group_out_bits {
6222 u8 status[0x8];
b4ff3a36 6223 u8 reserved_at_8[0x18];
e281682b
SM		 6224
6225 u8 syndrome[0x20];
6226
b4ff3a36 6227 u8 reserved_at_40[0x8];
e281682b
SM		 6228 u8 group_id[0x18];
6229
b4ff3a36 6230 u8 reserved_at_60[0x20];
e281682b
SM		 6231};
6232
6233enum {
6234 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
6235 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
6236 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
6237};
6238
6239struct mlx5_ifc_create_flow_group_in_bits {
6240 u8 opcode[0x10];
b4ff3a36 6241 u8 reserved_at_10[0x10];
e281682b 6242
b4ff3a36 6243 u8 reserved_at_20[0x10];
e281682b
SM		 6244 u8 op_mod[0x10];
6245
7d5e1423
SM		 6246 u8 other_vport[0x1];
6247 u8 reserved_at_41[0xf];
6248 u8 vport_number[0x10];
6249
6250 u8 reserved_at_60[0x20];
e281682b
SM		 6251
6252 u8 table_type[0x8];
b4ff3a36 6253 u8 reserved_at_88[0x18];
e281682b 6254
b4ff3a36 6255 u8 reserved_at_a0[0x8];
e281682b
SM		 6256 u8 table_id[0x18];
6257
b4ff3a36 6258 u8 reserved_at_c0[0x20];
e281682b
SM		 6259
6260 u8 start_flow_index[0x20];
6261
b4ff3a36 6262 u8 reserved_at_100[0x20];
e281682b
SM		 6263
6264 u8 end_flow_index[0x20];
6265
b4ff3a36 6266 u8 reserved_at_140[0xa0];
e281682b 6267
b4ff3a36 6268 u8 reserved_at_1e0[0x18];
e281682b
SM		 6269 u8 match_criteria_enable[0x8];
6270
6271 struct mlx5_ifc_fte_match_param_bits match_criteria;
6272
b4ff3a36 6273 u8 reserved_at_1200[0xe00];
e281682b
SM		 6274};
6275
6276struct mlx5_ifc_create_eq_out_bits {
6277 u8 status[0x8];
b4ff3a36 6278 u8 reserved_at_8[0x18];
e281682b
SM		 6279
6280 u8 syndrome[0x20];
6281
b4ff3a36 6282 u8 reserved_at_40[0x18];
e281682b
SM		 6283 u8 eq_number[0x8];
6284
b4ff3a36 6285 u8 reserved_at_60[0x20];
e281682b
SM		 6286};
6287
6288struct mlx5_ifc_create_eq_in_bits {
6289 u8 opcode[0x10];
b4ff3a36 6290 u8 reserved_at_10[0x10];
e281682b 6291
b4ff3a36 6292 u8 reserved_at_20[0x10];
e281682b
SM		 6293 u8 op_mod[0x10];
6294
b4ff3a36 6295 u8 reserved_at_40[0x40];
e281682b
SM		 6296
6297 struct mlx5_ifc_eqc_bits eq_context_entry;
6298
b4ff3a36 6299 u8 reserved_at_280[0x40];
e281682b
SM		 6300
6301 u8 event_bitmask[0x40];
6302
b4ff3a36 6303 u8 reserved_at_300[0x580];
e281682b
SM		 6304
6305 u8 pas[0][0x40];
6306};
6307
6308struct mlx5_ifc_create_dct_out_bits {
6309 u8 status[0x8];
b4ff3a36 6310 u8 reserved_at_8[0x18];
e281682b
SM		 6311
6312 u8 syndrome[0x20];
6313
b4ff3a36 6314 u8 reserved_at_40[0x8];
e281682b
SM		 6315 u8 dctn[0x18];
6316
b4ff3a36 6317 u8 reserved_at_60[0x20];
e281682b
SM		 6318};
6319
6320struct mlx5_ifc_create_dct_in_bits {
6321 u8 opcode[0x10];
b4ff3a36 6322 u8 reserved_at_10[0x10];
e281682b 6323
b4ff3a36 6324 u8 reserved_at_20[0x10];
e281682b
SM		 6325 u8 op_mod[0x10];
6326
b4ff3a36 6327 u8 reserved_at_40[0x40];
e281682b
SM		 6328
6329 struct mlx5_ifc_dctc_bits dct_context_entry;
6330
b4ff3a36 6331 u8 reserved_at_280[0x180];
e281682b
SM		 6332};
6333
6334struct mlx5_ifc_create_cq_out_bits {
6335 u8 status[0x8];
b4ff3a36 6336 u8 reserved_at_8[0x18];
e281682b
SM		 6337
6338 u8 syndrome[0x20];
6339
b4ff3a36 6340 u8 reserved_at_40[0x8];
e281682b
SM		 6341 u8 cqn[0x18];
6342
b4ff3a36 6343 u8 reserved_at_60[0x20];
e281682b
SM		 6344};
6345
6346struct mlx5_ifc_create_cq_in_bits {
6347 u8 opcode[0x10];
b4ff3a36 6348 u8 reserved_at_10[0x10];
e281682b 6349
b4ff3a36 6350 u8 reserved_at_20[0x10];
e281682b
SM		 6351 u8 op_mod[0x10];
6352
b4ff3a36 6353 u8 reserved_at_40[0x40];
e281682b
SM		 6354
6355 struct mlx5_ifc_cqc_bits cq_context;
6356
b4ff3a36 6357 u8 reserved_at_280[0x600];
e281682b
SM		 6358
6359 u8 pas[0][0x40];
6360};
6361
6362struct mlx5_ifc_config_int_moderation_out_bits {
6363 u8 status[0x8];
b4ff3a36 6364 u8 reserved_at_8[0x18];
e281682b
SM		 6365
6366 u8 syndrome[0x20];
6367
b4ff3a36 6368 u8 reserved_at_40[0x4];
e281682b
SM		 6369 u8 min_delay[0xc];
6370 u8 int_vector[0x10];
6371
b4ff3a36 6372 u8 reserved_at_60[0x20];
e281682b
SM		 6373};
6374
6375enum {
6376 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
6377 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
6378};
6379
6380struct mlx5_ifc_config_int_moderation_in_bits {
6381 u8 opcode[0x10];
b4ff3a36 6382 u8 reserved_at_10[0x10];
e281682b 6383
b4ff3a36 6384 u8 reserved_at_20[0x10];
e281682b
SM		 6385 u8 op_mod[0x10];
6386
b4ff3a36 6387 u8 reserved_at_40[0x4];
e281682b
SM		 6388 u8 min_delay[0xc];
6389 u8 int_vector[0x10];
6390
b4ff3a36 6391 u8 reserved_at_60[0x20];
e281682b
SM		 6392};
6393
6394struct mlx5_ifc_attach_to_mcg_out_bits {
6395 u8 status[0x8];
b4ff3a36 6396 u8 reserved_at_8[0x18];
e281682b
SM		 6397
6398 u8 syndrome[0x20];
6399
b4ff3a36 6400 u8 reserved_at_40[0x40];
e281682b
SM		 6401};
6402
6403struct mlx5_ifc_attach_to_mcg_in_bits {
6404 u8 opcode[0x10];
b4ff3a36 6405 u8 reserved_at_10[0x10];
e281682b 6406
b4ff3a36 6407 u8 reserved_at_20[0x10];
e281682b
SM		 6408 u8 op_mod[0x10];
6409
b4ff3a36 6410 u8 reserved_at_40[0x8];
e281682b
SM		 6411 u8 qpn[0x18];
6412
b4ff3a36 6413 u8 reserved_at_60[0x20];
e281682b
SM		 6414
6415 u8 multicast_gid[16][0x8];
6416};
6417
7486216b
SM		 6418struct mlx5_ifc_arm_xrq_out_bits {
6419 u8 status[0x8];
6420 u8 reserved_at_8[0x18];
6421
6422 u8 syndrome[0x20];
6423
6424 u8 reserved_at_40[0x40];
6425};
6426
6427struct mlx5_ifc_arm_xrq_in_bits {
6428 u8 opcode[0x10];
6429 u8 reserved_at_10[0x10];
6430
6431 u8 reserved_at_20[0x10];
6432 u8 op_mod[0x10];
6433
6434 u8 reserved_at_40[0x8];
6435 u8 xrqn[0x18];
6436
6437 u8 reserved_at_60[0x10];
6438 u8 lwm[0x10];
6439};
6440
e281682b
SM		 6441struct mlx5_ifc_arm_xrc_srq_out_bits {
6442 u8 status[0x8];
b4ff3a36 6443 u8 reserved_at_8[0x18];
e281682b
SM		 6444
6445 u8 syndrome[0x20];
6446
b4ff3a36 6447 u8 reserved_at_40[0x40];
e281682b
SM		 6448};
6449
6450enum {
6451 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
6452};
6453
6454struct mlx5_ifc_arm_xrc_srq_in_bits {
6455 u8 opcode[0x10];
b4ff3a36 6456 u8 reserved_at_10[0x10];
e281682b 6457
b4ff3a36 6458 u8 reserved_at_20[0x10];
e281682b
SM		 6459 u8 op_mod[0x10];
6460
b4ff3a36 6461 u8 reserved_at_40[0x8];
e281682b
SM		 6462 u8 xrc_srqn[0x18];
6463
b4ff3a36 6464 u8 reserved_at_60[0x10];
e281682b
SM		 6465 u8 lwm[0x10];
6466};
6467
6468struct mlx5_ifc_arm_rq_out_bits {
6469 u8 status[0x8];
b4ff3a36 6470 u8 reserved_at_8[0x18];
e281682b
SM		 6471
6472 u8 syndrome[0x20];
6473
b4ff3a36 6474 u8 reserved_at_40[0x40];
e281682b
SM		 6475};
6476
6477enum {
7486216b
SM		 6478 MLX5_ARM_RQ_IN_OP_MOD_SRQ = 0x1,
6479 MLX5_ARM_RQ_IN_OP_MOD_XRQ = 0x2,
e281682b
SM		 6480};
6481
6482struct mlx5_ifc_arm_rq_in_bits {
6483 u8 opcode[0x10];
b4ff3a36 6484 u8 reserved_at_10[0x10];
e281682b 6485
b4ff3a36 6486 u8 reserved_at_20[0x10];
e281682b
SM		 6487 u8 op_mod[0x10];
6488
b4ff3a36 6489 u8 reserved_at_40[0x8];
e281682b
SM		 6490 u8 srq_number[0x18];
6491
b4ff3a36 6492 u8 reserved_at_60[0x10];
e281682b
SM		 6493 u8 lwm[0x10];
6494};
6495
6496struct mlx5_ifc_arm_dct_out_bits {
6497 u8 status[0x8];
b4ff3a36 6498 u8 reserved_at_8[0x18];
e281682b
SM		 6499
6500 u8 syndrome[0x20];
6501
b4ff3a36 6502 u8 reserved_at_40[0x40];
e281682b
SM		 6503};
6504
6505struct mlx5_ifc_arm_dct_in_bits {
6506 u8 opcode[0x10];
b4ff3a36 6507 u8 reserved_at_10[0x10];
e281682b 6508
b4ff3a36 6509 u8 reserved_at_20[0x10];
e281682b
SM		 6510 u8 op_mod[0x10];
6511
b4ff3a36 6512 u8 reserved_at_40[0x8];
e281682b
SM		 6513 u8 dct_number[0x18];
6514
b4ff3a36 6515 u8 reserved_at_60[0x20];
e281682b
SM		 6516};
6517
6518struct mlx5_ifc_alloc_xrcd_out_bits {
6519 u8 status[0x8];
b4ff3a36 6520 u8 reserved_at_8[0x18];
e281682b
SM		 6521
6522 u8 syndrome[0x20];
6523
b4ff3a36 6524 u8 reserved_at_40[0x8];
e281682b
SM		 6525 u8 xrcd[0x18];
6526
b4ff3a36 6527 u8 reserved_at_60[0x20];
e281682b
SM		 6528};
6529
6530struct mlx5_ifc_alloc_xrcd_in_bits {
6531 u8 opcode[0x10];
b4ff3a36 6532 u8 reserved_at_10[0x10];
e281682b 6533
b4ff3a36 6534 u8 reserved_at_20[0x10];
e281682b
SM		 6535 u8 op_mod[0x10];
6536
b4ff3a36 6537 u8 reserved_at_40[0x40];
e281682b
SM		 6538};
6539
6540struct mlx5_ifc_alloc_uar_out_bits {
6541 u8 status[0x8];
b4ff3a36 6542 u8 reserved_at_8[0x18];
e281682b
SM		 6543
6544 u8 syndrome[0x20];
6545
b4ff3a36 6546 u8 reserved_at_40[0x8];
e281682b
SM		 6547 u8 uar[0x18];
6548
b4ff3a36 6549 u8 reserved_at_60[0x20];
e281682b
SM		 6550};
6551
6552struct mlx5_ifc_alloc_uar_in_bits {
6553 u8 opcode[0x10];
b4ff3a36 6554 u8 reserved_at_10[0x10];
e281682b 6555
b4ff3a36 6556 u8 reserved_at_20[0x10];
e281682b
SM		 6557 u8 op_mod[0x10];
6558
b4ff3a36 6559 u8 reserved_at_40[0x40];
e281682b
SM		 6560};
6561
6562struct mlx5_ifc_alloc_transport_domain_out_bits {
6563 u8 status[0x8];
b4ff3a36 6564 u8 reserved_at_8[0x18];
e281682b
SM		 6565
6566 u8 syndrome[0x20];
6567
b4ff3a36 6568 u8 reserved_at_40[0x8];
e281682b
SM		 6569 u8 transport_domain[0x18];
6570
b4ff3a36 6571 u8 reserved_at_60[0x20];
e281682b
SM		 6572};
6573
6574struct mlx5_ifc_alloc_transport_domain_in_bits {
6575 u8 opcode[0x10];
b4ff3a36 6576 u8 reserved_at_10[0x10];
e281682b 6577
b4ff3a36 6578 u8 reserved_at_20[0x10];
e281682b
SM		 6579 u8 op_mod[0x10];
6580
b4ff3a36 6581 u8 reserved_at_40[0x40];
e281682b
SM		 6582};
6583
6584struct mlx5_ifc_alloc_q_counter_out_bits {
6585 u8 status[0x8];
b4ff3a36 6586 u8 reserved_at_8[0x18];
e281682b
SM		 6587
6588 u8 syndrome[0x20];
6589
b4ff3a36 6590 u8 reserved_at_40[0x18];
e281682b
SM		 6591 u8 counter_set_id[0x8];
6592
b4ff3a36 6593 u8 reserved_at_60[0x20];
e281682b
SM		 6594};
6595
6596struct mlx5_ifc_alloc_q_counter_in_bits {
6597 u8 opcode[0x10];
b4ff3a36 6598 u8 reserved_at_10[0x10];
e281682b 6599
b4ff3a36 6600 u8 reserved_at_20[0x10];
e281682b
SM		 6601 u8 op_mod[0x10];
6602
b4ff3a36 6603 u8 reserved_at_40[0x40];
e281682b
SM		 6604};
6605
6606struct mlx5_ifc_alloc_pd_out_bits {
6607 u8 status[0x8];
b4ff3a36 6608 u8 reserved_at_8[0x18];
e281682b
SM		 6609
6610 u8 syndrome[0x20];
6611
b4ff3a36 6612 u8 reserved_at_40[0x8];
e281682b
SM		 6613 u8 pd[0x18];
6614
b4ff3a36 6615 u8 reserved_at_60[0x20];
e281682b
SM		 6616};
6617
6618struct mlx5_ifc_alloc_pd_in_bits {
9dc0b289
AV		 6619 u8 opcode[0x10];
6620 u8 reserved_at_10[0x10];
6621
6622 u8 reserved_at_20[0x10];
6623 u8 op_mod[0x10];
6624
6625 u8 reserved_at_40[0x40];
6626};
6627
6628struct mlx5_ifc_alloc_flow_counter_out_bits {
6629 u8 status[0x8];
6630 u8 reserved_at_8[0x18];
6631
6632 u8 syndrome[0x20];
6633
6634 u8 reserved_at_40[0x10];
6635 u8 flow_counter_id[0x10];
6636
6637 u8 reserved_at_60[0x20];
6638};
6639
6640struct mlx5_ifc_alloc_flow_counter_in_bits {
e281682b 6641 u8 opcode[0x10];
b4ff3a36 6642 u8 reserved_at_10[0x10];
e281682b 6643
b4ff3a36 6644 u8 reserved_at_20[0x10];
e281682b
SM		 6645 u8 op_mod[0x10];
6646
b4ff3a36 6647 u8 reserved_at_40[0x40];
e281682b
SM		 6648};
6649
6650struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
6651 u8 status[0x8];
b4ff3a36 6652 u8 reserved_at_8[0x18];
e281682b
SM		 6653
6654 u8 syndrome[0x20];
6655
b4ff3a36 6656 u8 reserved_at_40[0x40];
e281682b
SM		 6657};
6658
6659struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
6660 u8 opcode[0x10];
b4ff3a36 6661 u8 reserved_at_10[0x10];
e281682b 6662
b4ff3a36 6663 u8 reserved_at_20[0x10];
e281682b
SM		 6664 u8 op_mod[0x10];
6665
b4ff3a36 6666 u8 reserved_at_40[0x20];
e281682b 6667
b4ff3a36 6668 u8 reserved_at_60[0x10];
e281682b
SM		 6669 u8 vxlan_udp_port[0x10];
6670};
6671
7486216b
SM		 6672struct mlx5_ifc_set_rate_limit_out_bits {
6673 u8 status[0x8];
6674 u8 reserved_at_8[0x18];
6675
6676 u8 syndrome[0x20];
6677
6678 u8 reserved_at_40[0x40];
6679};
6680
6681struct mlx5_ifc_set_rate_limit_in_bits {
6682 u8 opcode[0x10];
6683 u8 reserved_at_10[0x10];
6684
6685 u8 reserved_at_20[0x10];
6686 u8 op_mod[0x10];
6687
6688 u8 reserved_at_40[0x10];
6689 u8 rate_limit_index[0x10];
6690
6691 u8 reserved_at_60[0x20];
6692
6693 u8 rate_limit[0x20];
6694};
6695
e281682b
SM		 6696struct mlx5_ifc_access_register_out_bits {
6697 u8 status[0x8];
b4ff3a36 6698 u8 reserved_at_8[0x18];
e281682b
SM		 6699
6700 u8 syndrome[0x20];
6701
b4ff3a36 6702 u8 reserved_at_40[0x40];
e281682b
SM		 6703
6704 u8 register_data[0][0x20];
6705};
6706
6707enum {
6708 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
6709 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
6710};
6711
6712struct mlx5_ifc_access_register_in_bits {
6713 u8 opcode[0x10];
b4ff3a36 6714 u8 reserved_at_10[0x10];
e281682b 6715
b4ff3a36 6716 u8 reserved_at_20[0x10];
e281682b
SM		 6717 u8 op_mod[0x10];
6718
b4ff3a36 6719 u8 reserved_at_40[0x10];
e281682b
SM		 6720 u8 register_id[0x10];
6721
6722 u8 argument[0x20];
6723
6724 u8 register_data[0][0x20];
6725};
6726
6727struct mlx5_ifc_sltp_reg_bits {
6728 u8 status[0x4];
6729 u8 version[0x4];
6730 u8 local_port[0x8];
6731 u8 pnat[0x2];
b4ff3a36 6732 u8 reserved_at_12[0x2];
e281682b 6733 u8 lane[0x4];
b4ff3a36 6734 u8 reserved_at_18[0x8];
e281682b 6735
b4ff3a36 6736 u8 reserved_at_20[0x20];
e281682b 6737
b4ff3a36 6738 u8 reserved_at_40[0x7];
e281682b
SM		 6739 u8 polarity[0x1];
6740 u8 ob_tap0[0x8];
6741 u8 ob_tap1[0x8];
6742 u8 ob_tap2[0x8];
6743
b4ff3a36 6744 u8 reserved_at_60[0xc];
e281682b
SM		 6745 u8 ob_preemp_mode[0x4];
6746 u8 ob_reg[0x8];
6747 u8 ob_bias[0x8];
6748
b4ff3a36 6749 u8 reserved_at_80[0x20];
e281682b
SM		 6750};
6751
6752struct mlx5_ifc_slrg_reg_bits {
6753 u8 status[0x4];
6754 u8 version[0x4];
6755 u8 local_port[0x8];
6756 u8 pnat[0x2];
b4ff3a36 6757 u8 reserved_at_12[0x2];
e281682b 6758 u8 lane[0x4];
b4ff3a36 6759 u8 reserved_at_18[0x8];
e281682b
SM		 6760
6761 u8 time_to_link_up[0x10];
b4ff3a36 6762 u8 reserved_at_30[0xc];
e281682b
SM		 6763 u8 grade_lane_speed[0x4];
6764
6765 u8 grade_version[0x8];
6766 u8 grade[0x18];
6767
b4ff3a36 6768 u8 reserved_at_60[0x4];
e281682b
SM		 6769 u8 height_grade_type[0x4];
6770 u8 height_grade[0x18];
6771
6772 u8 height_dz[0x10];
6773 u8 height_dv[0x10];
6774
b4ff3a36 6775 u8 reserved_at_a0[0x10];
e281682b
SM		 6776 u8 height_sigma[0x10];
6777
b4ff3a36 6778 u8 reserved_at_c0[0x20];
e281682b 6779
b4ff3a36 6780 u8 reserved_at_e0[0x4];
e281682b
SM		 6781 u8 phase_grade_type[0x4];
6782 u8 phase_grade[0x18];
6783
b4ff3a36 6784 u8 reserved_at_100[0x8];
e281682b 6785 u8 phase_eo_pos[0x8];
b4ff3a36 6786 u8 reserved_at_110[0x8];
e281682b
SM		 6787 u8 phase_eo_neg[0x8];
6788
6789 u8 ffe_set_tested[0x10];
6790 u8 test_errors_per_lane[0x10];
6791};
6792
6793struct mlx5_ifc_pvlc_reg_bits {
b4ff3a36 6794 u8 reserved_at_0[0x8];
e281682b 6795 u8 local_port[0x8];
b4ff3a36 6796 u8 reserved_at_10[0x10];
e281682b 6797
b4ff3a36 6798 u8 reserved_at_20[0x1c];
e281682b
SM		 6799 u8 vl_hw_cap[0x4];
6800
b4ff3a36 6801 u8 reserved_at_40[0x1c];
e281682b
SM		 6802 u8 vl_admin[0x4];
6803
b4ff3a36 6804 u8 reserved_at_60[0x1c];
e281682b
SM		 6805 u8 vl_operational[0x4];
6806};
6807
6808struct mlx5_ifc_pude_reg_bits {
6809 u8 swid[0x8];
6810 u8 local_port[0x8];
b4ff3a36 6811 u8 reserved_at_10[0x4];
e281682b 6812 u8 admin_status[0x4];
b4ff3a36 6813 u8 reserved_at_18[0x4];
e281682b
SM		 6814 u8 oper_status[0x4];
6815
b4ff3a36 6816 u8 reserved_at_20[0x60];
e281682b
SM		 6817};
6818
6819struct mlx5_ifc_ptys_reg_bits {
7486216b
SM		 6820 u8 an_disable_cap[0x1];
6821 u8 an_disable_admin[0x1];
6822 u8 reserved_at_2[0x6];
e281682b 6823 u8 local_port[0x8];
b4ff3a36 6824 u8 reserved_at_10[0xd];
e281682b
SM		 6825 u8 proto_mask[0x3];
6826
7486216b
SM		 6827 u8 an_status[0x4];
6828 u8 reserved_at_24[0x3c];
e281682b
SM		 6829
6830 u8 eth_proto_capability[0x20];
6831
6832 u8 ib_link_width_capability[0x10];
6833 u8 ib_proto_capability[0x10];
6834
b4ff3a36 6835 u8 reserved_at_a0[0x20];
e281682b
SM		 6836
6837 u8 eth_proto_admin[0x20];
6838
6839 u8 ib_link_width_admin[0x10];
6840 u8 ib_proto_admin[0x10];
6841
b4ff3a36 6842 u8 reserved_at_100[0x20];
e281682b
SM		 6843
6844 u8 eth_proto_oper[0x20];
6845
6846 u8 ib_link_width_oper[0x10];
6847 u8 ib_proto_oper[0x10];
6848
b4ff3a36 6849 u8 reserved_at_160[0x20];
e281682b
SM		 6850
6851 u8 eth_proto_lp_advertise[0x20];
6852
b4ff3a36 6853 u8 reserved_at_1a0[0x60];
e281682b
SM		 6854};
6855
7d5e1423
SM		 6856struct mlx5_ifc_mlcr_reg_bits {
6857 u8 reserved_at_0[0x8];
6858 u8 local_port[0x8];
6859 u8 reserved_at_10[0x20];
6860
6861 u8 beacon_duration[0x10];
6862 u8 reserved_at_40[0x10];
6863
6864 u8 beacon_remain[0x10];
6865};
6866
e281682b 6867struct mlx5_ifc_ptas_reg_bits {
b4ff3a36 6868 u8 reserved_at_0[0x20];
e281682b
SM		 6869
6870 u8 algorithm_options[0x10];
b4ff3a36 6871 u8 reserved_at_30[0x4];
e281682b
SM		 6872 u8 repetitions_mode[0x4];
6873 u8 num_of_repetitions[0x8];
6874
6875 u8 grade_version[0x8];
6876 u8 height_grade_type[0x4];
6877 u8 phase_grade_type[0x4];
6878 u8 height_grade_weight[0x8];
6879 u8 phase_grade_weight[0x8];
6880
6881 u8 gisim_measure_bits[0x10];
6882 u8 adaptive_tap_measure_bits[0x10];
6883
6884 u8 ber_bath_high_error_threshold[0x10];
6885 u8 ber_bath_mid_error_threshold[0x10];
6886
6887 u8 ber_bath_low_error_threshold[0x10];
6888 u8 one_ratio_high_threshold[0x10];
6889
6890 u8 one_ratio_high_mid_threshold[0x10];
6891 u8 one_ratio_low_mid_threshold[0x10];
6892
6893 u8 one_ratio_low_threshold[0x10];
6894 u8 ndeo_error_threshold[0x10];
6895
6896 u8 mixer_offset_step_size[0x10];
b4ff3a36 6897 u8 reserved_at_110[0x8];
e281682b
SM		 6898 u8 mix90_phase_for_voltage_bath[0x8];
6899
6900 u8 mixer_offset_start[0x10];
6901 u8 mixer_offset_end[0x10];
6902
b4ff3a36 6903 u8 reserved_at_140[0x15];
e281682b
SM		 6904 u8 ber_test_time[0xb];
6905};
6906
6907struct mlx5_ifc_pspa_reg_bits {
6908 u8 swid[0x8];
6909 u8 local_port[0x8];
6910 u8 sub_port[0x8];
b4ff3a36 6911 u8 reserved_at_18[0x8];
e281682b 6912
b4ff3a36 6913 u8 reserved_at_20[0x20];
e281682b
SM		 6914};
6915
6916struct mlx5_ifc_pqdr_reg_bits {
b4ff3a36 6917 u8 reserved_at_0[0x8];
e281682b 6918 u8 local_port[0x8];
b4ff3a36 6919 u8 reserved_at_10[0x5];
e281682b 6920 u8 prio[0x3];
b4ff3a36 6921 u8 reserved_at_18[0x6];
e281682b
SM		 6922 u8 mode[0x2];
6923
b4ff3a36 6924 u8 reserved_at_20[0x20];
e281682b 6925
b4ff3a36 6926 u8 reserved_at_40[0x10];
e281682b
SM		 6927 u8 min_threshold[0x10];
6928
b4ff3a36 6929 u8 reserved_at_60[0x10];
e281682b
SM		 6930 u8 max_threshold[0x10];
6931
b4ff3a36 6932 u8 reserved_at_80[0x10];
e281682b
SM		 6933 u8 mark_probability_denominator[0x10];
6934
b4ff3a36 6935 u8 reserved_at_a0[0x60];
e281682b
SM		 6936};
6937
6938struct mlx5_ifc_ppsc_reg_bits {
b4ff3a36 6939 u8 reserved_at_0[0x8];
e281682b 6940 u8 local_port[0x8];
b4ff3a36 6941 u8 reserved_at_10[0x10];
e281682b 6942
b4ff3a36 6943 u8 reserved_at_20[0x60];
e281682b 6944
b4ff3a36 6945 u8 reserved_at_80[0x1c];
e281682b
SM		 6946 u8 wrps_admin[0x4];
6947
b4ff3a36 6948 u8 reserved_at_a0[0x1c];
e281682b
SM		 6949 u8 wrps_status[0x4];
6950
b4ff3a36 6951 u8 reserved_at_c0[0x8];
e281682b 6952 u8 up_threshold[0x8];
b4ff3a36 6953 u8 reserved_at_d0[0x8];
e281682b
SM		 6954 u8 down_threshold[0x8];
6955
b4ff3a36 6956 u8 reserved_at_e0[0x20];
e281682b 6957
b4ff3a36 6958 u8 reserved_at_100[0x1c];
e281682b
SM		 6959 u8 srps_admin[0x4];
6960
b4ff3a36 6961 u8 reserved_at_120[0x1c];
e281682b
SM		 6962 u8 srps_status[0x4];
6963
b4ff3a36 6964 u8 reserved_at_140[0x40];
e281682b
SM		 6965};
6966
6967struct mlx5_ifc_pplr_reg_bits {
b4ff3a36 6968 u8 reserved_at_0[0x8];
e281682b 6969 u8 local_port[0x8];
b4ff3a36 6970 u8 reserved_at_10[0x10];
e281682b 6971
b4ff3a36 6972 u8 reserved_at_20[0x8];
e281682b 6973 u8 lb_cap[0x8];
b4ff3a36 6974 u8 reserved_at_30[0x8];
e281682b
SM		 6975 u8 lb_en[0x8];
6976};
6977
6978struct mlx5_ifc_pplm_reg_bits {
b4ff3a36 6979 u8 reserved_at_0[0x8];
e281682b 6980 u8 local_port[0x8];
b4ff3a36 6981 u8 reserved_at_10[0x10];
e281682b 6982
b4ff3a36 6983 u8 reserved_at_20[0x20];
e281682b
SM		 6984
6985 u8 port_profile_mode[0x8];
6986 u8 static_port_profile[0x8];
6987 u8 active_port_profile[0x8];
b4ff3a36 6988 u8 reserved_at_58[0x8];
e281682b
SM		 6989
6990 u8 retransmission_active[0x8];
6991 u8 fec_mode_active[0x18];
6992
b4ff3a36 6993 u8 reserved_at_80[0x20];
e281682b
SM		 6994};
6995
6996struct mlx5_ifc_ppcnt_reg_bits {
6997 u8 swid[0x8];
6998 u8 local_port[0x8];
6999 u8 pnat[0x2];
b4ff3a36 7000 u8 reserved_at_12[0x8];
e281682b
SM		 7001 u8 grp[0x6];
7002
7003 u8 clr[0x1];
b4ff3a36 7004 u8 reserved_at_21[0x1c];
e281682b
SM		 7005 u8 prio_tc[0x3];
7006
7007 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
7008};
7009
7010struct mlx5_ifc_ppad_reg_bits {
b4ff3a36 7011 u8 reserved_at_0[0x3];
e281682b 7012 u8 single_mac[0x1];
b4ff3a36 7013 u8 reserved_at_4[0x4];
e281682b
SM		 7014 u8 local_port[0x8];
7015 u8 mac_47_32[0x10];
7016
7017 u8 mac_31_0[0x20];
7018
b4ff3a36 7019 u8 reserved_at_40[0x40];
e281682b
SM		 7020};
7021
7022struct mlx5_ifc_pmtu_reg_bits {
b4ff3a36 7023 u8 reserved_at_0[0x8];
e281682b 7024 u8 local_port[0x8];
b4ff3a36 7025 u8 reserved_at_10[0x10];
e281682b
SM		 7026
7027 u8 max_mtu[0x10];
b4ff3a36 7028 u8 reserved_at_30[0x10];
e281682b
SM		 7029
7030 u8 admin_mtu[0x10];
b4ff3a36 7031 u8 reserved_at_50[0x10];
e281682b
SM		 7032
7033 u8 oper_mtu[0x10];
b4ff3a36 7034 u8 reserved_at_70[0x10];
e281682b
SM		 7035};
7036
7037struct mlx5_ifc_pmpr_reg_bits {
b4ff3a36 7038 u8 reserved_at_0[0x8];
e281682b 7039 u8 module[0x8];
b4ff3a36 7040 u8 reserved_at_10[0x10];
e281682b 7041
b4ff3a36 7042 u8 reserved_at_20[0x18];
e281682b
SM		 7043 u8 attenuation_5g[0x8];
7044
b4ff3a36 7045 u8 reserved_at_40[0x18];
e281682b
SM		 7046 u8 attenuation_7g[0x8];
7047
b4ff3a36 7048 u8 reserved_at_60[0x18];
e281682b
SM		 7049 u8 attenuation_12g[0x8];
7050};
7051
7052struct mlx5_ifc_pmpe_reg_bits {
b4ff3a36 7053 u8 reserved_at_0[0x8];
e281682b 7054 u8 module[0x8];
b4ff3a36 7055 u8 reserved_at_10[0xc];
e281682b
SM		 7056 u8 module_status[0x4];
7057
b4ff3a36 7058 u8 reserved_at_20[0x60];
e281682b
SM		 7059};
7060
7061struct mlx5_ifc_pmpc_reg_bits {
7062 u8 module_state_updated[32][0x8];
7063};
7064
7065struct mlx5_ifc_pmlpn_reg_bits {
b4ff3a36 7066 u8 reserved_at_0[0x4];
e281682b
SM		 7067 u8 mlpn_status[0x4];
7068 u8 local_port[0x8];
b4ff3a36 7069 u8 reserved_at_10[0x10];
e281682b
SM		 7070
7071 u8 e[0x1];
b4ff3a36 7072 u8 reserved_at_21[0x1f];
e281682b
SM		 7073};
7074
7075struct mlx5_ifc_pmlp_reg_bits {
7076 u8 rxtx[0x1];
b4ff3a36 7077 u8 reserved_at_1[0x7];
e281682b 7078 u8 local_port[0x8];
b4ff3a36 7079 u8 reserved_at_10[0x8];
e281682b
SM		 7080 u8 width[0x8];
7081
7082 u8 lane0_module_mapping[0x20];
7083
7084 u8 lane1_module_mapping[0x20];
7085
7086 u8 lane2_module_mapping[0x20];
7087
7088 u8 lane3_module_mapping[0x20];
7089
b4ff3a36 7090 u8 reserved_at_a0[0x160];
e281682b
SM		 7091};
7092
7093struct mlx5_ifc_pmaos_reg_bits {
b4ff3a36 7094 u8 reserved_at_0[0x8];
e281682b 7095 u8 module[0x8];
b4ff3a36 7096 u8 reserved_at_10[0x4];
e281682b 7097 u8 admin_status[0x4];
b4ff3a36 7098 u8 reserved_at_18[0x4];
e281682b
SM		 7099 u8 oper_status[0x4];
7100
7101 u8 ase[0x1];
7102 u8 ee[0x1];
b4ff3a36 7103 u8 reserved_at_22[0x1c];
e281682b
SM		 7104 u8 e[0x2];
7105
b4ff3a36 7106 u8 reserved_at_40[0x40];
e281682b
SM		 7107};
7108
7109struct mlx5_ifc_plpc_reg_bits {
b4ff3a36 7110 u8 reserved_at_0[0x4];
e281682b 7111 u8 profile_id[0xc];
b4ff3a36 7112 u8 reserved_at_10[0x4];
e281682b 7113 u8 proto_mask[0x4];
b4ff3a36 7114 u8 reserved_at_18[0x8];
e281682b 7115
b4ff3a36 7116 u8 reserved_at_20[0x10];
e281682b
SM		 7117 u8 lane_speed[0x10];
7118
b4ff3a36 7119 u8 reserved_at_40[0x17];
e281682b
SM		 7120 u8 lpbf[0x1];
7121 u8 fec_mode_policy[0x8];
7122
7123 u8 retransmission_capability[0x8];
7124 u8 fec_mode_capability[0x18];
7125
7126 u8 retransmission_support_admin[0x8];
7127 u8 fec_mode_support_admin[0x18];
7128
7129 u8 retransmission_request_admin[0x8];
7130 u8 fec_mode_request_admin[0x18];
7131
b4ff3a36 7132 u8 reserved_at_c0[0x80];
e281682b
SM		 7133};
7134
7135struct mlx5_ifc_plib_reg_bits {
b4ff3a36 7136 u8 reserved_at_0[0x8];
e281682b 7137 u8 local_port[0x8];
b4ff3a36 7138 u8 reserved_at_10[0x8];
e281682b
SM		 7139 u8 ib_port[0x8];
7140
b4ff3a36 7141 u8 reserved_at_20[0x60];
e281682b
SM		 7142};
7143
7144struct mlx5_ifc_plbf_reg_bits {
b4ff3a36 7145 u8 reserved_at_0[0x8];
e281682b 7146 u8 local_port[0x8];
b4ff3a36 7147 u8 reserved_at_10[0xd];
e281682b
SM		 7148 u8 lbf_mode[0x3];
7149
b4ff3a36 7150 u8 reserved_at_20[0x20];
e281682b
SM		 7151};
7152
7153struct mlx5_ifc_pipg_reg_bits {
b4ff3a36 7154 u8 reserved_at_0[0x8];
e281682b 7155 u8 local_port[0x8];
b4ff3a36 7156 u8 reserved_at_10[0x10];
e281682b
SM		 7157
7158 u8 dic[0x1];
b4ff3a36 7159 u8 reserved_at_21[0x19];
e281682b 7160 u8 ipg[0x4];
b4ff3a36 7161 u8 reserved_at_3e[0x2];
e281682b
SM		 7162};
7163
7164struct mlx5_ifc_pifr_reg_bits {
b4ff3a36 7165 u8 reserved_at_0[0x8];
e281682b 7166 u8 local_port[0x8];
b4ff3a36 7167 u8 reserved_at_10[0x10];
e281682b 7168
b4ff3a36 7169 u8 reserved_at_20[0xe0];
e281682b
SM		 7170
7171 u8 port_filter[8][0x20];
7172
7173 u8 port_filter_update_en[8][0x20];
7174};
7175
7176struct mlx5_ifc_pfcc_reg_bits {
b4ff3a36 7177 u8 reserved_at_0[0x8];
e281682b 7178 u8 local_port[0x8];
b4ff3a36 7179 u8 reserved_at_10[0x10];
e281682b
SM		 7180
7181 u8 ppan[0x4];
b4ff3a36 7182 u8 reserved_at_24[0x4];
e281682b 7183 u8 prio_mask_tx[0x8];
b4ff3a36 7184 u8 reserved_at_30[0x8];
e281682b
SM		 7185 u8 prio_mask_rx[0x8];
7186
7187 u8 pptx[0x1];
7188 u8 aptx[0x1];
b4ff3a36 7189 u8 reserved_at_42[0x6];
e281682b 7190 u8 pfctx[0x8];
b4ff3a36 7191 u8 reserved_at_50[0x10];
e281682b
SM		 7192
7193 u8 pprx[0x1];
7194 u8 aprx[0x1];
b4ff3a36 7195 u8 reserved_at_62[0x6];
e281682b 7196 u8 pfcrx[0x8];
b4ff3a36 7197 u8 reserved_at_70[0x10];
e281682b 7198
b4ff3a36 7199 u8 reserved_at_80[0x80];
e281682b
SM		 7200};
7201
7202struct mlx5_ifc_pelc_reg_bits {
7203 u8 op[0x4];
b4ff3a36 7204 u8 reserved_at_4[0x4];
e281682b 7205 u8 local_port[0x8];
b4ff3a36 7206 u8 reserved_at_10[0x10];
e281682b
SM		 7207
7208 u8 op_admin[0x8];
7209 u8 op_capability[0x8];
7210 u8 op_request[0x8];
7211 u8 op_active[0x8];
7212
7213 u8 admin[0x40];
7214
7215 u8 capability[0x40];
7216
7217 u8 request[0x40];
7218
7219 u8 active[0x40];
7220
b4ff3a36 7221 u8 reserved_at_140[0x80];
e281682b
SM		 7222};
7223
7224struct mlx5_ifc_peir_reg_bits {
b4ff3a36 7225 u8 reserved_at_0[0x8];
e281682b 7226 u8 local_port[0x8];
b4ff3a36 7227 u8 reserved_at_10[0x10];
e281682b 7228
b4ff3a36 7229 u8 reserved_at_20[0xc];
e281682b 7230 u8 error_count[0x4];
b4ff3a36 7231 u8 reserved_at_30[0x10];
e281682b 7232
b4ff3a36 7233 u8 reserved_at_40[0xc];
e281682b 7234 u8 lane[0x4];
b4ff3a36 7235 u8 reserved_at_50[0x8];
e281682b
SM		 7236 u8 error_type[0x8];
7237};
7238
7239struct mlx5_ifc_pcap_reg_bits {
b4ff3a36 7240 u8 reserved_at_0[0x8];
e281682b 7241 u8 local_port[0x8];
b4ff3a36 7242 u8 reserved_at_10[0x10];
e281682b
SM		 7243
7244 u8 port_capability_mask[4][0x20];
7245};
7246
7247struct mlx5_ifc_paos_reg_bits {
7248 u8 swid[0x8];
7249 u8 local_port[0x8];
b4ff3a36 7250 u8 reserved_at_10[0x4];
e281682b 7251 u8 admin_status[0x4];
b4ff3a36 7252 u8 reserved_at_18[0x4];
e281682b
SM		 7253 u8 oper_status[0x4];
7254
7255 u8 ase[0x1];
7256 u8 ee[0x1];
b4ff3a36 7257 u8 reserved_at_22[0x1c];
e281682b
SM		 7258 u8 e[0x2];
7259
b4ff3a36 7260 u8 reserved_at_40[0x40];
e281682b
SM		 7261};
7262
7263struct mlx5_ifc_pamp_reg_bits {
b4ff3a36 7264 u8 reserved_at_0[0x8];
e281682b 7265 u8 opamp_group[0x8];
b4ff3a36 7266 u8 reserved_at_10[0xc];
e281682b
SM		 7267 u8 opamp_group_type[0x4];
7268
7269 u8 start_index[0x10];
b4ff3a36 7270 u8 reserved_at_30[0x4];
e281682b
SM		 7271 u8 num_of_indices[0xc];
7272
7273 u8 index_data[18][0x10];
7274};
7275
7d5e1423
SM		 7276struct mlx5_ifc_pcmr_reg_bits {
7277 u8 reserved_at_0[0x8];
7278 u8 local_port[0x8];
7279 u8 reserved_at_10[0x2e];
7280 u8 fcs_cap[0x1];
7281 u8 reserved_at_3f[0x1f];
7282 u8 fcs_chk[0x1];
7283 u8 reserved_at_5f[0x1];
7284};
7285
e281682b 7286struct mlx5_ifc_lane_2_module_mapping_bits {
b4ff3a36 7287 u8 reserved_at_0[0x6];
e281682b 7288 u8 rx_lane[0x2];
b4ff3a36 7289 u8 reserved_at_8[0x6];
e281682b 7290 u8 tx_lane[0x2];
b4ff3a36 7291 u8 reserved_at_10[0x8];
e281682b
SM		 7292 u8 module[0x8];
7293};
7294
7295struct mlx5_ifc_bufferx_reg_bits {
b4ff3a36 7296 u8 reserved_at_0[0x6];
e281682b
SM		 7297 u8 lossy[0x1];
7298 u8 epsb[0x1];
b4ff3a36 7299 u8 reserved_at_8[0xc];
e281682b
SM		 7300 u8 size[0xc];
7301
7302 u8 xoff_threshold[0x10];
7303 u8 xon_threshold[0x10];
7304};
7305
7306struct mlx5_ifc_set_node_in_bits {
7307 u8 node_description[64][0x8];
7308};
7309
7310struct mlx5_ifc_register_power_settings_bits {
b4ff3a36 7311 u8 reserved_at_0[0x18];
e281682b
SM		 7312 u8 power_settings_level[0x8];
7313
b4ff3a36 7314 u8 reserved_at_20[0x60];
e281682b
SM		 7315};
7316
7317struct mlx5_ifc_register_host_endianness_bits {
7318 u8 he[0x1];
b4ff3a36 7319 u8 reserved_at_1[0x1f];
e281682b 7320
b4ff3a36 7321 u8 reserved_at_20[0x60];
e281682b
SM		 7322};
7323
7324struct mlx5_ifc_umr_pointer_desc_argument_bits {
b4ff3a36 7325 u8 reserved_at_0[0x20];
e281682b
SM		 7326
7327 u8 mkey[0x20];
7328
7329 u8 addressh_63_32[0x20];
7330
7331 u8 addressl_31_0[0x20];
7332};
7333
7334struct mlx5_ifc_ud_adrs_vector_bits {
7335 u8 dc_key[0x40];
7336
7337 u8 ext[0x1];
b4ff3a36 7338 u8 reserved_at_41[0x7];
e281682b
SM		 7339 u8 destination_qp_dct[0x18];
7340
7341 u8 static_rate[0x4];
7342 u8 sl_eth_prio[0x4];
7343 u8 fl[0x1];
7344 u8 mlid[0x7];
7345 u8 rlid_udp_sport[0x10];
7346
b4ff3a36 7347 u8 reserved_at_80[0x20];
e281682b
SM		 7348
7349 u8 rmac_47_16[0x20];
7350
7351 u8 rmac_15_0[0x10];
7352 u8 tclass[0x8];
7353 u8 hop_limit[0x8];
7354
b4ff3a36 7355 u8 reserved_at_e0[0x1];
e281682b 7356 u8 grh[0x1];
b4ff3a36 7357 u8 reserved_at_e2[0x2];
e281682b
SM		 7358 u8 src_addr_index[0x8];
7359 u8 flow_label[0x14];
7360
7361 u8 rgid_rip[16][0x8];
7362};
7363
7364struct mlx5_ifc_pages_req_event_bits {
b4ff3a36 7365 u8 reserved_at_0[0x10];
e281682b
SM		 7366 u8 function_id[0x10];
7367
7368 u8 num_pages[0x20];
7369
b4ff3a36 7370 u8 reserved_at_40[0xa0];
e281682b
SM		 7371};
7372
7373struct mlx5_ifc_eqe_bits {
b4ff3a36 7374 u8 reserved_at_0[0x8];
e281682b 7375 u8 event_type[0x8];
b4ff3a36 7376 u8 reserved_at_10[0x8];
e281682b
SM		 7377 u8 event_sub_type[0x8];
7378
b4ff3a36 7379 u8 reserved_at_20[0xe0];
e281682b
SM		 7380
7381 union mlx5_ifc_event_auto_bits event_data;
7382
b4ff3a36 7383 u8 reserved_at_1e0[0x10];
e281682b 7384 u8 signature[0x8];
b4ff3a36 7385 u8 reserved_at_1f8[0x7];
e281682b
SM		 7386 u8 owner[0x1];
7387};
7388
7389enum {
7390 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
7391};
7392
7393struct mlx5_ifc_cmd_queue_entry_bits {
7394 u8 type[0x8];
b4ff3a36 7395 u8 reserved_at_8[0x18];
e281682b
SM		 7396
7397 u8 input_length[0x20];
7398
7399 u8 input_mailbox_pointer_63_32[0x20];
7400
7401 u8 input_mailbox_pointer_31_9[0x17];
b4ff3a36 7402 u8 reserved_at_77[0x9];
e281682b
SM		 7403
7404 u8 command_input_inline_data[16][0x8];
7405
7406 u8 command_output_inline_data[16][0x8];
7407
7408 u8 output_mailbox_pointer_63_32[0x20];
7409
7410 u8 output_mailbox_pointer_31_9[0x17];
b4ff3a36 7411 u8 reserved_at_1b7[0x9];
e281682b
SM		 7412
7413 u8 output_length[0x20];
7414
7415 u8 token[0x8];
7416 u8 signature[0x8];
b4ff3a36 7417 u8 reserved_at_1f0[0x8];
e281682b
SM		 7418 u8 status[0x7];
7419 u8 ownership[0x1];
7420};
7421
7422struct mlx5_ifc_cmd_out_bits {
7423 u8 status[0x8];
b4ff3a36 7424 u8 reserved_at_8[0x18];
e281682b
SM		 7425
7426 u8 syndrome[0x20];
7427
7428 u8 command_output[0x20];
7429};
7430
7431struct mlx5_ifc_cmd_in_bits {
7432 u8 opcode[0x10];
b4ff3a36 7433 u8 reserved_at_10[0x10];
e281682b 7434
b4ff3a36 7435 u8 reserved_at_20[0x10];
e281682b
SM		 7436 u8 op_mod[0x10];
7437
7438 u8 command[0][0x20];
7439};
7440
7441struct mlx5_ifc_cmd_if_box_bits {
7442 u8 mailbox_data[512][0x8];
7443
b4ff3a36 7444 u8 reserved_at_1000[0x180];
e281682b
SM		 7445
7446 u8 next_pointer_63_32[0x20];
7447
7448 u8 next_pointer_31_10[0x16];
b4ff3a36 7449 u8 reserved_at_11b6[0xa];
e281682b
SM		 7450
7451 u8 block_number[0x20];
7452
b4ff3a36 7453 u8 reserved_at_11e0[0x8];
e281682b
SM		 7454 u8 token[0x8];
7455 u8 ctrl_signature[0x8];
7456 u8 signature[0x8];
7457};
7458
7459struct mlx5_ifc_mtt_bits {
7460 u8 ptag_63_32[0x20];
7461
7462 u8 ptag_31_8[0x18];
b4ff3a36 7463 u8 reserved_at_38[0x6];
e281682b
SM		 7464 u8 wr_en[0x1];
7465 u8 rd_en[0x1];
7466};
7467
928cfe87
TT		 7468struct mlx5_ifc_query_wol_rol_out_bits {
7469 u8 status[0x8];
7470 u8 reserved_at_8[0x18];
7471
7472 u8 syndrome[0x20];
7473
7474 u8 reserved_at_40[0x10];
7475 u8 rol_mode[0x8];
7476 u8 wol_mode[0x8];
7477
7478 u8 reserved_at_60[0x20];
7479};
7480
7481struct mlx5_ifc_query_wol_rol_in_bits {
7482 u8 opcode[0x10];
7483 u8 reserved_at_10[0x10];
7484
7485 u8 reserved_at_20[0x10];
7486 u8 op_mod[0x10];
7487
7488 u8 reserved_at_40[0x40];
7489};
7490
7491struct mlx5_ifc_set_wol_rol_out_bits {
7492 u8 status[0x8];
7493 u8 reserved_at_8[0x18];
7494
7495 u8 syndrome[0x20];
7496
7497 u8 reserved_at_40[0x40];
7498};
7499
7500struct mlx5_ifc_set_wol_rol_in_bits {
7501 u8 opcode[0x10];
7502 u8 reserved_at_10[0x10];
7503
7504 u8 reserved_at_20[0x10];
7505 u8 op_mod[0x10];
7506
7507 u8 rol_mode_valid[0x1];
7508 u8 wol_mode_valid[0x1];
7509 u8 reserved_at_42[0xe];
7510 u8 rol_mode[0x8];
7511 u8 wol_mode[0x8];
7512
7513 u8 reserved_at_60[0x20];
7514};
7515
e281682b
SM		 7516enum {
7517 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
7518 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
7519 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
7520};
7521
7522enum {
7523 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
7524 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
7525 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
7526};
7527
7528enum {
7529 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
7530 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
7531 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
7532 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
7533 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
7534 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
7535 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
7536 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
7537 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
7538 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
7539 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
7540};
7541
7542struct mlx5_ifc_initial_seg_bits {
7543 u8 fw_rev_minor[0x10];
7544 u8 fw_rev_major[0x10];
7545
7546 u8 cmd_interface_rev[0x10];
7547 u8 fw_rev_subminor[0x10];
7548
b4ff3a36 7549 u8 reserved_at_40[0x40];
e281682b
SM		 7550
7551 u8 cmdq_phy_addr_63_32[0x20];
7552
7553 u8 cmdq_phy_addr_31_12[0x14];
b4ff3a36 7554 u8 reserved_at_b4[0x2];
e281682b
SM		 7555 u8 nic_interface[0x2];
7556 u8 log_cmdq_size[0x4];
7557 u8 log_cmdq_stride[0x4];
7558
7559 u8 command_doorbell_vector[0x20];
7560
b4ff3a36 7561 u8 reserved_at_e0[0xf00];
e281682b
SM		 7562
7563 u8 initializing[0x1];
b4ff3a36 7564 u8 reserved_at_fe1[0x4];
e281682b 7565 u8 nic_interface_supported[0x3];
b4ff3a36 7566 u8 reserved_at_fe8[0x18];
e281682b
SM		 7567
7568 struct mlx5_ifc_health_buffer_bits health_buffer;
7569
7570 u8 no_dram_nic_offset[0x20];
7571
b4ff3a36 7572 u8 reserved_at_1220[0x6e40];
e281682b 7573
b4ff3a36 7574 u8 reserved_at_8060[0x1f];
e281682b
SM		 7575 u8 clear_int[0x1];
7576
7577 u8 health_syndrome[0x8];
7578 u8 health_counter[0x18];
7579
b4ff3a36 7580 u8 reserved_at_80a0[0x17fc0];
e281682b
SM		 7581};
7582
7583union mlx5_ifc_ports_control_registers_document_bits {
7584 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
7585 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
7586 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
7587 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
7588 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
7589 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
7590 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
7591 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
7592 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
7593 struct mlx5_ifc_pamp_reg_bits pamp_reg;
7594 struct mlx5_ifc_paos_reg_bits paos_reg;
7595 struct mlx5_ifc_pcap_reg_bits pcap_reg;
7596 struct mlx5_ifc_peir_reg_bits peir_reg;
7597 struct mlx5_ifc_pelc_reg_bits pelc_reg;
7598 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
1c64bf6f 7599 struct mlx5_ifc_ib_port_cntrs_grp_data_layout_bits ib_port_cntrs_grp_data_layout;
e281682b
SM		 7600 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
7601 struct mlx5_ifc_pifr_reg_bits pifr_reg;
7602 struct mlx5_ifc_pipg_reg_bits pipg_reg;
7603 struct mlx5_ifc_plbf_reg_bits plbf_reg;
7604 struct mlx5_ifc_plib_reg_bits plib_reg;
7605 struct mlx5_ifc_plpc_reg_bits plpc_reg;
7606 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
7607 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
7608 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
7609 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
7610 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
7611 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
7612 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
7613 struct mlx5_ifc_ppad_reg_bits ppad_reg;
7614 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
7615 struct mlx5_ifc_pplm_reg_bits pplm_reg;
7616 struct mlx5_ifc_pplr_reg_bits pplr_reg;
7617 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
7618 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
7619 struct mlx5_ifc_pspa_reg_bits pspa_reg;
7620 struct mlx5_ifc_ptas_reg_bits ptas_reg;
7621 struct mlx5_ifc_ptys_reg_bits ptys_reg;
7d5e1423 7622 struct mlx5_ifc_mlcr_reg_bits mlcr_reg;
e281682b
SM		 7623 struct mlx5_ifc_pude_reg_bits pude_reg;
7624 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
7625 struct mlx5_ifc_slrg_reg_bits slrg_reg;
7626 struct mlx5_ifc_sltp_reg_bits sltp_reg;
b4ff3a36 7627 u8 reserved_at_0[0x60e0];
e281682b
SM		 7628};
7629
7630union mlx5_ifc_debug_enhancements_document_bits {
7631 struct mlx5_ifc_health_buffer_bits health_buffer;
b4ff3a36 7632 u8 reserved_at_0[0x200];
e281682b
SM		 7633};
7634
7635union mlx5_ifc_uplink_pci_interface_document_bits {
7636 struct mlx5_ifc_initial_seg_bits initial_seg;
b4ff3a36 7637 u8 reserved_at_0[0x20060];
b775516b
EC		 7638};
7639
2cc43b49
MG		 7640struct mlx5_ifc_set_flow_table_root_out_bits {
7641 u8 status[0x8];
b4ff3a36 7642 u8 reserved_at_8[0x18];
2cc43b49
MG		 7643
7644 u8 syndrome[0x20];
7645
b4ff3a36 7646 u8 reserved_at_40[0x40];
2cc43b49
MG		 7647};
7648
7649struct mlx5_ifc_set_flow_table_root_in_bits {
7650 u8 opcode[0x10];
b4ff3a36 7651 u8 reserved_at_10[0x10];
2cc43b49 7652
b4ff3a36 7653 u8 reserved_at_20[0x10];
2cc43b49
MG		 7654 u8 op_mod[0x10];
7655
7d5e1423
SM		 7656 u8 other_vport[0x1];
7657 u8 reserved_at_41[0xf];
7658 u8 vport_number[0x10];
7659
7660 u8 reserved_at_60[0x20];
2cc43b49
MG		 7661
7662 u8 table_type[0x8];
b4ff3a36 7663 u8 reserved_at_88[0x18];
2cc43b49 7664
b4ff3a36 7665 u8 reserved_at_a0[0x8];
2cc43b49
MG		 7666 u8 table_id[0x18];
7667
b4ff3a36 7668 u8 reserved_at_c0[0x140];
2cc43b49
MG		 7669};
7670
34a40e68
MG		 7671enum {
7672 MLX5_MODIFY_FLOW_TABLE_MISS_TABLE_ID = 0x1,
7673};
7674
7675struct mlx5_ifc_modify_flow_table_out_bits {
7676 u8 status[0x8];
b4ff3a36 7677 u8 reserved_at_8[0x18];
34a40e68
MG		 7678
7679 u8 syndrome[0x20];
7680
b4ff3a36 7681 u8 reserved_at_40[0x40];
34a40e68
MG		 7682};
7683
7684struct mlx5_ifc_modify_flow_table_in_bits {
7685 u8 opcode[0x10];
b4ff3a36 7686 u8 reserved_at_10[0x10];
34a40e68 7687
b4ff3a36 7688 u8 reserved_at_20[0x10];
34a40e68
MG		 7689 u8 op_mod[0x10];
7690
7d5e1423
SM		 7691 u8 other_vport[0x1];
7692 u8 reserved_at_41[0xf];
7693 u8 vport_number[0x10];
34a40e68 7694
b4ff3a36 7695 u8 reserved_at_60[0x10];
34a40e68
MG		 7696 u8 modify_field_select[0x10];
7697
7698 u8 table_type[0x8];
b4ff3a36 7699 u8 reserved_at_88[0x18];
34a40e68 7700
b4ff3a36 7701 u8 reserved_at_a0[0x8];
34a40e68
MG		 7702 u8 table_id[0x18];
7703
b4ff3a36 7704 u8 reserved_at_c0[0x4];
34a40e68 7705 u8 table_miss_mode[0x4];
b4ff3a36 7706 u8 reserved_at_c8[0x18];
34a40e68 7707
b4ff3a36 7708 u8 reserved_at_e0[0x8];
34a40e68
MG		 7709 u8 table_miss_id[0x18];
7710
b4ff3a36 7711 u8 reserved_at_100[0x100];
34a40e68
MG		 7712};
7713
4f3961ee
SM		 7714struct mlx5_ifc_ets_tcn_config_reg_bits {
7715 u8 g[0x1];
7716 u8 b[0x1];
7717 u8 r[0x1];
7718 u8 reserved_at_3[0x9];
7719 u8 group[0x4];
7720 u8 reserved_at_10[0x9];
7721 u8 bw_allocation[0x7];
7722
7723 u8 reserved_at_20[0xc];
7724 u8 max_bw_units[0x4];
7725 u8 reserved_at_30[0x8];
7726 u8 max_bw_value[0x8];
7727};
7728
7729struct mlx5_ifc_ets_global_config_reg_bits {
7730 u8 reserved_at_0[0x2];
7731 u8 r[0x1];
7732 u8 reserved_at_3[0x1d];
7733
7734 u8 reserved_at_20[0xc];
7735 u8 max_bw_units[0x4];
7736 u8 reserved_at_30[0x8];
7737 u8 max_bw_value[0x8];
7738};
7739
7740struct mlx5_ifc_qetc_reg_bits {
7741 u8 reserved_at_0[0x8];
7742 u8 port_number[0x8];
7743 u8 reserved_at_10[0x30];
7744
7745 struct mlx5_ifc_ets_tcn_config_reg_bits tc_configuration[0x8];
7746 struct mlx5_ifc_ets_global_config_reg_bits global_configuration;
7747};
7748
7749struct mlx5_ifc_qtct_reg_bits {
7750 u8 reserved_at_0[0x8];
7751 u8 port_number[0x8];
7752 u8 reserved_at_10[0xd];
7753 u8 prio[0x3];
7754
7755 u8 reserved_at_20[0x1d];
7756 u8 tclass[0x3];
7757};
7758
7d5e1423
SM		 7759struct mlx5_ifc_mcia_reg_bits {
7760 u8 l[0x1];
7761 u8 reserved_at_1[0x7];
7762 u8 module[0x8];
7763 u8 reserved_at_10[0x8];
7764 u8 status[0x8];
7765
7766 u8 i2c_device_address[0x8];
7767 u8 page_number[0x8];
7768 u8 device_address[0x10];
7769
7770 u8 reserved_at_40[0x10];
7771 u8 size[0x10];
7772
7773 u8 reserved_at_60[0x20];
7774
7775 u8 dword_0[0x20];
7776 u8 dword_1[0x20];
7777 u8 dword_2[0x20];
7778 u8 dword_3[0x20];
7779 u8 dword_4[0x20];
7780 u8 dword_5[0x20];
7781 u8 dword_6[0x20];
7782 u8 dword_7[0x20];
7783 u8 dword_8[0x20];
7784 u8 dword_9[0x20];
7785 u8 dword_10[0x20];
7786 u8 dword_11[0x20];
7787};
7788
7486216b
SM		 7789struct mlx5_ifc_dcbx_param_bits {
7790 u8 dcbx_cee_cap[0x1];
7791 u8 dcbx_ieee_cap[0x1];
7792 u8 dcbx_standby_cap[0x1];
7793 u8 reserved_at_0[0x5];
7794 u8 port_number[0x8];
7795 u8 reserved_at_10[0xa];
7796 u8 max_application_table_size[6];
7797 u8 reserved_at_20[0x15];
7798 u8 version_oper[0x3];
7799 u8 reserved_at_38[5];
7800 u8 version_admin[0x3];
7801 u8 willing_admin[0x1];
7802 u8 reserved_at_41[0x3];
7803 u8 pfc_cap_oper[0x4];
7804 u8 reserved_at_48[0x4];
7805 u8 pfc_cap_admin[0x4];
7806 u8 reserved_at_50[0x4];
7807 u8 num_of_tc_oper[0x4];
7808 u8 reserved_at_58[0x4];
7809 u8 num_of_tc_admin[0x4];
7810 u8 remote_willing[0x1];
7811 u8 reserved_at_61[3];
7812 u8 remote_pfc_cap[4];
7813 u8 reserved_at_68[0x14];
7814 u8 remote_num_of_tc[0x4];
7815 u8 reserved_at_80[0x18];
7816 u8 error[0x8];
7817 u8 reserved_at_a0[0x160];
7818};
d29b796a 7819#endif /* MLX5_IFC_H */
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