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Merge branch 'netcp-next'
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d29b796a 1/*
e281682b 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved.
d29b796a
EC		 3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
e281682b 31*/
d29b796a
EC		 32#ifndef MLX5_IFC_H
33#define MLX5_IFC_H
34
e281682b
SM		 35enum {
36 MLX5_EVENT_TYPE_CODING_COMPLETION_EVENTS = 0x0,
37 MLX5_EVENT_TYPE_CODING_PATH_MIGRATED_SUCCEEDED = 0x1,
38 MLX5_EVENT_TYPE_CODING_COMMUNICATION_ESTABLISHED = 0x2,
39 MLX5_EVENT_TYPE_CODING_SEND_QUEUE_DRAINED = 0x3,
40 MLX5_EVENT_TYPE_CODING_LAST_WQE_REACHED = 0x13,
41 MLX5_EVENT_TYPE_CODING_SRQ_LIMIT = 0x14,
42 MLX5_EVENT_TYPE_CODING_DCT_ALL_CONNECTIONS_CLOSED = 0x1c,
43 MLX5_EVENT_TYPE_CODING_DCT_ACCESS_KEY_VIOLATION = 0x1d,
44 MLX5_EVENT_TYPE_CODING_CQ_ERROR = 0x4,
45 MLX5_EVENT_TYPE_CODING_LOCAL_WQ_CATASTROPHIC_ERROR = 0x5,
46 MLX5_EVENT_TYPE_CODING_PATH_MIGRATION_FAILED = 0x7,
47 MLX5_EVENT_TYPE_CODING_PAGE_FAULT_EVENT = 0xc,
48 MLX5_EVENT_TYPE_CODING_INVALID_REQUEST_LOCAL_WQ_ERROR = 0x10,
49 MLX5_EVENT_TYPE_CODING_LOCAL_ACCESS_VIOLATION_WQ_ERROR = 0x11,
50 MLX5_EVENT_TYPE_CODING_LOCAL_SRQ_CATASTROPHIC_ERROR = 0x12,
51 MLX5_EVENT_TYPE_CODING_INTERNAL_ERROR = 0x8,
52 MLX5_EVENT_TYPE_CODING_PORT_STATE_CHANGE = 0x9,
53 MLX5_EVENT_TYPE_CODING_GPIO_EVENT = 0x15,
54 MLX5_EVENT_TYPE_CODING_REMOTE_CONFIGURATION_PROTOCOL_EVENT = 0x19,
55 MLX5_EVENT_TYPE_CODING_DOORBELL_BLUEFLAME_CONGESTION_EVENT = 0x1a,
56 MLX5_EVENT_TYPE_CODING_STALL_VL_EVENT = 0x1b,
57 MLX5_EVENT_TYPE_CODING_DROPPED_PACKET_LOGGED_EVENT = 0x1f,
58 MLX5_EVENT_TYPE_CODING_COMMAND_INTERFACE_COMPLETION = 0xa,
59 MLX5_EVENT_TYPE_CODING_PAGE_REQUEST = 0xb
60};
61
62enum {
63 MLX5_MODIFY_TIR_BITMASK_LRO = 0x0,
64 MLX5_MODIFY_TIR_BITMASK_INDIRECT_TABLE = 0x1,
65 MLX5_MODIFY_TIR_BITMASK_HASH = 0x2,
66 MLX5_MODIFY_TIR_BITMASK_TUNNELED_OFFLOAD_EN = 0x3
67};
68
d29b796a
EC		 69enum {
70 MLX5_CMD_OP_QUERY_HCA_CAP = 0x100,
71 MLX5_CMD_OP_QUERY_ADAPTER = 0x101,
72 MLX5_CMD_OP_INIT_HCA = 0x102,
73 MLX5_CMD_OP_TEARDOWN_HCA = 0x103,
74 MLX5_CMD_OP_ENABLE_HCA = 0x104,
75 MLX5_CMD_OP_DISABLE_HCA = 0x105,
76 MLX5_CMD_OP_QUERY_PAGES = 0x107,
77 MLX5_CMD_OP_MANAGE_PAGES = 0x108,
78 MLX5_CMD_OP_SET_HCA_CAP = 0x109,
e281682b
SM		 79 MLX5_CMD_OP_QUERY_ISSI = 0x10a,
80 MLX5_CMD_OP_SET_ISSI = 0x10b,
d29b796a
EC		 81 MLX5_CMD_OP_CREATE_MKEY = 0x200,
82 MLX5_CMD_OP_QUERY_MKEY = 0x201,
83 MLX5_CMD_OP_DESTROY_MKEY = 0x202,
84 MLX5_CMD_OP_QUERY_SPECIAL_CONTEXTS = 0x203,
85 MLX5_CMD_OP_PAGE_FAULT_RESUME = 0x204,
86 MLX5_CMD_OP_CREATE_EQ = 0x301,
87 MLX5_CMD_OP_DESTROY_EQ = 0x302,
88 MLX5_CMD_OP_QUERY_EQ = 0x303,
89 MLX5_CMD_OP_GEN_EQE = 0x304,
90 MLX5_CMD_OP_CREATE_CQ = 0x400,
91 MLX5_CMD_OP_DESTROY_CQ = 0x401,
92 MLX5_CMD_OP_QUERY_CQ = 0x402,
93 MLX5_CMD_OP_MODIFY_CQ = 0x403,
94 MLX5_CMD_OP_CREATE_QP = 0x500,
95 MLX5_CMD_OP_DESTROY_QP = 0x501,
96 MLX5_CMD_OP_RST2INIT_QP = 0x502,
97 MLX5_CMD_OP_INIT2RTR_QP = 0x503,
98 MLX5_CMD_OP_RTR2RTS_QP = 0x504,
99 MLX5_CMD_OP_RTS2RTS_QP = 0x505,
100 MLX5_CMD_OP_SQERR2RTS_QP = 0x506,
101 MLX5_CMD_OP_2ERR_QP = 0x507,
102 MLX5_CMD_OP_2RST_QP = 0x50a,
103 MLX5_CMD_OP_QUERY_QP = 0x50b,
e281682b 104 MLX5_CMD_OP_SQD_RTS_QP = 0x50c,
d29b796a
EC		 105 MLX5_CMD_OP_INIT2INIT_QP = 0x50e,
106 MLX5_CMD_OP_CREATE_PSV = 0x600,
107 MLX5_CMD_OP_DESTROY_PSV = 0x601,
108 MLX5_CMD_OP_CREATE_SRQ = 0x700,
109 MLX5_CMD_OP_DESTROY_SRQ = 0x701,
110 MLX5_CMD_OP_QUERY_SRQ = 0x702,
111 MLX5_CMD_OP_ARM_RQ = 0x703,
e281682b
SM		 112 MLX5_CMD_OP_CREATE_XRC_SRQ = 0x705,
113 MLX5_CMD_OP_DESTROY_XRC_SRQ = 0x706,
114 MLX5_CMD_OP_QUERY_XRC_SRQ = 0x707,
115 MLX5_CMD_OP_ARM_XRC_SRQ = 0x708,
d29b796a
EC		 116 MLX5_CMD_OP_CREATE_DCT = 0x710,
117 MLX5_CMD_OP_DESTROY_DCT = 0x711,
118 MLX5_CMD_OP_DRAIN_DCT = 0x712,
119 MLX5_CMD_OP_QUERY_DCT = 0x713,
120 MLX5_CMD_OP_ARM_DCT_FOR_KEY_VIOLATION = 0x714,
121 MLX5_CMD_OP_QUERY_VPORT_STATE = 0x750,
122 MLX5_CMD_OP_MODIFY_VPORT_STATE = 0x751,
123 MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT = 0x752,
124 MLX5_CMD_OP_MODIFY_ESW_VPORT_CONTEXT = 0x753,
125 MLX5_CMD_OP_QUERY_NIC_VPORT_CONTEXT = 0x754,
126 MLX5_CMD_OP_MODIFY_NIC_VPORT_CONTEXT = 0x755,
e281682b 127 MLX5_CMD_OP_QUERY_ROCE_ADDRESS = 0x760,
d29b796a 128 MLX5_CMD_OP_SET_ROCE_ADDRESS = 0x761,
e281682b
SM		 129 MLX5_CMD_OP_QUERY_HCA_VPORT_CONTEXT = 0x762,
130 MLX5_CMD_OP_MODIFY_HCA_VPORT_CONTEXT = 0x763,
131 MLX5_CMD_OP_QUERY_HCA_VPORT_GID = 0x764,
132 MLX5_CMD_OP_QUERY_HCA_VPORT_PKEY = 0x765,
d29b796a
EC		 133 MLX5_CMD_OP_QUERY_VPORT_COUNTER = 0x770,
134 MLX5_CMD_OP_ALLOC_Q_COUNTER = 0x771,
135 MLX5_CMD_OP_DEALLOC_Q_COUNTER = 0x772,
136 MLX5_CMD_OP_QUERY_Q_COUNTER = 0x773,
137 MLX5_CMD_OP_ALLOC_PD = 0x800,
138 MLX5_CMD_OP_DEALLOC_PD = 0x801,
139 MLX5_CMD_OP_ALLOC_UAR = 0x802,
140 MLX5_CMD_OP_DEALLOC_UAR = 0x803,
141 MLX5_CMD_OP_CONFIG_INT_MODERATION = 0x804,
142 MLX5_CMD_OP_ACCESS_REG = 0x805,
143 MLX5_CMD_OP_ATTACH_TO_MCG = 0x806,
e281682b 144 MLX5_CMD_OP_DETTACH_FROM_MCG = 0x807,
d29b796a
EC		 145 MLX5_CMD_OP_GET_DROPPED_PACKET_LOG = 0x80a,
146 MLX5_CMD_OP_MAD_IFC = 0x50d,
147 MLX5_CMD_OP_QUERY_MAD_DEMUX = 0x80b,
148 MLX5_CMD_OP_SET_MAD_DEMUX = 0x80c,
149 MLX5_CMD_OP_NOP = 0x80d,
150 MLX5_CMD_OP_ALLOC_XRCD = 0x80e,
151 MLX5_CMD_OP_DEALLOC_XRCD = 0x80f,
e281682b
SM		 152 MLX5_CMD_OP_ALLOC_TRANSPORT_DOMAIN = 0x816,
153 MLX5_CMD_OP_DEALLOC_TRANSPORT_DOMAIN = 0x817,
154 MLX5_CMD_OP_QUERY_CONG_STATUS = 0x822,
155 MLX5_CMD_OP_MODIFY_CONG_STATUS = 0x823,
156 MLX5_CMD_OP_QUERY_CONG_PARAMS = 0x824,
157 MLX5_CMD_OP_MODIFY_CONG_PARAMS = 0x825,
158 MLX5_CMD_OP_QUERY_CONG_STATISTICS = 0x826,
159 MLX5_CMD_OP_ADD_VXLAN_UDP_DPORT = 0x827,
160 MLX5_CMD_OP_DELETE_VXLAN_UDP_DPORT = 0x828,
161 MLX5_CMD_OP_SET_L2_TABLE_ENTRY = 0x829,
162 MLX5_CMD_OP_QUERY_L2_TABLE_ENTRY = 0x82a,
163 MLX5_CMD_OP_DELETE_L2_TABLE_ENTRY = 0x82b,
d29b796a
EC		 164 MLX5_CMD_OP_CREATE_TIR = 0x900,
165 MLX5_CMD_OP_MODIFY_TIR = 0x901,
166 MLX5_CMD_OP_DESTROY_TIR = 0x902,
167 MLX5_CMD_OP_QUERY_TIR = 0x903,
d29b796a
EC		 168 MLX5_CMD_OP_CREATE_SQ = 0x904,
169 MLX5_CMD_OP_MODIFY_SQ = 0x905,
170 MLX5_CMD_OP_DESTROY_SQ = 0x906,
171 MLX5_CMD_OP_QUERY_SQ = 0x907,
172 MLX5_CMD_OP_CREATE_RQ = 0x908,
173 MLX5_CMD_OP_MODIFY_RQ = 0x909,
174 MLX5_CMD_OP_DESTROY_RQ = 0x90a,
175 MLX5_CMD_OP_QUERY_RQ = 0x90b,
176 MLX5_CMD_OP_CREATE_RMP = 0x90c,
177 MLX5_CMD_OP_MODIFY_RMP = 0x90d,
178 MLX5_CMD_OP_DESTROY_RMP = 0x90e,
179 MLX5_CMD_OP_QUERY_RMP = 0x90f,
e281682b
SM		 180 MLX5_CMD_OP_CREATE_TIS = 0x912,
181 MLX5_CMD_OP_MODIFY_TIS = 0x913,
182 MLX5_CMD_OP_DESTROY_TIS = 0x914,
183 MLX5_CMD_OP_QUERY_TIS = 0x915,
184 MLX5_CMD_OP_CREATE_RQT = 0x916,
185 MLX5_CMD_OP_MODIFY_RQT = 0x917,
186 MLX5_CMD_OP_DESTROY_RQT = 0x918,
187 MLX5_CMD_OP_QUERY_RQT = 0x919,
188 MLX5_CMD_OP_CREATE_FLOW_TABLE = 0x930,
189 MLX5_CMD_OP_DESTROY_FLOW_TABLE = 0x931,
190 MLX5_CMD_OP_QUERY_FLOW_TABLE = 0x932,
191 MLX5_CMD_OP_CREATE_FLOW_GROUP = 0x933,
192 MLX5_CMD_OP_DESTROY_FLOW_GROUP = 0x934,
193 MLX5_CMD_OP_QUERY_FLOW_GROUP = 0x935,
194 MLX5_CMD_OP_SET_FLOW_TABLE_ENTRY = 0x936,
195 MLX5_CMD_OP_QUERY_FLOW_TABLE_ENTRY = 0x937,
196 MLX5_CMD_OP_DELETE_FLOW_TABLE_ENTRY = 0x938
197};
198
199struct mlx5_ifc_flow_table_fields_supported_bits {
200 u8 outer_dmac[0x1];
201 u8 outer_smac[0x1];
202 u8 outer_ether_type[0x1];
203 u8 reserved_0[0x1];
204 u8 outer_first_prio[0x1];
205 u8 outer_first_cfi[0x1];
206 u8 outer_first_vid[0x1];
207 u8 reserved_1[0x1];
208 u8 outer_second_prio[0x1];
209 u8 outer_second_cfi[0x1];
210 u8 outer_second_vid[0x1];
211 u8 reserved_2[0x1];
212 u8 outer_sip[0x1];
213 u8 outer_dip[0x1];
214 u8 outer_frag[0x1];
215 u8 outer_ip_protocol[0x1];
216 u8 outer_ip_ecn[0x1];
217 u8 outer_ip_dscp[0x1];
218 u8 outer_udp_sport[0x1];
219 u8 outer_udp_dport[0x1];
220 u8 outer_tcp_sport[0x1];
221 u8 outer_tcp_dport[0x1];
222 u8 outer_tcp_flags[0x1];
223 u8 outer_gre_protocol[0x1];
224 u8 outer_gre_key[0x1];
225 u8 outer_vxlan_vni[0x1];
226 u8 reserved_3[0x5];
227 u8 source_eswitch_port[0x1];
228
229 u8 inner_dmac[0x1];
230 u8 inner_smac[0x1];
231 u8 inner_ether_type[0x1];
232 u8 reserved_4[0x1];
233 u8 inner_first_prio[0x1];
234 u8 inner_first_cfi[0x1];
235 u8 inner_first_vid[0x1];
236 u8 reserved_5[0x1];
237 u8 inner_second_prio[0x1];
238 u8 inner_second_cfi[0x1];
239 u8 inner_second_vid[0x1];
240 u8 reserved_6[0x1];
241 u8 inner_sip[0x1];
242 u8 inner_dip[0x1];
243 u8 inner_frag[0x1];
244 u8 inner_ip_protocol[0x1];
245 u8 inner_ip_ecn[0x1];
246 u8 inner_ip_dscp[0x1];
247 u8 inner_udp_sport[0x1];
248 u8 inner_udp_dport[0x1];
249 u8 inner_tcp_sport[0x1];
250 u8 inner_tcp_dport[0x1];
251 u8 inner_tcp_flags[0x1];
252 u8 reserved_7[0x9];
253
254 u8 reserved_8[0x40];
255};
256
257struct mlx5_ifc_flow_table_prop_layout_bits {
258 u8 ft_support[0x1];
259 u8 reserved_0[0x1f];
260
261 u8 reserved_1[0x2];
262 u8 log_max_ft_size[0x6];
263 u8 reserved_2[0x10];
264 u8 max_ft_level[0x8];
265
266 u8 reserved_3[0x20];
267
268 u8 reserved_4[0x18];
269 u8 log_max_ft_num[0x8];
270
271 u8 reserved_5[0x18];
272 u8 log_max_destination[0x8];
273
274 u8 reserved_6[0x18];
275 u8 log_max_flow[0x8];
276
277 u8 reserved_7[0x40];
278
279 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_support;
280
281 struct mlx5_ifc_flow_table_fields_supported_bits ft_field_bitmask_support;
282};
283
284struct mlx5_ifc_odp_per_transport_service_cap_bits {
285 u8 send[0x1];
286 u8 receive[0x1];
287 u8 write[0x1];
288 u8 read[0x1];
289 u8 reserved_0[0x1];
290 u8 srq_receive[0x1];
291 u8 reserved_1[0x1a];
292};
293
294struct mlx5_ifc_fte_match_set_lyr_2_4_bits {
295 u8 smac_47_16[0x20];
296
297 u8 smac_15_0[0x10];
298 u8 ethertype[0x10];
299
300 u8 dmac_47_16[0x20];
301
302 u8 dmac_15_0[0x10];
303 u8 first_prio[0x3];
304 u8 first_cfi[0x1];
305 u8 first_vid[0xc];
306
307 u8 ip_protocol[0x8];
308 u8 ip_dscp[0x6];
309 u8 ip_ecn[0x2];
310 u8 vlan_tag[0x1];
311 u8 reserved_0[0x1];
312 u8 frag[0x1];
313 u8 reserved_1[0x4];
314 u8 tcp_flags[0x9];
315
316 u8 tcp_sport[0x10];
317 u8 tcp_dport[0x10];
318
319 u8 reserved_2[0x20];
320
321 u8 udp_sport[0x10];
322 u8 udp_dport[0x10];
323
324 u8 src_ip[4][0x20];
325
326 u8 dst_ip[4][0x20];
327};
328
329struct mlx5_ifc_fte_match_set_misc_bits {
330 u8 reserved_0[0x20];
331
332 u8 reserved_1[0x10];
333 u8 source_port[0x10];
334
335 u8 outer_second_prio[0x3];
336 u8 outer_second_cfi[0x1];
337 u8 outer_second_vid[0xc];
338 u8 inner_second_prio[0x3];
339 u8 inner_second_cfi[0x1];
340 u8 inner_second_vid[0xc];
341
342 u8 outer_second_vlan_tag[0x1];
343 u8 inner_second_vlan_tag[0x1];
344 u8 reserved_2[0xe];
345 u8 gre_protocol[0x10];
346
347 u8 gre_key_h[0x18];
348 u8 gre_key_l[0x8];
349
350 u8 vxlan_vni[0x18];
351 u8 reserved_3[0x8];
352
353 u8 reserved_4[0x20];
354
355 u8 reserved_5[0xc];
356 u8 outer_ipv6_flow_label[0x14];
357
358 u8 reserved_6[0xc];
359 u8 inner_ipv6_flow_label[0x14];
360
361 u8 reserved_7[0xe0];
362};
363
364struct mlx5_ifc_cmd_pas_bits {
365 u8 pa_h[0x20];
366
367 u8 pa_l[0x14];
368 u8 reserved_0[0xc];
369};
370
371struct mlx5_ifc_uint64_bits {
372 u8 hi[0x20];
373
374 u8 lo[0x20];
375};
376
377enum {
378 MLX5_ADS_STAT_RATE_NO_LIMIT = 0x0,
379 MLX5_ADS_STAT_RATE_2_5GBPS = 0x7,
380 MLX5_ADS_STAT_RATE_10GBPS = 0x8,
381 MLX5_ADS_STAT_RATE_30GBPS = 0x9,
382 MLX5_ADS_STAT_RATE_5GBPS = 0xa,
383 MLX5_ADS_STAT_RATE_20GBPS = 0xb,
384 MLX5_ADS_STAT_RATE_40GBPS = 0xc,
385 MLX5_ADS_STAT_RATE_60GBPS = 0xd,
386 MLX5_ADS_STAT_RATE_80GBPS = 0xe,
387 MLX5_ADS_STAT_RATE_120GBPS = 0xf,
388};
389
390struct mlx5_ifc_ads_bits {
391 u8 fl[0x1];
392 u8 free_ar[0x1];
393 u8 reserved_0[0xe];
394 u8 pkey_index[0x10];
395
396 u8 reserved_1[0x8];
397 u8 grh[0x1];
398 u8 mlid[0x7];
399 u8 rlid[0x10];
400
401 u8 ack_timeout[0x5];
402 u8 reserved_2[0x3];
403 u8 src_addr_index[0x8];
404 u8 reserved_3[0x4];
405 u8 stat_rate[0x4];
406 u8 hop_limit[0x8];
407
408 u8 reserved_4[0x4];
409 u8 tclass[0x8];
410 u8 flow_label[0x14];
411
412 u8 rgid_rip[16][0x8];
413
414 u8 reserved_5[0x4];
415 u8 f_dscp[0x1];
416 u8 f_ecn[0x1];
417 u8 reserved_6[0x1];
418 u8 f_eth_prio[0x1];
419 u8 ecn[0x2];
420 u8 dscp[0x6];
421 u8 udp_sport[0x10];
422
423 u8 dei_cfi[0x1];
424 u8 eth_prio[0x3];
425 u8 sl[0x4];
426 u8 port[0x8];
427 u8 rmac_47_32[0x10];
428
429 u8 rmac_31_0[0x20];
430};
431
432struct mlx5_ifc_flow_table_nic_cap_bits {
433 u8 reserved_0[0x200];
434
435 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive;
436
437 u8 reserved_1[0x200];
438
439 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_receive_sniffer;
440
441 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit;
442
443 u8 reserved_2[0x200];
444
445 struct mlx5_ifc_flow_table_prop_layout_bits flow_table_properties_nic_transmit_sniffer;
446
447 u8 reserved_3[0x7200];
448};
449
450struct mlx5_ifc_per_protocol_networking_offload_caps_bits {
451 u8 csum_cap[0x1];
452 u8 vlan_cap[0x1];
453 u8 lro_cap[0x1];
454 u8 lro_psh_flag[0x1];
455 u8 lro_time_stamp[0x1];
456 u8 reserved_0[0x6];
457 u8 max_lso_cap[0x5];
458 u8 reserved_1[0x4];
459 u8 rss_ind_tbl_cap[0x4];
460 u8 reserved_2[0x3];
461 u8 tunnel_lso_const_out_ip_id[0x1];
462 u8 reserved_3[0x2];
463 u8 tunnel_statless_gre[0x1];
464 u8 tunnel_stateless_vxlan[0x1];
465
466 u8 reserved_4[0x20];
467
468 u8 reserved_5[0x10];
469 u8 lro_min_mss_size[0x10];
470
471 u8 reserved_6[0x120];
472
473 u8 lro_timer_supported_periods[4][0x20];
474
475 u8 reserved_7[0x600];
476};
477
478struct mlx5_ifc_roce_cap_bits {
479 u8 roce_apm[0x1];
480 u8 reserved_0[0x1f];
481
482 u8 reserved_1[0x60];
483
484 u8 reserved_2[0xc];
485 u8 l3_type[0x4];
486 u8 reserved_3[0x8];
487 u8 roce_version[0x8];
488
489 u8 reserved_4[0x10];
490 u8 r_roce_dest_udp_port[0x10];
491
492 u8 r_roce_max_src_udp_port[0x10];
493 u8 r_roce_min_src_udp_port[0x10];
494
495 u8 reserved_5[0x10];
496 u8 roce_address_table_size[0x10];
497
498 u8 reserved_6[0x700];
499};
500
501enum {
502 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_1_BYTE = 0x0,
503 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_2_BYTES = 0x2,
504 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_4_BYTES = 0x4,
505 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_8_BYTES = 0x8,
506 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_16_BYTES = 0x10,
507 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_32_BYTES = 0x20,
508 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_64_BYTES = 0x40,
509 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_128_BYTES = 0x80,
510 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_QP_256_BYTES = 0x100,
511};
512
513enum {
514 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_1_BYTE = 0x1,
515 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_2_BYTES = 0x2,
516 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_4_BYTES = 0x4,
517 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_8_BYTES = 0x8,
518 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_16_BYTES = 0x10,
519 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_32_BYTES = 0x20,
520 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_64_BYTES = 0x40,
521 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_128_BYTES = 0x80,
522 MLX5_ATOMIC_CAPS_ATOMIC_SIZE_DC_256_BYTES = 0x100,
523};
524
525struct mlx5_ifc_atomic_caps_bits {
526 u8 reserved_0[0x40];
527
528 u8 atomic_req_endianness[0x1];
529 u8 reserved_1[0x1f];
530
531 u8 reserved_2[0x20];
532
533 u8 reserved_3[0x10];
534 u8 atomic_operations[0x10];
535
536 u8 reserved_4[0x10];
537 u8 atomic_size_qp[0x10];
538
539 u8 reserved_5[0x10];
540 u8 atomic_size_dc[0x10];
541
542 u8 reserved_6[0x720];
543};
544
545struct mlx5_ifc_odp_cap_bits {
546 u8 reserved_0[0x40];
547
548 u8 sig[0x1];
549 u8 reserved_1[0x1f];
550
551 u8 reserved_2[0x20];
552
553 struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps;
554
555 struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps;
556
557 struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps;
558
559 u8 reserved_3[0x720];
560};
561
562enum {
563 MLX5_WQ_TYPE_LINKED_LIST = 0x0,
564 MLX5_WQ_TYPE_CYCLIC = 0x1,
565 MLX5_WQ_TYPE_STRQ = 0x2,
566};
567
568enum {
569 MLX5_WQ_END_PAD_MODE_NONE = 0x0,
570 MLX5_WQ_END_PAD_MODE_ALIGN = 0x1,
571};
572
573enum {
574 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_8_GID_ENTRIES = 0x0,
575 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_16_GID_ENTRIES = 0x1,
576 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_32_GID_ENTRIES = 0x2,
577 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_64_GID_ENTRIES = 0x3,
578 MLX5_CMD_HCA_CAP_GID_TABLE_SIZE_128_GID_ENTRIES = 0x4,
579};
580
581enum {
582 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_128_ENTRIES = 0x0,
583 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_256_ENTRIES = 0x1,
584 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_512_ENTRIES = 0x2,
585 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_1K_ENTRIES = 0x3,
586 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_2K_ENTRIES = 0x4,
587 MLX5_CMD_HCA_CAP_PKEY_TABLE_SIZE_4K_ENTRIES = 0x5,
588};
589
590enum {
591 MLX5_CMD_HCA_CAP_PORT_TYPE_IB = 0x0,
592 MLX5_CMD_HCA_CAP_PORT_TYPE_ETHERNET = 0x1,
593};
594
595enum {
596 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_DISABLED = 0x0,
597 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_INITIAL_STATE = 0x1,
598 MLX5_CMD_HCA_CAP_CMDIF_CHECKSUM_ENABLED = 0x3,
599};
600
601enum {
602 MLX5_CAP_PORT_TYPE_IB = 0x0,
603 MLX5_CAP_PORT_TYPE_ETH = 0x1,
d29b796a
EC		 604};
605
b775516b
EC		 606struct mlx5_ifc_cmd_hca_cap_bits {
607 u8 reserved_0[0x80];
608
609 u8 log_max_srq_sz[0x8];
610 u8 log_max_qp_sz[0x8];
611 u8 reserved_1[0xb];
612 u8 log_max_qp[0x5];
613
e281682b
SM		 614 u8 reserved_2[0xb];
615 u8 log_max_srq[0x5];
b775516b
EC		 616 u8 reserved_3[0x10];
617
618 u8 reserved_4[0x8];
619 u8 log_max_cq_sz[0x8];
620 u8 reserved_5[0xb];
621 u8 log_max_cq[0x5];
622
623 u8 log_max_eq_sz[0x8];
624 u8 reserved_6[0x2];
625 u8 log_max_mkey[0x6];
626 u8 reserved_7[0xc];
627 u8 log_max_eq[0x4];
628
629 u8 max_indirection[0x8];
630 u8 reserved_8[0x1];
631 u8 log_max_mrw_sz[0x7];
632 u8 reserved_9[0x2];
633 u8 log_max_bsf_list_size[0x6];
634 u8 reserved_10[0x2];
635 u8 log_max_klm_list_size[0x6];
636
637 u8 reserved_11[0xa];
638 u8 log_max_ra_req_dc[0x6];
639 u8 reserved_12[0xa];
640 u8 log_max_ra_res_dc[0x6];
641
642 u8 reserved_13[0xa];
643 u8 log_max_ra_req_qp[0x6];
644 u8 reserved_14[0xa];
645 u8 log_max_ra_res_qp[0x6];
646
647 u8 pad_cap[0x1];
648 u8 cc_query_allowed[0x1];
649 u8 cc_modify_allowed[0x1];
e281682b
SM		 650 u8 reserved_15[0xd];
651 u8 gid_table_size[0x10];
b775516b 652
e281682b
SM		 653 u8 out_of_seq_cnt[0x1];
654 u8 vport_counters[0x1];
655 u8 reserved_16[0x4];
b775516b
EC		 656 u8 max_qp_cnt[0xa];
657 u8 pkey_table_size[0x10];
658
e281682b
SM		 659 u8 vport_group_manager[0x1];
660 u8 vhca_group_manager[0x1];
661 u8 ib_virt[0x1];
662 u8 eth_virt[0x1];
663 u8 reserved_17[0x1];
664 u8 ets[0x1];
665 u8 nic_flow_table[0x1];
666 u8 reserved_18[0x4];
b775516b 667 u8 local_ca_ack_delay[0x5];
e281682b
SM		 668 u8 reserved_19[0x6];
669 u8 port_type[0x2];
b775516b
EC		 670 u8 num_ports[0x8];
671
e281682b 672 u8 reserved_20[0x3];
b775516b 673 u8 log_max_msg[0x5];
e281682b 674 u8 reserved_21[0x18];
b775516b
EC		 675
676 u8 stat_rate_support[0x10];
e281682b
SM		 677 u8 reserved_22[0xc];
678 u8 cqe_version[0x4];
b775516b 679
e281682b
SM		 680 u8 compact_address_vector[0x1];
681 u8 reserved_23[0xe];
682 u8 drain_sigerr[0x1];
b775516b
EC		 683 u8 cmdif_checksum[0x2];
684 u8 sigerr_cqe[0x1];
e281682b 685 u8 reserved_24[0x1];
b775516b
EC		 686 u8 wq_signature[0x1];
687 u8 sctr_data_cqe[0x1];
e281682b 688 u8 reserved_25[0x1];
b775516b
EC		 689 u8 sho[0x1];
690 u8 tph[0x1];
691 u8 rf[0x1];
e281682b
SM		 692 u8 dct[0x1];
693 u8 reserved_26[0x1];
694 u8 eth_net_offloads[0x1];
b775516b
EC		 695 u8 roce[0x1];
696 u8 atomic[0x1];
e281682b 697 u8 reserved_27[0x1];
b775516b
EC		 698
699 u8 cq_oi[0x1];
700 u8 cq_resize[0x1];
701 u8 cq_moderation[0x1];
e281682b
SM		 702 u8 reserved_28[0x3];
703 u8 cq_eq_remap[0x1];
b775516b
EC		 704 u8 pg[0x1];
705 u8 block_lb_mc[0x1];
e281682b
SM		 706 u8 reserved_29[0x1];
707 u8 scqe_break_moderation[0x1];
708 u8 reserved_30[0x1];
b775516b 709 u8 cd[0x1];
e281682b 710 u8 reserved_31[0x1];
b775516b 711 u8 apm[0x1];
e281682b 712 u8 reserved_32[0x7];
b775516b
EC		 713 u8 qkv[0x1];
714 u8 pkv[0x1];
e281682b 715 u8 reserved_33[0x4];
b775516b
EC		 716 u8 xrc[0x1];
717 u8 ud[0x1];
718 u8 uc[0x1];
719 u8 rc[0x1];
720
e281682b 721 u8 reserved_34[0xa];
b775516b 722 u8 uar_sz[0x6];
e281682b 723 u8 reserved_35[0x8];
b775516b
EC		 724 u8 log_pg_sz[0x8];
725
726 u8 bf[0x1];
e281682b
SM		 727 u8 reserved_36[0x1];
728 u8 pad_tx_eth_packet[0x1];
729 u8 reserved_37[0x8];
b775516b 730 u8 log_bf_reg_size[0x5];
e281682b 731 u8 reserved_38[0x10];
b775516b 732
e281682b 733 u8 reserved_39[0x10];
b775516b
EC		 734 u8 max_wqe_sz_sq[0x10];
735
e281682b 736 u8 reserved_40[0x10];
b775516b
EC		 737 u8 max_wqe_sz_rq[0x10];
738
e281682b 739 u8 reserved_41[0x10];
b775516b
EC		 740 u8 max_wqe_sz_sq_dc[0x10];
741
e281682b 742 u8 reserved_42[0x7];
b775516b
EC		 743 u8 max_qp_mcg[0x19];
744
e281682b 745 u8 reserved_43[0x18];
b775516b
EC		 746 u8 log_max_mcg[0x8];
747
e281682b
SM		 748 u8 reserved_44[0x3];
749 u8 log_max_transport_domain[0x5];
750 u8 reserved_45[0x3];
b775516b 751 u8 log_max_pd[0x5];
e281682b 752 u8 reserved_46[0xb];
b775516b
EC		 753 u8 log_max_xrcd[0x5];
754
e281682b 755 u8 reserved_47[0x20];
b775516b 756
e281682b 757 u8 reserved_48[0x3];
b775516b 758 u8 log_max_rq[0x5];
e281682b 759 u8 reserved_49[0x3];
b775516b 760 u8 log_max_sq[0x5];
e281682b 761 u8 reserved_50[0x3];
b775516b 762 u8 log_max_tir[0x5];
e281682b 763 u8 reserved_51[0x3];
b775516b
EC		 764 u8 log_max_tis[0x5];
765
e281682b
SM		 766 u8 basic_cyclic_rcv_wqe[0x1];
767 u8 reserved_52[0x2];
768 u8 log_max_rmp[0x5];
769 u8 reserved_53[0x3];
770 u8 log_max_rqt[0x5];
771 u8 reserved_54[0x3];
772 u8 log_max_rqt_size[0x5];
773 u8 reserved_55[0x3];
b775516b
EC		 774 u8 log_max_tis_per_sq[0x5];
775
e281682b
SM		 776 u8 reserved_56[0x3];
777 u8 log_max_stride_sz_rq[0x5];
778 u8 reserved_57[0x3];
779 u8 log_min_stride_sz_rq[0x5];
780 u8 reserved_58[0x3];
781 u8 log_max_stride_sz_sq[0x5];
782 u8 reserved_59[0x3];
783 u8 log_min_stride_sz_sq[0x5];
784
785 u8 reserved_60[0x1b];
786 u8 log_max_wq_sz[0x5];
787
788 u8 reserved_61[0xa0];
b775516b 789
e281682b
SM		 790 u8 reserved_62[0x3];
791 u8 log_max_l2_table[0x5];
792 u8 reserved_63[0x8];
b775516b
EC		 793 u8 log_uar_page_sz[0x10];
794
e281682b 795 u8 reserved_64[0x100];
b775516b 796
e281682b 797 u8 reserved_65[0x1f];
b775516b
EC		 798 u8 cqe_zip[0x1];
799
800 u8 cqe_zip_timeout[0x10];
801 u8 cqe_zip_max_num[0x10];
802
e281682b 803 u8 reserved_66[0x220];
b775516b
EC		 804};
805
e281682b
SM		 806enum {
807 MLX5_DEST_FORMAT_STRUCT_DESTINATION_TYPE_FLOW_TABLE_ = 0x1,
808 MLX5_DEST_FORMAT_STRUCT_DESTINATION_TYPE_TIR = 0x2,
809};
b775516b 810
e281682b
SM		 811struct mlx5_ifc_dest_format_struct_bits {
812 u8 destination_type[0x8];
813 u8 destination_id[0x18];
b775516b 814
e281682b
SM		 815 u8 reserved_0[0x20];
816};
817
818struct mlx5_ifc_fte_match_param_bits {
819 struct mlx5_ifc_fte_match_set_lyr_2_4_bits outer_headers;
820
821 struct mlx5_ifc_fte_match_set_misc_bits misc_parameters;
822
823 struct mlx5_ifc_fte_match_set_lyr_2_4_bits inner_headers;
b775516b 824
e281682b 825 u8 reserved_0[0xa00];
b775516b
EC		 826};
827
e281682b
SM		 828enum {
829 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_SRC_IP = 0x0,
830 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_DST_IP = 0x1,
831 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_SPORT = 0x2,
832 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_L4_DPORT = 0x3,
833 MLX5_RX_HASH_FIELD_SELECT_SELECTED_FIELDS_IPSEC_SPI = 0x4,
834};
b775516b 835
e281682b
SM		 836struct mlx5_ifc_rx_hash_field_select_bits {
837 u8 l3_prot_type[0x1];
838 u8 l4_prot_type[0x1];
839 u8 selected_fields[0x1e];
840};
b775516b 841
e281682b
SM		 842enum {
843 MLX5_WQ_WQ_TYPE_WQ_LINKED_LIST = 0x0,
844 MLX5_WQ_WQ_TYPE_WQ_CYCLIC = 0x1,
b775516b
EC		 845};
846
e281682b
SM		 847enum {
848 MLX5_WQ_END_PADDING_MODE_END_PAD_NONE = 0x0,
849 MLX5_WQ_END_PADDING_MODE_END_PAD_ALIGN = 0x1,
850};
851
852struct mlx5_ifc_wq_bits {
853 u8 wq_type[0x4];
854 u8 wq_signature[0x1];
855 u8 end_padding_mode[0x2];
856 u8 cd_slave[0x1];
b775516b
EC		 857 u8 reserved_0[0x18];
858
e281682b
SM		 859 u8 hds_skip_first_sge[0x1];
860 u8 log2_hds_buf_size[0x3];
861 u8 reserved_1[0x7];
862 u8 page_offset[0x5];
863 u8 lwm[0x10];
b775516b 864
e281682b
SM		 865 u8 reserved_2[0x8];
866 u8 pd[0x18];
867
868 u8 reserved_3[0x8];
869 u8 uar_page[0x18];
870
871 u8 dbr_addr[0x40];
872
873 u8 hw_counter[0x20];
874
875 u8 sw_counter[0x20];
876
877 u8 reserved_4[0xc];
878 u8 log_wq_stride[0x4];
879 u8 reserved_5[0x3];
880 u8 log_wq_pg_sz[0x5];
881 u8 reserved_6[0x3];
882 u8 log_wq_sz[0x5];
883
884 u8 reserved_7[0x4e0];
b775516b 885
e281682b 886 struct mlx5_ifc_cmd_pas_bits pas[0];
b775516b
EC		 887};
888
e281682b
SM		 889struct mlx5_ifc_rq_num_bits {
890 u8 reserved_0[0x8];
891 u8 rq_num[0x18];
892};
b775516b 893
e281682b
SM		 894struct mlx5_ifc_mac_address_layout_bits {
895 u8 reserved_0[0x10];
896 u8 mac_addr_47_32[0x10];
b775516b 897
e281682b
SM		 898 u8 mac_addr_31_0[0x20];
899};
900
901struct mlx5_ifc_cong_control_r_roce_ecn_np_bits {
902 u8 reserved_0[0xa0];
903
904 u8 min_time_between_cnps[0x20];
905
906 u8 reserved_1[0x12];
907 u8 cnp_dscp[0x6];
908 u8 reserved_2[0x5];
909 u8 cnp_802p_prio[0x3];
910
911 u8 reserved_3[0x720];
912};
913
914struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits {
915 u8 reserved_0[0x60];
916
917 u8 reserved_1[0x4];
918 u8 clamp_tgt_rate[0x1];
919 u8 reserved_2[0x3];
920 u8 clamp_tgt_rate_after_time_inc[0x1];
921 u8 reserved_3[0x17];
922
923 u8 reserved_4[0x20];
924
925 u8 rpg_time_reset[0x20];
926
927 u8 rpg_byte_reset[0x20];
928
929 u8 rpg_threshold[0x20];
930
931 u8 rpg_max_rate[0x20];
932
933 u8 rpg_ai_rate[0x20];
934
935 u8 rpg_hai_rate[0x20];
936
937 u8 rpg_gd[0x20];
938
939 u8 rpg_min_dec_fac[0x20];
940
941 u8 rpg_min_rate[0x20];
942
943 u8 reserved_5[0xe0];
944
945 u8 rate_to_set_on_first_cnp[0x20];
946
947 u8 dce_tcp_g[0x20];
948
949 u8 dce_tcp_rtt[0x20];
950
951 u8 rate_reduce_monitor_period[0x20];
952
953 u8 reserved_6[0x20];
954
955 u8 initial_alpha_value[0x20];
956
957 u8 reserved_7[0x4a0];
958};
959
960struct mlx5_ifc_cong_control_802_1qau_rp_bits {
961 u8 reserved_0[0x80];
962
963 u8 rppp_max_rps[0x20];
964
965 u8 rpg_time_reset[0x20];
966
967 u8 rpg_byte_reset[0x20];
968
969 u8 rpg_threshold[0x20];
970
971 u8 rpg_max_rate[0x20];
972
973 u8 rpg_ai_rate[0x20];
974
975 u8 rpg_hai_rate[0x20];
976
977 u8 rpg_gd[0x20];
978
979 u8 rpg_min_dec_fac[0x20];
980
981 u8 rpg_min_rate[0x20];
982
983 u8 reserved_1[0x640];
984};
985
986enum {
987 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_CQ_SIZE = 0x1,
988 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_PAGE_OFFSET = 0x2,
989 MLX5_RESIZE_FIELD_SELECT_RESIZE_FIELD_SELECT_LOG_PAGE_SIZE = 0x4,
990};
991
992struct mlx5_ifc_resize_field_select_bits {
993 u8 resize_field_select[0x20];
994};
995
996enum {
997 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_PERIOD = 0x1,
998 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_CQ_MAX_COUNT = 0x2,
999 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_OI = 0x4,
1000 MLX5_MODIFY_FIELD_SELECT_MODIFY_FIELD_SELECT_C_EQN = 0x8,
1001};
1002
1003struct mlx5_ifc_modify_field_select_bits {
1004 u8 modify_field_select[0x20];
1005};
1006
1007struct mlx5_ifc_field_select_r_roce_np_bits {
1008 u8 field_select_r_roce_np[0x20];
1009};
1010
1011struct mlx5_ifc_field_select_r_roce_rp_bits {
1012 u8 field_select_r_roce_rp[0x20];
1013};
1014
1015enum {
1016 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPPP_MAX_RPS = 0x4,
1017 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_TIME_RESET = 0x8,
1018 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_BYTE_RESET = 0x10,
1019 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_THRESHOLD = 0x20,
1020 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MAX_RATE = 0x40,
1021 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_AI_RATE = 0x80,
1022 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_HAI_RATE = 0x100,
1023 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_GD = 0x200,
1024 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_DEC_FAC = 0x400,
1025 MLX5_FIELD_SELECT_802_1QAU_RP_FIELD_SELECT_8021QAURP_RPG_MIN_RATE = 0x800,
1026};
1027
1028struct mlx5_ifc_field_select_802_1qau_rp_bits {
1029 u8 field_select_8021qaurp[0x20];
1030};
1031
1032struct mlx5_ifc_phys_layer_cntrs_bits {
1033 u8 time_since_last_clear_high[0x20];
1034
1035 u8 time_since_last_clear_low[0x20];
1036
1037 u8 symbol_errors_high[0x20];
1038
1039 u8 symbol_errors_low[0x20];
1040
1041 u8 sync_headers_errors_high[0x20];
1042
1043 u8 sync_headers_errors_low[0x20];
1044
1045 u8 edpl_bip_errors_lane0_high[0x20];
1046
1047 u8 edpl_bip_errors_lane0_low[0x20];
1048
1049 u8 edpl_bip_errors_lane1_high[0x20];
1050
1051 u8 edpl_bip_errors_lane1_low[0x20];
1052
1053 u8 edpl_bip_errors_lane2_high[0x20];
1054
1055 u8 edpl_bip_errors_lane2_low[0x20];
1056
1057 u8 edpl_bip_errors_lane3_high[0x20];
1058
1059 u8 edpl_bip_errors_lane3_low[0x20];
1060
1061 u8 fc_fec_corrected_blocks_lane0_high[0x20];
1062
1063 u8 fc_fec_corrected_blocks_lane0_low[0x20];
1064
1065 u8 fc_fec_corrected_blocks_lane1_high[0x20];
1066
1067 u8 fc_fec_corrected_blocks_lane1_low[0x20];
1068
1069 u8 fc_fec_corrected_blocks_lane2_high[0x20];
1070
1071 u8 fc_fec_corrected_blocks_lane2_low[0x20];
1072
1073 u8 fc_fec_corrected_blocks_lane3_high[0x20];
1074
1075 u8 fc_fec_corrected_blocks_lane3_low[0x20];
1076
1077 u8 fc_fec_uncorrectable_blocks_lane0_high[0x20];
1078
1079 u8 fc_fec_uncorrectable_blocks_lane0_low[0x20];
1080
1081 u8 fc_fec_uncorrectable_blocks_lane1_high[0x20];
1082
1083 u8 fc_fec_uncorrectable_blocks_lane1_low[0x20];
1084
1085 u8 fc_fec_uncorrectable_blocks_lane2_high[0x20];
1086
1087 u8 fc_fec_uncorrectable_blocks_lane2_low[0x20];
1088
1089 u8 fc_fec_uncorrectable_blocks_lane3_high[0x20];
1090
1091 u8 fc_fec_uncorrectable_blocks_lane3_low[0x20];
1092
1093 u8 rs_fec_corrected_blocks_high[0x20];
1094
1095 u8 rs_fec_corrected_blocks_low[0x20];
1096
1097 u8 rs_fec_uncorrectable_blocks_high[0x20];
1098
1099 u8 rs_fec_uncorrectable_blocks_low[0x20];
1100
1101 u8 rs_fec_no_errors_blocks_high[0x20];
1102
1103 u8 rs_fec_no_errors_blocks_low[0x20];
1104
1105 u8 rs_fec_single_error_blocks_high[0x20];
1106
1107 u8 rs_fec_single_error_blocks_low[0x20];
1108
1109 u8 rs_fec_corrected_symbols_total_high[0x20];
1110
1111 u8 rs_fec_corrected_symbols_total_low[0x20];
1112
1113 u8 rs_fec_corrected_symbols_lane0_high[0x20];
1114
1115 u8 rs_fec_corrected_symbols_lane0_low[0x20];
1116
1117 u8 rs_fec_corrected_symbols_lane1_high[0x20];
1118
1119 u8 rs_fec_corrected_symbols_lane1_low[0x20];
1120
1121 u8 rs_fec_corrected_symbols_lane2_high[0x20];
1122
1123 u8 rs_fec_corrected_symbols_lane2_low[0x20];
1124
1125 u8 rs_fec_corrected_symbols_lane3_high[0x20];
1126
1127 u8 rs_fec_corrected_symbols_lane3_low[0x20];
1128
1129 u8 link_down_events[0x20];
1130
1131 u8 successful_recovery_events[0x20];
1132
1133 u8 reserved_0[0x180];
1134};
1135
1136struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits {
1137 u8 transmit_queue_high[0x20];
1138
1139 u8 transmit_queue_low[0x20];
1140
1141 u8 reserved_0[0x780];
1142};
1143
1144struct mlx5_ifc_eth_per_prio_grp_data_layout_bits {
1145 u8 rx_octets_high[0x20];
1146
1147 u8 rx_octets_low[0x20];
1148
1149 u8 reserved_0[0xc0];
1150
1151 u8 rx_frames_high[0x20];
1152
1153 u8 rx_frames_low[0x20];
1154
1155 u8 tx_octets_high[0x20];
1156
1157 u8 tx_octets_low[0x20];
1158
1159 u8 reserved_1[0xc0];
1160
1161 u8 tx_frames_high[0x20];
1162
1163 u8 tx_frames_low[0x20];
1164
1165 u8 rx_pause_high[0x20];
1166
1167 u8 rx_pause_low[0x20];
1168
1169 u8 rx_pause_duration_high[0x20];
1170
1171 u8 rx_pause_duration_low[0x20];
1172
1173 u8 tx_pause_high[0x20];
1174
1175 u8 tx_pause_low[0x20];
1176
1177 u8 tx_pause_duration_high[0x20];
1178
1179 u8 tx_pause_duration_low[0x20];
1180
1181 u8 rx_pause_transition_high[0x20];
1182
1183 u8 rx_pause_transition_low[0x20];
1184
1185 u8 reserved_2[0x400];
1186};
1187
1188struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits {
1189 u8 port_transmit_wait_high[0x20];
1190
1191 u8 port_transmit_wait_low[0x20];
1192
1193 u8 reserved_0[0x780];
1194};
1195
1196struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits {
1197 u8 dot3stats_alignment_errors_high[0x20];
1198
1199 u8 dot3stats_alignment_errors_low[0x20];
1200
1201 u8 dot3stats_fcs_errors_high[0x20];
1202
1203 u8 dot3stats_fcs_errors_low[0x20];
1204
1205 u8 dot3stats_single_collision_frames_high[0x20];
1206
1207 u8 dot3stats_single_collision_frames_low[0x20];
1208
1209 u8 dot3stats_multiple_collision_frames_high[0x20];
1210
1211 u8 dot3stats_multiple_collision_frames_low[0x20];
1212
1213 u8 dot3stats_sqe_test_errors_high[0x20];
1214
1215 u8 dot3stats_sqe_test_errors_low[0x20];
1216
1217 u8 dot3stats_deferred_transmissions_high[0x20];
1218
1219 u8 dot3stats_deferred_transmissions_low[0x20];
1220
1221 u8 dot3stats_late_collisions_high[0x20];
1222
1223 u8 dot3stats_late_collisions_low[0x20];
1224
1225 u8 dot3stats_excessive_collisions_high[0x20];
1226
1227 u8 dot3stats_excessive_collisions_low[0x20];
1228
1229 u8 dot3stats_internal_mac_transmit_errors_high[0x20];
1230
1231 u8 dot3stats_internal_mac_transmit_errors_low[0x20];
1232
1233 u8 dot3stats_carrier_sense_errors_high[0x20];
1234
1235 u8 dot3stats_carrier_sense_errors_low[0x20];
1236
1237 u8 dot3stats_frame_too_longs_high[0x20];
1238
1239 u8 dot3stats_frame_too_longs_low[0x20];
1240
1241 u8 dot3stats_internal_mac_receive_errors_high[0x20];
1242
1243 u8 dot3stats_internal_mac_receive_errors_low[0x20];
1244
1245 u8 dot3stats_symbol_errors_high[0x20];
1246
1247 u8 dot3stats_symbol_errors_low[0x20];
1248
1249 u8 dot3control_in_unknown_opcodes_high[0x20];
1250
1251 u8 dot3control_in_unknown_opcodes_low[0x20];
1252
1253 u8 dot3in_pause_frames_high[0x20];
1254
1255 u8 dot3in_pause_frames_low[0x20];
1256
1257 u8 dot3out_pause_frames_high[0x20];
1258
1259 u8 dot3out_pause_frames_low[0x20];
1260
1261 u8 reserved_0[0x3c0];
1262};
1263
1264struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits {
1265 u8 ether_stats_drop_events_high[0x20];
1266
1267 u8 ether_stats_drop_events_low[0x20];
1268
1269 u8 ether_stats_octets_high[0x20];
1270
1271 u8 ether_stats_octets_low[0x20];
1272
1273 u8 ether_stats_pkts_high[0x20];
1274
1275 u8 ether_stats_pkts_low[0x20];
1276
1277 u8 ether_stats_broadcast_pkts_high[0x20];
1278
1279 u8 ether_stats_broadcast_pkts_low[0x20];
1280
1281 u8 ether_stats_multicast_pkts_high[0x20];
1282
1283 u8 ether_stats_multicast_pkts_low[0x20];
1284
1285 u8 ether_stats_crc_align_errors_high[0x20];
1286
1287 u8 ether_stats_crc_align_errors_low[0x20];
1288
1289 u8 ether_stats_undersize_pkts_high[0x20];
1290
1291 u8 ether_stats_undersize_pkts_low[0x20];
1292
1293 u8 ether_stats_oversize_pkts_high[0x20];
1294
1295 u8 ether_stats_oversize_pkts_low[0x20];
1296
1297 u8 ether_stats_fragments_high[0x20];
1298
1299 u8 ether_stats_fragments_low[0x20];
1300
1301 u8 ether_stats_jabbers_high[0x20];
1302
1303 u8 ether_stats_jabbers_low[0x20];
1304
1305 u8 ether_stats_collisions_high[0x20];
1306
1307 u8 ether_stats_collisions_low[0x20];
1308
1309 u8 ether_stats_pkts64octets_high[0x20];
1310
1311 u8 ether_stats_pkts64octets_low[0x20];
1312
1313 u8 ether_stats_pkts65to127octets_high[0x20];
1314
1315 u8 ether_stats_pkts65to127octets_low[0x20];
1316
1317 u8 ether_stats_pkts128to255octets_high[0x20];
1318
1319 u8 ether_stats_pkts128to255octets_low[0x20];
1320
1321 u8 ether_stats_pkts256to511octets_high[0x20];
1322
1323 u8 ether_stats_pkts256to511octets_low[0x20];
1324
1325 u8 ether_stats_pkts512to1023octets_high[0x20];
1326
1327 u8 ether_stats_pkts512to1023octets_low[0x20];
1328
1329 u8 ether_stats_pkts1024to1518octets_high[0x20];
1330
1331 u8 ether_stats_pkts1024to1518octets_low[0x20];
1332
1333 u8 ether_stats_pkts1519to2047octets_high[0x20];
1334
1335 u8 ether_stats_pkts1519to2047octets_low[0x20];
1336
1337 u8 ether_stats_pkts2048to4095octets_high[0x20];
1338
1339 u8 ether_stats_pkts2048to4095octets_low[0x20];
1340
1341 u8 ether_stats_pkts4096to8191octets_high[0x20];
1342
1343 u8 ether_stats_pkts4096to8191octets_low[0x20];
1344
1345 u8 ether_stats_pkts8192to10239octets_high[0x20];
1346
1347 u8 ether_stats_pkts8192to10239octets_low[0x20];
1348
1349 u8 reserved_0[0x280];
1350};
1351
1352struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits {
1353 u8 if_in_octets_high[0x20];
1354
1355 u8 if_in_octets_low[0x20];
1356
1357 u8 if_in_ucast_pkts_high[0x20];
1358
1359 u8 if_in_ucast_pkts_low[0x20];
1360
1361 u8 if_in_discards_high[0x20];
1362
1363 u8 if_in_discards_low[0x20];
1364
1365 u8 if_in_errors_high[0x20];
1366
1367 u8 if_in_errors_low[0x20];
1368
1369 u8 if_in_unknown_protos_high[0x20];
1370
1371 u8 if_in_unknown_protos_low[0x20];
1372
1373 u8 if_out_octets_high[0x20];
1374
1375 u8 if_out_octets_low[0x20];
1376
1377 u8 if_out_ucast_pkts_high[0x20];
1378
1379 u8 if_out_ucast_pkts_low[0x20];
1380
1381 u8 if_out_discards_high[0x20];
1382
1383 u8 if_out_discards_low[0x20];
1384
1385 u8 if_out_errors_high[0x20];
1386
1387 u8 if_out_errors_low[0x20];
1388
1389 u8 if_in_multicast_pkts_high[0x20];
1390
1391 u8 if_in_multicast_pkts_low[0x20];
1392
1393 u8 if_in_broadcast_pkts_high[0x20];
1394
1395 u8 if_in_broadcast_pkts_low[0x20];
1396
1397 u8 if_out_multicast_pkts_high[0x20];
1398
1399 u8 if_out_multicast_pkts_low[0x20];
1400
1401 u8 if_out_broadcast_pkts_high[0x20];
1402
1403 u8 if_out_broadcast_pkts_low[0x20];
1404
1405 u8 reserved_0[0x480];
1406};
1407
1408struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits {
1409 u8 a_frames_transmitted_ok_high[0x20];
1410
1411 u8 a_frames_transmitted_ok_low[0x20];
1412
1413 u8 a_frames_received_ok_high[0x20];
1414
1415 u8 a_frames_received_ok_low[0x20];
1416
1417 u8 a_frame_check_sequence_errors_high[0x20];
1418
1419 u8 a_frame_check_sequence_errors_low[0x20];
1420
1421 u8 a_alignment_errors_high[0x20];
1422
1423 u8 a_alignment_errors_low[0x20];
1424
1425 u8 a_octets_transmitted_ok_high[0x20];
1426
1427 u8 a_octets_transmitted_ok_low[0x20];
1428
1429 u8 a_octets_received_ok_high[0x20];
1430
1431 u8 a_octets_received_ok_low[0x20];
1432
1433 u8 a_multicast_frames_xmitted_ok_high[0x20];
1434
1435 u8 a_multicast_frames_xmitted_ok_low[0x20];
1436
1437 u8 a_broadcast_frames_xmitted_ok_high[0x20];
1438
1439 u8 a_broadcast_frames_xmitted_ok_low[0x20];
1440
1441 u8 a_multicast_frames_received_ok_high[0x20];
1442
1443 u8 a_multicast_frames_received_ok_low[0x20];
1444
1445 u8 a_broadcast_frames_received_ok_high[0x20];
1446
1447 u8 a_broadcast_frames_received_ok_low[0x20];
1448
1449 u8 a_in_range_length_errors_high[0x20];
1450
1451 u8 a_in_range_length_errors_low[0x20];
1452
1453 u8 a_out_of_range_length_field_high[0x20];
1454
1455 u8 a_out_of_range_length_field_low[0x20];
1456
1457 u8 a_frame_too_long_errors_high[0x20];
1458
1459 u8 a_frame_too_long_errors_low[0x20];
1460
1461 u8 a_symbol_error_during_carrier_high[0x20];
1462
1463 u8 a_symbol_error_during_carrier_low[0x20];
1464
1465 u8 a_mac_control_frames_transmitted_high[0x20];
1466
1467 u8 a_mac_control_frames_transmitted_low[0x20];
1468
1469 u8 a_mac_control_frames_received_high[0x20];
1470
1471 u8 a_mac_control_frames_received_low[0x20];
1472
1473 u8 a_unsupported_opcodes_received_high[0x20];
1474
1475 u8 a_unsupported_opcodes_received_low[0x20];
1476
1477 u8 a_pause_mac_ctrl_frames_received_high[0x20];
1478
1479 u8 a_pause_mac_ctrl_frames_received_low[0x20];
1480
1481 u8 a_pause_mac_ctrl_frames_transmitted_high[0x20];
1482
1483 u8 a_pause_mac_ctrl_frames_transmitted_low[0x20];
1484
1485 u8 reserved_0[0x300];
1486};
1487
1488struct mlx5_ifc_cmd_inter_comp_event_bits {
1489 u8 command_completion_vector[0x20];
1490
1491 u8 reserved_0[0xc0];
1492};
1493
1494struct mlx5_ifc_stall_vl_event_bits {
1495 u8 reserved_0[0x18];
1496 u8 port_num[0x1];
1497 u8 reserved_1[0x3];
1498 u8 vl[0x4];
1499
1500 u8 reserved_2[0xa0];
1501};
1502
1503struct mlx5_ifc_db_bf_congestion_event_bits {
1504 u8 event_subtype[0x8];
1505 u8 reserved_0[0x8];
1506 u8 congestion_level[0x8];
1507 u8 reserved_1[0x8];
1508
1509 u8 reserved_2[0xa0];
1510};
1511
1512struct mlx5_ifc_gpio_event_bits {
1513 u8 reserved_0[0x60];
1514
1515 u8 gpio_event_hi[0x20];
1516
1517 u8 gpio_event_lo[0x20];
1518
1519 u8 reserved_1[0x40];
1520};
1521
1522struct mlx5_ifc_port_state_change_event_bits {
1523 u8 reserved_0[0x40];
1524
1525 u8 port_num[0x4];
1526 u8 reserved_1[0x1c];
1527
1528 u8 reserved_2[0x80];
1529};
1530
1531struct mlx5_ifc_dropped_packet_logged_bits {
1532 u8 reserved_0[0xe0];
1533};
1534
1535enum {
1536 MLX5_CQ_ERROR_SYNDROME_CQ_OVERRUN = 0x1,
1537 MLX5_CQ_ERROR_SYNDROME_CQ_ACCESS_VIOLATION_ERROR = 0x2,
1538};
1539
1540struct mlx5_ifc_cq_error_bits {
1541 u8 reserved_0[0x8];
1542 u8 cqn[0x18];
1543
1544 u8 reserved_1[0x20];
1545
1546 u8 reserved_2[0x18];
1547 u8 syndrome[0x8];
1548
1549 u8 reserved_3[0x80];
1550};
1551
1552struct mlx5_ifc_rdma_page_fault_event_bits {
1553 u8 bytes_committed[0x20];
1554
1555 u8 r_key[0x20];
1556
1557 u8 reserved_0[0x10];
1558 u8 packet_len[0x10];
1559
1560 u8 rdma_op_len[0x20];
1561
1562 u8 rdma_va[0x40];
1563
1564 u8 reserved_1[0x5];
1565 u8 rdma[0x1];
1566 u8 write[0x1];
1567 u8 requestor[0x1];
1568 u8 qp_number[0x18];
1569};
1570
1571struct mlx5_ifc_wqe_associated_page_fault_event_bits {
1572 u8 bytes_committed[0x20];
1573
1574 u8 reserved_0[0x10];
1575 u8 wqe_index[0x10];
1576
1577 u8 reserved_1[0x10];
1578 u8 len[0x10];
1579
1580 u8 reserved_2[0x60];
1581
1582 u8 reserved_3[0x5];
1583 u8 rdma[0x1];
1584 u8 write_read[0x1];
1585 u8 requestor[0x1];
1586 u8 qpn[0x18];
1587};
1588
1589struct mlx5_ifc_qp_events_bits {
1590 u8 reserved_0[0xa0];
1591
1592 u8 type[0x8];
1593 u8 reserved_1[0x18];
1594
1595 u8 reserved_2[0x8];
1596 u8 qpn_rqn_sqn[0x18];
1597};
1598
1599struct mlx5_ifc_dct_events_bits {
1600 u8 reserved_0[0xc0];
1601
1602 u8 reserved_1[0x8];
1603 u8 dct_number[0x18];
1604};
1605
1606struct mlx5_ifc_comp_event_bits {
1607 u8 reserved_0[0xc0];
1608
1609 u8 reserved_1[0x8];
1610 u8 cq_number[0x18];
1611};
1612
1613enum {
1614 MLX5_QPC_STATE_RST = 0x0,
1615 MLX5_QPC_STATE_INIT = 0x1,
1616 MLX5_QPC_STATE_RTR = 0x2,
1617 MLX5_QPC_STATE_RTS = 0x3,
1618 MLX5_QPC_STATE_SQER = 0x4,
1619 MLX5_QPC_STATE_ERR = 0x6,
1620 MLX5_QPC_STATE_SQD = 0x7,
1621 MLX5_QPC_STATE_SUSPENDED = 0x9,
1622};
1623
1624enum {
1625 MLX5_QPC_ST_RC = 0x0,
1626 MLX5_QPC_ST_UC = 0x1,
1627 MLX5_QPC_ST_UD = 0x2,
1628 MLX5_QPC_ST_XRC = 0x3,
1629 MLX5_QPC_ST_DCI = 0x5,
1630 MLX5_QPC_ST_QP0 = 0x7,
1631 MLX5_QPC_ST_QP1 = 0x8,
1632 MLX5_QPC_ST_RAW_DATAGRAM = 0x9,
1633 MLX5_QPC_ST_REG_UMR = 0xc,
1634};
1635
1636enum {
1637 MLX5_QPC_PM_STATE_ARMED = 0x0,
1638 MLX5_QPC_PM_STATE_REARM = 0x1,
1639 MLX5_QPC_PM_STATE_RESERVED = 0x2,
1640 MLX5_QPC_PM_STATE_MIGRATED = 0x3,
1641};
1642
1643enum {
1644 MLX5_QPC_END_PADDING_MODE_SCATTER_AS_IS = 0x0,
1645 MLX5_QPC_END_PADDING_MODE_PAD_TO_CACHE_LINE_ALIGNMENT = 0x1,
1646};
1647
1648enum {
1649 MLX5_QPC_MTU_256_BYTES = 0x1,
1650 MLX5_QPC_MTU_512_BYTES = 0x2,
1651 MLX5_QPC_MTU_1K_BYTES = 0x3,
1652 MLX5_QPC_MTU_2K_BYTES = 0x4,
1653 MLX5_QPC_MTU_4K_BYTES = 0x5,
1654 MLX5_QPC_MTU_RAW_ETHERNET_QP = 0x7,
1655};
1656
1657enum {
1658 MLX5_QPC_ATOMIC_MODE_IB_SPEC = 0x1,
1659 MLX5_QPC_ATOMIC_MODE_ONLY_8B = 0x2,
1660 MLX5_QPC_ATOMIC_MODE_UP_TO_8B = 0x3,
1661 MLX5_QPC_ATOMIC_MODE_UP_TO_16B = 0x4,
1662 MLX5_QPC_ATOMIC_MODE_UP_TO_32B = 0x5,
1663 MLX5_QPC_ATOMIC_MODE_UP_TO_64B = 0x6,
1664 MLX5_QPC_ATOMIC_MODE_UP_TO_128B = 0x7,
1665 MLX5_QPC_ATOMIC_MODE_UP_TO_256B = 0x8,
1666};
1667
1668enum {
1669 MLX5_QPC_CS_REQ_DISABLE = 0x0,
1670 MLX5_QPC_CS_REQ_UP_TO_32B = 0x11,
1671 MLX5_QPC_CS_REQ_UP_TO_64B = 0x22,
1672};
1673
1674enum {
1675 MLX5_QPC_CS_RES_DISABLE = 0x0,
1676 MLX5_QPC_CS_RES_UP_TO_32B = 0x1,
1677 MLX5_QPC_CS_RES_UP_TO_64B = 0x2,
1678};
1679
1680struct mlx5_ifc_qpc_bits {
1681 u8 state[0x4];
1682 u8 reserved_0[0x4];
1683 u8 st[0x8];
1684 u8 reserved_1[0x3];
1685 u8 pm_state[0x2];
1686 u8 reserved_2[0x7];
1687 u8 end_padding_mode[0x2];
1688 u8 reserved_3[0x2];
1689
1690 u8 wq_signature[0x1];
1691 u8 block_lb_mc[0x1];
1692 u8 atomic_like_write_en[0x1];
1693 u8 latency_sensitive[0x1];
1694 u8 reserved_4[0x1];
1695 u8 drain_sigerr[0x1];
1696 u8 reserved_5[0x2];
1697 u8 pd[0x18];
1698
1699 u8 mtu[0x3];
1700 u8 log_msg_max[0x5];
1701 u8 reserved_6[0x1];
1702 u8 log_rq_size[0x4];
1703 u8 log_rq_stride[0x3];
1704 u8 no_sq[0x1];
1705 u8 log_sq_size[0x4];
1706 u8 reserved_7[0x6];
1707 u8 rlky[0x1];
1708 u8 reserved_8[0x4];
1709
1710 u8 counter_set_id[0x8];
1711 u8 uar_page[0x18];
1712
1713 u8 reserved_9[0x8];
1714 u8 user_index[0x18];
1715
1716 u8 reserved_10[0x3];
1717 u8 log_page_size[0x5];
1718 u8 remote_qpn[0x18];
1719
1720 struct mlx5_ifc_ads_bits primary_address_path;
1721
1722 struct mlx5_ifc_ads_bits secondary_address_path;
1723
1724 u8 log_ack_req_freq[0x4];
1725 u8 reserved_11[0x4];
1726 u8 log_sra_max[0x3];
1727 u8 reserved_12[0x2];
1728 u8 retry_count[0x3];
1729 u8 rnr_retry[0x3];
1730 u8 reserved_13[0x1];
1731 u8 fre[0x1];
1732 u8 cur_rnr_retry[0x3];
1733 u8 cur_retry_count[0x3];
1734 u8 reserved_14[0x5];
1735
1736 u8 reserved_15[0x20];
1737
1738 u8 reserved_16[0x8];
1739 u8 next_send_psn[0x18];
1740
1741 u8 reserved_17[0x8];
1742 u8 cqn_snd[0x18];
1743
1744 u8 reserved_18[0x40];
1745
1746 u8 reserved_19[0x8];
1747 u8 last_acked_psn[0x18];
1748
1749 u8 reserved_20[0x8];
1750 u8 ssn[0x18];
1751
1752 u8 reserved_21[0x8];
1753 u8 log_rra_max[0x3];
1754 u8 reserved_22[0x1];
1755 u8 atomic_mode[0x4];
1756 u8 rre[0x1];
1757 u8 rwe[0x1];
1758 u8 rae[0x1];
1759 u8 reserved_23[0x1];
1760 u8 page_offset[0x6];
1761 u8 reserved_24[0x3];
1762 u8 cd_slave_receive[0x1];
1763 u8 cd_slave_send[0x1];
1764 u8 cd_master[0x1];
1765
1766 u8 reserved_25[0x3];
1767 u8 min_rnr_nak[0x5];
1768 u8 next_rcv_psn[0x18];
1769
1770 u8 reserved_26[0x8];
1771 u8 xrcd[0x18];
1772
1773 u8 reserved_27[0x8];
1774 u8 cqn_rcv[0x18];
1775
1776 u8 dbr_addr[0x40];
1777
1778 u8 q_key[0x20];
1779
1780 u8 reserved_28[0x5];
1781 u8 rq_type[0x3];
1782 u8 srqn_rmpn[0x18];
1783
1784 u8 reserved_29[0x8];
1785 u8 rmsn[0x18];
1786
1787 u8 hw_sq_wqebb_counter[0x10];
1788 u8 sw_sq_wqebb_counter[0x10];
1789
1790 u8 hw_rq_counter[0x20];
1791
1792 u8 sw_rq_counter[0x20];
1793
1794 u8 reserved_30[0x20];
1795
1796 u8 reserved_31[0xf];
1797 u8 cgs[0x1];
1798 u8 cs_req[0x8];
1799 u8 cs_res[0x8];
1800
1801 u8 dc_access_key[0x40];
1802
1803 u8 reserved_32[0xc0];
1804};
1805
1806struct mlx5_ifc_roce_addr_layout_bits {
1807 u8 source_l3_address[16][0x8];
1808
1809 u8 reserved_0[0x3];
1810 u8 vlan_valid[0x1];
1811 u8 vlan_id[0xc];
1812 u8 source_mac_47_32[0x10];
1813
1814 u8 source_mac_31_0[0x20];
1815
1816 u8 reserved_1[0x14];
1817 u8 roce_l3_type[0x4];
1818 u8 roce_version[0x8];
1819
1820 u8 reserved_2[0x20];
1821};
1822
1823union mlx5_ifc_hca_cap_union_bits {
1824 struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;
1825 struct mlx5_ifc_odp_cap_bits odp_cap;
1826 struct mlx5_ifc_atomic_caps_bits atomic_caps;
1827 struct mlx5_ifc_roce_cap_bits roce_cap;
1828 struct mlx5_ifc_per_protocol_networking_offload_caps_bits per_protocol_networking_offload_caps;
1829 struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;
1830 u8 reserved_0[0x8000];
1831};
1832
1833enum {
1834 MLX5_FLOW_CONTEXT_ACTION_ALLOW = 0x1,
1835 MLX5_FLOW_CONTEXT_ACTION_DROP = 0x2,
1836 MLX5_FLOW_CONTEXT_ACTION_FWD_DEST = 0x4,
1837};
1838
1839struct mlx5_ifc_flow_context_bits {
1840 u8 reserved_0[0x20];
1841
1842 u8 group_id[0x20];
1843
1844 u8 reserved_1[0x8];
1845 u8 flow_tag[0x18];
1846
1847 u8 reserved_2[0x10];
1848 u8 action[0x10];
1849
1850 u8 reserved_3[0x8];
1851 u8 destination_list_size[0x18];
1852
1853 u8 reserved_4[0x160];
1854
1855 struct mlx5_ifc_fte_match_param_bits match_value;
1856
1857 u8 reserved_5[0x600];
1858
1859 struct mlx5_ifc_dest_format_struct_bits destination[0];
1860};
1861
1862enum {
1863 MLX5_XRC_SRQC_STATE_GOOD = 0x0,
1864 MLX5_XRC_SRQC_STATE_ERROR = 0x1,
1865};
1866
1867struct mlx5_ifc_xrc_srqc_bits {
1868 u8 state[0x4];
1869 u8 log_xrc_srq_size[0x4];
1870 u8 reserved_0[0x18];
1871
1872 u8 wq_signature[0x1];
1873 u8 cont_srq[0x1];
1874 u8 reserved_1[0x1];
1875 u8 rlky[0x1];
1876 u8 basic_cyclic_rcv_wqe[0x1];
1877 u8 log_rq_stride[0x3];
1878 u8 xrcd[0x18];
1879
1880 u8 page_offset[0x6];
1881 u8 reserved_2[0x2];
1882 u8 cqn[0x18];
1883
1884 u8 reserved_3[0x20];
1885
1886 u8 user_index_equal_xrc_srqn[0x1];
1887 u8 reserved_4[0x1];
1888 u8 log_page_size[0x6];
1889 u8 user_index[0x18];
1890
1891 u8 reserved_5[0x20];
1892
1893 u8 reserved_6[0x8];
1894 u8 pd[0x18];
1895
1896 u8 lwm[0x10];
1897 u8 wqe_cnt[0x10];
1898
1899 u8 reserved_7[0x40];
1900
1901 u8 db_record_addr_h[0x20];
1902
1903 u8 db_record_addr_l[0x1e];
1904 u8 reserved_8[0x2];
1905
1906 u8 reserved_9[0x80];
1907};
1908
1909struct mlx5_ifc_traffic_counter_bits {
1910 u8 packets[0x40];
1911
1912 u8 octets[0x40];
1913};
1914
1915struct mlx5_ifc_tisc_bits {
1916 u8 reserved_0[0xc];
1917 u8 prio[0x4];
1918 u8 reserved_1[0x10];
1919
1920 u8 reserved_2[0x100];
1921
1922 u8 reserved_3[0x8];
1923 u8 transport_domain[0x18];
1924
1925 u8 reserved_4[0x3c0];
1926};
1927
1928enum {
1929 MLX5_TIRC_DISP_TYPE_DIRECT = 0x0,
1930 MLX5_TIRC_DISP_TYPE_INDIRECT = 0x1,
1931};
1932
1933enum {
1934 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO = 0x1,
1935 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO = 0x2,
1936};
1937
1938enum {
1939 MLX5_TIRC_RX_HASH_FN_HASH_NONE = 0x0,
1940 MLX5_TIRC_RX_HASH_FN_HASH_INVERTED_XOR8 = 0x1,
1941 MLX5_TIRC_RX_HASH_FN_HASH_TOEPLITZ = 0x2,
1942};
1943
1944enum {
1945 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_ = 0x1,
1946 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_MULTICAST_ = 0x2,
1947};
1948
1949struct mlx5_ifc_tirc_bits {
1950 u8 reserved_0[0x20];
1951
1952 u8 disp_type[0x4];
1953 u8 reserved_1[0x1c];
1954
1955 u8 reserved_2[0x40];
1956
1957 u8 reserved_3[0x4];
1958 u8 lro_timeout_period_usecs[0x10];
1959 u8 lro_enable_mask[0x4];
1960 u8 lro_max_ip_payload_size[0x8];
1961
1962 u8 reserved_4[0x40];
1963
1964 u8 reserved_5[0x8];
1965 u8 inline_rqn[0x18];
1966
1967 u8 rx_hash_symmetric[0x1];
1968 u8 reserved_6[0x1];
1969 u8 tunneled_offload_en[0x1];
1970 u8 reserved_7[0x5];
1971 u8 indirect_table[0x18];
1972
1973 u8 rx_hash_fn[0x4];
1974 u8 reserved_8[0x2];
1975 u8 self_lb_block[0x2];
1976 u8 transport_domain[0x18];
1977
1978 u8 rx_hash_toeplitz_key[10][0x20];
1979
1980 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_outer;
1981
1982 struct mlx5_ifc_rx_hash_field_select_bits rx_hash_field_selector_inner;
1983
1984 u8 reserved_9[0x4c0];
1985};
1986
1987enum {
1988 MLX5_SRQC_STATE_GOOD = 0x0,
1989 MLX5_SRQC_STATE_ERROR = 0x1,
1990};
1991
1992struct mlx5_ifc_srqc_bits {
1993 u8 state[0x4];
1994 u8 log_srq_size[0x4];
1995 u8 reserved_0[0x18];
1996
1997 u8 wq_signature[0x1];
1998 u8 cont_srq[0x1];
1999 u8 reserved_1[0x1];
2000 u8 rlky[0x1];
2001 u8 reserved_2[0x1];
2002 u8 log_rq_stride[0x3];
2003 u8 xrcd[0x18];
2004
2005 u8 page_offset[0x6];
2006 u8 reserved_3[0x2];
2007 u8 cqn[0x18];
2008
2009 u8 reserved_4[0x20];
2010
2011 u8 reserved_5[0x2];
2012 u8 log_page_size[0x6];
2013 u8 reserved_6[0x18];
2014
2015 u8 reserved_7[0x20];
2016
2017 u8 reserved_8[0x8];
2018 u8 pd[0x18];
2019
2020 u8 lwm[0x10];
2021 u8 wqe_cnt[0x10];
2022
2023 u8 reserved_9[0x40];
2024
01949d01 2025 u8 dbr_addr[0x40];
e281682b 2026
01949d01 2027 u8 reserved_10[0x80];
e281682b
SM		 2028};
2029
2030enum {
2031 MLX5_SQC_STATE_RST = 0x0,
2032 MLX5_SQC_STATE_RDY = 0x1,
2033 MLX5_SQC_STATE_ERR = 0x3,
2034};
2035
2036struct mlx5_ifc_sqc_bits {
2037 u8 rlky[0x1];
2038 u8 cd_master[0x1];
2039 u8 fre[0x1];
2040 u8 flush_in_error_en[0x1];
2041 u8 reserved_0[0x4];
2042 u8 state[0x4];
2043 u8 reserved_1[0x14];
2044
2045 u8 reserved_2[0x8];
2046 u8 user_index[0x18];
2047
2048 u8 reserved_3[0x8];
2049 u8 cqn[0x18];
2050
2051 u8 reserved_4[0xa0];
2052
2053 u8 tis_lst_sz[0x10];
2054 u8 reserved_5[0x10];
2055
2056 u8 reserved_6[0x40];
2057
2058 u8 reserved_7[0x8];
2059 u8 tis_num_0[0x18];
2060
2061 struct mlx5_ifc_wq_bits wq;
2062};
2063
2064struct mlx5_ifc_rqtc_bits {
2065 u8 reserved_0[0xa0];
2066
2067 u8 reserved_1[0x10];
2068 u8 rqt_max_size[0x10];
2069
2070 u8 reserved_2[0x10];
2071 u8 rqt_actual_size[0x10];
2072
2073 u8 reserved_3[0x6a0];
2074
2075 struct mlx5_ifc_rq_num_bits rq_num[0];
2076};
2077
2078enum {
2079 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE = 0x0,
2080 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_RMP = 0x1,
2081};
2082
2083enum {
2084 MLX5_RQC_STATE_RST = 0x0,
2085 MLX5_RQC_STATE_RDY = 0x1,
2086 MLX5_RQC_STATE_ERR = 0x3,
2087};
2088
2089struct mlx5_ifc_rqc_bits {
2090 u8 rlky[0x1];
2091 u8 reserved_0[0x2];
2092 u8 vsd[0x1];
2093 u8 mem_rq_type[0x4];
2094 u8 state[0x4];
2095 u8 reserved_1[0x1];
2096 u8 flush_in_error_en[0x1];
2097 u8 reserved_2[0x12];
2098
2099 u8 reserved_3[0x8];
2100 u8 user_index[0x18];
2101
2102 u8 reserved_4[0x8];
2103 u8 cqn[0x18];
2104
2105 u8 counter_set_id[0x8];
2106 u8 reserved_5[0x18];
2107
2108 u8 reserved_6[0x8];
2109 u8 rmpn[0x18];
2110
2111 u8 reserved_7[0xe0];
2112
2113 struct mlx5_ifc_wq_bits wq;
2114};
2115
2116enum {
2117 MLX5_RMPC_STATE_RDY = 0x1,
2118 MLX5_RMPC_STATE_ERR = 0x3,
2119};
2120
2121struct mlx5_ifc_rmpc_bits {
2122 u8 reserved_0[0x8];
2123 u8 state[0x4];
2124 u8 reserved_1[0x14];
2125
2126 u8 basic_cyclic_rcv_wqe[0x1];
2127 u8 reserved_2[0x1f];
2128
2129 u8 reserved_3[0x140];
2130
2131 struct mlx5_ifc_wq_bits wq;
2132};
2133
2134enum {
2135 MLX5_NIC_VPORT_CONTEXT_ALLOWED_LIST_TYPE_CURRENT_UC_MAC_ADDRESS = 0x0,
2136};
2137
2138struct mlx5_ifc_nic_vport_context_bits {
2139 u8 reserved_0[0x1f];
2140 u8 roce_en[0x1];
2141
2142 u8 reserved_1[0x760];
2143
2144 u8 reserved_2[0x5];
2145 u8 allowed_list_type[0x3];
2146 u8 reserved_3[0xc];
2147 u8 allowed_list_size[0xc];
2148
2149 struct mlx5_ifc_mac_address_layout_bits permanent_address;
2150
2151 u8 reserved_4[0x20];
2152
2153 u8 current_uc_mac_address[0][0x40];
2154};
2155
2156enum {
2157 MLX5_MKC_ACCESS_MODE_PA = 0x0,
2158 MLX5_MKC_ACCESS_MODE_MTT = 0x1,
2159 MLX5_MKC_ACCESS_MODE_KLMS = 0x2,
2160};
2161
2162struct mlx5_ifc_mkc_bits {
2163 u8 reserved_0[0x1];
2164 u8 free[0x1];
2165 u8 reserved_1[0xd];
2166 u8 small_fence_on_rdma_read_response[0x1];
2167 u8 umr_en[0x1];
2168 u8 a[0x1];
2169 u8 rw[0x1];
2170 u8 rr[0x1];
2171 u8 lw[0x1];
2172 u8 lr[0x1];
2173 u8 access_mode[0x2];
2174 u8 reserved_2[0x8];
2175
2176 u8 qpn[0x18];
2177 u8 mkey_7_0[0x8];
2178
2179 u8 reserved_3[0x20];
2180
2181 u8 length64[0x1];
2182 u8 bsf_en[0x1];
2183 u8 sync_umr[0x1];
2184 u8 reserved_4[0x2];
2185 u8 expected_sigerr_count[0x1];
2186 u8 reserved_5[0x1];
2187 u8 en_rinval[0x1];
2188 u8 pd[0x18];
2189
2190 u8 start_addr[0x40];
2191
2192 u8 len[0x40];
2193
2194 u8 bsf_octword_size[0x20];
2195
2196 u8 reserved_6[0x80];
2197
2198 u8 translations_octword_size[0x20];
2199
2200 u8 reserved_7[0x1b];
2201 u8 log_page_size[0x5];
2202
2203 u8 reserved_8[0x20];
2204};
2205
2206struct mlx5_ifc_pkey_bits {
2207 u8 reserved_0[0x10];
2208 u8 pkey[0x10];
2209};
2210
2211struct mlx5_ifc_array128_auto_bits {
2212 u8 array128_auto[16][0x8];
2213};
2214
2215struct mlx5_ifc_hca_vport_context_bits {
2216 u8 field_select[0x20];
2217
2218 u8 reserved_0[0xe0];
2219
2220 u8 sm_virt_aware[0x1];
2221 u8 has_smi[0x1];
2222 u8 has_raw[0x1];
2223 u8 grh_required[0x1];
707c4602
MD		 2224 u8 reserved_1[0xc];
2225 u8 port_physical_state[0x4];
2226 u8 vport_state_policy[0x4];
2227 u8 port_state[0x4];
e281682b
SM		 2228 u8 vport_state[0x4];
2229
707c4602
MD		 2230 u8 reserved_2[0x20];
2231
2232 u8 system_image_guid[0x40];
e281682b
SM		 2233
2234 u8 port_guid[0x40];
2235
2236 u8 node_guid[0x40];
2237
2238 u8 cap_mask1[0x20];
2239
2240 u8 cap_mask1_field_select[0x20];
2241
2242 u8 cap_mask2[0x20];
2243
2244 u8 cap_mask2_field_select[0x20];
2245
2246 u8 reserved_3[0x80];
2247
2248 u8 lid[0x10];
2249 u8 reserved_4[0x4];
2250 u8 init_type_reply[0x4];
2251 u8 lmc[0x3];
2252 u8 subnet_timeout[0x5];
2253
2254 u8 sm_lid[0x10];
2255 u8 sm_sl[0x4];
2256 u8 reserved_5[0xc];
2257
2258 u8 qkey_violation_counter[0x10];
2259 u8 pkey_violation_counter[0x10];
2260
2261 u8 reserved_6[0xca0];
2262};
2263
2264enum {
2265 MLX5_EQC_STATUS_OK = 0x0,
2266 MLX5_EQC_STATUS_EQ_WRITE_FAILURE = 0xa,
2267};
2268
2269enum {
2270 MLX5_EQC_ST_ARMED = 0x9,
2271 MLX5_EQC_ST_FIRED = 0xa,
2272};
2273
2274struct mlx5_ifc_eqc_bits {
2275 u8 status[0x4];
2276 u8 reserved_0[0x9];
2277 u8 ec[0x1];
2278 u8 oi[0x1];
2279 u8 reserved_1[0x5];
2280 u8 st[0x4];
2281 u8 reserved_2[0x8];
2282
2283 u8 reserved_3[0x20];
2284
2285 u8 reserved_4[0x14];
2286 u8 page_offset[0x6];
2287 u8 reserved_5[0x6];
2288
2289 u8 reserved_6[0x3];
2290 u8 log_eq_size[0x5];
2291 u8 uar_page[0x18];
2292
2293 u8 reserved_7[0x20];
2294
2295 u8 reserved_8[0x18];
2296 u8 intr[0x8];
2297
2298 u8 reserved_9[0x3];
2299 u8 log_page_size[0x5];
2300 u8 reserved_10[0x18];
2301
2302 u8 reserved_11[0x60];
2303
2304 u8 reserved_12[0x8];
2305 u8 consumer_counter[0x18];
2306
2307 u8 reserved_13[0x8];
2308 u8 producer_counter[0x18];
2309
2310 u8 reserved_14[0x80];
2311};
2312
2313enum {
2314 MLX5_DCTC_STATE_ACTIVE = 0x0,
2315 MLX5_DCTC_STATE_DRAINING = 0x1,
2316 MLX5_DCTC_STATE_DRAINED = 0x2,
2317};
2318
2319enum {
2320 MLX5_DCTC_CS_RES_DISABLE = 0x0,
2321 MLX5_DCTC_CS_RES_NA = 0x1,
2322 MLX5_DCTC_CS_RES_UP_TO_64B = 0x2,
2323};
2324
2325enum {
2326 MLX5_DCTC_MTU_256_BYTES = 0x1,
2327 MLX5_DCTC_MTU_512_BYTES = 0x2,
2328 MLX5_DCTC_MTU_1K_BYTES = 0x3,
2329 MLX5_DCTC_MTU_2K_BYTES = 0x4,
2330 MLX5_DCTC_MTU_4K_BYTES = 0x5,
2331};
2332
2333struct mlx5_ifc_dctc_bits {
2334 u8 reserved_0[0x4];
2335 u8 state[0x4];
2336 u8 reserved_1[0x18];
2337
2338 u8 reserved_2[0x8];
2339 u8 user_index[0x18];
2340
2341 u8 reserved_3[0x8];
2342 u8 cqn[0x18];
2343
2344 u8 counter_set_id[0x8];
2345 u8 atomic_mode[0x4];
2346 u8 rre[0x1];
2347 u8 rwe[0x1];
2348 u8 rae[0x1];
2349 u8 atomic_like_write_en[0x1];
2350 u8 latency_sensitive[0x1];
2351 u8 rlky[0x1];
2352 u8 free_ar[0x1];
2353 u8 reserved_4[0xd];
2354
2355 u8 reserved_5[0x8];
2356 u8 cs_res[0x8];
2357 u8 reserved_6[0x3];
2358 u8 min_rnr_nak[0x5];
2359 u8 reserved_7[0x8];
2360
2361 u8 reserved_8[0x8];
2362 u8 srqn[0x18];
2363
2364 u8 reserved_9[0x8];
2365 u8 pd[0x18];
2366
2367 u8 tclass[0x8];
2368 u8 reserved_10[0x4];
2369 u8 flow_label[0x14];
2370
2371 u8 dc_access_key[0x40];
2372
2373 u8 reserved_11[0x5];
2374 u8 mtu[0x3];
2375 u8 port[0x8];
2376 u8 pkey_index[0x10];
2377
2378 u8 reserved_12[0x8];
2379 u8 my_addr_index[0x8];
2380 u8 reserved_13[0x8];
2381 u8 hop_limit[0x8];
2382
2383 u8 dc_access_key_violation_count[0x20];
2384
2385 u8 reserved_14[0x14];
2386 u8 dei_cfi[0x1];
2387 u8 eth_prio[0x3];
2388 u8 ecn[0x2];
2389 u8 dscp[0x6];
2390
2391 u8 reserved_15[0x40];
2392};
2393
2394enum {
2395 MLX5_CQC_STATUS_OK = 0x0,
2396 MLX5_CQC_STATUS_CQ_OVERFLOW = 0x9,
2397 MLX5_CQC_STATUS_CQ_WRITE_FAIL = 0xa,
2398};
2399
2400enum {
2401 MLX5_CQC_CQE_SZ_64_BYTES = 0x0,
2402 MLX5_CQC_CQE_SZ_128_BYTES = 0x1,
2403};
2404
2405enum {
2406 MLX5_CQC_ST_SOLICITED_NOTIFICATION_REQUEST_ARMED = 0x6,
2407 MLX5_CQC_ST_NOTIFICATION_REQUEST_ARMED = 0x9,
2408 MLX5_CQC_ST_FIRED = 0xa,
2409};
2410
2411struct mlx5_ifc_cqc_bits {
2412 u8 status[0x4];
2413 u8 reserved_0[0x4];
2414 u8 cqe_sz[0x3];
2415 u8 cc[0x1];
2416 u8 reserved_1[0x1];
2417 u8 scqe_break_moderation_en[0x1];
2418 u8 oi[0x1];
2419 u8 reserved_2[0x2];
2420 u8 cqe_zip_en[0x1];
2421 u8 mini_cqe_res_format[0x2];
2422 u8 st[0x4];
2423 u8 reserved_3[0x8];
2424
2425 u8 reserved_4[0x20];
2426
2427 u8 reserved_5[0x14];
2428 u8 page_offset[0x6];
2429 u8 reserved_6[0x6];
2430
2431 u8 reserved_7[0x3];
2432 u8 log_cq_size[0x5];
2433 u8 uar_page[0x18];
2434
2435 u8 reserved_8[0x4];
2436 u8 cq_period[0xc];
2437 u8 cq_max_count[0x10];
2438
2439 u8 reserved_9[0x18];
2440 u8 c_eqn[0x8];
2441
2442 u8 reserved_10[0x3];
2443 u8 log_page_size[0x5];
2444 u8 reserved_11[0x18];
2445
2446 u8 reserved_12[0x20];
2447
2448 u8 reserved_13[0x8];
2449 u8 last_notified_index[0x18];
2450
2451 u8 reserved_14[0x8];
2452 u8 last_solicit_index[0x18];
2453
2454 u8 reserved_15[0x8];
2455 u8 consumer_counter[0x18];
2456
2457 u8 reserved_16[0x8];
2458 u8 producer_counter[0x18];
2459
2460 u8 reserved_17[0x40];
2461
2462 u8 dbr_addr[0x40];
2463};
2464
2465union mlx5_ifc_cong_control_roce_ecn_auto_bits {
2466 struct mlx5_ifc_cong_control_802_1qau_rp_bits cong_control_802_1qau_rp;
2467 struct mlx5_ifc_cong_control_r_roce_ecn_rp_bits cong_control_r_roce_ecn_rp;
2468 struct mlx5_ifc_cong_control_r_roce_ecn_np_bits cong_control_r_roce_ecn_np;
2469 u8 reserved_0[0x800];
2470};
2471
2472struct mlx5_ifc_query_adapter_param_block_bits {
211e6c80 2473 u8 reserved_0[0xc0];
e281682b 2474
211e6c80
MD		 2475 u8 reserved_1[0x8];
2476 u8 ieee_vendor_id[0x18];
2477
2478 u8 reserved_2[0x10];
e281682b
SM		 2479 u8 vsd_vendor_id[0x10];
2480
2481 u8 vsd[208][0x8];
2482
2483 u8 vsd_contd_psid[16][0x8];
2484};
2485
2486union mlx5_ifc_modify_field_select_resize_field_select_auto_bits {
2487 struct mlx5_ifc_modify_field_select_bits modify_field_select;
2488 struct mlx5_ifc_resize_field_select_bits resize_field_select;
2489 u8 reserved_0[0x20];
2490};
2491
2492union mlx5_ifc_field_select_802_1_r_roce_auto_bits {
2493 struct mlx5_ifc_field_select_802_1qau_rp_bits field_select_802_1qau_rp;
2494 struct mlx5_ifc_field_select_r_roce_rp_bits field_select_r_roce_rp;
2495 struct mlx5_ifc_field_select_r_roce_np_bits field_select_r_roce_np;
2496 u8 reserved_0[0x20];
2497};
2498
2499union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits {
2500 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
2501 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
2502 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
2503 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
2504 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
2505 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
2506 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
2507 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
2508 u8 reserved_0[0x7c0];
2509};
2510
2511union mlx5_ifc_event_auto_bits {
2512 struct mlx5_ifc_comp_event_bits comp_event;
2513 struct mlx5_ifc_dct_events_bits dct_events;
2514 struct mlx5_ifc_qp_events_bits qp_events;
2515 struct mlx5_ifc_wqe_associated_page_fault_event_bits wqe_associated_page_fault_event;
2516 struct mlx5_ifc_rdma_page_fault_event_bits rdma_page_fault_event;
2517 struct mlx5_ifc_cq_error_bits cq_error;
2518 struct mlx5_ifc_dropped_packet_logged_bits dropped_packet_logged;
2519 struct mlx5_ifc_port_state_change_event_bits port_state_change_event;
2520 struct mlx5_ifc_gpio_event_bits gpio_event;
2521 struct mlx5_ifc_db_bf_congestion_event_bits db_bf_congestion_event;
2522 struct mlx5_ifc_stall_vl_event_bits stall_vl_event;
2523 struct mlx5_ifc_cmd_inter_comp_event_bits cmd_inter_comp_event;
2524 u8 reserved_0[0xe0];
2525};
2526
2527struct mlx5_ifc_health_buffer_bits {
2528 u8 reserved_0[0x100];
2529
2530 u8 assert_existptr[0x20];
2531
2532 u8 assert_callra[0x20];
2533
2534 u8 reserved_1[0x40];
2535
2536 u8 fw_version[0x20];
2537
2538 u8 hw_id[0x20];
2539
2540 u8 reserved_2[0x20];
2541
2542 u8 irisc_index[0x8];
2543 u8 synd[0x8];
2544 u8 ext_synd[0x10];
2545};
2546
2547struct mlx5_ifc_register_loopback_control_bits {
2548 u8 no_lb[0x1];
2549 u8 reserved_0[0x7];
2550 u8 port[0x8];
2551 u8 reserved_1[0x10];
2552
2553 u8 reserved_2[0x60];
2554};
2555
2556struct mlx5_ifc_teardown_hca_out_bits {
2557 u8 status[0x8];
2558 u8 reserved_0[0x18];
2559
2560 u8 syndrome[0x20];
2561
2562 u8 reserved_1[0x40];
2563};
2564
2565enum {
2566 MLX5_TEARDOWN_HCA_IN_PROFILE_GRACEFUL_CLOSE = 0x0,
2567 MLX5_TEARDOWN_HCA_IN_PROFILE_PANIC_CLOSE = 0x1,
2568};
2569
2570struct mlx5_ifc_teardown_hca_in_bits {
2571 u8 opcode[0x10];
2572 u8 reserved_0[0x10];
2573
2574 u8 reserved_1[0x10];
2575 u8 op_mod[0x10];
2576
2577 u8 reserved_2[0x10];
2578 u8 profile[0x10];
2579
2580 u8 reserved_3[0x20];
2581};
2582
2583struct mlx5_ifc_sqerr2rts_qp_out_bits {
2584 u8 status[0x8];
2585 u8 reserved_0[0x18];
2586
2587 u8 syndrome[0x20];
2588
2589 u8 reserved_1[0x40];
2590};
2591
2592struct mlx5_ifc_sqerr2rts_qp_in_bits {
2593 u8 opcode[0x10];
2594 u8 reserved_0[0x10];
2595
2596 u8 reserved_1[0x10];
2597 u8 op_mod[0x10];
2598
2599 u8 reserved_2[0x8];
2600 u8 qpn[0x18];
2601
2602 u8 reserved_3[0x20];
2603
2604 u8 opt_param_mask[0x20];
2605
2606 u8 reserved_4[0x20];
2607
2608 struct mlx5_ifc_qpc_bits qpc;
2609
2610 u8 reserved_5[0x80];
2611};
2612
2613struct mlx5_ifc_sqd2rts_qp_out_bits {
2614 u8 status[0x8];
2615 u8 reserved_0[0x18];
2616
2617 u8 syndrome[0x20];
2618
2619 u8 reserved_1[0x40];
2620};
2621
2622struct mlx5_ifc_sqd2rts_qp_in_bits {
2623 u8 opcode[0x10];
2624 u8 reserved_0[0x10];
2625
2626 u8 reserved_1[0x10];
2627 u8 op_mod[0x10];
2628
2629 u8 reserved_2[0x8];
2630 u8 qpn[0x18];
2631
2632 u8 reserved_3[0x20];
2633
2634 u8 opt_param_mask[0x20];
2635
2636 u8 reserved_4[0x20];
2637
2638 struct mlx5_ifc_qpc_bits qpc;
2639
2640 u8 reserved_5[0x80];
2641};
2642
2643struct mlx5_ifc_set_roce_address_out_bits {
2644 u8 status[0x8];
2645 u8 reserved_0[0x18];
2646
2647 u8 syndrome[0x20];
2648
2649 u8 reserved_1[0x40];
2650};
2651
2652struct mlx5_ifc_set_roce_address_in_bits {
2653 u8 opcode[0x10];
2654 u8 reserved_0[0x10];
2655
2656 u8 reserved_1[0x10];
2657 u8 op_mod[0x10];
2658
2659 u8 roce_address_index[0x10];
2660 u8 reserved_2[0x10];
2661
2662 u8 reserved_3[0x20];
2663
2664 struct mlx5_ifc_roce_addr_layout_bits roce_address;
2665};
2666
2667struct mlx5_ifc_set_mad_demux_out_bits {
2668 u8 status[0x8];
2669 u8 reserved_0[0x18];
2670
2671 u8 syndrome[0x20];
2672
2673 u8 reserved_1[0x40];
2674};
2675
2676enum {
2677 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_PASS_ALL = 0x0,
2678 MLX5_SET_MAD_DEMUX_IN_DEMUX_MODE_SELECTIVE = 0x2,
2679};
2680
2681struct mlx5_ifc_set_mad_demux_in_bits {
2682 u8 opcode[0x10];
2683 u8 reserved_0[0x10];
2684
2685 u8 reserved_1[0x10];
2686 u8 op_mod[0x10];
2687
2688 u8 reserved_2[0x20];
2689
2690 u8 reserved_3[0x6];
2691 u8 demux_mode[0x2];
2692 u8 reserved_4[0x18];
2693};
2694
2695struct mlx5_ifc_set_l2_table_entry_out_bits {
2696 u8 status[0x8];
2697 u8 reserved_0[0x18];
2698
2699 u8 syndrome[0x20];
2700
2701 u8 reserved_1[0x40];
2702};
2703
2704struct mlx5_ifc_set_l2_table_entry_in_bits {
2705 u8 opcode[0x10];
2706 u8 reserved_0[0x10];
2707
2708 u8 reserved_1[0x10];
2709 u8 op_mod[0x10];
2710
2711 u8 reserved_2[0x60];
2712
2713 u8 reserved_3[0x8];
2714 u8 table_index[0x18];
2715
2716 u8 reserved_4[0x20];
2717
2718 u8 reserved_5[0x13];
2719 u8 vlan_valid[0x1];
2720 u8 vlan[0xc];
2721
2722 struct mlx5_ifc_mac_address_layout_bits mac_address;
2723
2724 u8 reserved_6[0xc0];
2725};
2726
2727struct mlx5_ifc_set_issi_out_bits {
2728 u8 status[0x8];
2729 u8 reserved_0[0x18];
2730
2731 u8 syndrome[0x20];
2732
2733 u8 reserved_1[0x40];
2734};
2735
2736struct mlx5_ifc_set_issi_in_bits {
2737 u8 opcode[0x10];
2738 u8 reserved_0[0x10];
2739
2740 u8 reserved_1[0x10];
2741 u8 op_mod[0x10];
2742
2743 u8 reserved_2[0x10];
2744 u8 current_issi[0x10];
2745
2746 u8 reserved_3[0x20];
2747};
2748
2749struct mlx5_ifc_set_hca_cap_out_bits {
2750 u8 status[0x8];
2751 u8 reserved_0[0x18];
2752
2753 u8 syndrome[0x20];
2754
2755 u8 reserved_1[0x40];
2756};
2757
2758struct mlx5_ifc_set_hca_cap_in_bits {
2759 u8 opcode[0x10];
2760 u8 reserved_0[0x10];
2761
2762 u8 reserved_1[0x10];
2763 u8 op_mod[0x10];
2764
2765 u8 reserved_2[0x40];
2766
2767 union mlx5_ifc_hca_cap_union_bits capability;
2768};
2769
2770struct mlx5_ifc_set_fte_out_bits {
2771 u8 status[0x8];
2772 u8 reserved_0[0x18];
2773
2774 u8 syndrome[0x20];
2775
2776 u8 reserved_1[0x40];
2777};
2778
2779struct mlx5_ifc_set_fte_in_bits {
2780 u8 opcode[0x10];
2781 u8 reserved_0[0x10];
2782
2783 u8 reserved_1[0x10];
2784 u8 op_mod[0x10];
2785
2786 u8 reserved_2[0x40];
2787
2788 u8 table_type[0x8];
2789 u8 reserved_3[0x18];
2790
2791 u8 reserved_4[0x8];
2792 u8 table_id[0x18];
2793
2794 u8 reserved_5[0x40];
2795
2796 u8 flow_index[0x20];
2797
2798 u8 reserved_6[0xe0];
2799
2800 struct mlx5_ifc_flow_context_bits flow_context;
2801};
2802
2803struct mlx5_ifc_rts2rts_qp_out_bits {
2804 u8 status[0x8];
2805 u8 reserved_0[0x18];
2806
2807 u8 syndrome[0x20];
2808
2809 u8 reserved_1[0x40];
2810};
2811
2812struct mlx5_ifc_rts2rts_qp_in_bits {
2813 u8 opcode[0x10];
2814 u8 reserved_0[0x10];
2815
2816 u8 reserved_1[0x10];
2817 u8 op_mod[0x10];
2818
2819 u8 reserved_2[0x8];
2820 u8 qpn[0x18];
2821
2822 u8 reserved_3[0x20];
2823
2824 u8 opt_param_mask[0x20];
2825
2826 u8 reserved_4[0x20];
2827
2828 struct mlx5_ifc_qpc_bits qpc;
2829
2830 u8 reserved_5[0x80];
2831};
2832
2833struct mlx5_ifc_rtr2rts_qp_out_bits {
2834 u8 status[0x8];
2835 u8 reserved_0[0x18];
2836
2837 u8 syndrome[0x20];
2838
2839 u8 reserved_1[0x40];
2840};
2841
2842struct mlx5_ifc_rtr2rts_qp_in_bits {
2843 u8 opcode[0x10];
2844 u8 reserved_0[0x10];
2845
2846 u8 reserved_1[0x10];
2847 u8 op_mod[0x10];
2848
2849 u8 reserved_2[0x8];
2850 u8 qpn[0x18];
2851
2852 u8 reserved_3[0x20];
2853
2854 u8 opt_param_mask[0x20];
2855
2856 u8 reserved_4[0x20];
2857
2858 struct mlx5_ifc_qpc_bits qpc;
2859
2860 u8 reserved_5[0x80];
2861};
2862
2863struct mlx5_ifc_rst2init_qp_out_bits {
2864 u8 status[0x8];
2865 u8 reserved_0[0x18];
2866
2867 u8 syndrome[0x20];
2868
2869 u8 reserved_1[0x40];
2870};
2871
2872struct mlx5_ifc_rst2init_qp_in_bits {
2873 u8 opcode[0x10];
2874 u8 reserved_0[0x10];
2875
2876 u8 reserved_1[0x10];
2877 u8 op_mod[0x10];
2878
2879 u8 reserved_2[0x8];
2880 u8 qpn[0x18];
2881
2882 u8 reserved_3[0x20];
2883
2884 u8 opt_param_mask[0x20];
2885
2886 u8 reserved_4[0x20];
2887
2888 struct mlx5_ifc_qpc_bits qpc;
2889
2890 u8 reserved_5[0x80];
2891};
2892
2893struct mlx5_ifc_query_xrc_srq_out_bits {
2894 u8 status[0x8];
2895 u8 reserved_0[0x18];
2896
2897 u8 syndrome[0x20];
2898
2899 u8 reserved_1[0x40];
2900
2901 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
2902
2903 u8 reserved_2[0x600];
2904
2905 u8 pas[0][0x40];
2906};
2907
2908struct mlx5_ifc_query_xrc_srq_in_bits {
2909 u8 opcode[0x10];
2910 u8 reserved_0[0x10];
2911
2912 u8 reserved_1[0x10];
2913 u8 op_mod[0x10];
2914
2915 u8 reserved_2[0x8];
2916 u8 xrc_srqn[0x18];
2917
2918 u8 reserved_3[0x20];
2919};
2920
2921enum {
2922 MLX5_QUERY_VPORT_STATE_OUT_STATE_DOWN = 0x0,
2923 MLX5_QUERY_VPORT_STATE_OUT_STATE_UP = 0x1,
2924};
2925
2926struct mlx5_ifc_query_vport_state_out_bits {
2927 u8 status[0x8];
2928 u8 reserved_0[0x18];
2929
2930 u8 syndrome[0x20];
2931
2932 u8 reserved_1[0x20];
2933
2934 u8 reserved_2[0x18];
2935 u8 admin_state[0x4];
2936 u8 state[0x4];
2937};
2938
2939enum {
2940 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT = 0x0,
2941};
2942
2943struct mlx5_ifc_query_vport_state_in_bits {
2944 u8 opcode[0x10];
2945 u8 reserved_0[0x10];
2946
2947 u8 reserved_1[0x10];
2948 u8 op_mod[0x10];
2949
2950 u8 other_vport[0x1];
2951 u8 reserved_2[0xf];
2952 u8 vport_number[0x10];
2953
2954 u8 reserved_3[0x20];
2955};
2956
2957struct mlx5_ifc_query_vport_counter_out_bits {
2958 u8 status[0x8];
2959 u8 reserved_0[0x18];
2960
2961 u8 syndrome[0x20];
2962
2963 u8 reserved_1[0x40];
2964
2965 struct mlx5_ifc_traffic_counter_bits received_errors;
2966
2967 struct mlx5_ifc_traffic_counter_bits transmit_errors;
2968
2969 struct mlx5_ifc_traffic_counter_bits received_ib_unicast;
2970
2971 struct mlx5_ifc_traffic_counter_bits transmitted_ib_unicast;
2972
2973 struct mlx5_ifc_traffic_counter_bits received_ib_multicast;
2974
2975 struct mlx5_ifc_traffic_counter_bits transmitted_ib_multicast;
2976
2977 struct mlx5_ifc_traffic_counter_bits received_eth_broadcast;
2978
2979 struct mlx5_ifc_traffic_counter_bits transmitted_eth_broadcast;
2980
2981 struct mlx5_ifc_traffic_counter_bits received_eth_unicast;
2982
2983 struct mlx5_ifc_traffic_counter_bits transmitted_eth_unicast;
2984
2985 struct mlx5_ifc_traffic_counter_bits received_eth_multicast;
2986
2987 struct mlx5_ifc_traffic_counter_bits transmitted_eth_multicast;
2988
2989 u8 reserved_2[0xa00];
2990};
2991
2992enum {
2993 MLX5_QUERY_VPORT_COUNTER_IN_OP_MOD_VPORT_COUNTERS = 0x0,
2994};
2995
2996struct mlx5_ifc_query_vport_counter_in_bits {
2997 u8 opcode[0x10];
2998 u8 reserved_0[0x10];
2999
3000 u8 reserved_1[0x10];
3001 u8 op_mod[0x10];
3002
3003 u8 other_vport[0x1];
3004 u8 reserved_2[0xf];
3005 u8 vport_number[0x10];
3006
3007 u8 reserved_3[0x60];
3008
3009 u8 clear[0x1];
3010 u8 reserved_4[0x1f];
3011
3012 u8 reserved_5[0x20];
3013};
3014
3015struct mlx5_ifc_query_tis_out_bits {
3016 u8 status[0x8];
3017 u8 reserved_0[0x18];
3018
3019 u8 syndrome[0x20];
3020
3021 u8 reserved_1[0x40];
3022
3023 struct mlx5_ifc_tisc_bits tis_context;
3024};
3025
3026struct mlx5_ifc_query_tis_in_bits {
3027 u8 opcode[0x10];
3028 u8 reserved_0[0x10];
3029
3030 u8 reserved_1[0x10];
3031 u8 op_mod[0x10];
3032
3033 u8 reserved_2[0x8];
3034 u8 tisn[0x18];
3035
3036 u8 reserved_3[0x20];
3037};
3038
3039struct mlx5_ifc_query_tir_out_bits {
3040 u8 status[0x8];
3041 u8 reserved_0[0x18];
3042
3043 u8 syndrome[0x20];
3044
3045 u8 reserved_1[0xc0];
3046
3047 struct mlx5_ifc_tirc_bits tir_context;
3048};
3049
3050struct mlx5_ifc_query_tir_in_bits {
3051 u8 opcode[0x10];
3052 u8 reserved_0[0x10];
3053
3054 u8 reserved_1[0x10];
3055 u8 op_mod[0x10];
3056
3057 u8 reserved_2[0x8];
3058 u8 tirn[0x18];
3059
3060 u8 reserved_3[0x20];
3061};
3062
3063struct mlx5_ifc_query_srq_out_bits {
3064 u8 status[0x8];
3065 u8 reserved_0[0x18];
3066
3067 u8 syndrome[0x20];
3068
3069 u8 reserved_1[0x40];
3070
3071 struct mlx5_ifc_srqc_bits srq_context_entry;
3072
3073 u8 reserved_2[0x600];
3074
3075 u8 pas[0][0x40];
3076};
3077
3078struct mlx5_ifc_query_srq_in_bits {
3079 u8 opcode[0x10];
3080 u8 reserved_0[0x10];
3081
3082 u8 reserved_1[0x10];
3083 u8 op_mod[0x10];
3084
3085 u8 reserved_2[0x8];
3086 u8 srqn[0x18];
3087
3088 u8 reserved_3[0x20];
3089};
3090
3091struct mlx5_ifc_query_sq_out_bits {
3092 u8 status[0x8];
3093 u8 reserved_0[0x18];
3094
3095 u8 syndrome[0x20];
3096
3097 u8 reserved_1[0xc0];
3098
3099 struct mlx5_ifc_sqc_bits sq_context;
3100};
3101
3102struct mlx5_ifc_query_sq_in_bits {
3103 u8 opcode[0x10];
3104 u8 reserved_0[0x10];
3105
3106 u8 reserved_1[0x10];
3107 u8 op_mod[0x10];
3108
3109 u8 reserved_2[0x8];
3110 u8 sqn[0x18];
3111
3112 u8 reserved_3[0x20];
3113};
3114
3115struct mlx5_ifc_query_special_contexts_out_bits {
3116 u8 status[0x8];
3117 u8 reserved_0[0x18];
3118
3119 u8 syndrome[0x20];
3120
3121 u8 reserved_1[0x20];
3122
3123 u8 resd_lkey[0x20];
3124};
3125
3126struct mlx5_ifc_query_special_contexts_in_bits {
3127 u8 opcode[0x10];
3128 u8 reserved_0[0x10];
3129
3130 u8 reserved_1[0x10];
3131 u8 op_mod[0x10];
3132
3133 u8 reserved_2[0x40];
3134};
3135
3136struct mlx5_ifc_query_rqt_out_bits {
3137 u8 status[0x8];
3138 u8 reserved_0[0x18];
3139
3140 u8 syndrome[0x20];
3141
3142 u8 reserved_1[0xc0];
3143
3144 struct mlx5_ifc_rqtc_bits rqt_context;
3145};
3146
3147struct mlx5_ifc_query_rqt_in_bits {
3148 u8 opcode[0x10];
3149 u8 reserved_0[0x10];
3150
3151 u8 reserved_1[0x10];
3152 u8 op_mod[0x10];
3153
3154 u8 reserved_2[0x8];
3155 u8 rqtn[0x18];
3156
3157 u8 reserved_3[0x20];
3158};
3159
3160struct mlx5_ifc_query_rq_out_bits {
3161 u8 status[0x8];
3162 u8 reserved_0[0x18];
3163
3164 u8 syndrome[0x20];
3165
3166 u8 reserved_1[0xc0];
3167
3168 struct mlx5_ifc_rqc_bits rq_context;
3169};
3170
3171struct mlx5_ifc_query_rq_in_bits {
3172 u8 opcode[0x10];
3173 u8 reserved_0[0x10];
3174
3175 u8 reserved_1[0x10];
3176 u8 op_mod[0x10];
3177
3178 u8 reserved_2[0x8];
3179 u8 rqn[0x18];
3180
3181 u8 reserved_3[0x20];
3182};
3183
3184struct mlx5_ifc_query_roce_address_out_bits {
3185 u8 status[0x8];
3186 u8 reserved_0[0x18];
3187
3188 u8 syndrome[0x20];
3189
3190 u8 reserved_1[0x40];
3191
3192 struct mlx5_ifc_roce_addr_layout_bits roce_address;
3193};
3194
3195struct mlx5_ifc_query_roce_address_in_bits {
3196 u8 opcode[0x10];
3197 u8 reserved_0[0x10];
3198
3199 u8 reserved_1[0x10];
3200 u8 op_mod[0x10];
3201
3202 u8 roce_address_index[0x10];
3203 u8 reserved_2[0x10];
3204
3205 u8 reserved_3[0x20];
3206};
3207
3208struct mlx5_ifc_query_rmp_out_bits {
3209 u8 status[0x8];
3210 u8 reserved_0[0x18];
3211
3212 u8 syndrome[0x20];
3213
3214 u8 reserved_1[0xc0];
3215
3216 struct mlx5_ifc_rmpc_bits rmp_context;
3217};
3218
3219struct mlx5_ifc_query_rmp_in_bits {
3220 u8 opcode[0x10];
3221 u8 reserved_0[0x10];
3222
3223 u8 reserved_1[0x10];
3224 u8 op_mod[0x10];
3225
3226 u8 reserved_2[0x8];
3227 u8 rmpn[0x18];
3228
3229 u8 reserved_3[0x20];
3230};
3231
3232struct mlx5_ifc_query_qp_out_bits {
3233 u8 status[0x8];
3234 u8 reserved_0[0x18];
3235
3236 u8 syndrome[0x20];
3237
3238 u8 reserved_1[0x40];
3239
3240 u8 opt_param_mask[0x20];
3241
3242 u8 reserved_2[0x20];
3243
3244 struct mlx5_ifc_qpc_bits qpc;
3245
3246 u8 reserved_3[0x80];
3247
3248 u8 pas[0][0x40];
3249};
3250
3251struct mlx5_ifc_query_qp_in_bits {
3252 u8 opcode[0x10];
3253 u8 reserved_0[0x10];
3254
3255 u8 reserved_1[0x10];
3256 u8 op_mod[0x10];
3257
3258 u8 reserved_2[0x8];
3259 u8 qpn[0x18];
3260
3261 u8 reserved_3[0x20];
3262};
3263
3264struct mlx5_ifc_query_q_counter_out_bits {
3265 u8 status[0x8];
3266 u8 reserved_0[0x18];
3267
3268 u8 syndrome[0x20];
3269
3270 u8 reserved_1[0x40];
3271
3272 u8 rx_write_requests[0x20];
3273
3274 u8 reserved_2[0x20];
3275
3276 u8 rx_read_requests[0x20];
3277
3278 u8 reserved_3[0x20];
3279
3280 u8 rx_atomic_requests[0x20];
3281
3282 u8 reserved_4[0x20];
3283
3284 u8 rx_dct_connect[0x20];
3285
3286 u8 reserved_5[0x20];
3287
3288 u8 out_of_buffer[0x20];
3289
3290 u8 reserved_6[0x20];
3291
3292 u8 out_of_sequence[0x20];
3293
3294 u8 reserved_7[0x620];
3295};
3296
3297struct mlx5_ifc_query_q_counter_in_bits {
3298 u8 opcode[0x10];
3299 u8 reserved_0[0x10];
3300
3301 u8 reserved_1[0x10];
3302 u8 op_mod[0x10];
3303
3304 u8 reserved_2[0x80];
3305
3306 u8 clear[0x1];
3307 u8 reserved_3[0x1f];
3308
3309 u8 reserved_4[0x18];
3310 u8 counter_set_id[0x8];
3311};
3312
3313struct mlx5_ifc_query_pages_out_bits {
3314 u8 status[0x8];
3315 u8 reserved_0[0x18];
3316
3317 u8 syndrome[0x20];
3318
3319 u8 reserved_1[0x10];
3320 u8 function_id[0x10];
3321
3322 u8 num_pages[0x20];
3323};
3324
3325enum {
3326 MLX5_QUERY_PAGES_IN_OP_MOD_BOOT_PAGES = 0x1,
3327 MLX5_QUERY_PAGES_IN_OP_MOD_INIT_PAGES = 0x2,
3328 MLX5_QUERY_PAGES_IN_OP_MOD_REGULAR_PAGES = 0x3,
3329};
3330
3331struct mlx5_ifc_query_pages_in_bits {
3332 u8 opcode[0x10];
3333 u8 reserved_0[0x10];
3334
3335 u8 reserved_1[0x10];
3336 u8 op_mod[0x10];
3337
3338 u8 reserved_2[0x10];
3339 u8 function_id[0x10];
3340
3341 u8 reserved_3[0x20];
3342};
3343
3344struct mlx5_ifc_query_nic_vport_context_out_bits {
3345 u8 status[0x8];
3346 u8 reserved_0[0x18];
3347
3348 u8 syndrome[0x20];
3349
3350 u8 reserved_1[0x40];
3351
3352 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
3353};
3354
3355struct mlx5_ifc_query_nic_vport_context_in_bits {
3356 u8 opcode[0x10];
3357 u8 reserved_0[0x10];
3358
3359 u8 reserved_1[0x10];
3360 u8 op_mod[0x10];
3361
3362 u8 other_vport[0x1];
3363 u8 reserved_2[0xf];
3364 u8 vport_number[0x10];
3365
3366 u8 reserved_3[0x5];
3367 u8 allowed_list_type[0x3];
3368 u8 reserved_4[0x18];
3369};
3370
3371struct mlx5_ifc_query_mkey_out_bits {
3372 u8 status[0x8];
3373 u8 reserved_0[0x18];
3374
3375 u8 syndrome[0x20];
3376
3377 u8 reserved_1[0x40];
3378
3379 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
3380
3381 u8 reserved_2[0x600];
3382
3383 u8 bsf0_klm0_pas_mtt0_1[16][0x8];
3384
3385 u8 bsf1_klm1_pas_mtt2_3[16][0x8];
3386};
3387
3388struct mlx5_ifc_query_mkey_in_bits {
3389 u8 opcode[0x10];
3390 u8 reserved_0[0x10];
3391
3392 u8 reserved_1[0x10];
3393 u8 op_mod[0x10];
3394
3395 u8 reserved_2[0x8];
3396 u8 mkey_index[0x18];
3397
3398 u8 pg_access[0x1];
3399 u8 reserved_3[0x1f];
3400};
3401
3402struct mlx5_ifc_query_mad_demux_out_bits {
3403 u8 status[0x8];
3404 u8 reserved_0[0x18];
3405
3406 u8 syndrome[0x20];
3407
3408 u8 reserved_1[0x40];
3409
3410 u8 mad_dumux_parameters_block[0x20];
3411};
3412
3413struct mlx5_ifc_query_mad_demux_in_bits {
3414 u8 opcode[0x10];
3415 u8 reserved_0[0x10];
3416
3417 u8 reserved_1[0x10];
3418 u8 op_mod[0x10];
3419
3420 u8 reserved_2[0x40];
3421};
3422
3423struct mlx5_ifc_query_l2_table_entry_out_bits {
3424 u8 status[0x8];
3425 u8 reserved_0[0x18];
3426
3427 u8 syndrome[0x20];
3428
3429 u8 reserved_1[0xa0];
3430
3431 u8 reserved_2[0x13];
3432 u8 vlan_valid[0x1];
3433 u8 vlan[0xc];
3434
3435 struct mlx5_ifc_mac_address_layout_bits mac_address;
3436
3437 u8 reserved_3[0xc0];
3438};
3439
3440struct mlx5_ifc_query_l2_table_entry_in_bits {
3441 u8 opcode[0x10];
3442 u8 reserved_0[0x10];
3443
3444 u8 reserved_1[0x10];
3445 u8 op_mod[0x10];
3446
3447 u8 reserved_2[0x60];
3448
3449 u8 reserved_3[0x8];
3450 u8 table_index[0x18];
3451
3452 u8 reserved_4[0x140];
3453};
3454
3455struct mlx5_ifc_query_issi_out_bits {
3456 u8 status[0x8];
3457 u8 reserved_0[0x18];
3458
3459 u8 syndrome[0x20];
3460
3461 u8 reserved_1[0x10];
3462 u8 current_issi[0x10];
3463
3464 u8 reserved_2[0xa0];
3465
3466 u8 supported_issi_reserved[76][0x8];
3467 u8 supported_issi_dw0[0x20];
3468};
3469
3470struct mlx5_ifc_query_issi_in_bits {
3471 u8 opcode[0x10];
3472 u8 reserved_0[0x10];
3473
3474 u8 reserved_1[0x10];
3475 u8 op_mod[0x10];
3476
3477 u8 reserved_2[0x40];
3478};
3479
3480struct mlx5_ifc_query_hca_vport_pkey_out_bits {
3481 u8 status[0x8];
3482 u8 reserved_0[0x18];
3483
3484 u8 syndrome[0x20];
3485
3486 u8 reserved_1[0x40];
3487
3488 struct mlx5_ifc_pkey_bits pkey[0];
3489};
3490
3491struct mlx5_ifc_query_hca_vport_pkey_in_bits {
3492 u8 opcode[0x10];
3493 u8 reserved_0[0x10];
3494
3495 u8 reserved_1[0x10];
3496 u8 op_mod[0x10];
3497
3498 u8 other_vport[0x1];
707c4602
MD		 3499 u8 reserved_2[0xb];
3500 u8 port_num[0x4];
e281682b
SM		 3501 u8 vport_number[0x10];
3502
3503 u8 reserved_3[0x10];
3504 u8 pkey_index[0x10];
3505};
3506
3507struct mlx5_ifc_query_hca_vport_gid_out_bits {
3508 u8 status[0x8];
3509 u8 reserved_0[0x18];
3510
3511 u8 syndrome[0x20];
3512
3513 u8 reserved_1[0x20];
3514
3515 u8 gids_num[0x10];
3516 u8 reserved_2[0x10];
3517
3518 struct mlx5_ifc_array128_auto_bits gid[0];
3519};
3520
3521struct mlx5_ifc_query_hca_vport_gid_in_bits {
3522 u8 opcode[0x10];
3523 u8 reserved_0[0x10];
3524
3525 u8 reserved_1[0x10];
3526 u8 op_mod[0x10];
3527
3528 u8 other_vport[0x1];
707c4602
MD		 3529 u8 reserved_2[0xb];
3530 u8 port_num[0x4];
e281682b
SM		 3531 u8 vport_number[0x10];
3532
3533 u8 reserved_3[0x10];
3534 u8 gid_index[0x10];
3535};
3536
3537struct mlx5_ifc_query_hca_vport_context_out_bits {
3538 u8 status[0x8];
3539 u8 reserved_0[0x18];
3540
3541 u8 syndrome[0x20];
3542
3543 u8 reserved_1[0x40];
3544
3545 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
3546};
3547
3548struct mlx5_ifc_query_hca_vport_context_in_bits {
3549 u8 opcode[0x10];
3550 u8 reserved_0[0x10];
3551
3552 u8 reserved_1[0x10];
3553 u8 op_mod[0x10];
3554
3555 u8 other_vport[0x1];
707c4602
MD		 3556 u8 reserved_2[0xb];
3557 u8 port_num[0x4];
e281682b
SM		 3558 u8 vport_number[0x10];
3559
3560 u8 reserved_3[0x20];
3561};
3562
3563struct mlx5_ifc_query_hca_cap_out_bits {
3564 u8 status[0x8];
3565 u8 reserved_0[0x18];
3566
3567 u8 syndrome[0x20];
3568
3569 u8 reserved_1[0x40];
3570
3571 union mlx5_ifc_hca_cap_union_bits capability;
3572};
3573
3574struct mlx5_ifc_query_hca_cap_in_bits {
3575 u8 opcode[0x10];
3576 u8 reserved_0[0x10];
3577
3578 u8 reserved_1[0x10];
3579 u8 op_mod[0x10];
3580
3581 u8 reserved_2[0x40];
3582};
3583
3584struct mlx5_ifc_query_flow_table_out_bits {
3585 u8 status[0x8];
3586 u8 reserved_0[0x18];
3587
3588 u8 syndrome[0x20];
3589
3590 u8 reserved_1[0x80];
3591
3592 u8 reserved_2[0x8];
3593 u8 level[0x8];
3594 u8 reserved_3[0x8];
3595 u8 log_size[0x8];
3596
3597 u8 reserved_4[0x120];
3598};
3599
3600struct mlx5_ifc_query_flow_table_in_bits {
3601 u8 opcode[0x10];
3602 u8 reserved_0[0x10];
3603
3604 u8 reserved_1[0x10];
3605 u8 op_mod[0x10];
3606
3607 u8 reserved_2[0x40];
3608
3609 u8 table_type[0x8];
3610 u8 reserved_3[0x18];
3611
3612 u8 reserved_4[0x8];
3613 u8 table_id[0x18];
3614
3615 u8 reserved_5[0x140];
3616};
3617
3618struct mlx5_ifc_query_fte_out_bits {
3619 u8 status[0x8];
3620 u8 reserved_0[0x18];
3621
3622 u8 syndrome[0x20];
3623
3624 u8 reserved_1[0x1c0];
3625
3626 struct mlx5_ifc_flow_context_bits flow_context;
3627};
3628
3629struct mlx5_ifc_query_fte_in_bits {
3630 u8 opcode[0x10];
3631 u8 reserved_0[0x10];
3632
3633 u8 reserved_1[0x10];
3634 u8 op_mod[0x10];
3635
3636 u8 reserved_2[0x40];
3637
3638 u8 table_type[0x8];
3639 u8 reserved_3[0x18];
3640
3641 u8 reserved_4[0x8];
3642 u8 table_id[0x18];
3643
3644 u8 reserved_5[0x40];
3645
3646 u8 flow_index[0x20];
3647
3648 u8 reserved_6[0xe0];
3649};
3650
3651enum {
3652 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
3653 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
3654 MLX5_QUERY_FLOW_GROUP_OUT_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
3655};
3656
3657struct mlx5_ifc_query_flow_group_out_bits {
3658 u8 status[0x8];
3659 u8 reserved_0[0x18];
3660
3661 u8 syndrome[0x20];
3662
3663 u8 reserved_1[0xa0];
3664
3665 u8 start_flow_index[0x20];
3666
3667 u8 reserved_2[0x20];
3668
3669 u8 end_flow_index[0x20];
3670
3671 u8 reserved_3[0xa0];
3672
3673 u8 reserved_4[0x18];
3674 u8 match_criteria_enable[0x8];
3675
3676 struct mlx5_ifc_fte_match_param_bits match_criteria;
3677
3678 u8 reserved_5[0xe00];
3679};
3680
3681struct mlx5_ifc_query_flow_group_in_bits {
3682 u8 opcode[0x10];
3683 u8 reserved_0[0x10];
3684
3685 u8 reserved_1[0x10];
3686 u8 op_mod[0x10];
3687
3688 u8 reserved_2[0x40];
3689
3690 u8 table_type[0x8];
3691 u8 reserved_3[0x18];
3692
3693 u8 reserved_4[0x8];
3694 u8 table_id[0x18];
3695
3696 u8 group_id[0x20];
3697
3698 u8 reserved_5[0x120];
3699};
3700
3701struct mlx5_ifc_query_eq_out_bits {
3702 u8 status[0x8];
3703 u8 reserved_0[0x18];
3704
3705 u8 syndrome[0x20];
3706
3707 u8 reserved_1[0x40];
3708
3709 struct mlx5_ifc_eqc_bits eq_context_entry;
3710
3711 u8 reserved_2[0x40];
3712
3713 u8 event_bitmask[0x40];
3714
3715 u8 reserved_3[0x580];
3716
3717 u8 pas[0][0x40];
3718};
3719
3720struct mlx5_ifc_query_eq_in_bits {
3721 u8 opcode[0x10];
3722 u8 reserved_0[0x10];
3723
3724 u8 reserved_1[0x10];
3725 u8 op_mod[0x10];
3726
3727 u8 reserved_2[0x18];
3728 u8 eq_number[0x8];
3729
3730 u8 reserved_3[0x20];
3731};
3732
3733struct mlx5_ifc_query_dct_out_bits {
3734 u8 status[0x8];
3735 u8 reserved_0[0x18];
3736
3737 u8 syndrome[0x20];
3738
3739 u8 reserved_1[0x40];
3740
3741 struct mlx5_ifc_dctc_bits dct_context_entry;
3742
3743 u8 reserved_2[0x180];
3744};
3745
3746struct mlx5_ifc_query_dct_in_bits {
3747 u8 opcode[0x10];
3748 u8 reserved_0[0x10];
3749
3750 u8 reserved_1[0x10];
3751 u8 op_mod[0x10];
3752
3753 u8 reserved_2[0x8];
3754 u8 dctn[0x18];
3755
3756 u8 reserved_3[0x20];
3757};
3758
3759struct mlx5_ifc_query_cq_out_bits {
3760 u8 status[0x8];
3761 u8 reserved_0[0x18];
3762
3763 u8 syndrome[0x20];
3764
3765 u8 reserved_1[0x40];
3766
3767 struct mlx5_ifc_cqc_bits cq_context;
3768
3769 u8 reserved_2[0x600];
3770
3771 u8 pas[0][0x40];
3772};
3773
3774struct mlx5_ifc_query_cq_in_bits {
3775 u8 opcode[0x10];
3776 u8 reserved_0[0x10];
3777
3778 u8 reserved_1[0x10];
3779 u8 op_mod[0x10];
3780
3781 u8 reserved_2[0x8];
3782 u8 cqn[0x18];
3783
3784 u8 reserved_3[0x20];
3785};
3786
3787struct mlx5_ifc_query_cong_status_out_bits {
3788 u8 status[0x8];
3789 u8 reserved_0[0x18];
3790
3791 u8 syndrome[0x20];
3792
3793 u8 reserved_1[0x20];
3794
3795 u8 enable[0x1];
3796 u8 tag_enable[0x1];
3797 u8 reserved_2[0x1e];
3798};
3799
3800struct mlx5_ifc_query_cong_status_in_bits {
3801 u8 opcode[0x10];
3802 u8 reserved_0[0x10];
3803
3804 u8 reserved_1[0x10];
3805 u8 op_mod[0x10];
3806
3807 u8 reserved_2[0x18];
3808 u8 priority[0x4];
3809 u8 cong_protocol[0x4];
3810
3811 u8 reserved_3[0x20];
3812};
3813
3814struct mlx5_ifc_query_cong_statistics_out_bits {
3815 u8 status[0x8];
3816 u8 reserved_0[0x18];
3817
3818 u8 syndrome[0x20];
3819
3820 u8 reserved_1[0x40];
3821
3822 u8 cur_flows[0x20];
3823
3824 u8 sum_flows[0x20];
3825
3826 u8 cnp_ignored_high[0x20];
3827
3828 u8 cnp_ignored_low[0x20];
3829
3830 u8 cnp_handled_high[0x20];
3831
3832 u8 cnp_handled_low[0x20];
3833
3834 u8 reserved_2[0x100];
3835
3836 u8 time_stamp_high[0x20];
3837
3838 u8 time_stamp_low[0x20];
3839
3840 u8 accumulators_period[0x20];
3841
3842 u8 ecn_marked_roce_packets_high[0x20];
3843
3844 u8 ecn_marked_roce_packets_low[0x20];
3845
3846 u8 cnps_sent_high[0x20];
3847
3848 u8 cnps_sent_low[0x20];
3849
3850 u8 reserved_3[0x560];
3851};
3852
3853struct mlx5_ifc_query_cong_statistics_in_bits {
3854 u8 opcode[0x10];
3855 u8 reserved_0[0x10];
3856
3857 u8 reserved_1[0x10];
3858 u8 op_mod[0x10];
3859
3860 u8 clear[0x1];
3861 u8 reserved_2[0x1f];
3862
3863 u8 reserved_3[0x20];
3864};
3865
3866struct mlx5_ifc_query_cong_params_out_bits {
3867 u8 status[0x8];
3868 u8 reserved_0[0x18];
3869
3870 u8 syndrome[0x20];
3871
3872 u8 reserved_1[0x40];
3873
3874 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
3875};
3876
3877struct mlx5_ifc_query_cong_params_in_bits {
3878 u8 opcode[0x10];
3879 u8 reserved_0[0x10];
3880
3881 u8 reserved_1[0x10];
3882 u8 op_mod[0x10];
3883
3884 u8 reserved_2[0x1c];
3885 u8 cong_protocol[0x4];
3886
3887 u8 reserved_3[0x20];
3888};
3889
3890struct mlx5_ifc_query_adapter_out_bits {
3891 u8 status[0x8];
3892 u8 reserved_0[0x18];
3893
3894 u8 syndrome[0x20];
3895
3896 u8 reserved_1[0x40];
3897
3898 struct mlx5_ifc_query_adapter_param_block_bits query_adapter_struct;
3899};
3900
3901struct mlx5_ifc_query_adapter_in_bits {
3902 u8 opcode[0x10];
3903 u8 reserved_0[0x10];
3904
3905 u8 reserved_1[0x10];
3906 u8 op_mod[0x10];
3907
3908 u8 reserved_2[0x40];
3909};
3910
3911struct mlx5_ifc_qp_2rst_out_bits {
3912 u8 status[0x8];
3913 u8 reserved_0[0x18];
3914
3915 u8 syndrome[0x20];
3916
3917 u8 reserved_1[0x40];
3918};
3919
3920struct mlx5_ifc_qp_2rst_in_bits {
3921 u8 opcode[0x10];
3922 u8 reserved_0[0x10];
3923
3924 u8 reserved_1[0x10];
3925 u8 op_mod[0x10];
3926
3927 u8 reserved_2[0x8];
3928 u8 qpn[0x18];
3929
3930 u8 reserved_3[0x20];
3931};
3932
3933struct mlx5_ifc_qp_2err_out_bits {
3934 u8 status[0x8];
3935 u8 reserved_0[0x18];
3936
3937 u8 syndrome[0x20];
3938
3939 u8 reserved_1[0x40];
3940};
3941
3942struct mlx5_ifc_qp_2err_in_bits {
3943 u8 opcode[0x10];
3944 u8 reserved_0[0x10];
3945
3946 u8 reserved_1[0x10];
3947 u8 op_mod[0x10];
3948
3949 u8 reserved_2[0x8];
3950 u8 qpn[0x18];
3951
3952 u8 reserved_3[0x20];
3953};
3954
3955struct mlx5_ifc_page_fault_resume_out_bits {
3956 u8 status[0x8];
3957 u8 reserved_0[0x18];
3958
3959 u8 syndrome[0x20];
3960
3961 u8 reserved_1[0x40];
3962};
3963
3964struct mlx5_ifc_page_fault_resume_in_bits {
3965 u8 opcode[0x10];
3966 u8 reserved_0[0x10];
3967
3968 u8 reserved_1[0x10];
3969 u8 op_mod[0x10];
3970
3971 u8 error[0x1];
3972 u8 reserved_2[0x4];
3973 u8 rdma[0x1];
3974 u8 read_write[0x1];
3975 u8 req_res[0x1];
3976 u8 qpn[0x18];
3977
3978 u8 reserved_3[0x20];
3979};
3980
3981struct mlx5_ifc_nop_out_bits {
3982 u8 status[0x8];
3983 u8 reserved_0[0x18];
3984
3985 u8 syndrome[0x20];
3986
3987 u8 reserved_1[0x40];
3988};
3989
3990struct mlx5_ifc_nop_in_bits {
3991 u8 opcode[0x10];
3992 u8 reserved_0[0x10];
3993
3994 u8 reserved_1[0x10];
3995 u8 op_mod[0x10];
3996
3997 u8 reserved_2[0x40];
3998};
3999
4000struct mlx5_ifc_modify_vport_state_out_bits {
4001 u8 status[0x8];
4002 u8 reserved_0[0x18];
4003
4004 u8 syndrome[0x20];
4005
4006 u8 reserved_1[0x40];
4007};
4008
4009struct mlx5_ifc_modify_vport_state_in_bits {
4010 u8 opcode[0x10];
4011 u8 reserved_0[0x10];
4012
4013 u8 reserved_1[0x10];
4014 u8 op_mod[0x10];
4015
4016 u8 other_vport[0x1];
4017 u8 reserved_2[0xf];
4018 u8 vport_number[0x10];
4019
4020 u8 reserved_3[0x18];
4021 u8 admin_state[0x4];
4022 u8 reserved_4[0x4];
4023};
4024
4025struct mlx5_ifc_modify_tis_out_bits {
4026 u8 status[0x8];
4027 u8 reserved_0[0x18];
4028
4029 u8 syndrome[0x20];
4030
4031 u8 reserved_1[0x40];
4032};
4033
4034struct mlx5_ifc_modify_tis_in_bits {
4035 u8 opcode[0x10];
4036 u8 reserved_0[0x10];
4037
4038 u8 reserved_1[0x10];
4039 u8 op_mod[0x10];
4040
4041 u8 reserved_2[0x8];
4042 u8 tisn[0x18];
4043
4044 u8 reserved_3[0x20];
4045
4046 u8 modify_bitmask[0x40];
4047
4048 u8 reserved_4[0x40];
4049
4050 struct mlx5_ifc_tisc_bits ctx;
4051};
4052
4053struct mlx5_ifc_modify_tir_out_bits {
4054 u8 status[0x8];
4055 u8 reserved_0[0x18];
4056
4057 u8 syndrome[0x20];
4058
4059 u8 reserved_1[0x40];
4060};
4061
4062struct mlx5_ifc_modify_tir_in_bits {
4063 u8 opcode[0x10];
4064 u8 reserved_0[0x10];
4065
4066 u8 reserved_1[0x10];
4067 u8 op_mod[0x10];
4068
4069 u8 reserved_2[0x8];
4070 u8 tirn[0x18];
4071
4072 u8 reserved_3[0x20];
4073
4074 u8 modify_bitmask[0x40];
4075
4076 u8 reserved_4[0x40];
4077
4078 struct mlx5_ifc_tirc_bits ctx;
4079};
4080
4081struct mlx5_ifc_modify_sq_out_bits {
4082 u8 status[0x8];
4083 u8 reserved_0[0x18];
4084
4085 u8 syndrome[0x20];
4086
4087 u8 reserved_1[0x40];
4088};
4089
4090struct mlx5_ifc_modify_sq_in_bits {
4091 u8 opcode[0x10];
4092 u8 reserved_0[0x10];
4093
4094 u8 reserved_1[0x10];
4095 u8 op_mod[0x10];
4096
4097 u8 sq_state[0x4];
4098 u8 reserved_2[0x4];
4099 u8 sqn[0x18];
4100
4101 u8 reserved_3[0x20];
4102
4103 u8 modify_bitmask[0x40];
4104
4105 u8 reserved_4[0x40];
4106
4107 struct mlx5_ifc_sqc_bits ctx;
4108};
4109
4110struct mlx5_ifc_modify_rqt_out_bits {
4111 u8 status[0x8];
4112 u8 reserved_0[0x18];
4113
4114 u8 syndrome[0x20];
4115
4116 u8 reserved_1[0x40];
4117};
4118
4119struct mlx5_ifc_modify_rqt_in_bits {
4120 u8 opcode[0x10];
4121 u8 reserved_0[0x10];
4122
4123 u8 reserved_1[0x10];
4124 u8 op_mod[0x10];
4125
4126 u8 reserved_2[0x8];
4127 u8 rqtn[0x18];
4128
4129 u8 reserved_3[0x20];
4130
4131 u8 modify_bitmask[0x40];
4132
4133 u8 reserved_4[0x40];
4134
4135 struct mlx5_ifc_rqtc_bits ctx;
4136};
4137
4138struct mlx5_ifc_modify_rq_out_bits {
4139 u8 status[0x8];
4140 u8 reserved_0[0x18];
4141
4142 u8 syndrome[0x20];
4143
4144 u8 reserved_1[0x40];
4145};
4146
4147struct mlx5_ifc_modify_rq_in_bits {
4148 u8 opcode[0x10];
4149 u8 reserved_0[0x10];
4150
4151 u8 reserved_1[0x10];
4152 u8 op_mod[0x10];
4153
4154 u8 rq_state[0x4];
4155 u8 reserved_2[0x4];
4156 u8 rqn[0x18];
4157
4158 u8 reserved_3[0x20];
4159
4160 u8 modify_bitmask[0x40];
4161
4162 u8 reserved_4[0x40];
4163
4164 struct mlx5_ifc_rqc_bits ctx;
4165};
4166
4167struct mlx5_ifc_modify_rmp_out_bits {
4168 u8 status[0x8];
4169 u8 reserved_0[0x18];
4170
4171 u8 syndrome[0x20];
4172
4173 u8 reserved_1[0x40];
4174};
4175
01949d01
HA		 4176struct mlx5_ifc_rmp_bitmask_bits {
4177 u8 reserved[0x20];
4178
4179 u8 reserved1[0x1f];
4180 u8 lwm[0x1];
4181};
4182
e281682b
SM		 4183struct mlx5_ifc_modify_rmp_in_bits {
4184 u8 opcode[0x10];
4185 u8 reserved_0[0x10];
4186
4187 u8 reserved_1[0x10];
4188 u8 op_mod[0x10];
4189
4190 u8 rmp_state[0x4];
4191 u8 reserved_2[0x4];
4192 u8 rmpn[0x18];
4193
4194 u8 reserved_3[0x20];
4195
01949d01 4196 struct mlx5_ifc_rmp_bitmask_bits bitmask;
e281682b
SM		 4197
4198 u8 reserved_4[0x40];
4199
4200 struct mlx5_ifc_rmpc_bits ctx;
4201};
4202
4203struct mlx5_ifc_modify_nic_vport_context_out_bits {
4204 u8 status[0x8];
4205 u8 reserved_0[0x18];
4206
4207 u8 syndrome[0x20];
4208
4209 u8 reserved_1[0x40];
4210};
4211
4212struct mlx5_ifc_modify_nic_vport_field_select_bits {
4213 u8 reserved_0[0x1c];
4214 u8 permanent_address[0x1];
4215 u8 addresses_list[0x1];
4216 u8 roce_en[0x1];
4217 u8 reserved_1[0x1];
4218};
4219
4220struct mlx5_ifc_modify_nic_vport_context_in_bits {
4221 u8 opcode[0x10];
4222 u8 reserved_0[0x10];
4223
4224 u8 reserved_1[0x10];
4225 u8 op_mod[0x10];
4226
4227 u8 other_vport[0x1];
4228 u8 reserved_2[0xf];
4229 u8 vport_number[0x10];
4230
4231 struct mlx5_ifc_modify_nic_vport_field_select_bits field_select;
4232
4233 u8 reserved_3[0x780];
4234
4235 struct mlx5_ifc_nic_vport_context_bits nic_vport_context;
4236};
4237
4238struct mlx5_ifc_modify_hca_vport_context_out_bits {
4239 u8 status[0x8];
4240 u8 reserved_0[0x18];
4241
4242 u8 syndrome[0x20];
4243
4244 u8 reserved_1[0x40];
4245};
4246
4247struct mlx5_ifc_modify_hca_vport_context_in_bits {
4248 u8 opcode[0x10];
4249 u8 reserved_0[0x10];
4250
4251 u8 reserved_1[0x10];
4252 u8 op_mod[0x10];
4253
4254 u8 other_vport[0x1];
707c4602
MD		 4255 u8 reserved_2[0xb];
4256 u8 port_num[0x4];
e281682b
SM		 4257 u8 vport_number[0x10];
4258
4259 u8 reserved_3[0x20];
4260
4261 struct mlx5_ifc_hca_vport_context_bits hca_vport_context;
4262};
4263
4264struct mlx5_ifc_modify_cq_out_bits {
4265 u8 status[0x8];
4266 u8 reserved_0[0x18];
4267
4268 u8 syndrome[0x20];
4269
4270 u8 reserved_1[0x40];
4271};
4272
4273enum {
4274 MLX5_MODIFY_CQ_IN_OP_MOD_MODIFY_CQ = 0x0,
4275 MLX5_MODIFY_CQ_IN_OP_MOD_RESIZE_CQ = 0x1,
4276};
4277
4278struct mlx5_ifc_modify_cq_in_bits {
4279 u8 opcode[0x10];
4280 u8 reserved_0[0x10];
4281
4282 u8 reserved_1[0x10];
4283 u8 op_mod[0x10];
4284
4285 u8 reserved_2[0x8];
4286 u8 cqn[0x18];
4287
4288 union mlx5_ifc_modify_field_select_resize_field_select_auto_bits modify_field_select_resize_field_select;
4289
4290 struct mlx5_ifc_cqc_bits cq_context;
4291
4292 u8 reserved_3[0x600];
4293
4294 u8 pas[0][0x40];
4295};
4296
4297struct mlx5_ifc_modify_cong_status_out_bits {
4298 u8 status[0x8];
4299 u8 reserved_0[0x18];
4300
4301 u8 syndrome[0x20];
4302
4303 u8 reserved_1[0x40];
4304};
4305
4306struct mlx5_ifc_modify_cong_status_in_bits {
4307 u8 opcode[0x10];
4308 u8 reserved_0[0x10];
4309
4310 u8 reserved_1[0x10];
4311 u8 op_mod[0x10];
4312
4313 u8 reserved_2[0x18];
4314 u8 priority[0x4];
4315 u8 cong_protocol[0x4];
4316
4317 u8 enable[0x1];
4318 u8 tag_enable[0x1];
4319 u8 reserved_3[0x1e];
4320};
4321
4322struct mlx5_ifc_modify_cong_params_out_bits {
4323 u8 status[0x8];
4324 u8 reserved_0[0x18];
4325
4326 u8 syndrome[0x20];
4327
4328 u8 reserved_1[0x40];
4329};
4330
4331struct mlx5_ifc_modify_cong_params_in_bits {
4332 u8 opcode[0x10];
4333 u8 reserved_0[0x10];
4334
4335 u8 reserved_1[0x10];
4336 u8 op_mod[0x10];
4337
4338 u8 reserved_2[0x1c];
4339 u8 cong_protocol[0x4];
4340
4341 union mlx5_ifc_field_select_802_1_r_roce_auto_bits field_select;
4342
4343 u8 reserved_3[0x80];
4344
4345 union mlx5_ifc_cong_control_roce_ecn_auto_bits congestion_parameters;
4346};
4347
4348struct mlx5_ifc_manage_pages_out_bits {
4349 u8 status[0x8];
4350 u8 reserved_0[0x18];
4351
4352 u8 syndrome[0x20];
4353
4354 u8 output_num_entries[0x20];
4355
4356 u8 reserved_1[0x20];
4357
4358 u8 pas[0][0x40];
4359};
4360
4361enum {
4362 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_FAIL = 0x0,
4363 MLX5_MANAGE_PAGES_IN_OP_MOD_ALLOCATION_SUCCESS = 0x1,
4364 MLX5_MANAGE_PAGES_IN_OP_MOD_HCA_RETURN_PAGES = 0x2,
4365};
4366
4367struct mlx5_ifc_manage_pages_in_bits {
4368 u8 opcode[0x10];
4369 u8 reserved_0[0x10];
4370
4371 u8 reserved_1[0x10];
4372 u8 op_mod[0x10];
4373
4374 u8 reserved_2[0x10];
4375 u8 function_id[0x10];
4376
4377 u8 input_num_entries[0x20];
4378
4379 u8 pas[0][0x40];
4380};
4381
4382struct mlx5_ifc_mad_ifc_out_bits {
4383 u8 status[0x8];
4384 u8 reserved_0[0x18];
4385
4386 u8 syndrome[0x20];
4387
4388 u8 reserved_1[0x40];
4389
4390 u8 response_mad_packet[256][0x8];
4391};
4392
4393struct mlx5_ifc_mad_ifc_in_bits {
4394 u8 opcode[0x10];
4395 u8 reserved_0[0x10];
4396
4397 u8 reserved_1[0x10];
4398 u8 op_mod[0x10];
4399
4400 u8 remote_lid[0x10];
4401 u8 reserved_2[0x8];
4402 u8 port[0x8];
4403
4404 u8 reserved_3[0x20];
4405
4406 u8 mad[256][0x8];
4407};
4408
4409struct mlx5_ifc_init_hca_out_bits {
4410 u8 status[0x8];
4411 u8 reserved_0[0x18];
4412
4413 u8 syndrome[0x20];
4414
4415 u8 reserved_1[0x40];
4416};
4417
4418struct mlx5_ifc_init_hca_in_bits {
4419 u8 opcode[0x10];
4420 u8 reserved_0[0x10];
4421
4422 u8 reserved_1[0x10];
4423 u8 op_mod[0x10];
4424
4425 u8 reserved_2[0x40];
4426};
4427
4428struct mlx5_ifc_init2rtr_qp_out_bits {
4429 u8 status[0x8];
4430 u8 reserved_0[0x18];
4431
4432 u8 syndrome[0x20];
4433
4434 u8 reserved_1[0x40];
4435};
4436
4437struct mlx5_ifc_init2rtr_qp_in_bits {
4438 u8 opcode[0x10];
4439 u8 reserved_0[0x10];
4440
4441 u8 reserved_1[0x10];
4442 u8 op_mod[0x10];
4443
4444 u8 reserved_2[0x8];
4445 u8 qpn[0x18];
4446
4447 u8 reserved_3[0x20];
4448
4449 u8 opt_param_mask[0x20];
4450
4451 u8 reserved_4[0x20];
4452
4453 struct mlx5_ifc_qpc_bits qpc;
4454
4455 u8 reserved_5[0x80];
4456};
4457
4458struct mlx5_ifc_init2init_qp_out_bits {
4459 u8 status[0x8];
4460 u8 reserved_0[0x18];
4461
4462 u8 syndrome[0x20];
4463
4464 u8 reserved_1[0x40];
4465};
4466
4467struct mlx5_ifc_init2init_qp_in_bits {
4468 u8 opcode[0x10];
4469 u8 reserved_0[0x10];
4470
4471 u8 reserved_1[0x10];
4472 u8 op_mod[0x10];
4473
4474 u8 reserved_2[0x8];
4475 u8 qpn[0x18];
4476
4477 u8 reserved_3[0x20];
4478
4479 u8 opt_param_mask[0x20];
4480
4481 u8 reserved_4[0x20];
4482
4483 struct mlx5_ifc_qpc_bits qpc;
4484
4485 u8 reserved_5[0x80];
4486};
4487
4488struct mlx5_ifc_get_dropped_packet_log_out_bits {
4489 u8 status[0x8];
4490 u8 reserved_0[0x18];
4491
4492 u8 syndrome[0x20];
4493
4494 u8 reserved_1[0x40];
4495
4496 u8 packet_headers_log[128][0x8];
4497
4498 u8 packet_syndrome[64][0x8];
4499};
4500
4501struct mlx5_ifc_get_dropped_packet_log_in_bits {
4502 u8 opcode[0x10];
4503 u8 reserved_0[0x10];
4504
4505 u8 reserved_1[0x10];
4506 u8 op_mod[0x10];
4507
4508 u8 reserved_2[0x40];
4509};
4510
4511struct mlx5_ifc_gen_eqe_in_bits {
4512 u8 opcode[0x10];
4513 u8 reserved_0[0x10];
4514
4515 u8 reserved_1[0x10];
4516 u8 op_mod[0x10];
4517
4518 u8 reserved_2[0x18];
4519 u8 eq_number[0x8];
4520
4521 u8 reserved_3[0x20];
4522
4523 u8 eqe[64][0x8];
4524};
4525
4526struct mlx5_ifc_gen_eq_out_bits {
4527 u8 status[0x8];
4528 u8 reserved_0[0x18];
4529
4530 u8 syndrome[0x20];
4531
4532 u8 reserved_1[0x40];
4533};
4534
4535struct mlx5_ifc_enable_hca_out_bits {
4536 u8 status[0x8];
4537 u8 reserved_0[0x18];
4538
4539 u8 syndrome[0x20];
4540
4541 u8 reserved_1[0x20];
4542};
4543
4544struct mlx5_ifc_enable_hca_in_bits {
4545 u8 opcode[0x10];
4546 u8 reserved_0[0x10];
4547
4548 u8 reserved_1[0x10];
4549 u8 op_mod[0x10];
4550
4551 u8 reserved_2[0x10];
4552 u8 function_id[0x10];
4553
4554 u8 reserved_3[0x20];
4555};
4556
4557struct mlx5_ifc_drain_dct_out_bits {
4558 u8 status[0x8];
4559 u8 reserved_0[0x18];
4560
4561 u8 syndrome[0x20];
4562
4563 u8 reserved_1[0x40];
4564};
4565
4566struct mlx5_ifc_drain_dct_in_bits {
4567 u8 opcode[0x10];
4568 u8 reserved_0[0x10];
4569
4570 u8 reserved_1[0x10];
4571 u8 op_mod[0x10];
4572
4573 u8 reserved_2[0x8];
4574 u8 dctn[0x18];
4575
4576 u8 reserved_3[0x20];
4577};
4578
4579struct mlx5_ifc_disable_hca_out_bits {
4580 u8 status[0x8];
4581 u8 reserved_0[0x18];
4582
4583 u8 syndrome[0x20];
4584
4585 u8 reserved_1[0x20];
4586};
4587
4588struct mlx5_ifc_disable_hca_in_bits {
4589 u8 opcode[0x10];
4590 u8 reserved_0[0x10];
4591
4592 u8 reserved_1[0x10];
4593 u8 op_mod[0x10];
4594
4595 u8 reserved_2[0x10];
4596 u8 function_id[0x10];
4597
4598 u8 reserved_3[0x20];
4599};
4600
4601struct mlx5_ifc_detach_from_mcg_out_bits {
4602 u8 status[0x8];
4603 u8 reserved_0[0x18];
4604
4605 u8 syndrome[0x20];
4606
4607 u8 reserved_1[0x40];
4608};
4609
4610struct mlx5_ifc_detach_from_mcg_in_bits {
4611 u8 opcode[0x10];
4612 u8 reserved_0[0x10];
4613
4614 u8 reserved_1[0x10];
4615 u8 op_mod[0x10];
4616
4617 u8 reserved_2[0x8];
4618 u8 qpn[0x18];
4619
4620 u8 reserved_3[0x20];
4621
4622 u8 multicast_gid[16][0x8];
4623};
4624
4625struct mlx5_ifc_destroy_xrc_srq_out_bits {
4626 u8 status[0x8];
4627 u8 reserved_0[0x18];
4628
4629 u8 syndrome[0x20];
4630
4631 u8 reserved_1[0x40];
4632};
4633
4634struct mlx5_ifc_destroy_xrc_srq_in_bits {
4635 u8 opcode[0x10];
4636 u8 reserved_0[0x10];
4637
4638 u8 reserved_1[0x10];
4639 u8 op_mod[0x10];
4640
4641 u8 reserved_2[0x8];
4642 u8 xrc_srqn[0x18];
4643
4644 u8 reserved_3[0x20];
4645};
4646
4647struct mlx5_ifc_destroy_tis_out_bits {
4648 u8 status[0x8];
4649 u8 reserved_0[0x18];
4650
4651 u8 syndrome[0x20];
4652
4653 u8 reserved_1[0x40];
4654};
4655
4656struct mlx5_ifc_destroy_tis_in_bits {
4657 u8 opcode[0x10];
4658 u8 reserved_0[0x10];
4659
4660 u8 reserved_1[0x10];
4661 u8 op_mod[0x10];
4662
4663 u8 reserved_2[0x8];
4664 u8 tisn[0x18];
4665
4666 u8 reserved_3[0x20];
4667};
4668
4669struct mlx5_ifc_destroy_tir_out_bits {
4670 u8 status[0x8];
4671 u8 reserved_0[0x18];
4672
4673 u8 syndrome[0x20];
4674
4675 u8 reserved_1[0x40];
4676};
4677
4678struct mlx5_ifc_destroy_tir_in_bits {
4679 u8 opcode[0x10];
4680 u8 reserved_0[0x10];
4681
4682 u8 reserved_1[0x10];
4683 u8 op_mod[0x10];
4684
4685 u8 reserved_2[0x8];
4686 u8 tirn[0x18];
4687
4688 u8 reserved_3[0x20];
4689};
4690
4691struct mlx5_ifc_destroy_srq_out_bits {
4692 u8 status[0x8];
4693 u8 reserved_0[0x18];
4694
4695 u8 syndrome[0x20];
4696
4697 u8 reserved_1[0x40];
4698};
4699
4700struct mlx5_ifc_destroy_srq_in_bits {
4701 u8 opcode[0x10];
4702 u8 reserved_0[0x10];
4703
4704 u8 reserved_1[0x10];
4705 u8 op_mod[0x10];
4706
4707 u8 reserved_2[0x8];
4708 u8 srqn[0x18];
4709
4710 u8 reserved_3[0x20];
4711};
4712
4713struct mlx5_ifc_destroy_sq_out_bits {
4714 u8 status[0x8];
4715 u8 reserved_0[0x18];
4716
4717 u8 syndrome[0x20];
4718
4719 u8 reserved_1[0x40];
4720};
4721
4722struct mlx5_ifc_destroy_sq_in_bits {
4723 u8 opcode[0x10];
4724 u8 reserved_0[0x10];
4725
4726 u8 reserved_1[0x10];
4727 u8 op_mod[0x10];
4728
4729 u8 reserved_2[0x8];
4730 u8 sqn[0x18];
4731
4732 u8 reserved_3[0x20];
4733};
4734
4735struct mlx5_ifc_destroy_rqt_out_bits {
4736 u8 status[0x8];
4737 u8 reserved_0[0x18];
4738
4739 u8 syndrome[0x20];
4740
4741 u8 reserved_1[0x40];
4742};
4743
4744struct mlx5_ifc_destroy_rqt_in_bits {
4745 u8 opcode[0x10];
4746 u8 reserved_0[0x10];
4747
4748 u8 reserved_1[0x10];
4749 u8 op_mod[0x10];
4750
4751 u8 reserved_2[0x8];
4752 u8 rqtn[0x18];
4753
4754 u8 reserved_3[0x20];
4755};
4756
4757struct mlx5_ifc_destroy_rq_out_bits {
4758 u8 status[0x8];
4759 u8 reserved_0[0x18];
4760
4761 u8 syndrome[0x20];
4762
4763 u8 reserved_1[0x40];
4764};
4765
4766struct mlx5_ifc_destroy_rq_in_bits {
4767 u8 opcode[0x10];
4768 u8 reserved_0[0x10];
4769
4770 u8 reserved_1[0x10];
4771 u8 op_mod[0x10];
4772
4773 u8 reserved_2[0x8];
4774 u8 rqn[0x18];
4775
4776 u8 reserved_3[0x20];
4777};
4778
4779struct mlx5_ifc_destroy_rmp_out_bits {
4780 u8 status[0x8];
4781 u8 reserved_0[0x18];
4782
4783 u8 syndrome[0x20];
4784
4785 u8 reserved_1[0x40];
4786};
4787
4788struct mlx5_ifc_destroy_rmp_in_bits {
4789 u8 opcode[0x10];
4790 u8 reserved_0[0x10];
4791
4792 u8 reserved_1[0x10];
4793 u8 op_mod[0x10];
4794
4795 u8 reserved_2[0x8];
4796 u8 rmpn[0x18];
4797
4798 u8 reserved_3[0x20];
4799};
4800
4801struct mlx5_ifc_destroy_qp_out_bits {
4802 u8 status[0x8];
4803 u8 reserved_0[0x18];
4804
4805 u8 syndrome[0x20];
4806
4807 u8 reserved_1[0x40];
4808};
4809
4810struct mlx5_ifc_destroy_qp_in_bits {
4811 u8 opcode[0x10];
4812 u8 reserved_0[0x10];
4813
4814 u8 reserved_1[0x10];
4815 u8 op_mod[0x10];
4816
4817 u8 reserved_2[0x8];
4818 u8 qpn[0x18];
4819
4820 u8 reserved_3[0x20];
4821};
4822
4823struct mlx5_ifc_destroy_psv_out_bits {
4824 u8 status[0x8];
4825 u8 reserved_0[0x18];
4826
4827 u8 syndrome[0x20];
4828
4829 u8 reserved_1[0x40];
4830};
4831
4832struct mlx5_ifc_destroy_psv_in_bits {
4833 u8 opcode[0x10];
4834 u8 reserved_0[0x10];
4835
4836 u8 reserved_1[0x10];
4837 u8 op_mod[0x10];
4838
4839 u8 reserved_2[0x8];
4840 u8 psvn[0x18];
4841
4842 u8 reserved_3[0x20];
4843};
4844
4845struct mlx5_ifc_destroy_mkey_out_bits {
4846 u8 status[0x8];
4847 u8 reserved_0[0x18];
4848
4849 u8 syndrome[0x20];
4850
4851 u8 reserved_1[0x40];
4852};
4853
4854struct mlx5_ifc_destroy_mkey_in_bits {
4855 u8 opcode[0x10];
4856 u8 reserved_0[0x10];
4857
4858 u8 reserved_1[0x10];
4859 u8 op_mod[0x10];
4860
4861 u8 reserved_2[0x8];
4862 u8 mkey_index[0x18];
4863
4864 u8 reserved_3[0x20];
4865};
4866
4867struct mlx5_ifc_destroy_flow_table_out_bits {
4868 u8 status[0x8];
4869 u8 reserved_0[0x18];
4870
4871 u8 syndrome[0x20];
4872
4873 u8 reserved_1[0x40];
4874};
4875
4876struct mlx5_ifc_destroy_flow_table_in_bits {
4877 u8 opcode[0x10];
4878 u8 reserved_0[0x10];
4879
4880 u8 reserved_1[0x10];
4881 u8 op_mod[0x10];
4882
4883 u8 reserved_2[0x40];
4884
4885 u8 table_type[0x8];
4886 u8 reserved_3[0x18];
4887
4888 u8 reserved_4[0x8];
4889 u8 table_id[0x18];
4890
4891 u8 reserved_5[0x140];
4892};
4893
4894struct mlx5_ifc_destroy_flow_group_out_bits {
4895 u8 status[0x8];
4896 u8 reserved_0[0x18];
4897
4898 u8 syndrome[0x20];
4899
4900 u8 reserved_1[0x40];
4901};
4902
4903struct mlx5_ifc_destroy_flow_group_in_bits {
4904 u8 opcode[0x10];
4905 u8 reserved_0[0x10];
4906
4907 u8 reserved_1[0x10];
4908 u8 op_mod[0x10];
4909
4910 u8 reserved_2[0x40];
4911
4912 u8 table_type[0x8];
4913 u8 reserved_3[0x18];
4914
4915 u8 reserved_4[0x8];
4916 u8 table_id[0x18];
4917
4918 u8 group_id[0x20];
4919
4920 u8 reserved_5[0x120];
4921};
4922
4923struct mlx5_ifc_destroy_eq_out_bits {
4924 u8 status[0x8];
4925 u8 reserved_0[0x18];
4926
4927 u8 syndrome[0x20];
4928
4929 u8 reserved_1[0x40];
4930};
4931
4932struct mlx5_ifc_destroy_eq_in_bits {
4933 u8 opcode[0x10];
4934 u8 reserved_0[0x10];
4935
4936 u8 reserved_1[0x10];
4937 u8 op_mod[0x10];
4938
4939 u8 reserved_2[0x18];
4940 u8 eq_number[0x8];
4941
4942 u8 reserved_3[0x20];
4943};
4944
4945struct mlx5_ifc_destroy_dct_out_bits {
4946 u8 status[0x8];
4947 u8 reserved_0[0x18];
4948
4949 u8 syndrome[0x20];
4950
4951 u8 reserved_1[0x40];
4952};
4953
4954struct mlx5_ifc_destroy_dct_in_bits {
4955 u8 opcode[0x10];
4956 u8 reserved_0[0x10];
4957
4958 u8 reserved_1[0x10];
4959 u8 op_mod[0x10];
4960
4961 u8 reserved_2[0x8];
4962 u8 dctn[0x18];
4963
4964 u8 reserved_3[0x20];
4965};
4966
4967struct mlx5_ifc_destroy_cq_out_bits {
4968 u8 status[0x8];
4969 u8 reserved_0[0x18];
4970
4971 u8 syndrome[0x20];
4972
4973 u8 reserved_1[0x40];
4974};
4975
4976struct mlx5_ifc_destroy_cq_in_bits {
4977 u8 opcode[0x10];
4978 u8 reserved_0[0x10];
4979
4980 u8 reserved_1[0x10];
4981 u8 op_mod[0x10];
4982
4983 u8 reserved_2[0x8];
4984 u8 cqn[0x18];
4985
4986 u8 reserved_3[0x20];
4987};
4988
4989struct mlx5_ifc_delete_vxlan_udp_dport_out_bits {
4990 u8 status[0x8];
4991 u8 reserved_0[0x18];
4992
4993 u8 syndrome[0x20];
4994
4995 u8 reserved_1[0x40];
4996};
4997
4998struct mlx5_ifc_delete_vxlan_udp_dport_in_bits {
4999 u8 opcode[0x10];
5000 u8 reserved_0[0x10];
5001
5002 u8 reserved_1[0x10];
5003 u8 op_mod[0x10];
5004
5005 u8 reserved_2[0x20];
5006
5007 u8 reserved_3[0x10];
5008 u8 vxlan_udp_port[0x10];
5009};
5010
5011struct mlx5_ifc_delete_l2_table_entry_out_bits {
5012 u8 status[0x8];
5013 u8 reserved_0[0x18];
5014
5015 u8 syndrome[0x20];
5016
5017 u8 reserved_1[0x40];
5018};
5019
5020struct mlx5_ifc_delete_l2_table_entry_in_bits {
5021 u8 opcode[0x10];
5022 u8 reserved_0[0x10];
5023
5024 u8 reserved_1[0x10];
5025 u8 op_mod[0x10];
5026
5027 u8 reserved_2[0x60];
5028
5029 u8 reserved_3[0x8];
5030 u8 table_index[0x18];
5031
5032 u8 reserved_4[0x140];
5033};
5034
5035struct mlx5_ifc_delete_fte_out_bits {
5036 u8 status[0x8];
5037 u8 reserved_0[0x18];
5038
5039 u8 syndrome[0x20];
5040
5041 u8 reserved_1[0x40];
5042};
5043
5044struct mlx5_ifc_delete_fte_in_bits {
5045 u8 opcode[0x10];
5046 u8 reserved_0[0x10];
5047
5048 u8 reserved_1[0x10];
5049 u8 op_mod[0x10];
5050
5051 u8 reserved_2[0x40];
5052
5053 u8 table_type[0x8];
5054 u8 reserved_3[0x18];
5055
5056 u8 reserved_4[0x8];
5057 u8 table_id[0x18];
5058
5059 u8 reserved_5[0x40];
5060
5061 u8 flow_index[0x20];
5062
5063 u8 reserved_6[0xe0];
5064};
5065
5066struct mlx5_ifc_dealloc_xrcd_out_bits {
5067 u8 status[0x8];
5068 u8 reserved_0[0x18];
5069
5070 u8 syndrome[0x20];
5071
5072 u8 reserved_1[0x40];
5073};
5074
5075struct mlx5_ifc_dealloc_xrcd_in_bits {
5076 u8 opcode[0x10];
5077 u8 reserved_0[0x10];
5078
5079 u8 reserved_1[0x10];
5080 u8 op_mod[0x10];
5081
5082 u8 reserved_2[0x8];
5083 u8 xrcd[0x18];
5084
5085 u8 reserved_3[0x20];
5086};
5087
5088struct mlx5_ifc_dealloc_uar_out_bits {
5089 u8 status[0x8];
5090 u8 reserved_0[0x18];
5091
5092 u8 syndrome[0x20];
5093
5094 u8 reserved_1[0x40];
5095};
5096
5097struct mlx5_ifc_dealloc_uar_in_bits {
5098 u8 opcode[0x10];
5099 u8 reserved_0[0x10];
5100
5101 u8 reserved_1[0x10];
5102 u8 op_mod[0x10];
5103
5104 u8 reserved_2[0x8];
5105 u8 uar[0x18];
5106
5107 u8 reserved_3[0x20];
5108};
5109
5110struct mlx5_ifc_dealloc_transport_domain_out_bits {
5111 u8 status[0x8];
5112 u8 reserved_0[0x18];
5113
5114 u8 syndrome[0x20];
5115
5116 u8 reserved_1[0x40];
5117};
5118
5119struct mlx5_ifc_dealloc_transport_domain_in_bits {
5120 u8 opcode[0x10];
5121 u8 reserved_0[0x10];
5122
5123 u8 reserved_1[0x10];
5124 u8 op_mod[0x10];
5125
5126 u8 reserved_2[0x8];
5127 u8 transport_domain[0x18];
5128
5129 u8 reserved_3[0x20];
5130};
5131
5132struct mlx5_ifc_dealloc_q_counter_out_bits {
5133 u8 status[0x8];
5134 u8 reserved_0[0x18];
5135
5136 u8 syndrome[0x20];
5137
5138 u8 reserved_1[0x40];
5139};
5140
5141struct mlx5_ifc_dealloc_q_counter_in_bits {
5142 u8 opcode[0x10];
5143 u8 reserved_0[0x10];
5144
5145 u8 reserved_1[0x10];
5146 u8 op_mod[0x10];
5147
5148 u8 reserved_2[0x18];
5149 u8 counter_set_id[0x8];
5150
5151 u8 reserved_3[0x20];
5152};
5153
5154struct mlx5_ifc_dealloc_pd_out_bits {
5155 u8 status[0x8];
5156 u8 reserved_0[0x18];
5157
5158 u8 syndrome[0x20];
5159
5160 u8 reserved_1[0x40];
5161};
5162
5163struct mlx5_ifc_dealloc_pd_in_bits {
5164 u8 opcode[0x10];
5165 u8 reserved_0[0x10];
5166
5167 u8 reserved_1[0x10];
5168 u8 op_mod[0x10];
5169
5170 u8 reserved_2[0x8];
5171 u8 pd[0x18];
5172
5173 u8 reserved_3[0x20];
5174};
5175
5176struct mlx5_ifc_create_xrc_srq_out_bits {
5177 u8 status[0x8];
5178 u8 reserved_0[0x18];
5179
5180 u8 syndrome[0x20];
5181
5182 u8 reserved_1[0x8];
5183 u8 xrc_srqn[0x18];
5184
5185 u8 reserved_2[0x20];
5186};
5187
5188struct mlx5_ifc_create_xrc_srq_in_bits {
5189 u8 opcode[0x10];
5190 u8 reserved_0[0x10];
5191
5192 u8 reserved_1[0x10];
5193 u8 op_mod[0x10];
5194
5195 u8 reserved_2[0x40];
5196
5197 struct mlx5_ifc_xrc_srqc_bits xrc_srq_context_entry;
5198
5199 u8 reserved_3[0x600];
5200
5201 u8 pas[0][0x40];
5202};
5203
5204struct mlx5_ifc_create_tis_out_bits {
5205 u8 status[0x8];
5206 u8 reserved_0[0x18];
5207
5208 u8 syndrome[0x20];
5209
5210 u8 reserved_1[0x8];
5211 u8 tisn[0x18];
5212
5213 u8 reserved_2[0x20];
5214};
5215
5216struct mlx5_ifc_create_tis_in_bits {
5217 u8 opcode[0x10];
5218 u8 reserved_0[0x10];
5219
5220 u8 reserved_1[0x10];
5221 u8 op_mod[0x10];
5222
5223 u8 reserved_2[0xc0];
5224
5225 struct mlx5_ifc_tisc_bits ctx;
5226};
5227
5228struct mlx5_ifc_create_tir_out_bits {
5229 u8 status[0x8];
5230 u8 reserved_0[0x18];
5231
5232 u8 syndrome[0x20];
5233
5234 u8 reserved_1[0x8];
5235 u8 tirn[0x18];
5236
5237 u8 reserved_2[0x20];
5238};
5239
5240struct mlx5_ifc_create_tir_in_bits {
5241 u8 opcode[0x10];
5242 u8 reserved_0[0x10];
5243
5244 u8 reserved_1[0x10];
5245 u8 op_mod[0x10];
5246
5247 u8 reserved_2[0xc0];
5248
5249 struct mlx5_ifc_tirc_bits ctx;
5250};
5251
5252struct mlx5_ifc_create_srq_out_bits {
5253 u8 status[0x8];
5254 u8 reserved_0[0x18];
5255
5256 u8 syndrome[0x20];
5257
5258 u8 reserved_1[0x8];
5259 u8 srqn[0x18];
5260
5261 u8 reserved_2[0x20];
5262};
5263
5264struct mlx5_ifc_create_srq_in_bits {
5265 u8 opcode[0x10];
5266 u8 reserved_0[0x10];
5267
5268 u8 reserved_1[0x10];
5269 u8 op_mod[0x10];
5270
5271 u8 reserved_2[0x40];
5272
5273 struct mlx5_ifc_srqc_bits srq_context_entry;
5274
5275 u8 reserved_3[0x600];
5276
5277 u8 pas[0][0x40];
5278};
5279
5280struct mlx5_ifc_create_sq_out_bits {
5281 u8 status[0x8];
5282 u8 reserved_0[0x18];
5283
5284 u8 syndrome[0x20];
5285
5286 u8 reserved_1[0x8];
5287 u8 sqn[0x18];
5288
5289 u8 reserved_2[0x20];
5290};
5291
5292struct mlx5_ifc_create_sq_in_bits {
5293 u8 opcode[0x10];
5294 u8 reserved_0[0x10];
5295
5296 u8 reserved_1[0x10];
5297 u8 op_mod[0x10];
5298
5299 u8 reserved_2[0xc0];
5300
5301 struct mlx5_ifc_sqc_bits ctx;
5302};
5303
5304struct mlx5_ifc_create_rqt_out_bits {
5305 u8 status[0x8];
5306 u8 reserved_0[0x18];
5307
5308 u8 syndrome[0x20];
5309
5310 u8 reserved_1[0x8];
5311 u8 rqtn[0x18];
5312
5313 u8 reserved_2[0x20];
5314};
5315
5316struct mlx5_ifc_create_rqt_in_bits {
5317 u8 opcode[0x10];
5318 u8 reserved_0[0x10];
5319
5320 u8 reserved_1[0x10];
5321 u8 op_mod[0x10];
5322
5323 u8 reserved_2[0xc0];
5324
5325 struct mlx5_ifc_rqtc_bits rqt_context;
5326};
5327
5328struct mlx5_ifc_create_rq_out_bits {
5329 u8 status[0x8];
5330 u8 reserved_0[0x18];
5331
5332 u8 syndrome[0x20];
5333
5334 u8 reserved_1[0x8];
5335 u8 rqn[0x18];
5336
5337 u8 reserved_2[0x20];
5338};
5339
5340struct mlx5_ifc_create_rq_in_bits {
5341 u8 opcode[0x10];
5342 u8 reserved_0[0x10];
5343
5344 u8 reserved_1[0x10];
5345 u8 op_mod[0x10];
5346
5347 u8 reserved_2[0xc0];
5348
5349 struct mlx5_ifc_rqc_bits ctx;
5350};
5351
5352struct mlx5_ifc_create_rmp_out_bits {
5353 u8 status[0x8];
5354 u8 reserved_0[0x18];
5355
5356 u8 syndrome[0x20];
5357
5358 u8 reserved_1[0x8];
5359 u8 rmpn[0x18];
5360
5361 u8 reserved_2[0x20];
5362};
5363
5364struct mlx5_ifc_create_rmp_in_bits {
5365 u8 opcode[0x10];
5366 u8 reserved_0[0x10];
5367
5368 u8 reserved_1[0x10];
5369 u8 op_mod[0x10];
5370
5371 u8 reserved_2[0xc0];
5372
5373 struct mlx5_ifc_rmpc_bits ctx;
5374};
5375
5376struct mlx5_ifc_create_qp_out_bits {
5377 u8 status[0x8];
5378 u8 reserved_0[0x18];
5379
5380 u8 syndrome[0x20];
5381
5382 u8 reserved_1[0x8];
5383 u8 qpn[0x18];
5384
5385 u8 reserved_2[0x20];
5386};
5387
5388struct mlx5_ifc_create_qp_in_bits {
5389 u8 opcode[0x10];
5390 u8 reserved_0[0x10];
5391
5392 u8 reserved_1[0x10];
5393 u8 op_mod[0x10];
5394
5395 u8 reserved_2[0x40];
5396
5397 u8 opt_param_mask[0x20];
5398
5399 u8 reserved_3[0x20];
5400
5401 struct mlx5_ifc_qpc_bits qpc;
5402
5403 u8 reserved_4[0x80];
5404
5405 u8 pas[0][0x40];
5406};
5407
5408struct mlx5_ifc_create_psv_out_bits {
5409 u8 status[0x8];
5410 u8 reserved_0[0x18];
5411
5412 u8 syndrome[0x20];
5413
5414 u8 reserved_1[0x40];
5415
5416 u8 reserved_2[0x8];
5417 u8 psv0_index[0x18];
5418
5419 u8 reserved_3[0x8];
5420 u8 psv1_index[0x18];
5421
5422 u8 reserved_4[0x8];
5423 u8 psv2_index[0x18];
5424
5425 u8 reserved_5[0x8];
5426 u8 psv3_index[0x18];
5427};
5428
5429struct mlx5_ifc_create_psv_in_bits {
5430 u8 opcode[0x10];
5431 u8 reserved_0[0x10];
5432
5433 u8 reserved_1[0x10];
5434 u8 op_mod[0x10];
5435
5436 u8 num_psv[0x4];
5437 u8 reserved_2[0x4];
5438 u8 pd[0x18];
5439
5440 u8 reserved_3[0x20];
5441};
5442
5443struct mlx5_ifc_create_mkey_out_bits {
5444 u8 status[0x8];
5445 u8 reserved_0[0x18];
5446
5447 u8 syndrome[0x20];
5448
5449 u8 reserved_1[0x8];
5450 u8 mkey_index[0x18];
5451
5452 u8 reserved_2[0x20];
5453};
5454
5455struct mlx5_ifc_create_mkey_in_bits {
5456 u8 opcode[0x10];
5457 u8 reserved_0[0x10];
5458
5459 u8 reserved_1[0x10];
5460 u8 op_mod[0x10];
5461
5462 u8 reserved_2[0x20];
5463
5464 u8 pg_access[0x1];
5465 u8 reserved_3[0x1f];
5466
5467 struct mlx5_ifc_mkc_bits memory_key_mkey_entry;
5468
5469 u8 reserved_4[0x80];
5470
5471 u8 translations_octword_actual_size[0x20];
5472
5473 u8 reserved_5[0x560];
5474
5475 u8 klm_pas_mtt[0][0x20];
5476};
5477
5478struct mlx5_ifc_create_flow_table_out_bits {
5479 u8 status[0x8];
5480 u8 reserved_0[0x18];
5481
5482 u8 syndrome[0x20];
5483
5484 u8 reserved_1[0x8];
5485 u8 table_id[0x18];
5486
5487 u8 reserved_2[0x20];
5488};
5489
5490struct mlx5_ifc_create_flow_table_in_bits {
5491 u8 opcode[0x10];
5492 u8 reserved_0[0x10];
5493
5494 u8 reserved_1[0x10];
5495 u8 op_mod[0x10];
5496
5497 u8 reserved_2[0x40];
5498
5499 u8 table_type[0x8];
5500 u8 reserved_3[0x18];
5501
5502 u8 reserved_4[0x20];
5503
5504 u8 reserved_5[0x8];
5505 u8 level[0x8];
5506 u8 reserved_6[0x8];
5507 u8 log_size[0x8];
5508
5509 u8 reserved_7[0x120];
5510};
5511
5512struct mlx5_ifc_create_flow_group_out_bits {
5513 u8 status[0x8];
5514 u8 reserved_0[0x18];
5515
5516 u8 syndrome[0x20];
5517
5518 u8 reserved_1[0x8];
5519 u8 group_id[0x18];
5520
5521 u8 reserved_2[0x20];
5522};
5523
5524enum {
5525 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_OUTER_HEADERS = 0x0,
5526 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_MISC_PARAMETERS = 0x1,
5527 MLX5_CREATE_FLOW_GROUP_IN_MATCH_CRITERIA_ENABLE_INNER_HEADERS = 0x2,
5528};
5529
5530struct mlx5_ifc_create_flow_group_in_bits {
5531 u8 opcode[0x10];
5532 u8 reserved_0[0x10];
5533
5534 u8 reserved_1[0x10];
5535 u8 op_mod[0x10];
5536
5537 u8 reserved_2[0x40];
5538
5539 u8 table_type[0x8];
5540 u8 reserved_3[0x18];
5541
5542 u8 reserved_4[0x8];
5543 u8 table_id[0x18];
5544
5545 u8 reserved_5[0x20];
5546
5547 u8 start_flow_index[0x20];
5548
5549 u8 reserved_6[0x20];
5550
5551 u8 end_flow_index[0x20];
5552
5553 u8 reserved_7[0xa0];
5554
5555 u8 reserved_8[0x18];
5556 u8 match_criteria_enable[0x8];
5557
5558 struct mlx5_ifc_fte_match_param_bits match_criteria;
5559
5560 u8 reserved_9[0xe00];
5561};
5562
5563struct mlx5_ifc_create_eq_out_bits {
5564 u8 status[0x8];
5565 u8 reserved_0[0x18];
5566
5567 u8 syndrome[0x20];
5568
5569 u8 reserved_1[0x18];
5570 u8 eq_number[0x8];
5571
5572 u8 reserved_2[0x20];
5573};
5574
5575struct mlx5_ifc_create_eq_in_bits {
5576 u8 opcode[0x10];
5577 u8 reserved_0[0x10];
5578
5579 u8 reserved_1[0x10];
5580 u8 op_mod[0x10];
5581
5582 u8 reserved_2[0x40];
5583
5584 struct mlx5_ifc_eqc_bits eq_context_entry;
5585
5586 u8 reserved_3[0x40];
5587
5588 u8 event_bitmask[0x40];
5589
5590 u8 reserved_4[0x580];
5591
5592 u8 pas[0][0x40];
5593};
5594
5595struct mlx5_ifc_create_dct_out_bits {
5596 u8 status[0x8];
5597 u8 reserved_0[0x18];
5598
5599 u8 syndrome[0x20];
5600
5601 u8 reserved_1[0x8];
5602 u8 dctn[0x18];
5603
5604 u8 reserved_2[0x20];
5605};
5606
5607struct mlx5_ifc_create_dct_in_bits {
5608 u8 opcode[0x10];
5609 u8 reserved_0[0x10];
5610
5611 u8 reserved_1[0x10];
5612 u8 op_mod[0x10];
5613
5614 u8 reserved_2[0x40];
5615
5616 struct mlx5_ifc_dctc_bits dct_context_entry;
5617
5618 u8 reserved_3[0x180];
5619};
5620
5621struct mlx5_ifc_create_cq_out_bits {
5622 u8 status[0x8];
5623 u8 reserved_0[0x18];
5624
5625 u8 syndrome[0x20];
5626
5627 u8 reserved_1[0x8];
5628 u8 cqn[0x18];
5629
5630 u8 reserved_2[0x20];
5631};
5632
5633struct mlx5_ifc_create_cq_in_bits {
5634 u8 opcode[0x10];
5635 u8 reserved_0[0x10];
5636
5637 u8 reserved_1[0x10];
5638 u8 op_mod[0x10];
5639
5640 u8 reserved_2[0x40];
5641
5642 struct mlx5_ifc_cqc_bits cq_context;
5643
5644 u8 reserved_3[0x600];
5645
5646 u8 pas[0][0x40];
5647};
5648
5649struct mlx5_ifc_config_int_moderation_out_bits {
5650 u8 status[0x8];
5651 u8 reserved_0[0x18];
5652
5653 u8 syndrome[0x20];
5654
5655 u8 reserved_1[0x4];
5656 u8 min_delay[0xc];
5657 u8 int_vector[0x10];
5658
5659 u8 reserved_2[0x20];
5660};
5661
5662enum {
5663 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_WRITE = 0x0,
5664 MLX5_CONFIG_INT_MODERATION_IN_OP_MOD_READ = 0x1,
5665};
5666
5667struct mlx5_ifc_config_int_moderation_in_bits {
5668 u8 opcode[0x10];
5669 u8 reserved_0[0x10];
5670
5671 u8 reserved_1[0x10];
5672 u8 op_mod[0x10];
5673
5674 u8 reserved_2[0x4];
5675 u8 min_delay[0xc];
5676 u8 int_vector[0x10];
5677
5678 u8 reserved_3[0x20];
5679};
5680
5681struct mlx5_ifc_attach_to_mcg_out_bits {
5682 u8 status[0x8];
5683 u8 reserved_0[0x18];
5684
5685 u8 syndrome[0x20];
5686
5687 u8 reserved_1[0x40];
5688};
5689
5690struct mlx5_ifc_attach_to_mcg_in_bits {
5691 u8 opcode[0x10];
5692 u8 reserved_0[0x10];
5693
5694 u8 reserved_1[0x10];
5695 u8 op_mod[0x10];
5696
5697 u8 reserved_2[0x8];
5698 u8 qpn[0x18];
5699
5700 u8 reserved_3[0x20];
5701
5702 u8 multicast_gid[16][0x8];
5703};
5704
5705struct mlx5_ifc_arm_xrc_srq_out_bits {
5706 u8 status[0x8];
5707 u8 reserved_0[0x18];
5708
5709 u8 syndrome[0x20];
5710
5711 u8 reserved_1[0x40];
5712};
5713
5714enum {
5715 MLX5_ARM_XRC_SRQ_IN_OP_MOD_XRC_SRQ = 0x1,
5716};
5717
5718struct mlx5_ifc_arm_xrc_srq_in_bits {
5719 u8 opcode[0x10];
5720 u8 reserved_0[0x10];
5721
5722 u8 reserved_1[0x10];
5723 u8 op_mod[0x10];
5724
5725 u8 reserved_2[0x8];
5726 u8 xrc_srqn[0x18];
5727
5728 u8 reserved_3[0x10];
5729 u8 lwm[0x10];
5730};
5731
5732struct mlx5_ifc_arm_rq_out_bits {
5733 u8 status[0x8];
5734 u8 reserved_0[0x18];
5735
5736 u8 syndrome[0x20];
5737
5738 u8 reserved_1[0x40];
5739};
5740
5741enum {
5742 MLX5_ARM_RQ_IN_OP_MOD_SRQ_ = 0x1,
5743};
5744
5745struct mlx5_ifc_arm_rq_in_bits {
5746 u8 opcode[0x10];
5747 u8 reserved_0[0x10];
5748
5749 u8 reserved_1[0x10];
5750 u8 op_mod[0x10];
5751
5752 u8 reserved_2[0x8];
5753 u8 srq_number[0x18];
5754
5755 u8 reserved_3[0x10];
5756 u8 lwm[0x10];
5757};
5758
5759struct mlx5_ifc_arm_dct_out_bits {
5760 u8 status[0x8];
5761 u8 reserved_0[0x18];
5762
5763 u8 syndrome[0x20];
5764
5765 u8 reserved_1[0x40];
5766};
5767
5768struct mlx5_ifc_arm_dct_in_bits {
5769 u8 opcode[0x10];
5770 u8 reserved_0[0x10];
5771
5772 u8 reserved_1[0x10];
5773 u8 op_mod[0x10];
5774
5775 u8 reserved_2[0x8];
5776 u8 dct_number[0x18];
5777
5778 u8 reserved_3[0x20];
5779};
5780
5781struct mlx5_ifc_alloc_xrcd_out_bits {
5782 u8 status[0x8];
5783 u8 reserved_0[0x18];
5784
5785 u8 syndrome[0x20];
5786
5787 u8 reserved_1[0x8];
5788 u8 xrcd[0x18];
5789
5790 u8 reserved_2[0x20];
5791};
5792
5793struct mlx5_ifc_alloc_xrcd_in_bits {
5794 u8 opcode[0x10];
5795 u8 reserved_0[0x10];
5796
5797 u8 reserved_1[0x10];
5798 u8 op_mod[0x10];
5799
5800 u8 reserved_2[0x40];
5801};
5802
5803struct mlx5_ifc_alloc_uar_out_bits {
5804 u8 status[0x8];
5805 u8 reserved_0[0x18];
5806
5807 u8 syndrome[0x20];
5808
5809 u8 reserved_1[0x8];
5810 u8 uar[0x18];
5811
5812 u8 reserved_2[0x20];
5813};
5814
5815struct mlx5_ifc_alloc_uar_in_bits {
5816 u8 opcode[0x10];
5817 u8 reserved_0[0x10];
5818
5819 u8 reserved_1[0x10];
5820 u8 op_mod[0x10];
5821
5822 u8 reserved_2[0x40];
5823};
5824
5825struct mlx5_ifc_alloc_transport_domain_out_bits {
5826 u8 status[0x8];
5827 u8 reserved_0[0x18];
5828
5829 u8 syndrome[0x20];
5830
5831 u8 reserved_1[0x8];
5832 u8 transport_domain[0x18];
5833
5834 u8 reserved_2[0x20];
5835};
5836
5837struct mlx5_ifc_alloc_transport_domain_in_bits {
5838 u8 opcode[0x10];
5839 u8 reserved_0[0x10];
5840
5841 u8 reserved_1[0x10];
5842 u8 op_mod[0x10];
5843
5844 u8 reserved_2[0x40];
5845};
5846
5847struct mlx5_ifc_alloc_q_counter_out_bits {
5848 u8 status[0x8];
5849 u8 reserved_0[0x18];
5850
5851 u8 syndrome[0x20];
5852
5853 u8 reserved_1[0x18];
5854 u8 counter_set_id[0x8];
5855
5856 u8 reserved_2[0x20];
5857};
5858
5859struct mlx5_ifc_alloc_q_counter_in_bits {
5860 u8 opcode[0x10];
5861 u8 reserved_0[0x10];
5862
5863 u8 reserved_1[0x10];
5864 u8 op_mod[0x10];
5865
5866 u8 reserved_2[0x40];
5867};
5868
5869struct mlx5_ifc_alloc_pd_out_bits {
5870 u8 status[0x8];
5871 u8 reserved_0[0x18];
5872
5873 u8 syndrome[0x20];
5874
5875 u8 reserved_1[0x8];
5876 u8 pd[0x18];
5877
5878 u8 reserved_2[0x20];
5879};
5880
5881struct mlx5_ifc_alloc_pd_in_bits {
5882 u8 opcode[0x10];
5883 u8 reserved_0[0x10];
5884
5885 u8 reserved_1[0x10];
5886 u8 op_mod[0x10];
5887
5888 u8 reserved_2[0x40];
5889};
5890
5891struct mlx5_ifc_add_vxlan_udp_dport_out_bits {
5892 u8 status[0x8];
5893 u8 reserved_0[0x18];
5894
5895 u8 syndrome[0x20];
5896
5897 u8 reserved_1[0x40];
5898};
5899
5900struct mlx5_ifc_add_vxlan_udp_dport_in_bits {
5901 u8 opcode[0x10];
5902 u8 reserved_0[0x10];
5903
5904 u8 reserved_1[0x10];
5905 u8 op_mod[0x10];
5906
5907 u8 reserved_2[0x20];
5908
5909 u8 reserved_3[0x10];
5910 u8 vxlan_udp_port[0x10];
5911};
5912
5913struct mlx5_ifc_access_register_out_bits {
5914 u8 status[0x8];
5915 u8 reserved_0[0x18];
5916
5917 u8 syndrome[0x20];
5918
5919 u8 reserved_1[0x40];
5920
5921 u8 register_data[0][0x20];
5922};
5923
5924enum {
5925 MLX5_ACCESS_REGISTER_IN_OP_MOD_WRITE = 0x0,
5926 MLX5_ACCESS_REGISTER_IN_OP_MOD_READ = 0x1,
5927};
5928
5929struct mlx5_ifc_access_register_in_bits {
5930 u8 opcode[0x10];
5931 u8 reserved_0[0x10];
5932
5933 u8 reserved_1[0x10];
5934 u8 op_mod[0x10];
5935
5936 u8 reserved_2[0x10];
5937 u8 register_id[0x10];
5938
5939 u8 argument[0x20];
5940
5941 u8 register_data[0][0x20];
5942};
5943
5944struct mlx5_ifc_sltp_reg_bits {
5945 u8 status[0x4];
5946 u8 version[0x4];
5947 u8 local_port[0x8];
5948 u8 pnat[0x2];
5949 u8 reserved_0[0x2];
5950 u8 lane[0x4];
5951 u8 reserved_1[0x8];
5952
5953 u8 reserved_2[0x20];
5954
5955 u8 reserved_3[0x7];
5956 u8 polarity[0x1];
5957 u8 ob_tap0[0x8];
5958 u8 ob_tap1[0x8];
5959 u8 ob_tap2[0x8];
5960
5961 u8 reserved_4[0xc];
5962 u8 ob_preemp_mode[0x4];
5963 u8 ob_reg[0x8];
5964 u8 ob_bias[0x8];
5965
5966 u8 reserved_5[0x20];
5967};
5968
5969struct mlx5_ifc_slrg_reg_bits {
5970 u8 status[0x4];
5971 u8 version[0x4];
5972 u8 local_port[0x8];
5973 u8 pnat[0x2];
5974 u8 reserved_0[0x2];
5975 u8 lane[0x4];
5976 u8 reserved_1[0x8];
5977
5978 u8 time_to_link_up[0x10];
5979 u8 reserved_2[0xc];
5980 u8 grade_lane_speed[0x4];
5981
5982 u8 grade_version[0x8];
5983 u8 grade[0x18];
5984
5985 u8 reserved_3[0x4];
5986 u8 height_grade_type[0x4];
5987 u8 height_grade[0x18];
5988
5989 u8 height_dz[0x10];
5990 u8 height_dv[0x10];
5991
5992 u8 reserved_4[0x10];
5993 u8 height_sigma[0x10];
5994
5995 u8 reserved_5[0x20];
5996
5997 u8 reserved_6[0x4];
5998 u8 phase_grade_type[0x4];
5999 u8 phase_grade[0x18];
6000
6001 u8 reserved_7[0x8];
6002 u8 phase_eo_pos[0x8];
6003 u8 reserved_8[0x8];
6004 u8 phase_eo_neg[0x8];
6005
6006 u8 ffe_set_tested[0x10];
6007 u8 test_errors_per_lane[0x10];
6008};
6009
6010struct mlx5_ifc_pvlc_reg_bits {
6011 u8 reserved_0[0x8];
6012 u8 local_port[0x8];
6013 u8 reserved_1[0x10];
6014
6015 u8 reserved_2[0x1c];
6016 u8 vl_hw_cap[0x4];
6017
6018 u8 reserved_3[0x1c];
6019 u8 vl_admin[0x4];
6020
6021 u8 reserved_4[0x1c];
6022 u8 vl_operational[0x4];
6023};
6024
6025struct mlx5_ifc_pude_reg_bits {
6026 u8 swid[0x8];
6027 u8 local_port[0x8];
6028 u8 reserved_0[0x4];
6029 u8 admin_status[0x4];
6030 u8 reserved_1[0x4];
6031 u8 oper_status[0x4];
6032
6033 u8 reserved_2[0x60];
6034};
6035
6036struct mlx5_ifc_ptys_reg_bits {
6037 u8 reserved_0[0x8];
6038 u8 local_port[0x8];
6039 u8 reserved_1[0xd];
6040 u8 proto_mask[0x3];
6041
6042 u8 reserved_2[0x40];
6043
6044 u8 eth_proto_capability[0x20];
6045
6046 u8 ib_link_width_capability[0x10];
6047 u8 ib_proto_capability[0x10];
6048
6049 u8 reserved_3[0x20];
6050
6051 u8 eth_proto_admin[0x20];
6052
6053 u8 ib_link_width_admin[0x10];
6054 u8 ib_proto_admin[0x10];
6055
6056 u8 reserved_4[0x20];
6057
6058 u8 eth_proto_oper[0x20];
6059
6060 u8 ib_link_width_oper[0x10];
6061 u8 ib_proto_oper[0x10];
6062
6063 u8 reserved_5[0x20];
6064
6065 u8 eth_proto_lp_advertise[0x20];
6066
6067 u8 reserved_6[0x60];
6068};
6069
6070struct mlx5_ifc_ptas_reg_bits {
6071 u8 reserved_0[0x20];
6072
6073 u8 algorithm_options[0x10];
6074 u8 reserved_1[0x4];
6075 u8 repetitions_mode[0x4];
6076 u8 num_of_repetitions[0x8];
6077
6078 u8 grade_version[0x8];
6079 u8 height_grade_type[0x4];
6080 u8 phase_grade_type[0x4];
6081 u8 height_grade_weight[0x8];
6082 u8 phase_grade_weight[0x8];
6083
6084 u8 gisim_measure_bits[0x10];
6085 u8 adaptive_tap_measure_bits[0x10];
6086
6087 u8 ber_bath_high_error_threshold[0x10];
6088 u8 ber_bath_mid_error_threshold[0x10];
6089
6090 u8 ber_bath_low_error_threshold[0x10];
6091 u8 one_ratio_high_threshold[0x10];
6092
6093 u8 one_ratio_high_mid_threshold[0x10];
6094 u8 one_ratio_low_mid_threshold[0x10];
6095
6096 u8 one_ratio_low_threshold[0x10];
6097 u8 ndeo_error_threshold[0x10];
6098
6099 u8 mixer_offset_step_size[0x10];
6100 u8 reserved_2[0x8];
6101 u8 mix90_phase_for_voltage_bath[0x8];
6102
6103 u8 mixer_offset_start[0x10];
6104 u8 mixer_offset_end[0x10];
6105
6106 u8 reserved_3[0x15];
6107 u8 ber_test_time[0xb];
6108};
6109
6110struct mlx5_ifc_pspa_reg_bits {
6111 u8 swid[0x8];
6112 u8 local_port[0x8];
6113 u8 sub_port[0x8];
6114 u8 reserved_0[0x8];
6115
6116 u8 reserved_1[0x20];
6117};
6118
6119struct mlx5_ifc_pqdr_reg_bits {
6120 u8 reserved_0[0x8];
6121 u8 local_port[0x8];
6122 u8 reserved_1[0x5];
6123 u8 prio[0x3];
6124 u8 reserved_2[0x6];
6125 u8 mode[0x2];
6126
6127 u8 reserved_3[0x20];
6128
6129 u8 reserved_4[0x10];
6130 u8 min_threshold[0x10];
6131
6132 u8 reserved_5[0x10];
6133 u8 max_threshold[0x10];
6134
6135 u8 reserved_6[0x10];
6136 u8 mark_probability_denominator[0x10];
6137
6138 u8 reserved_7[0x60];
6139};
6140
6141struct mlx5_ifc_ppsc_reg_bits {
6142 u8 reserved_0[0x8];
6143 u8 local_port[0x8];
6144 u8 reserved_1[0x10];
6145
6146 u8 reserved_2[0x60];
6147
6148 u8 reserved_3[0x1c];
6149 u8 wrps_admin[0x4];
6150
6151 u8 reserved_4[0x1c];
6152 u8 wrps_status[0x4];
6153
6154 u8 reserved_5[0x8];
6155 u8 up_threshold[0x8];
6156 u8 reserved_6[0x8];
6157 u8 down_threshold[0x8];
6158
6159 u8 reserved_7[0x20];
6160
6161 u8 reserved_8[0x1c];
6162 u8 srps_admin[0x4];
6163
6164 u8 reserved_9[0x1c];
6165 u8 srps_status[0x4];
6166
6167 u8 reserved_10[0x40];
6168};
6169
6170struct mlx5_ifc_pplr_reg_bits {
6171 u8 reserved_0[0x8];
6172 u8 local_port[0x8];
6173 u8 reserved_1[0x10];
6174
6175 u8 reserved_2[0x8];
6176 u8 lb_cap[0x8];
6177 u8 reserved_3[0x8];
6178 u8 lb_en[0x8];
6179};
6180
6181struct mlx5_ifc_pplm_reg_bits {
6182 u8 reserved_0[0x8];
6183 u8 local_port[0x8];
6184 u8 reserved_1[0x10];
6185
6186 u8 reserved_2[0x20];
6187
6188 u8 port_profile_mode[0x8];
6189 u8 static_port_profile[0x8];
6190 u8 active_port_profile[0x8];
6191 u8 reserved_3[0x8];
6192
6193 u8 retransmission_active[0x8];
6194 u8 fec_mode_active[0x18];
6195
6196 u8 reserved_4[0x20];
6197};
6198
6199struct mlx5_ifc_ppcnt_reg_bits {
6200 u8 swid[0x8];
6201 u8 local_port[0x8];
6202 u8 pnat[0x2];
6203 u8 reserved_0[0x8];
6204 u8 grp[0x6];
6205
6206 u8 clr[0x1];
6207 u8 reserved_1[0x1c];
6208 u8 prio_tc[0x3];
6209
6210 union mlx5_ifc_eth_cntrs_grp_data_layout_auto_bits counter_set;
6211};
6212
6213struct mlx5_ifc_ppad_reg_bits {
6214 u8 reserved_0[0x3];
6215 u8 single_mac[0x1];
6216 u8 reserved_1[0x4];
6217 u8 local_port[0x8];
6218 u8 mac_47_32[0x10];
6219
6220 u8 mac_31_0[0x20];
6221
6222 u8 reserved_2[0x40];
6223};
6224
6225struct mlx5_ifc_pmtu_reg_bits {
6226 u8 reserved_0[0x8];
6227 u8 local_port[0x8];
6228 u8 reserved_1[0x10];
6229
6230 u8 max_mtu[0x10];
6231 u8 reserved_2[0x10];
6232
6233 u8 admin_mtu[0x10];
6234 u8 reserved_3[0x10];
6235
6236 u8 oper_mtu[0x10];
6237 u8 reserved_4[0x10];
6238};
6239
6240struct mlx5_ifc_pmpr_reg_bits {
6241 u8 reserved_0[0x8];
6242 u8 module[0x8];
6243 u8 reserved_1[0x10];
6244
6245 u8 reserved_2[0x18];
6246 u8 attenuation_5g[0x8];
6247
6248 u8 reserved_3[0x18];
6249 u8 attenuation_7g[0x8];
6250
6251 u8 reserved_4[0x18];
6252 u8 attenuation_12g[0x8];
6253};
6254
6255struct mlx5_ifc_pmpe_reg_bits {
6256 u8 reserved_0[0x8];
6257 u8 module[0x8];
6258 u8 reserved_1[0xc];
6259 u8 module_status[0x4];
6260
6261 u8 reserved_2[0x60];
6262};
6263
6264struct mlx5_ifc_pmpc_reg_bits {
6265 u8 module_state_updated[32][0x8];
6266};
6267
6268struct mlx5_ifc_pmlpn_reg_bits {
6269 u8 reserved_0[0x4];
6270 u8 mlpn_status[0x4];
6271 u8 local_port[0x8];
6272 u8 reserved_1[0x10];
6273
6274 u8 e[0x1];
6275 u8 reserved_2[0x1f];
6276};
6277
6278struct mlx5_ifc_pmlp_reg_bits {
6279 u8 rxtx[0x1];
6280 u8 reserved_0[0x7];
6281 u8 local_port[0x8];
6282 u8 reserved_1[0x8];
6283 u8 width[0x8];
6284
6285 u8 lane0_module_mapping[0x20];
6286
6287 u8 lane1_module_mapping[0x20];
6288
6289 u8 lane2_module_mapping[0x20];
6290
6291 u8 lane3_module_mapping[0x20];
6292
6293 u8 reserved_2[0x160];
6294};
6295
6296struct mlx5_ifc_pmaos_reg_bits {
6297 u8 reserved_0[0x8];
6298 u8 module[0x8];
6299 u8 reserved_1[0x4];
6300 u8 admin_status[0x4];
6301 u8 reserved_2[0x4];
6302 u8 oper_status[0x4];
6303
6304 u8 ase[0x1];
6305 u8 ee[0x1];
6306 u8 reserved_3[0x1c];
6307 u8 e[0x2];
6308
6309 u8 reserved_4[0x40];
6310};
6311
6312struct mlx5_ifc_plpc_reg_bits {
6313 u8 reserved_0[0x4];
6314 u8 profile_id[0xc];
6315 u8 reserved_1[0x4];
6316 u8 proto_mask[0x4];
6317 u8 reserved_2[0x8];
6318
6319 u8 reserved_3[0x10];
6320 u8 lane_speed[0x10];
6321
6322 u8 reserved_4[0x17];
6323 u8 lpbf[0x1];
6324 u8 fec_mode_policy[0x8];
6325
6326 u8 retransmission_capability[0x8];
6327 u8 fec_mode_capability[0x18];
6328
6329 u8 retransmission_support_admin[0x8];
6330 u8 fec_mode_support_admin[0x18];
6331
6332 u8 retransmission_request_admin[0x8];
6333 u8 fec_mode_request_admin[0x18];
6334
6335 u8 reserved_5[0x80];
6336};
6337
6338struct mlx5_ifc_plib_reg_bits {
6339 u8 reserved_0[0x8];
6340 u8 local_port[0x8];
6341 u8 reserved_1[0x8];
6342 u8 ib_port[0x8];
6343
6344 u8 reserved_2[0x60];
6345};
6346
6347struct mlx5_ifc_plbf_reg_bits {
6348 u8 reserved_0[0x8];
6349 u8 local_port[0x8];
6350 u8 reserved_1[0xd];
6351 u8 lbf_mode[0x3];
6352
6353 u8 reserved_2[0x20];
6354};
6355
6356struct mlx5_ifc_pipg_reg_bits {
6357 u8 reserved_0[0x8];
6358 u8 local_port[0x8];
6359 u8 reserved_1[0x10];
6360
6361 u8 dic[0x1];
6362 u8 reserved_2[0x19];
6363 u8 ipg[0x4];
6364 u8 reserved_3[0x2];
6365};
6366
6367struct mlx5_ifc_pifr_reg_bits {
6368 u8 reserved_0[0x8];
6369 u8 local_port[0x8];
6370 u8 reserved_1[0x10];
6371
6372 u8 reserved_2[0xe0];
6373
6374 u8 port_filter[8][0x20];
6375
6376 u8 port_filter_update_en[8][0x20];
6377};
6378
6379struct mlx5_ifc_pfcc_reg_bits {
6380 u8 reserved_0[0x8];
6381 u8 local_port[0x8];
6382 u8 reserved_1[0x10];
6383
6384 u8 ppan[0x4];
6385 u8 reserved_2[0x4];
6386 u8 prio_mask_tx[0x8];
6387 u8 reserved_3[0x8];
6388 u8 prio_mask_rx[0x8];
6389
6390 u8 pptx[0x1];
6391 u8 aptx[0x1];
6392 u8 reserved_4[0x6];
6393 u8 pfctx[0x8];
6394 u8 reserved_5[0x10];
6395
6396 u8 pprx[0x1];
6397 u8 aprx[0x1];
6398 u8 reserved_6[0x6];
6399 u8 pfcrx[0x8];
6400 u8 reserved_7[0x10];
6401
6402 u8 reserved_8[0x80];
6403};
6404
6405struct mlx5_ifc_pelc_reg_bits {
6406 u8 op[0x4];
6407 u8 reserved_0[0x4];
6408 u8 local_port[0x8];
6409 u8 reserved_1[0x10];
6410
6411 u8 op_admin[0x8];
6412 u8 op_capability[0x8];
6413 u8 op_request[0x8];
6414 u8 op_active[0x8];
6415
6416 u8 admin[0x40];
6417
6418 u8 capability[0x40];
6419
6420 u8 request[0x40];
6421
6422 u8 active[0x40];
6423
6424 u8 reserved_2[0x80];
6425};
6426
6427struct mlx5_ifc_peir_reg_bits {
6428 u8 reserved_0[0x8];
6429 u8 local_port[0x8];
6430 u8 reserved_1[0x10];
6431
6432 u8 reserved_2[0xc];
6433 u8 error_count[0x4];
6434 u8 reserved_3[0x10];
6435
6436 u8 reserved_4[0xc];
6437 u8 lane[0x4];
6438 u8 reserved_5[0x8];
6439 u8 error_type[0x8];
6440};
6441
6442struct mlx5_ifc_pcap_reg_bits {
6443 u8 reserved_0[0x8];
6444 u8 local_port[0x8];
6445 u8 reserved_1[0x10];
6446
6447 u8 port_capability_mask[4][0x20];
6448};
6449
6450struct mlx5_ifc_paos_reg_bits {
6451 u8 swid[0x8];
6452 u8 local_port[0x8];
6453 u8 reserved_0[0x4];
6454 u8 admin_status[0x4];
6455 u8 reserved_1[0x4];
6456 u8 oper_status[0x4];
6457
6458 u8 ase[0x1];
6459 u8 ee[0x1];
6460 u8 reserved_2[0x1c];
6461 u8 e[0x2];
6462
6463 u8 reserved_3[0x40];
6464};
6465
6466struct mlx5_ifc_pamp_reg_bits {
6467 u8 reserved_0[0x8];
6468 u8 opamp_group[0x8];
6469 u8 reserved_1[0xc];
6470 u8 opamp_group_type[0x4];
6471
6472 u8 start_index[0x10];
6473 u8 reserved_2[0x4];
6474 u8 num_of_indices[0xc];
6475
6476 u8 index_data[18][0x10];
6477};
6478
6479struct mlx5_ifc_lane_2_module_mapping_bits {
6480 u8 reserved_0[0x6];
6481 u8 rx_lane[0x2];
6482 u8 reserved_1[0x6];
6483 u8 tx_lane[0x2];
6484 u8 reserved_2[0x8];
6485 u8 module[0x8];
6486};
6487
6488struct mlx5_ifc_bufferx_reg_bits {
6489 u8 reserved_0[0x6];
6490 u8 lossy[0x1];
6491 u8 epsb[0x1];
6492 u8 reserved_1[0xc];
6493 u8 size[0xc];
6494
6495 u8 xoff_threshold[0x10];
6496 u8 xon_threshold[0x10];
6497};
6498
6499struct mlx5_ifc_set_node_in_bits {
6500 u8 node_description[64][0x8];
6501};
6502
6503struct mlx5_ifc_register_power_settings_bits {
6504 u8 reserved_0[0x18];
6505 u8 power_settings_level[0x8];
6506
6507 u8 reserved_1[0x60];
6508};
6509
6510struct mlx5_ifc_register_host_endianness_bits {
6511 u8 he[0x1];
6512 u8 reserved_0[0x1f];
6513
6514 u8 reserved_1[0x60];
6515};
6516
6517struct mlx5_ifc_umr_pointer_desc_argument_bits {
6518 u8 reserved_0[0x20];
6519
6520 u8 mkey[0x20];
6521
6522 u8 addressh_63_32[0x20];
6523
6524 u8 addressl_31_0[0x20];
6525};
6526
6527struct mlx5_ifc_ud_adrs_vector_bits {
6528 u8 dc_key[0x40];
6529
6530 u8 ext[0x1];
6531 u8 reserved_0[0x7];
6532 u8 destination_qp_dct[0x18];
6533
6534 u8 static_rate[0x4];
6535 u8 sl_eth_prio[0x4];
6536 u8 fl[0x1];
6537 u8 mlid[0x7];
6538 u8 rlid_udp_sport[0x10];
6539
6540 u8 reserved_1[0x20];
6541
6542 u8 rmac_47_16[0x20];
6543
6544 u8 rmac_15_0[0x10];
6545 u8 tclass[0x8];
6546 u8 hop_limit[0x8];
6547
6548 u8 reserved_2[0x1];
6549 u8 grh[0x1];
6550 u8 reserved_3[0x2];
6551 u8 src_addr_index[0x8];
6552 u8 flow_label[0x14];
6553
6554 u8 rgid_rip[16][0x8];
6555};
6556
6557struct mlx5_ifc_pages_req_event_bits {
6558 u8 reserved_0[0x10];
6559 u8 function_id[0x10];
6560
6561 u8 num_pages[0x20];
6562
6563 u8 reserved_1[0xa0];
6564};
6565
6566struct mlx5_ifc_eqe_bits {
6567 u8 reserved_0[0x8];
6568 u8 event_type[0x8];
6569 u8 reserved_1[0x8];
6570 u8 event_sub_type[0x8];
6571
6572 u8 reserved_2[0xe0];
6573
6574 union mlx5_ifc_event_auto_bits event_data;
6575
6576 u8 reserved_3[0x10];
6577 u8 signature[0x8];
6578 u8 reserved_4[0x7];
6579 u8 owner[0x1];
6580};
6581
6582enum {
6583 MLX5_CMD_QUEUE_ENTRY_TYPE_PCIE_CMD_IF_TRANSPORT = 0x7,
6584};
6585
6586struct mlx5_ifc_cmd_queue_entry_bits {
6587 u8 type[0x8];
6588 u8 reserved_0[0x18];
6589
6590 u8 input_length[0x20];
6591
6592 u8 input_mailbox_pointer_63_32[0x20];
6593
6594 u8 input_mailbox_pointer_31_9[0x17];
6595 u8 reserved_1[0x9];
6596
6597 u8 command_input_inline_data[16][0x8];
6598
6599 u8 command_output_inline_data[16][0x8];
6600
6601 u8 output_mailbox_pointer_63_32[0x20];
6602
6603 u8 output_mailbox_pointer_31_9[0x17];
6604 u8 reserved_2[0x9];
6605
6606 u8 output_length[0x20];
6607
6608 u8 token[0x8];
6609 u8 signature[0x8];
6610 u8 reserved_3[0x8];
6611 u8 status[0x7];
6612 u8 ownership[0x1];
6613};
6614
6615struct mlx5_ifc_cmd_out_bits {
6616 u8 status[0x8];
6617 u8 reserved_0[0x18];
6618
6619 u8 syndrome[0x20];
6620
6621 u8 command_output[0x20];
6622};
6623
6624struct mlx5_ifc_cmd_in_bits {
6625 u8 opcode[0x10];
6626 u8 reserved_0[0x10];
6627
6628 u8 reserved_1[0x10];
6629 u8 op_mod[0x10];
6630
6631 u8 command[0][0x20];
6632};
6633
6634struct mlx5_ifc_cmd_if_box_bits {
6635 u8 mailbox_data[512][0x8];
6636
6637 u8 reserved_0[0x180];
6638
6639 u8 next_pointer_63_32[0x20];
6640
6641 u8 next_pointer_31_10[0x16];
6642 u8 reserved_1[0xa];
6643
6644 u8 block_number[0x20];
6645
6646 u8 reserved_2[0x8];
6647 u8 token[0x8];
6648 u8 ctrl_signature[0x8];
6649 u8 signature[0x8];
6650};
6651
6652struct mlx5_ifc_mtt_bits {
6653 u8 ptag_63_32[0x20];
6654
6655 u8 ptag_31_8[0x18];
6656 u8 reserved_0[0x6];
6657 u8 wr_en[0x1];
6658 u8 rd_en[0x1];
6659};
6660
6661enum {
6662 MLX5_INITIAL_SEG_NIC_INTERFACE_FULL_DRIVER = 0x0,
6663 MLX5_INITIAL_SEG_NIC_INTERFACE_DISABLED = 0x1,
6664 MLX5_INITIAL_SEG_NIC_INTERFACE_NO_DRAM_NIC = 0x2,
6665};
6666
6667enum {
6668 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_FULL_DRIVER = 0x0,
6669 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_DISABLED = 0x1,
6670 MLX5_INITIAL_SEG_NIC_INTERFACE_SUPPORTED_NO_DRAM_NIC = 0x2,
6671};
6672
6673enum {
6674 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_INTERNAL_ERR = 0x1,
6675 MLX5_INITIAL_SEG_HEALTH_SYNDROME_DEAD_IRISC = 0x7,
6676 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HW_FATAL_ERR = 0x8,
6677 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FW_CRC_ERR = 0x9,
6678 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_FETCH_PCI_ERR = 0xa,
6679 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ICM_PAGE_ERR = 0xb,
6680 MLX5_INITIAL_SEG_HEALTH_SYNDROME_ASYNCHRONOUS_EQ_BUF_OVERRUN = 0xc,
6681 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_IN_ERR = 0xd,
6682 MLX5_INITIAL_SEG_HEALTH_SYNDROME_EQ_INV = 0xe,
6683 MLX5_INITIAL_SEG_HEALTH_SYNDROME_FFSER_ERR = 0xf,
6684 MLX5_INITIAL_SEG_HEALTH_SYNDROME_HIGH_TEMP_ERR = 0x10,
6685};
6686
6687struct mlx5_ifc_initial_seg_bits {
6688 u8 fw_rev_minor[0x10];
6689 u8 fw_rev_major[0x10];
6690
6691 u8 cmd_interface_rev[0x10];
6692 u8 fw_rev_subminor[0x10];
6693
6694 u8 reserved_0[0x40];
6695
6696 u8 cmdq_phy_addr_63_32[0x20];
6697
6698 u8 cmdq_phy_addr_31_12[0x14];
6699 u8 reserved_1[0x2];
6700 u8 nic_interface[0x2];
6701 u8 log_cmdq_size[0x4];
6702 u8 log_cmdq_stride[0x4];
6703
6704 u8 command_doorbell_vector[0x20];
6705
6706 u8 reserved_2[0xf00];
6707
6708 u8 initializing[0x1];
6709 u8 reserved_3[0x4];
6710 u8 nic_interface_supported[0x3];
6711 u8 reserved_4[0x18];
6712
6713 struct mlx5_ifc_health_buffer_bits health_buffer;
6714
6715 u8 no_dram_nic_offset[0x20];
6716
6717 u8 reserved_5[0x6e40];
6718
6719 u8 reserved_6[0x1f];
6720 u8 clear_int[0x1];
6721
6722 u8 health_syndrome[0x8];
6723 u8 health_counter[0x18];
6724
6725 u8 reserved_7[0x17fc0];
6726};
6727
6728union mlx5_ifc_ports_control_registers_document_bits {
6729 struct mlx5_ifc_bufferx_reg_bits bufferx_reg;
6730 struct mlx5_ifc_eth_2819_cntrs_grp_data_layout_bits eth_2819_cntrs_grp_data_layout;
6731 struct mlx5_ifc_eth_2863_cntrs_grp_data_layout_bits eth_2863_cntrs_grp_data_layout;
6732 struct mlx5_ifc_eth_3635_cntrs_grp_data_layout_bits eth_3635_cntrs_grp_data_layout;
6733 struct mlx5_ifc_eth_802_3_cntrs_grp_data_layout_bits eth_802_3_cntrs_grp_data_layout;
6734 struct mlx5_ifc_eth_extended_cntrs_grp_data_layout_bits eth_extended_cntrs_grp_data_layout;
6735 struct mlx5_ifc_eth_per_prio_grp_data_layout_bits eth_per_prio_grp_data_layout;
6736 struct mlx5_ifc_eth_per_traffic_grp_data_layout_bits eth_per_traffic_grp_data_layout;
6737 struct mlx5_ifc_lane_2_module_mapping_bits lane_2_module_mapping;
6738 struct mlx5_ifc_pamp_reg_bits pamp_reg;
6739 struct mlx5_ifc_paos_reg_bits paos_reg;
6740 struct mlx5_ifc_pcap_reg_bits pcap_reg;
6741 struct mlx5_ifc_peir_reg_bits peir_reg;
6742 struct mlx5_ifc_pelc_reg_bits pelc_reg;
6743 struct mlx5_ifc_pfcc_reg_bits pfcc_reg;
6744 struct mlx5_ifc_phys_layer_cntrs_bits phys_layer_cntrs;
6745 struct mlx5_ifc_pifr_reg_bits pifr_reg;
6746 struct mlx5_ifc_pipg_reg_bits pipg_reg;
6747 struct mlx5_ifc_plbf_reg_bits plbf_reg;
6748 struct mlx5_ifc_plib_reg_bits plib_reg;
6749 struct mlx5_ifc_plpc_reg_bits plpc_reg;
6750 struct mlx5_ifc_pmaos_reg_bits pmaos_reg;
6751 struct mlx5_ifc_pmlp_reg_bits pmlp_reg;
6752 struct mlx5_ifc_pmlpn_reg_bits pmlpn_reg;
6753 struct mlx5_ifc_pmpc_reg_bits pmpc_reg;
6754 struct mlx5_ifc_pmpe_reg_bits pmpe_reg;
6755 struct mlx5_ifc_pmpr_reg_bits pmpr_reg;
6756 struct mlx5_ifc_pmtu_reg_bits pmtu_reg;
6757 struct mlx5_ifc_ppad_reg_bits ppad_reg;
6758 struct mlx5_ifc_ppcnt_reg_bits ppcnt_reg;
6759 struct mlx5_ifc_pplm_reg_bits pplm_reg;
6760 struct mlx5_ifc_pplr_reg_bits pplr_reg;
6761 struct mlx5_ifc_ppsc_reg_bits ppsc_reg;
6762 struct mlx5_ifc_pqdr_reg_bits pqdr_reg;
6763 struct mlx5_ifc_pspa_reg_bits pspa_reg;
6764 struct mlx5_ifc_ptas_reg_bits ptas_reg;
6765 struct mlx5_ifc_ptys_reg_bits ptys_reg;
6766 struct mlx5_ifc_pude_reg_bits pude_reg;
6767 struct mlx5_ifc_pvlc_reg_bits pvlc_reg;
6768 struct mlx5_ifc_slrg_reg_bits slrg_reg;
6769 struct mlx5_ifc_sltp_reg_bits sltp_reg;
6770 u8 reserved_0[0x60e0];
6771};
6772
6773union mlx5_ifc_debug_enhancements_document_bits {
6774 struct mlx5_ifc_health_buffer_bits health_buffer;
6775 u8 reserved_0[0x200];
6776};
6777
6778union mlx5_ifc_uplink_pci_interface_document_bits {
6779 struct mlx5_ifc_initial_seg_bits initial_seg;
6780 u8 reserved_0[0x20060];
b775516b
EC		 6781};
6782
d29b796a 6783#endif /* MLX5_IFC_H */
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