[mirror_ubuntu-bionic-kernel.git] / include / linux / mlx5 / qp.h

/*
 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
 *
 * This software is available to you under a choice of one of two
 * licenses.  You may choose to be licensed under the terms of the GNU
 * General Public License (GPL) Version 2, available from the file
 * COPYING in the main directory of this source tree, or the
 * OpenIB.org BSD license below:
 *
 *     Redistribution and use in source and binary forms, with or
 *     without modification, are permitted provided that the following
 *     conditions are met:
 *
 *      - Redistributions of source code must retain the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer.
 *
 *      - Redistributions in binary form must reproduce the above
 *        copyright notice, this list of conditions and the following
 *        disclaimer in the documentation and/or other materials
 *        provided with the distribution.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 * SOFTWARE.
 */

#ifndef MLX5_QP_H
#define MLX5_QP_H

#include <linux/mlx5/device.h>
#include <linux/mlx5/driver.h>

#define MLX5_INVALID_LKEY	0x100
#define MLX5_SIG_WQE_SIZE	(MLX5_SEND_WQE_BB * 5)
#define MLX5_DIF_SIZE		8
#define MLX5_STRIDE_BLOCK_OP	0x400
#define MLX5_CPY_GRD_MASK	0xc0
#define MLX5_CPY_APP_MASK	0x30
#define MLX5_CPY_REF_MASK	0x0f
#define MLX5_BSF_INC_REFTAG	(1 << 6)
#define MLX5_BSF_INL_VALID	(1 << 15)
#define MLX5_BSF_REFRESH_DIF	(1 << 14)
#define MLX5_BSF_REPEAT_BLOCK	(1 << 7)
#define MLX5_BSF_APPTAG_ESCAPE	0x1
#define MLX5_BSF_APPREF_ESCAPE	0x2

#define MLX5_QPN_BITS		24
#define MLX5_QPN_MASK		((1 << MLX5_QPN_BITS) - 1)

enum mlx5_qp_optpar {
	MLX5_QP_OPTPAR_ALT_ADDR_PATH		= 1 << 0,
	MLX5_QP_OPTPAR_RRE			= 1 << 1,
	MLX5_QP_OPTPAR_RAE			= 1 << 2,
	MLX5_QP_OPTPAR_RWE			= 1 << 3,
	MLX5_QP_OPTPAR_PKEY_INDEX		= 1 << 4,
	MLX5_QP_OPTPAR_Q_KEY			= 1 << 5,
	MLX5_QP_OPTPAR_RNR_TIMEOUT		= 1 << 6,
	MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH	= 1 << 7,
	MLX5_QP_OPTPAR_SRA_MAX			= 1 << 8,
	MLX5_QP_OPTPAR_RRA_MAX			= 1 << 9,
	MLX5_QP_OPTPAR_PM_STATE			= 1 << 10,
	MLX5_QP_OPTPAR_RETRY_COUNT		= 1 << 12,
	MLX5_QP_OPTPAR_RNR_RETRY		= 1 << 13,
	MLX5_QP_OPTPAR_ACK_TIMEOUT		= 1 << 14,
	MLX5_QP_OPTPAR_PRI_PORT			= 1 << 16,
	MLX5_QP_OPTPAR_SRQN			= 1 << 18,
	MLX5_QP_OPTPAR_CQN_RCV			= 1 << 19,
	MLX5_QP_OPTPAR_DC_HS			= 1 << 20,
	MLX5_QP_OPTPAR_DC_KEY			= 1 << 21,
};

enum mlx5_qp_state {
	MLX5_QP_STATE_RST			= 0,
	MLX5_QP_STATE_INIT			= 1,
	MLX5_QP_STATE_RTR			= 2,
	MLX5_QP_STATE_RTS			= 3,
	MLX5_QP_STATE_SQER			= 4,
	MLX5_QP_STATE_SQD			= 5,
	MLX5_QP_STATE_ERR			= 6,
	MLX5_QP_STATE_SQ_DRAINING		= 7,
	MLX5_QP_STATE_SUSPENDED			= 9,
	MLX5_QP_NUM_STATE,
	MLX5_QP_STATE,
	MLX5_QP_STATE_BAD,
};

enum {
	MLX5_SQ_STATE_NA	= MLX5_SQC_STATE_ERR + 1,
	MLX5_SQ_NUM_STATE	= MLX5_SQ_STATE_NA + 1,
	MLX5_RQ_STATE_NA	= MLX5_RQC_STATE_ERR + 1,
	MLX5_RQ_NUM_STATE	= MLX5_RQ_STATE_NA + 1,
};

enum {
	MLX5_QP_ST_RC				= 0x0,
	MLX5_QP_ST_UC				= 0x1,
	MLX5_QP_ST_UD				= 0x2,
	MLX5_QP_ST_XRC				= 0x3,
	MLX5_QP_ST_MLX				= 0x4,
	MLX5_QP_ST_DCI				= 0x5,
	MLX5_QP_ST_DCT				= 0x6,
	MLX5_QP_ST_QP0				= 0x7,
	MLX5_QP_ST_QP1				= 0x8,
	MLX5_QP_ST_RAW_ETHERTYPE		= 0x9,
	MLX5_QP_ST_RAW_IPV6			= 0xa,
	MLX5_QP_ST_SNIFFER			= 0xb,
	MLX5_QP_ST_SYNC_UMR			= 0xe,
	MLX5_QP_ST_PTP_1588			= 0xd,
	MLX5_QP_ST_REG_UMR			= 0xc,
	MLX5_QP_ST_MAX
};

enum {
	MLX5_QP_PM_MIGRATED			= 0x3,
	MLX5_QP_PM_ARMED			= 0x0,
	MLX5_QP_PM_REARM			= 0x1
};

enum {
	MLX5_NON_ZERO_RQ	= 0x0,
	MLX5_SRQ_RQ		= 0x1,
	MLX5_CRQ_RQ		= 0x2,
	MLX5_ZERO_LEN_RQ	= 0x3
};

/* TODO REM */
enum {
	/* params1 */
	MLX5_QP_BIT_SRE				= 1 << 15,
	MLX5_QP_BIT_SWE				= 1 << 14,
	MLX5_QP_BIT_SAE				= 1 << 13,
	/* params2 */
	MLX5_QP_BIT_RRE				= 1 << 15,
	MLX5_QP_BIT_RWE				= 1 << 14,
	MLX5_QP_BIT_RAE				= 1 << 13,
	MLX5_QP_BIT_RIC				= 1 <<	4,
	MLX5_QP_BIT_CC_SLAVE_RECV		= 1 <<  2,
	MLX5_QP_BIT_CC_SLAVE_SEND		= 1 <<  1,
	MLX5_QP_BIT_CC_MASTER			= 1 <<  0
};

enum {
	MLX5_WQE_CTRL_CQ_UPDATE		= 2 << 2,
	MLX5_WQE_CTRL_CQ_UPDATE_AND_EQE	= 3 << 2,
	MLX5_WQE_CTRL_SOLICITED		= 1 << 1,
};

enum {
	MLX5_SEND_WQE_DS	= 16,
	MLX5_SEND_WQE_BB	= 64,
};

#define MLX5_SEND_WQEBB_NUM_DS	(MLX5_SEND_WQE_BB / MLX5_SEND_WQE_DS)

enum {
	MLX5_SEND_WQE_MAX_WQEBBS	= 16,
};

enum {
	MLX5_WQE_FMR_PERM_LOCAL_READ	= 1 << 27,
	MLX5_WQE_FMR_PERM_LOCAL_WRITE	= 1 << 28,
	MLX5_WQE_FMR_PERM_REMOTE_READ	= 1 << 29,
	MLX5_WQE_FMR_PERM_REMOTE_WRITE	= 1 << 30,
	MLX5_WQE_FMR_PERM_ATOMIC	= 1 << 31
};

enum {
	MLX5_FENCE_MODE_NONE			= 0 << 5,
	MLX5_FENCE_MODE_INITIATOR_SMALL		= 1 << 5,
	MLX5_FENCE_MODE_FENCE			= 2 << 5,
	MLX5_FENCE_MODE_STRONG_ORDERING		= 3 << 5,
	MLX5_FENCE_MODE_SMALL_AND_FENCE		= 4 << 5,
};

enum {
	MLX5_RCV_DBR	= 0,
	MLX5_SND_DBR	= 1,
};

enum {
	MLX5_FLAGS_INLINE	= 1<<7,
	MLX5_FLAGS_CHECK_FREE   = 1<<5,
};

struct mlx5_wqe_fmr_seg {
	__be32			flags;
	__be32			mem_key;
	__be64			buf_list;
	__be64			start_addr;
	__be64			reg_len;
	__be32			offset;
	__be32			page_size;
	u32			reserved[2];
};

struct mlx5_wqe_ctrl_seg {
	__be32			opmod_idx_opcode;
	__be32			qpn_ds;
	u8			signature;
	u8			rsvd[2];
	u8			fm_ce_se;
	__be32			imm;
};

#define MLX5_WQE_CTRL_DS_MASK 0x3f
#define MLX5_WQE_CTRL_QPN_MASK 0xffffff00
#define MLX5_WQE_CTRL_QPN_SHIFT 8
#define MLX5_WQE_DS_UNITS 16
#define MLX5_WQE_CTRL_OPCODE_MASK 0xff
#define MLX5_WQE_CTRL_WQE_INDEX_MASK 0x00ffff00
#define MLX5_WQE_CTRL_WQE_INDEX_SHIFT 8

enum {
	MLX5_ETH_WQE_L3_INNER_CSUM      = 1 << 4,
	MLX5_ETH_WQE_L4_INNER_CSUM      = 1 << 5,
	MLX5_ETH_WQE_L3_CSUM            = 1 << 6,
	MLX5_ETH_WQE_L4_CSUM            = 1 << 7,
};

struct mlx5_wqe_eth_seg {
	u8              rsvd0[4];
	u8              cs_flags;
	u8              rsvd1;
	__be16          mss;
	__be32          rsvd2;
	__be16          inline_hdr_sz;
	u8              inline_hdr_start[2];
};

struct mlx5_wqe_xrc_seg {
	__be32			xrc_srqn;
	u8			rsvd[12];
};

struct mlx5_wqe_masked_atomic_seg {
	__be64			swap_add;
	__be64			compare;
	__be64			swap_add_mask;
	__be64			compare_mask;
};

struct mlx5_av {
	union {
		struct {
			__be32	qkey;
			__be32	reserved;
		} qkey;
		__be64	dc_key;
	} key;
	__be32	dqp_dct;
	u8	stat_rate_sl;
	u8	fl_mlid;
	union {
		__be16	rlid;
		__be16  udp_sport;
	};
	u8	reserved0[4];
	u8	rmac[6];
	u8	tclass;
	u8	hop_limit;
	__be32	grh_gid_fl;
	u8	rgid[16];
};

struct mlx5_wqe_datagram_seg {
	struct mlx5_av	av;
};

struct mlx5_wqe_raddr_seg {
	__be64			raddr;
	__be32			rkey;
	u32			reserved;
};

struct mlx5_wqe_atomic_seg {
	__be64			swap_add;
	__be64			compare;
};

struct mlx5_wqe_data_seg {
	__be32			byte_count;
	__be32			lkey;
	__be64			addr;
};

struct mlx5_wqe_umr_ctrl_seg {
	u8		flags;
	u8		rsvd0[3];
	__be16		klm_octowords;
	__be16		bsf_octowords;
	__be64		mkey_mask;
	u8		rsvd1[32];
};

struct mlx5_seg_set_psv {
	__be32		psv_num;
	__be16		syndrome;
	__be16		status;
	__be32		transient_sig;
	__be32		ref_tag;
};

struct mlx5_seg_get_psv {
	u8		rsvd[19];
	u8		num_psv;
	__be32		l_key;
	__be64		va;
	__be32		psv_index[4];
};

struct mlx5_seg_check_psv {
	u8		rsvd0[2];
	__be16		err_coalescing_op;
	u8		rsvd1[2];
	__be16		xport_err_op;
	u8		rsvd2[2];
	__be16		xport_err_mask;
	u8		rsvd3[7];
	u8		num_psv;
	__be32		l_key;
	__be64		va;
	__be32		psv_index[4];
};

struct mlx5_rwqe_sig {
	u8	rsvd0[4];
	u8	signature;
	u8	rsvd1[11];
};

struct mlx5_wqe_signature_seg {
	u8	rsvd0[4];
	u8	signature;
	u8	rsvd1[11];
};

#define MLX5_WQE_INLINE_SEG_BYTE_COUNT_MASK 0x3ff

struct mlx5_wqe_inline_seg {
	__be32	byte_count;
};

enum mlx5_sig_type {
	MLX5_DIF_CRC = 0x1,
	MLX5_DIF_IPCS = 0x2,
};

struct mlx5_bsf_inl {
	__be16		vld_refresh;
	__be16		dif_apptag;
	__be32		dif_reftag;
	u8		sig_type;
	u8		rp_inv_seed;
	u8		rsvd[3];
	u8		dif_inc_ref_guard_check;
	__be16		dif_app_bitmask_check;
};

struct mlx5_bsf {
	struct mlx5_bsf_basic {
		u8		bsf_size_sbs;
		u8		check_byte_mask;
		union {
			u8	copy_byte_mask;
			u8	bs_selector;
			u8	rsvd_wflags;
		} wire;
		union {
			u8	bs_selector;
			u8	rsvd_mflags;
		} mem;
		__be32		raw_data_size;
		__be32		w_bfs_psv;
		__be32		m_bfs_psv;
	} basic;
	struct mlx5_bsf_ext {
		__be32		t_init_gen_pro_size;
		__be32		rsvd_epi_size;
		__be32		w_tfs_psv;
		__be32		m_tfs_psv;
	} ext;
	struct mlx5_bsf_inl	w_inl;
	struct mlx5_bsf_inl	m_inl;
};

struct mlx5_klm {
	__be32		bcount;
	__be32		key;
	__be64		va;
};

struct mlx5_stride_block_entry {
	__be16		stride;
	__be16		bcount;
	__be32		key;
	__be64		va;
};

struct mlx5_stride_block_ctrl_seg {
	__be32		bcount_per_cycle;
	__be32		op;
	__be32		repeat_count;
	u16		rsvd;
	__be16		num_entries;
};

enum mlx5_pagefault_flags {
	MLX5_PFAULT_REQUESTOR = 1 << 0,
	MLX5_PFAULT_WRITE     = 1 << 1,
	MLX5_PFAULT_RDMA      = 1 << 2,
};

/* Contains the details of a pagefault. */
struct mlx5_pagefault {
	u32			bytes_committed;
	u8			event_subtype;
	enum mlx5_pagefault_flags flags;
	union {
		/* Initiator or send message responder pagefault details. */
		struct {
			/* Received packet size, only valid for responders. */
			u32	packet_size;
			/*
			 * WQE index. Refers to either the send queue or
			 * receive queue, according to event_subtype.
			 */
			u16	wqe_index;
		} wqe;
		/* RDMA responder pagefault details */
		struct {
			u32	r_key;
			/*
			 * Received packet size, minimal size page fault
			 * resolution required for forward progress.
			 */
			u32	packet_size;
			u32	rdma_op_len;
			u64	rdma_va;
		} rdma;
	};
};

struct mlx5_core_qp {
	struct mlx5_core_rsc_common	common; /* must be first */
	void (*event)		(struct mlx5_core_qp *, int);
	void (*pfault_handler)(struct mlx5_core_qp *, struct mlx5_pagefault *);
	int			qpn;
	struct mlx5_rsc_debug	*dbg;
	int			pid;
};

struct mlx5_qp_path {
	u8			fl_free_ar;
	u8			rsvd3;
	__be16			pkey_index;
	u8			rsvd0;
	u8			grh_mlid;
	__be16			rlid;
	u8			ackto_lt;
	u8			mgid_index;
	u8			static_rate;
	u8			hop_limit;
	__be32			tclass_flowlabel;
	union {
		u8		rgid[16];
		u8		rip[16];
	};
	u8			f_dscp_ecn_prio;
	u8			ecn_dscp;
	__be16			udp_sport;
	u8			dci_cfi_prio_sl;
	u8			port;
	u8			rmac[6];
};

struct mlx5_qp_context {
	__be32			flags;
	__be32			flags_pd;
	u8			mtu_msgmax;
	u8			rq_size_stride;
	__be16			sq_crq_size;
	__be32			qp_counter_set_usr_page;
	__be32			wire_qpn;
	__be32			log_pg_sz_remote_qpn;
	struct			mlx5_qp_path pri_path;
	struct			mlx5_qp_path alt_path;
	__be32			params1;
	u8			reserved2[4];
	__be32			next_send_psn;
	__be32			cqn_send;
	__be32			deth_sqpn;
	u8			reserved3[4];
	__be32			last_acked_psn;
	__be32			ssn;
	__be32			params2;
	__be32			rnr_nextrecvpsn;
	__be32			xrcd;
	__be32			cqn_recv;
	__be64			db_rec_addr;
	__be32			qkey;
	__be32			rq_type_srqn;
	__be32			rmsn;
	__be16			hw_sq_wqe_counter;
	__be16			sw_sq_wqe_counter;
	__be16			hw_rcyclic_byte_counter;
	__be16			hw_rq_counter;
	__be16			sw_rcyclic_byte_counter;
	__be16			sw_rq_counter;
	u8			rsvd0[5];
	u8			cgs;
	u8			cs_req;
	u8			cs_res;
	__be64			dc_access_key;
	u8			rsvd1[24];
};

struct mlx5_modify_qp_mbox_in {
	struct mlx5_inbox_hdr	hdr;
	__be32			qpn;
	u8			rsvd0[4];
	__be32			optparam;
	u8			rsvd1[4];
	struct mlx5_qp_context	ctx;
	u8			rsvd2[16];
};

struct mlx5_modify_qp_mbox_out {
	struct mlx5_outbox_hdr	hdr;
	u8			rsvd0[8];
};

static inline struct mlx5_core_qp *__mlx5_qp_lookup(struct mlx5_core_dev *dev, u32 qpn)
{
	return radix_tree_lookup(&dev->priv.qp_table.tree, qpn);
}

static inline struct mlx5_core_mkey *__mlx5_mr_lookup(struct mlx5_core_dev *dev, u32 key)
{
	return radix_tree_lookup(&dev->priv.mkey_table.tree, key);
}

int mlx5_core_create_qp(struct mlx5_core_dev *dev,
			struct mlx5_core_qp *qp,
			u32 *in,
			int inlen);
int mlx5_core_qp_modify(struct mlx5_core_dev *dev, u16 operation,
			struct mlx5_modify_qp_mbox_in *in, int sqd_event,
			struct mlx5_core_qp *qp);
int mlx5_core_destroy_qp(struct mlx5_core_dev *dev,
			 struct mlx5_core_qp *qp);
int mlx5_core_qp_query(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp,
		       u32 *out, int outlen);

int mlx5_core_xrcd_alloc(struct mlx5_core_dev *dev, u32 *xrcdn);
int mlx5_core_xrcd_dealloc(struct mlx5_core_dev *dev, u32 xrcdn);
void mlx5_init_qp_table(struct mlx5_core_dev *dev);
void mlx5_cleanup_qp_table(struct mlx5_core_dev *dev);
int mlx5_debug_qp_add(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp);
void mlx5_debug_qp_remove(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp);
#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
int mlx5_core_page_fault_resume(struct mlx5_core_dev *dev, u32 qpn,
				u8 context, int error);
#endif
int mlx5_core_create_rq_tracked(struct mlx5_core_dev *dev, u32 *in, int inlen,
				struct mlx5_core_qp *rq);
void mlx5_core_destroy_rq_tracked(struct mlx5_core_dev *dev,
				  struct mlx5_core_qp *rq);
int mlx5_core_create_sq_tracked(struct mlx5_core_dev *dev, u32 *in, int inlen,
				struct mlx5_core_qp *sq);
void mlx5_core_destroy_sq_tracked(struct mlx5_core_dev *dev,
				  struct mlx5_core_qp *sq);
int mlx5_core_alloc_q_counter(struct mlx5_core_dev *dev, u16 *counter_id);
int mlx5_core_dealloc_q_counter(struct mlx5_core_dev *dev, u16 counter_id);
int mlx5_core_query_q_counter(struct mlx5_core_dev *dev, u16 counter_id,
			      int reset, void *out, int out_size);
int mlx5_core_query_out_of_buffer(struct mlx5_core_dev *dev, u16 counter_id,
				  u32 *out_of_buffer);

static inline const char *mlx5_qp_type_str(int type)
{
	switch (type) {
	case MLX5_QP_ST_RC: return "RC";
	case MLX5_QP_ST_UC: return "C";
	case MLX5_QP_ST_UD: return "UD";
	case MLX5_QP_ST_XRC: return "XRC";
	case MLX5_QP_ST_MLX: return "MLX";
	case MLX5_QP_ST_QP0: return "QP0";
	case MLX5_QP_ST_QP1: return "QP1";
	case MLX5_QP_ST_RAW_ETHERTYPE: return "RAW_ETHERTYPE";
	case MLX5_QP_ST_RAW_IPV6: return "RAW_IPV6";
	case MLX5_QP_ST_SNIFFER: return "SNIFFER";
	case MLX5_QP_ST_SYNC_UMR: return "SYNC_UMR";
	case MLX5_QP_ST_PTP_1588: return "PTP_1588";
	case MLX5_QP_ST_REG_UMR: return "REG_UMR";
	default: return "Invalid transport type";
	}
}

static inline const char *mlx5_qp_state_str(int state)
{
	switch (state) {
	case MLX5_QP_STATE_RST:
	return "RST";
	case MLX5_QP_STATE_INIT:
	return "INIT";
	case MLX5_QP_STATE_RTR:
	return "RTR";
	case MLX5_QP_STATE_RTS:
	return "RTS";
	case MLX5_QP_STATE_SQER:
	return "SQER";
	case MLX5_QP_STATE_SQD:
	return "SQD";
	case MLX5_QP_STATE_ERR:
	return "ERR";
	case MLX5_QP_STATE_SQ_DRAINING:
	return "SQ_DRAINING";
	case MLX5_QP_STATE_SUSPENDED:
	return "SUSPENDED";
	default: return "Invalid QP state";
	}
}

#endif /* MLX5_QP_H */
Commit	Line	Data
e126ba97	1	/*
302bdf68	2	* Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
e126ba97 EC	3	*
	4	* This software is available to you under a choice of one of two
	5	* licenses. You may choose to be licensed under the terms of the GNU
	6	* General Public License (GPL) Version 2, available from the file
	7	* COPYING in the main directory of this source tree, or the
	8	* OpenIB.org BSD license below:
	9	*
	10	* Redistribution and use in source and binary forms, with or
	11	* without modification, are permitted provided that the following
	12	* conditions are met:
	13	*
	14	* - Redistributions of source code must retain the above
	15	* copyright notice, this list of conditions and the following
	16	* disclaimer.
	17	*
	18	* - Redistributions in binary form must reproduce the above
	19	* copyright notice, this list of conditions and the following
	20	* disclaimer in the documentation and/or other materials
	21	* provided with the distribution.
	22	*
	23	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	24	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
	25	* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	26	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
	27	* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
	28	* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
	29	* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
	30	* SOFTWARE.
	31	*/
	32
	33	#ifndef MLX5_QP_H
	34	#define MLX5_QP_H
	35
	36	#include <linux/mlx5/device.h>
	37	#include <linux/mlx5/driver.h>
	38
	39	#define MLX5_INVALID_LKEY 0x100
e1e66cc2	40	#define MLX5_SIG_WQE_SIZE (MLX5_SEND_WQE_BB * 5)
e6631814 SG	41	#define MLX5_DIF_SIZE 8
e6631814 SG	42	#define MLX5_STRIDE_BLOCK_OP 0x400
fd22f78c SG	43	#define MLX5_CPY_GRD_MASK 0xc0
	44	#define MLX5_CPY_APP_MASK 0x30
	45	#define MLX5_CPY_REF_MASK 0x0f
142537f4 SG	46	#define MLX5_BSF_INC_REFTAG (1 << 6)
	47	#define MLX5_BSF_INL_VALID (1 << 15)
	48	#define MLX5_BSF_REFRESH_DIF (1 << 14)
	49	#define MLX5_BSF_REPEAT_BLOCK (1 << 7)
	50	#define MLX5_BSF_APPTAG_ESCAPE 0x1
	51	#define MLX5_BSF_APPREF_ESCAPE 0x2
e126ba97	52
e420f0c0 HE	53	#define MLX5_QPN_BITS 24
	54	#define MLX5_QPN_MASK ((1 << MLX5_QPN_BITS) - 1)
	55
e126ba97 EC	56	enum mlx5_qp_optpar {
	57	MLX5_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0,
	58	MLX5_QP_OPTPAR_RRE = 1 << 1,
	59	MLX5_QP_OPTPAR_RAE = 1 << 2,
	60	MLX5_QP_OPTPAR_RWE = 1 << 3,
	61	MLX5_QP_OPTPAR_PKEY_INDEX = 1 << 4,
	62	MLX5_QP_OPTPAR_Q_KEY = 1 << 5,
	63	MLX5_QP_OPTPAR_RNR_TIMEOUT = 1 << 6,
	64	MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
	65	MLX5_QP_OPTPAR_SRA_MAX = 1 << 8,
	66	MLX5_QP_OPTPAR_RRA_MAX = 1 << 9,
	67	MLX5_QP_OPTPAR_PM_STATE = 1 << 10,
	68	MLX5_QP_OPTPAR_RETRY_COUNT = 1 << 12,
	69	MLX5_QP_OPTPAR_RNR_RETRY = 1 << 13,
	70	MLX5_QP_OPTPAR_ACK_TIMEOUT = 1 << 14,
	71	MLX5_QP_OPTPAR_PRI_PORT = 1 << 16,
	72	MLX5_QP_OPTPAR_SRQN = 1 << 18,
	73	MLX5_QP_OPTPAR_CQN_RCV = 1 << 19,
	74	MLX5_QP_OPTPAR_DC_HS = 1 << 20,
	75	MLX5_QP_OPTPAR_DC_KEY = 1 << 21,
	76	};
	77
	78	enum mlx5_qp_state {
	79	MLX5_QP_STATE_RST = 0,
	80	MLX5_QP_STATE_INIT = 1,
	81	MLX5_QP_STATE_RTR = 2,
	82	MLX5_QP_STATE_RTS = 3,
	83	MLX5_QP_STATE_SQER = 4,
	84	MLX5_QP_STATE_SQD = 5,
	85	MLX5_QP_STATE_ERR = 6,
	86	MLX5_QP_STATE_SQ_DRAINING = 7,
	87	MLX5_QP_STATE_SUSPENDED = 9,
6d2f89df	88	MLX5_QP_NUM_STATE,
	89	MLX5_QP_STATE,
	90	MLX5_QP_STATE_BAD,
	91	};
	92
	93	enum {
	94	MLX5_SQ_STATE_NA = MLX5_SQC_STATE_ERR + 1,
	95	MLX5_SQ_NUM_STATE = MLX5_SQ_STATE_NA + 1,
	96	MLX5_RQ_STATE_NA = MLX5_RQC_STATE_ERR + 1,
	97	MLX5_RQ_NUM_STATE = MLX5_RQ_STATE_NA + 1,
e126ba97 EC	98	};
	99
	100	enum {
	101	MLX5_QP_ST_RC = 0x0,
	102	MLX5_QP_ST_UC = 0x1,
	103	MLX5_QP_ST_UD = 0x2,
	104	MLX5_QP_ST_XRC = 0x3,
	105	MLX5_QP_ST_MLX = 0x4,
	106	MLX5_QP_ST_DCI = 0x5,
	107	MLX5_QP_ST_DCT = 0x6,
	108	MLX5_QP_ST_QP0 = 0x7,
	109	MLX5_QP_ST_QP1 = 0x8,
	110	MLX5_QP_ST_RAW_ETHERTYPE = 0x9,
	111	MLX5_QP_ST_RAW_IPV6 = 0xa,
	112	MLX5_QP_ST_SNIFFER = 0xb,
	113	MLX5_QP_ST_SYNC_UMR = 0xe,
	114	MLX5_QP_ST_PTP_1588 = 0xd,
	115	MLX5_QP_ST_REG_UMR = 0xc,
	116	MLX5_QP_ST_MAX
	117	};
	118
	119	enum {
	120	MLX5_QP_PM_MIGRATED = 0x3,
	121	MLX5_QP_PM_ARMED = 0x0,
	122	MLX5_QP_PM_REARM = 0x1
	123	};
	124
	125	enum {
09a7d9ec SM	126	MLX5_NON_ZERO_RQ = 0x0,
	127	MLX5_SRQ_RQ = 0x1,
	128	MLX5_CRQ_RQ = 0x2,
	129	MLX5_ZERO_LEN_RQ = 0x3
e126ba97 EC	130	};
e126ba97 EC	131
09a7d9ec	132	/* TODO REM */
e126ba97 EC	133	enum {
	134	/* params1 */
	135	MLX5_QP_BIT_SRE = 1 << 15,
	136	MLX5_QP_BIT_SWE = 1 << 14,
	137	MLX5_QP_BIT_SAE = 1 << 13,
	138	/* params2 */
	139	MLX5_QP_BIT_RRE = 1 << 15,
	140	MLX5_QP_BIT_RWE = 1 << 14,
	141	MLX5_QP_BIT_RAE = 1 << 13,
	142	MLX5_QP_BIT_RIC = 1 << 4,
051f2630 LR	143	MLX5_QP_BIT_CC_SLAVE_RECV = 1 << 2,
	144	MLX5_QP_BIT_CC_SLAVE_SEND = 1 << 1,
	145	MLX5_QP_BIT_CC_MASTER = 1 << 0
e126ba97 EC	146	};
	147
	148	enum {
	149	MLX5_WQE_CTRL_CQ_UPDATE = 2 << 2,
e281682b	150	MLX5_WQE_CTRL_CQ_UPDATE_AND_EQE = 3 << 2,
e126ba97 EC	151	MLX5_WQE_CTRL_SOLICITED = 1 << 1,
	152	};
	153
	154	enum {
e281682b	155	MLX5_SEND_WQE_DS = 16,
e126ba97 EC	156	MLX5_SEND_WQE_BB = 64,
	157	};
	158
e281682b SM	159	#define MLX5_SEND_WQEBB_NUM_DS (MLX5_SEND_WQE_BB / MLX5_SEND_WQE_DS)
	160
	161	enum {
	162	MLX5_SEND_WQE_MAX_WQEBBS = 16,
	163	};
	164
e126ba97 EC	165	enum {
	166	MLX5_WQE_FMR_PERM_LOCAL_READ = 1 << 27,
	167	MLX5_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28,
	168	MLX5_WQE_FMR_PERM_REMOTE_READ = 1 << 29,
	169	MLX5_WQE_FMR_PERM_REMOTE_WRITE = 1 << 30,
	170	MLX5_WQE_FMR_PERM_ATOMIC = 1 << 31
	171	};
	172
	173	enum {
	174	MLX5_FENCE_MODE_NONE = 0 << 5,
	175	MLX5_FENCE_MODE_INITIATOR_SMALL = 1 << 5,
c9b25495	176	MLX5_FENCE_MODE_FENCE = 2 << 5,
e126ba97 EC	177	MLX5_FENCE_MODE_STRONG_ORDERING = 3 << 5,
	178	MLX5_FENCE_MODE_SMALL_AND_FENCE = 4 << 5,
	179	};
	180
e126ba97 EC	181	enum {
	182	MLX5_RCV_DBR = 0,
	183	MLX5_SND_DBR = 1,
	184	};
	185
e6631814 SG	186	enum {
	187	MLX5_FLAGS_INLINE = 1<<7,
	188	MLX5_FLAGS_CHECK_FREE = 1<<5,
	189	};
	190
e126ba97 EC	191	struct mlx5_wqe_fmr_seg {
	192	__be32 flags;
	193	__be32 mem_key;
	194	__be64 buf_list;
	195	__be64 start_addr;
	196	__be64 reg_len;
	197	__be32 offset;
	198	__be32 page_size;
	199	u32 reserved[2];
	200	};
	201
	202	struct mlx5_wqe_ctrl_seg {
	203	__be32 opmod_idx_opcode;
	204	__be32 qpn_ds;
	205	u8 signature;
	206	u8 rsvd[2];
	207	u8 fm_ce_se;
	208	__be32 imm;
	209	};
	210
c1395a2a	211	#define MLX5_WQE_CTRL_DS_MASK 0x3f
7bdf65d4 HE	212	#define MLX5_WQE_CTRL_QPN_MASK 0xffffff00
7bdf65d4 HE	213	#define MLX5_WQE_CTRL_QPN_SHIFT 8
c1395a2a	214	#define MLX5_WQE_DS_UNITS 16
7bdf65d4 HE	215	#define MLX5_WQE_CTRL_OPCODE_MASK 0xff
	216	#define MLX5_WQE_CTRL_WQE_INDEX_MASK 0x00ffff00
	217	#define MLX5_WQE_CTRL_WQE_INDEX_SHIFT 8
c1395a2a	218
e281682b SM	219	enum {
	220	MLX5_ETH_WQE_L3_INNER_CSUM = 1 << 4,
	221	MLX5_ETH_WQE_L4_INNER_CSUM = 1 << 5,
	222	MLX5_ETH_WQE_L3_CSUM = 1 << 6,
	223	MLX5_ETH_WQE_L4_CSUM = 1 << 7,
	224	};
	225
	226	struct mlx5_wqe_eth_seg {
	227	u8 rsvd0[4];
	228	u8 cs_flags;
	229	u8 rsvd1;
	230	__be16 mss;
	231	__be32 rsvd2;
	232	__be16 inline_hdr_sz;
	233	u8 inline_hdr_start[2];
	234	};
	235
e126ba97 EC	236	struct mlx5_wqe_xrc_seg {
	237	__be32 xrc_srqn;
	238	u8 rsvd[12];
	239	};
	240
	241	struct mlx5_wqe_masked_atomic_seg {
	242	__be64 swap_add;
	243	__be64 compare;
	244	__be64 swap_add_mask;
	245	__be64 compare_mask;
	246	};
	247
	248	struct mlx5_av {
	249	union {
	250	struct {
	251	__be32 qkey;
	252	__be32 reserved;
	253	} qkey;
	254	__be64 dc_key;
	255	} key;
	256	__be32 dqp_dct;
	257	u8 stat_rate_sl;
	258	u8 fl_mlid;
2811ba51 AS	259	union {
	260	__be16 rlid;
	261	__be16 udp_sport;
	262	};
	263	u8 reserved0[4];
	264	u8 rmac[6];
e126ba97 EC	265	u8 tclass;
	266	u8 hop_limit;
	267	__be32 grh_gid_fl;
	268	u8 rgid[16];
	269	};
	270
	271	struct mlx5_wqe_datagram_seg {
	272	struct mlx5_av av;
	273	};
	274
	275	struct mlx5_wqe_raddr_seg {
	276	__be64 raddr;
	277	__be32 rkey;
	278	u32 reserved;
	279	};
	280
	281	struct mlx5_wqe_atomic_seg {
	282	__be64 swap_add;
	283	__be64 compare;
	284	};
	285
	286	struct mlx5_wqe_data_seg {
	287	__be32 byte_count;
	288	__be32 lkey;
	289	__be64 addr;
	290	};
	291
	292	struct mlx5_wqe_umr_ctrl_seg {
	293	u8 flags;
	294	u8 rsvd0[3];
	295	__be16 klm_octowords;
	296	__be16 bsf_octowords;
	297	__be64 mkey_mask;
	298	u8 rsvd1[32];
	299	};
	300
	301	struct mlx5_seg_set_psv {
	302	__be32 psv_num;
	303	__be16 syndrome;
	304	__be16 status;
	305	__be32 transient_sig;
	306	__be32 ref_tag;
	307	};
	308
	309	struct mlx5_seg_get_psv {
	310	u8 rsvd[19];
	311	u8 num_psv;
	312	__be32 l_key;
	313	__be64 va;
	314	__be32 psv_index[4];
	315	};
	316
	317	struct mlx5_seg_check_psv {
	318	u8 rsvd0[2];
	319	__be16 err_coalescing_op;
	320	u8 rsvd1[2];
	321	__be16 xport_err_op;
	322	u8 rsvd2[2];
	323	__be16 xport_err_mask;
	324	u8 rsvd3[7];
	325	u8 num_psv;
	326	__be32 l_key;
	327	__be64 va;
	328	__be32 psv_index[4];
329	};
330
331	struct mlx5_rwqe_sig {
332	u8 rsvd0[4];
333	u8 signature;
334	u8 rsvd1[11];
335	};
336
337	struct mlx5_wqe_signature_seg {
338	u8 rsvd0[4];
339	u8 signature;
340	u8 rsvd1[11];
341	};
342
7bdf65d4 HE	343	#define MLX5_WQE_INLINE_SEG_BYTE_COUNT_MASK 0x3ff
7bdf65d4 HE	344
e126ba97 EC	345	struct mlx5_wqe_inline_seg {
	346	__be32 byte_count;
	347	};
	348
142537f4 SG	349	enum mlx5_sig_type {
	350	MLX5_DIF_CRC = 0x1,
	351	MLX5_DIF_IPCS = 0x2,
	352	};
	353
	354	struct mlx5_bsf_inl {
	355	__be16 vld_refresh;
	356	__be16 dif_apptag;
	357	__be32 dif_reftag;
	358	u8 sig_type;
	359	u8 rp_inv_seed;
	360	u8 rsvd[3];
	361	u8 dif_inc_ref_guard_check;
	362	__be16 dif_app_bitmask_check;
	363	};
	364
e6631814 SG	365	struct mlx5_bsf {
	366	struct mlx5_bsf_basic {
	367	u8 bsf_size_sbs;
	368	u8 check_byte_mask;
	369	union {
	370	u8 copy_byte_mask;
	371	u8 bs_selector;
	372	u8 rsvd_wflags;
	373	} wire;
	374	union {
	375	u8 bs_selector;
	376	u8 rsvd_mflags;
	377	} mem;
	378	__be32 raw_data_size;
	379	__be32 w_bfs_psv;
	380	__be32 m_bfs_psv;
	381	} basic;
	382	struct mlx5_bsf_ext {
	383	__be32 t_init_gen_pro_size;
	384	__be32 rsvd_epi_size;
	385	__be32 w_tfs_psv;
	386	__be32 m_tfs_psv;
	387	} ext;
142537f4 SG	388	struct mlx5_bsf_inl w_inl;
142537f4 SG	389	struct mlx5_bsf_inl m_inl;
e6631814 SG	390	};
	391
	392	struct mlx5_klm {
	393	__be32 bcount;
	394	__be32 key;
	395	__be64 va;
	396	};
	397
	398	struct mlx5_stride_block_entry {
	399	__be16 stride;
	400	__be16 bcount;
	401	__be32 key;
	402	__be64 va;
	403	};
	404
	405	struct mlx5_stride_block_ctrl_seg {
	406	__be32 bcount_per_cycle;
	407	__be32 op;
	408	__be32 repeat_count;
	409	u16 rsvd;
	410	__be16 num_entries;
	411	};
	412
e420f0c0 HE	413	enum mlx5_pagefault_flags {
	414	MLX5_PFAULT_REQUESTOR = 1 << 0,
	415	MLX5_PFAULT_WRITE = 1 << 1,
	416	MLX5_PFAULT_RDMA = 1 << 2,
	417	};
	418
	419	/* Contains the details of a pagefault. */
	420	struct mlx5_pagefault {
	421	u32 bytes_committed;
	422	u8 event_subtype;
	423	enum mlx5_pagefault_flags flags;
	424	union {
	425	/* Initiator or send message responder pagefault details. */
	426	struct {
	427	/* Received packet size, only valid for responders. */
	428	u32 packet_size;
	429	/*
	430	* WQE index. Refers to either the send queue or
	431	* receive queue, according to event_subtype.
	432	*/
	433	u16 wqe_index;
	434	} wqe;
	435	/* RDMA responder pagefault details */
	436	struct {
	437	u32 r_key;
	438	/*
	439	* Received packet size, minimal size page fault
	440	* resolution required for forward progress.
	441	*/
	442	u32 packet_size;
	443	u32 rdma_op_len;
	444	u64 rdma_va;
	445	} rdma;
	446	};
	447	};
	448
e126ba97	449	struct mlx5_core_qp {
5903325a	450	struct mlx5_core_rsc_common common; /* must be first */
e126ba97	451	void (event) (struct mlx5_core_qp , int);
e420f0c0	452	void (pfault_handler)(struct mlx5_core_qp , struct mlx5_pagefault *);
e126ba97	453	int qpn;
e126ba97 EC	454	struct mlx5_rsc_debug *dbg;
	455	int pid;
	456	};
	457
	458	struct mlx5_qp_path {
d3ae2bde	459	u8 fl_free_ar;
e126ba97	460	u8 rsvd3;
d3ae2bde	461	__be16 pkey_index;
e126ba97 EC	462	u8 rsvd0;
	463	u8 grh_mlid;
	464	__be16 rlid;
	465	u8 ackto_lt;
	466	u8 mgid_index;
	467	u8 static_rate;
	468	u8 hop_limit;
	469	__be32 tclass_flowlabel;
2811ba51 AS	470	union {
	471	u8 rgid[16];
	472	u8 rip[16];
	473	};
	474	u8 f_dscp_ecn_prio;
	475	u8 ecn_dscp;
	476	__be16 udp_sport;
	477	u8 dci_cfi_prio_sl;
e126ba97	478	u8 port;
2811ba51	479	u8 rmac[6];
e126ba97 EC	480	};
	481
	482	struct mlx5_qp_context {
	483	__be32 flags;
	484	__be32 flags_pd;
	485	u8 mtu_msgmax;
	486	u8 rq_size_stride;
	487	__be16 sq_crq_size;
	488	__be32 qp_counter_set_usr_page;
	489	__be32 wire_qpn;
	490	__be32 log_pg_sz_remote_qpn;
	491	struct mlx5_qp_path pri_path;
	492	struct mlx5_qp_path alt_path;
	493	__be32 params1;
	494	u8 reserved2[4];
	495	__be32 next_send_psn;
	496	__be32 cqn_send;
b11a4f9c HE	497	__be32 deth_sqpn;
b11a4f9c HE	498	u8 reserved3[4];
e126ba97 EC	499	__be32 last_acked_psn;
	500	__be32 ssn;
	501	__be32 params2;
	502	__be32 rnr_nextrecvpsn;
	503	__be32 xrcd;
	504	__be32 cqn_recv;
	505	__be64 db_rec_addr;
	506	__be32 qkey;
	507	__be32 rq_type_srqn;
	508	__be32 rmsn;
	509	__be16 hw_sq_wqe_counter;
	510	__be16 sw_sq_wqe_counter;
	511	__be16 hw_rcyclic_byte_counter;
	512	__be16 hw_rq_counter;
	513	__be16 sw_rcyclic_byte_counter;
	514	__be16 sw_rq_counter;
	515	u8 rsvd0[5];
	516	u8 cgs;
	517	u8 cs_req;
	518	u8 cs_res;
	519	__be64 dc_access_key;
	520	u8 rsvd1[24];
	521	};
	522
e126ba97 EC	523	struct mlx5_modify_qp_mbox_in {
	524	struct mlx5_inbox_hdr hdr;
	525	__be32 qpn;
e126ba97	526	u8 rsvd0[4];
e3353c26 AK	527	__be32 optparam;
e3353c26 AK	528	u8 rsvd1[4];
e126ba97	529	struct mlx5_qp_context ctx;
418f8399	530	u8 rsvd2[16];
e126ba97 EC	531	};
	532
	533	struct mlx5_modify_qp_mbox_out {
	534	struct mlx5_outbox_hdr hdr;
	535	u8 rsvd0[8];
	536	};
	537
e126ba97 EC	538	static inline struct mlx5_core_qp __mlx5_qp_lookup(struct mlx5_core_dev dev, u32 qpn)
	539	{
	540	return radix_tree_lookup(&dev->priv.qp_table.tree, qpn);
	541	}
	542
a606b0f6	543	static inline struct mlx5_core_mkey __mlx5_mr_lookup(struct mlx5_core_dev dev, u32 key)
d5436ba0	544	{
a606b0f6	545	return radix_tree_lookup(&dev->priv.mkey_table.tree, key);
d5436ba0 SG	546	}
d5436ba0 SG	547
e126ba97 EC	548	int mlx5_core_create_qp(struct mlx5_core_dev *dev,
e126ba97 EC	549	struct mlx5_core_qp *qp,
09a7d9ec	550	u32 *in,
e126ba97	551	int inlen);
427c1e7b	552	int mlx5_core_qp_modify(struct mlx5_core_dev *dev, u16 operation,
e126ba97 EC	553	struct mlx5_modify_qp_mbox_in *in, int sqd_event,
	554	struct mlx5_core_qp *qp);
	555	int mlx5_core_destroy_qp(struct mlx5_core_dev *dev,
	556	struct mlx5_core_qp *qp);
	557	int mlx5_core_qp_query(struct mlx5_core_dev dev, struct mlx5_core_qp qp,
09a7d9ec	558	u32 *out, int outlen);
e126ba97 EC	559
	560	int mlx5_core_xrcd_alloc(struct mlx5_core_dev dev, u32 xrcdn);
	561	int mlx5_core_xrcd_dealloc(struct mlx5_core_dev *dev, u32 xrcdn);
	562	void mlx5_init_qp_table(struct mlx5_core_dev *dev);
	563	void mlx5_cleanup_qp_table(struct mlx5_core_dev *dev);
	564	int mlx5_debug_qp_add(struct mlx5_core_dev dev, struct mlx5_core_qp qp);
	565	void mlx5_debug_qp_remove(struct mlx5_core_dev dev, struct mlx5_core_qp qp);
e420f0c0 HE	566	#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
	567	int mlx5_core_page_fault_resume(struct mlx5_core_dev *dev, u32 qpn,
	568	u8 context, int error);
	569	#endif
e2013b21	570	int mlx5_core_create_rq_tracked(struct mlx5_core_dev dev, u32 in, int inlen,
	571	struct mlx5_core_qp *rq);
	572	void mlx5_core_destroy_rq_tracked(struct mlx5_core_dev *dev,
	573	struct mlx5_core_qp *rq);
	574	int mlx5_core_create_sq_tracked(struct mlx5_core_dev dev, u32 in, int inlen,
	575	struct mlx5_core_qp *sq);
	576	void mlx5_core_destroy_sq_tracked(struct mlx5_core_dev *dev,
	577	struct mlx5_core_qp *sq);
237cd218 TT	578	int mlx5_core_alloc_q_counter(struct mlx5_core_dev dev, u16 counter_id);
	579	int mlx5_core_dealloc_q_counter(struct mlx5_core_dev *dev, u16 counter_id);
	580	int mlx5_core_query_q_counter(struct mlx5_core_dev *dev, u16 counter_id,
	581	int reset, void *out, int out_size);
	582	int mlx5_core_query_out_of_buffer(struct mlx5_core_dev *dev, u16 counter_id,
	583	u32 *out_of_buffer);
e126ba97	584
db81a5c3 EC	585	static inline const char *mlx5_qp_type_str(int type)
	586	{
	587	switch (type) {
	588	case MLX5_QP_ST_RC: return "RC";
	589	case MLX5_QP_ST_UC: return "C";
	590	case MLX5_QP_ST_UD: return "UD";
	591	case MLX5_QP_ST_XRC: return "XRC";
	592	case MLX5_QP_ST_MLX: return "MLX";
	593	case MLX5_QP_ST_QP0: return "QP0";
	594	case MLX5_QP_ST_QP1: return "QP1";
	595	case MLX5_QP_ST_RAW_ETHERTYPE: return "RAW_ETHERTYPE";
	596	case MLX5_QP_ST_RAW_IPV6: return "RAW_IPV6";
	597	case MLX5_QP_ST_SNIFFER: return "SNIFFER";
	598	case MLX5_QP_ST_SYNC_UMR: return "SYNC_UMR";
	599	case MLX5_QP_ST_PTP_1588: return "PTP_1588";
	600	case MLX5_QP_ST_REG_UMR: return "REG_UMR";
	601	default: return "Invalid transport type";
	602	}
	603	}
	604
	605	static inline const char *mlx5_qp_state_str(int state)
	606	{
	607	switch (state) {
	608	case MLX5_QP_STATE_RST:
	609	return "RST";
	610	case MLX5_QP_STATE_INIT:
	611	return "INIT";
	612	case MLX5_QP_STATE_RTR:
	613	return "RTR";
	614	case MLX5_QP_STATE_RTS:
	615	return "RTS";
	616	case MLX5_QP_STATE_SQER:
	617	return "SQER";
	618	case MLX5_QP_STATE_SQD:
	619	return "SQD";
	620	case MLX5_QP_STATE_ERR:
	621	return "ERR";
	622	case MLX5_QP_STATE_SQ_DRAINING:
	623	return "SQ_DRAINING";
	624	case MLX5_QP_STATE_SUSPENDED:
	625	return "SUSPENDED";
	626	default: return "Invalid QP state";
	627	}
	628	}
	629
e126ba97	630	#endif /* MLX5_QP_H */